MTV512.pdf

Benq Q7T4 FP71G+ nie świeci dioda

Jak kołó MTV512 masz małą pamięc typu 24c0x to wina w niej (wsad) Ważny jest opis na płytce Benq FP71G+ Q7T4 P/N:9J.L1C72.KSE masz datasheet od MTV512 ale obudowa 44pin FPGA Zazwyczaj była wer. na 4-lampy http://obrazki.elektroda.pl/7821919200_1291316553_thumb.jpg


MTV512M
Preliminary

8051 Embedded Monitor Controller 64K Flash Type
The MTV512M micro-controller is an 8051 CPU core
embedded device especially tailored for flat panel
display applications. It includes an 8051 CPU core,
768-byte SRAM, 4 channels of 6-bit ADC, 3 external
counters/timers, 6 channels of PWM DAC, VESA
DDC interface, and a 64K-byte internal program
Flash-ROM memory in 44-pin PLCC package.

o
o
o
o

FEATURES
o 8051 core, 12MHz operating frequency with
single/double CPU clock option
o 0.35um process; 3.3V power supply

P3.4

8051
CORE

RD
WR
ALE
INT1

P7.6-7
P6.0-7
P5.0-6

P2.0-7

RD
WR
ALE
INT1

XFR

AUXRAM &
DDCRAM1 &
DDCRAM2

ADC

& 2

RST
X1
X2
CKO

P0.0-7

1)
,

P3.0-2

P2.0-3

AD0-3

PWM DAC
DA0-5

AUX
I/O

om
.c
4u
et
he
as
at
.d
w
w
w

DDC & IIC HSCL1
INTERFACE HSDA1
HSCL2
HSDA2

*This datasheet, which contains proprietary and trade secret information of MYSON CENTURY, INC., is
confidential and subject to various privileges against unauthorized disclosure.

Myson Century, Inc.
No. 2, Industry East Rd. III,
Science-Based Industrial Park, Hsin-Chu, Taiwan
Tel: 886-3-5784866 Fax: 886-3-5784349

sales@myson.com.tw
www.myson.com.tw
Rev. 0.4 August 25, 2003
page 1 of 1

www.DataSheet4U.com

P0.0-7

P1.0-7

'
(1

BLOCK DIAGRAM

o
o
o

768-byte RAM; 64K-byte program Flash memory
Maximum 6 channels of PWM DAC
Compliant with VESA DDC1/2B/2Bi/2B+ standard
Dual slave IIC addresses; two H/W auto transfer
DDC1/DDC2x data for both D-sub and DVI
interfaces
Watchdog timer with programmable interval
Support external counters/timers, 1 & 2
Single/double frequency clock output
Two external interrupts, INT1 is shared with Slave
IIC interrupt source.
Maximum 4 channels of 6-bit ADC
Flash-ROM code protection selection
44-pin PLCC package

7,
$/

o
o
o
o

GENERAL DESCRIPTIONS

MTV512M
Preliminary

& 2

1)
,

'
(1

7,
$/

PIN CONNECTION

page 2 of 2

MTV512M
Preliminary
PIN CONFIGURATION & DESCRIPTION
A "CMOS output pin" means it can sink and drive at least 4mA current. It is not recommended to use such pin
as input function.
An "open drain pin" means it can sink at least 4mA current. It can be used as input or output function and needs
an external pull up resistor.
An "8051 standard pin" is a pseudo open drain pin. It can sink at least 4mA current when output is at low level,
and drives at least 4mA current for 160nS when output transits from low to high, then keeps driving at 120?A to
maintain the pin at high level. It can be used as input or output function. It needs an external pull up resistor
when driving heavy load device.
There is an internal pull-up resistance on each CMOS PAD and an internal pull-down resistance on each input
PAD. It is recommended to add a pull high resistance on each open drain pin.

Pin No.

Direction

Default
Direction

Default
Output
Value

Internal
Pull
Up/Down

Pin Type

NC

1

-

-

-

-

-

DA0/P5.0

2

I/O

O

1(DA0)

7,
$/

Name

-

Description

No connection

Open Drain PWM DAC output/General
purpose I/O (open drain)

DA2/P5.2

DA3/P5.3

4

5

6

I/O

I/O

I/O

I/O

O

1(DA1)

-

O

O

O

1(DA2)

1(DA3)

1(DA4)

-

-

-

1)
,

DA4/ P5.4

3

'
(1

DA1/P5.1

-

P5.7/HSDA2

9

I/O

I

Z(P5.7)

-

RST

10

I

I

0

down

HSCL1/P3.0/RXD

11

I/O

I/O

Z(HSCL1)

-

NC

12

-

-

HSDA1/P3.1/TXD0

13

I/O

I/O

P5.5/DA5

8

I/O

I/O

& 2

P5.6/HSCL2

7

O

Open Drain PWM DAC output/General
purpose I/O (open drain)

Open Drain PWM DAC output/General
purpose I/O (open drain)

Open Drain PWM DAC output/General
purpose I/O (open drain)

Open Drain PWM DAC output/General
purpose I/O (open drain)

1(P5.5)

-

Open Drain PWM DAC output/General
purpose I/O (open drain)

I

Z(P5.6)

Open Drain General purpose I/O/Slave
IIC1 SCL2 (open drain)
w/ filter
Open Drain General purpose I/O/Slave
IIC1 SDA2 (open drain)
w/ filter

-

Z(HSDA1)

-

Input

High Active RESET

Open Drain Slave IIC clock/General
purpose I/O/Rxd (open drain)
w/ filter
-

No connection

Open Drain Slave IIC data/General
purpose I/O/Txd (open drain)
w/ filter

page 3 of 3

MTV512M
Preliminary

I

Default
Output
Value
Z(P3.2)

Internal
Pull
Up/Down
-

I/O

I

Z(P3.3)

16

I/O

I

P3.5/T1

17

I/O

P7.6/CLKO2

18

P7.7

Name

Pin No.

Direction

Default
Direction

P3.2/INT0

14

I/O

P3.3/INT1

15

P3.4/T0

Description

Standard
8051

General purpose I/O/External
interrupt 0 (Standard 8051)

-

Standard
8051

General purpose I/O/External
interrupt 1 (Standard 8051)

Z(P3.4)

-

Standard
8051

General purpose I/O/T0 Ext.
Counter/Timer 0 (Standard
8051)

I

Z(P3.5)

-

Standard
8051

General purpose I/O/T1 Ext.
Counter/Timer 1 (Standard
8051)

I/O

I

1(P7.6)

up

CMOS

General purpose I/O /Clock
out 2 (CMOS)

19

I/O

I

1

X2

20

O

-

-

X1

21

I

-

-

VSS

22

-

NC

23

-

P6.0/AD0

24

I/O

P6.1/AD1

25

I/O

I

P6.2/AD2

26

I/O

7,
$/

Pin Type

-

-

Crystal Out

-

-

Crystal In

'
(1

CMOS

-

-

-

-

Ground

-

-

-

-

No connection

I

1(P6.0)

up

CMOS

General purpose I/O (CMOS)
/6-bit ADC channel 0 input

1(P6.1)

up

CMOS

General purpose I/O (CMOS)
/6-bit ADC channel 1 input

I

1(P6.2)

up

CMOS

General purpose I/O (CMOS)
/6-bit ADC channel 2 input

1)
,

& 2

General purpose I/O (CMOS)

up

P6.3/AD3

27

I/O

I

1(P6.3)

up

CMOS

General purpose I/O (CMOS)
/6-bit ADC channel 3 input

P6.4

28

I/O

I

1

up

CMOS

General purpose I/O (CMOS)

P6.5

29

I/O

I

1

up

CMOS

General purpose I/O (CMOS)

P6.6/CLKO1

30

I/O

I

1(P6.6)

up

CMOS

General purpose I/O/CLKO1
(CMOS)

P6.7

31

I/O

I

1

up

CMOS

General purpose I/O (CMOS)

page 4 of 4

MTV512M
Preliminary

I

Default
Output
Value
0

Internal
Pull
Up/Down
down

-

-

-

-

-

No connection

34

-

-

-

-

-

No connection

NC

35

-

-

-

-

-

No connection

P1.7

36

I/O

I

Z

-

P1.6

37

I/O

I

Z

P1.5

38

I/O

I

Z

P1.4

39

I/O

I

Z

P1.3

40

I/O

P1.2

41

I/O

P1.1

42

I/O

P1.0/ET2

43

I/O

VCC

44

-

Standard
8051 or
CMOS
Standard
8051 or
CMOS
Standard
8051 or
CMOS
Standard
8051 or
CMOS
Standard
8051 or
CMOS
Standard
8051 or
CMOS
Standard
8051 or
CMOS
Standard
8051 or
CMOS
-

Direction

Default
Direction

VSYNC

32

I

NC

33

NC

-

-

-

I

Z

-

I

Z

-

I

Z

-

I

Z(P1.0)

-

-

-

-

Input

Description
VSYNC input

General purpose I/O
(Standard 8051/CMOS)
General purpose I/O
(Standard 8051/CMOS)
General purpose I/O
(Standard 8051/CMOS)
General purpose I/O
(Standard 8051/CMOS)
General purpose I/O
(Standard 8051/CMOS)
General purpose I/O
(Standard 8051/CMOS)
General purpose I/O
(Standard 8051/CMOS)
General purpose I/O/External
Counter/Timer2 (Standard
8051/CMOS)
3.3V power

& 2

1)
,

Pin Type

7,
$/

Pin No.

'
(1

Name

page 5 of 5

MTV512M
Preliminary
Pin Types

4mA

10uA

2 OSC
period
delay

120uA

Pin

8051 Standard Pin

4mA
Output
Data

Input
Data

Pin

7,
$/

Pin
Input
Data

Input
Data

10?A

4mA
Output
Data

Inputs

'
(1

Open Drain Pin

4mA

Pin

LPF
Input
Data

Pin
4mA

Output
Data

4mA

1)
,

Output
Data

Input
Data

CMOS

& 2

Open Drain with Filter Pin

10?A

page 6 of 6

MTV512M
Preliminary
FUNCTIONAL DESCRIPTIONS
8051 CPU Core
The CPU core of MTV512M is compatible with the industry standard 8051, which includes 256 bytes RAM,
Special Function Registers (SFR), two timers, five interrupt sources and a serial UART interface. The CPU core
fetches its program code from the 64K bytes Flash memory in MTV512M. It uses Port0 and Port2 to access the
"external special function register" (XFR) and external auxiliary RAM (AUXRAM).
The CPU core can run at double rate when FclkE is set. When the operating X'tal is 12MHz, Once the bit is set,
the CPU runs as if a 24MHz X'tal is applied on MTV512M, but the peripherals (IIC, DDC, Etimer, ADC, DAC)
still run at the original frequency.
Note: All registers listed in this document reside in 8051's external RAM area (XFR). For internal RAM
memory map, please refer to 8051 spec.

7,
$/

Memory Allocation
i) Internal Special Function Registers (SFR)

The SFR is a group of registers that are the same as standard 8051.
ii) Internal RAM

'
(1

There are total 256 bytes internal RAM in MTV512M, the same as standard 8052.
iii) External Special Function Registers (XFR)

The XFR is a group of registers allocated in the 8051 external RAM area F00h - FFFh. These registers are
used for special functions. Programs can use " MOVX " instruction to access these registers.
iv) Auxiliary RAM (AUXRAM)

1)
,

There are total 256 bytes auxiliary RAM allocated in the 8051 external RAM area 800h - 8FFh. Programs can
use " MOVX " instruction to access the AUXRAM.
v) Dual Port RAM (DDCRAM)

FFh

& 2

There are 256 bytes Dual Port RAM allocated in the 8051 external RAM area E00h - EFFh. Programs can use
" MOVX " instruction to access the RAM. The external DDC1/2 Host can access the RAM as if a 24LC0x
EEPROM is connected onto the interface. Address from E00h to E7Fh is for external DDC host1 to access the
DDC data. Address from E80h to EFFh is for external DDC host2.

Internal RAM
Accessible by
indirect
addressing only
(Using
MOV A,@Ri
instruction)

80h
7Fh

FFFh

Accessible by
direct addressing

XFR
Accessible by
indirect external
RAM addressing
(Using MOVX
instruction)

EFFh

E80h
E7Fh

F00h

Internal RAM
Accessible by
direct and indirect
addressing

00h

SFR

8FFh
E00h
8FFh

DDCRAM2
Accessible by
indirect external
RAM addressing
(Using MOVX
Instruction)

DDCRAM1
Accessible by
indirect external
RAM addressing
(Using MOVX
Instruction)

AUXRAM
Accessible by
indirect external
RAM addressing
(Using MOVX
Instruction)

800h

page 7 of 7

MTV512M
Preliminary

Chip Configuration
The Chip Configuration registers define configuration of the chip and function of the pins.
Reg name

addr

bit7

bit6

PADMOD

F50h(w)

PADMOD

F51h(w)

PADMOD

F52h(w)

HIIC1E

PADMOD

F53h(w)

P57oe

P56oe

PADMOD

F54h(w)

P67oe

PADMOD

F55h(w)

OPTION

F56h(w)

PADMOD

F5Eh(w)

PADMOD

F5Fh(w)

bit5

bit4

bit3

bit2

bit1

bit0

AD3E

AD2E

AD1E

AD0E

P53E

P52E

P51E

P50E

P54E

HIIC2E

CKOE1

P55oe

P54oe

P53oe

P52oe

P51oe

P50oe

P66oe

P65oe

P64oe

P63oe

P62oe

P61oe

P60oe

COP17

COP16

COP15

COP14

COP13

COP12

COP11

COP10

PWMF

DIV253

FclkE

DCLK

ENSCL

CKOE2
P77oe

P76oe

7,
$/

P55E

IP77E

PADMOD (w) : Pad mode control registers. (All are " 0 " in Chip Reset, except for HIIC1E bit)
-> Pin "P6.3/AD3" is AD3.

=0

-> Pin "P6.3/AD3" is P6.3.

=1

-> Pin "P6.2/AD2" is AD2.

=0

-> Pin "P6.2/AD2" is P6.2.

=1

-> Pin "P6.1/AD1" is AD1.

=0

-> Pin "P6.1/AD1" is P6.1.

AD0E

=1

-> Pin "P6.0/AD0" is AD0.

=0

-> Pin "P6.0/AD0" is P6.0.

P55E

=1

-> Pin "DA5/P5.5" is P5.5.

AD1E

=0
P54E

=1
=0

P53E

=1

-> Pin "DA5/P5.5" is DA5.

-> Pin "DA4/P5.4" is P5.4.
-> Pin "DA4/P5.4" is DA4.

-> Pin "DA3/P5.3" is P5.3.
-> Pin "DA3/P5.3" is DA3.

& 2

=0

1)
,

AD2E

'
(1

=1

AD3E

-> Pin "DA2/P5.2" is DA2.

=1

-> Pin "DA1/P5.1" is P5.1.
-> Pin "DA1/P5.1" is DA1.

=1

-> Pin "DA0/P5.0" is P5.0.

=0

P50E

-> Pin "DA2/P5.2" is P5.2.

=0

P51E

=1
=0

P52E

-> Pin "DA0/P5.0" is DA0.
-> Pin "HSCL1/P3.0/Rxd" is HSCL1;

pin "HSDA1/P3.1/Txd" is HSDA1.

-> Pin "HSCL1/P3.0/Rxd" is P3.0/Rxd;

pin "HSDA1/P3.1/Txd" is P3.1/Txd.

-> Pin "HSCL2/P5.6" is HSCL2.

Pin "HSDA2/P5.7" is HSDA2.

=0

-> Pin "HSCL2/P5.6" is P5.6.

Pin "HSDA2/P5.7" is P5.7.

CKOE1 = 1

-> Pin "P6.6/CLKO1" is P6.6.

HIIC1E = 1
=0
HIIC2E = 1

=0

-> Pin "P6.6/CLKO1" is CLKO1.

page 8 of 8

MTV512M
Preliminary

=0
P55oe = 1
=0
P54oe = 1
=0
P53oe = 1
=0
P52oe = 1
=0
P51oe = 1
=0
P50oe = 1
=0
P67oe = 1
=0
P66oe = 1
=0
P65oe = 1
=0
P64oe = 1
=0
P63oe = 1
=0
P62oe = 1
=0
P61oe = 1
=0

-> P5.6 is input pin.
-> P5.5 is output pin.
-> P5.5 is input pin.
-> P5.4 is output pin.
-> P5.4 is input pin.
-> P5.3 is output pin.
-> P5.3 is input pin.
-> P5.2 is output pin.
-> P5.2 is input pin.
-> P5.1 is output pin.
-> P5.1 is input pin.
-> P5.0 is output pin.
-> P5.0 is input pin.
-> P6.7 is output pin.
-> P6.7 is input pin.
-> P6.6 is output pin.
-> P6.6 is input pin.

-> P6.5 is output pin.
-> P6.5 is input pin.

-> P6.4 is output pin.
-> P6.4 is input pin.

-> P6.3 is output pin.
-> P6.3 is input pin.

-> P6.2 is output pin.
-> P6.2 is input pin.

-> P6.1 is output pin.
-> P6.1 is input pin.

-> P6.0 is output pin.

& 2

P60oe = 1

-> P5.6 is output pin.

7,
$/

P56oe = 1

-> P5.7 is input pin.

'
(1

=0

-> P5.7 is output pin.

1)
,

P57oe = 1

=0

COP17 = 1
=0

COP16 = 1
=0

COP15 = 1
=0
COP14 = 1
=0
COP13 = 1
=0
COP12 = 1

-> P6.0 is input pin.
-> Pin "P1.7" is CMOS Output.
-> Pin "P1.7" is 8051 standard I/O.
-> Pin "P1.6" is CMOS Output.
-> Pin "P1.6" is 8051 standard I/O.
-> Pin "P1.5" is CMOS Output.
-> Pin "P1.5" is 8051 standard I/O.
-> Pin "P1.4" is CMOS Output.
-> Pin "P1.4" is 8051 standard I/O.
-> Pin "P1.3" is CMOS Output.
-> Pin "P1.3" is 8051 standard I/O.
-> Pin "P1.2" is CMOS Output.

page 9 of 9

MTV512M
Preliminary

COP11 = 1
=0
COP10 = 1
=0
P77oe = 1
=0
P76oe = 1
=0
IP77E = 1
=0
CKOE2 = 1
=0
OPTION (w) :

-> Pin "P1.2" is 8051 standard I/O.
-> Pin "P1.1" is CMOS Output.
-> Pin "P1.1" is 8051 standard I/O.
-> Pin "P1.0" is CMOS Output.
-> Pin "P1.0" is 8051 standard I/O.
-> P7.7 is output pin.
-> P7.7 is input pin.
-> P7.6 is output pin.
-> P7.6 is input pin.
-> Pin "P7.7 is P7.7. Available in ICE Mode only.
-> reserved.
-> Pin "P7.6/CLKO2" is CLKO2.
-> Pin "P7.6/CLKO2" is P7.6.

7,
$/

=0

Chip option configuration (All are " 0 " in Chip Reset).

PWMF = 1

-> Selects 94KHz PWM frequency.

=0

-> Selects 47KHz PWM frequency.

-> PWM pulse width is 253-step resolution.

=0

-> PWM pulse width is 256-step resolution.

=1

-> CPU is running at double rate

=0

-> CPU is running at normal rate

FclkE

DCLK = 1
=0

I/O Ports
i)

Port1

-> CLKO1 & CLKO2 outputs double frequency system clock.
-> CLKO1 & CLKO2 outputs single frequency system clock.
-> Enable slave IIC block to hold HSCL pin low while MTV512M is unable to
catch-up with the external master's speed.

1)
,

ENSCL = 1

'
(1

DIV253 = 1

& 2

Port1 is a group of pseudo open drain pins or CMOS output pins. It can be used as general purpose I/O.
Behavior of Port1 is the same as standard 8051.
ii) P3.0-2, P3.4

If these pins are not set as IIC pins, Port3 can be used as general purpose I/O, interrupt, UART and Timer pins.
Behavior of Port3 is the same as standard 8051.
iii) Port5, Port6 and Port7
Port5, Port6 and Port7 are used as general purpose I/O. S/W needs to set the corresponding P5(n)oe and
P6(n)oe to define whether these pins are input or output.
Reg name

addr

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

PORT5

F30h(r/w)

P50

PORT5

F31h(r/w)

P51

PORT5

F32h(r/w)

P52

PORT5

F33h(r/w)

P53
page 10 of 10

MTV512M
Preliminary
F34h(r/w)

P54

PORT5

F35h(r/w)

P55

PORT5

F36h(r/w)

P56

PORT5

F37h(r/w)

P57

PORT6

F38h(r/w)

P60

PORT6

F39h(r/w)

P61

PORT6

F3Ah(r/w)

P62

PORT6

F3Bh(r/w)

P63

PORT6

F3Ch(r/w)

P64

PORT6

F3Dh(r/w)

P65

PORT6

F3Eh(r/w)

P66

PORT6

F3Fh(r/w)

P67

PORT7

F76h(r/w)

PORT7

F77h(r/w)

Port 5 data input/output value.

PORT6 (r/w) :

Port 6 data input/output value.

P76
P77

'
(1

PORT5 (r/w) :

7,
$/

PORT5

PWM DAC

1)
,

Each output pulse width of PWM DAC converter is controlled by an 8-bit register in XFR. The frequency of
PWM clock is 47KHz or 94KHz, selected by PWMF. And the total duty cycle step of these DAC outputs is 253
or 256, selected by DIV253. If DIV253=1, writing FDH/FEH/FFH to DAC register generates stable high output.
If DIV253=0, the output pulses low at least once even if the DAC register's content is FFH. Writing 00H to DAC
register generates stable low output.
addr

bit7

DA0

F20h(r/w)

Pulse width of PWM DAC 0

DA1

F21h(r/w)

Pulse width of PWM DAC 1

DA2

F22h(r/w)

Pulse width of PWM DAC 2

DA3

F23h(r/w)

Pulse width of PWM DAC 3

& 2

Reg name

bit6

bit5

bit4

bit3

DA4

F24h(r/w)
F25h(r/w)

bit1

bit0

Pulse width of PWM DAC 4

DA5

bit2

Pulse width of PWM DAC 5

DA0-5 (r/w) :
The output pulse width control for DA0-5.
* All of PWM DAC converters are centered with value 80h after power on.

DDC & IIC Interface
i) DDC1/DDC2x Mode, DDCRAM1/DDCRAM2 and SlaveA1/SlaveA2 Block
The MTV512M supports VESA DDC for both D-sub and DVI interfaces through HSCL1/HSDA1 and
HSCL2/HSDA2 pins. The HSCL1/HSDA1 pins access DDCRAM1 by SlaveA1, and the HSCL2/HSDA2 pins
access DDCRAM2 by SlaveA2. The MTV512M enters DDC1 mode for both DDC channels after Reset. In this
mode, VSYNC is used as data clock. The HSCL1/HSCL2 pin should remain at high. The data output to the
HSDA1/HSDA2 pin is taken from a shift register in MTV512M. The shift register automatically fetches EDID
page 11 of 11

MTV512M
Preliminary
data from the lower 128 bytes of the Dual Port RAM (DDCRAM1/DDCRAM2), then sends it in 9-bit packet
formats inclusive of a null bit (=1) as packet separator. S/W may enable/disable the DDC1 function by
setting/clearing the DDC1en control bit.
The MTV512M switches to DDC2x mode when it detects a high to low transition on the HSCL1/HSCL2 pin. In
this mode, the SlaveA1/SlaveA2 IIC block automatically transmits/receives data to/from the IIC Master. The
transmitted/received data is taken-from/saved-to the DDCRAM1/DDCRAM2. In simple words, MTV512M can
behave as two 24LC0x EEPROMs. The only thing S/W needs to do is to write the EDID data to
DDCRAM1/DDCRAM2. These slave addresses of SlaveA1/SlaveA2 block can be chosen by S/W as 5-bit, 6-bit
or 7-bit. For example, if S/W chooses 5-bit slave address as 10100b, the SlaveA1 IIC block then responds to
slave address 10100xxb. The SlaveA1/SlaveA2 can be enabled/disabled by setting/clearing the
EnslvA1/EnslvA2 bit. The DDCRAM1/DDCRAM2 can/cannot be written by the IIC Master by setting/clearing the
EN128w bit.

7,
$/

The MTV512M returns to DDC1 mode if HSCL1 is kept high for 128 VSYNC clock period. However, it locks in
DDC2B mode if a valid IIC address (1010xxxb) has been detected on HSCL1/HSDA1 buses. The DDC2 flag
reflects the current DDC status, S/W may clear it by writing a " 0 " to it.

ii) SlaveB Block

The SlaveB IIC block is connected to HSDA1 and HSCL1 pins only. This block can receive/transmit data using
IIC protocols. S/W may write the SLVBADR register to determine the slave addresses.

'
(1

In receive mode, the block first detects IIC slave address matching the condition then issues a SlvBMI interrupt.
The data from HSDA1 is shifted into shift register then written to RCBBUF register when a data byte is received.
The first byte loaded is word address (slave address is dropped). This block also generates a RCBI (receives
buffer full interrupt) every time when the RCBBUF is loaded. If S/W is not able to read out the RCBBUF in time,
the next byte in shift register is not written to RCBBUF and the slave block returns NACK to the master. This
feature guarantees the data integrity of communication. The WadrB flag can tell S/W whether the data in
RCBBUF is a word address or not.

1)
,

In transmit mode, the block first detects IIC slave address matching the condition, then issues a SlvBMI interrupt.
In the meantime, the data pre-stored in the TXBBUF is loaded into shift register, resulting in TXBBUF emptying
and generates a TXBI (transmit buffer empty interrupt). S/W should write the TXBBUF a new byte for the next
transfer before shift register empties. A failure of this process causes data corruption. The TXBI occurs every
time when shift register reads out the data from TXBBUF.

& 2

The SlvBMI is cleared by writing " 0 " to corresponding bit in INTFLG register. The RCBI is cleared by reading out
RCBBUF. The TXBI is cleared by writing TXBBUF.

page 12 of 12

MTV512M
Preliminary
HSCL

Slave IIC Receive Timing
HSDA

0: The SLVAADR=40h before the transfer

5

1: H/W returns an ACK and triggers SlvAM
as slave address match.
2: The SlvAMI is reset by S/W writing 0 to

1

SlvAMI
/WR_INTFLG

3: RCAIarises when a new byte loaded int
the RCABUF, H/W returns an ACK in th
meantime.

2

RCABUF

XX

63

F0

3

RCAI

3

/RD_RCABUF

5: H/W returns a NACK because S/W has
not read out the RCABUF in time, the
RCABUF keeps its old value.
6: H/W can hold SCL low at byte section
if S/W sets ENSCL bit.

3

4

SCLOUT

4: When S/W reads RCABUF, the RCAI is
reset and SCL hold condition is released

C0

4

6

6

6

WadrA
SLVS
SlvRWB

HSCL

Slave IIC Transmit Timing

HSDA

0: The SLVAADR=40h and TXABUF=F0h
before the transfer.
1: H/W returns an ACK and triggers
SlvAMI as slave address match.

1

SlvAMI
/WR_INTFLG

2

TXABUF

3

TXAI

C0

63

F0

3

3

/WR_TXABUF

4

4

SCLOUT

6

6

2: The SlvAMI is reset by S/W writing 0
to it.
3: TXAI arises when the shift register is
loaded from the TXABUF; result in
TXABUF empty.
4: When S/W writes TXABUF, the TXAI
is reset and SCL hold condition is
released.
5: H/W sends the old data because S/W
has not updated TXABUF in time.
6: H/W can hold SCL low at byte section
if S/W sets ENSCL bit.

'
(1

SAckin

6

7,
$/

5

SLVS
SlvRWB

Figure 1. Slave IIC Timing Diagram (Transmit and Receive)

SCL

1)
,

Slave Transmission Timing in Writing Mode

1

DATA IN

& 2

DATA OUT

9

8

tR
tACKST

tR
tACKSP

Figure 2. Slave Ack Timing in Write Mode

page 13 of 13

MTV512M
Preliminary

SCL

1

9

8

DATA OUT

tR
THD;DAT

Figure 3. Slave Data Transmission Timing in Read Mode

Time interval from SCL falling** edge
(under VIL) to data starting to update
(10% or 90% swing)
Time interval from SCL falling edge
(under VIL) to slave starting to update
(10% swing)
Time interval from SCL falling edge
(under VIL) to slave starting to update
(10% swing)
SDA rise time by slave IIC (10% to
90% swing)
SDA fall time by slave IIC (90% to 90%
swing)

time

Symbol
tHD;DAT

min
2 x sysclk
*

max
3 x sysclk

2 x sysclk

3 x sysclk

2 x sysclk

3 x sysclk

7,
$/

Parameter

tACKST

'
(1

tACKSP
tR

123.9ns

127.1nsns

tF

0.85ns

2.79ns

*sysclk is the clock input on X1. It is 83ns for 12MHz crystal.
**SCL falling means when SCL drop below VIL of IIC PAD, which is 1.0 volt in typical case.

1)
,

Acceptable IIC start/stop Timing

& 2

SCL

DATA OUT

TSU;STO

TBUF

THD;STA

Figure 4. Acceptable IIC Start/Stop Timing
Parameter
Time interval from SCL
rising edge (over VIH) to
SDA rising edge (10% swing)
Time interval from SDA
rising edge to SCL falling
edge (90% swing)
Bus free time between stop
and start (from 90% to 90%

Symbol
tSU;STO

Min
600ns

Max
-

tHD;STA

600ns

-

tBUF

1300ns

-

page 14 of 14

MTV512M
Preliminary
swing)

Reg name

addr

bit7

bit6

IICCTR

F00h
(r/w)

DDC2A1

DDC2A2

IICSTUS

F01h (r)

WadrB

INTFLG

F03h (r)

TXBI

INTFLG

F03h
(w)

INTEN

F04h
(w)

ETXBI

DDCCTRA1

F06h
(w)

DDC1en

SLVA1ADR

F07h
(w)

ENSlvA1

RCBBUF

F08h (r)

Slave B IIC receive buffer

TXBBUF

F08h
(w)

Slave B IIC transmit buffer

SLVBADR

F09h
(w)

CTRSLVB

F0Ah (r)

CTRSLVB

F0Ah
(w)

DDCCTRA2

F86h
(w)

DDC1en

SLVA2ADR

F87h
(w)

ENSlvA2

bit3

SlvRWB

SAckIn

SLVS

SlvBMI

STOPI

SlvBMI
ERCBI
En128W

RCBI

bit2

bit1

ReStaI

WslvA1I

WslvA2I

STOPI

ReStaI

WslvA1I

WslvA2I

ESlvBMI

ESTOPI

EReStaI

EWSlvA1I

EWSlvA2I

Rev0

Rev1

SlvA1bs1

bit0

SlvA1bs0

7,
$/

Slave A1 IIC address

SlvBa1

SlvBa0

SlvBbs1

SlvBbs0

Rev1

SlvA2bs1

SlvA2bs0

Slave B IIC address

'
(1

ENSlvB

En128W

Rev0

Slave A2 IIC address

IIC interface status/control register.

DDC2A1 = 1
=0
DDC2A2 = 1
=0

-> DDC2 is active for HSCL1/HSDA1 pins.
-> MTV512M remains in DDC1 mode for HSCL1/HSDA1 pins.
-> DDC2 is active for HSCL2/HSDA2 pins.
-> MTV512M remains in DDC1 mode for HSCL2/HSDA2 pins.

IIC interface status register.

& 2

IICSTUS (r) :

bit4

1)
,

IICCTR (r/w) :

bit5

WadrB = 1

-> The data in RCBBUF is word address.

SlvRWB = 1

-> Current transfer is slave transmit

=0

-> Current transfer is slave receive

SAckIn = 1

-> The external IIC host respond NACK.

SLVS

-> The slave block has detected a START, cleared when STOP detected.

INTFLG (w) :

=1

Interrupt flag. An interrupt event will set its individual flag, and, if the corresponding interrupt
enable bit is set, the 8051 INT1 source will be driven by a zero level. Software MUST clear this
register while serving the interrupt routine.

SlvBMI = 1
=0
STOPI = 1
=0
ReStaI = 1

-> No action.
-> Clears SlvBMI flag.
-> No action.
-> Clears STOPI flag.
-> No action.
page 15 of 15

MTV512M
Preliminary
-> Clears ReStaI flag.

=0

-> No action.

WslvA1I = 1

-> Clears WslvA1I flag.

=0

-> No action.

WslvA2I = 1
=0

INTFLG (r) :

=1

-> No action.

=0

MbufI

-> Clears WslvA2I flag.
-> Clears Master IIC bus interrupt flag (MbufI).

Interrupt flag.

TXBI

=1

-> Indicates the TXBBUF need a new data byte, cleared by writing TXBBUF.

RCBI

=1

-> Indicates the RCBBUF has received a new data byte, cleared by reading RCBBUF.
-> Indicates the slave IIC address B match condition.

STOPI = 1

-> Indicates the slave IIC has detected a STOP condition for HSCL1/HSDA1 pins.

ReStaI = 1

-> Indicates the slave IIC has detected a repeat START condition for HSCL1/HSDA1
pins.

WslvA1I = 1

-> Indicates the slave A1 IIC has detected a STOP condition of write mode.

WslvA2I = 1

-> Indicates the slave A2 IIC has detected a STOP condition of write mode.

Interrupt enable.

'
(1

INTEN (w) :

7,
$/

SlvBMI = 1

ETXBI = 1

-> Enables TXBBUF interrupt.

ERCBI = 1

-> Enables RCBBUF interrupt.

ESlvBMI = 1

-> Enables slave address B match interrupt.

ESTOPI = 1

-> Enables IIC bus STOP interrupt.

EReStaI = 1

-> Enables IIC bus repeat START interrupt.

EWSlvA1I = 1

-> Enables slave A1 IIC bus STOP of write mode interrupt.
-> Enables slave A2 IIC bus STOP of write mode interrupt.

1)
,

EWSlvA2I = 1

DDCCTRA1 (w) : DDC interface control register for HSCL1, HSDA1 pins.
DDC1en = 1
=0

-> Disables DDC1 data transfer in DDC1 mode.
-> The 128 bytes of DDCRAM1 can be written by IIC master.

& 2

En128W = 1

-> Enables DDC1 data transfer in DDC1 mode.

=0

-> The 128 bytes of DDCRAM1 cannot be written by IIC master.

Rev0

=1

-> reserved

=0

-> Normal operation.

Rev1

=1

-> Normal operation.

=0
-> reserved
SlvA1bs1,SlvA1bs0 : Slave IIC block A1's slave address length.
= 1,0

-> 5-bit slave address.

= 0,1

-> 6-bit slave address.

= 0,0

-> 7-bit slave address.

SLVA1ADR (w) : Slave IIC block A1's enable and address.
EnslvA1= 1

-> Enables slave IIC block A1.

=0

-> Disables slave IIC block A1.
page 16 of 16

MTV512M
Preliminary
bit6-0 :
RCBBUF (r) :

Slave IIC address A1 to which the slave block should respond.
Slave IIC block B receives data buffer.

TXBBUF (w) : Slave IIC block B transmits data buffer.
SLVBADR (w) : Slave IIC block B's enable and address.
-> Enables slave IIC block B.

ENslvB = 1

-> Disables slave IIC block B.
Slave IIC address B to which the slave block should respond.

=0
bit6-0 :

CTRSLVB (r/w) :
Slave IIC block B's Control registers.
SlvBbs1,SlvBbs0 : Slave IIC block B's slave address length.
-> 5-bit slave address.

= 0,1

-> 6-bit slave address.

= 0,0 -> 7-bit slave address.
SlavBa1 : Bit1 of received Slave B IIC address.
SlavBa0 : Bit0 of received Slave B IIC address.

7,
$/

= 1,0

DDCCTRA2 (w) : DDC interface control register for HSCL2, HSDA2 pins.
DDC1en = 1

-> Enables DDC1 data transfer in DDC1 mode.

-> Disables DDC1 data transfer in DDC1 mode.

En128W = 1

-> The 128 bytes of DDCRAM2 can be written by IIC master.

'
(1

=0
=0

-> The 128 bytes of DDCRAM2 cannot be written by IIC master.

Rev0

=1

-> reserved

=0

-> Normal operation.

Rev1

=1

-> Normal operation.

=0
-> reserved
SlvA2bs1,SlvA2bs0 : Slave IIC block A2's slave address length.
-> 5-bit slave address.

= 0,1

-> 6-bit slave address.

= 0,0

-> 7-bit slave address.

1)
,
= 1,0

SLVA2ADR (w) : Slave IIC block A2's enable and address.
-> Enables slave IIC block A2.

& 2

EnslvA2= 1
=0

bit6-0 :

-> Disables slave IIC block A2.
Slave IIC address A2 to which the slave block should respond.

A/D converter

The MTV512M is equipped with 4 VDD range 6-bit A/D converters. The ADC conversion range is from VSS to
VDD, S/W can select the current convert channel by setting the SADC1/SADC0 bit. The refresh rate for the
ADC is OSC freq./2304 (192us for 12MHz X'tal).
The ADC compares the input pin voltage with internal VDD*N/64 voltage (where N = 0 - 63). The ADC output
value is N when pin voltage is greater than VDD*N/64 and smaller than VDD*(N+1)/64.
Reg name

addr

bit7

ADC

F10h (w)

ENADC

ADC

F10h (r)

W DT

F18h (w)

bit6

bit5

bit4

bit3

bit2

bit1

bit0

SADC3

SADC2

SADC1

SADC0

WDT2

WDT1

WDT0

ADC convert result
WEN

WCLR

page 17 of 17

MTV512M
Preliminary
Low Power Reset (LVR) & Watchdog Timer
W hen the voltage level of power supply is below 2.4V (+/-0.4V) for a specific period of time, the LVR generates
a chip reset signal. After the power supply is above 2.4V (+/-0.4V), LVR maintains in reset state for 144 X'tal
cycle to guarantee the chip exit reset condition with a stable X'tal oscillation. The Watchdog Timer automatically
generates a device reset when it is overflowed. The interval of overflow is 0.25 sec x N, when N is a number
from 1 to 8, and can be programmed via register WDT (2:0). The timer function is disabled after power on reset,
users can activate this function by setting WEN, and clear the timer by setting WCLR.
WDT (w) :

Watchdog Timer control register.

WEN

=1

-> Enables Watchdog Timer.

WCLR

=1

-> Clears Watchdog Timer.
-> Overflow interval = 8 x 0.25 sec.

=1

-> Overflow interval = 1 x 0.25 sec.

=2

-> Overflow interval = 2 x 0.25 sec.

=3

-> Overflow interval = 3 x 0.25 sec.

=4

-> Overflow interval = 4 x 0.25 sec.

=5

-> Overflow interval = 5 x 0.25 sec.

=6

-> Overflow interval = 6 x 0.25 sec.

=7

-> Overflow interval = 7 x 0.25 sec.

ADC control.

'
(1

ADC (w) :

7,
$/

WDT2: WDT0 = 0

ENADC

=1

-> Enables ADC.

SADC0

=1

-> Selects ADC0 pin input.

SADC1

=1

-> Selects ADC1 pin input.

SADC2

=1

-> Selects ADC2 pin input.

SADC3

=1

-> Selects ADC3 pin input.

ADC convert result.

1)
,

ADC (r) :
Etimer

& 2

The Etimer is a 16-bit Timer/Counter which provide capture/reload functions like timer2 in 8052. The type is
selected by C/T2 in the SFRETCTR. Etimer has 2 modes, capture/auto-reload (up or down counting). The
modes are selected by CP/RLS in ETCTR. Etimer contains two 8-bit registers, TLET and THET. When it is
used in the timer mode, THET-TLET count rate is 1/12 of the oscillator frequency. In the counter mode, the
counter is incremented when 1 -> 0 transition at Port 1.0,
1. Capture mode

In the capture mode, if EXEN2 = 0, Etimer is a 16-bit timer or counter. When EXEN2 = 0, Etimer counters
up to FFFFh and then set TF2 upon overflow. This bit will generate an interrupt (INT1) to 8051. If EXEN2 =
1, Etimer capture the current value in THET-TLET into RCAPETH-RCAPETL, respectively when 1-> 0
transition at Port. 1.1. This will also generate an interrupt.
2. Auto-reload mode
Etimer can be programmed to count-up or down when in auto-reload mode. This feature is selected by
DCEN in SFR ETMOD. If EXEN2 = 0, Etimer counts up to 0FFFFh and then set TF2 (overflow). At this
mode, the counter is reloaded the 16-bit value from RCAPETH-RCAPETL. If EXEN2 = 1, the reload
function can be triggered by overflow or by 1 -> 0 transition at Port 1.1.
ETCTR

F88h (w)

TF2

EXF2

-

-

EXEN2

TR2

C/T2

CP/RL2

page 18 of 18

MTV512M
Preliminary
F88h (r)
F89h (w)
F89h (r)
F8Ah (w)
F8Ah (r)
F8Bh (w)
F8Bh (r)
F8Ch (w)
F8Ch (r)
F8Dh (w)
F8Dh (r)
F8Eh (w)

ETMOD
THET
TLET
RCAPETH
RCAPETL
EINT1PEN

ETCTR (w):

TF2

EXF2

EXEN2

TR2

C/T2

CP/RL2
DCEN
DCEN

THET
THET
TLET
TLET
RCAPETH
RCAPETH
RCAPETL
RCAPETL
EEINT1

ETE

TSTP1

Etimer control register
-> No actions

=0

-> Clear Etimer overflow interrupt

7,
$/

=1

TF2

-> No actions

-> Clear Etimer external capture / reload interrupt

=1

-> Enable Port 1.1 capture / reload trigger

=0

-> Disable Port 1.1 capture / reload trigger

TR2

=1

-> Enable Etimer

=0

-> Disable Etimer

C/T2

=1

-> Etimer functions as a counter

=0

-> Etimer functions as a timer

=1

-> Set Etimer in Capture mode

EXEN2

CP/RL2

=0
-> Set Etimer in Auto-reload mode
Etimer control register

TF2
EXF2
EXEN2
TR2
C/T2

-> TF2 state

=

-> EXF2 state

=

-> EXEN2 state

=

-> TR2 state

=

-> CT2 state

=

-> CP/RL2 state

& 2

CP/RL2

=

1)
,

ETCTR (r):

'
(1

=1
=0

EXF2

THET (w/r):
Etimer high 8-bit register
TLET (w/r):
Etimer low 8-bit register
RCAPETH(w/r): Etimer high 8-bit capture/reload register
RCAPETL(w/r): Etimer high 8-bit capture/reload register
EINT1PEN(w): External interrupt control
=1

-> Enable P3.3 as external interrupt1 trigger

=0

ETINT1 (w):

-> Disable P3.3 as external interrupt1 trigger

TSTP1 (w):

=1

-> Enable Etimer interrupt

=0

ETE (w):

-> Disable Etimer interrupt

=1

-> Reserved

=0

-> Normal operation

page 19 of 19

MTV512M
Preliminary
VSYNC Interrupt
The MTV512M checks the VSYNC input pulse and generates an interrupt at its leading edge. The VSYNC flag
is set each time when MTV512M detects a VSYNC pulse. The flag is cleared by S/W writing a "0".
INTFLG

F48h(r/w)

Vsync

INTEN

F49h(w)

EVsync

INTFLG(w): Interrupt flag. An interrupt event will set its individual flag, and, if the corresponding interrupt enable
bit is set, the INT1 source of 8051 core will be driven by a zero level. Software MUST clear this
register while serving the interrupt routine.
Vsync = 1

-> No action.

INTEN(w):

Vsync = 1 -> Indicates a VSYNC interrupt.
Interrupt enable.

& 2

1)
,

'
(1

EVsync = 1 -> Enables VSYNC interrupt.

7,
$/

= 0 -> Clears VSYNC interrupt flag.
INTFLG(r): Interrupt flag.

page 20 of 20

MTV512M
Preliminary
Memory Map of XFR
Reg name

addr

bit7

bit6

bit5

bit4

bit3

IICCTR

F00h (r/w)

DDC2A1

DDC2A
2

IICSTUS

F01h (r)

WadrB

SlvRWB

SAckIn

SLVS

INTFLG

F03h (r)

TXBI

SlvBMI

STOPI

INTFLG

F03h (w)

SlvBMI

INTEN

F04h (w)

ETXBI

ERCBI

DDCCTRA1

F06h (w)

DDC1en

En128W

SLVA1ADR

F07h (w)

ENSlvA

RCBBUF

F08h (r)

Slave B IIC receives buffer

TXBBUF

F08h (w)

Slave B IIC transmits buffer

SLVBADR

F09h (w)

CTRSLVB

F0Ah (r)

CTRSLVB

F0Ah (w)

ADC

F10h (w)

ADC

F10h (r)

W DT

F18h (w)

DA0

F20h(r/w)

DA1

F21h(r/w)

DA2

F22h(r/w)

DA3

F23h(r/w)

DA4

F24h(r/w)

DA5

F25h(r/w)

PORT5

F30h(r/w)

P50

PORT5

F31h(r/w)

P51

PORT5

F32h(r/w)

P52

PORT5

F33h(r/w)

P53

PORT5

F34h(r/w)

P54

RCBI

bit2

bit1

bit0

ReStaI

WSlvAI

WslvA2I

STOPI

ReStaI

WSlvAI

WslvA2I

ESlvBMI

ESTOPI

EReStaI

EWSlvA
I

EWSlvA
2I

Rev0

Rev1

SlvAbs1

SlvAbs0

7,
$/

Slave A IIC address

ENSlvB

Slave B IIC address

SlvBa1

SlvBbs1

ENADC

SADC3

SADC2

SlvBa0
SlvBbs0

SADC1

SADC0

WDT1

WDT0

ADC convert Result

WCLR

WDT2

'
(1

WEN

Pulse width of PWM DAC 0
Pulse width of PWM DAC 1
Pulse width of PWM DAC 2
Pulse width of PWM DAC 3
Pulse width of PWM DAC 4

& 2

1)
,

Pulse width of PWM DAC 5

PORT5

F35h(r/w)

P55

PORT5

F36h(r/w)

P56

PORT6

F38h(r/w)

P60

PORT6

F39h(r/w)

P61

PORT6

F3Ah(r/w)

P62

PORT6

F3Bh(r/w)

P63

PORT6

F3Ch(r/w)

P64

PORT6

F3Dh(r/w)

P65

PORT6

F3Eh(r/w)

P66

PORT6

F3Fh(r/w)

P67

PADMOD

F50h(w)

DA13E

DA12E

DA11E

DA10E

AD3E

AD2E

AD1E

AD0E

PADMOD

F51h(w)

P57E

P56E

P55E

P54E

P53E

P52E

P51E

P50E

page 21 of 21

MTV512M
Preliminary
PADMOD

F52h(w)

HIIC1E

IIICE

HIIC2E

CKOE

PADMOD

F53h(w)

P57oe

P56oe

P55oe

P54oe

P53oe

P52oe

P51oe

P50oe

PADMOD

F54h(w)

P67oe

P66oe

P65oe

P64oe

P63oe

P62oe

P61oe

P60oe

PADMOD

F55h(w)

COP17

COP16

COP15

COP14

COP13

COP12

COP11

COP10

PWMF

DIV253

FclkE

DCLK

ENSCL

OPTION

F56h(w)

PADMOD

F5Eh(w)

PADMOD

F5Fh(w)

PORT7

F76h(r/w)

P76

PORT7

F77h(r/w)

P77

DDCCTRA2

F86h (w)

DDC1en

SLVA2ADR

F87h (w)

ENSlvA2

ETCTR

F88h (w)

TF2

EXF2

RCLK

F88h (r)

TF2

EXF2

RCLK

P77oe

P76oe

En128W

Rev0

F89h (w)

F8Ah (w)

SlvA2bs
0

TCLK

EXEN2

TR2

C/T2

CP/RL2

TCLK

EXEN2

TR2

C/T2

CP/RL2
DCEN
DCEN

THET

THET

'
(1

F8Ah (r)
F8Bh (w)

TLET

F8Bh (r)

TLET

F8Ch (w)

RCAPETH

F8Ch (r)

RCAPETH

F8Dh (w)

RCAPETL

1)
,

F8Dh (r)

EEINT1

ETE

RCAPETL

TSTP1

& 2

F8Eh (w)

SlvA2bs
1

Slave A2 IIC address

F89h (r)

EINT1PEN

Rev1

7,
$/

ETMOD

IP77E

P76E

page 22 of 22

MTV512M
Preliminary
ELECTRICAL PARAMETERS
Absolute Maximum Ratings
at: Ta= 0 to 70 oC, VSS=0V
Symbol

Range

Unit

Maximum Supply Voltage

VDD

-0.3 to +3.6

V

Maximum Input Voltage
(HSYNC, VSYNC & open-drain pins)

Vin1

-0.3 to 3.3+0.3

V

Maximum Input Voltage (other pins)

Vin2

-0.3 to VDD+0.3

V

Maximum Output Voltage

Vout

-0.3 to VDD+0.3

V

Maximum Operating Temperature

Topg

0 to +70

oC

Maximum Storage Temperature

Tstg

-25 to +125

oC

Allowable Operating Conditions
at: Ta= 0 to 70 oC, VSS=0V
Name

Symbol

Supply Voltage

Condition

Vih

Input " L " Voltage

Vil

Operating Freq.

Fopg

DC Characteristics

Max.

Unit

3.0

3.6

V

'
(1

Input " H " Voltage

Min.

3.3V applications

VDD

7,
$/

Name

3.3V applications

0.6 x VDD

VDD +0.3

V

3.3V applications

-0.3

0.3 x VDD

V

-

15

MHz

1)
,

at: Ta=0 to 70 oC, VDD=3.3V, VSS=0V
Name

Symbol

Condition

Min.

Typ.

Max.

Unit

Output " H " Voltage, open drain pin

Voh1

VDD=3.3V, Ioh=0? A

2.65

V

Output " H " Voltage, 8051 I/O port pin

Voh2

VDD=3.3V, Ioh=-50? A

2.65

V

Output " H " Voltage, CMOS output

Voh3

VDD=3.3V, Ioh=-4mA

2.65

V

& 2

Output " L " Voltage

Power Supply Current

Vol

Iol=5mA

0.45

V

Active

RST Pull-Down Resistor

Rrst

Pin Capacitance

Cio

18

24

mA

Idle

1.3

4.0

mA

Power-Down

Idd

50

80

?A

250

Kohm

15

pF

VDD=3.3V

150

page 23 of 23

MTV512M
Preliminary
AC Characteristics
at: Ta=0 to 70 oC, VDD=3.3V, VSS=0V
Name

Symbol

Condition

Min.

Typ.

Max.

Unit

Crystal Frequency

fXtal

PWM DAC Frequency

fDA

fXtal=12MHz

46.875

94.86

KHz

HS input pulse Width

tHIPW

fXtal=12MHz

0.3

7.5

uS

VS input pulse Width

tVIPW

fXtal=12MHz

3

HSYNC to Hblank output jitter

tHHBJ

H+V to Vblank output delay

tVVBD

fXtal=12MHz

VS pulse width in H+V signal

tVCPW

FXtal=12MHz

12

MHz

uS
5
8

uS
uS

7,
$/

20

nS

Test Mode Condition

In normal application, users should avoid the MTV512M entering its test mode or writer mode, outlined as
follows: adding pull-up resistor to HSCL1/HSDA1/HSCL2/HSDA2 pins is recommended.

& 2

1)
,

'
(1

Test Mode: RESET's falling edge & HSCL1=0 & HSDA1 & HSCL2=0 & HSDA2 = 0

page 24 of 24

MTV512M
Preliminary
PACKAGE DIMENSION

Symbol
A
A1

Dimension in Millimeters

Dimension in Inches

Min

Nom

Max

Min

Nom

Max

-

-

4.70

-

-

0.185

0.51

-

-

0.020

-

-

3.70

3.80

3.90

0.145

0.150

0.155

b

0.41

0.46

0.56

0.016

0.018

0.022

b1

0.65

0.70

0.80

0.026

0.028

0.032

c

0.18

0.25

0.33

0.007

0.010

0.013

D

16.46

16.60

16.71

0.648

0.653

0.658

E

16.46

16.60

16.71

0.648

0.653

0.658

& 2

A2

1)
,

'
(1

7,
$/

44-pin PLCC

e

1.27 (Typ)

0.050 (Typ)

Gd

15.00

15.50

16.00

0.590

0.610

0.630

Ge

15.00

15.50

16.00

0.590

0.610

0.630

Hd

17.30

17.50

17.80

0.680

0.690

0.700

He

17.30

17.50

17.80

0.680

0.690

0.700

L

2.29

2.54

2.80

0.090

0.100

0.110

0?

-

10?

0?

-

10?

page 25 of 25

MTV512M
Preliminary
Ordering Information
Standard Configurations:
Part Type

Package Type

MTV

512M

V: PLCC

& 2

1)
,

'
(1

7,
$/

Prefix

page 26 of 26


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