now it looks like, im using keil mVision 4.22.22.0 . I have a skype - maybe it is easy to communcate
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- ʱÖÓÅäÖÃ:
- XTAL = 12.00 MHz
- SYSCLK = 72.00 MHz
- HCLK = SYSCLK = 72.00 MHz
- PCLK1 = HCLK/2 = 36.00 MHz
- PCLK2 = HCLK = 72.00 MHz
- ADCLK = PCLK2/6 = 12.00 MHz
- SYSTICK = HCLK/8 = 9.00 MHz
- ÔÚÕæ²ÊÒº¾§ÉÏÏÔʾλͼ
/*----------------------------------------------------------------------------
* Name: Retarget.c
* Purpose: 'Retarget' layer for target-dependent low level functions
* Version: V1.0
*----------------------------------------------------------------------------
* This file is part of the uVision/ARM development tools.
* This software may only be used under the terms of a valid, current,
* end user licence from KEIL for a compatible version of KEIL software
* development tools. Nothing else gives you the right to use this software.
*
* Copyright (c) 2005-2007 Keil Software. All rights reserved.
*----------------------------------------------------------------------------*/
#include & lt; stdio.h & gt;
#include & lt; rt_misc.h & gt;
#pragma import(__use_no_semihosting_swi)
/*----------------------------------------------------------------------------
external functions
*----------------------------------------------------------------------------*/
extern int SendChar(int ch);
extern int GetKey(void);
struct __FILE {
int handle; // Add whatever you need here
};
FILE __stdout;
FILE __stdin;
/*----------------------------------------------------------------------------
fputc
*----------------------------------------------------------------------------*/
int fputc(int ch, FILE *f) {
return (SendChar(ch));
}
/*----------------------------------------------------------------------------
fgetc
*----------------------------------------------------------------------------*/
int fgetc(FILE *f) {
return (SendChar(GetKey()));
}
/*----------------------------------------------------------------------------
_ttywrch
*----------------------------------------------------------------------------*/
void _ttywrch(int ch) {
SendChar (ch);
}
/*----------------------------------------------------------------------------
ferror
*----------------------------------------------------------------------------*/
int ferror(FILE *f) {
// Your implementation of ferror
return EOF;
}
/*----------------------------------------------------------------------------
_sys_exit
*----------------------------------------------------------------------------*/
void _sys_exit(int return_code) {
label: goto label; // endless loop
}
/*
\\\|///
\\ - - //
( @ @ )
+---------------------oOOo-(_)-oOOo-------------------------+
| ÖÇÁÖSTM32¿ª·¢°åÊÔÑé³ÌÐò |
| Timer2 PWM Êä³ö·½Ê½ÊÔÑé |
| ÁõЦȻ by Xiaoran Liu |
| 2008.4.16 |
| |
| ÖÇÁÖ²â¿Ø¼¼ÊõÑо¿Ëù ZERO research group |
| www.the0.net |
| Oooo |
+-----------------------oooO--( )-------------------------+
( ) ) /
\ ( (_/
\_)
*/
/*----------------------------------------------------------*\
| ÒýÈëÏà¹ØоƬµÄÍ·Îļþ |
\*----------------------------------------------------------*/
#include & lt; stdio.h & gt;
#include & lt; stm32f10x_lib.h & gt; // STM32F10x Library Definitions
#include " STM32_Init.h " // STM32 Initialization
#include " spi.h "
#include " enc28j60.h "
#include " simple_server.h "
//#include " TFT018.h "
/*----------------------------------------------------------*\
| HARDWARE DEFINE |
\*----------------------------------------------------------*/
#define LED ( 1 & lt; & lt; 5 ) // PB5: LED D2
#define BP2 0x2000 // PC13: BP2
#define BP3 0x0001 // PA0 : BP3
#define UP 0x0800 // PB11: UP
#define RIGHT 0x1000 // PB12: RIGHT
#define LEFT 0x2000 // PB13: LEFT
#define DOWN 0x4000 // PB14: DOWN
#define OK 0x8000 // PB15: OK
#define ENC28J60_CSL() GPIOA- & gt; BRR = ENC28J60_CS;
#define ENC28J60_CSH() GPIOA- & gt; BSRR = ENC28J60_CS;
#define JOYSTICK 0xF800 // JOYSTICK ALL KEYS
/*----------------------------------------------------------*\
| SOFTWARE DATA |
\*----------------------------------------------------------*/
/*----------------------------------------------------------*\
| Delay |
| ÑÓʱ Inserts a delay time. |
| nCount: ÑÓʱʱ¼ä |
| nCount: specifies the delay time length. |
\*----------------------------------------------------------*/
void Delay(vu32 nCount) {
for(; nCount != 0; nCount--);
}
/*----------------------------------------------------------*\
| SendChar |
| Write character to Serial Port. |
\*----------------------------------------------------------*/
int SendChar (int ch) {
while (!(USART1- & gt; SR & USART_FLAG_TXE));
USART1- & gt; DR = (ch & 0x1FF);
return (ch);
}
/*----------------------------------------------------------*\
| GetKey |
| Read character to Serial Port. |
\*----------------------------------------------------------*/
int GetKey (void) {
while (!(USART1- & gt; SR & USART_FLAG_RXNE));
return ((int)(USART1- & gt; DR & 0x1FF));
}
const unsigned char enc28j60_MAC[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
/*----------------------------------------------------------*\
| MIAN ENTRY |
\*----------------------------------------------------------*/
int main (void)
{
int rev = 0;
stm32_Init (); // STM32 setup
// GPIOD- & gt; ODR & = ~(1 & lt; & lt; 9);//GPIOA- & gt; BRR = ENC28J60_CS;
// GPIOD- & gt; ODR |= 1 & lt; & lt; 9;//GPIOA- & gt; BSRR = ENC28J60_CS;
printf ( " SPI1_Init starting...\r\n " );
SPI1_Init();
// ENC28J60_CSH();
printf ( " enc28j60 init...\r\n " );
//enc28j60Init((unsigned char *)enc28j60_MAC);
// simple_server();
// enc28j60Init((unsigned char *)enc28j60_MAC);
ENC28J60_CSL();
//Delay(250);
// SPI1_ReadWrite(0x5f);//SPI_I2S_SendData(SPI1, 0x5f); //çàïèñü ECON1
// SPI1_ReadWrite(0x03);//SPI_I2S_SendData(SPI1, 0x03); // âûáîð 3 áàíêà ðåãèñòðîâ
// SPI1_ReadWrite(0x12);//SPI_I2S_SendData(SPI1, 0x12); // êîìàíäà íà ÷òåíèå âåðñèè
//SPI_I2S_ReceiveData(SPI1);
// rev=SPI1_ReadWrite(0xff);
Delay(250000);
ENC28J60_CSH();
// = SPI_I2S_ReceiveData(SPI1); //enc28j60getrev();
printf ( " rev...%x\r\n " ,rev);
return rev;
/*
for(;;) {
unsigned char c;
printf ( " Press a key. " );
c = getchar ();
printf ( " \r\n " );
printf ( " You pressed '%c'.\r\n\r\n " , c);
}
*/
}
/*----------------------------------------------------------*\
| END OF FILE |
\*----------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Name: STM32_Init.h
* Purpose: STM32 peripherals initialisation definitions
* Version: V1.00
*----------------------------------------------------------------------------
* This file is part of the uVision/ARM development tools.
* This software may only be used under the terms of a valid, current,
* end user licence from KEIL for a compatible version of KEIL software
* development tools. Nothing else gives you the right to use it.
*
* Copyright (c) 2005-2007 Keil Software.
*----------------------------------------------------------------------------*/
/* Define to prevent recursive inclusion ------------------------------------ */
#ifndef __STM32_INIT_H
#define __STM32_INIT_H
extern void stm32_Init (void);
extern unsigned int stm32_GetPCLK1 (void);
#endif
//#include " includes.h "
#include " enc28j60.h "
#include " spi.h "
#include & lt; stdio.h & gt;
static unsigned char Enc28j60Bank;
static unsigned int NextPacketPtr;
unsigned char enc28j60ReadOp(unsigned char op, unsigned char address)
{
unsigned char dat = 0;
ENC28J60_CSL();
dat = op | (address & ADDR_MASK);
SPI1_ReadWrite(dat);
dat = SPI1_ReadWrite(0xFF);
// do dummy read if needed (for mac and mii, see datasheet page 29)
if(address & 0x80)
{
dat = SPI1_ReadWrite(0xFF);
}
// release CS
ENC28J60_CSH();
return dat;
}
void enc28j60WriteOp(unsigned char op, unsigned char address, unsigned char data)
{
unsigned char dat = 0;
ENC28J60_CSL();
// issue write command
dat = op | (address & ADDR_MASK);
SPI1_ReadWrite(dat);
// write data
dat = data;
SPI1_ReadWrite(dat);
ENC28J60_CSH();
}
void enc28j60ReadBuffer(unsigned int len, unsigned char* data)
{
ENC28J60_CSL();
// issue read command
SPI1_ReadWrite(ENC28J60_READ_BUF_MEM);
while(len)
{
len--;
// read data
*data = (unsigned char)SPI1_ReadWrite(0);
data++;
}
*data='\0';
ENC28J60_CSH();
}
void enc28j60WriteBuffer(unsigned int len, unsigned char* data)
{
ENC28J60_CSL();
// issue write command
SPI1_ReadWrite(ENC28J60_WRITE_BUF_MEM);
while(len)
{
len--;
SPI1_ReadWrite(*data);
data++;
}
ENC28J60_CSH();
}
void enc28j60SetBank(unsigned char address)
{
// set the bank (if needed)
if((address & BANK_MASK) != Enc28j60Bank)
{
// set the bank
enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, ECON1, (ECON1_BSEL1|ECON1_BSEL0));
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, (address & BANK_MASK) & gt; & gt; 5);
Enc28j60Bank = (address & BANK_MASK);
}
}
unsigned char enc28j60Read(unsigned char address)
{
// set the bank
enc28j60SetBank(address);
// do the read
return enc28j60ReadOp(ENC28J60_READ_CTRL_REG, address);
}
void enc28j60Write(unsigned char address, unsigned char data)
{
// set the bank
enc28j60SetBank(address);
// do the write
enc28j60WriteOp(ENC28J60_WRITE_CTRL_REG, address, data);
}
void enc28j60PhyWrite(unsigned char address, unsigned int data)
{
// set the PHY register address
enc28j60Write(MIREGADR, address);
// write the PHY data
enc28j60Write(MIWRL, data);
enc28j60Write(MIWRH, data & gt; & gt; 8);
// wait until the PHY write completes
while(enc28j60Read(MISTAT) & MISTAT_BUSY)
{
//Del_10us(1);
//_nop_();
}
}
void enc28j60clkout(unsigned char clk)
{
//setup clkout: 2 is 12.5MHz:
enc28j60Write(ECOCON, clk & 0x7);
}
void enc28j60Init(unsigned char* macaddr)
{
// initialize I/O
//enc28j60CSinit();
ENC28J60_CSH();
//enc28j60SetSCK();
//enc28j60HWreset();
// perform system reset
enc28j60WriteOp(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
// Del_1ms(250);
// check CLKRDY bit to see if reset is complete
// The CLKRDY does not work. See Rev. B4 Silicon Errata point. Just wait.
//while(!(enc28j60Read(ESTAT) & ESTAT_CLKRDY));
// do bank 0 stuff
// initialize receive buffer
// 16-bit transfers, must write low byte first
// set receive buffer start address
NextPacketPtr = RXSTART_INIT;
// Rx start
enc28j60Write(ERXSTL, RXSTART_INIT & 0xFF);
enc28j60Write(ERXSTH, RXSTART_INIT & gt; & gt; 8);
// set receive pointer address
enc28j60Write(ERXRDPTL, RXSTART_INIT & 0xFF);
enc28j60Write(ERXRDPTH, RXSTART_INIT & gt; & gt; 8);
// RX end
enc28j60Write(ERXNDL, RXSTOP_INIT & 0xFF);
enc28j60Write(ERXNDH, RXSTOP_INIT & gt; & gt; 8);
// TX start
enc28j60Write(ETXSTL, TXSTART_INIT & 0xFF);
enc28j60Write(ETXSTH, TXSTART_INIT & gt; & gt; 8);
// TX end
enc28j60Write(ETXNDL, TXSTOP_INIT & 0xFF);
enc28j60Write(ETXNDH, TXSTOP_INIT & gt; & gt; 8);
// do bank 1 stuff, packet filter:
// For broadcast packets we allow only ARP packtets
// All other packets should be unicast only for our mac (MAADR)
//
// The pattern to match on is therefore
// Type ETH.DST
// ARP BROADCAST
// 06 08 -- ff ff ff ff ff ff - & gt; ip checksum for theses bytes=f7f9
// in binary these poitions are:11 0000 0011 1111
// This is hex 303F- & gt; EPMM0=0x3f,EPMM1=0x30
enc28j60Write(ERXFCON, ERXFCON_UCEN|ERXFCON_CRCEN|ERXFCON_PMEN);
enc28j60Write(EPMM0, 0x3f);
enc28j60Write(EPMM1, 0x30);
enc28j60Write(EPMCSL, 0xf9);
enc28j60Write(EPMCSH, 0xf7);
//
//
// do bank 2 stuff
// enable MAC receive
enc28j60Write(MACON1, MACON1_MARXEN|MACON1_TXPAUS|MACON1_RXPAUS);
// bring MAC out of reset
enc28j60Write(MACON2, 0x00);
// enable automatic padding to 60bytes and CRC operations
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN|MACON3_FULDPX);
// set inter-frame gap (non-back-to-back)
enc28j60Write(MAIPGL, 0x12);
enc28j60Write(MAIPGH, 0x0C);
// set inter-frame gap (back-to-back)
enc28j60Write(MABBIPG, 0x12);
// Set the maximum packet size which the controller will accept
// Do not send packets longer than MAX_FRAMELEN:
enc28j60Write(MAMXFLL, MAX_FRAMELEN & 0xFF);
enc28j60Write(MAMXFLH, MAX_FRAMELEN & gt; & gt; 8);
// do bank 3 stuff
// write MAC address
// NOTE: MAC address in ENC28J60 is byte-backward
enc28j60Write(MAADR5, macaddr[0]);
enc28j60Write(MAADR4, macaddr[1]);
enc28j60Write(MAADR3, macaddr[2]);
enc28j60Write(MAADR2, macaddr[3]);
enc28j60Write(MAADR1, macaddr[4]);
enc28j60Write(MAADR0, macaddr[5]);
printf( " MAADR5 = 0x%x\r\n " , enc28j60Read(MAADR5));
printf( " MAADR4 = 0x%x\r\n " , enc28j60Read(MAADR4));
printf( " MAADR3 = 0x%x\r\n " , enc28j60Read(MAADR3));
printf( " MAADR2 = 0x%x\r\n " , enc28j60Read(MAADR2));
printf( " MAADR1 = 0x%x\r\n " , enc28j60Read(MAADR1));
printf( " MAADR0 = 0x%x\r\n " , enc28j60Read(MAADR0));
enc28j60PhyWrite(PHCON1, PHCON1_PDPXMD);
// no loopback of transmitted frames
enc28j60PhyWrite(PHCON2, PHCON2_HDLDIS);
// switch to bank 0
enc28j60SetBank(ECON1);
// enable interrutps
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, EIE, EIE_INTIE|EIE_PKTIE);
// enable packet reception
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
}
// read the revision of the chip:
unsigned char enc28j60getrev(void)
{
return(enc28j60Read(EREVID));
}
void enc28j60PacketSend(unsigned int len, unsigned char* packet)
{
// Set the write pointer to start of transmit buffer area
enc28j60Write(EWRPTL, TXSTART_INIT & 0xFF);
enc28j60Write(EWRPTH, TXSTART_INIT & gt; & gt; 8);
// Set the TXND pointer to correspond to the packet size given
enc28j60Write(ETXNDL, (TXSTART_INIT+len) & 0xFF);
enc28j60Write(ETXNDH, (TXSTART_INIT+len) & gt; & gt; 8);
// write per-packet control byte (0x00 means use macon3 settings)
enc28j60WriteOp(ENC28J60_WRITE_BUF_MEM, 0, 0x00);
// copy the packet into the transmit buffer
enc28j60WriteBuffer(len, packet);
// send the contents of the transmit buffer onto the network
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRTS);
// Reset the transmit logic problem. See Rev. B4 Silicon Errata point 12.
if( (enc28j60Read(EIR) & EIR_TXERIF) )
{
enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRTS);
}
}
// Gets a packet from the network receive buffer, if one is available.
// The packet will by headed by an ethernet header.
// maxlen The maximum acceptable length of a retrieved packet.
// packet Pointer where packet data should be stored.
// Returns: Packet length in bytes if a packet was retrieved, zero otherwise.
unsigned int enc28j60PacketReceive(unsigned int maxlen, unsigned char* packet)
{
unsigned int rxstat;
unsigned int len;
// check if a packet has been received and buffered
//if( !(enc28j60Read(EIR) & EIR_PKTIF) ){
// The above does not work. See Rev. B4 Silicon Errata point 6.
if( enc28j60Read(EPKTCNT) ==0 )
{
return(0);
}
// Set the read pointer to the start of the received packet
enc28j60Write(ERDPTL, (NextPacketPtr));
enc28j60Write(ERDPTH, (NextPacketPtr) & gt; & gt; 8);
// read the next packet pointer
NextPacketPtr = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
NextPacketPtr |= enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0) & lt; & lt; 8;
// read the packet length (see datasheet page 43)
len = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
len |= enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0) & lt; & lt; 8;
len-=4; //remove the CRC count
// read the receive status (see datasheet page 43)
rxstat = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
rxstat |= enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0) & lt; & lt; 8;
// limit retrieve length
if (len & gt; maxlen-1)
{
len=maxlen-1;
}
// check CRC and symbol errors (see datasheet page 44, table 7-3):
// The ERXFCON.CRCEN is set by default. Normally we should not
// need to check this.
if ((rxstat & 0x80)==0)
{
// invalid
len=0;
}
else
{
// copy the packet from the receive buffer
enc28j60ReadBuffer(len, packet);
}
// Move the RX read pointer to the start of the next received packet
// This frees the memory we just read out
enc28j60Write(ERXRDPTL, (NextPacketPtr));
enc28j60Write(ERXRDPTH, (NextPacketPtr) & gt; & gt; 8);
// decrement the packet counter indicate we are done with this packet
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_PKTDEC);
return(len);
}
/*----------------------------------------------------------------------------
* Name: STM32_Init.c
* Purpose: STM32 peripherals initialisation
* Version: V1.10
*----------------------------------------------------------------------------
* This file is part of the uVision/ARM development tools.
* This software may only be used under the terms of a valid, current,
* end user licence from KEIL for a compatible version of KEIL software
* development tools. Nothing else gives you the right to use this software.
*
* Copyright (c) 2005-2007 Keil Software. All rights reserved.
*----------------------------------------------------------------------------*/
#include & lt; stm32f10x_lib.h & gt; // STM32F10x Library Definitions
#include " STM32_Reg.h " // missing bit definitions
//-------- & lt; & lt; & lt; Use Configuration Wizard in Context Menu & gt; & gt; & gt; -----------------
//
//=========================================================================== Clock Configuration
// & lt; e0 & gt; Clock Configuration
// & lt; h & gt; Clock Control Register Configuration (RCC_CR)
// & lt; e1.24 & gt; PLLON: PLL enable
// & lt; i & gt; Default: PLL Disabled
// & lt; o2.18..21 & gt; PLLMUL: PLL Multiplication Factor
// & lt; i & gt; Default: PLLSRC * 2
// & lt; 0= & gt; PLLSRC * 2
// & lt; 1= & gt; PLLSRC * 3
// & lt; 2= & gt; PLLSRC * 4
// & lt; 3= & gt; PLLSRC * 5
// & lt; 4= & gt; PLLSRC * 6
// & lt; 5= & gt; PLLSRC * 7
// & lt; 6= & gt; PLLSRC * 8
// & lt; 7= & gt; PLLSRC * 9
// & lt; 8= & gt; PLLSRC * 10
// & lt; 9= & gt; PLLSRC * 11
// & lt; 10= & gt; PLLSRC * 12
// & lt; 11= & gt; PLLSRC * 13
// & lt; 12= & gt; PLLSRC * 14
// & lt; 13= & gt; PLLSRC * 15
// & lt; 14= & gt; PLLSRC * 16
// & lt; o2.17 & gt; PLLXTPRE: HSE divider for PLL entry
// & lt; i & gt; Default: HSE
// & lt; 0= & gt; HSE
// & lt; 1= & gt; HSE / 2
// & lt; o2.16 & gt; PLLSRC: PLL entry clock source
// & lt; i & gt; Default: HSI/2
// & lt; 0= & gt; HSI / 2
// & lt; 1= & gt; HSE (PLLXTPRE output)
// & lt; /e & gt;
// & lt; o1.19 & gt; CSSON: Clock Security System enable
// & lt; i & gt; Default: Clock detector OFF
// & lt; o1.18 & gt; HSEBYP: External High Speed clock Bypass
// & lt; i & gt; Default: HSE oscillator not bypassed
// & lt; o1.16 & gt; HSEON: External High Speed clock enable
// & lt; i & gt; Default: HSE oscillator OFF
// & lt; o1.3..7 & gt; HSITRIM: Internal High Speed clock trimming & lt; 0-31 & gt;
// & lt; i & gt; Default: 0
// & lt; o1.0 & gt; HSION: Internal High Speed clock enable
// & lt; i & gt; Default: internal 8MHz RC oscillator OFF
// & lt; /h & gt;
// & lt; h & gt; Clock Configuration Register Configuration (RCC_CFGR)
// & lt; o2.24..26 & gt; MCO: Microcontroller Clock Output
// & lt; i & gt; Default: MCO = noClock
// & lt; 0= & gt; MCO = noClock
// & lt; 4= & gt; MCO = SYSCLK
// & lt; 5= & gt; MCO = HSI
// & lt; 6= & gt; MCO = HSE
// & lt; 7= & gt; MCO = PLLCLK / 2
// & lt; o2.22 & gt; USBPRE: USB prescaler
// & lt; i & gt; Default: USBCLK = PLLCLK / 1.5
// & lt; 0= & gt; USBCLK = PLLCLK / 1.5
// & lt; 1= & gt; USBCLK = PLLCLK
// & lt; o2.14..15 & gt; ADCPRE: ADC prescaler
// & lt; i & gt; Default: ADCCLK=PCLK2 / 2
// & lt; 0= & gt; ADCCLK = PCLK2 / 2
// & lt; 1= & gt; ADCCLK = PCLK2 / 4
// & lt; 2= & gt; ADCCLK = PCLK2 / 6
// & lt; 3= & gt; ADCCLK = PCLK2 / 8
// & lt; o2.11..13 & gt; PPRE2: APB High speed prescaler (APB2)
// & lt; i & gt; Default: PCLK2 = HCLK
// & lt; 0= & gt; PCLK2 = HCLK
// & lt; 4= & gt; PCLK2 = HCLK / 2
// & lt; 5= & gt; PCLK2 = HCLK / 4
// & lt; 6= & gt; PCLK2 = HCLK / 8
// & lt; 7= & gt; PCLK2 = HCLK / 16
// & lt; o2.8..10 & gt; PPRE1: APB Low speed prescaler (APB1)
// & lt; i & gt; Default: PCLK1 = HCLK
// & lt; 0= & gt; PCLK1 = HCLK
// & lt; 4= & gt; PCLK1 = HCLK / 2
// & lt; 5= & gt; PCLK1 = HCLK / 4
// & lt; 6= & gt; PCLK1 = HCLK / 8
// & lt; 7= & gt; PCLK1 = HCLK / 16
// & lt; o2.4..7 & gt; HPRE: AHB prescaler
// & lt; i & gt; Default: HCLK = SYSCLK
// & lt; 0= & gt; HCLK = SYSCLK
// & lt; 8= & gt; HCLK = SYSCLK / 2
// & lt; 9= & gt; HCLK = SYSCLK / 4
// & lt; 10= & gt; HCLK = SYSCLK / 8
// & lt; 11= & gt; HCLK = SYSCLK / 16
// & lt; 12= & gt; HCLK = SYSCLK / 64
// & lt; 13= & gt; HCLK = SYSCLK / 128
// & lt; 14= & gt; HCLK = SYSCLK / 256
// & lt; 15= & gt; HCLK = SYSCLK / 512
// & lt; o2.0..1 & gt; SW: System Clock Switch
// & lt; i & gt; Default: SYSCLK = HSE
// & lt; 0= & gt; SYSCLK = HSI
// & lt; 1= & gt; SYSCLK = HSE
// & lt; 2= & gt; SYSCLK = PLLCLK
// & lt; /h & gt;
// & lt; o3 & gt; HSE: External High Speed Clock [Hz] & lt; 4000000-16000000 & gt;
// & lt; i & gt; clock value for the used External High Speed Clock (4MHz & lt; = HSE & lt; = 16MHz).
// & lt; i & gt; Default: 8000000 (8MHz)
// & lt; /e & gt; End of Clock Configuration
#define __CLOCK_SETUP 1
#define __RCC_CR_VAL 0x01010082
#define __RCC_CFGR_VAL 0x00118402
#define __HSE 4000000
//=========================================================================== Independent Watchdog Configuration
// & lt; e0 & gt; Independent Watchdog Configuration
// & lt; o1 & gt; IWDG period [us] & lt; 125-32000000:125 & gt;
// & lt; i & gt; Set the timer period for Independent Watchdog.
// & lt; i & gt; Default: 1000000 (1s)
// & lt; /e & gt;
#define __IWDG_SETUP 0
#define __IWDG_PERIOD 0x001E8480
//=========================================================================== System Timer Configuration
// & lt; e0 & gt; System Timer Configuration
// & lt; o1.2 & gt; System Timer clock source selection
// & lt; i & gt; Default: SYSTICKCLK = HCLK/8
// & lt; 0= & gt; SYSTICKCLK = HCLK/8
// & lt; 1= & gt; SYSTICKCLK = HCLK
// & lt; o2 & gt; SYSTICK period [ms] & lt; 1-1000:10 & gt;
// & lt; i & gt; Set the timer period for System Timer.
// & lt; i & gt; Default: 1 (1ms)
// & lt; o1.1 & gt; System Timer interrupt enabled
// & lt; /e & gt;
#define __SYSTICK_SETUP 0
#define __SYSTICK_CTRL_VAL 0x00000006
#define __SYSTICK_PERIOD 0x000000C8
//=========================================================================== Real Time Clock Configuration
// & lt; e0 & gt; Real Time Clock Configuration
// & lt; o1.8..9 & gt; RTC clock source selection
// & lt; i & gt; Default: No Clock
// & lt; 0= & gt; No Clock
// & lt; 1= & gt; RTCCLK = LSE (32,768kHz)
// & lt; 2= & gt; RTCCLK = LSI (32 kHz)
// & lt; 3= & gt; RTCCLK = HSE/128
// & lt; o2 & gt; RTC period [ms] & lt; 10-1000:10 & gt;
// & lt; i & gt; Set the timer period for Real Time Clock.
// & lt; i & gt; Default: 1000 (1s)
// & lt; h & gt; RTC Time Value
// & lt; o3 & gt; Hour & lt; 0-23 & gt;
// & lt; o4 & gt; Minute & lt; 0-59 & gt;
// & lt; o5 & gt; Second & lt; 0-59 & gt;
// & lt; /h & gt;
// & lt; h & gt; RTC Alarm Value
// & lt; o6 & gt; Hour & lt; 0-23 & gt;
// & lt; o7 & gt; Minute & lt; 0-59 & gt;
// & lt; o8 & gt; Second & lt; 0-59 & gt;
// & lt; /h & gt;
// & lt; e9 & gt; RTC interrupts
// & lt; o10.0 & gt; RTC_CRH.SECIE: Second interrupt enabled
// & lt; o10.1 & gt; RTC_CRH.ALRIE: Alarm interrupt enabled
// & lt; o10.2 & gt; RTC_CRH.OWIE: Overflow interrupt enabled
// & lt; /e & gt;
// & lt; /e & gt;
#define __RTC_SETUP 0
#define __RTC_CLKSRC_VAL 0x00000100
#define __RTC_PERIOD 0x000003E8
#define __RTC_TIME_H 0x00
#define __RTC_TIME_M 0x00
#define __RTC_TIME_S 0x00
#define __RTC_ALARM_H 0x00
#define __RTC_ALARM_M 0x01
#define __RTC_ALARM_S 0x00
#define __RTC_INTERRUPTS 0x00000001
#define __RTC_CRH 0x00000001
//=========================================================================== Timer Configuration
// & lt; e0 & gt; Timer Configuration
//--------------------------------------------------------------------------- Timer 1 enabled
// & lt; e1.0 & gt; TIM1 : Timer 1 enabled
// & lt; o4 & gt; TIM1 period [us] & lt; 1-72000000:10 & gt;
// & lt; i & gt; Set the timer period for Timer 1.
// & lt; i & gt; Default: 1000 (1ms)
// & lt; i & gt; Ignored if detailed settings is selected
// & lt; o7 & gt; TIM1 repetition counter & lt; 0-255 & gt;
// & lt; i & gt; Set the repetition counter for Timer 1.
// & lt; i & gt; Default: 0
// & lt; i & gt; Ignored if detailed settings is selected
// & lt; e2.0 & gt; TIM1 detailed settings
//--------------------------------------------------------------------------- Timer 1 detailed settings
// & lt; o5 & gt; TIM1.PSC: Timer1 Prescaler & lt; 0-65535 & gt;
// & lt; i & gt; Set the prescaler for Timer 1.
// & lt; o6 & gt; TIM1.ARR: Timer1 Auto-reload & lt; 0-65535 & gt;
// & lt; i & gt; Set the Auto-reload for Timer 1.
// & lt; o7 & gt; TIM1.RCR: Timer1 Repetition Counter & lt; 0-255 & gt;
// & lt; i & gt; Set the Repetition Counter for Timer 1.
//
// & lt; h & gt; Timer 1 Control Register 1 Configuration (TIM1_CR1)
// & lt; o8.8..9 & gt; TIM1_CR1.CKD: Clock division
// & lt; i & gt; Default: tDTS = tCK_INT
// & lt; i & gt; devision ratio between timer clock and dead time
// & lt; 0= & gt; tDTS = tCK_INT
// & lt; 1= & gt; tDTS = 2*tCK_INT
// & lt; 2= & gt; tDTS = 4*tCK_INT
// & lt; o8.7 & gt; TIM1_CR1.ARPE: Auto-reload preload enable
// & lt; i & gt; Default: Auto-reload preload disenabled
// & lt; o8.5..6 & gt; TIM1_CR1.CMS: Center aligned mode selection
// & lt; i & gt; Default: Edge-aligned
// & lt; 0= & gt; Edge-aligned
// & lt; 1= & gt; Center-aligned mode1
// & lt; 2= & gt; Center-aligned mode2
// & lt; 3= & gt; Center-aligned mode3
// & lt; o8.4 & gt; TIM1_CR1.DIR: Direction
// & lt; i & gt; Default: DIR = Counter used as up-counter
// & lt; i & gt; read only if timer is configured as Center-aligned or Encoder mode
// & lt; 0= & gt; Counter used as up-counter
// & lt; 1= & gt; Counter used as down-counter
// & lt; o8.3 & gt; TIM1_CR1.OPM: One pulse mode enable
// & lt; i & gt; Default: One pulse mode disabled
// & lt; o8.2 & gt; TIM1_CR1.URS: Update request source
// & lt; i & gt; Default: URS = Counter over-/underflow, UG bit, Slave mode controller
// & lt; 0= & gt; Counter over-/underflow, UG bit, Slave mode controller
// & lt; 1= & gt; Counter over-/underflow
// & lt; o8.1 & gt; TIM1_CR1.UDIS: Update disable
// & lt; i & gt; Default: Update enabled
// & lt; /h & gt;
//
// & lt; h & gt; Timer 1 Control Register 2 Configuration (TIM1_CR2)
// & lt; o9.14 & gt; TIM1_CR2.OIS4: Output Idle state4 (OC4 output) & lt; 0-1 & gt;
// & lt; o9.13 & gt; TIM1_CR2.OIS3N: Output Idle state3 (OC3N output) & lt; 0-1 & gt;
// & lt; o9.12 & gt; TIM1_CR2.OIS3: Output Idle state3 (OC3 output) & lt; 0-1 & gt;
// & lt; o9.11 & gt; TIM1_CR2.OIS2N: Output Idle state2 (OC2N output) & lt; 0-1 & gt;
// & lt; o9.10 & gt; TIM1_CR2.OIS2: Output Idle state2 (OC2 output) & lt; 0-1 & gt;
// & lt; o9.9 & gt; TIM1_CR2.OIS1N: Output Idle state1 (OC1N output)
// & lt; i & gt; Default: OC1 = 0
// & lt; 0= & gt; OC1N=0 when MOE=0
// & lt; 1= & gt; OC1N=1 when MOE=0
// & lt; o9.8 & gt; TIM1_CR2.OI1S: Output Idle state1 (OC1 output)
// & lt; i & gt; Default: OC1=0
// & lt; 0= & gt; OC1=0 when MOE=0
// & lt; 1= & gt; OC1=1 when MOE=0
// & lt; o9.7 & gt; TIM1_CR2.TI1S: TI1 Selection
// & lt; i & gt; Default: TIM1CH1 connected to TI1 input
// & lt; 0= & gt; TIM1CH1 connected to TI1 input
// & lt; 1= & gt; TIM1CH1,CH2,CH3 connected to TI1 input
// & lt; o9.4..6 & gt; TIM1_CR2.MMS: Master Mode Selection
// & lt; i & gt; Default: Reset
// & lt; i & gt; Select information to be sent in master mode to slave timers for synchronisation
// & lt; 0= & gt; Reset
// & lt; 1= & gt; Enable
// & lt; 2= & gt; Update
// & lt; 3= & gt; Compare Pulse
// & lt; 4= & gt; Compare OC1REF iused as TRGO
// & lt; 5= & gt; Compare OC2REF iused as TRGO
// & lt; 6= & gt; Compare OC3REF iused as TRGO
// & lt; 7= & gt; Compare OC4REF iused as TRGO
// & lt; o9.2 & gt; TIM1_CR2.CCUS: Capture/Compare Control Update Selection
// & lt; i & gt; Default: setting COM bit
// & lt; 0= & gt; setting COM bit
// & lt; 1= & gt; setting COM bit or rising edge TRGI
// & lt; o9.0 & gt; TIM1_CR2.CCPC: Capture/Compare Preloaded Control
// & lt; i & gt; Default: CCxE,CCxNE,OCxM not preloaded
// & lt; 0= & gt; CCxE,CCxNE,OCxM not preloaded
// & lt; 1= & gt; CCxE,CCxNE,OCxM preloaded
// & lt; /h & gt;
//
// & lt; h & gt; Timer 1 Slave mode control register Configuration (TIM1_SMC)
// & lt; o10.15 & gt; TIM1_SMCR.ETP: External trigger polarity
// & lt; i & gt; Default: ETR is non-inverted
// & lt; 0= & gt; ETR is non-inverted
// & lt; 1= & gt; ETR is inverted
// & lt; o10.14 & gt; TIM1_SMCR.ECE: External clock mode 2 enabled
// & lt; o10.12..13 & gt; TIM1_SMCR.ETPS: External trigger prescaler
// & lt; i & gt; Default: Prescaler OFF
// & lt; 0= & gt; Prescaler OFF
// & lt; 1= & gt; fETPR/2
// & lt; 2= & gt; fETPR/4
// & lt; 3= & gt; fETPR/8
// & lt; o10.8..11 & gt; TIM1_SMCR.ETF: External trigger filter
// & lt; i & gt; Default: No filter
// & lt; 0= & gt; No filter
// & lt; 1= & gt; fSampling=fCK_INT, N=2
// & lt; 2= & gt; fSampling=fCK_INT, N=4
// & lt; 3= & gt; fSampling=fCK_INT, N=8
// & lt; 4= & gt; fSampling=fDTS/2, N=6
// & lt; 5= & gt; fSampling=fDTS/2, N=8
// & lt; 6= & gt; fSampling=fDTS/4, N=6
// & lt; 7= & gt; fSampling=fDTS/4, N=8
// & lt; 8= & gt; fSampling=fDTS/8, N=6
// & lt; 9= & gt; fSampling=fDTS/8, N=8
// & lt; 10= & gt; fSampling=fDTS/16, N=5
// & lt; 11= & gt; fSampling=fDTS/16, N=6
// & lt; 12= & gt; fSampling=fDTS/16, N=8
// & lt; 13= & gt; fSampling=fDTS/32, N=5
// & lt; 14= & gt; fSampling=fDTS/32, N=6
// & lt; 15= & gt; fSampling=fDTS/32, N=8
// & lt; o10.7 & gt; TIM1_SMCR.MSM: Delay trigger input
// & lt; o10.4..6 & gt; TIM1_SMCR.TS: Trigger Selection
// & lt; i & gt; Default: Reserved
// & lt; 0= & gt; Reserved
// & lt; 1= & gt; TIM2 (ITR1)
// & lt; 2= & gt; TIM3 (ITR2)
// & lt; 3= & gt; TIM4 (ITR3)
// & lt; 4= & gt; TI1 Edge Detector (TI1F_ED)
// & lt; 5= & gt; Filtered Timer Input 1 (TI1FP1)
// & lt; 6= & gt; Filtered Timer Input 2 (TI1FP2)
// & lt; 7= & gt; External Trigger Input (ETRF)
// & lt; o10.0..2 & gt; TIM1_SMCR.SMS: Slave mode selection
// & lt; i & gt; Default: Slave mode disabled
// & lt; 0= & gt; Slave mode disabled
// & lt; 1= & gt; Encoder mode 1
// & lt; 2= & gt; Encoder mode 2
// & lt; 3= & gt; Encoder mode 3
// & lt; 4= & gt; Reset mode
// & lt; 5= & gt; Gated mode
// & lt; 6= & gt; Trigger mode
// & lt; 7= & gt; External clock mode 1
// & lt; /h & gt;
//
//--------------------------------------------------------------------------- Timer 1 channel 1
// & lt; h & gt; Channel 1 Configuration
// & lt; h & gt; Cannel configured as output
// & lt; o11.7 & gt; TIM1_CCMR1.OC1CE: Output Compare 1 Clear enabled
// & lt; o11.4..6 & gt; TIM1_CCMR1.OC1M: Output Compare 1 Mode
// & lt; i & gt; Default: Frozen
// & lt; 0= & gt; Frozen
// & lt; 1= & gt; Set channel 1 to active level on match
// & lt; 2= & gt; Set channel 1 to inactive level on match
// & lt; 3= & gt; Toggle
// & lt; 4= & gt; Force inactive level
// & lt; 5= & gt; Force active level
// & lt; 6= & gt; PWM mode 1
// & lt; 7= & gt; PWM mode 2
// & lt; o11.3 & gt; TIM1_CCMR1.OC1PE: Output Compare 1 Preload enabled
// & lt; o11.2 & gt; TIM1_CCMR1.OC1FE: Output Compare 1 Fast enabled
// & lt; o11.0..1 & gt; TIM1_CCMR1.CC1S: Capture/compare 1 selection
// & lt; i & gt; Default: CC1 configured as output
// & lt; 0= & gt; CC1 configured as output
// & lt; o13.3 & gt; TIM1_CCER.CC1NP: Capture/compare 1 Complementary output Polarity set
// & lt; i & gt; Default: OC1N active high
// & lt; 0= & gt; OC1N active high
// & lt; 1= & gt; OC1N active low
// & lt; o13.2 & gt; TIM1_CCER.CC1NE: Capture/compare 1 Complementary output enabled
// & lt; i & gt; Default: OC1N not active
// & lt; 0= & gt; OC1N not active
// & lt; 1= & gt; OC1N is output on corresponding pin
// & lt; o13.1 & gt; TIM1_CCER.CC1P: Capture/compare 1 output Polarity set
// & lt; i & gt; Default: OC1 active high
// & lt; 0= & gt; OC1 active high
// & lt; 1= & gt; OC1 active low
// & lt; o13.0 & gt; TIM1_CCER.CC1E: Capture/compare 1 output enabled
// & lt; i & gt; Default: OC1 not active
// & lt; 0= & gt; OC1 not active
// & lt; 1= & gt; OC1 is output on corresponding pin
// & lt; /h & gt;
// & lt; h & gt; Channel configured as input
// & lt; o11.4..7 & gt; TIM1_CCMR1.IC1F: Input Capture 1 Filter
// & lt; i & gt; Default: No filter
// & lt; 0= & gt; No filter
// & lt; 1= & gt; fSampling=fCK_INT, N=2
// & lt; 2= & gt; fSampling=fCK_INT, N=4
// & lt; 3= & gt; fSampling=fCK_INT, N=8
// & lt; 4= & gt; fSampling=fDTS/2, N=6
// & lt; 5= & gt; fSampling=fDTS/2, N=8
// & lt; 6= & gt; fSampling=fDTS/4, N=6
// & lt; 7= & gt; fSampling=fDTS/4, N=8
// & lt; 8= & gt; fSampling=fDTS/8, N=6
// & lt; 9= & gt; fSampling=fDTS/8, N=8
// & lt; 10= & gt; fSampling=fDTS/16, N=5
// & lt; 11= & gt; fSampling=fDTS/16, N=6
// & lt; 12= & gt; fSampling=fDTS/16, N=8
// & lt; 13= & gt; fSampling=fDTS/32, N=5
// & lt; 14= & gt; fSampling=fDTS/32, N=6
// & lt; 15= & gt; fSampling=fDTS/32, N=8
// & lt; o11.2..3 & gt; TIM1_CCMR1.IC1PSC: Input Capture 1 Prescaler
// & lt; i & gt; Default: No prescaler
// & lt; 0= & gt; No prescaler
// & lt; 1= & gt; capture every 2 events
// & lt; 2= & gt; capture every 4 events
// & lt; 3= & gt; capture every 8 events
// & lt; o11.0..1 & gt; TIM1_CCMR1.CC1S: Capture/compare 1 selection
// & lt; i & gt; Default: CC1 configured as output
// & lt; 0= & gt; CC1 configured as output
// & lt; 1= & gt; CC1 configured as input, IC1 mapped on TI1
// & lt; 2= & gt; CC1 configured as input, IC1 mapped on TI2
// & lt; 3= & gt; CC1 configured as input, IC1 mapped on TRGI
// & lt; o13.1 & gt; TIM1_CCER.CC1P: Capture/compare 1 output Polarity set
// & lt; i & gt; Default: non-inverted
// & lt; 0= & gt; non-inverted
// & lt; 1= & gt; inverted
// & lt; o13.0 & gt; TIM1_CCER.CC1E: Capture/compare 1 output enabled
// & lt; i & gt; Default: Capture disabled
// & lt; 0= & gt; Capture disabled
// & lt; 1= & gt; Capture enabled
// & lt; /h & gt;
// & lt; o14 & gt; TIM1_CCR1: Capture/compare register 1 & lt; 0-65535 & gt;
// & lt; i & gt; Set the Compare register value for compare register 1.
// & lt; i & gt; Default: 0
// & lt; /h & gt;
//
//--------------------------------------------------------------------------- Timer 1 channel 2
// & lt; h & gt; Channel 2 Configuration
// & lt; h & gt; Cannel configured as output
// & lt; o11.15 & gt; TIM1_CCMR1.OC2CE: Output Compare 2 Clear enabled
// & lt; o11.12..14 & gt; TIM1_CCMR1.OC2M: Output Compare 2 Mode
// & lt; i & gt; Default: Frozen
// & lt; 0= & gt; Frozen
// & lt; 1= & gt; Set channel 2 to active level on match
// & lt; 2= & gt; Set channel 2 to inactive level on match
// & lt; 3= & gt; Toggle
// & lt; 4= & gt; Force inactive level
// & lt; 5= & gt; Force active level
// & lt; 6= & gt; PWM mode 1
// & lt; 7= & gt; PWM mode 2
// & lt; o11.11 & gt; TIM1_CCMR1.OC2PE: Output Compare 2 Preload enabled
// & lt; o11.10 & gt; TIM1_CCMR1.OC2FE: Output Compare 2 Fast enabled
// & lt; o11.8..9 & gt; TIM1_CCMR1.CC2S: Capture/compare 2 selection
// & lt; i & gt; Default: CC2 configured as output
// & lt; 0= & gt; CC2 configured as output
// & lt; o13.7 & gt; TIM1_CCER.CC2NP: Capture/compare 2 Complementary output Polarity set
// & lt; i & gt; Default: OC2N active high
// & lt; 0= & gt; OC2N active high
// & lt; 1= & gt; OC2N active low
// & lt; o13.6 & gt; TIM1_CCER.CC2NE: Capture/compare 2 Complementary output enabled
// & lt; i & gt; Default: OC2N not active
// & lt; 0= & gt; OC2N not active
// & lt; 1= & gt; OC2N is output on corresponding pin
// & lt; o13.5 & gt; TIM1_CCER.CC2P: Capture/compare 2 output Polarity set
// & lt; i & gt; Default: OC2 active high
// & lt; 0= & gt; OC2 active high
// & lt; 1= & gt; OC2 active low
// & lt; o13.4 & gt; TIM1_CCER.CC2E: Capture/compare 2 output enabled
// & lt; i & gt; Default: OC2 not active
// & lt; 0= & gt; OC2 not active
// & lt; 1= & gt; OC2 is output on corresponding pin
// & lt; /h & gt;
// & lt; h & gt; Channel configured as input
// & lt; o11.12..15 & gt; TIM1_CCMR1.IC2F: Input Capture 2 Filter
// & lt; i & gt; Default: No filter
// & lt; 0= & gt; No filter
// & lt; 1= & gt; fSampling=fCK_INT, N=2
// & lt; 2= & gt; fSampling=fCK_INT, N=4
// & lt; 3= & gt; fSampling=fCK_INT, N=8
// & lt; 4= & gt; fSampling=fDTS/2, N=6
// & lt; 5= & gt; fSampling=fDTS/2, N=8
// & lt; 6= & gt; fSampling=fDTS/4, N=6
// & lt; 7= & gt; fSampling=fDTS/4, N=8
// & lt; 8= & gt; fSampling=fDTS/8, N=6
// & lt; 9= & gt; fSampling=fDTS/8, N=8
// & lt; 10= & gt; fSampling=fDTS/16, N=5
// & lt; 11= & gt; fSampling=fDTS/16, N=6
// & lt; 12= & gt; fSampling=fDTS/16, N=8
// & lt; 13= & gt; fSampling=fDTS/32, N=5
// & lt; 14= & gt; fSampling=fDTS/32, N=6
// & lt; 15= & gt; fSampling=fDTS/32, N=8
// & lt; o11.10..11 & gt; TIM1_CCMR1.IC2PSC: Input Capture 2 Prescaler
// & lt; i & gt; Default: No prescaler
// & lt; 0= & gt; No prescaler
// & lt; 1= & gt; capture every 2 events
// & lt; 2= & gt; capture every 4 events
// & lt; 3= & gt; capture every 8 events
// & lt; o11.8..9 & gt; TIM1_CCMR1.CC2S: Capture/compare 2 selection
// & lt; i & gt; Default: CC2 configured as output
// & lt; 0= & gt; CC2 configured as output
// & lt; 1= & gt; CC2 configured as input, IC2 mapped on TI1
// & lt; 2= & gt; CC2 configured as input, IC2 mapped on TI2
// & lt; 3= & gt; CC2 configured as input, IC2 mapped on TRGI
// & lt; o13.5 & gt; TIM1_CCER.CC2P: Capture/compare 2 output Polarity set
// & lt; i & gt; Default: non-inverted
// & lt; 0= & gt; non-inverted
// & lt; 1= & gt; inverted
// & lt; o13.4 & gt; TIM1_CCER.CC2E: Capture/compare 2 output enabled
// & lt; i & gt; Default: Capture disabled
// & lt; 0= & gt; Capture disabled
// & lt; 1= & gt; Capture enabled
// & lt; /h & gt;
// & lt; o15 & gt; TIM1_CCR2: Capture/compare register 2 & lt; 0-65535 & gt;
// & lt; i & gt; Set the Compare register value for compare register 2.
// & lt; i & gt; Default: 0
// & lt; /h & gt;
//
//--------------------------------------------------------------------------- Timer 1 channel 3
// & lt; h & gt; Channel 3 Configuration
// & lt; h & gt; Cannel configured as output
// & lt; o12.7 & gt; TIM1_CCMR2.OC3CE: Output Compare 3 Clear enabled
// & lt; o12.4..6 & gt; TIM1_CCMR2.OC3M: Output Compare 3 Mode
// & lt; i & gt; Default: Frozen
// & lt; 0= & gt; Frozen
// & lt; 1= & gt; Set channel 3 to active level on match
// & lt; 2= & gt; Set channel 3 to inactive level on match
// & lt; 3= & gt; Toggle
// & lt; 4= & gt; Force inactive level
// & lt; 5= & gt; Force active level
// & lt; 6= & gt; PWM mode 1
// & lt; 7= & gt; PWM mode 2
// & lt; o12.3 & gt; TIM1_CCMR2.OC3PE: Output Compare 3 Preload enabled
// & lt; o12.2 & gt; TIM1_CCMR2.OC3FE: Output Compare 3 Fast enabled
// & lt; o12.0..1 & gt; TIM1_CCMR2.CC3S: Capture/compare 3 selection
// & lt; i & gt; Default: CC3 configured as output
// & lt; 0= & gt; CC3 configured as output
// & lt; o13.11 & gt; TIM1_CCER.CC3NP: Capture/compare 3 Complementary output Polarity set
// & lt; i & gt; Default: OC3N active high
// & lt; 0= & gt; OC3N active high
// & lt; 1= & gt; OC3N active low
// & lt; o13.10 & gt; TIM1_CCER.CC3NE: Capture/compare 3 Complementary output enabled
// & lt; i & gt; Default: OC3N not active
// & lt; 0= & gt; OC3N not active
// & lt; 1= & gt; OC3N is output on corresponding pin
// & lt; o13.9 & gt; TIM1_CCER.CC3P: Capture/compare 3 output Polarity set
// & lt; i & gt; Default: OC3 active high
// & lt; 0= & gt; OC3 active high
// & lt; 1= & gt; OC3 active low
// & lt; o13.8 & gt; TIM1_CCER.CC3E: Capture/compare 3 output enabled
// & lt; i & gt; Default: OC3 not active
// & lt; 0= & gt; OC3 not active
// & lt; 1= & gt; OC3 is output on corresponding pin
// & lt; /h & gt;
// & lt; h & gt; Channel configured as input
// & lt; o12.4..7 & gt; TIM1_CCMR2.IC3F: Input Capture 3 Filter
// & lt; i & gt; Default: No filter
// & lt; 0= & gt; No filter
// & lt; 1= & gt; fSampling=fCK_INT, N=2
// & lt; 2= & gt; fSampling=fCK_INT, N=4
// & lt; 3= & gt; fSampling=fCK_INT, N=8
// & lt; 4= & gt; fSampling=fDTS/2, N=6
// & lt; 5= & gt; fSampling=fDTS/2, N=8
// & lt; 6= & gt; fSampling=fDTS/4, N=6
// & lt; 7= & gt; fSampling=fDTS/4, N=8
// & lt; 8= & gt; fSampling=fDTS/8, N=6
// & lt; 9= & gt; fSampling=fDTS/8, N=8
// & lt; 10= & gt; fSampling=fDTS/16, N=5
// & lt; 11= & gt; fSampling=fDTS/16, N=6
// & lt; 12= & gt; fSampling=fDTS/16, N=8
// & lt; 13= & gt; fSampling=fDTS/32, N=5
// & lt; 14= & gt; fSampling=fDTS/32, N=6
// & lt; 15= & gt; fSampling=fDTS/32, N=8
// & lt; o12.2..3 & gt; TIM1_CCMR2.IC3PSC: Input Capture 3 Prescaler
// & lt; i & gt; Default: No prescaler
// & lt; 0= & gt; No prescaler
// & lt; 1= & gt; capture every 2 events
// & lt; 2= & gt; capture every 4 events
// & lt; 3= & gt; capture every 8 events
// & lt; o12.0..1 & gt; TIM1_CCMR2.CC3S: Capture/compare 3 selection
// & lt; i & gt; Default: CC3 configured as output
// & lt; 0= & gt; CC3 configured as output
// & lt; 1= & gt; CC3 configured as input, IC3 mapped on TI1
// & lt; 2= & gt; CC3 configured as input, IC3 mapped on TI2
// & lt; 3= & gt; CC3 configured as input, IC3 mapped on TRGI
// & lt; o13.9 & gt; TIM1_CCER.CC3P: Capture/compare 3 output Polarity set
// & lt; i & gt; Default: non-inverted
// & lt; 0= & gt; non-inverted
// & lt; 1= & gt; inverted
// & lt; o13.8 & gt; TIM1_CCER.CC3E: Capture/compare 3 output enabled
// & lt; i & gt; Default: Capture disabled
// & lt; 0= & gt; Capture disabled
// & lt; 1= & gt; Capture enabled
// & lt; /h & gt;
// & lt; o16 & gt; TIM1_CCR3: Capture/compare register 3 & lt; 0-65535 & gt;
// & lt; i & gt; Set the Compare register value for compare register 3.
// & lt; i & gt; Default: 0
// & lt; /h & gt;
//
//--------------------------------------------------------------------------- Timer 1 channel 4
// & lt; h & gt; Channel 4 Configuration
// & lt; h & gt; Cannel configured as output
// & lt; o12.15 & gt; TIM1_CCMR2.OC4CE: Output Compare 4 Clear enabled
// & lt; o12.12..14 & gt; TIM1_CCMR2.OC4M: Output Compare 4 Mode
// & lt; i & gt; Default: Frozen
// & lt; 0= & gt; Frozen
// & lt; 1= & gt; Set channel 4 to active level on match
// & lt; 2= & gt; Set channel 4 to inactive level on match
// & lt; 3= & gt; Toggle
// & lt; 4= & gt; Force inactive level
// & lt; 5= & gt; Force active level
// & lt; 6= & gt; PWM mode 1
// & lt; 7= & gt; PWM mode 2
// & lt; o12.11 & gt; TIM1_CCMR2.OC4PE: Output Compare 4 Preload enabled
// & lt; o12.10 & gt; TIM1_CCMR2.OC4FE: Output Compare 4 Fast enabled
// & lt; o12.8..9 & gt; TIM1_CCMR2.CC4S: Capture/compare 4 selection
// & lt; i & gt; Default: CC4 configured as output
// & lt; 0= & gt; CC4 configured as output
// & lt; o13.13 & gt; TIM1_CCER.CC4P: Capture/compare 4 output Polarity set
// & lt; i & gt; Default: OC4 active high
// & lt; 0= & gt; OC4 active high
// & lt; 1= & gt; OC4 active low
// & lt; o13.12 & gt; TIM1_CCER.CC4E: Capture/compare 4 output enabled
// & lt; i & gt; Default: OC4 not active
// & lt; 0= & gt; OC4 not active
// & lt; 1= & gt; OC4 is output on corresponding pin
// & lt; /h & gt;
// & lt; h & gt; Channel configured as input
// & lt; o12.12..15 & gt; TIM1_CCMR2.IC4F: Input Capture 4 Filter
// & lt; i & gt; Default: No filter
// & lt; 0= & gt; No filter
// & lt; 1= & gt; fSampling=fCK_INT, N=2
// & lt; 2= & gt; fSampling=fCK_INT, N=4
// & lt; 3= & gt; fSampling=fCK_INT, N=8
// & lt; 4= & gt; fSampling=fDTS/2, N=6
// & lt; 5= & gt; fSampling=fDTS/2, N=8
// & lt; 6= & gt; fSampling=fDTS/4, N=6
// & lt; 7= & gt; fSampling=fDTS/4, N=8
// & lt; 8= & gt; fSampling=fDTS/8, N=6
// & lt; 9= & gt; fSampling=fDTS/8, N=8
// & lt; 10= & gt; fSampling=fDTS/16, N=5
// & lt; 11= & gt; fSampling=fDTS/16, N=6
// & lt; 12= & gt; fSampling=fDTS/16, N=8
// & lt; 13= & gt; fSampling=fDTS/32, N=5
// & lt; 14= & gt; fSampling=fDTS/32, N=6
// & lt; 15= & gt; fSampling=fDTS/32, N=8
// & lt; o12.10..11 & gt; TIM1_CCMR2.IC4PSC: Input Capture 4 Prescaler
// & lt; i & gt; Default: No prescaler
// & lt; 0= & gt; No prescaler
// & lt; 1= & gt; capture every 2 events
// & lt; 2= & gt; capture every 4 events
// & lt; 3= & gt; capture every 8 events
// & lt; o12.8..9 & gt; TIM1_CCMR2.CC4S: Capture/compare 4 selection
// & lt; i & gt; Default: CC4 configured as output
// & lt; 0= & gt; CC4 configured as output
// & lt; 1= & gt; CC4 configured as input, IC4 mapped on TI1
// & lt; 2= & gt; CC4 configured as input, IC4 mapped on TI2
// & lt; 3= & gt; CC4 configured as input, IC4 mapped on TRGI
// & lt; o13.13 & gt; TIM1_CCER.CC4P: Capture/compare 4 output Polarity set
// & lt; i & gt; Default: non-inverted
// & lt; 0= & gt; non-inverted
// & lt; 1= & gt; inverted
// & lt; o13.12 & gt; TIM1_CCER.CC4E: Capture/compare 4 output enabled
// & lt; i & gt; Default: Capture disabled
// & lt; 0= & gt; Capture disabled
// & lt; 1= & gt; Capture enabled
// & lt; /h & gt;
// & lt; o17 & gt; TIM1_CCR4: Capture/compare register 4 & lt; 0-65535 & gt;
// & lt; i & gt; Set the Compare register value for compare register 4.
// & lt; i & gt; Default: 0
// & lt; /h & gt;
//
// & lt; h & gt; Timer1 Break and dead-time register Configuration (TIM1_BDTR)
// & lt; o18.15 & gt; TIM1_BDTR.MOE: Main Output enabled
// & lt; o18.14 & gt; TIM1_BDTR.AOE: Automatic Output enabled
// & lt; o18.13 & gt; TIM1_BDTR.BKP: Break Polarity active high
// & lt; o18.12 & gt; TIM1_BDTR.BKE: Break Inputs enabled
// & lt; o18.11 & gt; TIM1_BDTR.OSSR: Off-State Selection for Run mode
// & lt; i & gt; Default: OC/OCN output signal=0
// & lt; 0= & gt; OC/OCN output signal=0
// & lt; 1= & gt; OC/OCN output signal=1
// & lt; o18.10 & gt; TIM1_BDTR.OSSI: Off-State Selection for Idle mode
// & lt; i & gt; Default: OC/OCN output signal=0
// & lt; 0= & gt; OC/OCN output signal=0
// & lt; 1= & gt; OC/OCN output signal=1
// & lt; o18.8..9 & gt; TIM1_BDTR.LOCK: Lock Level & lt; 0-3 & gt;
// & lt; i & gt; Default: 0 (LOCK OFF)
// & lt; o18.0..7 & gt; TIM1_BDTR.DTG: Dead-Time Generator set-up & lt; 0x00-0xFF & gt;
// & lt; /h & gt;
//
// & lt; /e & gt;
// & lt; e3.0 & gt; TIM1 interrupts
// & lt; o19.14 & gt; TIM1_DIER.TDE: Trigger DMA request enabled
// & lt; o19.12 & gt; TIM1_DIER.CC4DE: Capture/Compare 4 DMA request enabled
// & lt; o19.11 & gt; TIM1_DIER.CC3DE: Capture/Compare 3 DMA request enabled
// & lt; o19.10 & gt; TIM1_DIER.CC2DE: Capture/Compare 2 DMA request enabled
// & lt; o19.9 & gt; TIM1_DIER.CC1DE: Capture/Compare 1 DMA request enabled
// & lt; o19.8 & gt; TIM1_DIER.UDE: Update DMA request enabled
// & lt; o19.7 & gt; TIM1_DIER.BIE: Break interrupt enabled
// & lt; o19.6 & gt; TIM1_DIER.TIE: Trigger interrupt enabled
// & lt; o19.5 & gt; TIM1_DIER.COMIE: COM interrupt enabled
// & lt; o19.4 & gt; TIM1_DIER.CC4IE: Capture/Compare 4 interrupt enabled
// & lt; o19.3 & gt; TIM1_DIER.CC3IE: Capture/Compare 3 interrupt enabled
// & lt; o19.2 & gt; TIM1_DIER.CC2IE: Capture/Compare 2 interrupt enabled
// & lt; o19.1 & gt; TIM1_DIER.CC1IE: Capture/Compare 1 interrupt enabled
// & lt; o19.0 & gt; TIM1_DIER.UIE: Update interrupt enabled
// & lt; /e & gt;
// & lt; /e & gt;
//--------------------------------------------------------------------------- Timer 2 enabled
// & lt; e1.1 & gt; TIM2 : Timer 2 enabled
// & lt; o20 & gt; TIM2 period [us] & lt; 1-72000000:10 & gt;
// & lt; i & gt; Set the timer period for Timer 2.
// & lt; i & gt; Default: 1000 (1ms)
// & lt; i & gt; Ignored if Detailed settings is selected
// & lt; e2.1 & gt; TIM2 detailed settings
//--------------------------------------------------------------------------- Timer 2 detailed settings
// & lt; o21 & gt; TIM2.PSC: Timer 2 Prescaler & lt; 0-65535 & gt;
// & lt; i & gt; Set the prescaler for Timer 2.
// & lt; o22 & gt; TIM2.ARR: Timer 2 Auto-reload & lt; 0-65535 & gt;
// & lt; i & gt; Set the Auto-reload for Timer 2.
// & lt; h & gt; Timer 2 Control Register 1 Configuration (TIM2_CR1)
// & lt; o23.8..9 & gt; TIM2_CR1.CKD: Clock division
// & lt; i & gt; Default: tDTS = tCK_INT
// & lt; i & gt; devision ratio between timer clock and dead time
// & lt; 0= & gt; tDTS = tCK_INT
// & lt; 1= & gt; tDTS = 2*tCK_INT
// & lt; 2= & gt; tDTS = 4*tCK_INT
// & lt; o23.7 & gt; TIM2_CR1.ARPE: Auto-reload preload enable
// & lt; i & gt; Default: Auto-reload preload disenabled
// & lt; o23.5..6 & gt; TIM2_CR1.CMS: Center aligned mode selection
// & lt; i & gt; Default: Edge-aligned
// & lt; 0= & gt; Edge-aligned
// & lt; 1= & gt; Center-aligned mode1
// & lt; 2= & gt; Center-aligned mode2
// & lt; 3= & gt; Center-aligned mode3
// & lt; o23.4 & gt; TIM2_CR1.DIR: Direction
// & lt; i & gt; Default: DIR = Counter used as up-counter
// & lt; i & gt; read only if timer is configured as Center-aligned or Encoder mode
// & lt; 0= & gt; Counter used as up-counter
// & lt; 1= & gt; Counter used as down-counter
// & lt; o23.3 & gt; TIM2_CR1.OPM: One pulse mode enable
// & lt; i & gt; Default: One pulse mode disabled
// & lt; o23.2 & gt; TIM2_CR1.URS: Update request source
// & lt; i & gt; Default: URS = Counter over-/underflow, UG bit, Slave mode controller
// & lt; 0= & gt; Counter over-/underflow, UG bit, Slave mode controller
// & lt; 1= & gt; Counter over-/underflow
// & lt; o23.1 & gt; TIM2_CR1.UDIS: Update disable
// & lt; i & gt; Default: Update enabled
// & lt; /h & gt;
//
// & lt; h & gt; Timer 2 Control Register 2 Configuration (TIM2_CR2)
// & lt; o24.7 & gt; TIM2_CR2.TI1S: TI1 Selection
// & lt; i & gt; Default: TIM2CH1 connected to TI1 input
// & lt; 0= & gt; TIM2CH1 connected to TI1 input
// & lt; 1= & gt; TIM2CH1,CH2,CH3 connected to TI1 input
// & lt; o24.4..6 & gt; TIM2_CR2.MMS: Master Mode Selection
// & lt; i & gt; Default: Reset
// & lt; i & gt; Select information to be sent in master mode to slave timers for synchronisation
// & lt; 0= & gt; Reset
// & lt; 1= & gt; Enable
// & lt; 2= & gt; Update
// & lt; 3= & gt; Compare Pulse
// & lt; 4= & gt; Compare OC1REF iused as TRGO
// & lt; 5= & gt; Compare OC2REF iused as TRGO
// & lt; 6= & gt; Compare OC3REF iused as TRGO
// & lt; 7= & gt; Compare OC4REF iused as TRGO
// & lt; o24.3 & gt; TIM2_CR2.CCDS: Capture/Compare DMA Selection
// & lt; i & gt; Default: CC4 DMA request on CC4 event
// & lt; 0= & gt; CC4 DMA request on CC4 event
// & lt; 1= & gt; CC4 DMA request on update event
// & lt; /h & gt;
//
// & lt; h & gt; Timer 2 Slave mode control register Configuration (TIM2_SMC)
// & lt; o25.15 & gt; TIM2_SMCR.ETP: External trigger polarity
// & lt; i & gt; Default: ETR is non-inverted
// & lt; 0= & gt; ETR is non-inverted
// & lt; 1= & gt; ETR is inverted
// & lt; o25.14 & gt; TIM2_SMCR.ECE: External clock mode 2 enabled
// & lt; o25.12..13 & gt; TIM2_SMCR.ETPS: External trigger prescaler
// & lt; i & gt; Default: Prescaler OFF
// & lt; 0= & gt; Prescaler OFF
// & lt; 1= & gt; fETPR/2
// & lt; 2= & gt; fETPR/4
// & lt; 3= & gt; fETPR/8
// & lt; o25.8..11 & gt; TIM2_SMCR.ETF: External trigger filter
// & lt; i & gt; Default: No filter
// & lt; 0= & gt; No filter
// & lt; 1= & gt; fSampling=fCK_INT, N=2
// & lt; 2= & gt; fSampling=fCK_INT, N=4
// & lt; 3= & gt; fSampling=fCK_INT, N=8
// & lt; 4= & gt; fSampling=fDTS/2, N=6
// & lt; 5= & gt; fSampling=fDTS/2, N=8
// & lt; 6= & gt; fSampling=fDTS/4, N=6
// & lt; 7= & gt; fSampling=fDTS/4, N=8
// & lt; 8= & gt; fSampling=fDTS/8, N=6
// & lt; 9= & gt; fSampling=fDTS/8, N=8
// & lt; 10= & gt; fSampling=fDTS/16, N=5
// & lt; 11= & gt; fSampling=fDTS/16, N=6
// & lt; 12= & gt; fSampling=fDTS/16, N=8
// & lt; 13= & gt; fSampling=fDTS/32, N=5
// & lt; 14= & gt; fSampling=fDTS/32, N=6
// & lt; 15= & gt; fSampling=fDTS/32, N=8
// & lt; o25.7 & gt; TIM2_SMCR.MSM: Delay trigger input
// & lt; o25.4..6 & gt; TIM2_SMCR.TS: Trigger Selection
// & lt; i & gt; Default: Reserved
// & lt; 0= & gt; Reserved
// & lt; 1= & gt; TIM2 (ITR1)
// & lt; 2= & gt; TIM3 (ITR2)
// & lt; 3= & gt; TIM2 (ITR3)
// & lt; 4= & gt; TI1 Edge Detector (TI1F_ED)
// & lt; 5= & gt; Filtered Timer Input 1 (TI1FP1)
// & lt; 6= & gt; Filtered Timer Input 2 (TI1FP2)
// & lt; 7= & gt; External Trigger Input (ETRF)
// & lt; o25.0..2 & gt; TIM2_SMCR.SMS: Slave mode selection
// & lt; i & gt; Default: Slave mode disabled
// & lt; 0= & gt; Slave mode disabled
// & lt; 1= & gt; Encoder mode 1
// & lt; 2= & gt; Encoder mode 2
// & lt; 3= & gt; Encoder mode 3
// & lt; 4= & gt; Reset mode
// & lt; 5= & gt; Gated mode
// & lt; 6= & gt; Trigger mode
// & lt; 7= & gt; External clock mode 1
// & lt; /h & gt;
//
//
//--------------------------------------------------------------------------- Timer 2 channel 1
// & lt; h & gt; Channel 1 Configuration
// & lt; h & gt; Cannel configured as output
// & lt; o26.7 & gt; TIM2_CCMR1.OC1CE: Output Compare 1 Clear enabled
// & lt; o26.4..6 & gt; TIM2_CCMR1.OC1M: Output Compare 1 Mode
// & lt; i & gt; Default: Frozen
// & lt; 0= & gt; Frozen
// & lt; 1= & gt; Set channel 1 to active level on match
// & lt; 2= & gt; Set channel 1 to inactive level on match
// & lt; 3= & gt; Toggle
// & lt; 4= & gt; Force inactive level
// & lt; 5= & gt; Force active level
// & lt; 6= & gt; PWM mode 1
// & lt; 7= & gt; PWM mode 2
// & lt; o26.3 & gt; TIM2_CCMR1.OC1PE: Output Compare 1 Preload enabled
// & lt; o26.2 & gt; TIM2_CCMR1.OC1FE: Output Compare 1 Fast enabled
// & lt; o26.0..1 & gt; TIM2_CCMR1.CC1S: Capture/compare 1 selection
// & lt; i & gt; Default: CC1 configured as output
// & lt; 0= & gt; CC1 configured as output
// & lt; o28.1 & gt; TIM2_CCER.CC1P: Capture/compare 1 output Polarity set
// & lt; i & gt; Default: OC1 active high
// & lt; 0= & gt; OC1 active high
// & lt; 1= & gt; OC1 active low
// & lt; o28.0 & gt; TIM1_CCER.CC1E: Capture/compare 1 output enabled
// & lt; i & gt; Default: OC1 not active
// & lt; 0= & gt; OC1 not active
// & lt; 1= & gt; OC1 is output on corresponding pin
// & lt; /h & gt;
// & lt; h & gt; Channel configured as input
// & lt; o26.4..7 & gt; TIM2_CCMR1.IC1F: Input Capture 1 Filter
// & lt; i & gt; Default: No filter
// & lt; 0= & gt; No filter
// & lt; 1= & gt; fSampling=fCK_INT, N=2
// & lt; 2= & gt; fSampling=fCK_INT, N=4
// & lt; 3= & gt; fSampling=fCK_INT, N=8
// & lt; 4= & gt; fSampling=fDTS/2, N=6
// & lt; 5= & gt; fSampling=fDTS/2, N=8
// & lt; 6= & gt; fSampling=fDTS/4, N=6
// & lt; 7= & gt; fSampling=fDTS/4, N=8
// & lt; 8= & gt; fSampling=fDTS/8, N=6
// & lt; 9= & gt; fSampling=fDTS/8, N=8
// & lt; 10= & gt; fSampling=fDTS/16, N=5
// & lt; 11= & gt; fSampling=fDTS/16, N=6
// & lt; 12= & gt; fSampling=fDTS/16, N=8
// & lt; 13= & gt; fSampling=fDTS/32, N=5
// & lt; 14= & gt; fSampling=fDTS/32, N=6
// & lt; 15= & gt; fSampling=fDTS/32, N=8
// & lt; o26.2..3 & gt; TIM2_CCMR1.IC1PSC: Input Capture 1 Prescaler
// & lt; i & gt; Default: No prescaler
// & lt; 0= & gt; No prescaler
// & lt; 1= & gt; capture every 2 events
// & lt; 2= & gt; capture every 4 events
// & lt; 3= & gt; capture every 8 events
// & lt; o26.0..1 & gt; TIM2_CCMR1.CC1S: Capture/compare 1 selection
// & lt; i & gt; Default: CC1 configured as output
// & lt; 0= & gt; CC1 configured as output
// & lt; 1= & gt; CC1 configured as input, IC1 mapped on TI1
// & lt; 2= & gt; CC1 configured as input, IC1 mapped on TI2
// & lt; 3= & gt; CC1 configured as input, IC1 mapped on TRGI
// & lt; o28.1 & gt; TIM2_CCER.CC1P: Capture/compare 1 output Polarity set
// & lt; i & gt; Default: non-inverted
// & lt; 0= & gt; non-inverted
// & lt; 1= & gt; inverted
// & lt; o28.0 & gt; TIM2_CCER.CC1E: Capture/compare 1 output enabled
// & lt; i & gt; Default: Capture disabled
// & lt; 0= & gt; Capture disabled
// & lt; 1= & gt; Capture enabled
// & lt; /h & gt;
// & lt; o29 & gt; TIM2_CCR1: Capture/compare register 1 & lt; 0-65535 & gt;
// & lt; i & gt; Set the Compare register value for compare register 1.
// & lt; i & gt; Default: 0
// & lt; /h & gt;
//
//--------------------------------------------------------------------------- Timer 2 channel 2
// & lt; h & gt; Channel 2 Configuration
// & lt; h & gt; Cannel configured as output
// & lt; o26.15 & gt; TIM2_CCMR1.OC2CE: Output Compare 2 Clear enabled
// & lt; o26.12..14 & gt; TIM2_CCMR1.OC2M: Output Compare 2 Mode
// & lt; i & gt; Default: Frozen
// & lt; 0= & gt; Frozen
// & lt; 1= & gt; Set channel 2 to active level on match
// & lt; 2= & gt; Set channel 2 to inactive level on match
// & lt; 3= & gt; Toggle
// & lt; 4= & gt; Force inactive level
// & lt; 5= & gt; Force active level
// & lt; 6= & gt; PWM mode 1
// & lt; 7= & gt; PWM mode 2
// & lt; o26.11 & gt; TIM2_CCMR1.OC2PE: Output Compare 2 Preload enabled
// & lt; o26.10 & gt; TIM2_CCMR1.OC2FE: Output Compare 2 Fast enabled
// & lt; o26.8..9 & gt; TIM2_CCMR1.CC2S: Capture/compare 2 selection
// & lt; i & gt; Default: CC2 configured as output
// & lt; 0= & gt; CC2 configured as output
// & lt; o28.5 & gt; TIM2_CCER.CC2P: Capture/compare 2 output Polarity set
// & lt; i & gt; Default: OC2 active high
// & lt; 0= & gt; OC2 active high
// & lt; 1= & gt; OC2 active low
// & lt; o28.4 & gt; TIM2_CCER.CC2E: Capture/compare 2 output enabled
// & lt; i & gt; Default: OC2 not active
// & lt; 0= & gt; OC2 not active
// & lt; 1= & gt; OC2 is output on corresponding pin
// & lt; /h & gt;
// & lt; h & gt; Channel configured as input
// & lt; o26.12..15 & gt; TIM2_CCMR1.IC2F: Input Capture 2 Filter
// & lt; i & gt; Default: No filter
// & lt; 0= & gt; No filter
// & lt; 1= & gt; fSampling=fCK_INT, N=2
// & lt; 2= & gt; fSampling=fCK_INT, N=4
// & lt; 3= & gt; fSampling=fCK_INT, N=8
// & lt; 4= & gt; fSampling=fDTS/2, N=6
// & lt; 5= & gt; fSampling=fDTS/2, N=8
// & lt; 6= & gt; fSampling=fDTS/4, N=6
// & lt; 7= & gt; fSampling=fDTS/4, N=8
// & lt; 8= & gt; fSampling=fDTS/8, N=6
// & lt; 9= & gt; fSampling=fDTS/8, N=8
// & lt; 10= & gt; fSampling=fDTS/16, N=5
// & lt; 11= & gt; fSampling=fDTS/16, N=6
// & lt; 12= & gt; fSampling=fDTS/16, N=8
// & lt; 13= & gt; fSampling=fDTS/32, N=5
// & lt; 14= & gt; fSampling=fDTS/32, N=6
// & lt; 15= & gt; fSampling=fDTS/32, N=8
// & lt; o26.10..11 & gt; TIM2_CCMR1.IC2PSC: Input Capture 2 Prescaler
// & lt; i & gt; Default: No prescaler
// & lt; 0= & gt; No prescaler
// & lt; 1= & gt; capture every 2 events
// & lt; 2= & gt; capture every 4 events
// & lt; 3= & gt; capture every 8 events
// & lt; o26.8..9 & gt; TIM2_CCMR1.CC2S: Capture/compare 2 selection
// & lt; i & gt; Default: CC2 configured as output
// & lt; 0= & gt; CC2 configured as output
// & lt; 1= & gt; CC2 configured as input, IC2 mapped on TI1
// & lt; 2= & gt; CC2 configured as input, IC2 mapped on TI2
// & lt; 3= & gt; CC2 configured as input, IC2 mapped on TRGI
// & lt; o28.5 & gt; TIM2_CCER.CC2P: Capture/compare 2 output Polarity set
// & lt; i & gt; Default: non-inverted
// & lt; 0= & gt; non-inverted
// & lt; 1= & gt; inverted
// & lt; o28.4 & gt; TIM2_CCER.CC2E: Capture/compare 2 output enabled
// & lt; i & gt; Default: Capture disabled
// & lt; 0= & gt; Capture disabled
// & lt; 1= & gt; Capture enabled
// & lt; /h & gt;
// & lt; o30 & gt; TIM2_CCR2: Capture/compare register 2 & lt; 0-65535 & gt;
// & lt; i & gt; Set the Compare register value for compare register 2.
// & lt; i & gt; Default: 0
// & lt; /h & gt;
//
//--------------------------------------------------------------------------- Timer 2 channel 3
// & lt; h & gt; Channel 3 Configuration
// & lt; h & gt; Cannel configured as output
// & lt; o27.7 & gt; TIM2_CCMR2.OC3CE: Output Compare 3 Clear enabled
// & lt; o27.4..6 & gt; TIM2_CCMR2.OC3M: Output Compare 3 Mode
// & lt; i & gt; Default: Frozen
// & lt; 0= & gt; Frozen
// & lt; 1= & gt; Set channel 3 to active level on match
// & lt; 2= & gt; Set channel 3 to inactive level on match
// & lt; 3= & gt; Toggle
// & lt; 4= & gt; Force inactive level
// & lt; 5= & gt; Force active level
// & lt; 6= & gt; PWM mode 1
// & lt; 7= & gt; PWM mode 2
// & lt; o27.3 & gt; TIM2_CCMR2.OC3PE: Output Compare 3 Preload enabled
// & lt; o27.2 & gt; TIM2_CCMR2.OC3FE: Output Compare 3 Fast enabled
// & lt; o27.0..1 & gt; TIM2_CCMR2.CC3S: Capture/compare 3 selection
// & lt; i & gt; Default: CC3 configured as output
// & lt; 0= & gt; CC3 configured as output
// & lt; o28.9 & gt; TIM2_CCER.CC3P: Capture/compare 3 output Polarity set
// & lt; i & gt; Default: OC3 active high
// & lt; 0= & gt; OC3 active high
// & lt; 1= & gt; OC3 active low
// & lt; o28.8 & gt; TIM2_CCER.CC3E: Capture/compare 3 output enabled
// & lt; i & gt; Default: OC3 not active
// & lt; 0= & gt; OC3 not active
// & lt; 1= & gt; OC3 is output on corresponding pin
// & lt; /h & gt;
// & lt; h & gt; Channel configured as input
// & lt; o27.4..7 & gt; TIM2_CCMR2.IC3F: Input Capture 3 Filter
// & lt; i & gt; Default: No filter
// & lt; 0= & gt; No filter
// & lt; 1= & gt; fSampling=fCK_INT, N=2
// & lt; 2= & gt; fSampling=fCK_INT, N=4
// & lt; 3= & gt; fSampling=fCK_INT, N=8
// & lt; 4= & gt; fSampling=fDTS/2, N=6
// & lt; 5= & gt; fSampling=fDTS/2, N=8
// & lt; 6= & gt; fSampling=fDTS/4, N=6
// & lt; 7= & gt; fSampling=fDTS/4, N=8
// & lt; 8= & gt; fSampling=fDTS/8, N=6
// & lt; 9= & gt; fSampling=fDTS/8, N=8
// & lt; 10= & gt; fSampling=fDTS/16, N=5
// & lt; 11= & gt; fSampling=fDTS/16, N=6
// & lt; 12= & gt; fSampling=fDTS/16, N=8
// & lt; 13= & gt; fSampling=fDTS/32, N=5
// & lt; 14= & gt; fSampling=fDTS/32, N=6
// & lt; 15= & gt; fSampling=fDTS/32, N=8
// & lt; o27.2..3 & gt; TIM2_CCMR2.IC3PSC: Input Capture 3 Prescaler
// & lt; i & gt; Default: No prescaler
// & lt; 0= & gt; No prescaler
// & lt; 1= & gt; capture every 2 events
// & lt; 2= & gt; capture every 4 events
// & lt; 3= & gt; capture every 8 events
// & lt; o27.0..1 & gt; TIM2_CCMR2.CC3S: Capture/compare 3 selection
// & lt; i & gt; Default: CC3 configured as output
// & lt; 0= & gt; CC3 configured as output
// & lt; 1= & gt; CC3 configured as input, IC3 mapped on TI1
// & lt; 2= & gt; CC3 configured as input, IC3 mapped on TI2
// & lt; 3= & gt; CC3 configured as input, IC3 mapped on TRGI
// & lt; o28.9 & gt; TIM2_CCER.CC3P: Capture/compare 3 output Polarity set
// & lt; i & gt; Default: non-inverted
// & lt; 0= & gt; non-inverted
// & lt; 1= & gt; inverted
// & lt; o28.8 & gt; TIM2_CCER.CC3E: Capture/compare 3 output enabled
// & lt; i & gt; Default: Capture disabled
// & lt; 0= & gt; Capture disabled
// & lt; 1= & gt; Capture enabled
// & lt; /h & gt;
// & lt; o31 & gt; TIM2_CCR3: Capture/compare register 3 & lt; 0-65535 & gt;
// & lt; i & gt; Set the Compare register value for compare register 3.
// & lt; i & gt; Default: 0
// & lt; /h & gt;
//
//--------------------------------------------------------------------------- Timer 2 channel 4
// & lt; h & gt; Channel 4 Configuration
// & lt; h & gt; Cannel configured as output
// & lt; o27.15 & gt; TIM2_CCMR2.OC4CE: Output Compare 4 Clear enabled
// & lt; o27.12..14 & gt; TIM2_CCMR2.OC4M: Output Compare 4 Mode
// & lt; i & gt; Default: Frozen
// & lt; 0= & gt; Frozen
// & lt; 1= & gt; Set channel 4 to active level on match
// & lt; 2= & gt; Set channel 4 to inactive level on match
// & lt; 3= & gt; Toggle
// & lt; 4= & gt; Force inactive level
// & lt; 5= & gt; Force active level
// & lt; 6= & gt; PWM mode 1
// & lt; 7= & gt; PWM mode 2
// & lt; o27.11 & gt; TIM2_CCMR2.OC4PE: Output Compare 4 Preload enabled
// & lt; o27.10 & gt; TIM2_CCMR2.OC4FE: Output Compare 4 Fast enabled
// & lt; o27.8..9 & gt; TIM2_CCMR2.CC4S: Capture/compare 4 selection
// & lt; i & gt; Default: CC4 configured as output
// & lt; 0= & gt; CC4 configured as output
// & lt; o28.13 & gt; TIM2_CCER.CC4P: Capture/compare 4 output Polarity set
// & lt; i & gt; Default: OC4 active high
// & lt; 0= & gt; OC4 active high
// & lt; 1= & gt; OC4 active low
// & lt; o28.12 & gt; TIM2_CCER.CC4E: Capture/compare 4 output enabled
// & lt; i & gt; Default: OC4 not active
// & lt; 0= & gt; OC4 not active
// & lt; 1= & gt; OC4 is output on corresponding pin
// & lt; /h & gt;
// & lt; h & gt; Channel configured as input
// & lt; o27.12..15 & gt; TIM2_CCMR2.IC4F: Input Capture 4 Filter
// & lt; i & gt; Default: No filter
// & lt; 0= & gt; No filter
// & lt; 1= & gt; fSampling=fCK_INT, N=2
// & lt; 2= & gt; fSampling=fCK_INT, N=4
// & lt; 3= & gt; fSampling=fCK_INT, N=8
// & lt; 4= & gt; fSampling=fDTS/2, N=6
// & lt; 5= & gt; fSampling=fDTS/2, N=8
// & lt; 6= & gt; fSampling=fDTS/4, N=6
// & lt; 7= & gt; fSampling=fDTS/4, N=8
// & lt; 8= & gt; fSampling=fDTS/8, N=6
// & lt; 9= & gt; fSampling=fDTS/8, N=8
// & lt; 10= & gt; fSampling=fDTS/16, N=5
// & lt; 11= & gt; fSampling=fDTS/16, N=6
// & lt; 12= & gt; fSampling=fDTS/16, N=8
// & lt; 13= & gt; fSampling=fDTS/32, N=5
// & lt; 14= & gt; fSampling=fDTS/32, N=6
// & lt; 15= & gt; fSampling=fDTS/32, N=8
// & lt; o27.10..11 & gt; TIM2_CCMR2.IC4PSC: Input Capture 4 Prescaler
// & lt; i & gt; Default: No prescaler
// & lt; 0= & gt; No prescaler
// & lt; 1= & gt; capture every 2 events
// & lt; 2= & gt; capture every 4 events
// & lt; 3= & gt; capture every 8 events
// & lt; o27.8..9 & gt; TIM2_CCMR2.CC4S: Capture/compare 4 selection
// & lt; i & gt; Default: CC4 configured as output
// & lt; 0= & gt; CC4 configured as output
// & lt; 1= & gt; CC4 configured as input, IC4 mapped on TI1
// & lt; 2= & gt; CC4 configured as input, IC4 mapped on TI2
// & lt; 3= & gt; CC4 configured as input, IC4 mapped on TRGI
// & lt; o28.13 & gt; TIM2_CCER.CC4P: Capture/compare 4 output Polarity set
// & lt; i & gt; Default: non-inverted
// & lt; 0= & gt; non-inverted
// & lt; 1= & gt; inverted
// & lt; o28.12 & gt; TIM2_CCER.CC4E: Capture/compare 4 output enabled
// & lt; i & gt; Default: Capture disabled
// & lt; 0= & gt; Capture disabled
// & lt; 1= & gt; Capture enabled
// & lt; /h & gt;
// & lt; o32 & gt; TIM2_CCR4: Capture/compare register 4 & lt; 0-65535 & gt;
// & lt; i & gt; Set the Compare register value for compare register 4.
// & lt; i & gt; Default: 0
// & lt; /h & gt;
//
// & lt; /e & gt;
// & lt; e3.1 & gt; TIM2 interrupts
// & lt; o33.14 & gt; TIM2_DIER.TDE: Trigger DMA request enabled
// & lt; o33.12 & gt; TIM2_DIER.CC4DE: Capture/Compare 4 DMA request enabled
// & lt; o33.11 & gt; TIM2_DIER.CC3DE: Capture/Compare 3 DMA request enabled
// & lt; o33.10 & gt; TIM2_DIER.CC2DE: Capture/Compare 2 DMA request enabled
// & lt; o33.9 & gt; TIM2_DIER.CC1DE: Capture/Compare 1 DMA request enabled
// & lt; o33.8 & gt; TIM2_DIER.UDE: Update DMA request enabled
// & lt; o33.6 & gt; TIM2_DIER.TIE: Trigger interrupt enabled
// & lt; o33.4 & gt; TIM2_DIER.CC4IE: Capture/Compare 4 interrupt enabled
// & lt; o33.3 & gt; TIM2_DIER.CC3IE: Capture/Compare 3 interrupt enabled
// & lt; o33.2 & gt; TIM2_DIER.CC2IE: Capture/Compare 2 interrupt enabled
// & lt; o33.1 & gt; TIM2_DIER.CC1IE: Capture/Compare 1 interrupt enabled
// & lt; o33.0 & gt; TIM2_DIER.UIE: Update interrupt enabled
// & lt; /e & gt;
// & lt; /e & gt;
//--------------------------------------------------------------------------- Timer 3 enabled
// & lt; e1.2 & gt; TIM3 : Timer 3 enabled
// & lt; o34 & gt; TIM3 period [us] & lt; 1-72000000:10 & gt;
// & lt; i & gt; Set the timer period for Timer 3.
// & lt; i & gt; Default: 1000 (1ms)
// & lt; i & gt; Ignored if Detailed settings is selected
//--------------------------------------------------------------------------- Timer 3 detailed settings
// & lt; e2.2 & gt; TIM3 detailed settings
// & lt; o35 & gt; TIM3.PSC: Timer 3 Prescaler & lt; 0-65535 & gt;
// & lt; i & gt; Set the prescaler for Timer 3.
// & lt; o36 & gt; TIM3.ARR: Timer 3 Auto-reload & lt; 0-65535 & gt;
// & lt; i & gt; Set the Auto-reload for Timer 3.
// & lt; h & gt; Timer 3 Control Register 1 Configuration (TIM3_CR1)
// & lt; o37.8..9 & gt; TIM3_CR1.CKD: Clock division
// & lt; i & gt; Default: tDTS = tCK_INT
// & lt; i & gt; devision ratio between timer clock and dead time
// & lt; 0= & gt; tDTS = tCK_INT
// & lt; 1= & gt; tDTS = 2*tCK_INT
// & lt; 2= & gt; tDTS = 4*tCK_INT
// & lt; o37.7 & gt; TIM3_CR1.ARPE: Auto-reload preload enable
// & lt; i & gt; Default: Auto-reload preload disenabled
// & lt; o37.5..6 & gt; TIM3_CR1.CMS: Center aligned mode selection
// & lt; i & gt; Default: Edge-aligned
// & lt; 0= & gt; Edge-aligned
// & lt; 1= & gt; Center-aligned mode1
// & lt; 2= & gt; Center-aligned mode2
// & lt; 3= & gt; Center-aligned mode3
// & lt; o37.4 & gt; TIM3_CR1.DIR: Direction
// & lt; i & gt; Default: DIR = Counter used as up-counter
// & lt; i & gt; read only if timer is configured as Center-aligned or Encoder mode
// & lt; 0= & gt; Counter used as up-counter
// & lt; 1= & gt; Counter used as down-counter
// & lt; o37.3 & gt; TIM3_CR1.OPM: One pulse mode enable
// & lt; i & gt; Default: One pulse mode disabled
// & lt; o37.2 & gt; TIM3_CR1.URS: Update request source
// & lt; i & gt; Default: URS = Counter over-/underflow, UG bit, Slave mode controller
// & lt; 0= & gt; Counter over-/underflow, UG bit, Slave mode controller
// & lt; 1= & gt; Counter over-/underflow
// & lt; o37.1 & gt; TIM3_CR1.UDIS: Update disable
// & lt; i & gt; Default: Update enabled
// & lt; /h & gt;
//
// & lt; h & gt; Timer 3 Control Register 2 Configuration (TIM3_CR2)
// & lt; o38.7 & gt; TIM3_CR2.TI1S: TI1 Selection
// & lt; i & gt; Default: TIM3CH1 connected to TI1 input
// & lt; 0= & gt; TIM3CH1 connected to TI1 input
// & lt; 1= & gt; TIM3CH1,CH2,CH3 connected to TI1 input
// & lt; o38.4..6 & gt; TIM3_CR2.MMS: Master Mode Selection
// & lt; i & gt; Default: Reset
// & lt; i & gt; Select information to be sent in master mode to slave timers for synchronisation
// & lt; 0= & gt; Reset
// & lt; 1= & gt; Enable
// & lt; 2= & gt; Update
// & lt; 3= & gt; Compare Pulse
// & lt; 4= & gt; Compare OC1REF iused as TRGO
// & lt; 5= & gt; Compare OC2REF iused as TRGO
// & lt; 6= & gt; Compare OC3REF iused as TRGO
// & lt; 7= & gt; Compare OC4REF iused as TRGO
// & lt; o38.3 & gt; TIM3_CR2.CCDS: Capture/Compare DMA Selection
// & lt; i & gt; Default: CC4 DMA request on CC4 event
// & lt; 0= & gt; CC4 DMA request on CC4 event
// & lt; 1= & gt; CC4 DMA request on update event
// & lt; /h & gt;
//
// & lt; h & gt; Timer 3 Slave mode control register Configuration (TIM3_SMC)
// & lt; o39.15 & gt; TIM3_SMCR.ETP: External trigger polarity
// & lt; i & gt; Default: ETR is non-inverted
// & lt; 0= & gt; ETR is non-inverted
// & lt; 1= & gt; ETR is inverted
// & lt; o39.14 & gt; TIM3_SMCR.ECE: External clock mode 2 enabled
// & lt; o39.12..13 & gt; TIM3_SMCR.ETPS: External trigger prescaler
// & lt; i & gt; Default: Prescaler OFF
// & lt; 0= & gt; Prescaler OFF
// & lt; 1= & gt; fETPR/2
// & lt; 2= & gt; fETPR/4
// & lt; 3= & gt; fETPR/8
// & lt; o39.8..11 & gt; TIM3_SMCR.ETF: External trigger filter
// & lt; i & gt; Default: No filter
// & lt; 0= & gt; No filter
// & lt; 1= & gt; fSampling=fCK_INT, N=2
// & lt; 2= & gt; fSampling=fCK_INT, N=4
// & lt; 3= & gt; fSampling=fCK_INT, N=8
// & lt; 4= & gt; fSampling=fDTS/2, N=6
// & lt; 5= & gt; fSampling=fDTS/2, N=8
// & lt; 6= & gt; fSampling=fDTS/4, N=6
// & lt; 7= & gt; fSampling=fDTS/4, N=8
// & lt; 8= & gt; fSampling=fDTS/8, N=6
// & lt; 9= & gt; fSampling=fDTS/8, N=8
// & lt; 10= & gt; fSampling=fDTS/16, N=5
// & lt; 11= & gt; fSampling=fDTS/16, N=6
// & lt; 12= & gt; fSampling=fDTS/16, N=8
// & lt; 13= & gt; fSampling=fDTS/32, N=5
// & lt; 14= & gt; fSampling=fDTS/32, N=6
// & lt; 15= & gt; fSampling=fDTS/32, N=8
// & lt; o39.7 & gt; TIM3_SMCR.MSM: Delay trigger input
// & lt; o39.4..6 & gt; TIM3_SMCR.TS: Trigger Selection
// & lt; i & gt; Default: Reserved
// & lt; 0= & gt; Reserved
// & lt; 1= & gt; TIM2 (ITR1)
// & lt; 2= & gt; TIM3 (ITR2)
// & lt; 3= & gt; TIM3 (ITR3)
// & lt; 4= & gt; TI1 Edge Detector (TI1F_ED)
// & lt; 5= & gt; Filtered Timer Input 1 (TI1FP1)
// & lt; 6= & gt; Filtered Timer Input 2 (TI1FP2)
// & lt; 7= & gt; External Trigger Input (ETRF)
// & lt; o39.0..2 & gt; TIM3_SMCR.SMS: Slave mode selection
// & lt; i & gt; Default: Slave mode disabled
// & lt; 0= & gt; Slave mode disabled
// & lt; 1= & gt; Encoder mode 1
// & lt; 2= & gt; Encoder mode 2
// & lt; 3= & gt; Encoder mode 3
// & lt; 4= & gt; Reset mode
// & lt; 5= & gt; Gated mode
// & lt; 6= & gt; Trigger mode
// & lt; 7= & gt; External clock mode 1
// & lt; /h & gt;
//
//--------------------------------------------------------------------------- Timer 3 channel 1
// & lt; h & gt; Channel 1 Configuration
// & lt; h & gt; Cannel configured as output
// & lt; o40.7 & gt; TIM3_CCMR1.OC1CE: Output Compare 1 Clear enabled
// & lt; o40.4..6 & gt; TIM3_CCMR1.OC1M: Output Compare 1 Mode
// & lt; i & gt; Default: Frozen
// & lt; 0= & gt; Frozen
// & lt; 1= & gt; Set channel 1 to active level on match
// & lt; 2= & gt; Set channel 1 to inactive level on match
// & lt; 3= & gt; Toggle
// & lt; 4= & gt; Force inactive level
// & lt; 5= & gt; Force active level
// & lt; 6= & gt; PWM mode 1
// & lt; 7= & gt; PWM mode 2
// & lt; o40.3 & gt; TIM3_CCMR1.OC1PE: Output Compare 1 Preload enabled
// & lt; o40.2 & gt; TIM3_CCMR1.OC1FE: Output Compare 1 Fast enabled
// & lt; o40.0..1 & gt; TIM3_CCMR1.CC1S: Capture/compare 1 selection
// & lt; i & gt; Default: CC1 configured as output
// & lt; 0= & gt; CC1 configured as output
// & lt; o42.1 & gt; TIM3_CCER.CC1P: Capture/compare 1 output Polarity set
// & lt; i & gt; Default: OC1 active high
// & lt; 0= & gt; OC1 active high
// & lt; 1= & gt; OC1 active low
// & lt; o42.0 & gt; TIM1_CCER.CC1E: Capture/compare 1 output enabled
// & lt; i & gt; Default: OC1 not active
// & lt; 0= & gt; OC1 not active
// & lt; 1= & gt; OC1 is output on corresponding pin
// & lt; /h & gt;
// & lt; h & gt; Channel configured as input
// & lt; o40.4..7 & gt; TIM3_CCMR1.IC1F: Input Capture 1 Filter
// & lt; i & gt; Default: No filter
// & lt; 0= & gt; No filter
// & lt; 1= & gt; fSampling=fCK_INT, N=2
// & lt; 2= & gt; fSampling=fCK_INT, N=4
// & lt; 3= & gt; fSampling=fCK_INT, N=8
// & lt; 4= & gt; fSampling=fDTS/2, N=6
// & lt; 5= & gt; fSampling=fDTS/2, N=8
// & lt; 6= & gt; fSampling=fDTS/4, N=6
// & lt; 7= & gt; fSampling=fDTS/4, N=8
// & lt; 8= & gt; fSampling=fDTS/8, N=6
// & lt; 9= & gt; fSampling=fDTS/8, N=8
// & lt; 10= & gt; fSampling=fDTS/16, N=5
// & lt; 11= & gt; fSampling=fDTS/16, N=6
// & lt; 12= & gt; fSampling=fDTS/16, N=8
// & lt; 13= & gt; fSampling=fDTS/32, N=5
// & lt; 14= & gt; fSampling=fDTS/32, N=6
// & lt; 15= & gt; fSampling=fDTS/32, N=8
// & lt; o40.2..3 & gt; TIM3_CCMR1.IC1PSC: Input Capture 1 Prescaler
// & lt; i & gt; Default: No prescaler
// & lt; 0= & gt; No prescaler
// & lt; 1= & gt; capture every 2 events
// & lt; 2= & gt; capture every 4 events
// & lt; 3= & gt; capture every 8 events
// & lt; o40.0..1 & gt; TIM3_CCMR1.CC1S: Capture/compare 1 selection
// & lt; i & gt; Default: CC1 configured as output
// & lt; 0= & gt; CC1 configured as output
// & lt; 1= & gt; CC1 configured as input, IC1 mapped on TI1
// & lt; 2= & gt; CC1 configured as input, IC1 mapped on TI2
// & lt; 3= & gt; CC1 configured as input, IC1 mapped on TRGI
// & lt; o42.1 & gt; TIM3_CCER.CC1P: Capture/compare 1 output Polarity set
// & lt; i & gt; Default: non-inverted
// & lt; 0= & gt; non-inverted
// & lt; 1= & gt; inverted
// & lt; o42.0 & gt; TIM3_CCER.CC1E: Capture/compare 1 output enabled
// & lt; i & gt; Default: Capture disabled
// & lt; 0= & gt; Capture disabled
// & lt; 1= & gt; Capture enabled
// & lt; /h & gt;
// & lt; o43 & gt; TIM3_CCR1: Capture/compare register 1 & lt; 0-65535 & gt;
// & lt; i & gt; Set the Compare register value for compare register 1.
// & lt; i & gt; Default: 0
// & lt; /h & gt;
//
//--------------------------------------------------------------------------- Timer 3 channel 2
// & lt; h & gt; Channel 2 Configuration
// & lt; h & gt; Cannel configured as output
// & lt; o40.15 & gt; TIM3_CCMR1.OC2CE: Output Compare 2 Clear enabled
// & lt; o40.12..14 & gt; TIM3_CCMR1.OC2M: Output Compare 2 Mode
// & lt; i & gt; Default: Frozen
// & lt; 0= & gt; Frozen
// & lt; 1= & gt; Set channel 2 to active level on match
// & lt; 2= & gt; Set channel 2 to inactive level on match
// & lt; 3= & gt; Toggle
// & lt; 4= & gt; Force inactive level
// & lt; 5= & gt; Force active level
// & lt; 6= & gt; PWM mode 1
// & lt; 7= & gt; PWM mode 2
// & lt; o40.11 & gt; TIM3_CCMR1.OC2PE: Output Compare 2 Preload enabled
// & lt; o40.10 & gt; TIM3_CCMR1.OC2FE: Output Compare 2 Fast enabled
// & lt; o40.8..9 & gt; TIM3_CCMR1.CC2S: Capture/compare 2 selection
// & lt; i & gt; Default: CC2 configured as output
// & lt; 0= & gt; CC2 configured as output
// & lt; o42.5 & gt; TIM3_CCER.CC2P: Capture/compare 2 output Polarity set
// & lt; i & gt; Default: OC2 active high
// & lt; 0= & gt; OC2 active high
// & lt; 1= & gt; OC2 active low
// & lt; o42.4 & gt; TIM3_CCER.CC2E: Capture/compare 2 output enabled
// & lt; i & gt; Default: OC2 not active
// & lt; 0= & gt; OC2 not active
// & lt; 1= & gt; OC2 is output on corresponding pin
// & lt; /h & gt;
// & lt; h & gt; Channel configured as input
// & lt; o40.12..15 & gt; TIM3_CCMR1.IC2F: Input Capture 2 Filter
// & lt; i & gt; Default: No filter
// & lt; 0= & gt; No filter
// & lt; 1= & gt; fSampling=fCK_INT, N=2
// & lt; 2= & gt; fSampling=fCK_INT, N=4
// & lt; 3= & gt; fSampling=fCK_INT, N=8
// & lt; 4= & gt; fSampling=fDTS/2, N=6
// & lt; 5= & gt; fSampling=fDTS/2, N=8
// & lt; 6= & gt; fSampling=fDTS/4, N=6
// & lt; 7= & gt; fSampling=fDTS/4, N=8
// & lt; 8= & gt; fSampling=fDTS/8, N=6
// & lt; 9= & gt; fSampling=fDTS/8, N=8
// & lt; 10= & gt; fSampling=fDTS/16, N=5
// & lt; 11= & gt; fSampling=fDTS/16, N=6
// & lt; 12= & gt; fSampling=fDTS/16, N=8
// & lt; 13= & gt; fSampling=fDTS/32, N=5
// & lt; 14= & gt; fSampling=fDTS/32, N=6
// & lt; 15= & gt; fSampling=fDTS/32, N=8
// & lt; o40.10..11 & gt; TIM3_CCMR1.IC2PSC: Input Capture 2 Prescaler
// & lt; i & gt; Default: No prescaler
// & lt; 0= & gt; No prescaler
// & lt; 1= & gt; capture every 2 events
// & lt; 2= & gt; capture every 4 events
// & lt; 3= & gt; capture every 8 events
// & lt; o40.8..9 & gt; TIM3_CCMR1.CC2S: Capture/compare 2 selection
// & lt; i & gt; Default: CC2 configured as output
// & lt; 0= & gt; CC2 configured as output
// & lt; 1= & gt; CC2 configured as input, IC2 mapped on TI1
// & lt; 2= & gt; CC2 configured as input, IC2 mapped on TI2
// & lt; 3= & gt; CC2 configured as input, IC2 mapped on TRGI
// & lt; o42.5 & gt; TIM3_CCER.CC2P: Capture/compare 2 output Polarity set
// & lt; i & gt; Default: non-inverted
// & lt; 0= & gt; non-inverted
// & lt; 1= & gt; inverted
// & lt; o42.4 & gt; TIM3_CCER.CC2E: Capture/compare 2 output enabled
// & lt; i & gt; Default: Capture disabled
// & lt; 0= & gt; Capture disabled
// & lt; 1= & gt; Capture enabled
// & lt; /h & gt;
// & lt; o44 & gt; TIM3_CCR2: Capture/compare register 2 & lt; 0-65535 & gt;
// & lt; i & gt; Set the Compare register value for compare register 2.
// & lt; i & gt; Default: 0
// & lt; /h & gt;
//
//--------------------------------------------------------------------------- Timer 3 channel 3
// & lt; h & gt; Channel 3 Configuration
// & lt; h & gt; Cannel configured as output
// & lt; o41.7 & gt; TIM3_CCMR2.OC3CE: Output Compare 3 Clear enabled
// & lt; o41.4..6 & gt; TIM3_CCMR2.OC3M: Output Compare 3 Mode
// & lt; i & gt; Default: Frozen
// & lt; 0= & gt; Frozen
// & lt; 1= & gt; Set channel 3 to active level on match
// & lt; 2= & gt; Set channel 3 to inactive level on match
// & lt; 3= & gt; Toggle
// & lt; 4= & gt; Force inactive level
// & lt; 5= & gt; Force active level
// & lt; 6= & gt; PWM mode 1
// & lt; 7= & gt; PWM mode 2
// & lt; o41.3 & gt; TIM3_CCMR2.OC3PE: Output Compare 3 Preload enabled
// & lt; o41.2 & gt; TIM3_CCMR2.OC3FE: Output Compare 3 Fast enabled
// & lt; o41.0..1 & gt; TIM3_CCMR2.CC3S: Capture/compare 3 selection
// & lt; i & gt; Default: CC3 configured as output
// & lt; 0= & gt; CC3 configured as output
// & lt; o42.9 & gt; TIM3_CCER.CC3P: Capture/compare 3 output Polarity set
// & lt; i & gt; Default: OC3 active high
// & lt; 0= & gt; OC3 active high
// & lt; 1= & gt; OC3 active low
// & lt; o42.8 & gt; TIM3_CCER.CC3E: Capture/compare 3 output enabled
// & lt; i & gt; Default: OC3 not active
// & lt; 0= & gt; OC3 not active
// & lt; 1= & gt; OC3 is output on corresponding pin
// & lt; /h & gt;
// & lt; h & gt; Channel configured as input
// & lt; o41.4..7 & gt; TIM3_CCMR2.IC3F: Input Capture 3 Filter
// & lt; i & gt; Default: No filter
// & lt; 0= & gt; No filter
// & lt; 1= & gt; fSampling=fCK_INT, N=2
// & lt; 2= & gt; fSampling=fCK_INT, N=4
// & lt; 3= & gt; fSampling=fCK_INT, N=8
// & lt; 4= & gt; fSampling=fDTS/2, N=6
// & lt; 5= & gt; fSampling=fDTS/2, N=8
// & lt; 6= & gt; fSampling=fDTS/4, N=6
// & lt; 7= & gt; fSampling=fDTS/4, N=8
// & lt; 8= & gt; fSampling=fDTS/8, N=6
// & lt; 9= & gt; fSampling=fDTS/8, N=8
// & lt; 10= & gt; fSampling=fDTS/16, N=5
// & lt; 11= & gt; fSampling=fDTS/16, N=6
// & lt; 12= & gt; fSampling=fDTS/16, N=8
// & lt; 13= & gt; fSampling=fDTS/32, N=5
// & lt; 14= & gt; fSampling=fDTS/32, N=6
// & lt; 15= & gt; fSampling=fDTS/32, N=8
// & lt; o41.2..3 & gt; TIM3_CCMR2.IC3PSC: Input Capture 3 Prescaler
// & lt; i & gt; Default: No prescaler
// & lt; 0= & gt; No prescaler
// & lt; 1= & gt; capture every 2 events
// & lt; 2= & gt; capture every 4 events
// & lt; 3= & gt; capture every 8 events
// & lt; o41.0..1 & gt; TIM3_CCMR2.CC3S: Capture/compare 3 selection
// & lt; i & gt; Default: CC3 configured as output
// & lt; 0= & gt; CC3 configured as output
// & lt; 1= & gt; CC3 configured as input, IC3 mapped on TI1
// & lt; 2= & gt; CC3 configured as input, IC3 mapped on TI2
// & lt; 3= & gt; CC3 configured as input, IC3 mapped on TRGI
// & lt; o42.9 & gt; TIM3_CCER.CC3P: Capture/compare 3 output Polarity set
// & lt; i & gt; Default: non-inverted
// & lt; 0= & gt; non-inverted
// & lt; 1= & gt; inverted
// & lt; o42.8 & gt; TIM3_CCER.CC3E: Capture/compare 3 output enabled
// & lt; i & gt; Default: Capture disabled
// & lt; 0= & gt; Capture disabled
// & lt; 1= & gt; Capture enabled
// & lt; /h & gt;
// & lt; o45 & gt; TIM3_CCR3: Capture/compare register 3 & lt; 0-65535 & gt;
// & lt; i & gt; Set the Compare register value for compare register 3.
// & lt; i & gt; Default: 0
// & lt; /h & gt;
//
//--------------------------------------------------------------------------- Timer 3 channel 4
// & lt; h & gt; Channel 4 Configuration
// & lt; h & gt; Cannel configured as output
// & lt; o41.15 & gt; TIM3_CCMR2.OC4CE: Output Compare 4 Clear enabled
// & lt; o41.12..14 & gt; TIM3_CCMR2.OC4M: Output Compare 4 Mode
// & lt; i & gt; Default: Frozen
// & lt; 0= & gt; Frozen
// & lt; 1= & gt; Set channel 4 to active level on match
// & lt; 2= & gt; Set channel 4 to inactive level on match
// & lt; 3= & gt; Toggle
// & lt; 4= & gt; Force inactive level
// & lt; 5= & gt; Force active level
// & lt; 6= & gt; PWM mode 1
// & lt; 7= & gt; PWM mode 2
// & lt; o41.11 & gt; TIM3_CCMR2.OC4PE: Output Compare 4 Preload enabled
// & lt; o41.10 & gt; TIM3_CCMR2.OC4FE: Output Compare 4 Fast enabled
// & lt; o41.8..9 & gt; TIM3_CCMR2.CC4S: Capture/compare 4 selection
// & lt; i & gt; Default: CC4 configured as output
// & lt; 0= & gt; CC4 configured as output
// & lt; o42.13 & gt; TIM3_CCER.CC4P: Capture/compare 4 output Polarity set
// & lt; i & gt; Default: OC4 active high
// & lt; 0= & gt; OC4 active high
// & lt; 1= & gt; OC4 active low
// & lt; o42.12 & gt; TIM3_CCER.CC4E: Capture/compare 4 output enabled
// & lt; i & gt; Default: OC4 not active
// & lt; 0= & gt; OC4 not active
// & lt; 1= & gt; OC4 is output on corresponding pin
// & lt; /h & gt;
// & lt; h & gt; Channel configured as input
// & lt; o41.12..15 & gt; TIM3_CCMR2.IC4F: Input Capture 4 Filter
// & lt; i & gt; Default: No filter
// & lt; 0= & gt; No filter
// & lt; 1= & gt; fSampling=fCK_INT, N=2
// & lt; 2= & gt; fSampling=fCK_INT, N=4
// & lt; 3= & gt; fSampling=fCK_INT, N=8
// & lt; 4= & gt; fSampling=fDTS/2, N=6
// & lt; 5= & gt; fSampling=fDTS/2, N=8
// & lt; 6= & gt; fSampling=fDTS/4, N=6
// & lt; 7= & gt; fSampling=fDTS/4, N=8
// & lt; 8= & gt; fSampling=fDTS/8, N=6
// & lt; 9= & gt; fSampling=fDTS/8, N=8
// & lt; 10= & gt; fSampling=fDTS/16, N=5
// & lt; 11= & gt; fSampling=fDTS/16, N=6
// & lt; 12= & gt; fSampling=fDTS/16, N=8
// & lt; 13= & gt; fSampling=fDTS/32, N=5
// & lt; 14= & gt; fSampling=fDTS/32, N=6
// & lt; 15= & gt; fSampling=fDTS/32, N=8
// & lt; o41.10..11 & gt; TIM3_CCMR2.IC4PSC: Input Capture 4 Prescaler
// & lt; i & gt; Default: No prescaler
// & lt; 0= & gt; No prescaler
// & lt; 1= & gt; capture every 2 events
// & lt; 2= & gt; capture every 4 events
// & lt; 3= & gt; capture every 8 events
// & lt; o41.8..9 & gt; TIM3_CCMR2.CC4S: Capture/compare 4 selection
// & lt; i & gt; Default: CC4 configured as output
// & lt; 0= & gt; CC4 configured as output
// & lt; 1= & gt; CC4 configured as input, IC4 mapped on TI1
// & lt; 2= & gt; CC4 configured as input, IC4 mapped on TI2
// & lt; 3= & gt; CC4 configured as input, IC4 mapped on TRGI
// & lt; o41.13 & gt; TIM3_CCER.CC4P: Capture/compare 4 output Polarity set
// & lt; i & gt; Default: non-inverted
// & lt; 0= & gt; non-inverted
// & lt; 1= & gt; inverted
// & lt; o41.12 & gt; TIM3_CCER.CC4E: Capture/compare 4 output enabled
// & lt; i & gt; Default: Capture disabled
// & lt; 0= & gt; Capture disabled
// & lt; 1= & gt; Capture enabled
// & lt; /h & gt;
// & lt; o46 & gt; TIM3_CCR4: Capture/compare register 4 & lt; 0-65535 & gt;
// & lt; i & gt; Set the Compare register value for compare register 4.
// & lt; i & gt; Default: 0
// & lt; /h & gt;
//
// & lt; /e & gt;
// & lt; e3.2 & gt; TIM3 interrupts
// & lt; o47.14 & gt; TIM3_DIER.TDE: Trigger DMA request enabled
// & lt; o47.12 & gt; TIM3_DIER.CC4DE: Capture/Compare 4 DMA request enabled
// & lt; o47.11 & gt; TIM3_DIER.CC3DE: Capture/Compare 3 DMA request enabled
// & lt; o47.10 & gt; TIM3_DIER.CC2DE: Capture/Compare 2 DMA request enabled
// & lt; o47.9 & gt; TIM3_DIER.CC1DE: Capture/Compare 1 DMA request enabled
// & lt; o47.8 & gt; TIM3_DIER.UDE: Update DMA request enabled
// & lt; o47.6 & gt; TIM3_DIER.TIE: Trigger interrupt enabled
// & lt; o47.4 & gt; TIM3_DIER.CC4IE: Capture/Compare 4 interrupt enabled
// & lt; o47.3 & gt; TIM3_DIER.CC3IE: Capture/Compare 3 interrupt enabled
// & lt; o47.2 & gt; TIM3_DIER.CC2IE: Capture/Compare 2 interrupt enabled
// & lt; o47.1 & gt; TIM3_DIER.CC1IE: Capture/Compare 1 interrupt enabled
// & lt; o47.0 & gt; TIM3_DIER.UIE: Update interrupt enabled
// & lt; /e & gt;
// & lt; /e & gt;
//
//--------------------------------------------------------------------------- Timer 4 enabled
// & lt; e1.3 & gt; TIM4 : Timer 4 enabled
// & lt; o48 & gt; TIM4 period [us] & lt; 1-72000000:10 & gt;
// & lt; i & gt; Set the timer period for Timer 4.
// & lt; i & gt; Default: 1000 (1ms)
// & lt; i & gt; Ignored if detailed settings is selected
//--------------------------------------------------------------------------- Timer 4 detailed settings
// & lt; e2.3 & gt; TIM4 detailed settings
// & lt; o49 & gt; TIM4.PSC: Timer 4 Prescaler & lt; 0-65535 & gt;
// & lt; i & gt; Set the prescaler for Timer 4.
// & lt; o50 & gt; TIM4.ARR: Timer 4 Auto-reload & lt; 0-65535 & gt;
// & lt; i & gt; Set the Auto-reload for Timer 4.
// & lt; h & gt; Timer 4 Control Register 1 Configuration (TIM4_CR1)
// & lt; o51.8..9 & gt; TIM4_CR1.CKD: Clock division
// & lt; i & gt; Default: tDTS = tCK_INT
// & lt; i & gt; devision ratio between timer clock and dead time
// & lt; 0= & gt; tDTS = tCK_INT
// & lt; 1= & gt; tDTS = 2*tCK_INT
// & lt; 2= & gt; tDTS = 4*tCK_INT
// & lt; o51.7 & gt; TIM4_CR1.ARPE: Auto-reload preload enable
// & lt; i & gt; Default: Auto-reload preload disenabled
// & lt; o51.5..6 & gt; TIM4_CR1.CMS: Center aligned mode selection
// & lt; i & gt; Default: Edge-aligned
// & lt; 0= & gt; Edge-aligned
// & lt; 1= & gt; Center-aligned mode1
// & lt; 2= & gt; Center-aligned mode2
// & lt; 3= & gt; Center-aligned mode3
// & lt; o51.4 & gt; TIM4_CR1.DIR: Direction
// & lt; i & gt; Default: DIR = Counter used as up-counter
// & lt; i & gt; read only if timer is configured as Center-aligned or Encoder mode
// & lt; 0= & gt; Counter used as up-counter
// & lt; 1= & gt; Counter used as down-counter
// & lt; o51.3 & gt; TIM4_CR1.OPM: One pulse mode enable
// & lt; i & gt; Default: One pulse mode disabled
// & lt; o51.2 & gt; TIM4_CR1.URS: Update request source
// & lt; i & gt; Default: URS = Counter over-/underflow, UG bit, Slave mode controller
// & lt; 0= & gt; Counter over-/underflow, UG bit, Slave mode controller
// & lt; 1= & gt; Counter over-/underflow
// & lt; o51.1 & gt; TIM4_CR1.UDIS: Update disable
// & lt; i & gt; Default: Update enabled
// & lt; /h & gt;
//
// & lt; h & gt; Timer 4 Control Register 2 Configuration (TIM4_CR2)
// & lt; o52.7 & gt; TIM4_CR2.TI1S: TI1 Selection
// & lt; i & gt; Default: TIM4CH1 connected to TI1 input
// & lt; 0= & gt; TIM4CH1 connected to TI1 input
// & lt; 1= & gt; TIM4CH1,CH2,CH3 connected to TI1 input
// & lt; o52.4..6 & gt; TIM4_CR2.MMS: Master Mode Selection
// & lt; i & gt; Default: Reset
// & lt; i & gt; Select information to be sent in master mode to slave timers for synchronisation
// & lt; 0= & gt; Reset
// & lt; 1= & gt; Enable
// & lt; 2= & gt; Update
// & lt; 3= & gt; Compare Pulse
// & lt; 4= & gt; Compare OC1REF iused as TRGO
// & lt; 5= & gt; Compare OC2REF iused as TRGO
// & lt; 6= & gt; Compare OC3REF iused as TRGO
// & lt; 7= & gt; Compare OC4REF iused as TRGO
// & lt; o52.3 & gt; TIM4_CR2.CCDS: Capture/Compare DMA Selection
// & lt; i & gt; Default: CC4 DMA request on CC4 event
// & lt; 0= & gt; CC4 DMA request on CC4 event
// & lt; 1= & gt; CC4 DMA request on update event
// & lt; /h & gt;
//
// & lt; h & gt; Timer 4 Slave mode control register Configuration (TIM4_SMC)
// & lt; o53.15 & gt; TIM4_SMCR.ETP: External trigger polarity
// & lt; i & gt; Default: ETR is non-inverted
// & lt; 0= & gt; ETR is non-inverted
// & lt; 1= & gt; ETR is inverted
// & lt; o53.14 & gt; TIM4_SMCR.ECE: External clock mode 2 enabled
// & lt; o53.12..13 & gt; TIM4_SMCR.ETPS: External trigger prescaler
// & lt; i & gt; Default: Prescaler OFF
// & lt; 0= & gt; Prescaler OFF
// & lt; 1= & gt; fETPR/2
// & lt; 2= & gt; fETPR/4
// & lt; 3= & gt; fETPR/8
// & lt; o53.8..11 & gt; TIM4_SMCR.ETF: External trigger filter
// & lt; i & gt; Default: No filter
// & lt; 0= & gt; No filter
// & lt; 1= & gt; fSampling=fCK_INT, N=2
// & lt; 2= & gt; fSampling=fCK_INT, N=4
// & lt; 3= & gt; fSampling=fCK_INT, N=8
// & lt; 4= & gt; fSampling=fDTS/2, N=6
// & lt; 5= & gt; fSampling=fDTS/2, N=8
// & lt; 6= & gt; fSampling=fDTS/4, N=6
// & lt; 7= & gt; fSampling=fDTS/4, N=8
// & lt; 8= & gt; fSampling=fDTS/8, N=6
// & lt; 9= & gt; fSampling=fDTS/8, N=8
// & lt; 10= & gt; fSampling=fDTS/16, N=5
// & lt; 11= & gt; fSampling=fDTS/16, N=6
// & lt; 12= & gt; fSampling=fDTS/16, N=8
// & lt; 13= & gt; fSampling=fDTS/32, N=5
// & lt; 14= & gt; fSampling=fDTS/32, N=6
// & lt; 15= & gt; fSampling=fDTS/32, N=8
// & lt; o53.7 & gt; TIM4_SMCR.MSM: Delay trigger input
// & lt; o53.4..6 & gt; TIM4_SMCR.TS: Trigger Selection
// & lt; i & gt; Default: Reserved
// & lt; 0= & gt; Reserved
// & lt; 1= & gt; TIM2 (ITR1)
// & lt; 2= & gt; TIM3 (ITR2)
// & lt; 3= & gt; TIM4 (ITR3)
// & lt; 4= & gt; TI1 Edge Detector (TI1F_ED)
// & lt; 5= & gt; Filtered Timer Input 1 (TI1FP1)
// & lt; 6= & gt; Filtered Timer Input 2 (TI1FP2)
// & lt; 7= & gt; External Trigger Input (ETRF)
// & lt; o53.0..2 & gt; TIM4_SMCR.SMS: Slave mode selection
// & lt; i & gt; Default: Slave mode disabled
// & lt; 0= & gt; Slave mode disabled
// & lt; 1= & gt; Encoder mode 1
// & lt; 2= & gt; Encoder mode 2
// & lt; 3= & gt; Encoder mode 3
// & lt; 4= & gt; Reset mode
// & lt; 5= & gt; Gated mode
// & lt; 6= & gt; Trigger mode
// & lt; 7= & gt; External clock mode 1
// & lt; /h & gt;
//
//
//--------------------------------------------------------------------------- Timer 4 channel 1
// & lt; h & gt; Channel 1 Configuration
// & lt; h & gt; Cannel configured as output
// & lt; o54.7 & gt; TIM4_CCMR1.OC1CE: Output Compare 1 Clear enabled
// & lt; o54.4..6 & gt; TIM4_CCMR1.OC1M: Output Compare 1 Mode
// & lt; i & gt; Default: Frozen
// & lt; 0= & gt; Frozen
// & lt; 1= & gt; Set channel 1 to active level on match
// & lt; 2= & gt; Set channel 1 to inactive level on match
// & lt; 3= & gt; Toggle
// & lt; 4= & gt; Force inactive level
// & lt; 5= & gt; Force active level
// & lt; 6= & gt; PWM mode 1
// & lt; 7= & gt; PWM mode 2
// & lt; o54.3 & gt; TIM4_CCMR1.OC1PE: Output Compare 1 Preload enabled
// & lt; o54.2 & gt; TIM4_CCMR1.OC1FE: Output Compare 1 Fast enabled
// & lt; o54.0..1 & gt; TIM4_CCMR1.CC1S: Capture/compare 1 selection
// & lt; i & gt; Default: CC1 configured as output
// & lt; 0= & gt; CC1 configured as output
// & lt; o56.1 & gt; TIM4_CCER.CC1P: Capture/compare 1 output Polarity set
// & lt; i & gt; Default: OC1 active high
// & lt; 0= & gt; OC1 active high
// & lt; 1= & gt; OC1 active low
// & lt; o56.0 & gt; TIM1_CCER.CC1E: Capture/compare 1 output enabled
// & lt; i & gt; Default: OC1 not active
// & lt; 0= & gt; OC1 not active
// & lt; 1= & gt; OC1 is output on corresponding pin
// & lt; /h & gt;
// & lt; h & gt; Channel configured as input
// & lt; o54.4..7 & gt; TIM4_CCMR1.IC1F: Input Capture 1 Filter
// & lt; i & gt; Default: No filter
// & lt; 0= & gt; No filter
// & lt; 1= & gt; fSampling=fCK_INT, N=2
// & lt; 2= & gt; fSampling=fCK_INT, N=4
// & lt; 3= & gt; fSampling=fCK_INT, N=8
// & lt; 4= & gt; fSampling=fDTS/2, N=6
// & lt; 5= & gt; fSampling=fDTS/2, N=8
// & lt; 6= & gt; fSampling=fDTS/4, N=6
// & lt; 7= & gt; fSampling=fDTS/4, N=8
// & lt; 8= & gt; fSampling=fDTS/8, N=6
// & lt; 9= & gt; fSampling=fDTS/8, N=8
// & lt; 10= & gt; fSampling=fDTS/16, N=5
// & lt; 11= & gt; fSampling=fDTS/16, N=6
// & lt; 12= & gt; fSampling=fDTS/16, N=8
// & lt; 13= & gt; fSampling=fDTS/32, N=5
// & lt; 14= & gt; fSampling=fDTS/32, N=6
// & lt; 15= & gt; fSampling=fDTS/32, N=8
// & lt; o54.2..3 & gt; TIM4_CCMR1.IC1PSC: Input Capture 1 Prescaler
// & lt; i & gt; Default: No prescaler
// & lt; 0= & gt; No prescaler
// & lt; 1= & gt; capture every 2 events
// & lt; 2= & gt; capture every 4 events
// & lt; 3= & gt; capture every 8 events
// & lt; o54.0..1 & gt; TIM4_CCMR1.CC1S: Capture/compare 1 selection
// & lt; i & gt; Default: CC1 configured as output
// & lt; 0= & gt; CC1 configured as output
// & lt; 1= & gt; CC1 configured as input, IC1 mapped on TI1
// & lt; 2= & gt; CC1 configured as input, IC1 mapped on TI2
// & lt; 3= & gt; CC1 configured as input, IC1 mapped on TRGI
// & lt; o56.1 & gt; TIM4_CCER.CC1P: Capture/compare 1 output Polarity set
// & lt; i & gt; Default: non-inverted
// & lt; 0= & gt; non-inverted
// & lt; 1= & gt; inverted
// & lt; o56.0 & gt; TIM4_CCER.CC1E: Capture/compare 1 output enabled
// & lt; i & gt; Default: Capture disabled
// & lt; 0= & gt; Capture disabled
// & lt; 1= & gt; Capture enabled
// & lt; /h & gt;
// & lt; o57 & gt; TIM4_CCR1: Capture/compare register 1 & lt; 0-65535 & gt;
// & lt; i & gt; Set the Compare register value for compare register 1.
// & lt; i & gt; Default: 0
// & lt; /h & gt;
//
//--------------------------------------------------------------------------- Timer 4 channel 2
// & lt; h & gt; Channel 2 Configuration
// & lt; h & gt; Cannel configured as output
// & lt; o54.15 & gt; TIM4_CCMR1.OC2CE: Output Compare 2 Clear enabled
// & lt; o54.12..14 & gt; TIM4_CCMR1.OC2M: Output Compare 2 Mode
// & lt; i & gt; Default: Frozen
// & lt; 0= & gt; Frozen
// & lt; 1= & gt; Set channel 2 to active level on match
// & lt; 2= & gt; Set channel 2 to inactive level on match
// & lt; 3= & gt; Toggle
// & lt; 4= & gt; Force inactive level
// & lt; 5= & gt; Force active level
// & lt; 6= & gt; PWM mode 1
// & lt; 7= & gt; PWM mode 2
// & lt; o54.11 & gt; TIM4_CCMR1.OC2PE: Output Compare 2 Preload enabled
// & lt; o54.10 & gt; TIM4_CCMR1.OC2FE: Output Compare 2 Fast enabled
// & lt; o54.8..9 & gt; TIM4_CCMR1.CC2S: Capture/compare 2 selection
// & lt; i & gt; Default: CC2 configured as output
// & lt; 0= & gt; CC2 configured as output
// & lt; o56.5 & gt; TIM4_CCER.CC2P: Capture/compare 2 output Polarity set
// & lt; i & gt; Default: OC2 active high
// & lt; 0= & gt; OC2 active high
// & lt; 1= & gt; OC2 active low
// & lt; o56.4 & gt; TIM4_CCER.CC2E: Capture/compare 2 output enabled
// & lt; i & gt; Default: OC2 not active
// & lt; 0= & gt; OC2 not active
// & lt; 1= & gt; OC2 is output on corresponding pin
// & lt; /h & gt;
// & lt; h & gt; Channel configured as input
// & lt; o54.12..15 & gt; TIM4_CCMR1.IC2F: Input Capture 2 Filter
// & lt; i & gt; Default: No filter
// & lt; 0= & gt; No filter
// & lt; 1= & gt; fSampling=fCK_INT, N=2
// & lt; 2= & gt; fSampling=fCK_INT, N=4
// & lt; 3= & gt; fSampling=fCK_INT, N=8
// & lt; 4= & gt; fSampling=fDTS/2, N=6
// & lt; 5= & gt; fSampling=fDTS/2, N=8
// & lt; 6= & gt; fSampling=fDTS/4, N=6
// & lt; 7= & gt; fSampling=fDTS/4, N=8
// & lt; 8= & gt; fSampling=fDTS/8, N=6
// & lt; 9= & gt; fSampling=fDTS/8, N=8
// & lt; 10= & gt; fSampling=fDTS/16, N=5
// & lt; 11= & gt; fSampling=fDTS/16, N=6
// & lt; 12= & gt; fSampling=fDTS/16, N=8
// & lt; 13= & gt; fSampling=fDTS/32, N=5
// & lt; 14= & gt; fSampling=fDTS/32, N=6
// & lt; 15= & gt; fSampling=fDTS/32, N=8
// & lt; o54.10..11 & gt; TIM4_CCMR1.IC2PSC: Input Capture 2 Prescaler
// & lt; i & gt; Default: No prescaler
// & lt; 0= & gt; No prescaler
// & lt; 1= & gt; capture every 2 events
// & lt; 2= & gt; capture every 4 events
// & lt; 3= & gt; capture every 8 events
// & lt; o54.8..9 & gt; TIM4_CCMR1.CC2S: Capture/compare 2 selection
// & lt; i & gt; Default: CC2 configured as output
// & lt; 0= & gt; CC2 configured as output
// & lt; 1= & gt; CC2 configured as input, IC2 mapped on TI1
// & lt; 2= & gt; CC2 configured as input, IC2 mapped on TI2
// & lt; 3= & gt; CC2 configured as input, IC2 mapped on TRGI
// & lt; o56.5 & gt; TIM4_CCER.CC2P: Capture/compare 2 output Polarity set
// & lt; i & gt; Default: non-inverted
// & lt; 0= & gt; non-inverted
// & lt; 1= & gt; inverted
// & lt; o56.4 & gt; TIM4_CCER.CC2E: Capture/compare 2 output enabled
// & lt; i & gt; Default: Capture disabled
// & lt; 0= & gt; Capture disabled
// & lt; 1= & gt; Capture enabled
// & lt; /h & gt;
// & lt; o58 & gt; TIM4_CCR2: Capture/compare register 2 & lt; 0-65535 & gt;
// & lt; i & gt; Set the Compare register value for compare register 2.
// & lt; i & gt; Default: 0
// & lt; /h & gt;
//
//--------------------------------------------------------------------------- Timer 4 channel 3
// & lt; h & gt; Channel 3 Configuration
// & lt; h & gt; Cannel configured as output
// & lt; o55.7 & gt; TIM4_CCMR2.OC3CE: Output Compare 3 Clear enabled
// & lt; o55.4..6 & gt; TIM4_CCMR2.OC3M: Output Compare 3 Mode
// & lt; i & gt; Default: Frozen
// & lt; 0= & gt; Frozen
// & lt; 1= & gt; Set channel 3 to active level on match
// & lt; 2= & gt; Set channel 3 to inactive level on match
// & lt; 3= & gt; Toggle
// & lt; 4= & gt; Force inactive level
// & lt; 5= & gt; Force active level
// & lt; 6= & gt; PWM mode 1
// & lt; 7= & gt; PWM mode 2
// & lt; o55.3 & gt; TIM4_CCMR2.OC3PE: Output Compare 3 Preload enabled
// & lt; o55.2 & gt; TIM4_CCMR2.OC3FE: Output Compare 3 Fast enabled
// & lt; o55.0..1 & gt; TIM4_CCMR2.CC3S: Capture/compare 3 selection
// & lt; i & gt; Default: CC3 configured as output
// & lt; 0= & gt; CC3 configured as output
// & lt; o56.9 & gt; TIM4_CCER.CC3P: Capture/compare 3 output Polarity set
// & lt; i & gt; Default: OC3 active high
// & lt; 0= & gt; OC3 active high
// & lt; 1= & gt; OC3 active low
// & lt; o56.8 & gt; TIM4_CCER.CC3E: Capture/compare 3 output enabled
// & lt; i & gt; Default: OC3 not active
// & lt; 0= & gt; OC3 not active
// & lt; 1= & gt; OC3 is output on corresponding pin
// & lt; /h & gt;
// & lt; h & gt; Channel configured as input
// & lt; o55.4..7 & gt; TIM4_CCMR2.IC3F: Input Capture 3 Filter
// & lt; i & gt; Default: No filter
// & lt; 0= & gt; No filter
// & lt; 1= & gt; fSampling=fCK_INT, N=2
// & lt; 2= & gt; fSampling=fCK_INT, N=4
// & lt; 3= & gt; fSampling=fCK_INT, N=8
// & lt; 4= & gt; fSampling=fDTS/2, N=6
// & lt; 5= & gt; fSampling=fDTS/2, N=8
// & lt; 6= & gt; fSampling=fDTS/4, N=6
// & lt; 7= & gt; fSampling=fDTS/4, N=8
// & lt; 8= & gt; fSampling=fDTS/8, N=6
// & lt; 9= & gt; fSampling=fDTS/8, N=8
// & lt; 10= & gt; fSampling=fDTS/16, N=5
// & lt; 11= & gt; fSampling=fDTS/16, N=6
// & lt; 12= & gt; fSampling=fDTS/16, N=8
// & lt; 13= & gt; fSampling=fDTS/32, N=5
// & lt; 14= & gt; fSampling=fDTS/32, N=6
// & lt; 15= & gt; fSampling=fDTS/32, N=8
// & lt; o55.2..3 & gt; TIM4_CCMR2.IC3PSC: Input Capture 3 Prescaler
// & lt; i & gt; Default: No prescaler
// & lt; 0= & gt; No prescaler
// & lt; 1= & gt; capture every 2 events
// & lt; 2= & gt; capture every 4 events
// & lt; 3= & gt; capture every 8 events
// & lt; o55.0..1 & gt; TIM4_CCMR2.CC3S: Capture/compare 3 selection
// & lt; i & gt; Default: CC3 configured as output
// & lt; 0= & gt; CC3 configured as output
// & lt; 1= & gt; CC3 configured as input, IC3 mapped on TI1
// & lt; 2= & gt; CC3 configured as input, IC3 mapped on TI2
// & lt; 3= & gt; CC3 configured as input, IC3 mapped on TRGI
// & lt; o56.9 & gt; TIM4_CCER.CC3P: Capture/compare 3 output Polarity set
// & lt; i & gt; Default: non-inverted
// & lt; 0= & gt; non-inverted
// & lt; 1= & gt; inverted
// & lt; o56.8 & gt; TIM4_CCER.CC3E: Capture/compare 3 output enabled
// & lt; i & gt; Default: Capture disabled
// & lt; 0= & gt; Capture disabled
// & lt; 1= & gt; Capture enabled
// & lt; /h & gt;
// & lt; o59 & gt; TIM4_CCR3: Capture/compare register 3 & lt; 0-65535 & gt;
// & lt; i & gt; Set the Compare register value for compare register 3.
// & lt; i & gt; Default: 0
// & lt; /h & gt;
//
//--------------------------------------------------------------------------- Timer 4 channel 4
// & lt; h & gt; Channel 4 Configuration
// & lt; h & gt; Cannel configured as output
// & lt; o55.15 & gt; TIM4_CCMR2.OC4CE: Output Compare 4 Clear enabled
// & lt; o55.12..14 & gt; TIM4_CCMR2.OC4M: Output Compare 4 Mode
// & lt; i & gt; Default: Frozen
// & lt; 0= & gt; Frozen
// & lt; 1= & gt; Set channel 4 to active level on match
// & lt; 2= & gt; Set channel 4 to inactive level on match
// & lt; 3= & gt; Toggle
// & lt; 4= & gt; Force inactive level
// & lt; 5= & gt; Force active level
// & lt; 6= & gt; PWM mode 1
// & lt; 7= & gt; PWM mode 2
// & lt; o55.11 & gt; TIM4_CCMR2.OC4PE: Output Compare 4 Preload enabled
// & lt; o55.10 & gt; TIM4_CCMR2.OC4FE: Output Compare 4 Fast enabled
// & lt; o55.8..9 & gt; TIM4_CCMR2.CC4S: Capture/compare 4 selection
// & lt; i & gt; Default: CC4 configured as output
// & lt; 0= & gt; CC4 configured as output
// & lt; o56.13 & gt; TIM4_CCER.CC4P: Capture/compare 4 output Polarity set
// & lt; i & gt; Default: OC4 active high
// & lt; 0= & gt; OC4 active high
// & lt; 1= & gt; OC4 active low
// & lt; o56.12 & gt; TIM4_CCER.CC4E: Capture/compare 4 output enabled
// & lt; i & gt; Default: OC4 not active
// & lt; 0= & gt; OC4 not active
// & lt; 1= & gt; OC4 is output on corresponding pin
// & lt; /h & gt;
// & lt; h & gt; Channel configured as input
// & lt; o54.12..15 & gt; TIM4_CCMR2.IC4F: Input Capture 4 Filter
// & lt; i & gt; Default: No filter
// & lt; 0= & gt; No filter
// & lt; 1= & gt; fSampling=fCK_INT, N=2
// & lt; 2= & gt; fSampling=fCK_INT, N=4
// & lt; 3= & gt; fSampling=fCK_INT, N=8
// & lt; 4= & gt; fSampling=fDTS/2, N=6
// & lt; 5= & gt; fSampling=fDTS/2, N=8
// & lt; 6= & gt; fSampling=fDTS/4, N=6
// & lt; 7= & gt; fSampling=fDTS/4, N=8
// & lt; 8= & gt; fSampling=fDTS/8, N=6
// & lt; 9= & gt; fSampling=fDTS/8, N=8
// & lt; 10= & gt; fSampling=fDTS/16, N=5
// & lt; 11= & gt; fSampling=fDTS/16, N=6
// & lt; 12= & gt; fSampling=fDTS/16, N=8
// & lt; 13= & gt; fSampling=fDTS/32, N=5
// & lt; 14= & gt; fSampling=fDTS/32, N=6
// & lt; 15= & gt; fSampling=fDTS/32, N=8
// & lt; o54.10..11 & gt; TIM4_CCMR2.IC4PSC: Input Capture 4 Prescaler
// & lt; i & gt; Default: No prescaler
// & lt; 0= & gt; No prescaler
// & lt; 1= & gt; capture every 2 events
// & lt; 2= & gt; capture every 4 events
// & lt; 3= & gt; capture every 8 events
// & lt; o54.8..9 & gt; TIM4_CCMR2.CC4S: Capture/compare 4 selection
// & lt; i & gt; Default: CC4 configured as output
// & lt; 0= & gt; CC4 configured as output
// & lt; 1= & gt; CC4 configured as input, IC4 mapped on TI1
// & lt; 2= & gt; CC4 configured as input, IC4 mapped on TI2
// & lt; 3= & gt; CC4 configured as input, IC4 mapped on TRGI
// & lt; o56.13 & gt; TIM4_CCER.CC4P: Capture/compare 4 output Polarity set
// & lt; i & gt; Default: non-inverted
// & lt; 0= & gt; non-inverted
// & lt; 1= & gt; inverted
// & lt; o56.12 & gt; TIM4_CCER.CC4E: Capture/compare 4 output enabled
// & lt; i & gt; Default: Capture disabled
// & lt; 0= & gt; Capture disabled
// & lt; 1= & gt; Capture enabled
// & lt; /h & gt;
// & lt; o60 & gt; TIM4_CCR4: Capture/compare register 4 & lt; 0-65535 & gt;
// & lt; i & gt; Set the Compare register value for compare register 4.
// & lt; i & gt; Default: 0
// & lt; /h & gt;
//
// & lt; /e & gt;
// & lt; e3.3 & gt; TIM4 interrupts
// & lt; o61.14 & gt; TIM4_DIER.TDE: Trigger DMA request enabled
// & lt; o61.12 & gt; TIM4_DIER.CC4DE: Capture/Compare 4 DMA request enabled
// & lt; o61.11 & gt; TIM4_DIER.CC3DE: Capture/Compare 3 DMA request enabled
// & lt; o61.10 & gt; TIM4_DIER.CC2DE: Capture/Compare 2 DMA request enabled
// & lt; o61.9 & gt; TIM4_DIER.CC1DE: Capture/Compare 1 DMA request enabled
// & lt; o61.8 & gt; TIM4_DIER.UDE: Update DMA request enabled
// & lt; o61.6 & gt; TIM4_DIER.TIE: Trigger interrupt enabled
// & lt; o61.4 & gt; TIM4_DIER.CC4IE: Capture/Compare 4 interrupt enabled
// & lt; o61.3 & gt; TIM4_DIER.CC3IE: Capture/Compare 3 interrupt enabled
// & lt; o61.2 & gt; TIM4_DIER.CC2IE: Capture/Compare 2 interrupt enabled
// & lt; o61.1 & gt; TIM4_DIER.CC1IE: Capture/Compare 1 interrupt enabled
// & lt; o61.0 & gt; TIM4_DIER.UIE: Update interrupt enabled
// & lt; /e & gt;
//
//
// & lt; /e & gt;
// & lt; /e & gt; End of Timer Configuration
#define __TIMER_SETUP 0 // 0
#define __TIMER_USED 0x0002 // 1
#define __TIMER_DETAILS 0x000A // 2
#define __TIMER_INTERRUPTS 0x0000 // 3
#define __TIM1_PERIOD 0xF4240 // 4
#define __TIM1_PSC 0x0000 // 5
#define __TIM1_ARR 0x0004 // 6
#define __TIM1_RCR 0x0002 // 7
#define __TIM1_CR1 0x0004 // 8
#define __TIM1_CR2 0x0000 // 9
#define __TIM1_SMCR 0x0000 // 10
#define __TIM1_CCMR1 0x0061 // 11
#define __TIM1_CCMR2 0x0068 // 12
#define __TIM1_CCER 0x0000 // 13
#define __TIM1_CCR1 0x0000 // 14
#define __TIM1_CCR2 0x0000 // 15
#define __TIM1_CCR3 0x0000 // 16
#define __TIM1_CCR4 0x0000 // 17
#define __TIM1_BDTR 0x0000 // 18
#define __TIM1_DIER 0x0000 // 19
#define __TIM2_PERIOD 0x00064 // 20
#define __TIM2_PSC 0x0000 // 21
#define __TIM2_ARR 0x0048 // 22
#define __TIM2_CR1 0x0004 // 23
#define __TIM2_CR2 0x0000 // 24
#define __TIM2_SMCR 0x0000 // 25
#define __TIM2_CCMR1 0x6000 // 26
#define __TIM2_CCMR2 0x0060 // 27
#define __TIM2_CCER 0x0100 // 28
#define __TIM2_CCR1 0x001E // 29
#define __TIM2_CCR2 0x1388 // 30
#define __TIM2_CCR3 0x0005 // 31
#define __TIM2_CCR4 0x0000 // 32
#define __TIM2_DIER 0x0000 // 33
#define __TIM3_PERIOD 0x7A120 // 34
#define __TIM3_PSC 0x0000 // 35
#define __TIM3_ARR 0x0004 // 36
#define __TIM3_CR1 0x0000 // 37
#define __TIM3_CR2 0x0000 // 38
#define __TIM3_SMCR 0x0000 // 39
#define __TIM3_CCMR1 0x0000 // 40
#define __TIM3_CCMR2 0x0000 // 41
#define __TIM3_CCER 0x0000 // 42
#define __TIM3_CCR1 0x0000 // 43
#define __TIM3_CCR2 0x0000 // 44
#define __TIM3_CCR3 0x0000 // 45
#define __TIM3_CCR4 0x0000 // 46
#define __TIM3_DIER 0x0000 // 47
#define __TIM4_PERIOD 0x003E8 // 48
#define __TIM4_PSC 0x1C1F // 49
#define __TIM4_ARR 0x270F // 50
#define __TIM4_CR1 0x0004 // 51
#define __TIM4_CR2 0x0000 // 52
#define __TIM4_SMCR 0x0000 // 53
#define __TIM4_CCMR1 0x0000 // 54
#define __TIM4_CCMR2 0x6060 // 55
#define __TIM4_CCER 0x1100 // 56
#define __TIM4_CCR1 0x0000 // 57
#define __TIM4_CCR2 0x0000 // 58
#define __TIM4_CCR3 0x1388 // 59
#define __TIM4_CCR4 0x09C4 // 60
#define __TIM4_DIER 0x0018 // 61
//=========================================================================== USART Configuration
// & lt; e0 & gt; USART Configuration
//--------------------------------------------------------------------------- USART1
// & lt; e1.0 & gt; USART1 : USART #1 enable
// & lt; o4 & gt; Baudrate
// & lt; 9600= & gt; 9600 Baud
// & lt; 14400= & gt; 14400 Baud
// & lt; 19200= & gt; 19200 Baud
// & lt; 28800= & gt; 28800 Baud
// & lt; 38400= & gt; 38400 Baud
// & lt; 56000= & gt; 56000 Baud
// & lt; 57600= & gt; 57600 Baud
// & lt; 115200= & gt; 115200 Baud
// & lt; o5.12 & gt; Data Bits
// & lt; 0= & gt; 8 Data Bits
// & lt; 1= & gt; 9 Data Bits
// & lt; o6.12..13 & gt; Stop Bits
// & lt; 1= & gt; 0.5 Stop Bit
// & lt; 0= & gt; 1 Stop Bit
// & lt; 3= & gt; 1.5 Stop Bits
// & lt; 2= & gt; 2 Stop Bits
// & lt; o7.9..10 & gt; Parity
// & lt; 0= & gt; No Parity
// & lt; 2= & gt; Even Parity
// & lt; 3= & gt; Odd Parity
// & lt; o8.8..9 & gt; Flow Control
// & lt; 0= & gt; None
// & lt; 3= & gt; Hardware
// & lt; o9.2 & gt; Pins used
// & lt; 0= & gt; TX = PA9, RX = PA10
// & lt; 1= & gt; TX = PB6, RX = PB7
// & lt; e3.0 & gt; USART1 interrupts
// & lt; o10.4 & gt; USART1_CR1.IDLEIE: IDLE Interrupt enable
// & lt; o10.5 & gt; USART1_CR1.RXNEIE: RXNE Interrupt enable
// & lt; o10.6 & gt; USART1_CR1.TCIE: Transmission Complete Interrupt enable
// & lt; o10.7 & gt; USART1_CR1.TXEIE: TXE Interrupt enable
// & lt; o10.8 & gt; USART1_CR1.PEIE: PE Interrupt enable
// & lt; o11.6 & gt; USART1_CR2.LBDIE: LIN Break Detection Interrupt enable
// & lt; o12.0 & gt; USART1_CR3.EIE: Error Interrupt enable
// & lt; o12.10 & gt; USART1_CR3.CTSIE: CTS Interrupt enable
// & lt; /e & gt;
// & lt; /e & gt;
//--------------------------------------------------------------------------- USART2
// & lt; e1.1 & gt; USART2 : USART #2 enable
// & lt; o13 & gt; Baudrate
// & lt; 9600= & gt; 9600 Baud
// & lt; 14400= & gt; 14400 Baud
// & lt; 19200= & gt; 19200 Baud
// & lt; 28800= & gt; 28800 Baud
// & lt; 38400= & gt; 38400 Baud
// & lt; 56000= & gt; 56000 Baud
// & lt; 57600= & gt; 57600 Baud
// & lt; 115200= & gt; 115200 Baud
// & lt; o14.12 & gt; Data Bits
// & lt; 0= & gt; 8 Data Bits
// & lt; 1= & gt; 9 Data Bits
// & lt; o15.12..13 & gt; Stop Bits
// & lt; 1= & gt; 0.5 Stop Bit
// & lt; 0= & gt; 1 Stop Bit
// & lt; 3= & gt; 1.5 Stop Bits
// & lt; 2= & gt; 2 Stop Bits
// & lt; o16.9..10 & gt; Parity
// & lt; 0= & gt; No Parity
// & lt; 2= & gt; Even Parity
// & lt; 3= & gt; Odd Parity
// & lt; o17.8..9 & gt; Flow Control
// & lt; 0= & gt; None
// & lt; 3= & gt; Hardware
// & lt; o18.3 & gt; Pins used
// & lt; 0= & gt; CTS = PA0, RTS = PA1, TX = PA2, RX = PA3
// & lt; 1= & gt; CTS = PD3, RTS = PD4, TX = PD5, RX = PD6
// & lt; e3.1 & gt; USART2 interrupts
// & lt; o19.4 & gt; USART1_CR2.IDLEIE: IDLE Interrupt enable
// & lt; o19.5 & gt; USART1_CR2.RXNEIE: RXNE Interrupt enable
// & lt; o19.6 & gt; USART1_CR2.TCIE: Transmission Complete Interrupt enable
// & lt; o19.7 & gt; USART1_CR2.TXEIE: TXE Interrupt enable
// & lt; o19.8 & gt; USART1_CR2.PEIE: PE Interrupt enable
// & lt; o20.6 & gt; USART1_CR2.LBDIE: LIN Break Detection Interrupt enable
// & lt; o21.0 & gt; USART1_CR2.EIE: Error Interrupt enable
// & lt; o21.10 & gt; USART1_CR2.CTSIE: CTS Interrupt enable
// & lt; /e & gt;
// & lt; /e & gt;
//--------------------------------------------------------------------------- USART3
// & lt; e1.2 & gt; USART3 : USART #3 enable
// & lt; o22 & gt; Baudrate
// & lt; 9600= & gt; 9600 Baud
// & lt; 14400= & gt; 14400 Baud
// & lt; 19200= & gt; 19200 Baud
// & lt; 28800= & gt; 28800 Baud
// & lt; 38400= & gt; 38400 Baud
// & lt; 56000= & gt; 56000 Baud
// & lt; 57600= & gt; 57600 Baud
// & lt; 115200= & gt; 115200 Baud
// & lt; o23.12 & gt; Data Bits
// & lt; 0= & gt; 8 Data Bits
// & lt; 1= & gt; 9 Data Bits
// & lt; o24.12..13 & gt; Stop Bits
// & lt; 1= & gt; 0.5 Stop Bit
// & lt; 0= & gt; 1 Stop Bit
// & lt; 3= & gt; 1.5 Stop Bits
// & lt; 2= & gt; 2 Stop Bits
// & lt; o25.9..10 & gt; Parity
// & lt; 0= & gt; No Parity
// & lt; 2= & gt; Even Parity
// & lt; 3= & gt; Odd Parity
// & lt; o26.8..9 & gt; Flow Control
// & lt; 0= & gt; None
// & lt; 3= & gt; Hardware
// & lt; o27.4..5 & gt; Pins used
// & lt; 0= & gt; TX = PB10, RX = PB11, CTS = PB13, RTS = PB14
// & lt; 1= & gt; TX = PC10, RX = PC11, CTS = PB13, RTS = PB14
// & lt; 3= & gt; TX = PD8, RX = PD9, CTS = PD11, RTS = PB12
// & lt; e3.2 & gt; USART3 interrupts
// & lt; o28.4 & gt; USART3_CR1.IDLEIE: IDLE Interrupt enable
// & lt; o28.5 & gt; USART3_CR1.RXNEIE: RXNE Interrupt enable
// & lt; o28.6 & gt; USART3_CR1.TCIE: Transmission Complete Interrupt enable
// & lt; o28.7 & gt; USART3_CR1.TXEIE: TXE Interrupt enable
// & lt; o28.8 & gt; USART3_CR1.PEIE: PE Interrupt enable
// & lt; o29.6 & gt; USART3_CR2.LBDIE: LIN Break Detection Interrupt enable
// & lt; o30.0 & gt; USART3_CR3.EIE: Error Interrupt enable
// & lt; o30.10 & gt; USART3_CR3.CTSIE: CTS Interrupt enable
// & lt; /e & gt;
// & lt; /e & gt;
// & lt; /e & gt; End of USART Configuration
#define __USART_SETUP 1 // 0
#define __USART_USED 0x01 // 1
#define __USART_DETAILS 0x00 // 2
#define __USART_INTERRUPTS 0x00 // 3
#define __USART1_BAUDRATE 9600 // 4
#define __USART1_DATABITS 0x00000000
#define __USART1_STOPBITS 0x00000000
#define __USART1_PARITY 0x00000000
#define __USART1_FLOWCTRL 0x00000000
#define __USART1_REMAP 0x00000000
#define __USART1_CR1 0x00000000
#define __USART1_CR2 0x00000000
#define __USART1_CR3 0x00000000
#define __USART2_BAUDRATE 9600 // 13
#define __USART2_DATABITS 0x00000000
#define __USART2_STOPBITS 0x00000000
#define __USART2_PARITY 0x00000000
#define __USART2_FLOWCTRL 0x00000000
#define __USART2_REMAP 0x00000008
#define __USART2_CR1 0x00000000
#define __USART2_CR2 0x00000000
#define __USART2_CR3 0x00000000
#define __USART3_BAUDRATE 9600 // 22
#define __USART3_DATABITS 0x00000000
#define __USART3_STOPBITS 0x00000000
#define __USART3_PARITY 0x00000000
#define __USART3_FLOWCTRL 0x00000000
#define __USART3_REMAP 0x00000000
#define __USART3_CR1 0x00000000
#define __USART3_CR2 0x00000000
#define __USART3_CR3 0x00000000
//=========================================================================== External interrupt/event Configuration
// & lt; e0 & gt; External interrupt/event Configuration
//--------------------------------------------------------------------------- EXTI line 0
// & lt; e1.0 & gt; EXTI0: EXTI line 0 enable
// & lt; o2.0 & gt; interrupt enable
// & lt; o3.0 & gt; generate interrupt
// & lt; o4.0 & gt; generate event
// & lt; o5.0 & gt; use rising trigger for interrupt/event
// & lt; o6.0 & gt; use falling trigger for interrupt/event
// & lt; o7.0..3 & gt; use pin for for interrupt/event
// & lt; i & gt; Default: pin = PA0
// & lt; 0= & gt; pin = PA0
// & lt; 1= & gt; pin = PB0
// & lt; 2= & gt; pin = PC0
// & lt; 3= & gt; pin = PD0
// & lt; 4= & gt; pin = PE0
// & lt; /e & gt;
//--------------------------------------------------------------------------- EXTI line 1
// & lt; e1.1 & gt; EXTI1: EXTI line 1 enable
// & lt; o2.1 & gt; interrupt enable
// & lt; o3.1 & gt; generate interrupt
// & lt; o4.1 & gt; generate event
// & lt; o5.1 & gt; use rising trigger for interrupt/event
// & lt; o6.1 & gt; use falling trigger for interrupt/event
// & lt; o7.4..7 & gt; use pin for for interrupt/event
// & lt; i & gt; Default: pin = PA1
// & lt; 0= & gt; pin = PA1
// & lt; 1= & gt; pin = PB1
// & lt; 2= & gt; pin = PC1
// & lt; 3= & gt; pin = PD1
// & lt; 4= & gt; pin = PE1
// & lt; /e & gt;
//--------------------------------------------------------------------------- EXTI line 2
// & lt; e1.2 & gt; EXTI2: EXTI line 2 enable
// & lt; o2.2 & gt; interrupt enable
// & lt; o3.2 & gt; generate interrupt
// & lt; o4.2 & gt; generate event
// & lt; o5.2 & gt; use rising trigger for interrupt/event
// & lt; o6.2 & gt; use falling trigger for interrupt/event
// & lt; o7.8..11 & gt; use pin for for interrupt/event
// & lt; i & gt; Default: pin = PA2
// & lt; 0= & gt; pin = PA2
// & lt; 1= & gt; pin = PB2
// & lt; 2= & gt; pin = PC2
// & lt; 3= & gt; pin = PD2
// & lt; 4= & gt; pin = PE2
// & lt; /e & gt;
//--------------------------------------------------------------------------- EXTI line 3
// & lt; e1.3 & gt; EXTI3: EXTI line 3 enable
// & lt; o2.3 & gt; interrupt enable
// & lt; o3.3 & gt; generate interrupt
// & lt; o4.3 & gt; generate event
// & lt; o5.3 & gt; use rising trigger for interrupt/event
// & lt; o6.3 & gt; use falling trigger for interrupt/event
// & lt; o7.12..15 & gt; use pin for for interrupt/event
// & lt; i & gt; Default: pin = PA3
// & lt; 0= & gt; pin = PA3
// & lt; 1= & gt; pin = PB3
// & lt; 2= & gt; pin = PC3
// & lt; 3= & gt; pin = PD3
// & lt; 4= & gt; pin = PE3
// & lt; /e & gt;
//--------------------------------------------------------------------------- EXTI line 4
// & lt; e1.4 & gt; EXTI4: EXTI line 4 enable
// & lt; o2.4 & gt; interrupt enable
// & lt; o3.4 & gt; generate interrupt
// & lt; o4.4 & gt; generate event
// & lt; o5.4 & gt; use rising trigger for interrupt/event
// & lt; o6.4 & gt; use falling trigger for interrupt/event
// & lt; o8.0..3 & gt; use pin for for interrupt/event
// & lt; i & gt; Default: pin = PA4
// & lt; 0= & gt; pin = PA4
// & lt; 1= & gt; pin = PB4
// & lt; 2= & gt; pin = PC4
// & lt; 3= & gt; pin = PD4
// & lt; 4= & gt; pin = PE4
// & lt; /e & gt;
//--------------------------------------------------------------------------- EXTI line 5
// & lt; e1.5 & gt; EXTI5: EXTI line 5 enable
// & lt; o2.5 & gt; interrupt enable
// & lt; o3.5 & gt; generate interrupt
// & lt; o4.5 & gt; generate event
// & lt; o5.5 & gt; use rising trigger for interrupt/event
// & lt; o6.5 & gt; use falling trigger for interrupt/event
// & lt; o8.4..7 & gt; use pin for for interrupt/event
// & lt; i & gt; Default: pin = PA5
// & lt; 0= & gt; pin = PA5
// & lt; 1= & gt; pin = PB5
// & lt; 2= & gt; pin = PC5
// & lt; 3= & gt; pin = PD5
// & lt; 4= & gt; pin = PE5
// & lt; /e & gt;
//--------------------------------------------------------------------------- EXTI line 6
// & lt; e1.6 & gt; EXTI6: EXTI line 6 enable
// & lt; o2.6 & gt; interrupt enable
// & lt; o3.6 & gt; generate interrupt
// & lt; o4.6 & gt; generate event
// & lt; o5.6 & gt; use rising trigger for interrupt/event
// & lt; o6.6 & gt; use falling trigger for interrupt/event
// & lt; o8.8..11 & gt; use pin for for interrupt/event
// & lt; i & gt; Default: pin = PA6
// & lt; 0= & gt; pin = PA6
// & lt; 1= & gt; pin = PB6
// & lt; 2= & gt; pin = PC6
// & lt; 3= & gt; pin = PD6
// & lt; 4= & gt; pin = PE6
// & lt; /e & gt;
//--------------------------------------------------------------------------- EXTI line 7
// & lt; e1.7 & gt; EXTI7: EXTI line 7 enable
// & lt; o2.7 & gt; interrupt enable
// & lt; o3.7 & gt; generate interrupt
// & lt; o4.7 & gt; generate event
// & lt; o5.7 & gt; use rising trigger for interrupt/event
// & lt; o6.7 & gt; use falling trigger for interrupt/event
// & lt; o8.12..15 & gt; use pin for for interrupt/event
// & lt; i & gt; Default: pin = PA7
// & lt; 0= & gt; pin = PA7
// & lt; 1= & gt; pin = PB7
// & lt; 2= & gt; pin = PC7
// & lt; 3= & gt; pin = PD7
// & lt; 4= & gt; pin = PE7
// & lt; /e & gt;
//--------------------------------------------------------------------------- EXTI line 8
// & lt; e1.8 & gt; EXTI8: EXTI line 8 enable
// & lt; o2.8 & gt; interrupt enable
// & lt; o3.8 & gt; generate interrupt
// & lt; o4.8 & gt; generate event
// & lt; o5.8 & gt; use rising trigger for interrupt/event
// & lt; o6.8 & gt; use falling trigger for interrupt/event
// & lt; o9.0..3 & gt; use pin for for interrupt/event
// & lt; i & gt; Default: pin = PA8
// & lt; 0= & gt; pin = PA8
// & lt; 1= & gt; pin = PB8
// & lt; 2= & gt; pin = PC8
// & lt; 3= & gt; pin = PD8
// & lt; 4= & gt; pin = PE8
// & lt; /e & gt;
//--------------------------------------------------------------------------- EXTI line 9
// & lt; e1.9 & gt; EXTI9: EXTI line 9 enable
// & lt; o2.9 & gt; interrupt enable
// & lt; o3.9 & gt; generate interrupt
// & lt; o4.9 & gt; generate event
// & lt; o5.9 & gt; use rising trigger for interrupt/event
// & lt; o6.9 & gt; use falling trigger for interrupt/event
// & lt; o9.4..7 & gt; use pin for for interrupt/event
// & lt; i & gt; Default: pin = PA9
// & lt; 0= & gt; pin = PA9
// & lt; 1= & gt; pin = PB9
// & lt; 2= & gt; pin = PC9
// & lt; 3= & gt; pin = PD9
// & lt; 4= & gt; pin = PE9
// & lt; /e & gt;
//--------------------------------------------------------------------------- EXTI line 10
// & lt; e1.10 & gt; EXTI10: EXTI line 10 enable
// & lt; o2.10 & gt; interrupt enable
// & lt; o3.10 & gt; generate interrupt
// & lt; o4.10 & gt; generate event
// & lt; o5.10 & gt; use rising trigger for interrupt/event
// & lt; o6.10 & gt; use falling trigger for interrupt/event
// & lt; o9.8..11 & gt; use pin for for interrupt/event
// & lt; i & gt; Default: pin = PA10
// & lt; 0= & gt; pin = PA10
// & lt; 1= & gt; pin = PB10
// & lt; 2= & gt; pin = PC10
// & lt; 3= & gt; pin = PD10
// & lt; 4= & gt; pin = PE10
// & lt; /e & gt;
//--------------------------------------------------------------------------- EXTI line 11
// & lt; e1.11 & gt; EXTI11: EXTI line 11 enable
// & lt; o2.11 & gt; interrupt enable
// & lt; o3.11 & gt; generate interrupt
// & lt; o4.11 & gt; generate event
// & lt; o5.11 & gt; use rising trigger for interrupt/event
// & lt; o6.11 & gt; use falling trigger for interrupt/event
// & lt; o9.12..15 & gt; use pin for for interrupt/event
// & lt; i & gt; Default: pin = PA11
// & lt; 0= & gt; pin = PA11
// & lt; 1= & gt; pin = PB11
// & lt; 2= & gt; pin = PC11
// & lt; 3= & gt; pin = PD11
// & lt; 4= & gt; pin = PE11
// & lt; /e & gt;
//--------------------------------------------------------------------------- EXTI line 12
// & lt; e1.12 & gt; EXTI12: EXTI line 12 enable
// & lt; o2.12 & gt; interrupt enable
// & lt; o3.12 & gt; generate interrupt
// & lt; o4.12 & gt; generate event
// & lt; o5.12 & gt; use rising trigger for interrupt/event
// & lt; o6.12 & gt; use falling trigger for interrupt/event
// & lt; o10.0..3 & gt; use pin for for interrupt/event
// & lt; i & gt; Default: pin = PA12
// & lt; 0= & gt; pin = PA12
// & lt; 1= & gt; pin = PB12
// & lt; 2= & gt; pin = PC12
// & lt; 3= & gt; pin = PD12
// & lt; 4= & gt; pin = PE12
// & lt; /e & gt;
//--------------------------------------------------------------------------- EXTI line 13
// & lt; e1.13 & gt; EXTI13: EXTI line 13 enable
// & lt; o2.13 & gt; interrupt enable
// & lt; o3.13 & gt; generate interrupt
// & lt; o4.13 & gt; generate event
// & lt; o5.13 & gt; use rising trigger for interrupt/event
// & lt; o6.13 & gt; use falling trigger for interrupt/event
// & lt; o10.4..7 & gt; use pin for for interrupt/event
// & lt; i & gt; Default: pin = PA13
// & lt; 0= & gt; pin = PA13
// & lt; 1= & gt; pin = PB13
// & lt; 2= & gt; pin = PC13
// & lt; 3= & gt; pin = PD13
// & lt; 4= & gt; pin = PE13
// & lt; /e & gt;
//--------------------------------------------------------------------------- EXTI line 14
// & lt; e1.14 & gt; EXTI14: EXTI line 14 enable
// & lt; o2.14 & gt; interrupt enable
// & lt; o3.14 & gt; generate interrupt
// & lt; o4.14 & gt; generate event
// & lt; o5.14 & gt; use rising trigger for interrupt/event
// & lt; o6.14 & gt; use falling trigger for interrupt/event
// & lt; o10.8..11 & gt; use pin for for interrupt/event
// & lt; i & gt; Default: pin = PA14
// & lt; 0= & gt; pin = PA14
// & lt; 1= & gt; pin = PB14
// & lt; 2= & gt; pin = PC14
// & lt; 3= & gt; pin = PD14
// & lt; 4= & gt; pin = PE14
// & lt; /e & gt;
//--------------------------------------------------------------------------- EXTI line 15
// & lt; e1.15 & gt; EXTI15: EXTI line 15 enable
// & lt; o2.15 & gt; interrupt enable
// & lt; o3.15 & gt; generate interrupt
// & lt; o4.15 & gt; generate event
// & lt; o5.15 & gt; use rising trigger for interrupt/event
// & lt; o6.15 & gt; use falling trigger for interrupt/event
// & lt; o10.12..15 & gt; use pin for for interrupt/event
// & lt; i & gt; Default: pin = PA15
// & lt; 0= & gt; pin = PA15
// & lt; 1= & gt; pin = PB15
// & lt; 2= & gt; pin = PC15
// & lt; 3= & gt; pin = PD15
// & lt; 4= & gt; pin = PE15
// & lt; /e & gt;
// & lt; /e & gt; End of External interrupt/event Configuration
#define __EXTI_SETUP 0 // 0
#define __EXTI_USED 0x0000 // 1
#define __EXTI_INTERRUPTS 0x00000000 // 2
#define __EXTI_IMR 0x00000000 // 3
#define __EXTI_EMR 0x00000000 // 4
#define __EXTI_RTSR 0x00000000 // 5
#define __EXTI_FTSR 0x00000000 // 6
#define __AFIO_EXTICR1 0x00000000 // 7
#define __AFIO_EXTICR2 0x00000000 // 8
#define __AFIO_EXTICR3 0x00000000 // 9
#define __AFIO_EXTICR4 0x00000000 // 10
//=========================================================================== Tamper Configuration
// & lt; e0 & gt; Tamper Configuration
// & lt; o1.0 & gt; Tamper Pin enable
// & lt; o1.1 & gt; Tamper pin active level
// & lt; i & gt; Default: active level = HIGH
// & lt; 0= & gt; active level = HIGH
// & lt; 1= & gt; active level = LOW
// & lt; o2.2 & gt; Tamper interrupt enable
// & lt; /e & gt; End of Tamper Configuration
#define __TAMPER_SETUP 0 // 0
#define __BKP_CR 0x00000000 // 1
#define __BKP_CSR 0x00000000 // 2
//=========================================================================== General purpose I/O Configuration
// & lt; e0 & gt; General purpose I/O Configuration
//--------------------------------------------------------------------------- GPIO port A
// & lt; e1.0 & gt; GPIOA : GPIO port A used
// & lt; o2.0..3 & gt; Pin 0 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o2.4..7 & gt; Pin 1 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o2.8..11 & gt; Pin 2 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o2.12..15 & gt; Pin 3 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o2.16..19 & gt; Pin 4 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
& lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz);
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o2.20..23 & gt; Pin 5 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
& lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o2.24..27 & gt; Pin 6 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
& lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o2.28..31 & gt; Pin 7 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
& lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o3.0..3 & gt; Pin 8 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o3.4..7 & gt; Pin 9 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o3.8..11 & gt; Pin 10 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o3.12..15 & gt; Pin 11 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o3.16..19 & gt; Pin 12 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o3.20..23 & gt; Pin 13 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o3.24..27 & gt; Pin 14 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o3.28..31 & gt; Pin 15 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; /e & gt;
//--------------------------------------------------------------------------- GPIO port B
// & lt; e1.1 & gt; GPIOB : GPIO port B used
// & lt; o4.0..3 & gt; Pin 0 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o4.4..7 & gt; Pin 1 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o4.8..11 & gt; Pin 2 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o4.12..15 & gt; Pin 3 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o4.16..19 & gt; Pin 4 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o4.20..23 & gt; Pin 5 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o4.24..27 & gt; Pin 6 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o4.28..31 & gt; Pin 7 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o5.0..3 & gt; Pin 8 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o5.4..7 & gt; Pin 9 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o5.8..11 & gt; Pin 10 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o5.12..15 & gt; Pin 11 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o5.16..19 & gt; Pin 12 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o5.20..23 & gt; Pin 13 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o5.24..27 & gt; Pin 14 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o5.28..31 & gt; Pin 15 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; /e & gt;
//--------------------------------------------------------------------------- GPIO port C
// & lt; e1.2 & gt; GPIOC : GPIO port C used
// & lt; o6.0..3 & gt; Pin 0 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o6.4..7 & gt; Pin 1 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o6.8..11 & gt; Pin 2 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o6.12..15 & gt; Pin 3 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o6.16..19 & gt; Pin 4 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o6.20..23 & gt; Pin 5 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o6.24..27 & gt; Pin 6 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o6.28..31 & gt; Pin 7 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o7.0..3 & gt; Pin 8 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o7.4..7 & gt; Pin 9 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o7.8..11 & gt; Pin 10 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o7.12..15 & gt; Pin 11 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o7.16..19 & gt; Pin 12 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o7.20..23 & gt; Pin 13 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o7.24..27 & gt; Pin 14 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o7.28..31 & gt; Pin 15 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; /e & gt;
//--------------------------------------------------------------------------- GPIO port D
// & lt; e1.3 & gt; GPIOD : GPIO port D used
// & lt; o8.0..3 & gt; Pin 0 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o8.4..7 & gt; Pin 1 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o8.8..11 & gt; Pin 2 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o8.12..15 & gt; Pin 3 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o8.16..19 & gt; Pin 4 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o8.20..23 & gt; Pin 5 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o8.24..27 & gt; Pin 6 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o8.28..31 & gt; Pin 7 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o9.0..3 & gt; Pin 8 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o9.4..7 & gt; Pin 9 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o9.8..11 & gt; Pin 10 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o9.12..15 & gt; Pin 11 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o9.16..19 & gt; Pin 12 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o9.20..23 & gt; Pin 13 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o9.24..27 & gt; Pin 14 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o9.28..31 & gt; Pin 15 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; /e & gt;
//--------------------------------------------------------------------------- GPIO port E
// & lt; e1.4 & gt; GPIOE : GPIO port E used
// & lt; o10.0..3 & gt; Pin 0 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o10.4..7 & gt; Pin 1 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o10.8..11 & gt; Pin 2 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o10.12..15 & gt; Pin 3 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o10.16..19 & gt; Pin 4 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o10.20..23 & gt; Pin 5 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o10.24..27 & gt; Pin 6 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o10.28..31 & gt; Pin 7 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o11.0..3 & gt; Pin 8 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o11.4..7 & gt; Pin 9 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o11.8..11 & gt; Pin 10 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o11.12..15 & gt; Pin 11 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o11.16..19 & gt; Pin 12 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o11.20..23 & gt; Pin 13 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o11.24..27 & gt; Pin 14 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; o11.28..31 & gt; Pin 15 used as
// & lt; 0= & gt; Analog Input
// & lt; 4= & gt; Floating Input
// & lt; 8= & gt; Input with pull-up / pull-down
// & lt; 1= & gt; General Purpose Output push-pull (max speed 10MHz)
// & lt; 5= & gt; General Purpose Output open-drain (max speed 10MHz)
// & lt; 2= & gt; General Purpose Output push-pull (max speed 2MHz)
// & lt; 6= & gt; General Purpose Output open-drain (max speed 2MHz)
// & lt; 3= & gt; General Purpose Output push-pull (max speed 50MHz)
// & lt; 7= & gt; General Purpose Output open-drain (max speed 50MHz)
// & lt; 9= & gt; Alternate Function push-pull (max speed 10MHz)
// & lt; 13= & gt; Alternate Function open-drain (max speed 10MHz)
// & lt; 10= & gt; Alternate Function push-pull (max speed 2MHz)
// & lt; 14= & gt; Alternate Function open-drain (max speed 2MHz)
// & lt; 11= & gt; Alternate Function push-pull (max speed 50MHz)
// & lt; 15= & gt; Alternate Function open-drain (max speed 50MHz)
// & lt; /e1.4 & gt;
// & lt; /e & gt; End of General purpose I/O Configuration
#define __GPIO_SETUP 1
#define __GPIO_USED 0x0F
#define __GPIOA_CRL 0x13110104
#define __GPIOA_CRH 0x00000330
#define __GPIOB_CRL 0x00300000
#define __GPIOB_CRH 0x44444000
#define __GPIOC_CRL 0x00000000
#define __GPIOC_CRH 0x00400000
#define __GPIOD_CRL 0x03300000
#define __GPIOD_CRH 0x00000030
#define __GPIOE_CRL 0x00000000
#define __GPIOE_CRH 0x00000000
//=========================================================================== Embedded Flash Configuration
// & lt; e0 & gt; Embedded Flash Configuration
// & lt; h & gt; Flash Access Control Configuration (FLASH_ACR)
// & lt; o1.0..2 & gt; LATENCY: Latency
// & lt; i & gt; Default: 2 wait states
// & lt; 0= & gt; 0 wait states
// & lt; 1= & gt; 1 wait states
// & lt; 2= & gt; 2 wait states
// & lt; o1.3 & gt; HLFCYA: Flash Half Cycle Access Enable
// & lt; o1.4 & gt; PRFTBE: Prefetch Buffer Enable
// & lt; o1.5 & gt; PRFTBS: Prefetch Buffer Status Enable
// & lt; /h & gt;
// & lt; /e & gt;
#define __EFI_SETUP 1
#define __EFI_ACR_Val 0x00000012
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
#define CFGR_SWS_MASK 0x0000000C // Mask for used SYSCLK
#define CFGR_SW_MASK 0x00000003 // Mask for used SYSCLK
#define CFGR_PLLMULL_MASK 0x003C0000 // Mask for PLL multiplier
#define CFGR_PLLXTPRE_MASK 0x00020000 // Mask for PLL HSE devider
#define CFGR_PLLSRC_MASK 0x00010000 // Mask for PLL clock source
#define CFGR_HPRE_MASK 0x000000F0 // Mask for AHB prescaler
#define CFGR_PRE1_MASK 0x00000700 // Mask for APB1 prescaler
#define CFGR_PRE2_MASK 0x00003800 // Mask for APB2 prescaler
/*----------------------------------------------------------------------------
Define SYSCLK
*----------------------------------------------------------------------------*/
#define __HSI 8000000UL
//#define __HSE 8000000UL
#define __PLLMULL (((__RCC_CFGR_VAL & CFGR_PLLMULL_MASK) & gt; & gt; 18) + 2)
#if ((__RCC_CFGR_VAL & CFGR_SW_MASK) == 0x00)
#define __SYSCLK __HSI // HSI is used as system clock
#elif ((__RCC_CFGR_VAL & CFGR_SW_MASK) == 0x01)
#define __SYSCLK __HSE // HSE is used as system clock
#elif ((__RCC_CFGR_VAL & CFGR_SW_MASK) == 0x02)
#if (__RCC_CFGR_VAL & CFGR_PLLSRC_MASK) // HSE is PLL clock source
#if (__RCC_CFGR_VAL & CFGR_PLLXTPRE_MASK) // HSE/2 is used
#define __SYSCLK ((__HSE & gt; & gt; 2) * __PLLMULL)// SYSCLK = HSE/2 * pllmull
#else // HSE is used
#define __SYSCLK ((__HSE & gt; & gt; 0) * __PLLMULL)// SYSCLK = HSE * pllmul
#endif
#else // HSI/2 is PLL clock source
#define __SYSCLK ((__HSI & gt; & gt; 2) * __PLLMULL) // SYSCLK = HSI/2 * pllmul
#endif
#else
#error " ask for help "
#endif
/*----------------------------------------------------------------------------
Define HCLK
*----------------------------------------------------------------------------*/
#define __HCLKPRESC ((__RCC_CFGR_VAL & CFGR_HPRE_MASK) & gt; & gt; 4)
#if (__HCLKPRESC & 0x08)
#define __HCLK (__SYSCLK & gt; & gt; ((__HCLKPRESC & 0x07)+1))
#else
#define __HCLK (__SYSCLK)
#endif
/*----------------------------------------------------------------------------
Define PCLK1
*----------------------------------------------------------------------------*/
#define __PCLK1PRESC ((__RCC_CFGR_VAL & CFGR_PRE1_MASK) & gt; & gt; 8)
#if (__PCLK1PRESC & 0x04)
#define __PCLK1 (__HCLK & gt; & gt; ((__PCLK1PRESC & 0x03)+1))
#else
#define __PCLK1 (__HCLK)
#endif
/*----------------------------------------------------------------------------
Define PCLK2
*----------------------------------------------------------------------------*/
#define __PCLK2PRESC ((__RCC_CFGR_VAL & CFGR_PRE2_MASK) & gt; & gt; 11)
#if (__PCLK2PRESC & 0x04)
#define __PCLK2 (__HCLK & gt; & gt; ((__PCLK2PRESC & 0x03)+1))
#else
#define __PCLK2 (__HCLK)
#endif
/*----------------------------------------------------------------------------
Define IWDG PR and RLR settings
*----------------------------------------------------------------------------*/
#if (__IWDG_PERIOD & gt; 16384000UL)
#define __IWDG_PR (6)
#define __IWDGCLOCK (32000UL/256)
#elif (__IWDG_PERIOD & gt; 8192000UL)
#define __IWDG_PR (5)
#define __IWDGCLOCK (32000UL/128)
#elif (__IWDG_PERIOD & gt; 4096000UL)
#define __IWDG_PR (4)
#define __IWDGCLOCK (32000UL/64)
#elif (__IWDG_PERIOD & gt; 2048000UL)
#define __IWDG_PR (3)
#define __IWDGCLOCK (32000UL/32)
#elif (__IWDG_PERIOD & gt; 1024000UL)
#define __IWDG_PR (2)
#define __IWDGCLOCK (32000UL/16)
#elif (__IWDG_PERIOD & gt; 512000UL)
#define __IWDG_PR (1)
#define __IWDGCLOCK (32000UL/8)
#else
#define __IWDG_PR (0)
#define __IWDGCLOCK (32000UL/4)
#endif
#define __IWGDCLK (32000UL/(0x04 & lt; & lt; __IWDG_PR))
#define __IWDG_RLR (__IWDG_PERIOD*__IWGDCLK/1000000UL-1)
/*----------------------------------------------------------------------------
Define SYSTICKCLK
*----------------------------------------------------------------------------*/
#if (__SYSTICK_CTRL_VAL & 0x04)
#define __SYSTICKCLK (__HCLK)
#else
#define __SYSTICKCLK (__HCLK/8)
#endif
/*----------------------------------------------------------------------------
Define RTCCLK
*----------------------------------------------------------------------------*/
#if ((__RTC_CLKSRC_VAL & 0x00000300) == 0x00000000)
#define __RTCCLK (0)
#elif ((__RTC_CLKSRC_VAL & 0x00000300) == 0x00000100)
#define __RTCCLK (32768)
#elif ((__RTC_CLKSRC_VAL & 0x00000300) == 0x00000200)
#define __RTCCLK (32000)
#elif ((__RTC_CLKSRC_VAL & 0x00000300) == 0x00000300)
#define __RTCCLK (__HSE/128)
#endif
/*----------------------------------------------------------------------------
Define TIM1CLK
*----------------------------------------------------------------------------*/
#if (__PCLK2PRESC & 0x04)
#define __TIM1CLK (2*__PCLK2)
#else
#define __TIM1CLK (__PCLK2)
#endif
/*----------------------------------------------------------------------------
Define TIMXCLK
*----------------------------------------------------------------------------*/
#if (__PCLK1PRESC & 0x04)
#define __TIMXCLK (2*__PCLK1)
#else
#define __TIMXCLK (__PCLK1)
#endif
/*----------------------------------------------------------------------------
Define Real Time Clock CNT and ALR settings
*----------------------------------------------------------------------------*/
#define __RTC_CNT_TICKS ((__RTC_TIME_H *3600UL)+(__RTC_TIME_M *60UL)+(__RTC_TIME_S) )
#define __RTC_ALR_TICKS ((__RTC_ALARM_H*3600UL)+(__RTC_ALARM_M*60UL)+(__RTC_ALARM_S))
#define __RTC_CNT (__RTC_CNT_TICKS*1000UL/__RTC_PERIOD)
#define __RTC_ALR (__RTC_ALR_TICKS*1000UL/__RTC_PERIOD)
/*----------------------------------------------------------------------------
Define Timer PSC and ARR settings
*----------------------------------------------------------------------------*/
#define __VAL(__TIMCLK, __PERIOD) ((__TIMCLK/1000000UL)*__PERIOD)
//#define __PSC(__TIMCLK, __PERIOD) ((__VAL(__TIMCLK, __PERIOD)-1) & gt; & gt; 15)
#define __PSC(__TIMCLK, __PERIOD) (((__VAL(__TIMCLK, __PERIOD)+49999UL)/50000UL) - 1)
#define __ARR(__TIMCLK, __PERIOD) ((__VAL(__TIMCLK, __PERIOD)/(__PSC(__TIMCLK, __PERIOD)+1)) - 1)
/*----------------------------------------------------------------------------
Define Baudrate setting (BRR) for USART1
*----------------------------------------------------------------------------*/
#define __DIV(__PCLK, __BAUD) ((__PCLK*25)/(4*__BAUD))
#define __DIVMANT(__PCLK, __BAUD) (__DIV(__PCLK, __BAUD)/100)
#define __DIVFRAQ(__PCLK, __BAUD) (((__DIV(__PCLK, __BAUD) - (__DIVMANT(__PCLK, __BAUD) * 100)) * 16 + 50) / 100)
#define __USART_BRR(__PCLK, __BAUD) ((__DIVMANT(__PCLK, __BAUD) & lt; & lt; 4)|(__DIVFRAQ(__PCLK, __BAUD) & 0x0F))
/*----------------------------------------------------------------------------
STM32 embedded Flash interface setup.
initializes the ACR register
*----------------------------------------------------------------------------*/
void stm32_EfiSetup (void) {
FLASH- & gt; ACR = __EFI_ACR_Val; // set access control register
}
/*----------------------------------------------------------------------------
STM32 clock setup.
initializes the RCC register
*----------------------------------------------------------------------------*/
void stm32_ClockSetup (void) {
/* Clock Configuration*/
RCC- & gt; CFGR = __RCC_CFGR_VAL; // set clock configuration register
RCC- & gt; CR = __RCC_CR_VAL; // set clock control register
if (__RCC_CR_VAL & RCC_CR_HSION) { // if HSI enabled
while ((RCC- & gt; CR & RCC_CR_HSIRDY) == 0); // Wait for HSIRDY = 1 (HSI is ready)
}
if (__RCC_CR_VAL & RCC_CR_HSEON) { // if HSE enabled
while ((RCC- & gt; CR & RCC_CR_HSERDY) == 0); // Wait for HSERDY = 1 (HSE is ready)
}
if (__RCC_CR_VAL & RCC_CR_PLLON) { // if PLL enabled
while ((RCC- & gt; CR & RCC_CR_PLLRDY) == 0); // Wait for PLLRDY = 1 (PLL is ready)
}
/* Wait till SYSCLK is stabilized (depending on selected clock) */
while ((RCC- & gt; CFGR & RCC_CFGR_SWS) != ((__RCC_CFGR_VAL & lt; & lt; 2) & RCC_CFGR_SWS));
} // end of stm32_ClockSetup
/*----------------------------------------------------------------------------
STM32 Independent watchdog setup.
initializes the IWDG register
*----------------------------------------------------------------------------*/
void stm32_IwdgSetup (void) {
// RCC- & gt; CSR |= (1 & lt; & lt; 0); // LSI enable, necessary for IWDG
// while ((RCC- & gt; CSR & (1 & lt; & lt; 1)) == 0); // wait till LSI is ready
IWDG- & gt; KR = 0x5555; // enable write to PR, RLR
IWDG- & gt; PR = __IWDG_PR; // Init prescaler
IWDG- & gt; RLR = __IWDG_RLR; // Init RLR
IWDG- & gt; KR = 0xAAAA; // Reload the watchdog
IWDG- & gt; KR = 0xCCCC; // Start the watchdog
} // end of stm32_IwdgSetup
/*----------------------------------------------------------------------------
STM32 System Timer setup.
initializes the SysTick register
*----------------------------------------------------------------------------*/
void stm32_SysTickSetup (void) {
#if ((__SYSTICK_PERIOD*(__SYSTICKCLK/1000)-1) & gt; 0xFFFFFF) // reload value to large
#error " Reload Value to large! Please use 'HCLK/8' as System Timer clock source or smaller period "
#else
SysTick- & gt; LOAD = __SYSTICK_PERIOD*(__SYSTICKCLK/1000)-1; // set reload register
SysTick- & gt; CTRL = __SYSTICK_CTRL_VAL; // set clock source and Interrupt enable
SysTick- & gt; VAL = 0; // clear the counter
SysTick- & gt; CTRL |= SYSTICK_CSR_ENABLE; // enable the counter
#endif
} // end of stm32_SysTickSetup
/*----------------------------------------------------------------------------
STM32 Real Time Clock setup.
initializes the RTC Prescaler and RTC counter register
*----------------------------------------------------------------------------*/
void stm32_RtcSetup (void) {
RCC- & gt; APB1ENR |= RCC_APB1ENR_PWREN; // enable clock for Power interface
PWR- & gt; CR |= PWR_CR_DBP; // enable access to RTC, BDC registers
if ((__RTC_CLKSRC_VAL & RCC_BDCR_RTCSEL) == 0x00000100) { // LSE is RTC clock source
RCC- & gt; BDCR |= RCC_BDCR_LSEON; // enable LSE
while ((RCC- & gt; BDCR & RCC_BDCR_LSERDY) == 0); // Wait for LSERDY = 1 (LSE is ready)
}
RCC- & gt; BDCR |= (__RTC_CLKSRC_VAL | RCC_BDCR_RTCEN); // set RTC clock source, enable RTC clock
// RTC- & gt; CRL & = ~(1 & lt; & lt; 3); // reset Registers Synchronized Flag
// while ((RTC- & gt; CRL & (1 & lt; & lt; 3)) == 0); // wait until registers are synchronized
RTC- & gt; CRL |= RTC_CRL_CNF; // set configuration mode
RTC- & gt; PRLH = ((__RTC_PERIOD*__RTCCLK/1000-1) & gt; & gt; 16) & 0x00FF; // set prescaler load register high
RTC- & gt; PRLL = ((__RTC_PERIOD*__RTCCLK/1000-1) ) & 0xFFFF; // set prescaler load register low
RTC- & gt; CNTH = ((__RTC_CNT) & gt; & gt; 16) & 0xFFFF; // set counter high
RTC- & gt; CNTL = ((__RTC_CNT) ) & 0xFFFF; // set counter low
RTC- & gt; ALRH = ((__RTC_ALR) & gt; & gt; 16) & 0xFFFF; // set alarm high
RTC- & gt; ALRL = ((__RTC_ALR) ) & 0xFFFF; // set alarm low
if (__RTC_INTERRUPTS) { // RTC interrupts used
RTC- & gt; CRH = __RTC_CRH; // enable RTC interrupts
NVIC- & gt; ISER[0] |= (1 & lt; & lt; (RTC_IRQChannel & 0x1F)); // enable interrupt
}
RTC- & gt; CRL & = ~RTC_CRL_CNF; // reset configuration mode
while ((RTC- & gt; CRL & RTC_CRL_RTOFF) == 0); // wait until write is finished
PWR- & gt; CR & = ~PWR_CR_DBP; // disable access to RTC registers
} // end of stm32_RtcSetup
/*----------------------------------------------------------------------------
STM32 Timer setup.
initializes the Timer register
*----------------------------------------------------------------------------*/
void stm32_TimerSetup (void) {
if (__TIMER_USED & 0x01) { // TIM1 used
RCC- & gt; APB2ENR |= RCC_APB2ENR_TIM1EN; // enable clock for TIM1
TIM1- & gt; PSC = __PSC(__TIM1CLK, __TIM1_PERIOD); // set prescaler
TIM1- & gt; ARR = __ARR(__TIM1CLK, __TIM1_PERIOD); // set auto-reload
TIM1- & gt; RCR = __TIM1_RCR; // set repetition counter
TIM1- & gt; CR1 = 0; // reset command register 1
TIM1- & gt; CR2 = 0; // reset command register 2
if (__TIMER_DETAILS & 0x01) { // detailed settings used
TIM1- & gt; PSC = __TIM1_PSC; // set prescaler
TIM1- & gt; ARR = __TIM1_ARR; // set auto-reload
TIM1- & gt; CCR1 = __TIM1_CCR1; //
TIM1- & gt; CCR2 = __TIM1_CCR2; //
TIM1- & gt; CCR3 = __TIM1_CCR3; //
TIM1- & gt; CCR4 = __TIM1_CCR4; //
TIM1- & gt; CCMR1 = __TIM1_CCMR1; //
TIM1- & gt; CCMR2 = __TIM1_CCMR2; //
TIM1- & gt; CCER = __TIM1_CCER; // set capture/compare enable register
TIM1- & gt; CR1 = __TIM1_CR1; // set command register 1
TIM1- & gt; CR2 = __TIM1_CR2; // set command register 2
}
if (__TIMER_INTERRUPTS & 0x01) { // interrupts used
TIM1- & gt; DIER = __TIM1_DIER; // enable interrupt
NVIC- & gt; ISER[0] |= (1 & lt; & lt; (TIM1_UP_IRQChannel & 0x1F));// enable interrupt
}
TIM1- & gt; CR1 |= TIMX_CR1_CEN; // enable timer
} // end TIM1 used
if (__TIMER_USED & 0x02) { // TIM2 used
RCC- & gt; APB1ENR |= RCC_APB1ENR_TIM2EN; // enable clock for TIM2
TIM2- & gt; PSC = __PSC(__TIMXCLK, __TIM2_PERIOD); // set prescaler
TIM2- & gt; ARR = __ARR(__TIMXCLK, __TIM2_PERIOD); // set auto-reload
TIM2- & gt; CR1 = 0; // reset command register 1
TIM2- & gt; CR2 = 0; // reset command register 2
if (__TIMER_DETAILS & 0x02) { // detailed settings used
TIM2- & gt; PSC = __TIM2_PSC; // set prescaler
TIM2- & gt; ARR = __TIM2_ARR; // set auto-reload
TIM2- & gt; CCR1 = __TIM2_CCR1; //
TIM2- & gt; CCR2 = __TIM2_CCR2; //
TIM2- & gt; CCR3 = __TIM2_CCR3; //
TIM2- & gt; CCR4 = __TIM2_CCR4; //
TIM2- & gt; CCMR1 = __TIM2_CCMR1; //
TIM2- & gt; CCMR2 = __TIM2_CCMR2; //
TIM2- & gt; CCER = __TIM2_CCER; // set capture/compare enable register
TIM2- & gt; CR1 = __TIM2_CR1; // set command register 1
TIM2- & gt; CR2 = __TIM2_CR2; // set command register 2
}
if (__TIMER_INTERRUPTS & 0x02) { // interrupts used
TIM2- & gt; DIER = __TIM2_DIER; // enable interrupt
NVIC- & gt; ISER[0] |= (1 & lt; & lt; (TIM2_IRQChannel & 0x1F)); // enable interrupt
}
TIM2- & gt; CR1 |= TIMX_CR1_CEN; // enable timer
} // end TIM2 used
if (__TIMER_USED & 0x04) { // TIM3 used
RCC- & gt; APB1ENR |= RCC_APB1ENR_TIM3EN; // enable clock for TIM3
TIM3- & gt; PSC = __PSC(__TIMXCLK, __TIM3_PERIOD); // set prescaler
TIM3- & gt; ARR = __ARR(__TIMXCLK, __TIM3_PERIOD); // set auto-reload
TIM3- & gt; CR1 = 0; // reset command register 1
TIM3- & gt; CR2 = 0; // reset command register 2
if (__TIMER_DETAILS & 0x04) { // detailed settings used
TIM3- & gt; PSC = __TIM3_PSC; // set prescaler
TIM3- & gt; ARR = __TIM3_ARR; // set auto-reload
TIM3- & gt; CCR1 = __TIM3_CCR1; //
TIM3- & gt; CCR2 = __TIM3_CCR2; //
TIM3- & gt; CCR3 = __TIM3_CCR3; //
TIM3- & gt; CCR4 = __TIM3_CCR4; //
TIM3- & gt; CCMR1 = __TIM3_CCMR1; //
TIM3- & gt; CCMR2 = __TIM3_CCMR2; //
TIM3- & gt; CCER = __TIM3_CCER; // set capture/compare enable register
TIM3- & gt; CR1 = __TIM3_CR1; // set command register 1
TIM3- & gt; CR2 = __TIM3_CR2; // set command register 2
}
if (__TIMER_INTERRUPTS & 0x04) { // interrupts used
TIM3- & gt; DIER = __TIM3_DIER; // enable interrupt
NVIC- & gt; ISER[0] |= (1 & lt; & lt; (TIM3_IRQChannel & 0x1F)); // enable interrupt
}
TIM3- & gt; CR1 |= TIMX_CR1_CEN; // enable timer
} // end TIM3 used
if (__TIMER_USED & 0x08) { // TIM4 used
RCC- & gt; APB1ENR |= RCC_APB1ENR_TIM4EN; // enable clock for TIM4
TIM4- & gt; PSC = __PSC(__TIMXCLK, __TIM4_PERIOD); // set prescaler
TIM4- & gt; ARR = __ARR(__TIMXCLK, __TIM4_PERIOD); // set auto-reload
TIM4- & gt; CR1 = 0; // reset command register 1
TIM4- & gt; CR2 = 0; // reset command register 2
if (__TIMER_DETAILS & 0x08) { // detailed settings used
TIM4- & gt; PSC = __TIM4_PSC; // set prescaler
TIM4- & gt; ARR = __TIM4_ARR; // set auto-reload
TIM4- & gt; CCR1 = __TIM4_CCR1; //
TIM4- & gt; CCR2 = __TIM4_CCR2; //
TIM4- & gt; CCR3 = __TIM4_CCR3; //
TIM4- & gt; CCR4 = __TIM4_CCR4; //
TIM4- & gt; CCMR1 = __TIM4_CCMR1; //
TIM4- & gt; CCMR2 = __TIM4_CCMR2; //
TIM4- & gt; CCER = __TIM4_CCER; // set capture/compare enable register
TIM4- & gt; CR1 = __TIM4_CR1; // set command register 1
TIM4- & gt; CR2 = __TIM4_CR2; // set command register 2
}
if (__TIMER_INTERRUPTS & 0x08) { // interrupts used
TIM4- & gt; DIER = __TIM4_DIER; // enable interrupt
NVIC- & gt; ISER[0] |= (1 & lt; & lt; (TIM4_IRQChannel & 0x1F)); // enable interrupt
}
TIM4- & gt; CR1 |= TIMX_CR1_CEN; // enable timer
} // end TIM4 used
} // end of stm32_TimSetup
/*----------------------------------------------------------------------------
STM32 GPIO setup.
initializes the GPIOx_CRL and GPIOxCRH register
*----------------------------------------------------------------------------*/
void stm32_GpioSetup (void) {
if (__GPIO_USED & 0x01) { // GPIO Port A used
RCC- & gt; APB2ENR |= RCC_APB2ENR_IOPAEN; // enable clock for GPIOA
GPIOA- & gt; CRL = __GPIOA_CRL; // set Port configuration register low
GPIOA- & gt; CRH = __GPIOA_CRH; // set Port configuration register high
}
if (__GPIO_USED & 0x02) { // GPIO Port B used
RCC- & gt; APB2ENR |= RCC_APB2ENR_IOPBEN; // enable clock for GPIOB
GPIOB- & gt; CRL = __GPIOB_CRL; // set Port configuration register low
GPIOB- & gt; CRH = __GPIOB_CRH; // set Port configuration register high
}
if (__GPIO_USED & 0x04) { // GPIO Port C used
RCC- & gt; APB2ENR |= RCC_APB2ENR_IOPCEN; // enable clock for GPIOC
GPIOC- & gt; CRL = __GPIOC_CRL; // set Port configuration register low
GPIOC- & gt; CRH = __GPIOC_CRH; // set Port configuration register high
}
if (__GPIO_USED & 0x08) { // GPIO Port D used
RCC- & gt; APB2ENR |= RCC_APB2ENR_IOPDEN; // enable clock for GPIOD
GPIOD- & gt; CRL = __GPIOD_CRL; // set Port configuration register low
GPIOD- & gt; CRH = __GPIOD_CRH; // set Port configuration register high
}
if (__GPIO_USED & 0x10) { // GPIO Port E used
RCC- & gt; APB2ENR |= RCC_APB2ENR_IOPEEN; // enable clock for GPIOE
GPIOE- & gt; CRL = __GPIOE_CRL; // set Port configuration register low
GPIOE- & gt; CRH = __GPIOE_CRH; // set Port configuration register high
}
} // end of stm32_GpioSetup
/*----------------------------------------------------------------------------
STM32 USART setup.
initializes the USARTx register
*----------------------------------------------------------------------------*/
void stm32_UsartSetup (void) {
if (__USART_USED & 0x01) { // USART1 used
if ((__USART1_REMAP & 0x04) == 0x00) { // USART1 no remap
RCC- & gt; APB2ENR |= RCC_APB2ENR_IOPAEN; // enable clock for GPIOA
GPIOA- & gt; CRH & = ~(0xFFUL & lt; & lt; 4); // Clear PA9, PA10
GPIOA- & gt; CRH |= (0x0BUL & lt; & lt; 4); // USART1 Tx (PA9) alternate output push-pull
GPIOA- & gt; CRH |= (0x04UL & lt; & lt; 8); // USART1 Rx (PA10) input floating
}
else { // USART1 remap
RCC- & gt; APB2ENR |= RCC_APB2ENR_AFIOEN; // enable clock for Alternate Function
AFIO- & gt; MAPR |= __USART1_REMAP; // set USART1 remap
RCC- & gt; APB2ENR |= RCC_APB2ENR_IOPBEN; // enable clock for GPIOB
GPIOB- & gt; CRL & = ~(0xFFUL & lt; & lt; 24); // Clear PB6, PB7
GPIOB- & gt; CRL |= (0x0BUL & lt; & lt; 24); // USART1 Tx (PB6) alternate output push-pull
GPIOB- & gt; CRL |= (0x04UL & lt; & lt; 28); // USART1 Rx (PB7) input floating
}
RCC- & gt; APB2ENR |= RCC_APB2ENR_USART1EN; // enable clock for USART1
USART1- & gt; BRR = __USART_BRR(__PCLK2, __USART1_BAUDRATE); // set baudrate
USART1- & gt; CR1 = __USART1_DATABITS; // set Data bits
USART1- & gt; CR2 = __USART1_STOPBITS; // set Stop bits
USART1- & gt; CR1 |= __USART1_PARITY; // set Parity
USART1- & gt; CR3 = __USART1_FLOWCTRL; // Set Flow Control
USART1- & gt; CR1 |= (USART_CR1_RE | USART_CR1_TE); // RX, TX enable
if (__USART_INTERRUPTS & 0x01) { // interrupts used
USART1- & gt; CR1 |= __USART1_CR1;
USART1- & gt; CR2 |= __USART1_CR2;
USART1- & gt; CR3 |= __USART1_CR3;
NVIC- & gt; ISER[1] |= (1 & lt; & lt; (USART1_IRQChannel & 0x1F)); // enable interrupt
}
USART1- & gt; CR1 |= USART_CR1_UE; // USART enable
} // end USART1 used
if (__USART_USED & 0x02) { // USART2 used
if ((__USART2_REMAP & 0x08) == 0x00) { // USART2 no remap
RCC- & gt; APB2ENR |= RCC_APB2ENR_IOPAEN; // enable clock for GPIOA
GPIOA- & gt; CRL & = ~(0xFFUL & lt; & lt; 8); // Clear PA2, PA3
GPIOA- & gt; CRL |= (0x0BUL & lt; & lt; 8); // USART2 Tx (PA2) alternate output push-pull
GPIOA- & gt; CRL |= (0x04UL & lt; & lt; 12); // USART2 Rx (PA3) input floating
if (__USART2_FLOWCTRL & 0x0300) { // HW flow control enabled
GPIOA- & gt; CRL & = ~(0xFFUL & lt; & lt; 0); // Clear PA0, PA1
GPIOA- & gt; CRL |= (0x04UL & lt; & lt; 0); // USART2 CTS (PA0) input floating
GPIOA- & gt; CRL |= (0x0BUL & lt; & lt; 4); // USART2 RTS (PA1) alternate output push-pull
}
}
else { // USART2 remap
RCC- & gt; APB2ENR |= RCC_APB2ENR_AFIOEN; // enable clock for Alternate Function
AFIO- & gt; MAPR |= __USART2_REMAP; // set USART2 remap
RCC- & gt; APB2ENR |= RCC_APB2ENR_IOPDEN; // enable clock for GPIOD
GPIOD- & gt; CRL & = ~(0xFFUL & lt; & lt; 20); // Clear PD5, PD6
GPIOD- & gt; CRL |= (0x0BUL & lt; & lt; 20); // USART2 Tx (PD5) alternate output push-pull
GPIOD- & gt; CRL |= (0x04UL & lt; & lt; 24); // USART2 Rx (PD6) input floating
if (__USART2_FLOWCTRL & 0x0300) { // HW flow control enabled
GPIOD- & gt; CRL & = ~(0xFFUL & lt; & lt; 12); // Clear PD3, PD4
GPIOD- & gt; CRL |= (0x04UL & lt; & lt; 12); // USART2 CTS (PD3) input floating
GPIOD- & gt; CRL |= (0x0BUL & lt; & lt; 16); // USART2 RTS (PD4) alternate output push-pull
}
}
RCC- & gt; APB1ENR |= RCC_APB1ENR_USART2EN; // enable clock for USART2
USART2- & gt; BRR = __USART_BRR(__PCLK1, __USART2_BAUDRATE); // set baudrate
USART2- & gt; CR1 = __USART2_DATABITS; // set Data bits
USART2- & gt; CR2 = __USART2_STOPBITS; // set Stop bits
USART2- & gt; CR1 |= __USART2_PARITY; // set Parity
USART2- & gt; CR3 = __USART2_FLOWCTRL; // Set Flow Control
USART2- & gt; CR1 |= (USART_CR1_RE | USART_CR1_TE); // RX, TX enable
if (__USART_INTERRUPTS & 0x02) { // interrupts used
USART2- & gt; CR1 |= __USART2_CR1;
USART2- & gt; CR2 |= __USART2_CR2;
USART2- & gt; CR3 |= __USART2_CR3;
NVIC- & gt; ISER[1] |= (1 & lt; & lt; (USART2_IRQChannel & 0x1F)); // enable interrupt
}
USART2- & gt; CR1 |= USART_CR1_UE; // USART enable
} // end USART2 used
if (__USART_USED & 0x04) { // USART3 used
AFIO- & gt; MAPR & = ~(3 & lt; & lt; 4); // clear USART3 remap
if ((__USART3_REMAP & 0x30) == 0x00) { // USART3 no remap
RCC- & gt; APB2ENR |= RCC_APB2ENR_IOPBEN; // enable clock for GPIOB
GPIOB- & gt; CRH & = ~(0xFFUL & lt; & lt; 8); // Clear PB10, PB11
GPIOB- & gt; CRH |= (0x0BUL & lt; & lt; 8); // USART3 Tx (PB10) alternate output push-pull
GPIOB- & gt; CRH |= (0x04UL & lt; & lt; 12); // USART3 Rx (PB11) input floating
if (__USART3_FLOWCTRL & 0x0300) { // HW flow control enabled
GPIOB- & gt; CRH & = ~(0xFFUL & lt; & lt; 20); // Clear PB13, PB14
GPIOB- & gt; CRH |= (0x04UL & lt; & lt; 20); // USART3 CTS (PB13) input floating
GPIOB- & gt; CRH |= (0x0BUL & lt; & lt; 24); // USART3 RTS (PB14) alternate output push-pull
}
}
else if ((__USART3_REMAP & 0x30) == 0x10) { // USART3 partial remap
RCC- & gt; APB2ENR |= RCC_APB2ENR_AFIOEN; // enable clock for Alternate Function
AFIO- & gt; MAPR |= __USART3_REMAP; // set USART3 remap
RCC- & gt; APB2ENR |= RCC_APB2ENR_IOPCEN; // enable clock for GPIOC
GPIOC- & gt; CRH & = ~(0xFFUL & lt; & lt; 8); // Clear PC10, PC11
GPIOC- & gt; CRH |= (0x0BUL & lt; & lt; 8); // USART3 Tx (PC10) alternate output push-pull
GPIOC- & gt; CRH |= (0x04UL & lt; & lt; 12); // USART3 Rx (PC11) input floating
if (__USART3_FLOWCTRL & 0x0300) { // HW flow control enabled
RCC- & gt; APB2ENR |= RCC_APB2ENR_IOPBEN; // enable clock for GPIOB
GPIOB- & gt; CRH & = ~(0xFFUL & lt; & lt; 20); // Clear PB13, PB14
GPIOB- & gt; CRH |= (0x04UL & lt; & lt; 20); // USART3 CTS (PB13) input floating
GPIOB- & gt; CRH |= (0x0BUL & lt; & lt; 24); // USART3 RTS (PB14) alternate output push-pull
}
}
else { // USART3 full remap
RCC- & gt; APB2ENR |= RCC_APB2ENR_AFIOEN; // enable clock for Alternate Function
AFIO- & gt; MAPR |= __USART3_REMAP; // set USART3 remap
RCC- & gt; APB2ENR |= RCC_APB2ENR_IOPDEN; // enable clock for GPIOD
GPIOD- & gt; CRH & = ~(0xFFUL & lt; & lt; 0); // Clear PD8, PD9
GPIOD- & gt; CRH |= (0x0BUL & lt; & lt; 0); // USART3 Tx (PD8) alternate output push-pull
GPIOD- & gt; CRH |= (0x04UL & lt; & lt; 4); // USART3 Rx (PD9) input floating
if (__USART3_FLOWCTRL & 0x0300) { // HW flow control enabled
GPIOD- & gt; CRH & = ~(0xFFUL & lt; & lt; 12); // Clear PD11, PD12
GPIOD- & gt; CRH |= (0x04UL & lt; & lt; 12); // USART3 CTS (PD11) input floating
GPIOD- & gt; CRH |= (0x0BUL & lt; & lt; 16); // USART3 RTS (PD12) alternate output push-pull
}
}
RCC- & gt; APB1ENR |= RCC_APB1ENR_USART3EN; // enable clock for USART3
USART3- & gt; BRR = __USART_BRR(__PCLK1, __USART3_BAUDRATE); // set baudrate
USART3- & gt; CR1 = __USART3_DATABITS; // set Data bits
USART3- & gt; CR2 = __USART3_STOPBITS; // set Stop bits
USART3- & gt; CR1 |= __USART3_PARITY; // set Parity
USART3- & gt; CR3 = __USART3_FLOWCTRL; // Set Flow Control
USART3- & gt; CR1 |= (USART_CR1_RE | USART_CR1_TE); // RX, TX enable
if (__USART_INTERRUPTS & 0x04) { // interrupts used
USART3- & gt; CR1 |= __USART3_CR1;
USART3- & gt; CR2 |= __USART3_CR2;
USART3- & gt; CR3 |= __USART3_CR3;
NVIC- & gt; ISER[1] |= (1 & lt; & lt; (USART3_IRQChannel & 0x1F)); // enable interrupt
}
USART3- & gt; CR1 |= USART_CR1_UE; // USART enable
} // end USART3 used
} // end of stm32_UsartSetup
/*----------------------------------------------------------------------------
STM32 EXTI setup.
initializes the EXTI register
*----------------------------------------------------------------------------*/
void stm32_ExtiSetup (void) {
if (__EXTI_USED & (1 & lt; & lt; 0)) { // EXTI0 used
RCC- & gt; APB2ENR |= RCC_APB2ENR_AFIOEN; // enable clock for Alternate Function
AFIO- & gt; EXTICR[0] & = 0xFFF0; // clear used pin
AFIO- & gt; EXTICR[0] |= (0x000F & __AFIO_EXTICR1); // set pin to use
EXTI- & gt; IMR |= ((1 & lt; & lt; 0) & __EXTI_IMR); // unmask interrupt
EXTI- & gt; EMR |= ((1 & lt; & lt; 0) & __EXTI_EMR); // unmask event
EXTI- & gt; RTSR |= ((1 & lt; & lt; 0) & __EXTI_RTSR); // set rising edge
EXTI- & gt; FTSR |= ((1 & lt; & lt; 0) & __EXTI_FTSR); // set falling edge
if (__EXTI_INTERRUPTS & (1 & lt; & lt; 0)) { // interrupt used
NVIC- & gt; ISER[0] |= (1 & lt; & lt; (EXTI0_IRQChannel & 0x1F)); // enable interrupt EXTI 0
}
} // end EXTI0 used
if (__EXTI_USED & (1 & lt; & lt; 1)) { // EXTI1 used
RCC- & gt; APB2ENR |= RCC_APB2ENR_AFIOEN; // enable clock for Alternate Function
AFIO- & gt; EXTICR[0] & = 0xFF0F; // clear used pin
AFIO- & gt; EXTICR[0] |= (0x00F0 & __AFIO_EXTICR1); // set pin to use
EXTI- & gt; IMR |= ((1 & lt; & lt; 1) & __EXTI_IMR); // unmask interrupt
EXTI- & gt; EMR |= ((1 & lt; & lt; 1) & __EXTI_EMR); // unmask event
EXTI- & gt; RTSR |= ((1 & lt; & lt; 1) & __EXTI_RTSR); // set rising edge
EXTI- & gt; FTSR |= ((1 & lt; & lt; 1) & __EXTI_FTSR); // set falling edge
if (__EXTI_INTERRUPTS & (1 & lt; & lt; 1)) { // interrupt used
NVIC- & gt; ISER[0] |= (1 & lt; & lt; (EXTI1_IRQChannel & 0x1F)); // enable interrupt EXTI 1
}
} // end EXTI1 used
if (__EXTI_USED & (1 & lt; & lt; 2)) { // EXTI2 used
RCC- & gt; APB2ENR |= RCC_APB2ENR_AFIOEN; // enable clock for Alternate Function
AFIO- & gt; EXTICR[0] & = 0xF0FF; // clear used pin
AFIO- & gt; EXTICR[0] |= (0x0F00 & __AFIO_EXTICR1); // set pin to use
EXTI- & gt; IMR |= ((1 & lt; & lt; 2) & __EXTI_IMR); // unmask interrupt
EXTI- & gt; EMR |= ((1 & lt; & lt; 2) & __EXTI_EMR); // unmask event
EXTI- & gt; RTSR |= ((1 & lt; & lt; 2) & __EXTI_RTSR); // set rising edge
EXTI- & gt; FTSR |= ((1 & lt; & lt; 2) & __EXTI_FTSR); // set falling edge
if (__EXTI_INTERRUPTS & (1 & lt; & lt; 2)) { // interrupt used
NVIC- & gt; ISER[0] |= (1 & lt; & lt; (EXTI2_IRQChannel & 0x1F)); // enable interrupt EXTI 2
}
} // end EXTI2 used
if (__EXTI_USED & (1 & lt; & lt; 3)) { // EXTI3 used
RCC- & gt; APB2ENR |= RCC_APB2ENR_AFIOEN; // enable clock for Alternate Function
AFIO- & gt; EXTICR[0] & = 0x0FFF; // clear used pin
AFIO- & gt; EXTICR[0] |= (0xFF00 & __AFIO_EXTICR1); // set pin to use
EXTI- & gt; IMR |= ((1 & lt; & lt; 3) & __EXTI_IMR); // unmask interrupt
EXTI- & gt; EMR |= ((1 & lt; & lt; 3) & __EXTI_EMR); // unmask event
EXTI- & gt; RTSR |= ((1 & lt; & lt; 3) & __EXTI_RTSR); // set rising edge
EXTI- & gt; FTSR |= ((1 & lt; & lt; 3) & __EXTI_FTSR); // set falling edge
if (__EXTI_INTERRUPTS & (1 & lt; & lt; 3)) { // interrupt used
NVIC- & gt; ISER[0] |= (1 & lt; & lt; (EXTI3_IRQChannel & 0x1F)); // enable interrupt EXTI 3
}
} // end EXTI3 used
if (__EXTI_USED & (1 & lt; & lt; 4)) { // EXTI4 used
RCC- & gt; APB2ENR |= RCC_APB2ENR_AFIOEN; // enable clock for Alternate Function
AFIO- & gt; EXTICR[1] & = 0xFFF0; // clear used pin
AFIO- & gt; EXTICR[1] |= (0x000F & __AFIO_EXTICR2); // set pin to use
EXTI- & gt; IMR |= ((1 & lt; & lt; 4) & __EXTI_IMR); // unmask interrupt
EXTI- & gt; EMR |= ((1 & lt; & lt; 4) & __EXTI_EMR); // unmask event
EXTI- & gt; RTSR |= ((1 & lt; & lt; 4) & __EXTI_RTSR); // set rising edge
EXTI- & gt; FTSR |= ((1 & lt; & lt; 4) & __EXTI_FTSR); // set falling edge
if (__EXTI_INTERRUPTS & (1 & lt; & lt; 4)) { // interrupt used
NVIC- & gt; ISER[0] |= (1 & lt; & lt; (EXTI4_IRQChannel & 0x1F)); // enable interrupt EXTI 4
}
} // end EXTI4 used
if (__EXTI_USED & (1 & lt; & lt; 5)) { // EXTI5 used
RCC- & gt; APB2ENR |= RCC_APB2ENR_AFIOEN; // enable clock for Alternate Function
AFIO- & gt; EXTICR[1] & = 0xFF0F; // clear used pin
AFIO- & gt; EXTICR[1] |= (0x00F0 & __AFIO_EXTICR2); // set pin to use
EXTI- & gt; IMR |= ((1 & lt; & lt; 5) & __EXTI_IMR); // unmask interrupt
EXTI- & gt; EMR |= ((1 & lt; & lt; 5) & __EXTI_EMR); // unmask event
EXTI- & gt; RTSR |= ((1 & lt; & lt; 5) & __EXTI_RTSR); // set rising edge
EXTI- & gt; FTSR |= ((1 & lt; & lt; 5) & __EXTI_FTSR); // set falling edge
if (__EXTI_INTERRUPTS & (1 & lt; & lt; 5)) { // interrupt used
NVIC- & gt; ISER[0] |= (1 & lt; & lt; (EXTI9_5_IRQChannel & 0x1F));// enable interrupt EXTI 9..5
}
} // end EXTI5 used
if (__EXTI_USED & (1 & lt; & lt; 6)) { // EXTI6 used
RCC- & gt; APB2ENR |= RCC_APB2ENR_AFIOEN; // enable clock for Alternate Function
AFIO- & gt; EXTICR[1] & = 0xF0FF; // clear used pin
AFIO- & gt; EXTICR[1] |= (0x0F00 & __AFIO_EXTICR2); // set pin to use
EXTI- & gt; IMR |= ((1 & lt; & lt; 6) & __EXTI_IMR); // unmask interrupt
EXTI- & gt; EMR |= ((1 & lt; & lt; 6) & __EXTI_EMR); // unmask event
EXTI- & gt; RTSR |= ((1 & lt; & lt; 6) & __EXTI_RTSR); // set rising edge
EXTI- & gt; FTSR |= ((1 & lt; & lt; 6) & __EXTI_FTSR); // set falling edge
if (__EXTI_INTERRUPTS & (1 & lt; & lt; 6)) { // interrupt used
NVIC- & gt; ISER[0] |= (1 & lt; & lt; (EXTI9_5_IRQChannel & 0x1F));// enable interrupt EXTI 9..5
}
} // end EXTI6 used
if (__EXTI_USED & (1 & lt; & lt; 7)) { // EXTI7 used
RCC- & gt; APB2ENR |= RCC_APB2ENR_AFIOEN; // enable clock for Alternate Function
AFIO- & gt; EXTICR[1] & = 0x0FFF; // clear used pin
AFIO- & gt; EXTICR[1] |= (0xF000 & __AFIO_EXTICR2); // set pin to use
EXTI- & gt; IMR |= ((1 & lt; & lt; 7) & __EXTI_IMR); // unmask interrupt
EXTI- & gt; EMR |= ((1 & lt; & lt; 7) & __EXTI_EMR); // unmask event
EXTI- & gt; RTSR |= ((1 & lt; & lt; 7) & __EXTI_RTSR); // set rising edge
EXTI- & gt; FTSR |= ((1 & lt; & lt; 7) & __EXTI_FTSR); // set falling edge
if (__EXTI_INTERRUPTS & (1 & lt; & lt; 7)) { // interrupt used
NVIC- & gt; ISER[0] |= (1 & lt; & lt; (EXTI9_5_IRQChannel & 0x1F));// enable interrupt EXTI 9..5
}
} // end EXTI7 used
if (__EXTI_USED & (1 & lt; & lt; 8)) { // EXTI8 used
RCC- & gt; APB2ENR |= RCC_APB2ENR_AFIOEN; // enable clock for Alternate Function
AFIO- & gt; EXTICR[2] & = 0xFFF0; // clear used pin
AFIO- & gt; EXTICR[2] |= (0x000F & __AFIO_EXTICR3); // set pin to use
EXTI- & gt; IMR |= ((1 & lt; & lt; 8) & __EXTI_IMR); // unmask interrupt
EXTI- & gt; EMR |= ((1 & lt; & lt; 8) & __EXTI_EMR); // unmask event
EXTI- & gt; RTSR |= ((1 & lt; & lt; 8) & __EXTI_RTSR); // set rising edge
EXTI- & gt; FTSR |= ((1 & lt; & lt; 8) & __EXTI_FTSR); // set falling edge
if (__EXTI_INTERRUPTS & (1 & lt; & lt; 8)) { // interrupt used
NVIC- & gt; ISER[0] |= (1 & lt; & lt; (EXTI9_5_IRQChannel & 0x1F));// enable interrupt EXTI 9..5
}
} // end EXTI8 used
if (__EXTI_USED & (1 & lt; & lt; 9)) { // EXTI9 used
RCC- & gt; APB2ENR |= RCC_APB2ENR_AFIOEN; // enable clock for Alternate Function
AFIO- & gt; EXTICR[2] & = 0xFF0F; // clear used pin
AFIO- & gt; EXTICR[2] |= (0x00F0 & __AFIO_EXTICR3); // set pin to use
EXTI- & gt; IMR |= ((1 & lt; & lt; 9) & __EXTI_IMR); // unmask interrupt
EXTI- & gt; EMR |= ((1 & lt; & lt; 9) & __EXTI_EMR); // unmask event
EXTI- & gt; RTSR |= ((1 & lt; & lt; 9) & __EXTI_RTSR); // set rising edge
EXTI- & gt; FTSR |= ((1 & lt; & lt; 9) & __EXTI_FTSR); // set falling edge
if (__EXTI_INTERRUPTS & (1 & lt; & lt; 9)) { // interrupt used
NVIC- & gt; ISER[0] |= (1 & lt; & lt; (EXTI9_5_IRQChannel & 0x1F));// enable interrupt EXTI 9..5
}
} // end EXTI9 used
if (__EXTI_USED & (1 & lt; & lt; 10)) { // EXTI10 used
RCC- & gt; APB2ENR |= RCC_APB2ENR_AFIOEN; // enable clock for Alternate Function
AFIO- & gt; EXTICR[2] & = 0xF0FF; // clear used pin
AFIO- & gt; EXTICR[2] |= (0x0F00 & __AFIO_EXTICR3); // set pin to use
EXTI- & gt; IMR |= ((1 & lt; & lt; 10) & __EXTI_IMR); // unmask interrupt
EXTI- & gt; EMR |= ((1 & lt; & lt; 10) & __EXTI_EMR); // unmask event
EXTI- & gt; RTSR |= ((1 & lt; & lt; 10) & __EXTI_RTSR); // set rising edge
EXTI- & gt; FTSR |= ((1 & lt; & lt; 10) & __EXTI_FTSR); // set falling edge
if (__EXTI_INTERRUPTS & (1 & lt; & lt; 10)) { // interrupt used
NVIC- & gt; ISER[1] |= (1 & lt; & lt; (EXTI15_10_IRQChannel & 0x1F));// enable interrupt EXTI 10..15
}
} // end EXTI10 used
if (__EXTI_USED & (1 & lt; & lt; 11)) { // EXTI11 used
RCC- & gt; APB2ENR |= RCC_APB2ENR_AFIOEN; // enable clock for Alternate Function
AFIO- & gt; EXTICR[2] & = 0x0FFF; // clear used pin
AFIO- & gt; EXTICR[2] |= (0xF000 & __AFIO_EXTICR3); // set pin to use
EXTI- & gt; IMR |= ((1 & lt; & lt; 11) & __EXTI_IMR); // unmask interrupt
EXTI- & gt; EMR |= ((1 & lt; & lt; 11) & __EXTI_EMR); // unmask event
EXTI- & gt; RTSR |= ((1 & lt; & lt; 11) & __EXTI_RTSR); // set rising edge
EXTI- & gt; FTSR |= ((1 & lt; & lt; 11) & __EXTI_FTSR); // set falling edge
if (__EXTI_INTERRUPTS & (1 & lt; & lt; 11)) { // interrupt used
NVIC- & gt; ISER[1] |= (1 & lt; & lt; (EXTI15_10_IRQChannel & 0x1F));// enable interrupt EXTI 10..15
}
} // end EXTI11 used
if (__EXTI_USED & (1 & lt; & lt; 12)) { // EXTI12 used
RCC- & gt; APB2ENR |= RCC_APB2ENR_AFIOEN; // enable clock for Alternate Function
AFIO- & gt; EXTICR[3] & = 0xFFF0; // clear used pin
AFIO- & gt; EXTICR[3] |= (0x000F & __AFIO_EXTICR4); // set pin to use
EXTI- & gt; IMR |= ((1 & lt; & lt; 12) & __EXTI_IMR); // unmask interrupt
EXTI- & gt; EMR |= ((1 & lt; & lt; 12) & __EXTI_EMR); // unmask event
EXTI- & gt; RTSR |= ((1 & lt; & lt; 12) & __EXTI_RTSR); // set rising edge
EXTI- & gt; FTSR |= ((1 & lt; & lt; 12) & __EXTI_FTSR); // set falling edge
if (__EXTI_INTERRUPTS & (1 & lt; & lt; 12)) { // interrupt used
NVIC- & gt; ISER[1] |= (1 & lt; & lt; (EXTI15_10_IRQChannel & 0x1F));// enable interrupt EXTI 10..15
}
} // end EXTI12 used
if (__EXTI_USED & (1 & lt; & lt; 13)) { // EXTI13 used
RCC- & gt; APB2ENR |= RCC_APB2ENR_AFIOEN; // enable clock for Alternate Function
AFIO- & gt; EXTICR[3] & = 0xFF0F; // clear used pin
AFIO- & gt; EXTICR[3] |= (0x00F0 & __AFIO_EXTICR4); // set pin to use
EXTI- & gt; IMR |= ((1 & lt; & lt; 13) & __EXTI_IMR); // unmask interrupt
EXTI- & gt; EMR |= ((1 & lt; & lt; 13) & __EXTI_EMR); // unmask event
EXTI- & gt; RTSR |= ((1 & lt; & lt; 13) & __EXTI_RTSR); // set rising edge
EXTI- & gt; FTSR |= ((1 & lt; & lt; 13) & __EXTI_FTSR); // set falling edge
if (__EXTI_INTERRUPTS & (1 & lt; & lt; 13)) { // interrupt used
NVIC- & gt; ISER[1] |= (1 & lt; & lt; (EXTI15_10_IRQChannel & 0x1F));// enable interrupt EXTI 10..15
}
} // end EXTI13 used
if (__EXTI_USED & (1 & lt; & lt; 14)) { // EXTI14 used
RCC- & gt; APB2ENR |= RCC_APB2ENR_AFIOEN; // enable clock for Alternate Function
AFIO- & gt; EXTICR[3] & = 0xF0FF; // clear used pin
AFIO- & gt; EXTICR[3] |= (0x0F00 & __AFIO_EXTICR4); // set pin to use
EXTI- & gt; IMR |= ((1 & lt; & lt; 14) & __EXTI_IMR); // unmask interrupt
EXTI- & gt; EMR |= ((1 & lt; & lt; 14) & __EXTI_EMR); // unmask event
EXTI- & gt; RTSR |= ((1 & lt; & lt; 14) & __EXTI_RTSR); // set rising edge
EXTI- & gt; FTSR |= ((1 & lt; & lt; 14) & __EXTI_FTSR); // set falling edge
if (__EXTI_INTERRUPTS & (1 & lt; & lt; 14)) { // interrupt used
NVIC- & gt; ISER[1] |= (1 & lt; & lt; (EXTI15_10_IRQChannel & 0x1F));// enable interrupt EXTI 10..15
}
} // end EXTI14 used
if (__EXTI_USED & (1 & lt; & lt; 15)) { // EXTI15 used
RCC- & gt; APB2ENR |= RCC_APB2ENR_AFIOEN; // enable clock for Alternate Function
AFIO- & gt; EXTICR[3] & = 0x0FFF; // clear used pin
AFIO- & gt; EXTICR[3] |= (0xF000 & __AFIO_EXTICR4); // set pin to use
EXTI- & gt; IMR |= ((1 & lt; & lt; 15) & __EXTI_IMR); // unmask interrupt
EXTI- & gt; EMR |= ((1 & lt; & lt; 15) & __EXTI_EMR); // unmask event
EXTI- & gt; RTSR |= ((1 & lt; & lt; 15) & __EXTI_RTSR); // set rising edge
EXTI- & gt; FTSR |= ((1 & lt; & lt; 15) & __EXTI_FTSR); // set falling edge
if (__EXTI_INTERRUPTS & (1 & lt; & lt; 15)) { // interrupt used
NVIC- & gt; ISER[1] |= (1 & lt; & lt; (EXTI15_10_IRQChannel & 0x1F));// enable interrupt EXTI 10..15
}
} // end EXTI15 used
} // end of stm32_ExtiSetup
/*----------------------------------------------------------------------------
STM32 Tamper setup.
initializes the Tamper register
*----------------------------------------------------------------------------*/
void stm32_TamperSetup (void) {
RCC- & gt; APB1ENR |= RCC_APB1ENR_BKPEN; // enable clock for Backup interface
RCC- & gt; APB1ENR |= RCC_APB1ENR_PWREN; // enable clock for Power interface
PWR- & gt; CR |= PWR_CR_DBP; // enable access to RTC, BDC registers
BKP- & gt; CR = __BKP_CR; // set BKP_CR register
BKP- & gt; CSR = __BKP_CSR; // set BKP_CSR register
BKP- & gt; CSR |= 0x0003; // clear CTI, CTE
PWR- & gt; CR & = ~PWR_CR_DBP; // disable access to RTC, BDC registers
if (BKP- & gt; CSR & (1 & lt; & lt; 2)) { // Tamper interrupt enable ?
NVIC- & gt; ISER[0] |= (1 & lt; & lt; (TAMPER_IRQChannel & 0x1F)); // enable interrupt
}
} // end of stm32_TamperSetup
/*----------------------------------------------------------------------------
STM32 initialization
Call this function as first in main ()
*----------------------------------------------------------------------------*/
void stm32_Init () {
#if __EFI_SETUP
stm32_EfiSetup ();
#endif
#if __CLOCK_SETUP
stm32_ClockSetup ();
#endif
#if __SYSTICK_SETUP
stm32_SysTickSetup ();
#endif
#if __RTC_SETUP
stm32_RtcSetup ();
#endif
#if __TIMER_SETUP
stm32_TimerSetup ();
#endif
#if __GPIO_SETUP
stm32_GpioSetup ();
#endif
#if __USART_SETUP
stm32_UsartSetup();
#endif
#if __EXTI_SETUP
stm32_ExtiSetup();
#endif
#if __TAMPER_SETUP
stm32_TamperSetup();
#endif
#if __IWDG_SETUP
stm32_IwdgSetup(); // this should be the last function. watchdog is running afterwards
#endif
} // end of stm32_Init
/*----------------------------------------------------------------------------
STM32 get PCLK1
deliver the PCLK1
*----------------------------------------------------------------------------*/
unsigned int stm32_GetPCLK1 (void) {
return ((unsigned int)__PCLK1);
}
/*********************************************
* vim:sw=8:ts=8:si:et
* To use the above modeline in vim you must have " set modeline " in your .vimrc
* Author: Guido Socher
* Copyright: GPL V2
*
* Based on the net.h file from the AVRlib library by Pascal Stang.
* For AVRlib See http://www.procyonengineering.com/
* Used with explicit permission of Pascal Stang.
*
* Chip type : ATMEGA88 with ENC28J60
*********************************************/
/*********************************************
* modified: 2007-08-08
* Author : awake
* Copyright: GPL V2
* http://www.icdev.com.cn/?2213/
* Host chip: ADUC7026
**********************************************/
// notation: _P = position of a field
// _V = value of a field
//@{
#ifndef NET_H
#define NET_H
// ******* ETH *******
#define ETH_HEADER_LEN 14
// values of certain bytes:
#define ETHTYPE_ARP_H_V 0x08
#define ETHTYPE_ARP_L_V 0x06
#define ETHTYPE_IP_H_V 0x08
#define ETHTYPE_IP_L_V 0x00
// byte positions in the ethernet frame:
//
// Ethernet type field (2bytes):
#define ETH_TYPE_H_P 12
#define ETH_TYPE_L_P 13
//
#define ETH_DST_MAC 0
#define ETH_SRC_MAC 6
// ******* ARP *******
#define ETH_ARP_OPCODE_REPLY_H_V 0x0
#define ETH_ARP_OPCODE_REPLY_L_V 0x02
//
#define ETHTYPE_ARP_L_V 0x06
// arp.dst.ip
#define ETH_ARP_DST_IP_P 0x26
// arp.opcode
#define ETH_ARP_OPCODE_H_P 0x14
#define ETH_ARP_OPCODE_L_P 0x15
// arp.src.mac
#define ETH_ARP_SRC_MAC_P 0x16
#define ETH_ARP_SRC_IP_P 0x1c
#define ETH_ARP_DST_MAC_P 0x20
#define ETH_ARP_DST_IP_P 0x26
// ******* IP *******
#define IP_HEADER_LEN 20
// ip.src
#define IP_SRC_P 0x1a
#define IP_DST_P 0x1e
#define IP_HEADER_LEN_VER_P 0xe
#define IP_CHECKSUM_P 0x18
#define IP_TTL_P 0x16
#define IP_FLAGS_P 0x14
#define IP_P 0xe
#define IP_TOTLEN_H_P 0x10
#define IP_TOTLEN_L_P 0x11
#define IP_PROTO_P 0x17
#define IP_PROTO_ICMP_V 1
#define IP_PROTO_TCP_V 6
// 17=0x11
#define IP_PROTO_UDP_V 17
// ******* ICMP *******
#define ICMP_TYPE_ECHOREPLY_V 0
#define ICMP_TYPE_ECHOREQUEST_V 8
//
#define ICMP_TYPE_P 0x22
#define ICMP_CHECKSUM_P 0x24
// ******* UDP *******
#define UDP_HEADER_LEN 8
//
#define UDP_SRC_PORT_H_P 0x22
#define UDP_SRC_PORT_L_P 0x23
#define UDP_DST_PORT_H_P 0x24
#define UDP_DST_PORT_L_P 0x25
//
#define UDP_LEN_H_P 0x26
#define UDP_LEN_L_P 0x27
#define UDP_CHECKSUM_H_P 0x28
#define UDP_CHECKSUM_L_P 0x29
#define UDP_DATA_P 0x2a
// ******* TCP *******
#define TCP_SRC_PORT_H_P 0x22
#define TCP_SRC_PORT_L_P 0x23
#define TCP_DST_PORT_H_P 0x24
#define TCP_DST_PORT_L_P 0x25
// the tcp seq number is 4 bytes 0x26-0x29
#define TCP_SEQ_H_P 0x26
#define TCP_SEQACK_H_P 0x2a
// flags: SYN=2
#define TCP_FLAGS_P 0x2f
#define TCP_FLAGS_SYN_V 2
#define TCP_FLAGS_FIN_V 1
#define TCP_FLAGS_PUSH_V 8
#define TCP_FLAGS_SYNACK_V 0x12
#define TCP_FLAGS_ACK_V 0x10
#define TCP_FLAGS_PSHACK_V 0x18
// plain len without the options:
#define TCP_HEADER_LEN_PLAIN 20
#define TCP_HEADER_LEN_P 0x2e
#define TCP_CHECKSUM_H_P 0x32
#define TCP_CHECKSUM_L_P 0x33
#define TCP_OPTIONS_P 0x36
//
#endif
//@}
//#include " includes.h "
#include & lt; STM32F10X_SPI.h & gt;
#include & lt; STM32F10X_GPIO.h & gt;
#include & lt; STM32F10X_RCC.h & gt;
//SPI1³õʼ»¯
void SPI1_Init(void)
{
SPI_InitTypeDef SPI_InitStructure;
GPIO_InitTypeDef GPIO_InitStructure;
/* Enable SPI1 and GPIOA clocks */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
/* Configure SPI1 pins: NSS, SCK, MISO and MOSI */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOA, & GPIO_InitStructure);
/* SPI1 configuration */
SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
SPI_InitStructure.SPI_CRCPolynomial = 7;
SPI_Init(SPI1, & SPI_InitStructure);
/* Enable SPI1 */
SPI_Cmd(SPI1, ENABLE);
}
//SPI1¶Áдһ×Ö½ÚÊý¾Ý
unsigned char SPI1_ReadWrite(unsigned char writedat)
{ unsigned char i=0;
/* Loop while DR register in not emplty */
while(SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_TXE) == RESET);
/* Send byte through the SPI1 peripheral */
SPI_I2S_SendData(SPI1, writedat);
// printf ( " writedat...%x\r\n " ,writedat);
/* Wait to receive a byte */
while(SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_RXNE) == RESET);
i= SPI_I2S_ReceiveData(SPI1) ;
// printf ( " spi recieved...%x\r\n " ,i);
/* Return the byte read from the SPI bus */
return i;
}
/*********************************************
* vim:sw=8:ts=8:si:et
* To use the above modeline in vim you must have " set modeline " in your .vimrc
* Author: Guido Socher
* Copyright: GPL V2
*
* IP/ARP/UDP/TCP functions
*
* Chip type : ATMEGA88 with ENC28J60
*********************************************/
/*********************************************
* modified: 2007-08-08
* Author : awake
* Copyright: GPL V2
* http://www.icdev.com.cn/?2213/
* Host chip: ADUC7026
**********************************************/
//@{
#ifndef IP_ARP_UDP_TCP_H
#define IP_ARP_UDP_TCP_H
// you must call this function once before you use any of the other functions:
extern void init_ip_arp_udp_tcp(unsigned char *mymac,unsigned char *myip,unsigned char wwwp);
//
extern unsigned char eth_type_is_arp_and_my_ip(unsigned char *buf,unsigned int len);
extern unsigned char eth_type_is_ip_and_my_ip(unsigned char *buf,unsigned int len);
extern void make_arp_answer_from_request(unsigned char *buf);
extern void make_echo_reply_from_request(unsigned char *buf,unsigned int len);
extern void make_udp_reply_from_request(unsigned char *buf,char *data,unsigned char datalen,unsigned int port);
extern void make_tcp_synack_from_syn(unsigned char *buf);
extern void init_len_info(unsigned char *buf);
extern unsigned int get_tcp_data_pointer(void);
extern unsigned int fill_tcp_data_p(unsigned char *buf,unsigned int pos, const unsigned char *progmem_s);
extern unsigned int fill_tcp_data(unsigned char *buf,unsigned int pos, const char *s);
extern void make_tcp_ack_from_any(unsigned char *buf);
extern void make_tcp_ack_with_data(unsigned char *buf,unsigned int dlen);
#endif /* IP_ARP_UDP_TCP_H */
//@}
Static Call Graph - [.\Output\USART_Pol.axf]
Static Call Graph for image .\Output\USART_Pol.axf
# & #060CALLGRAPH & #062# ARM Linker, 4.1 [Build 791]: Last Updated: Sat Jan 28 14:28:59 2012
Maximum Stack Usage = 136 bytes + Unknown(Functions without stacksize, Cycles, Untraceable Function Pointers)
Call chain for Maximum Stack Depth:
__rt_entry_main & rArr; main & rArr; __2printf & rArr; _printf_char_file & rArr; _printf_char_common & rArr; __printf
Functions with no stack information
__user_initial_stackheap
Mutually Recursive functions
NMI_Handler & nbsp; & nbsp; & nbsp; & rArr; & nbsp; & nbsp; & nbsp; NMI_Handler
HardFault_Handler & nbsp; & nbsp; & nbsp; & rArr; & nbsp; & nbsp; & nbsp; HardFault_Handler
MemManage_Handler & nbsp; & nbsp; & nbsp; & rArr; & nbsp; & nbsp; & nbsp; MemManage_Handler
BusFault_Handler & nbsp; & nbsp; & nbsp; & rArr; & nbsp; & nbsp; & nbsp; BusFault_Handler
UsageFault_Handler & nbsp; & nbsp; & nbsp; & rArr; & nbsp; & nbsp; & nbsp; UsageFault_Handler
SVC_Handler & nbsp; & nbsp; & nbsp; & rArr; & nbsp; & nbsp; & nbsp; SVC_Handler
DebugMon_Handler & nbsp; & nbsp; & nbsp; & rArr; & nbsp; & nbsp; & nbsp; DebugMon_Handler
PendSV_Handler & nbsp; & nbsp; & nbsp; & rArr; & nbsp; & nbsp; & nbsp; PendSV_Handler
SysTick_Handler & nbsp; & nbsp; & nbsp; & rArr; & nbsp; & nbsp; & nbsp; SysTick_Handler
ADC_IRQHandler & nbsp; & nbsp; & nbsp; & rArr; & nbsp; & nbsp; & nbsp; ADC_IRQHandler
Function Pointers
ADC_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
BusFault_Handler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
CAN_RX1_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
CAN_SCE_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
DMAChannel1_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
DMAChannel2_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
DMAChannel3_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
DMAChannel4_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
DMAChannel5_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
DMAChannel6_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
DMAChannel7_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
DebugMon_Handler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
EXTI0_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
EXTI15_10_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
EXTI1_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
EXTI2_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
EXTI3_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
EXTI4_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
EXTI9_5_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
FLASH_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
HardFault_Handler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
I2C1_ER_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
I2C1_EV_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
I2C2_ER_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
I2C2_EV_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
MemManage_Handler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
NMI_Handler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
PVD_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
PendSV_Handler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
RCC_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
RTCAlarm_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
RTC_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
Reset_Handler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
SPI1_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
SPI2_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
SVC_Handler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
SysTick_Handler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
TAMPER_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
TIM1_BRK_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
TIM1_CC_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
TIM1_TRG_COM_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
TIM1_UP_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
TIM2_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
TIM3_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
TIM4_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
USART1_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
USART2_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
USART3_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
USBWakeUp_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
USB_HP_CAN_TX_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
USB_LP_CAN_RX0_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
UsageFault_Handler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
WWDG_IRQHandler from stm32f10x.o(.text) referenced from stm32f10x.o(RESET)
__main from __main.o(!!!main) referenced from stm32f10x.o(.text)
_printf_input_char from _printf_char_common.o(.text) referenced from _printf_char_common.o(.text)
fputc from retarget.o(.text) referenced from _printf_char_file.o(.text)
Global Symbols
__main (Thumb, 8 bytes, Stack size 0 bytes, __main.o(!!!main))
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;__scatterload
& gt; & gt; & nbsp; & nbsp; & nbsp;__rt_entry
__scatterload (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter))
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;__main
__scatterload_rt2 (Thumb, 44 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED)
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;__rt_entry
__scatterload_rt2_thumb_only (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED)
__scatterload_null (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED)
__scatterload_copy (Thumb, 26 bytes, Stack size unknown bytes, __scatter_copy.o(!!handler_copy), UNUSED)
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;__scatterload_copy
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;__scatterload_copy
__scatterload_zeroinit (Thumb, 28 bytes, Stack size unknown bytes, __scatter_zi.o(!!handler_zi), UNUSED)
_printf_percent (Thumb, 0 bytes, Stack size unknown bytes, _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000))
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;__printf
_printf_x (Thumb, 0 bytes, Stack size unknown bytes, _printf_x.o(.ARM.Collect$$_printf_percent$$0000000C))
[Stack] Max Depth = 48 + Unknown Stack Size
Call Chain = _printf_x & rArr; _printf_int_hex & rArr; _printf_int_common
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;_printf_int_hex
_printf_percent_end (Thumb, 0 bytes, Stack size unknown bytes, _printf_percent_end.o(.ARM.Collect$$_printf_percent$$00000017))
__rt_lib_init (Thumb, 0 bytes, Stack size unknown bytes, libinit.o(.ARM.Collect$$libinit$$00000000))
[Stack] Max Depth = 8 + Unknown Stack Size
Call Chain = __rt_lib_init & rArr; _fp_init
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;_fp_init
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;__rt_entry_li
__rt_lib_init_alloca_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002A))
__rt_lib_init_argv_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000028))
__rt_lib_init_atexit_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000017))
__rt_lib_init_clock_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001D))
__rt_lib_init_cpp_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002E))
__rt_lib_init_exceptions_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002C))
__rt_lib_init_fp_trap_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001B))
__rt_lib_init_getenv_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001F))
__rt_lib_init_heap_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000006))
__rt_lib_init_lc_collate_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000D))
__rt_lib_init_lc_ctype_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000F))
__rt_lib_init_lc_monetary_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000011))
__rt_lib_init_lc_numeric_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000013))
__rt_lib_init_lc_time_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000015))
__rt_lib_init_rand_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000A))
__rt_lib_init_return (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002F))
__rt_lib_init_signal_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000019))
__rt_lib_init_stdio_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000021))
__rt_lib_init_user_alloc_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000008))
__rt_lib_shutdown (Thumb, 0 bytes, Stack size unknown bytes, libshutdown.o(.ARM.Collect$$libshutdown$$00000000))
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;__rt_exit_ls
__rt_lib_shutdown_fp_trap_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000006))
__rt_lib_shutdown_heap_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000E))
__rt_lib_shutdown_return (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F))
__rt_lib_shutdown_signal_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000009))
__rt_lib_shutdown_stdio_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000003))
__rt_lib_shutdown_user_alloc_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000B))
__rt_entry (Thumb, 0 bytes, Stack size unknown bytes, rtentry.o(.ARM.Collect$$rtentry$$00000000))
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;__scatterload_rt2
& gt; & gt; & nbsp; & nbsp; & nbsp;__main
__rt_entry_presh_1 (Thumb, 0 bytes, Stack size unknown bytes, rtentry2.o(.ARM.Collect$$rtentry$$00000002))
__rt_entry_sh (Thumb, 0 bytes, Stack size unknown bytes, rtentry4.o(.ARM.Collect$$rtentry$$00000004))
[Stack] Max Depth = 8 + Unknown Stack Size
Call Chain = __rt_entry_sh & rArr; __user_setup_stackheap
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;__user_setup_stackheap
__rt_entry_li (Thumb, 0 bytes, Stack size unknown bytes, rtentry2.o(.ARM.Collect$$rtentry$$0000000A))
[Stack] Max Depth = 8 + Unknown Stack Size
Call Chain = __rt_entry_li & rArr; __rt_lib_init & rArr; _fp_init
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;__rt_lib_init
__rt_entry_postsh_1 (Thumb, 0 bytes, Stack size unknown bytes, rtentry2.o(.ARM.Collect$$rtentry$$00000009))
__rt_entry_main (Thumb, 0 bytes, Stack size unknown bytes, rtentry2.o(.ARM.Collect$$rtentry$$0000000D))
[Stack] Max Depth = 136 + Unknown Stack Size
Call Chain = __rt_entry_main & rArr; main & rArr; __2printf & rArr; _printf_char_file & rArr; _printf_char_common & rArr; __printf
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;main
& gt; & gt; & nbsp; & nbsp; & nbsp;exit
__rt_entry_postli_1 (Thumb, 0 bytes, Stack size unknown bytes, rtentry2.o(.ARM.Collect$$rtentry$$0000000C))
__rt_exit (Thumb, 0 bytes, Stack size unknown bytes, rtexit.o(.ARM.Collect$$rtexit$$00000000))
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;exit
__rt_exit_ls (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000003))
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;__rt_lib_shutdown
__rt_exit_prels_1 (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000002))
__rt_exit_exit (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000004))
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;_sys_exit
fputc (Thumb, 14 bytes, Stack size 16 bytes, retarget.o(.text))
[Stack] Max Depth = 16 Call Chain = fputc
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;SendChar
[Address Reference Count : 1] _printf_char_file.o(.text)
fgetc (Thumb, 16 bytes, Stack size 16 bytes, retarget.o(.text), UNUSED)
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;SendChar
& gt; & gt; & nbsp; & nbsp; & nbsp;GetKey
_ttywrch (Thumb, 12 bytes, Stack size 8 bytes, retarget.o(.text), UNUSED)
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;SendChar
ferror (Thumb, 8 bytes, Stack size 0 bytes, retarget.o(.text))
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;_printf_char_file
_sys_exit (Thumb, 4 bytes, Stack size 0 bytes, retarget.o(.text))
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;__rt_exit_exit
SPI1_Init (Thumb, 128 bytes, Stack size 32 bytes, spi.o(.text))
[Stack] Max Depth = 52 Call Chain = SPI1_Init & rArr; GPIO_Init
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;SPI_Init
& gt; & gt; & nbsp; & nbsp; & nbsp;SPI_Cmd
& gt; & gt; & nbsp; & nbsp; & nbsp;RCC_APB2PeriphClockCmd
& gt; & gt; & nbsp; & nbsp; & nbsp;GPIO_Init
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;main
SPI1_ReadWrite (Thumb, 56 bytes, Stack size 16 bytes, spi.o(.text), UNUSED)
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;SPI_I2S_SendData
& gt; & gt; & nbsp; & nbsp; & nbsp;SPI_I2S_ReceiveData
& gt; & gt; & nbsp; & nbsp; & nbsp;SPI_I2S_GetFlagStatus
stm32_EfiSetup (Thumb, 10 bytes, Stack size 0 bytes, stm32_init.o(.text))
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;stm32_Init
stm32_ClockSetup (Thumb, 50 bytes, Stack size 0 bytes, stm32_init.o(.text))
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;stm32_Init
stm32_IwdgSetup (Thumb, 34 bytes, Stack size 0 bytes, stm32_init.o(.text), UNUSED)
stm32_SysTickSetup (Thumb, 32 bytes, Stack size 0 bytes, stm32_init.o(.text), UNUSED)
stm32_RtcSetup (Thumb, 184 bytes, Stack size 0 bytes, stm32_init.o(.text), UNUSED)
stm32_TimerSetup (Thumb, 116 bytes, Stack size 0 bytes, stm32_init.o(.text), UNUSED)
stm32_GpioSetup (Thumb, 114 bytes, Stack size 0 bytes, stm32_init.o(.text))
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;stm32_Init
stm32_UsartSetup (Thumb, 124 bytes, Stack size 0 bytes, stm32_init.o(.text))
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;stm32_Init
stm32_ExtiSetup (Thumb, 2 bytes, Stack size 0 bytes, stm32_init.o(.text), UNUSED)
stm32_TamperSetup (Thumb, 98 bytes, Stack size 0 bytes, stm32_init.o(.text), UNUSED)
stm32_Init (Thumb, 20 bytes, Stack size 4 bytes, stm32_init.o(.text))
[Stack] Max Depth = 4 Call Chain = stm32_Init
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;stm32_UsartSetup
& gt; & gt; & nbsp; & nbsp; & nbsp;stm32_GpioSetup
& gt; & gt; & nbsp; & nbsp; & nbsp;stm32_ClockSetup
& gt; & gt; & nbsp; & nbsp; & nbsp;stm32_EfiSetup
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;main
stm32_GetPCLK1 (Thumb, 4 bytes, Stack size 0 bytes, stm32_init.o(.text), UNUSED)
Delay (Thumb, 12 bytes, Stack size 0 bytes, usart_pol.o(.text))
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;main
SendChar (Thumb, 22 bytes, Stack size 0 bytes, usart_pol.o(.text))
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;_ttywrch
& gt; & gt; & nbsp; & nbsp; & nbsp;fgetc
& gt; & gt; & nbsp; & nbsp; & nbsp;fputc
GetKey (Thumb, 22 bytes, Stack size 0 bytes, usart_pol.o(.text), UNUSED)
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;fgetc
main (Thumb, 60 bytes, Stack size 8 bytes, usart_pol.o(.text))
[Stack] Max Depth = 136 + Unknown Stack Size
Call Chain = main & rArr; __2printf & rArr; _printf_char_file & rArr; _printf_char_common & rArr; __printf
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;__2printf
& gt; & gt; & nbsp; & nbsp; & nbsp;Delay
& gt; & gt; & nbsp; & nbsp; & nbsp;stm32_Init
& gt; & gt; & nbsp; & nbsp; & nbsp;SPI1_Init
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;__rt_entry_main
Reset_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;NMI_Handler
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;NMI_Handler
[Address Reference Count : 1] stm32f10x.o(RESET)
HardFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;HardFault_Handler
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;HardFault_Handler
[Address Reference Count : 1] stm32f10x.o(RESET)
MemManage_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;MemManage_Handler
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;MemManage_Handler
[Address Reference Count : 1] stm32f10x.o(RESET)
BusFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;BusFault_Handler
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;BusFault_Handler
[Address Reference Count : 1] stm32f10x.o(RESET)
UsageFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;UsageFault_Handler
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;UsageFault_Handler
[Address Reference Count : 1] stm32f10x.o(RESET)
SVC_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;SVC_Handler
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;SVC_Handler
[Address Reference Count : 1] stm32f10x.o(RESET)
DebugMon_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;DebugMon_Handler
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;DebugMon_Handler
[Address Reference Count : 1] stm32f10x.o(RESET)
PendSV_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;PendSV_Handler
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;PendSV_Handler
[Address Reference Count : 1] stm32f10x.o(RESET)
SysTick_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;SysTick_Handler
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;SysTick_Handler
[Address Reference Count : 1] stm32f10x.o(RESET)
ADC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;ADC_IRQHandler
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;ADC_IRQHandler
[Address Reference Count : 1] stm32f10x.o(RESET)
CAN_RX1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
CAN_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
DMAChannel1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
DMAChannel2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
DMAChannel3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
DMAChannel4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
DMAChannel5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
DMAChannel6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
DMAChannel7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
EXTI0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
EXTI15_10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
EXTI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
EXTI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
EXTI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
EXTI4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
EXTI9_5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
FLASH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
I2C1_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
I2C1_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
I2C2_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
I2C2_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
PVD_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
RCC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
RTCAlarm_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
RTC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
SPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
SPI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
TAMPER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
TIM1_BRK_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
TIM1_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
TIM1_TRG_COM_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
TIM1_UP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
TIM2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
TIM3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
TIM4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
USART1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
USART2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
USART3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
USBWakeUp_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
USB_HP_CAN_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
USB_LP_CAN_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
WWDG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, stm32f10x.o(.text))
[Address Reference Count : 1] stm32f10x.o(RESET)
__user_initial_stackheap (Thumb, 0 bytes, Stack size unknown bytes, stm32f10x.o(.text))
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;__user_setup_stackheap
SPI_I2S_DeInit (Thumb, 76 bytes, Stack size 8 bytes, stm32f10x_spi.o(.text), UNUSED)
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;RCC_APB2PeriphResetCmd
& gt; & gt; & nbsp; & nbsp; & nbsp;RCC_APB1PeriphResetCmd
SPI_Init (Thumb, 80 bytes, Stack size 8 bytes, stm32f10x_spi.o(.text))
[Stack] Max Depth = 8 Call Chain = SPI_Init
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;SPI1_Init
I2S_Init (Thumb, 250 bytes, Stack size 56 bytes, stm32f10x_spi.o(.text), UNUSED)
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;RCC_GetClocksFreq
SPI_StructInit (Thumb, 28 bytes, Stack size 0 bytes, stm32f10x_spi.o(.text), UNUSED)
I2S_StructInit (Thumb, 26 bytes, Stack size 0 bytes, stm32f10x_spi.o(.text), UNUSED)
SPI_Cmd (Thumb, 26 bytes, Stack size 0 bytes, stm32f10x_spi.o(.text))
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;SPI1_Init
I2S_Cmd (Thumb, 26 bytes, Stack size 0 bytes, stm32f10x_spi.o(.text), UNUSED)
SPI_I2S_ITConfig (Thumb, 50 bytes, Stack size 16 bytes, stm32f10x_spi.o(.text), UNUSED)
SPI_I2S_DMACmd (Thumb, 30 bytes, Stack size 8 bytes, stm32f10x_spi.o(.text), UNUSED)
SPI_I2S_SendData (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_spi.o(.text), UNUSED)
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;SPI1_ReadWrite
SPI_I2S_ReceiveData (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_spi.o(.text), UNUSED)
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;SPI1_ReadWrite
SPI_NSSInternalSoftwareConfig (Thumb, 32 bytes, Stack size 0 bytes, stm32f10x_spi.o(.text), UNUSED)
SPI_SSOutputCmd (Thumb, 26 bytes, Stack size 0 bytes, stm32f10x_spi.o(.text), UNUSED)
SPI_DataSizeConfig (Thumb, 22 bytes, Stack size 0 bytes, stm32f10x_spi.o(.text), UNUSED)
SPI_TransmitCRC (Thumb, 10 bytes, Stack size 0 bytes, stm32f10x_spi.o(.text), UNUSED)
SPI_CalculateCRC (Thumb, 26 bytes, Stack size 0 bytes, stm32f10x_spi.o(.text), UNUSED)
SPI_GetCRC (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_spi.o(.text), UNUSED)
SPI_GetCRCPolynomial (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_spi.o(.text), UNUSED)
SPI_BiDirectionalLineConfig (Thumb, 30 bytes, Stack size 0 bytes, stm32f10x_spi.o(.text), UNUSED)
SPI_I2S_GetFlagStatus (Thumb, 24 bytes, Stack size 0 bytes, stm32f10x_spi.o(.text), UNUSED)
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;SPI1_ReadWrite
SPI_I2S_ClearFlag (Thumb, 8 bytes, Stack size 0 bytes, stm32f10x_spi.o(.text), UNUSED)
SPI_I2S_GetITStatus (Thumb, 68 bytes, Stack size 20 bytes, stm32f10x_spi.o(.text), UNUSED)
SPI_I2S_ClearITPendingBit (Thumb, 28 bytes, Stack size 8 bytes, stm32f10x_spi.o(.text), UNUSED)
__I$use$semihosting (Thumb, 0 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED)
__use_no_semihosting_swi (Thumb, 2 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED)
__2printf (Thumb, 20 bytes, Stack size 24 bytes, noretval__2printf.o(.text))
[Stack] Max Depth = 128 + Unknown Stack Size
Call Chain = __2printf & rArr; _printf_char_file & rArr; _printf_char_common & rArr; __printf
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;_printf_char_file
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;main
__printf (Thumb, 106 bytes, Stack size 24 bytes, __printf.o(.text))
[Stack] Max Depth = 24 + Unknown Stack Size
Call Chain = __printf
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;_printf_percent
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;_printf_char_common
_printf_int_hex (Thumb, 88 bytes, Stack size 16 bytes, _printf_hex_int.o(.text))
[Stack] Max Depth = 48 Call Chain = _printf_int_hex & rArr; _printf_int_common
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;_printf_int_common
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;_printf_x
_printf_longlong_hex (Thumb, 0 bytes, Stack size 16 bytes, _printf_hex_int.o(.text), UNUSED)
__use_two_region_memory (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED)
__rt_heap_escrow$2region (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED)
__rt_heap_expand$2region (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED)
_printf_int_common (Thumb, 184 bytes, Stack size 32 bytes, _printf_intcommon.o(.text))
[Stack] Max Depth = 32 Call Chain = _printf_int_common
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;_printf_int_hex
_printf_char_file (Thumb, 32 bytes, Stack size 16 bytes, _printf_char_file.o(.text))
[Stack] Max Depth = 104 + Unknown Stack Size
Call Chain = _printf_char_file & rArr; _printf_char_common & rArr; __printf
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;ferror
& gt; & gt; & nbsp; & nbsp; & nbsp;_printf_char_common
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;__2printf
_printf_char_common (Thumb, 32 bytes, Stack size 64 bytes, _printf_char_common.o(.text))
[Stack] Max Depth = 88 + Unknown Stack Size
Call Chain = _printf_char_common & rArr; __printf
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;__printf
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;_printf_char_file
__user_setup_stackheap (Thumb, 74 bytes, Stack size 8 bytes, sys_stackheap_outer.o(.text))
[Stack] Max Depth = 8 + Unknown Stack Size
Call Chain = __user_setup_stackheap
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;__user_initial_stackheap
& gt; & gt; & nbsp; & nbsp; & nbsp;__user_perproc_libspace
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;__rt_entry_sh
exit (Thumb, 12 bytes, Stack size 0 bytes, exit.o(.text))
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;__rt_exit
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;__rt_entry_main
__user_libspace (Thumb, 8 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED)
__user_perproc_libspace (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text))
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;__user_setup_stackheap
__user_perthread_libspace (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED)
__rt_fp_status_addr (Thumb, 8 bytes, Stack size 0 bytes, rt_fp_status_addr_intlibspace.o(.text))
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;_fp_init
GPIO_Init (Thumb, 160 bytes, Stack size 20 bytes, stm32f10x_gpio.o(i.GPIO_Init))
[Stack] Max Depth = 20 Call Chain = GPIO_Init
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;SPI1_Init
RCC_APB1PeriphResetCmd (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd), UNUSED)
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;SPI_I2S_DeInit
RCC_APB2PeriphClockCmd (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd))
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;SPI1_Init
RCC_APB2PeriphResetCmd (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd), UNUSED)
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;SPI_I2S_DeInit
RCC_GetClocksFreq (Thumb, 132 bytes, Stack size 12 bytes, stm32f10x_rcc.o(i.RCC_GetClocksFreq), UNUSED)
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;I2S_Init
_fp_init (Thumb, 14 bytes, Stack size 8 bytes, fpinit.o(x$fpl$fpinit))
[Stack] Max Depth = 8 Call Chain = _fp_init
[Calls] & gt; & gt; & nbsp; & nbsp; & nbsp;__rt_fp_status_addr
[Called By] & gt; & gt; & nbsp; & nbsp; & nbsp;__rt_lib_init
__fplib_config_pureend_doubles (Thumb, 0 bytes, Stack size unknown bytes, fpinit.o(x$fpl$fpinit), UNUSED)
Local Symbols
_printf_input_char (Thumb, 10 bytes, Stack size 0 bytes, _printf_char_common.o(.text))
[Address Reference Count : 1] _printf_char_common.o(.text)
Undefined Global Symbols
#include " STM32F10X_GPIO.h "
#ifndef __ENC28J60_H
#define __ENC28J60_H
// ENC28J60 Control Registers
// Control register definitions are a combination of address,
// bank number, and Ethernet/MAC/PHY indicator bits.
// - Register address (bits 0-4)
// - Bank number (bits 5-6)
// - MAC/PHY indicator (bit 7)
#define ADDR_MASK 0x1F
#define BANK_MASK 0x60
#define SPRD_MASK 0x80
// All-bank registers
#define EIE 0x1B
#define EIR 0x1C
#define ESTAT 0x1D
#define ECON2 0x1E
#define ECON1 0x1F
// Bank 0 registers
#define ERDPTL (0x00|0x00)
#define ERDPTH (0x01|0x00)
#define EWRPTL (0x02|0x00)
#define EWRPTH (0x03|0x00)
#define ETXSTL (0x04|0x00)
#define ETXSTH (0x05|0x00)
#define ETXNDL (0x06|0x00)
#define ETXNDH (0x07|0x00)
#define ERXSTL (0x08|0x00)
#define ERXSTH (0x09|0x00)
#define ERXNDL (0x0A|0x00)
#define ERXNDH (0x0B|0x00)
#define ERXRDPTL (0x0C|0x00)
#define ERXRDPTH (0x0D|0x00)
#define ERXWRPTL (0x0E|0x00)
#define ERXWRPTH (0x0F|0x00)
#define EDMASTL (0x10|0x00)
#define EDMASTH (0x11|0x00)
#define EDMANDL (0x12|0x00)
#define EDMANDH (0x13|0x00)
#define EDMADSTL (0x14|0x00)
#define EDMADSTH (0x15|0x00)
#define EDMACSL (0x16|0x00)
#define EDMACSH (0x17|0x00)
// Bank 1 registers
#define EHT0 (0x00|0x20)
#define EHT1 (0x01|0x20)
#define EHT2 (0x02|0x20)
#define EHT3 (0x03|0x20)
#define EHT4 (0x04|0x20)
#define EHT5 (0x05|0x20)
#define EHT6 (0x06|0x20)
#define EHT7 (0x07|0x20)
#define EPMM0 (0x08|0x20)
#define EPMM1 (0x09|0x20)
#define EPMM2 (0x0A|0x20)
#define EPMM3 (0x0B|0x20)
#define EPMM4 (0x0C|0x20)
#define EPMM5 (0x0D|0x20)
#define EPMM6 (0x0E|0x20)
#define EPMM7 (0x0F|0x20)
#define EPMCSL (0x10|0x20)
#define EPMCSH (0x11|0x20)
#define EPMOL (0x14|0x20)
#define EPMOH (0x15|0x20)
#define EWOLIE (0x16|0x20)
#define EWOLIR (0x17|0x20)
#define ERXFCON (0x18|0x20)
#define EPKTCNT (0x19|0x20)
// Bank 2 registers
#define MACON1 (0x00|0x40|0x80)
#define MACON2 (0x01|0x40|0x80)
#define MACON3 (0x02|0x40|0x80)
#define MACON4 (0x03|0x40|0x80)
#define MABBIPG (0x04|0x40|0x80)
#define MAIPGL (0x06|0x40|0x80)
#define MAIPGH (0x07|0x40|0x80)
#define MACLCON1 (0x08|0x40|0x80)
#define MACLCON2 (0x09|0x40|0x80)
#define MAMXFLL (0x0A|0x40|0x80)
#define MAMXFLH (0x0B|0x40|0x80)
#define MAPHSUP (0x0D|0x40|0x80)
#define MICON (0x11|0x40|0x80)
#define MICMD (0x12|0x40|0x80)
#define MIREGADR (0x14|0x40|0x80)
#define MIWRL (0x16|0x40|0x80)
#define MIWRH (0x17|0x40|0x80)
#define MIRDL (0x18|0x40|0x80)
#define MIRDH (0x19|0x40|0x80)
// Bank 3 registers
#define MAADR1 (0x00|0x60|0x80)
#define MAADR0 (0x01|0x60|0x80)
#define MAADR3 (0x02|0x60|0x80)
#define MAADR2 (0x03|0x60|0x80)
#define MAADR5 (0x04|0x60|0x80)
#define MAADR4 (0x05|0x60|0x80)
#define EBSTSD (0x06|0x60)
#define EBSTCON (0x07|0x60)
#define EBSTCSL (0x08|0x60)
#define EBSTCSH (0x09|0x60)
#define MISTAT (0x0A|0x60|0x80)
#define EREVID (0x12|0x60)
#define ECOCON (0x15|0x60)
#define EFLOCON (0x17|0x60)
#define EPAUSL (0x18|0x60)
#define EPAUSH (0x19|0x60)
// PHY registers
#define PHCON1 0x00
#define PHSTAT1 0x01
#define PHHID1 0x02
#define PHHID2 0x03
#define PHCON2 0x10
#define PHSTAT2 0x11
#define PHIE 0x12
#define PHIR 0x13
#define PHLCON 0x14
// ENC28J60 ERXFCON Register Bit Definitions
#define ERXFCON_UCEN 0x80
#define ERXFCON_ANDOR 0x40
#define ERXFCON_CRCEN 0x20
#define ERXFCON_PMEN 0x10
#define ERXFCON_MPEN 0x08
#define ERXFCON_HTEN 0x04
#define ERXFCON_MCEN 0x02
#define ERXFCON_BCEN 0x01
// ENC28J60 EIE Register Bit Definitions
#define EIE_INTIE 0x80
#define EIE_PKTIE 0x40
#define EIE_DMAIE 0x20
#define EIE_LINKIE 0x10
#define EIE_TXIE 0x08
#define EIE_WOLIE 0x04
#define EIE_TXERIE 0x02
#define EIE_RXERIE 0x01
// ENC28J60 EIR Register Bit Definitions
#define EIR_PKTIF 0x40
#define EIR_DMAIF 0x20
#define EIR_LINKIF 0x10
#define EIR_TXIF 0x08
#define EIR_WOLIF 0x04
#define EIR_TXERIF 0x02
#define EIR_RXERIF 0x01
// ENC28J60 ESTAT Register Bit Definitions
#define ESTAT_INT 0x80
#define ESTAT_LATECOL 0x10
#define ESTAT_RXBUSY 0x04
#define ESTAT_TXABRT 0x02
#define ESTAT_CLKRDY 0x01
// ENC28J60 ECON2 Register Bit Definitions
#define ECON2_AUTOINC 0x80
#define ECON2_PKTDEC 0x40
#define ECON2_PWRSV 0x20
#define ECON2_VRPS 0x08
// ENC28J60 ECON1 Register Bit Definitions
#define ECON1_TXRST 0x80
#define ECON1_RXRST 0x40
#define ECON1_DMAST 0x20
#define ECON1_CSUMEN 0x10
#define ECON1_TXRTS 0x08
#define ECON1_RXEN 0x04
#define ECON1_BSEL1 0x02
#define ECON1_BSEL0 0x01
// ENC28J60 MACON1 Register Bit Definitions
#define MACON1_LOOPBK 0x10
#define MACON1_TXPAUS 0x08
#define MACON1_RXPAUS 0x04
#define MACON1_PASSALL 0x02
#define MACON1_MARXEN 0x01
// ENC28J60 MACON2 Register Bit Definitions
#define MACON2_MARST 0x80
#define MACON2_RNDRST 0x40
#define MACON2_MARXRST 0x08
#define MACON2_RFUNRST 0x04
#define MACON2_MATXRST 0x02
#define MACON2_TFUNRST 0x01
// ENC28J60 MACON3 Register Bit Definitions
#define MACON3_PADCFG2 0x80
#define MACON3_PADCFG1 0x40
#define MACON3_PADCFG0 0x20
#define MACON3_TXCRCEN 0x10
#define MACON3_PHDRLEN 0x08
#define MACON3_HFRMLEN 0x04
#define MACON3_FRMLNEN 0x02
#define MACON3_FULDPX 0x01
// ENC28J60 MICMD Register Bit Definitions
#define MICMD_MIISCAN 0x02
#define MICMD_MIIRD 0x01
// ENC28J60 MISTAT Register Bit Definitions
#define MISTAT_NVALID 0x04
#define MISTAT_SCAN 0x02
#define MISTAT_BUSY 0x01
// ENC28J60 PHY PHCON1 Register Bit Definitions
#define PHCON1_PRST 0x8000
#define PHCON1_PLOOPBK 0x4000
#define PHCON1_PPWRSV 0x0800
#define PHCON1_PDPXMD 0x0100
// ENC28J60 PHY PHSTAT1 Register Bit Definitions
#define PHSTAT1_PFDPX 0x1000
#define PHSTAT1_PHDPX 0x0800
#define PHSTAT1_LLSTAT 0x0004
#define PHSTAT1_JBSTAT 0x0002
// ENC28J60 PHY PHCON2 Register Bit Definitions
#define PHCON2_FRCLINK 0x4000
#define PHCON2_TXDIS 0x2000
#define PHCON2_JABBER 0x0400
#define PHCON2_HDLDIS 0x0100
// ENC28J60 Packet Control Byte Bit Definitions
#define PKTCTRL_PHUGEEN 0x08
#define PKTCTRL_PPADEN 0x04
#define PKTCTRL_PCRCEN 0x02
#define PKTCTRL_POVERRIDE 0x01
// SPI operation codes
#define ENC28J60_READ_CTRL_REG 0x00
#define ENC28J60_READ_BUF_MEM 0x3A
#define ENC28J60_WRITE_CTRL_REG 0x40
#define ENC28J60_WRITE_BUF_MEM 0x7A
#define ENC28J60_BIT_FIELD_SET 0x80
#define ENC28J60_BIT_FIELD_CLR 0xA0
#define ENC28J60_SOFT_RESET 0xFF
// The RXSTART_INIT should be zero. See Rev. B4 Silicon Errata
// buffer boundaries applied to internal 8K ram
// the entire available packet buffer space is allocated
//
// start with recbuf at 0/
#define RXSTART_INIT 0x0
// receive buffer end
#define RXSTOP_INIT (0x1FFF-0x0600-1)
// start TX buffer at 0x1FFF-0x0600, pace for one full ethernet frame (~1500 bytes)
#define TXSTART_INIT (0x1FFF-0x0600)
// stp TX buffer at end of mem
#define TXSTOP_INIT 0x1FFF
//
// max frame length which the conroller will accept:
#define MAX_FRAMELEN 1500 // (note: maximum ethernet frame length would be 1518)
//#define MAX_FRAMELEN 600
#define ENC28J60_CS GPIO_Pin_4
#define ENC28J60_CSL() GPIOA- & gt; BRR = ENC28J60_CS;
#define ENC28J60_CSH() GPIOA- & gt; BSRR = ENC28J60_CS;
//SPI1³õʼ»¯
//void ENC28J60_Init(void);
unsigned char enc28j60ReadOp(unsigned char op, unsigned char address);
void enc28j60WriteOp(unsigned char op, unsigned char address, unsigned char data);
void enc28j60ReadBuffer(unsigned int len, unsigned char* data);
void enc28j60WriteBuffer(unsigned int len, unsigned char* data);
void enc28j60SetBank(unsigned char address);
unsigned char enc28j60Read(unsigned char address);
void enc28j60Write(unsigned char address, unsigned char data);
void enc28j60PhyWrite(unsigned char address, unsigned int data);
void enc28j60clkout(unsigned char clk);
void enc28j60Init(unsigned char* macaddr);
unsigned char enc28j60getrev(void);
void enc28j60PacketSend(unsigned int len, unsigned char* packet);
unsigned int enc28j60PacketReceive(unsigned int maxlen, unsigned char* packet);
//SPI1¶Áдһ×Ö½ÚÊý¾Ý
//INT8U ENC28J60_ReadWrite(INT8U writedat);
#endif