S3F833.pdf

Szukam schematu do radia" imago model iM-C3 "

Witam Szukam schematu do radia" imago model iM-C3 " (procesor to S3F833BXZZ-QX8B) szukam też rozpiski tego klocka Dodano po 5 7 : Objawy -radio nie reaguje na przycisk zał po odpięciu zasilania (napięcie na podtrzymaniu (pamięci) nadal + )po kilku sekundach następuje mignięcie podświetlenia radia, po tym czasie podaję plus głównego zasilania wtedy czasami przycisk zał/ wyłącz reaguje poprawnie działa do czasu odpięcia zasilania gdy to zrobimy usterka objawia się ponownie radio nie reaguje na zał. Czasami usterka ustępuje po resecie ale też tylko do czasu gdy się nie odejmie zasilania ponowne podłączenie radio nie reaguje usterką w moim przypadku był kwarc XT202 po wymianie radio zachowuje się poprawnie :-) temat zamykam jeśli ktoś ma schemat tego radia prosił bym o wrzucenie na stronki elektrody


S3F833B/F834B
8-BIT CMOS
MICROCONTROLLERS
USER'S MANUAL
Revision 1.10

Important Notice
The information in this publication has been carefully
checked and is believed to be entirely accurate at
the time of publication. Samsung assumes no
responsibility, however, for possible errors or
omissions, or for any consequences resulting from
the use of the information contained herein.
Samsung reserves the right to make changes in its
products or product specifications with the intent to
improve function or design at any time and without
notice and is not required to update this
documentation to reflect such changes.
This publication does not convey to a purchaser of
semiconductor devices described herein any license
under the patent rights of Samsung or others.
Samsung makes no warranty, representation, or
guarantee regarding the suitability of its products for
any particular purpose, nor does Samsung assume
any liability arising out of the application or use of
any product or circuit and specifically disclaims any
and all liability, including without limitation any
consequential or incidental damages.

" Typical " parameters can and do vary in different
applications. All operating parameters, including
" Typicals " must be validated for each customer
application by the customer's technical experts.
Samsung products are not designed, intended, or
authorized for use as components in systems
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Samsung was negligent regarding the design or
manufacture of said product.

S3F833B/F834B 8-Bit CMOS Microcontrollers
User's Manual, Revision 1.10
Publication Number: 21.10-S3-F833B/F834B-012009
(C) 2009 Samsung Electronics
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in
any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior
written consent of Samsung Electronics.
Samsung Electronics' microcontroller business has been awarded full ISO-14001
certification (BSI Certificate No. FM24653). All semiconductor products are
designed and manufactured in accordance with the highest quality standards and
objectives.
Samsung Electronics Co., Ltd.
San #24 Nongseo-Dong, Giheung-Gu
Yongin-City, Gyeonggi-Do, Korea
C.P.O. Box #37, Suwon 446-711
TEL: (82)-(31)-209-5238
FAX: (82)-(31)-209-6494
Home-Page URL: Http://www.samsungsemi.com
Printed in the Republic of Korea

NOTIFICATION OF REVISIONS
ORIGINATOR:

Samsung Electronics, SOC Development Group, Ki-Heung, South Korea

PRODUCT NAME:

S3F833B/F834B Microcontroller

DOCUMENT NAME:

S3F833B/F834B User's Manual, Revision 1.10

DOCUMENT NUMBER:

21.10-S3-F833B/F834B-012009

EFFECTIVE DATE:

January, 2009

SUMMARY:

As a result of additional product testing and evaluation, some specifications
published in the S3F833B/F834B User's Manual, Revision 1, have been
changed. These changes for S3F833B/F834B microcontroller, which are
described in detail in the Revision Descriptions section below, are related to the
followings:
-- Chapter 5. Interrupt Structure
-- Chapter 20. Electrical Data
-- Chapter 22. Flash MCU
-- Chapter 23. Development Tools

DIRECTIONS:

Please note the changes in your copy (copies) of the S3F833B/F834B User's
Manual, Revision 1.00. Or, simply attach the Revision Descriptions of the next
page to S3F833B/F834B User's Manual, Revision 1.

REVISION HISTORY
Revision

Date

Remark

1.00

October, 2006

This is the first edition.

1.10

January, 2009

This is the second edition.

REVISION DESCRIPTIONS (Rev 1.10)
Chapter

Page

Location

5

9

-

NOTE is added

15

-

Programming Tips for "How to clear interrupt pending bit" is added.

9

3

Figure 9-1

Missing figure is added.

20

5

Table 20-3

Partial contents are modified.

6
7

Figure 20-3 Notes are modified.
Figure 20-4

22

Description

-

Table is deleted and typing error is modified.

5, 6
23

4

-

The contents about " OPERATING MODE CHRACTERISTICS" is
deleted and the contents for " On Board Writing" is added

-

Chapter 23

" Chapter 23.Development Tools" is updated.

Preface
The S3F833B/F834B Microcontroller User's Manual is designed for application designers and programmers who
are using the S3F833B/F834B microcontroller for application development. It is organized in two main parts:
Part I Programming Model
Part II Hardware Descriptions
Part I contains software-related information to familiarize you with the microcontroller's architecture, programming
model, instruction set, and interrupt structure. It has six chapters:
Chapter 1
Product Overview
Chapter 4
Control Registers
Chapter 2
Address Spaces
Chapter 5
Interrupt Structure
Chapter 3
Addressing Modes
Chapter 6
Instruction Set
Chapter 1, " Product Overview, " is a high-level introduction to S3F833B/F834B with general product descriptions,
as well as detailed information about individual pin characteristics and pin circuit types.
Chapter 2, " Address Spaces, " describes program and data memory spaces, the internal register file, and register
addressing. Chapter 2 also describes working register addressing, as well as system stack and user-defined
stack operations.
Chapter 3, " Addressing Modes, " contains detailed descriptions of the addressing modes that are supported by the
S3F8-series CPU.
Chapter 4, " Control Registers, " contains overview tables for all mapped system and peripheral control register
values, as well as detailed one-page descriptions in a standardized format. You can use these easy-to-read,
alphabetically organized, register descriptions as a quick-reference source when writing programs.
Chapter 5, " Interrupt Structure, " describes the S3F833B/F834B interrupt structure in detail and further prepares
you for additional information presented in the individual hardware module descriptions in Part II.
Chapter 6, " Instruction Set, " describes the features and conventions of the instruction set used for all S3F8-series
microcontrollers. Several summary tables are presented for orientation and reference. Detailed descriptions of
each instruction are presented in a standard format. Each instruction description includes one or more practical
examples of how to use the instruction when writing an application program.
A basic familiarity with the information in Part I will help you to understand the hardware module descriptions in
Part II. If you are not yet familiar with the S3F8-series microcontroller family and are reading this manual for the
first time, we recommend that you first read Chapters 1-3 carefully. Then, briefly look over the detailed
information in Chapters 4, 5, and 6. Later, you can reference the information in Part I as necessary.
Part II " hardware Descriptions, " has detailed information about specific hardware components of the
S3F833B/F834B microcontroller. Also included in Part II are electrical, mechanical, Flash MCU, and development
tools data. It has 17 chapters:
Chapter 7
Chapter 8
Chapter 9
Chapter 10
Chapter 11
Chapter 12
Chapter 13
Chapter 14
Chapter 15

Clock Circuit
RESET and Power-Down
I/O Ports
Basic Timer and Timer 0
8-bit Timer 1
16-bit Timer 2
Watch Timer
LCD Controller/Driver
10-bit-to-Digital Converter

S3F833B/F834B MICROCONTROLLER

Chapter 16
Chapter 17
Chapter 18
Chapter 19
Chapter 20
Chapter 21
Chapter 22
Chapter 23

Serial I/O Interface
UART
PLL Frequency Synthesizer
Intermediate Frequency Counter
Electrical Data
Mechanical Data
S3F833B/F834B Flash MCU
Development Tools

iii

Table of Contents
Part I -- Programming Model
Chapter 1

Product Overview

S3F8-Series Microcontrollers.......................................................................................................................1-1
S3F833B/F834B Microcontroller ..................................................................................................................1-1
Features .......................................................................................................................................................1-2
Block Diagram ..............................................................................................................................................1-4
Pin Assignment ............................................................................................................................................1-5
Pin Descriptions ...........................................................................................................................................1-7
Pin Circuits ...................................................................................................................................................1-11

Chapter 2

Address Spaces

Overview ......................................................................................................................................................2-1
Program Memory (ROM)..............................................................................................................................2-2
Smart Option.........................................................................................................................................2-3
Register Architecture....................................................................................................................................2-4
Register Page Pointer (PP) ..................................................................................................................2-6
Register Set 1 .......................................................................................................................................2-8
Register Set 2 .......................................................................................................................................2-8
Prime Register Space...........................................................................................................................2-9
Working Registers ................................................................................................................................2-10
Using the Register Points .....................................................................................................................2-11
Register Addressing.....................................................................................................................................2-13
Common Working Register Area (C0H-CFH) .....................................................................................2-15
4-Bit Working Register Addressing ......................................................................................................2-16
8-Bit Working Register Addressing ......................................................................................................2-18
System and User Stack................................................................................................................................2-20

Chapter 3

Addressing Modes

Overview ......................................................................................................................................................3-1
Register Addressing Mode (R).....................................................................................................................3-2
Indirect Register Addressing Mode (IR).......................................................................................................3-3
Indexed Addressing Mode (X)......................................................................................................................3-7
Direct Address Mode (DA) ...........................................................................................................................3-10
Indirect Address Mode (IA) ..........................................................................................................................3-12
Relative Address Mode (RA)........................................................................................................................3-13
Immediate Mode (IM) ...................................................................................................................................3-14

S3F833B/F834B MICROCONTROLLER

v

Table of Contents (Continued)
Chapter 4

Control Registers

Overview...................................................................................................................................................... 4-1

Chapter 5

Interrupt Structure

Overview...................................................................................................................................................... 5-1
Interrupt Types ..................................................................................................................................... 5-2
S3F833B/F834B Interrupt Structure .................................................................................................... 5-3
Interrupt Vector Addresses .................................................................................................................. 5-5
Enable/Disable Interrupt Instructions (EI, DI) ...................................................................................... 5-7
System-Level Interrupt Control Registers............................................................................................ 5-7
Interrupt Processing Control Points ..................................................................................................... 5-8
Peripheral Interrupt Control Registers ................................................................................................. 5-9
System Mode Register (SYM) ............................................................................................................. 5-10
Interrupt Mask Register (IMR) ............................................................................................................. 5-11
Interrupt Priority Register (IPR)............................................................................................................ 5-12
Interrupt Request Register (IRQ)......................................................................................................... 5-14
Interrupt Pending Function Types........................................................................................................ 5-15
Interrupt Source Polling Sequence ...................................................................................................... 5-16
Interrupt Service Routines ??????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 5-16
Generating interrupt Vector Addresses ............................................................................................... 5-17
Nesting of Vectored Interrupts ............................................................................................................. 5-17
Instruction Pointer (IP) ......................................................................................................................... 5-17
Fast Interrupt Processing..................................................................................................................... 5-17

Chapter 6

Instruction Set

Overview...................................................................................................................................................... 6-1
Data Types........................................................................................................................................... 6-1
Register Addressing............................................................................................................................. 6-1
Addressing Modes ............................................................................................................................... 6-1
Flags Register (FLAGS)....................................................................................................................... 6-6
Flag Descriptions ................................................................................................................................. 6-7
Instruction Set Notation........................................................................................................................ 6-8
Condition Codes .................................................................................................................................. 6-12
Instruction Descriptions........................................................................................................................ 6-13

vi

S3F833B/F834B MICROCONTROLLER

Table of Contents (Continued)
Part II Hardware Descriptions
Chapter 7

Clock Circuit

Overview ......................................................................................................................................................7-1
System Clock Circuit ............................................................................................................................7-1
Main Oscillator Circuits.........................................................................................................................7-2
Sub Oscillator Circuits ..........................................................................................................................7-2
Clock Status During Power-Down Modes ............................................................................................7-3
System Clock Control Register (CLKCON) ..........................................................................................7-4
Oscillator Control Register (OSCCON) ................................................................................................7-5
Switching the CPU Clock......................................................................................................................7-6
OSC PLL Control Register (OSCPLLR) ...............................................................................................7-8

Chapter 8

RESET and Power-Down

System Reset ...............................................................................................................................................8-1
Overview...............................................................................................................................................8-1
normal mode reset operation................................................................................................................8-1
Hardware Reset Values........................................................................................................................8-2
Power-Down Modes.....................................................................................................................................8-5
Stop Mode ............................................................................................................................................8-5
Idle Mode ..............................................................................................................................................8-6

Chapter 9

I/O Ports

Overview ......................................................................................................................................................9-1
Port Data Registers ..............................................................................................................................9-3
Port 0 ....................................................................................................................................................9-4
Port 1 ....................................................................................................................................................9-6
Port 2 ....................................................................................................................................................9-9
Port 3 ....................................................................................................................................................9-11
Port 4, 5 ................................................................................................................................................9-13
Port 6, 7 ................................................................................................................................................9-14
Port 8, 9 ................................................................................................................................................9-15
Port 10 ..................................................................................................................................................9-17

S3F833B/F834B MICROCONTROLLER

vii

Table of Contents (Continued)
Chapter 10

Basic Timer

Overview...................................................................................................................................................... 10-1
Basic Timer (BT).......................................................................................................................................... 10-1
Basic Timer Control Register (BTCON)............................................................................................... 10-2
Basic Timer Function Description ........................................................................................................ 10-3
8-Bit Timer/Counter 0 .................................................................................................................................. 10-5
Timer/Counter 0 Control Register (T0CON) ........................................................................................ 10-5
Timer 0 Function Description ............................................................................................................... 10-8

Chapter 11

8-bit Timer 1

Overview ....................................................................................................................................................... 11-1
Function Description ............................................................................................................................ 11-1
Timer 1 Control Register (T1CON) ...................................................................................................... 11-2
Block Diagram...................................................................................................................................... 11-3

Chapter 12

16-bit Timer 2

Overview...................................................................................................................................................... 12-1
Function Description ............................................................................................................................ 12-1
Timer 2 Control Register (T2CON) ...................................................................................................... 12-2
Block Diagram...................................................................................................................................... 12-3

Chapter 13

Watch Timer

Overview...................................................................................................................................................... 13-1
Watch Timer Control Register (WTCON) ............................................................................................ 13-2
Watch Timer Circuit Diagram............................................................................................................... 13-3

Chapter 14

LCD Controller/Driver

Overview...................................................................................................................................................... 14-1
LCD Circuit Diagram ???????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 14-2
LCD RAM Address Area ...................................................................................................................... 14-3
LCD Mode Control Register (LMOD)................................................................................................... 14-4
LCD Control Register (LCON) ............................................................................................................. 14-5
LCD voltage dividing resistor ............................................................................................................... 14-6
Common (COM) Signals...................................................................................................................... 14-7
Segment (SEG) Signals....................................................................................................................... 14-7

viii

S3F833B/F834B MICROCONTROLLER

Table of Contents (Continued)
Chapter 15

10-bit Analog-to-Digital Converter

Overview ......................................................................................................................................................15-1
Function Description ....................................................................................................................................15-1
Conversion Timing................................................................................................................................15-2
A/D Converter Control Register (ADCON) ...........................................................................................15-2
Internal Reference Voltage Levels .......................................................................................................15-3
Block Diagram ..............................................................................................................................................15-4

Chapter 16

Serial I/O Interface

Overview........................................................................................................................................................16-1
Programming Procedure ......................................................................................................................16-1
SIO0 and SIO1 Control Registers (SIO0CON, SIO1CON) ..................................................................16-2
SIO0 and SIO1 Pre-Scaler Register (SIO0PS, SIO1PS) .....................................................................16-4
SIO Block Diagram (SIO0, SIO1)..................................................................................................................16-5
Serial I/O Timing Diagram (SIO0, SIO1) ..............................................................................................16-6

Chapter 17

UART

Overview ......................................................................................................................................................17-1
Programming Procedure ......................................................................................................................17-1
UART0 Control Register (UART0CON) ...............................................................................................17-2
UART1 Control Register (UART1CON) ...............................................................................................17-3
UART0 Interrupt Pending bits...............................................................................................................17-4
UART1 Interrupt Pending bits...............................................................................................................17-5
UART0 Data Register (UDATA0) .........................................................................................................17-6
UART1 Data Register (UDATA1) .........................................................................................................17-6
UART0 Baud Rate Data Register (BRDATA0).....................................................................................17-7
UART1 Baud Rate Data Register (BRDATA1).....................................................................................17-7
Baud Rate Calculations ........................................................................................................................17-7
Block Diagram ..............................................................................................................................................17-9
UART0/ UART1 Mode 0 Function Description .....................................................................................17-11
Serial Port Mode 1 Function Description..............................................................................................17-13
Serial Port Mode 2 Function Description..............................................................................................17-14
Serial Port Mode 3 Function Description..............................................................................................17-15
Serial Communication for Multiprocessor Configurations ....................................................................17-17

S3F833B/F834B MICROCONTROLLER

ix

Table of Contents (Concluded)
Chapter 18

PLL Frequency Synthesizer

Overview...................................................................................................................................................... 18-1
PLL Frequency Synthesizer Function ......................................................................................................... 18-2
PLL Data Register (PLLD)........................................................................................................................... 18-3
Reference Frequency Generator................................................................................................................. 18-4
PLL Mode Register (PLLMOD) ................................................................................................................... 18-5
PLL Reference Frequency Selection Register (PLLREF) ........................................................................... 18-7
Phase Detector, Charge PUMP, and Unlock Detector................................................................................ 18-8
Using the PLL Frequency Synthesizer ........................................................................................................ 18-9

Chapter 19

Intermediate Frequency Counter

Overview...................................................................................................................................................... 19-1
IFC Mode Register (IFMOD) ....................................................................................................................... 19-2
IFC Gate Flag Register (PLLREF.5) ........................................................................................................... 19-3
GATE Times ................................................................................................................................................ 19-4
IF Counter (IFC) Operation.......................................................................................................................... 19-7
Input Pin Configuration ................................................................................................................................ 19-8
IFC Data Calculation ................................................................................................................................... 19-9

Chapter 20

Electrical Data

Overview ....................................................................................................................................................... 20-1

Chapter 21

Mechanical Data

Overview ....................................................................................................................................................... 21-1

Chapter 22

S3F833B/F834B Flash MCU

Overview ....................................................................................................................................................... 22-1
On board writing ........................................................................................................................................... 22-5

x

S3F833B/F834B MICROCONTROLLER

Table of Contents (Concluded)
Chapter 23

Development Tools

Overview........................................................................................................................................................23-1
Target Boards .......................................................................................................................................23-1
Programming Socket Adapter ..............................................................................................................23-1
TB833B/834B Target Board .................................................................................................................23-3
Third parties for Development Tools ....................................................................................................23-6
OTP/MTP Programmer (Writer)............................................................................................................23-7

S3F833B/F834B MICROCONTROLLER

xi

List of Figures
Figure
Number

Title

Page
Number

1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
1-9
1-10
1-11
1-12
1-13
1-14
1-15
1-16
1-17
1-18
1-19

Block Diagram ............................................................................................................1-4
S3F833B Pin Assignments (100-QFP-1420C)...........................................................1-5
S3F834B Pin Assignments (100-TQFP-1414) ...........................................................1-6
Pin Circuit Type A.......................................................................................................1-11
Pin Circuit Type B-5 (CE) ...........................................................................................1-11
Pin Circuit Type D-5 (P10.4).......................................................................................1-11
Pin Circuit Type B (nRESET) .....................................................................................1-11
Pin Circuit Type C.......................................................................................................1-11
Pin Circuit Type D-6 (P10.5-P10.7)............................................................................1-11
Pin Circuit Type D-9 (P1.4-P1.7)................................................................................1-12
Pin Circuit Type D-7 (P1.0-P1.3)................................................................................1-12
Pin Circuit Type E-2 (P3)............................................................................................1-12
Pin Circuit Type E-4 (P0)............................................................................................1-12
Pin Circuit Type F-16 (P2) ..........................................................................................1-13
Pin Circuit Type F-17 (P9.4-P9.7) ..............................................................................1-13
Pin Circuit Type F-18 (P10.0-P10.3) ..........................................................................1-13
Pin Circuit Type H-39 .................................................................................................1-13
Pin Circuit Type H-41 (P6-P8, P9.0-P9.3)..................................................................1-14
Pin Circuit Type H-42 (P4, P5) ...................................................................................1-14

2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16

Program Memory Address Space ..............................................................................2-2
Smart Option...............................................................................................................2-3
Internal Register File Organization.............................................................................2-5
Register Page Pointer (PP) ........................................................................................2-6
Set 1, Set 2, Prime Area Register, and LCD Data Register Map...............................2-9
8-Byte Working Register Areas (Slices) .....................................................................2-10
Contiguous 16-Byte Working Register Block .............................................................2-11
Non-Contiguous 16-Byte Working Register Block .....................................................2-12
16-Bit Register Pair ....................................................................................................2-13
Register File Addressing ............................................................................................2-14
Common Working Register Area................................................................................2-15
4-Bit Working Register Addressing ............................................................................2-17
4-Bit Working Register Addressing Example .............................................................2-17
8-Bit Working Register Addressing ............................................................................2-18
8-Bit Working Register Addressing Example .............................................................2-19
Stack Operations ........................................................................................................2-20

S3F833B/F834B MICROCONTROLLER

xiii

List of Figures (Continued)
Figure
Number

Title

Page
Number

3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14

Register Addressing................................................................................................... 3-2
Working Register Addressing .................................................................................... 3-2
Indirect Register Addressing to Register File ............................................................ 3-3
Indirect Register Addressing to Program Memory..................................................... 3-4
Indirect Working Register Addressing to Register File.............................................. 3-5
Indirect Working Register Addressing to Program or Data Memory ......................... 3-6
Indexed Addressing to Register File.......................................................................... 3-7
Indexed Addressing to Program or Data Memory with Short Offset ......................... 3-8
Indexed Addressing to Program or Data Memory ..................................................... 3-9
Direct Addressing for Load Instructions..................................................................... 3-10
Direct Addressing for Call and Jump Instructions...................................................... 3-11
Indirect Addressing .................................................................................................... 3-12
Relative Addressing ................................................................................................... 3-13
Immediate Addressing ............................................................................................... 3-14

4-1

Register Description Format ...................................................................................... 4-6

5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9

S3F8-Series Interrupt Types...................................................................................... 5-2
S3F833B/F834B Interrupt Structure .......................................................................... 5-4
ROM Vector Address Area ........................................................................................ 5-5
Interrupt Function Diagram ........................................................................................ 5-8
System Mode Register (SYM) ................................................................................... 5-10
Interrupt Mask Register (IMR) ................................................................................... 5-11
Interrupt Request Priority Groups .............................................................................. 5-12
Interrupt Priority Register (IPR) ................................................................................. 5-13
Interrupt Request Register (IRQ)............................................................................... 5-14

6-1

System Flags Register (FLAGS) ............................................................................... 6-6

7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-13

Crystal/Ceramic Oscillator (fx) ................................................................................... 7-2
External Oscillator (fx)................................................................................................ 7-2
RC Oscillator (fx)........................................................................................................ 7-2
Crystal/Ceramic Oscillator (fxt) .................................................................................. 7-2
External Oscillator (fxt)............................................................................................... 7-2
System Clock Circuit Diagram ................................................................................... 7-3
System Clock Control Register (CLKCON) ............................................................... 7-4
Oscillator Control Register (OSCCON) ..................................................................... 7-5
STOP Control Register (STPCON)............................................................................ 7-7
OSC PLL Control Register (OSCPLLR) .................................................................... 7-8
System Clock Selection Diagram .............................................................................. 7-11
OSC PLL Circuit Diagram .......................................................................................... 7-11
LPF External Circuit Diagram .................................................................................... 7-12

xiv

S3F833B/F834B MICROCONTROLLER

List of Figures (Continued)
Figure
Number

Title

Page
Number

9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
9-15
9-16
9-17
9-18
9-19

S3F833B/F834B I/O Port Data Register Format........................................................9-3
Port 0 High-Byte Control Register (P0CONH) ...........................................................9-4
Port 0 Low-Byte Control Register (P0CONL) .............................................................9-5
Port 0 Pull-up Resistor Enable Register (P0PUR) .....................................................9-5
Port 1 High-Byte Control Register (P1CONH) ...........................................................9-7
Port 1 Low-Byte Control Register (P1CONL) .............................................................9-7
Port 1 Interrupt Control Register (P1INT)...................................................................9-8
Port 1 Interrupt Pending Register (P1PND) ...............................................................9-8
Port 2 High-Byte Control Register (P2CONH) ...........................................................9-9
Port 2 Low-Byte Control Register (P2CONL).............................................................9-10
Port 3 High-Byte Control Register (P3CONH) ...........................................................9-11
Port 3 Low-Byte Control Register (P3CONL).............................................................9-12
Port 3 Pull-up Resistor Enable Register (P3PUR) .....................................................9-12
Port Group 0 Control Register (PG0CON) .................................................................9-13
Port Group 1 Control Register (PG1CON) .................................................................9-14
Port Group 2 Control Register (PG2CON) .................................................................9-15
Port 9 High-byte Control Register (P9CONH)............................................................9-16
Port 10 High-Byte Control Register (P10CONH) .......................................................9-17
Port 10 Low-Byte Control Register (P10CONL).........................................................9-18

10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8

Basic Timer Control Register (BTCON) .....................................................................10-2
Basic Timer Block Diagram ........................................................................................10-4
Timer 0 Control Register (T0CON).............................................................................10-6
Interrupt Pending Register (INTPND).........................................................................10-7
Simplified Timer 0 Function Diagram: Interval Timer Mode .......................................10-8
Simplified Timer 0 Function Diagram: PWM Mode ....................................................10-9
Simplified Timer 0 Function Diagram: Capture Mode ................................................10-10
Timer 0 Block Diagram ...............................................................................................10-11

11-1
11-2

Timer 1 Control Register (T1CON).............................................................................11-2
Timer 1 Functional Block Diagram .............................................................................11-3

S3F833B/F834B MICROCONTROLLER

xv

List of Figures (Continued)
Figure
Number

Title

Page
Number

12-1
12-2

Timer 2 Control Register (T2CON) ............................................................................ 12-2
Timer 2 Functional Block Diagram............................................................................. 12-3

13-1
13-2

Watch Timer Control Register (WTCON) .................................................................. 13-2
Watch Timer Circuit Diagram..................................................................................... 13-3

14-1
14-2
14-3
14-4
14-5
14-6
14-7
14-8
14-9
14-10

LCD Function Diagram .............................................................................................. 14-1
LCD Circuit Diagram .................................................................................................. 14-2
LCD Display Data RAM Organization........................................................................ 14-3
LCD Mode Control Register (LMOD)......................................................................... 14-4
LCD Control Register (LCON) ................................................................................... 14-5
LCD Voltage Dividing Resistor Connection ............................................................... 14-6
LCD Signal Waveforms (1/2 Duty, 1/2Bias) .............................................................. 14-8
LCD Signal Waveforms (1/3 Duty, 1/3 Bias) ............................................................. 14-9
LCD Signal Waveforms (1/4 Duty, 1/3 Bias) ............................................................. 14-10
LCD Signal Waveforms (1/8 Duty, 1/4 Bias) ............................................................. 14-11

15-1
15-2
15-3
15-4

A/D Converter Control Register (ADCON) ................................................................ 15-2
A/D Converter Data Register (ADDATAH/L) ............................................................. 15-3
A/D Converter Functional Block Diagram.................................................................. 15-4
Recommended A/D Converter Circuit for Highest Absolute Accuracy...................... 15-5

16-1
16-2
16-3
16-4
16-5
16-6
16-7

Serial I/O Module Control Register (SIO0CON) ........................................................ 16-2
Serial I/O Module Control Register (SIO1CON) ........................................................ 16-3
SIO0 Pre-scaler Register (SIO0PS) .......................................................................... 16-4
SIO1 Pre-scaler Register (SIO1PS) .......................................................................... 16-4
SIO0 Functional Block Diagram................................................................................. 16-5
SIO1 Functional Block Diagram................................................................................. 16-5
Serial I/O Timing in Transmit/Receive Mode
(Tx at falling, SIO0CON.4 or SIO1CON.4 = 0) .......................................................... 16-6
Serial I/O Timing in Transmit/Receive Mode
(Tx at rising, SIO0CON.4 or SIO1CON.4 = 1) ........................................................... 16-6

16-8

xvi

S3F833B/F834B MICROCONTROLLER

List of Figures (Concluded)
Figure
Number

Title

Page
Number

17-1
17-2
17-3
17-4
17-5
17-6
17-7
17-8
17-9
17-10
17-11
17-12
17-13
17-14
17-15

UART0 Control Register (UART0CON) .....................................................................17-2
UART1 Control Register (UART1CON) .....................................................................17-3
UART0 Interrupt Pending Bits (INTPND.2-.3) ...........................................................17-4
UART1 Interrupt Pending Bits (INTPND.5-.4) ...........................................................17-5
UART0 Data Register (UDATA0) ...............................................................................17-6
UART1 Data Register (UDATA1) ...............................................................................17-6
UART0 Baud Rate Data Register (BRDATA0) ..........................................................17-7
UART1 Baud Rate Data Register (BRDATA1) ..........................................................17-7
UART0 Functional Block Diagram..............................................................................17-9
UART1 Functional Block Diagram..............................................................................17-10
Timing Diagram for Serial Port Mode 0 Operation .....................................................17-12
Timing Diagram for Serial Port Mode 1 Operation .....................................................17-13
Timing Diagram for Serial Port Mode 2 Operation .....................................................17-14
Timing Diagram for Serial Port Mode 3 Operation .....................................................17-16
Connection Example for Multiprocessor Serial Data Communications .....................17-18

18-1
18-2
18-3

Block Diagram of the PLL Frequency Synthesizer.....................................................18-1
PLL Register Configuration ........................................................................................18-3
Reference Frequency Generator................................................................................18-4

19-1
19-2
19-3
19-4
19-5

IF Counter Block Diagram ..........................................................................................19-1
Gate Timing (2, 8, or 16 ms).......................................................................................19-4
Gate Timing (When Open) .........................................................................................19-5
Gate Timing (1-ms Error)............................................................................................19-6
AMIF and FMIF Pin Configuration ..............................................................................19-8

20-1
20-2
20-3
20-4
20-5
20-6
20-7
20-8
20-9
20-10
20-11

Input Timing for External Interrupts ............................................................................20-5
Input Timing for nRESET............................................................................................20-5
Stop Mode Release Timing Initiated by RESET.........................................................20-6
Stop Mode Release Timing Initiated by Interrupts .....................................................20-7
LVR (Low Voltage Reset) Timing ...............................................................................20-9
Serial Data Transfer Timing........................................................................................20-11
Waveform for UART Timing Characteristics ..............................................................20-12
Timing Waveform for the UART Module ....................................................................20-13
Clock Timing Measurement at XIN .............................................................................20-15
Clock Timing Measurement at XTIN ...........................................................................20-15
Operating Voltage Range (TA = -25 °C to + 85 °C)...................................................20-16

20-12

Operating Voltage Range (TA = -40 °C to + 85 °C)...................................................20-16

S3F833B/F834B MICROCONTROLLER

xvii

List of Figures (Concluded)
Figure
Number

Title

Page
Number

21-1
21-2

Package Dimensions (100-QFP-1420C) ................................................................... 21-1
Package Dimensions (100-TQFP-1414) ................................................................... 21-2

22-1
22-2
22-3

S3F833B Pin Assignments (100-QFP-1420C) .......................................................... 22-2
S3F834B Pin Assignments (100-TQFP-1414) .......................................................... 22-3
PCB Design Guide for on Board Programming ......................................................... 22-5

23-1
23-2
23-3
23-4

Emulator Product Configuration................................................................................. 23-2
TB833B/834B Target Board Configuration................................................................ 23-3
50-Pin Connectors (J101, J102) for TB833B/834B ................................................... 23-5
S3E833B Cables for 100-QFP Package ................................................................... 23-5

xviii

S3F833B/F834B MICROCONTROLLER

List of Tables
Table
Number

Title

Page
Number

1-1

S3F833B/F834B Pin Descriptions..............................................................................1-7

2-1

S3F833B/F834B Register Type Summary .................................................................2-4

4-1
4-2
4-3
4-4

Set 1 Registers ...........................................................................................................4-2
Page 0 Registers ........................................................................................................4-2
Set 1, Bank 0 Registers..............................................................................................4-3
Set 1, Bank 1 Registers..............................................................................................4-4

5-1
5-2
5-3

Interrupt Vectors .........................................................................................................5-6
Interrupt Control Register Overview ...........................................................................5-7
Interrupt Source Control and Data Registers .............................................................5-9

6-1
6-2
6-3
6-4
6-5
6-6

Instruction Group Summary........................................................................................6-2
Flag Notation Conventions .........................................................................................6-8
Instruction Set Symbols..............................................................................................6-8
Instruction Notation Conventions ...............................................................................6-9
Opcode Quick Reference ...........................................................................................6-10
Condition Codes .........................................................................................................6-12

8-1
8-2
8-3
8-4

S3F833B/F834B Set 1 Register and Values after nRESET.......................................8-2
S3F833B/F834B Page 0 Register and Values after nRESET ...................................8-2
S3F833B/F834B Set 1, Bank0 Register and Values after nRESET ..........................8-3
S3F833B/F834B Set 1, Bank1 Register and Values after nRESET ..........................8-4

9-1
9-2

S3F833B/F834B Port Configuration Overview...........................................................9-2
Port Data Register Summary......................................................................................9-3

S3F833B/F834B MICROCONTROLLER

xix

List of Tables (Continued)
Table
Number

Title

Page
Number

17-1

Commonly Used Baud Rates Generated by BRDATA0/ BRDATA1 ......................... 17-9

18-1
18-2
18-3

PLLMOD Organization............................................................................................... 18-6
PLLREF Register Organization(When IFMOD.4 = 0)................................................ 18-7
PLLREF Register Organization(When IFMOD.4 = 1)................................................ 18-7

19-1
19-2
19-3

IFMOD Organization .................................................................................................. 19-2
IF Counter Frequency Characteristics....................................................................... 19-7
Reset Vector Address ................................................................................................ 19-7

20-1
20-2
20-3
20-4
20-5
20-6
20-7
20-8
20-9
20-10
20-11
20-12
20-13
20-14
20-15

Absolute Maximum Ratings ....................................................................................... 20-2
D.C. Electrical Characteristics ................................................................................... 20-2
A.C. Electrical Characteristics ................................................................................... 20-5
Input/Output Capacitance .......................................................................................... 20-6
Data Retention Supply Voltage in Stop Mode ........................................................... 20-6
A/D Converter Electrical Characteristics ................................................................... 20-8
Low Voltage Reset Electrical Characteristics ............................................................ 20-9
PLL Electrical Characteristics .................................................................................... 20-1
PLL Oscillator Electrical Characteristics.................................................................... 20-9
Synchronous SIO Electrical Characteristics .............................................................. 20-10
UART TIMING characteristics IN MODE 0(11.1MHz) ............................................... 20-12
Main Oscillator Characteristics .................................................................................. 20-14
Sub Oscillation Characteristics .................................................................................. 20-14
Main Oscillation Stabilization Time ............................................................................ 20-15
Sub Oscillation Stabilization Time ............................................................................. 20-15

22-1
22-2

Descriptions of Pins Used to Read/Write the Flash ROM ......................................... 22-4
Reference Table for Connection................................................................................ 22-6

23-1
23-2

Components of TB833B/834B ................................................................................... 23-4
Setting of the Jumper in TB833B/834B ..................................................................... 23-4

xx

S3F833B/F834B MICROCONTROLLER

List of Programming Tips
Description
Chapter 2:

Page
Number
Address Spaces

Using the Page Pointer for RAM clear (Page 0, Page1) ..........................................................................2-7
Setting the Register Pointers ....................................................................................................................2-11
Using the RPs to Calculate the Sum of a Series of Registers..................................................................2-12
Addressing the Common Working Register Area.....................................................................................2-16
Standard Stack Operations Using PUSH and POP..................................................................................2-21
Chapter 5:

Interrupt Structure

How to clear an interrupt pending bit ........................................................................................................5-15
Chapter 7:

Clock Circuit

Switching the CPU Clock ..........................................................................................................................7-6
How to Switch the System Clock ..............................................................................................................7-9

S3F833B/F834B MICROCONTROLLER

xxi

List of Register Descriptions
Register
Identifier
ADCON
BTCON
CLKCON
FLAGS
IFMOD
IMR
INTPND
IPH
IPL
IPR
IRQ
LCON
LMOD
OSCCON
OSCPLLR
P0CONH
P0CONL
P0PUR
P1CONH
P1CONL
P1INT
P1PND
P2CONH
P2CONL
P3CONH
P3CONL
P3PUR
P9CONH
P10CONH
P10CONL
PG0CON
PG1CON

Full Register Name

Page
Number

A/D Converter Control Register ................................................................................. 4-7
Basic Timer Control Register ..................................................................................... 4-8
System Clock Control Register .................................................................................. 4-9
System Flags Register ............................................................................................... 4-10
IF Counter Mode Register.......................................................................................... 4-11
Interrupt Mask Register .............................................................................................. 4-12
Interrupt Pending Register ......................................................................................... 4-13
Instruction Pointer (High Byte) ................................................................................... 4-14
Instruction Pointer (Low Byte) .................................................................................... 4-14
Interrupt Priority Register ........................................................................................... 4-15
Interrupt Request Register ......................................................................................... 4-16
LCD Control Register ................................................................................................. 4-17
LCD Mode Control Register ....................................................................................... 4-18
Oscillator Control Register ......................................................................................... 4-19
OSC PLL Control Register ......................................................................................... 4-20
Port 0 Control Register (High Byte)............................................................................ 4-21
Port 0 Control Register (Low Byte) ............................................................................ 4-22
Port 0 Pull-up Control Register .................................................................................. 4-23
Port 1 Control Register (High Byte)............................................................................ 4-24
Port 1 Control Register (Low Byte) ............................................................................ 4-25
Port 1 Interrupt Control Register ................................................................................ 4-26
Port 1 Interrupt Pending Register............................................................................... 4-27
Port 2 Control Register (High Byte)............................................................................ 4-28
Port 2 Control Register (Low Byte) ............................................................................ 4-29
Port 3 Control Register (High Byte)............................................................................ 4-30
Port 3 Control Register (Low Byte) ............................................................................ 4-31
Port 3 Pull-up Control Register .................................................................................. 4-32
Port 9 Control Register (High Byte)............................................................................ 4-33
Port 10 Control Register (High Byte).......................................................................... 4-34
Port 10 Control Register (Low Byte) .......................................................................... 4-35
Port Group 0 Control Register.................................................................................... 4-36
Port Group 1 Control Register.................................................................................... 4-37

S3F833B/F834B MICROCONTROLLER

xxiii

List of Register Descriptions (Continued)
Register
Identifier
PG2CON
PLLMOD
PLLREF
PP
RP0
RP1
SIO0CON
SIO1CON
SPH
SPL
STPCON
SYM
T0CON
T1CON
T2CON
UART0CON
UART1CON
WTCON

xxiv

Full Register Name

Page
Number

Port Group 2 Control Register ....................................................................................4-38
PLL Mode Register .....................................................................................................4-39
PLL Reference Frequency Selection Register ...........................................................4-40
Register Page Pointer ................................................................................................4-42
Register Pointer 0 .......................................................................................................4-43
Register Pointer 1 .......................................................................................................4-43
SIO 0 Control Register ...............................................................................................4-44
SIO 1 Control Register ...............................................................................................4-45
Stack Pointer (High Byte) ...........................................................................................4-46
Stack Pointer (Low Byte) ............................................................................................4-46
Stop Control Register .................................................................................................4-47
System Mode Register ...............................................................................................4-48
Timer 0 Control Register ............................................................................................4-49
Timer 1 Control Register ............................................................................................4-50
Timer 2 Control Register ............................................................................................4-51
UART 0 Control Register............................................................................................4-52
UART 1 Control Register............................................................................................4-53
Watch Timer Control Register ....................................................................................4-54

S3F833B/F834B MICROCONTROLLER

List of Instruction Descriptions
Instruction
Mnemonic
ADC
ADD
AND
BAND
BCP
BITC
BITR
BITS
BOR
BTJRF
BTJRT
BXOR
CALL
CCF
CLR
COM
CP
CPIJE
CPIJNE
DA
DEC
DECW
DI
DIV
DJNZ
EI
ENTER
EXIT
IDLE
INC
INCW
IRET
JP
JR
LD
LDB

Full Register Name

Page
Number

Add with Carry............................................................................................................ 6-14
Add ............................................................................................................................. 6-15
Logical AND ............................................................................................................... 6-16
Bit AND....................................................................................................................... 6-17
Bit Compare ............................................................................................................... 6-18
Bit Complement.......................................................................................................... 6-19
Bit Reset ..................................................................................................................... 6-20
Bit Set ......................................................................................................................... 6-21
Bit OR ......................................................................................................................... 6-22
Bit Test, Jump Relative on False ............................................................................... 6-23
Bit Test, Jump Relative on True................................................................................. 6-24
Bit XOR....................................................................................................................... 6-25
Call Procedure............................................................................................................ 6-26
Complement Carry Flag ............................................................................................. 6-27
Clear ........................................................................................................................... 6-28
Complement ............................................................................................................... 6-29
Compare..................................................................................................................... 6-30
Compare, Increment, and Jump on Equal ................................................................. 6-31
Compare, Increment, and Jump on Non-Equal ......................................................... 6-32
Decimal Adjust ........................................................................................................... 6-33
Decrement.................................................................................................................. 6-35
Decrement Word ........................................................................................................ 6-36
Disable Interrupts ....................................................................................................... 6-37
Divide (Unsigned)....................................................................................................... 6-38
Decrement and Jump if Non-Zero.............................................................................. 6-39
Enable Interrupts ........................................................................................................ 6-40
Enter ........................................................................................................................... 6-41
Exit.............................................................................................................................. 6-42
Idle Operation............................................................................................................. 6-43
Increment ................................................................................................................... 6-44
Increment Word.......................................................................................................... 6-45
Interrupt Return .......................................................................................................... 6-46
Jump........................................................................................................................... 6-47
Jump Relative............................................................................................................. 6-48
Load............................................................................................................................ 6-49
Load Bit ...................................................................................................................... 6-51

S3F833B/F834B MICROCONTROLLER

xxv

List of Instruction Descriptions (Continued)
Instruction
Mnemonic
LDC/LDE
LDCD/LDED
LDCI/LDEI
LDCPD/LDEPD
LDCPI/LDEPI
LDW
MULT
NEXT
NOP
OR
POP
POPUD
POPUI
PUSH
PUSHUD
PUSHUI
RCF
RET
RL
RLC
RR
RRC
SB0
SB1
SBC
SCF
SRA
SRP/SRP0/SRP1
STOP
SUB
SWAP
TCM
TM
WFI
XOR

xxvi

Full Register Name

Page
Number

Load Memory..............................................................................................................6-52
Load Memory and Decrement ....................................................................................6-54
Load Memory and Increment......................................................................................6-55
Load Memory with Pre-Decrement.............................................................................6-56
Load Memory with Pre-Increment ..............................................................................6-57
Load Word ..................................................................................................................6-58
Multiply (Unsigned) .....................................................................................................6-59
Next.............................................................................................................................6-60
No Operation ..............................................................................................................6-61
Logical OR ..................................................................................................................6-62
Pop from Stack ...........................................................................................................6-63
Pop User Stack (Decrementing).................................................................................6-64
Pop User Stack (Incrementing) ..................................................................................6-65
Push to Stack..............................................................................................................6-66
Push User Stack (Decrementing)...............................................................................6-67
Push User Stack (Incrementing) ................................................................................6-68
Reset Carry Flag.........................................................................................................6-69
Return .........................................................................................................................6-70
Rotate Left ..................................................................................................................6-71
Rotate Left through Carry ...........................................................................................6-72
Rotate Right................................................................................................................6-73
Rotate Right through Carry.........................................................................................6-74
Select Bank 0..............................................................................................................6-75
Select Bank 1..............................................................................................................6-76
Subtract with Carry .....................................................................................................6-77
Set Carry Flag.............................................................................................................6-78
Shift Right Arithmetic ..................................................................................................6-79
Set Register Pointer....................................................................................................6-80
Stop Operation............................................................................................................6-81
Subtract ......................................................................................................................6-82
Swap Nibbles..............................................................................................................6-83
Test Complement under Mask ...................................................................................6-84
Test under Mask .........................................................................................................6-85
Wait for Interrupt .........................................................................................................6-86
Logical Exclusive OR..................................................................................................6-87

S3F833B/F834B MICROCONTROLLER

S3F833B/F834B_UM_REV1.10

1

PRODUCT OVERVIEW

PRODUCT OVERVIEW

S3F8-SERIES MICROCONTROLLERS
Samsung's S3F8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range
of integrated peripherals, and various mask-programmable ROM sizes. Among the major CPU features are:
-- Efficient register-oriented architecture
-- Selectable CPU clock sources
-- Idle and Stop power-down mode release by interrupt
-- Built-in basic timer with watchdog function
A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum of four CPU clocks) can be assigned to
specific interrupt levels.

S3F833B/F834B MICROCONTROLLER
The S3F833B/F834B single-chip CMOS microcontroller are fabricated using the highly advanced CMOS process.
Its design is based on the powerful SAM88RC CPU core. Stop and idle (power-down) modes were implemented
to reduce power consumption.
The S3F833B, S3F834B are a microcontroller with a 64K-byte Flash ROM embedded.
Using a proven modular design approach, Samsung engineers have successfully developed the S3F833B/F834B
by integrating the following peripheral modules with the powerful SAM8 core:
-- Eleven programmable I/O ports, including nine 8bit ports, and two 7-bit ports, for a total of 86 pins.

-- A/D converter with 12 selectable input pins

-- Eight bit-programmable pins for external interrupt.

-- Two UART modules

-- One 8-bit basic timer for oscillation stabilization
and watchdog functions (system reset).

-- Low voltage reset

-- Two 8-bit timer/counter and one 16-bit
timer/counter with selectable operating modes.
-- Watch timer for real time.

-- Two synchronous SIO modules

-- OSC PLL frequency synthesizer
-- PLL frequency synthesizer
-- 20-bit intermediate frequency counter

-- LCD Controller/driver
The S3F833B/F834B is versatile microcontroller for Audio, LCD and ADC application, etc. They are currently
available in 100-pin QFP (S3F833B) and 100-pin TQFP (S3F834B) package.

1-1

PRODUCT OVERVIEW

S3F833B/F834B_UM_REV1.10

FEATURES
CPU

Analog to Digital Converter

o

o
o

SAM88 RC CPU core

Memory
o

64K × 8 bits program memory (ROM)

o

2.5K × 8 bits data memory (RAM)

12-channel analog input
10-bit conversion resolution

PLL Frequency Synthesizer
o

Level: 100mVp-p (min)
- AMVCO range:
0.5MHz to 5MHz or 5MHz to 30MHz
- FMVCO range: 30 MHz to 130 MHz

o

Level: 150mVp-p (min)

Instruction Set
o 78 instructions
o Idle and stop instructions
86 I/O Pins
o

77-bit I/O port (44 pins sharing LCD signals)

o

9-bit Input port

- FMVCO range: 30 MHz to 150 MHz
20-Bit Intermediate Frequency (IF) Counter
o

Level: 100mVp-p (min)

Interrupts

o

AMIF range: 100 kHz to 1 MHz

o

8 interrupt levels and 21 interrupt sources

o

FMIF range: 5 MHz to 15 MHz

o

Fast interrupt processing feature

LCD Controller/Driver

8-Bit Basic Timer

o

36 segments and 8 common terminals

o

Watchdog timer function

o

8, 4, 3, 2 common selectable

o

4 kinds of clock source

o

Internal or external resistor circuit for LCD bias

8-Bit Timer/Counter 0

Two 8- bit UART

o

Programmable 8-bit internal timer

o

Full-duplex serial I/O interface

o

External event counter function

o

Four programmable operating modes

o

PWM and capture function

Two 8-bit Serial I/O Interface

8-Bit Timer/Counter 1

o

8-bit transmit/receive mode

o

Programmable 8-bit internal timer

o

8-bit receive mode

o

External event counter function

o

LSB-first or MSB-first transmission selectable

o

Internal or External clock source

16-Bit Timer/Counter 2
o

Programmable 16-bit internal timer

Low Voltage Reset (LVR)

o

External event counter function

o

2-Creteria voltage selectable (2.3V, 2.6V)

o

En/Disable by smart option (ROM address: 3FH)

Watch Timer
o

Interval time: 50mS, 0.1S, 0.5S, and 1S

o

0.47/0.94/1.87/3.75 kHz Selectable buzzer output

1-2

S3F833B/F834B_UM_REV1.10

PRODUCT OVERVIEW

FEATURES (Continued)

Operating Temperature Range

Two Power-Down Modes

o

o

Idle: only CPU clock stops

Current Consumption

o

Stop: selected system clock and CPU clock stop

o

-40°C to +85°C

Stop Current (in LVR Disable Mode)
1uA(typ) at VDD = 3 V

Oscillation Sources
o

Crystal, ceramic or RC for main clock

Package Type

o

Main clock frequency: 0.4 MHz -12MHz

o

Instruction Execution Times
o

S3F833B: 100-QFP-1420C
S3F834B: 100-TQFP-1414

0.33 us at 12 MHz fx (minimum)

Operating Voltage Range
o

-25°C to +85°C at
2.0 V to 3.6 V at 0.4 - 4.2 MHz
2.7 V to 3.6 V at 0.4 - 12 MHz
2.0 V to 3.6 V at 75 kHz
2.7 V to 3.6 V in PLL/IFC Mode
2.7V to 3.6V at 4.5/7.2/9 MHz
(PLL OSC at 75 kHz)

o

-40°C to +85°C at
2.4 V to 3.6 V at 0.4 - 4.2 MHz
2.7 V to 3.6 V at 0.4 - 12 MHz
2.4V to 3.6V at 75 kHz
2.7 V to 3.6 V in PLL/IFC Mode
2.7V to 3.6V at 4.5/7.2/9 MHz
(PLL OSC at 75 kHz)

1-3

PRODUCT OVERVIEW

S3F833B/F834B_UM_REV1.10

BLOCK DIAGRAM

X IN
X OUT
X T IN
X TOUT

Main
OSC

Sub OSC

nRESET

INT0~INT7

CE
I/O Port 0

LPF

P0.0- P0.6

PLL OSC
I/O Port 1

I/O Port 4

SCK0
SO0
SI0
SCK1
SO1
SI1
Watch-dog
Timer
BUZ
COM0- 3
COM4-7/SEG0- 3
SEG4- 39
VLC0-3
VCOAM
VCOFM
EO
AMIF
FMIF
AD0- AD11
RXD0
TXD0

P5.0- P5.7

I/O Port 6

P6.0- P6.7

P7.0-P7.7

P8.0-P8.7

I/O Port 9

I/O Port and Interrupt
Control

SAM88 RC
Core

P9.0- P9.7

SIO 0

SIO1

64KB
ROM

2.5KB RAM

Basic Timer

Watch Timer
LCD
Driver/
Controller
PLL
Synthesizer
TEST
IF
Counter

10 - bit ADC

UART1

VSS
VSSPLL

LVR

UART0

VDD
VDDPLL 0
VDDPLL 1

TXD1
RXD1

Figure 1-1. Block Diagram

1-4

P4.0-P4.7

I/O Port 8

16-bit Timer/
Counter 2

P3.0-P3.6

I/O Port 7

T2CLK
T2OUT

P2.0- P2.7

I/O Port 3

8-bit Timer/
Counter 1

I/O Port 2

8-bit Timer/
Counter 0

T1CLK
T1OUT

P1.4-P1.7
P1.0-P1.3

I/O Port 5

T0CAP
T0CLK
T0OUT/T0PWM

I/O Port 10

P10.5- P10.7
P10.0- P10.4

S3F833B/F834B_UM_REV1.10

PRODUCT OVERVIEW

PIN ASSIGNMENT

VDDPLL0
CE
P10.5/RXD0
P10.6/TXD0
P10.7
P0.0/T0CLK/RXD1
P0.1/T0CAP/TXD1
P0.2/T0OUT/T0PWM
P0.3/T1CLK
P0.4/T1OUT
P0.5/T2CLK
P0.6/T2OUT
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT3
P1.4/AD8/INT4
P1.5/AD9/INT5
P1.6/AD10/INT6
P1.7/AD11/INT7
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4/AD4
P2.5/AD5
P2.6/AD6
P2.7/AD7
P3.0/BUZ
P3.1/SCK0
P3.2/SO0
P3.3/SI0
P3.4/SCK1
P3.5/SO1
VDD
VSS
XOUT
XIN
TEST
XTIN
XTOUT
nRESET
LPF
AVDD
P3.6/SI1
P4.0/SEG39
P4.1/SEG38
P4.2/SEG37
P4.3/SEG36
P4.4/SEG35

1
2
3
4
5
6
7
8
9
10
11
12
13 (SDAT)
14 (SCLK)
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

S3F833B
100-QFP 1420C

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

EO/P10.4
FMIF/P10.3
AMIF/P10.2
VSSPLL
VCOAM/P10.1
VCOFM/P10.0
VDDPLL1
VLC0/P9.7
VLC1/P9.6
VLC2/P9.5
VLC3/P9.4
COM0/P8.7
COM1/P8.6
COM2/P8.5
COM3/P8.4
COM4/SEG0/P8.3
COM5/SEG1/P8.2
COM6/SEG2/P8.1
COM7/SEG3/P8.0
SEG4/P9.3
SEG5/P9.2
SEG6/P9.1
SEG7/P9.0
SEG8/P7.7
SEG9/P7.6
SEG10/P7.5
SEG11/P7.4
SEG12/P7.3
SEG13/P7.2
SEG14/P7.1

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
SEG15/P7.0
SEG16/P6.7
SEG17/P6.6
SEG18/P6.5
SEG19/P6.4
SEG20/P6.3
SEG21/P6.2
SEG22/P6.1
SEG23/P6.0
SEG24/P5.7
SEG25/P5.6
SEG26/P5.5
SEG27/P5.4
SEG28/P5.3
SEG29/P5.2
SEG30/P5.1
SEG31/P5.0
SEG32/P4.7
SEG33/P4.6
SEG34/P4.5

Figure 1-2. S3F833B Pin Assignments (100-QFP-1420C)

1-5

PRODUCT OVERVIEW

S3F833B/F834B_UM_REV1.10

AMIF/P10.2
FMIF/P10.3
P10.4/EO
VDDPLL0
CE
P10.5/RXD0
P10.6/TXD0
P10.7
P0.0/T0CLK/RXD1
P0.1/T0CAP/TXD1
P0.2/T0OUT/T0PWM
P0.3/T1CLK
P0.4/T1OUT
P0.5/T2CLK
P0.6/T2OUT
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT3
P1.4/AD8/INT4
P1.5/AD9/INT5
P1.6/AD10/INT6
P1.7/AD11/INT7
P2.0/AD0
P2.1/AD1
76
77
78
79
70
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

P2.2/AD2
P2.3/AD3
P2.4/AD4
P2.5/AD5
P2.6/AD6
P2.7/AD7
P3.0/BUZ
P3.1/SCK0
P3.2/SO0
P3.3/SI0
P3.4/SCK1
P3.5/SO1
VDD
VSS
XOUT
XIN
TEST
XTIN
XTOUT
nRESET
LPF
AVDD
P3.6/SI1
P4.0/SEG39
P4.1/SEG38

1
2
3
4
5
6
7
8
9
10
11 (SDAT)
12 (SCLK)
13
14
15
16
17
18
19
20
21
22
23
24
25

S3F834B
100-TQFP 1414

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
SEG13/P7.2
SEG14/P7.1
SEG15/P7.0
SEG16/P6.7
SEG17/P6.6
SEG18/P6.5
SEG19/P6.4
SEG20/P6.3
SEG21/P6.2
SEG22/P6.1
SEG23/P6.0
SEG24/P5.7
SEG25/P5.6
SEG26/P5.5
SEG27/P5.4
SEG28/P5.3
SEG29/P5.2
SEG30/P5.1
SEG31/P5.0
SEG32/P4.7
SEG33/P4.6
SEG34/P4.5
SEG35/P4.4
SEG36/P4.3
SEG37/P4.2

Figure 1-3. S3F834B Pin Assignments (100-TQFP-1414)

1-6

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

VSSPLL
VCOAM/P10.1
VCOFM/P10.0
VDDPLL1
VLC0/P9.7
VLC1/P9.6
VLC2/P9.5
VLC3/P9.4
COM0/P8.7
COM1/P8.6
COM2/P8.5
COM3/P8.4
COM4/SEG0/P8.3
COM5/SEG1/P8.2
COM6/SEG2/P8.1
COM7/SEG3/P8.0
SEG4/P9.3
SEG5/P9.2
SEG6/P9.1
SEG7/P9.0
SEG8/P7.7
SEG9/P7.6
SEG10/P7.5
SEG11/P7.4
SEG12/P7.3

S3F833B/F834B_UM_REV1.10

PRODUCT OVERVIEW

PIN DESCRIPTIONS
Table 1-1. S3F833B/F834B Pin Descriptions
Pin
Names

Pin
Type

Pin
Description

Circuit
Type

Pin
Numbers

Share
Pins

I/O

I/O port with bit-programmable pins
Schmitt trigger input or push-pull, opendrain output and software assignable pullups.

E-4

86(84)

T0CLK/RXD1

87(85)

T0CAP/TXD1

88(86)

T0OUT/T0PWM

P0.3

89(87)

T1CLK

P0.4

90(88)

T1OUT

P0.5

91(89)

T2CLK

P0.6

92(90)

T2OUT

P0.0
P0.1
P0.2

P1.0 - P1.3

I/O

P1.4 - P1.7

I

I/O port with bit-programmable pins;
Schmitt trigger input or push-pull output
and software assignable pull-ups;
Alternately used for external interrupt
input(noise filters, interrupt enable and
pending control).

D-7

93(91) - 96(94)

INT0 - INT3

Bit-programmable input and software
assignable pull-ups.

D-9

97(95) - 100(98)

INT4 - INT7/
AD8-AD11

P2.0 - P2.7

I/O

I/O port with bit-programmable pins;
Schmitt trigger input or push-pull output
and software assignable pull-ups.

F-16

1(99) - 8(6)

AD0 - AD7

P3.0

I/O

I/O port with bit-programmable pins
Input or push-pull, open-drain output and
software assignable pull-ups.

E-2

9(7)

BUZ

10(8)

SCK0

P3.2

11(9)

SO0

P3.3

12(10)

SI0

P3.4

13(11)

SCK1

P3.5

14(12)

SO1

P3.6

25(23)

SI1

P3.1

P4.0 - P4.7

I/O

I/O port with bit-programmable pins
Input or push-pull, open-drain output and
software assignable pull-ups.

H-42

26(24) - 33(31) SEG39 - SEG32

P5.0 - P5.7

I/O

I/O port with bit-programmable pins
Input or push-pull, open-drain output and
software assignable pull-ups.

H-42

34(32) - 41(39) SEG31 - SEG24

P6.0 - P6.7

I/O

I/O port with nibble-programmable pins;
Schmitt trigger input or push-pull, opendrain output and software assignable pullups.

H-41

42(40) - 49(47) SEG23 - SEG16

NOTE: Parentheses indicate pin number for S3F834B.

1-7

PRODUCT OVERVIEW

S3F833B/F834B_UM_REV1.10

Table 1-1. S3F833B/F834B Pin Descriptions (Continued)
Pin
Names

Pin
Type

Pin
Description

Circuit
Type

Pin
Numbers

Share
Pins

P7.0 - P7.7

I/O

I/O port with nibble-programmable
pins;
Schmitt trigger input or push-pull,
open-drain output and software
assignable pull-ups.

H-41

50(48) - 57(55)

SEG15 - SEG8

P8.0 - P8.3

I/O

I/O port with 8-bit programmable pins;
Schmitt trigger input or push-pull,
open-drain output and software
assignable pull-ups.

H-41

62(60) - 65(63)

SEG3-SEG0/
COM7 - COM4

66(64) - 69(67)

COM3 - COM0

P8.4 - P8.7
P9.0 - P9.3

I/O

I/O port with nibble-programmable
pins;
Schmitt trigger input or push-pull,
open-drain output and software
assignable pull-ups.

H-41

58(56) - 61(59)

SEG7 - SEG4

P9.4 - P9.7

I/O

I/O port with nibble-programmable
pins;
Input or push-pull output and software
assignable pull-ups.

F-17

70(68)
71(69)
72(70)
73(71)

VLC3
VLC2
VLC1
VLC0

P10.0 - P10.3

I

Bit-programmable input and software
assignable pull-ups.

F-18

75(73)
76(74)
78(76)
79(77)

VCOFM
VCOAM
AMIF
FMIF

P10.4

I

Bit-programmable input and software
assignable pull-ups.

D-5

80(78)

EO

P10.5 - P10.7

I/O

I/O port with bit-programmable pins
Input or push-pull and software
assignable pull-ups.

D-6

83(81)
84(82)
85(83)

RXD0
TXD0
-

COM0 - COM3

I/O

Common signal output for LCD display

H-41

69(67) - 66(64)

P8.7 - P8.4

65(63) - 62(60)

P8.3 - P8.0/
SEG0 - SEG3

65(63) - 62(60)

P8.3 - P8.0/
COM4 - COM7

61(59) - 58(56)

P9.3 - P9.0

COM4 - COM7
SEG0 - SEG3

I/O

LCD segment signal output.

H-41

SEG4 - SEG7
SEG8 - SEG23

I/O

LCD segment signal output.

H-41

57(55) - 42(40)

P7 - P6

SEG24 - SEG39

I/O

LCD segment signal output.

H-42

41(39) -26(24)

P5 - P4

NOTE: Parentheses indicate pin number for S3F834B.

1-8

S3F833B/F834B_UM_REV1.10

PRODUCT OVERVIEW

Table 1-1. S3F833B/F834B Pin Descriptions (Continued)
Pin
Names
VLC0-VLC3

Pin
Type
I/O

Pin
Description
LCD power supply, Voltage dividing
resistors are assignable by software

Circuit
Type

Pin
Numbers

Share
Pins

F-17

70(68) - 73(71)

P9.4 - P9.7

VDD

-

Main power supply

-

15(13)

-

VSS

-

Main Ground

-

16(14)

-

VDDPLL0
VDDPLL1

-

PLL/IFC power supply

-

81(79)
74(72)

-

VSSPLL

-

PLL/IFC ground

-

77(75)

-

AVDD

-

A/D converter power supply

-

24(22)

-

LPF

-

Loop filter pump output for OSC PLL

-

23(21)

-

Xout, Xin

-

Main oscillator pins for CPU oscillation

-

17(15), 18(16)

-

XTout, XTin

-

Sub oscillator pins for CPU oscillation

-

21(19), 20(18)

-

TEST

I

Test signal input pin
(Must be connected to Vss for normal
operation)

-

19(17)

-

nRESET

I

System reset pin

B

22(20)

-

CE

I

Input pin for checking device power.
Normal operation is high level and
PLL/IFC
Operation is stopped at low level.

B-5

82(80)

-

EO

I/O

PLL's phase error output

D-5

80(78)

P10.4

VCOAM
VCOFM

I

External VCOAM/ VCOFM signal
inputs

F-18

76(74), 75(73)

P10.1
P10.0

FMIF,
AMIF

I

FM/AM intermediate frequency signal
inputs.

F-18

79(77)
78(76)

P10.3
P10.2

ADC input pins

F-16

1(99)-8(6)

P2.0 - P2.7

D-9

97(95) - 100(98)

P1.4 -P1.7/
INT4 - INT7

AD0-AD7

I/O

AD8-AD11

I

BUZ

I/O

Buzzer signal output

E-2

9(7)

P3.0

RXD0

I/O

UART data input

D-6

83(81)

P10.5

RXD1

I/O

E-4

86(84)

P0.0

TXD0

I/O

D-6

84(82)

P10.6

TXD1

I/O

E-4

87(85)

P0.1

UART data output

NOTE: Parentheses indicate pin number for S3F834B.

1-9

PRODUCT OVERVIEW

S3F833B/F834B_UM_REV1.10

Table 1-1. S3F833B/F834B Pin Descriptions (Continued)
Pin
Names

Pin
Type

Pin
Description

Circuit
Type

Pin
Numbers

Share
Pins

SCK0

I/O

SIO0 interface signal

E-2

10(8)

P3.1

SO0

I/O

SIO0 interface data input signal

E-2

11(9)

P3.2

SI0

I/O

SIO0 interface data output signal

E-2

12(10)

P3.3

SCK1

I/O

SIO1 interface signal

E-2

13(11)

P3.4

SO1

I/O

SIO1 interface data input signal

E-2

14(12)

P3.5

SI1

I/O

SIO1 interface data output signal

E-2

25(23)

P3.6

T0CLK

I/O

Timer 0 clock input

E-4

86(84)

P0.0

T0CAP

I/O

Timer 0 capture input

E-4

87(85)

P0.1

T0OUT

I/O

Timer 0 clock output

E-4

88(86)

P0.2

T0PWM

I/O

Timer 0 PWM output

E-4

88(86)

P0.2

T1CLK

I/O

Timer 1 clock input

E-4

89(87)

P0.3

T1OUT

I/O

Timer 1 clock output

E-4

90(88)

P0.4

T2CLK

I/O

Timer 2 clock input

E-4

91(89)

P0.5

T2OUT

I/O

Timer 2 clock output

E-4

92(90)

P0.6

INT0-INT3

I/O

External interrupt input pins

D-7

93-96(91-94)

P1.0-P1.3

INT4-INT7

I

External interrupt input pins

D-9

97-100(95-98)

P1.4-P1.7/
AD8-AD11

NOTE: Parentheses indicate pin number for S3F834B.

1-10

S3F833B/F834B_UM_REV1.10

PRODUCT OVERVIEW

PIN CIRCUITS
VDD

VDD
Pull-Up
Resistor

P-Channel
In

In

N-Channel

Schmitt Trigger

Figure 1-7. Pin Circuit Type B (nRESET)

Figure 1-4. Pin Circuit Type A

VDD

In

P-Channel

Data

Out
N-Channel

Output
Disable

Figure 1-5. Pin Circuit Type B-5 (CE)

Figure 1-8. Pin Circuit Type C

VDD

Pull-up Enable
Alternative Disable

VDD

VDD

Pull-up
Enable

P-Channel

Up
Input
Down
Alternative Disable

Figure 1-6. Pin Circuit Type D-5 (P10.4)

Data
Output
Disable

Circuit
Type C

I/O

Figure 1-9. Pin Circuit Type D-6 (P10.5-P10.7)

1-11

PRODUCT OVERVIEW

S3F833B/F834B_UM_REV1.10

VDD
VDD

Pull-up
Enable

Pull-Up
Resistor
Pull-up
Enable

P-Channel
Input

ADCEN

OpenDrain EN

VDD

ADC Select

Data
TO
ADC

I/O

Output
Disable
Port Enable
(PG2CON.5)

Data

Vss

Figure 1-10. Pin Circuit Type D-9 (P1.4-P1.7)

Figure 1-12. Pin Circuit Type E-2 (P3)

VDD

VDD
Pull-Up
Resistor

Pull-up
Enable

Pull-Up
Enable

P-Channel
Open-Drain
EN

Data
Output
Disable

Circuit
Type C

VDD

I/O
Data

I/O

Output
Disable

Port Enable
(PG2CON.4)

VSS

Schmitt Trigger

Figure 1-11. Pin Circuit Type D-7 (P1.0-P1.3)

1-12

Figure 1-13. Pin Circuit Type E-4 (P0)

S3F833B/F834B_UM_REV1.10

PRODUCT OVERVIEW

VDD

VDD
Pull-up
Enable
Data
Output
Disable

Circuit
Type C

I/O

Pull-up
Enable
VCO
Enable
Data

ADCEN

Input

ADC Select
Data

Feedback
Enable

Type A

TO ADC

Figure 1-14. Pin Circuit Type F-16 (P2)

Figure 1-16. Pin Circuit Type F-18 (P10.0-P10.3)

VDD

VLC0
Pull-up
Enable
Data
Output
Disable

VLC1/2

Circuit
Type C

I/O
VLCx

VLC
Select

COM/
SEG
Output
Disable

Out

VLC2/3
Data

To LCD
Block

Figure 1-15. Pin Circuit Type F-17 (P9.4-P9.7)

Figure 1-17. Pin Circuit Type H-39

1-13

PRODUCT OVERVIEW

S3F833B/F834B_UM_REV1.10

VDD
Pull-up
Resistor

VDD

Resistor
Enable

Open
Drain

P-CH

Data

I/O

Output
Disable1
SEG
Output
Disable2

N-CH

Circuit
Type H-39

Figure 1-18. Pin Circuit Type H-41 (P6-P8, P9.0-P9.3)

VDD

VDD

Pull-up
Resistor
Resistor
Enable

Open
Drain

P-CH

Data

I/O

Output
Disable1
SEG
Output
Disable2

N-CH

Circuit
Type H-39

Figure 1-19. Pin Circuit Type H-42 (P4, P5)

1-14

S3F833B/F834B_UM_REV1.10

2

ADDRESS SPACES

ADDRESS SPACES

OVERVIEW
The S3F833B/F834B microcontroller has two types of address space:
-- Internal program memory (ROM)
-- Internal register file
A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and
data between the CPU and the register file.
The S3F833B/F834B has an internal 64-Kbyte Flash ROM.
The 256-byte physical register space is expanded into an addressable area of 320 bytes using addressing
modes.
A 40-byte LCD display register file is implemented.
There are 2,654 mapped registers in the internal register file. Of these, 2,568 are for general-purpose.
(This number includes a 16-byte working register common area used as a "scratch area" for data operations, 8byte peripheral control register, 40-byte LCD data register, ten 192-byte prime register areas, and ten 64-byte
areas (set2)). Thirteen 8-bit registers are used for the CPU and the system control, and 66 registers are mapped
for peripheral controls and data registers. Ten register locations are not mapped.

2-1

ADDRESS SPACES

S3F833B/F834B_UM_REV1.10

PROGRAM MEMORY (ROM)
Program memory (ROM) stores program codes or table data. The S3F833B/S3F834B has 64K bytes internal
Flash program memory.
The first 256 bytes of the ROM (0H-0FFH) are reserved for interrupt vector addresses. Unused locations in this
address range can be used as normal program memory. If you use the vector address area to store a program
code, be careful not to overwrite the vector addresses stored in these locations.
The ROM address at which a program execution starts after a reset is 0100H.

65,535

FFFFH

64- KByte
Internal
Program
Memory Area

255

Interrupt
Vector Area
Smart Option

0

FFH
3FH
3CH

0H

Figure 2-1. Program Memory Address Space

2-2

S3F833B/F834B_UM_REV1.10

ADDRESS SPACES

SMART OPTION
ROM Address: 003FH
MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Not used
LVR Criteria Voltage:
000 = 2.6V
110 = 2.3V

LVR enable/disable bit:
0 = Disable LVR
1 = Enable LVR

ROM Address: 003EH
MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

.1

.0

LSB

.1

.0

LSB

Not used
ROM Address: 003CH
MSB

.7

.6

.5

.4

.3

.2

Not used
ROM Address: 003DH
MSB

.7

.6

.5

.4

.3

.2

Not used

Figure 2-2. Smart Option
Smart option is the ROM option for start condition of the chip. The ROM address used by smart option is from
003DH to 003FH. The S3F833B/F834B only use 003FH. The default value of ROM is FFH (LVR disable).

2-3

ADDRESS SPACES

S3F833B/F834B_UM_REV1.10

REGISTER ARCHITECTURE
In the S3F833B/F834B implementation, the upper 64-byte area of register files is expanded two 64-byte areas,
called set 1 and set 2. The upper 32-byte area of set 1 is further expanded two 32-byte register banks (bank 0
and bank 1), and the lower 32-byte area is a single 32-byte common area.
In case of S3F833B/F834B the total number of addressable 8-bit registers is 2,654. Of these 2,654 registers, 13
bytes are for CPU and system control registers, 73 bytes are for peripheral control and data registers, 16 bytes
are used as a shared working registers, and 2,552 registers are for general-purpose use, page 0-page 9
(including 40 bytes for LCD data registers and 8 bytes for peripheral control registers).
You can always address set 1 register locations, regardless of which of the ten register pages is currently
selected. Set 1 locations, however, can only be addressed using register addressing modes.
The extension of register space into separately addressable areas (sets, banks, and pages) is supported by
various addressing mode restrictions, the select bank instructions, SB0 and SB1, and the register page pointer
(PP).
Specific register types and the area (in bytes) that they occupy in the register file are summarized in Table 2-1.
Table 2-1. S3F833B/F834B Register Type Summary
Register Type
General-purpose registers (including the 16-byte
common working register area, ten 192-byte prime
register area (including LCD data registers and
peripheral control registers), and ten 64-byte set 2 area)
CPU and system control registers
Mapped clock, peripheral, I/O control, and data registers

2,568

Total Addressable Bytes

2-4

Number of Bytes

2,654

13
73

S3F833B/F834B_UM_REV1.10

ADDRESS SPACES

Total 10 Pages
FFH

SET 1
FFH
FFH
32
Bytes

PAGE 9

FFH
BANK 1

FFH

PAGE 1

FFH

BANK
0

PAGE 0

System and
Peripheral
Control Registers

DATA REGISTERS
(
SET 2
DATA REGISTERS

(Register Addressing Mode)

INDEXED, OR

64
Bytes

Registers
ADDRESSING

E0H

(Indirect Register,
ONLY)
Indexed Mode, and
Stack Oeration

DFH

System Registers

(Register Addressing Mode)
D0H
CFH

Working Registers
(Working Registers
Addressing Only)

40
Bytes

BFH

PAGE 0

PAGE 9

~

Prime
Data Registers
(All Addressing Mode)
LCD Display register

~
(

192
Bytes

00H
07H

8
Bytes

PAGE 2

C0H

C0H
27H

256
BYTES

PAGE 3

~

ADDRESSING
Prime STACK
INDEXED, OR
REGISTER,
ONLY)
Data ADDRESSING
Registers
STACK
(All Addressing Mode)
ONLY)

~

~

~

~

PAGE 0

~

Peripheral Control
Registers
(All Addressing Mode)

~
00H

00H

Figure 2-3. Internal Register File Organization

2-5

ADDRESS SPACES

S3F833B/F834B_UM_REV1.10

REGISTER PAGE POINTER (PP)
The S3F8-series architecture supports the logical expansion of the physical 256-byte internal register file (using
an 8-bit data bus) into as many as 16 separately addressable register pages. Page addressing is controlled by
the register page pointer (PP, DFH). In the S3F833B/S3F834B microcontroller, a paged register file expansion is
implemented for LCD data registers, and the register page pointer must be changed to address other pages.
After a reset, the page pointer's source value (lower nibble) and the destination value (upper nibble) are always
" 0000 " , automatically selecting page 0 as the source and destination page for register addressing.

Register Page Pointer (PP)
DFH ,Set 1, R/W
MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Destination register page selection bits:

Source register page selection bits:

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Others

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Others

Destination: Page 0
Destination: Page 1
Destination: Page 2
Destination: Page 3
Destination: Page 4
Destination: Page 5
Destination: Page 6
Destination: Page 7
Destination: Page 8
Destination: Page 9
Not used for the S3F833B/F834B

NOTE:

Source: page 0
Source: page 1
Source: page 2
Source: page 3
Source: page 4
Source: page 5
Source: page 6
Source: page 7
Source: page 8
Source: page 9
Not used for the S3F833B/F834B

A hardware reset operation writes the 4-bit destination and
source values shown above to the register page pointer. These values should
be modified to address other pages.

Figure 2-4. Register Page Pointer (PP)

2-6

S3F833B/F834B_UM_REV1.10

ADDRESS SPACES

PROGRAMMING TIP -- Using the Page Pointer for RAM clear (Page 0, Page 1)

RAMCL0

RAMCL1

LD
SRP
LD
CLR
DJNZ
CLR

PP,#00H
#0C0H
R0,#0FFH
@R0
R0,RAMCL0
@R0

LD
LD
CLR
DJNZ
CLR

PP,#10H
R0,#0FFH
@R0
R0,RAMCL1
@R0

; Destination

<-

0, Source

<-

0

<-

0

; Page 0 RAM clear starts

; R0 = 00H
; Destination <- 1, Source
; Page 1 RAM clear starts

; R0 = 00H

NOTE: You should refer to page 6-39 and use DJNZ instruction properly when DJNZ instruction is used in your program.

2-7

ADDRESS SPACES

S3F833B/F834B_UM_REV1.10

REGISTER SET 1
The term set 1 refers to the upper 64 bytes of the register file, locations C0H-FFH.
The upper 32-byte area of this 64-byte space (E0H-FFH) is expanded two 32-byte register banks, bank 0 and
bank 1. The set register bank instructions, SB0 or SB1, are used to address one bank or the other. A hardware
reset operation always selects bank 0 addressing.
The upper two 32-byte areas (bank 0 and bank 1) of set 1 (E0H-FFH) contains 67mapped system and peripheral
control registers. The lower 32-byte area contains 13 system registers (D0H-DFH) and a 16-byte common
working register area (C0H-CFH). You can use the common working register area as a "scratch" area for data
operations being performed in other areas of the register file.
Registers in set 1 locations are directly accessible at all times using Register addressing mode. The 16-byte
working register area can only be accessed using working register addressing (For more information about
working register addressing, please refer to Chapter 3, "Addressing Modes.")
REGISTER SET 2
The same 64-byte physical space that is used for set 1 locations C0H-FFH is logically duplicated to add another
64 bytes of register space. This expanded area of the register file is called set 2.
For the S3F833B/S3F834B, the set 2 address range (C0H-FFH) is accessible on pages 0-9.
The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions. You can use only
Register addressing mode to access set 1 locations. In order to access registers in set 2, you must use Register
Indirect addressing mode or Indexed addressing mode.
The set 2 register area of page 0 is commonly used for stack operations.

2-8

S3F833B/F834B_UM_REV1.10

ADDRESS SPACES

PRIME REGISTER SPACE
The lower 192 bytes (00H-BFH) of the S3F833B/S3F834B's ten 256-byte register pages are called prime register
area. Prime registers can be accessed using any of the seven addressing modes
(see Chapter 3, &quot; Addressing Modes. &quot; )
The prime register area on page 0 is immediately addressable following a reset. In order to address prime
registers on pages 0, 1, 2, 3, 4, 5, 6, 7, 8, or 9 you must set the register page pointer (PP) to the appropriate
source and destination values.

Set 1
Bank 0

Bank 1

FFH
Page 9
FFH
Page 8
FFH
Page 7
FFH
Page 6
FFH
Page 5
FFH
Page 4
FFH
Page 3
FFH
Page 2
FFH
Page 1
FFH
Page 0

FFH
Set 2

FCH
E0H

27H

D0H

C0H
BFH

C0H

Page 9

Page 0

LCD Data
Register Area
Prime
Space

CPU and system control
General-purpose
Peripheral and I/O

08H
07H
Peripheral
control
Register Area

LCD data register
Peripheral control register

00H

00H

Figure 2-5. Set 1, Set 2, Prime Area Register, and LCD Data Register Map

2-9

ADDRESS SPACES

S3F833B/F834B_UM_REV1.10

WORKING REGISTERS
Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields.
When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as one
that consists of 32 8-byte register groups or &quot; slices. &quot; Each slice comprises of eight 8-bit registers.
Using the two 8-bit register pointers, RP1 and RP0, two working register slices can be selected at any one time to
form a 16-byte working register block. Using the register pointers, you can move this 16-byte register block
anywhere in the addressable register file, except the set 2 area.
The terms slice and block are used in this manual to help you visualize the size and relative locations of selected
working register spaces:
-- One working register slice is 8 bytes (eight 8-bit working registers, R0-R7 or R8-R15)
-- One working register block is 16 bytes (sixteen 8-bit working registers, R0-R15)
All the registers in an 8-byte working register slice have the same binary value for their five most significant
address bits. This makes it possible for each register pointer to point to one of the 24 slices in the register file.
The base addresses for the two selected 8-byte register slices are contained in register pointers RP0 and RP1.
After a reset, RP0 and RP1 always point to the 16-byte common area in set 1 (C0H-CFH).

FFH
F8H
F7H
F0H

Slice 32
Slice 31

11111XXX

Set 1
Only

RP1 (Registers R8-R15)
Each register pointer points to
one 8-byte slice of the register
space, selecting a total 16-byte
working register block.

CFH
C0H

~

~

00000XXX
RP0 (Registers R0-R7)

Slice 2
Slice 1

Figure 2-6. 8-Byte Working Register Areas (Slices)

2-10

10H
FH
8H
7H
0H

S3F833B/F834B_UM_REV1.10

ADDRESS SPACES

USING THE REGISTER POINTS
Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable
8-byte working register slices in the register file. After a reset, they point to the working register common area:
RP0 points to addresses C0H-C7H, and RP1 points to addresses C8H-CFH.
To change a register pointer value, you load a new value to RP0 and/or RP1 using an SRP or LD instruction.
(see Figures 2-7 and 2-8).
With working register addressing, you can only access those two 8-bit slices of the register file that are currently
pointed to by RP0 and RP1. You cannot, however, use the register pointers to select a working register space in
set 2, C0H-FFH, because these locations can be accessed only using the Indirect Register or Indexed
addressing modes.
The selected 16-byte working register block usually consists of two contiguous 8-byte slices. As a general
programming guideline, it is recommended that RP0 point to the &quot; lower &quot; slice and RP1 point to the &quot; upper &quot; slice
(see Figure 2-7). In some cases, it may be necessary to define working register areas in different (noncontiguous) areas of the register file. In Figure 2-8, RP0 points to the &quot; upper &quot; slice and RP1 to the &quot; lower &quot; slice.
Because a register pointer can point to either of the two 8-byte slices in the working register block, you can
flexibly define the working register area to support program requirements.

PROGRAMMING TIP -- Setting the Register Pointers
SRP
SRP1
SRP0
CLR
LD

#70H
#48H
#0A0H
RP0
RP1,#0F8H

;
;
;
;
;

RP0
RP0
RP0
RP0
RP0

<-
<-
<-
<-
<-

70H, RP1 <- 78H
no change, RP1 <- 48H
A0H, RP1 <- no change
00H, RP1 <- no change
no change, RP1 <- 0F8H

Register File
Contains 32
8-Byte Slices
00001XXX
8-Byte Slice

RP1
00000XXX

8-Byte Slice

FH (R15)
8H
7H
0H (R0)

16-Byte
Contiguous
Working
Register block

RP0

Figure 2-7. Contiguous 16-Byte Working Register Block

2-11

ADDRESS SPACES

S3F833B/F834B_UM_REV1.10

8-Byte Slice

F7H (R7)
F0H (R0)

11110

XXX

XXX

8-Byte Slice

16-Byte
Contiguous
working
Register block

Register File
Contains 32
8-Byte Slices

RP0
00000

7H (R15)
0H (R0)

RP1

Figure 2-8. Non-Contiguous 16-Byte Working Register Block

PROGRAMMING TIP -- Using the RPs to Calculate the Sum of a Series of Registers
Calculate the sum of registers 80H-85H using the register pointer. The register addresses from 80H through 85H
contain the values 10H, 11H, 12H, 13H, 14H, and 15H, respectively:
SRP0
ADD
ADC
ADC
ADC
ADC

#80H
R0,R1
R0,R2
R0,R3
R0,R4
R0,R5

;
;
;
;
;
;

RP0
R0
R0
R0
R0
R0

<-
<-
<-
<-
<-
<-

80H
R0 +
R0 +
R0 +
R0 +
R0 +

R1
R2 + C
R3 + C
R4 + C
R5 + C

The sum of these six registers, 6FH, is located in the register R0 (80H). The instruction string used in this
example takes 12 bytes of instruction code and its execution time is 36 cycles. If the register pointer is not used to
calculate the sum of these registers, the following instruction sequence would have to be used:
ADD
ADC
ADC
ADC
ADC

80H,81H
80H,82H
80H,83H
80H,84H
80H,85H

;
;
;
;
;

80H
80H
80H
80H
80H

<-
<-
<-
<-
<-

(80H)
(80H)
(80H)
(80H)
(80H)

+
+
+
+
+

(81H)
(82H)
(83H)
(84H)
(85H)

+
+
+
+

C
C
C
C

Now, the sum of the six registers is also located in register 80H. However, this instruction string takes 15 bytes of
instruction code rather than 12 bytes, and its execution time is 50 cycles rather than 36 cycles.

2-12

S3F833B/F834B_UM_REV1.10

ADDRESS SPACES

REGISTER ADDRESSING
The S3F8-series register architecture provides an efficient method of working register addressing that takes full
advantage of shorter instruction formats to reduce execution time.
With Register (R) addressing mode, in which the operand value is the content of a specific register or register
pair, you can access any location in the register file except for set 2. With working register addressing, you use a
register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that
space.
Registers are addressed either as a single 8-bit register or as a paired 16-bit register space. In a 16-bit register
pair, the address of the first 8-bit register is always an even number and the address of the next register is always
an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register, and
the least significant byte is always stored in the next (+1) odd-numbered register.
Working register addressing differs from Register addressing as it uses a register pointer to identify a specific
8-byte working register space in the internal register file and a specific 8-bit register within that space.

MSB

LSB

Rn

Rn+1

n = Even address

Figure 2-9. 16-Bit Register Pair

2-13

ADDRESS SPACES

S3F833B/F834B_UM_REV1.10

Special-Purpose Registers
Bank 1

General-Purpose Register

Bank 0

FFH

FFH
Control
Registers

E0H

Set 2

System
Registers

D0H

CFH
C0H

C0H
BFH
RP1
Register
Pointers
RP0
Each register pointer (RP) can independently point
to one of the 24 8-byte &quot; slices &quot; of the register file
(other than set 2). After a reset, RP0 points to
locations C0H-C7H and RP1 to locations C8H-CFH
(that is, to the common working register area).
NOTE:

Prime
Registers

LCD Data
Registers

In the S3F833B/F834B
microcontroller, pages 0-9 are implemented.
Pages 0-9 contain all of the addressable
registers in the internal register file.

00H

Page 0
Register Addressing Only

Can be Pointed by Register Pointer

All
Indirect Register,
All
Addressing
Indexed
Addressing
Modes
Addressing
Modes
Modes
Can be Pointed to
By register Pointer

Figure 2-10. Register File Addressing

2-14

Page 0

S3F833B/F834B_UM_REV1.10

ADDRESS SPACES

COMMON WORKING REGISTER AREA (C0H-CFH)
After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations
C0H-CFH, as the active 16-byte working register block:
RP0

->

C0H-C7H

RP1

->

C8H-CFH

This 16-byte address range is called common area. That is, locations in this area can be used as working
registers by operations that address any location on any page in the register file. Typically, these working
registers serve as temporary buffers for data operations between different pages.

FFH

FFH
Page 9
FFH
Page 8
FFH
Page 7
FFH
Page 6
FFH
Page 5
FFH
Page 4
FFH
Page 3
FFH
Page 2
FFH
Page 1
FFH
Page 0

FCH

Set 2

Set 1

E0H
D0H

C0H
BFH

C0H

~
~ 27H
~

Page 9

~

Page 0
~

Following a hardware reset, register
pointers RP0 and RP1 point to the
common working register area,
locations C0H-CFH.

RP0 =

1100

0000

RP1 =

1100

1000

LCD Data
Register Area

~
~
~
Prime
Space
08H
07H
00H

~

00H

~

Peripheral
Control
Register area

Figure 2-11. Common Working Register Area

2-15

ADDRESS SPACES

S3F833B/F834B_UM_REV1.10

PROGRAMMING TIP -- Addressing the Common Working Register Area
As the following examples show, you should access working registers in the common area, locations C0H-CFH,
using working register addressing mode only.
Examples

1. LD

0C2H,40H

; Invalid addressing mode!

Use working register addressing instead:
SRP
#0C0H
LD
R2,40H
; R2 (C2H) ->
2. ADD

0C3H,#45H

the value in location 40H

; Invalid addressing mode!

Use working register addressing instead:
SRP
#0C0H
ADD
R3,#45H
; R3 (C3H) ->

R3 + 45H

4-BIT WORKING REGISTER ADDRESSING
Each register pointer defines a movable 8-byte slice of working register space. The address information stored in
a register pointer serves as an addressing &quot; window &quot; that makes it possible for instructions to access working
registers very efficiently using short 4-bit addresses. When an instruction addresses a location in the selected
working register area, the address bits are concatenated in the following way to form a complete 8-bit address:
-- The high-order bit of the 4-bit address selects one of the register pointers ( &quot; 0 &quot; selects RP0, &quot; 1 &quot; selects RP1).
-- The five high-order bits in the register pointer select an 8-byte slice of the register space.
-- The three low-order bits of the 4-bit address select one of the eight registers in the slice.
As shown in Figure 2-12, the result of this operation is that the five high-order bits from the register pointer are
concatenated with the three low-order bits from the instruction address to form the complete address. As long as
the address stored in the register pointer remains unchanged, the three bits from the address will always point to
an address in the same 8-byte register slice.
Figure 2-13 shows a typical example of 4-bit working register addressing. The high-order bit of the instruction
&quot; INC R6 &quot; is &quot; 0 &quot; , which selects RP0. The five high-order bits stored in RP0 (01110B) are concatenated with the
three low-order bits of the instruction's 4-bit address (110B) to produce the register address 76H (01110110B).

2-16

S3F833B/F834B_UM_REV1.10

ADDRESS SPACES

RP0
RP1
Selects
RP0 or RP1
Address

OPCODE

4-bit address
provides three
low-order bits

Register pointer
provides five
high-order bits

Together they create an
8-bit register address

Figure 2-12. 4-Bit Working Register Addressing

RP0
01110

RP1
000

01111

000

Selects RP0

01110

110

Register
address
(76H)

R6

OPCODE

0110

1110

Instruction
'INC R6'

Figure 2-13. 4-Bit Working Register Addressing Example

2-17

ADDRESS SPACES

S3F833B/F834B_UM_REV1.10

8-BIT WORKING REGISTER ADDRESSING
You can also use 8-bit working register addressing to access registers in a selected working register area. To
initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value
&quot; 1100B. &quot; This 4-bit value (1100B) indicates that the remaining four bits have the same effect as 4-bit working
register addressing.
As shown in Figure 2-14, the lower nibble of the 8-bit address is concatenated in much the same way as for 4-bit
addressing: Bit 3 selects either RP0 or RP1, which then supplies the five high-order bits of the final address; the
three low-order bits of the complete address are provided by the original instruction.
Figure 2-15 shows an example of 8-bit working register addressing. The four high-order bits of the instruction
address (1100B) specify 8-bit working register addressing. Bit 4 ( &quot; 1 &quot; ) selects RP1 and the five high-order bits in
RP1 (10101B) become the five high-order bits of the register address. The three low-order bits of the register
address (011) are provided by the three low-order bits of the 8-bit instruction address. The five address bits from
RP1 and the three address bits from the instruction are concatenated to form the complete register address,
0ABH (10101011B).

RP0
RP1
Selects
RP0 or RP1
Address
These address
bits indicate 8-bit
working register
addressing

1

1

0

0

8-bit logical
address

Three low-order bits

Register pointer
provides five
high-order bits

8-bit physical address

Figure 2-14. 8-Bit Working Register Addressing

2-18

S3F833B/F834B_UM_REV1.10

ADDRESS SPACES

RP1

RP0
01100

000

10101

000

10101

011

Selects RP1

R11
1100

1

011

8-bit address
form instruction
'LD R11, R2'

Register
address
(0ABH)

Specifies working
register addressing

Figure 2-15. 8-Bit Working Register Addressing Example

2-19

ADDRESS SPACES

S3F833B/F834B_UM_REV1.10

SYSTEM AND USER STACK
The S3F8-series microcontrollers use the system stack for data storage, subroutine calls and returns. The PUSH
and POP instructions are used to control system stack operations. The S3F833B/F834B architecture supports
stack operations in the internal register file.
Stack Operations
Return addresses for procedure calls, interrupts, and data are stored on the stack. The contents of the PC are
saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents
of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to
their original locations. The stack address value is always decreased by one before a push operation and
increased by one after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top
of the stack, as shown in Figure 2-16.

High Address

PCL
PCL
Top of
stack

PCH
PCH

Top of
stack

Stack contents
after a call
instruction

Flags
Stack contents
after an
interrupt

Low Address

Figure 2-16. Stack Operations
User-Defined Stacks
You can freely define stacks in the internal register file as data storage locations. The instructions PUSHUI,
PUSHUD, POPUI, and POPUD support user-defined stack operations.
Stack Pointers (SPL, SPH)
Register locations D8H and D9H contain the 16-bit stack pointer (SP) that is used for system stack operations.
The most significant byte of the SP address, SP15-SP8, is stored in the SPH register (D8H), and the least
significant byte, SP7-SP0, is stored in the SPL register (D9H). After a reset, the SP value is undetermined.
Because only internal memory space is implemented in the S3F833B/F834B, the SPL must be initialized to an 8bit value in the range 00H-FFH. The SPH register is not needed and can be used as a general-purpose register,
if necessary.
When the SPL register contains the only stack pointer value (that is, when it points to a system stack in the
register file), you can use the SPH register as a general-purpose data register. However, if an overflow or
underflow condition occurs as a result of increasing or decreasing the stack address value in the SPL register
during normal stack operations, the value in the SPL register will overflow (or underflow) to the SPH register,
overwriting any other data that is currently stored there. To avoid overwriting data in the SPH register, you can
initialize the SPL value to &quot; FFH &quot; instead of &quot; 00H &quot; .

2-20

S3F833B/F834B_UM_REV1.10

ADDRESS SPACES

PROGRAMMING TIP -- Standard Stack Operations Using PUSH and POP
The following example shows you how to perform stack operations in the internal register file using PUSH and
POP instructions:
LD

SPL,#0FFH

; SPL <- FFH
; (Normally, the SPL is set to 0FFH by the initialization
; routine)

PP
RP0
RP1
R3

;
;
;
;

Stack address 0FEH <- PP
Stack address 0FDH <- RP0
Stack address 0FCH <- RP1
Stack address 0FBH <- R3

R3
RP1
RP0
PP

;
;
;
;

R3
RP1
RP0
PP

o
o
o

PUSH
PUSH
PUSH
PUSH
o
o
o

POP
POP
POP
POP

<- Stack address 0FBH
<- Stack address 0FCH
<- Stack address 0FDH
<- Stack address 0FEH

2-21

ADDRESS SPACES

S3F833B/F834B_UM_REV1.10

NOTES

2-22

S3F833B/F834B_UM_REV1.10

3

ADDRESSING MODES

ADDRESSING MODES

OVERVIEW
Instructions that are stored in program memory are fetched for execution using the program counter. Instructions
indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to
determine the location of the data operand. The operands specified in SAM88RC instructions may be condition
codes, immediate data, or a location in the register file, program memory, or data memory.
The S3C8-series instruction set supports seven explicit addressing modes. Not all of these addressing modes are
available for each instruction. The seven addressing modes and their symbols are:
-- Register (R)
-- Indirect Register (IR)
-- Indexed (X)
-- Direct Address (DA)
-- Indirect Address (IA)
-- Relative Address (RA)
-- Immediate (IM)

3-1

ADDRESSING MODES

S3F833B/F834B_UM_REV1.10

REGISTER ADDRESSING MODE (R)
In Register addressing mode (R), the operand value is the content of a specified register or register pair
(see Figure 3-1).
Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8-byte
working register space in the register file and an 8-bit register within that space (see Figure 3-2).

Program Memory
8-bit Register
File Address

dst
OPCODE

One-Operand
Instruction
(Example)

Register File

OPERAND
Point to One
Register in Register
File
Value used in
Instruction Execution

Sample Instruction:
DEC

CNTR

;

Where CNTR is the label of an 8-bit register address

Figure 3-1. Register Addressing

Register File
MSB Point to
RP0 ot RP1

RP0 or RP1
Selected
RP points
to start
of working
register
block

Program Memory
4-bit
Working Register

dst

3 LSBs

src

Point to the
Working Register
(1 of 8)

OPCODE
Two-Operand
Instruction
(Example)

OPERAND

Sample Instruction:
ADD

R1, R2

;

Where R1 and R2 are registers in the currently
selected working register area.

Figure 3-2. Working Register Addressing

3-2

S3F833B/F834B_UM_REV1.10

ADDRESSING MODES

INDIRECT REGISTER ADDRESSING MODE (IR)
In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the
operand. Depending on the instruction used, the actual address may point to a register in the register file, to
program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6).
You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to
indirectly address another memory location. Please note, however, that you cannot access locations C0H-FFH in
set 1 using the Indirect Register addressing mode.

Program Memory
8-bit Register
File Address

dst
OPCODE

One-Operand
Instruction
(Example)

Register File

Point to One
Register in Register
File

ADDRESS

Address of Operand
used by Instruction

Value used in
Instruction Execution

OPERAND

Sample Instruction:
RL

@SHIFT

;

Where SHIFT is the label of an 8-bit register address

Figure 3-3. Indirect Register Addressing to Register File

3-3

ADDRESSING MODES

S3F833B/F834B_UM_REV1.10

INDIRECT REGISTER ADDRESSING MODE (Continued)

Register File

Program Memory
Example
Instruction
References
Program
Memory

dst
OPCODE

REGISTER
PAIR
Points to
Register Pair

Program Memory
Sample Instructions:
CALL
JP

@RR2
@RR2

Value used in
Instruction

OPERAND

Figure 3-4. Indirect Register Addressing to Program Memory

3-4

16-Bit
Address
Points to
Program
Memory

S3F833B/F834B_UM_REV1.10

ADDRESSING MODES

INDIRECT REGISTER ADDRESSING MODE (Continued)

Register File
MSB Points to
RP0 or RP1
RP0 or RP1

Program Memory
4-bit
Working
Register
Address

dst

src

OPCODE

~

~

3 LSBs
Point to the
Working Register
(1 of 8)

ADDRESS

~
Sample Instruction:
OR

R3, @R6

Value used in
Instruction

Selected
RP points
to start fo
working register
block

~
OPERAND

Figure 3-5. Indirect Working Register Addressing to Register File

3-5

ADDRESSING MODES

S3F833B/F834B_UM_REV1.10

INDIRECT REGISTER ADDRESSING MODE (Concluded)

Register File
MSB Points to
RP0 or RP1
RP0 or RP1
Selected
RP points
to start of
working
register
block

Program Memory
4-bit Working
Register Address

Example Instruction
References either
Program Memory or
Data Memory

dst
src
OPCODE

Next 2-bit Point
to Working
Register Pair
(1 of 4)
LSB Selects

Value used in
Instruction

Register
Pair

Program Memory
or
Data Memory

16-Bit
address
points to
program
memory
or data
memory

OPERAND

Sample Instructions:
LCD
LDE
LDE

R5,@RR6
R3,@RR14
@RR4, R8

; Program memory access
; External data memory access
; External data memory access

Figure 3-6. Indirect Working Register Addressing to Program or Data Memory

3-6

S3F833B/F834B_UM_REV1.10

ADDRESSING MODES

INDEXED ADDRESSING MODE (X)
Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to
calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access
locations in the internal register file or in external memory. Please note, however, that you cannot access
locations C0H-FFH in set 1 using Indexed addressing mode.
In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range
to +127. This applies to external memory accesses only (see Figure 3-8.)

-128

For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained
in a working register. For external memory accesses, the base address is stored in the working register pair
designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to that base address
(see Figure 3-9).
The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction
(LD). The LDC and LDE instructions support Indexed addressing mode for internal program memory and for
external data memory, when implemented.

Register File

RP0 or RP1

~
Value used in
Instruction

+
Program Memory
Two-Operand
Instruction
Example

Base Address
dst/src
x

3 LSBs
Point to One of the
Woking Register
(1 of 8)

OPCODE

~
Selected RP
points to
start of
working
register
block

OPERAND

~

~
INDEX

Sample Instruction:
LD

R0, #BASE[R1]

;

Where BASE is an 8-bit immediate value

Figure 3-7. Indexed Addressing to Register File

3-7

ADDRESSING MODES

S3F833B/F834B_UM_REV1.10

INDEXED ADDRESSING MODE (Continued)

Register File
MSB Points to
RP0 or RP1
RP0 or RP1

~

~

Program Memory
4-bit Working
Register Address

OFFSET
dst/src
x
OPCODE

Selected
RP points
to start of
working
register
block

NEXT 2 Bits
Point to Working
Register Pair
(1 of 4)

LSB Selects

+
8-Bits

Register
Pair

Program Memory
or
Data Memory

16-Bit
address
added to
offset

16-Bits

16-Bits

OPERAND

Value used in
Instruction

Sample Instructions:
LDC

R4, #04H[RR2]

LDE

R4,#04H[RR2]

; The values in the program address (RR2 + 04H)
are loaded into register R4.
; Identical operation to LDC example, except that
external program memory is accessed.

Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset

3-8

S3F833B/F834B_UM_REV1.10

ADDRESSING MODES

INDEXED ADDRESSING MODE (Concluded)

Register File
MSB Points to
RP0 or RP1
RP0 or RP1

Program Memory

~

~

OFFSET
4-bit Working
Register Address

OFFSET
src
dst/src
OPCODE

Selected
RP points
to start of
working
register
block

NEXT 2 Bits
Point to Working
Register Pair

LSB Selects

+
8-Bits

Register
Pair

Program Memory
or
Data Memory

16-Bit
address
added to
offset

16-Bits

16-Bits

OPERAND

Value used in
Instruction

Sample Instructions:
LDC

R4, #1000H[RR2]

LDE

R4,#1000H[RR2]

; The values in the program address (RR2 + 1000H)
are loaded into register R4.
; Identical operation to LDC example, except that
external program memory is accessed.

Figure 3-9. Indexed Addressing to Program or Data Memory

3-9

ADDRESSING MODES

S3F833B/F834B_UM_REV1.10

DIRECT ADDRESS MODE (DA)
In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call
(CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC
whenever a JP or CALL instruction is executed.
The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for
Load operations to program memory (LDC) or to external data memory (LDE), if implemented.

Program or
Data Memory

Program Memory

Upper Address Byte
Lower Address Byte
dst/src &quot; 0 &quot; or &quot; 1 &quot;
OPCODE

Memory
Address
Used

LSB Selects Program
Memory or Data Memory:
&quot; 0 &quot; = Program Memory
&quot; 1 &quot; = Data Memory

Sample Instructions:
LDC

R5,1234H

;

LDE

R5,1234H

;

The values in the program address (1234H)
are loaded into register R5.
Identical operation to LDC example, except that
external program memory is accessed.

Figure 3-10. Direct Addressing for Load Instructions

3-10

S3F833B/F834B_UM_REV1.10

ADDRESSING MODES

DIRECT ADDRESS MODE (Continued)

Program Memory

Next OPCODE

Memory
Address
Used
Upper Address Byte
Lower Address Byte
OPCODE

Sample Instructions:
JP
CALL

C,JOB1
DISPLAY

;
;

Where JOB1 is a 16-bit immediate address
Where DISPLAY is a 16-bit immediate address

Figure 3-11. Direct Addressing for Call and Jump Instructions

3-11

ADDRESSING MODES

S3F833B/F834B_UM_REV1.10

INDIRECT ADDRESS MODE (IA)
In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program
memory. The selected pair of memory locations contains the actual address of the next instruction to be executed.
Only the CALL instruction can use the Indirect Address mode.
Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program
memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are
assumed to be all zeros.

Program Memory

Next Instruction

LSB Must be Zero
Current
Instruction

dst
OPCODE

Lower Address Byte
Upper Address Byte

Program Memory
Locations 0-255

Sample Instruction:
CALL

#40H

; The 16-bit value in program memory addresses 40H
and 41H is the subroutine start address.

Figure 3-12. Indirect Addressing

3-12

S3F833B/F834B_UM_REV1.10

ADDRESSING MODES

RELATIVE ADDRESS MODE (RA)
In Relative Address (RA) mode, a twos-complement signed displacement between - 128 and + 127 is
specified in the instruction. The displacement value is then added to the current PC value. The result is the
address of the next instruction to be executed. Before this addition occurs, the PC contains the address of the
instruction immediately following the current instruction.
Several program control instructions use the Relative Address mode to perform conditional jumps. The
instructions that support RA addressing are BTJRF, BTJRT, DJNZ, CPIJE, CPIJNE, and JR.

Program Memory

Next OPCODE
Program Memory
Address Used

Displacement
OPCODE

Current Instruction

Current
PC Value

+

Signed
Displacement Value

Sample Instructions:
JR

ULT,$+OFFSET

;

Where OFFSET is a value in the range +127 to -128

Figure 3-13. Relative Addressing

3-13

ADDRESSING MODES

S3F833B/F834B_UM_REV1.10

IMMEDIATE MODE (IM)
In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand
field itself. The operand may be one byte or one word in length, depending on the instruction used. Immediate
addressing mode is useful for loading constant values into registers.

Program Memory
OPERAND
OPCODE

(The Operand value is in the instruction)
Sample Instruction:
LD

R0,#0AAH

Figure 3-14. Immediate Addressing

3-14

S3F833B/F834B_UM_REV1.10

4

CONTROL REGISTER

CONTROL REGISTERS

OVERVIEW
In this chapter, detailed descriptions of the S3F833B/F834B control registers are presented in an easy-to-read
format. You can use this chapter as a quick-reference source when writing application programs. Figure 4-1
illustrates the important features of the standard register description format.
Control register descriptions are arranged in alphabetical order according to register mnemonic. More detailed
information about control registers is presented in the context of the specific peripheral hardware descriptions in
Part II of this manual.
Data and counter registers are not described in detail in this reference chapter. More information about all of the
registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part II of this
manual.
The locations and read/write characteristics of all mapped registers in the S3F833B/F834B register file are listed
in Table 4-1. The hardware reset value for each mapped register is described in Chapter 8, &quot; RESET and PowerDown. &quot;

4-1

CONTROL REGISTERS

S3F833B/F834B_UM_REV1.10

Table 4-1. Set 1 Registers
Register Name

Mnemonic

Address

R/W

nRESET Value(bit)

Decimal

Hex

BTCON

211

D3H

R/W

00000000

CLKCON

212

D4H

R/W

0--00---

FLAGS

213

D5H

R/W

xxxxxx00

Register Pointer 0

RP0

214

D6H

R/W

11000---

Register Pointer 1

RP1

215

D7H

R/W

11001---

Stack Pointer (High Byte)

SPH

216

D8H

R/W

xxxxxxx

x

Stack Pointer (Low Byte)

SPL

217

D9H

R/W

xxxxxxx

x

Instruction Pointer (High Byte)

IPH

218

DAH

R/W

xxxxxxx

x

Instruction Pointer (Low Byte)

IPL

219

DBH

R/W

xxxxxxx

x

Interrupt Request Register

IRQ

220

DCH

R

Interrupt Mask Register

IMR

221

DDH

R/W

xxxxxxx

System Mode Register

SYM

222

DEH

R/W

0--xxx00

Register Page Pointer

PP

223

DFH

R/W

00000000

R/W

nRESET Value(bit)

Basic timer control register
System Clock Control Register
System Flags Register

76543210

00000000
x

Table 4-2. Page 0 Registers
Register Name

Mnemonic

Address
Decimal

UART 0 Control Register
UART 0 Data Register
UART 0 Baud Rate Data Register
UART 1 Control Register
UART 1 Data Register
UART 1 Baud Rate Data Register

Hex

UART0CON

0

00H

R/W

00000000

UDATA0

1

01H

R/W

xxxxxxx

BRDATA0

2

02H

R/W

11111111

UART1CON

3

03H

R/W

00000000

UDATA1

4

04H

R/W

xxxxxxx

BRDATA1

5

05H

R/W

11111111

Locations 06H-07H are not mapped.

4-2

76543210
x

x

S3F833B/F834B_UM_REV1.10

CONTROL REGISTER

Table 4-3. Set1, Bank 0 Registers
Register Name

Mnemonic

Address
Decimal

R/W

Hex

nRESET Value(bit)
76543210

Interrupt Pending Register

INTPND

208

D0H

R/W

--000000

STOP control register

STPCON

209

D1H

R/W

00000000

Oscillator control register

OSCCON

210

D2H

R/W

----00-0

Timer 0 Counter Register

T0CNT

224

E0H

R

00000000

Timer 0 Data Register

T0DATA

225

E1H

R/W

11111111

Timer 0 Control Register

T0CON

226

E2H

R/W

00000000

Timer 1 Counter Register

T1CNT

227

E3H

R

00000000

Timer 1 Data Register

T1DATA

228

E4H

R/W

11111111

Timer 1 Control Register

T1CON

229

E5H

R/W

000-0000

Watch Timer Control Register

WTCON

230

E6H

R/W

00000000

SIO 0 Control Register

SIO0CON

231

E7H

R/W

00000000

SIO 0 Data Register

SIO0DATA

232

E8H

R/W

00000000

SIO0PS

233

E9H

R/W

00000000

SIO 1 Control Register

SIO1CON

234

EAH

R/W

00000000

SIO 1 Data Register

SIO1DATA

235

EBH

R/W

00000000

SIO1PS

236

ECH

R/W

00000000

SIO 0 Pre-scaler Register

SIO 1 Pre-scaler Register

Locations EDH-EEH are not mapped.
LCD Control Register

LCON

239

EFH

R/W

0---0000

LCD Mode Control Register

LMOD

240

F0H

R/W

00000000

IF Counter 2

IFCNT2

241

F1H

R

00000000

IF Counter 1

IFCNT1

242

F2H

R

00000000

IF Counter 0

IFCNT0

243

F3H

R

00000000

PLL Data Register 1

PLLD1

244

F4H

R/W

xxxxxxx

x

PLL Data Register 0

PLLD0

245

F5H

R/W

xxxxxxx

x

IF Counter Mode Register

IFMOD

246

F6H

R/W

00-00000

PLL Mode Register

PLLMOD

247

F7H

(note)

(note)

PLL Reference Frequency Register

PLLREF

248

F8H

(note)

(note)

A/D Converter Control Register

ADCON

249

F9H

R/W

00000000

A/D Converter Data Register (High
Byte)

ADDATAH

250

FAH

R

xxxxxxx

x

A/D Converter Data Register (Low
Byte)

ADDATAL

251

FBH

R

------x

x

Location FCH is not mapped.

4-3

CONTROL REGISTERS

S3F833B/F834B_UM_REV1.10

Table 4-3. Set1, Bank 0 Registers (Continued)
Register Name

Mnemonic

Address
Decimal

Basic Timer Counter

BTCNT

Hex

253

FDH

R/W

nRESET Value(bit)
76543210

R

00000000

Location FEH is not mapped.
Interrupt Priority Register
NOTE:

4-4

IPR

Refer to the "System Control Register Chapter".

255

FFH

R/W

xxxxxxx

x

S3F833B/F834B_UM_REV1.10

CONTROL REGISTER

Table 4-4. Set1, Bank 1 Registers
Register Name

Mnemonic

Address
Decimal

R/W

Hex

nRESET Value(bit)
76

5

43210

Port 10 Control Register (High Byte)

P10CONH

208

D0H

R/W

00

0

00000

Port 10 Control Register (Low Byte)

P10CONL

209

D1H

R/W

00

0

00000

OSC PLL Control Register

OSCPLLR

210

D2H

R/W

00

0

00000

Port 0 Control Register (High Byte)

P0CONH

224

E0H

R/W

--

0

00000

Port 0 Control Register (Low Byte)

P0CONL

225

E1H

R/W

00

0

00000

Port 0 Pull-up Resistor Enable Register

P0PUR

226

E2H

R/W

-0

0

00000

Port 1 Interrupt pending Register

P1PND

227

E3H

R/W

00

0

00000

Port 1 Control Register (High Byte)

P1CONH

228

E4H

R/W

00

0

00000

Port 1 Control Register (Low Byte)

P1CONL

229

E5H

R/W

00

0

00000

P1INT

230

E6H

R/W

00

0

00000

Port 9 Control Register (High Byte)

P9CONH

231

E7H

R/W

00

0

00000

Port 2 Control Register (High Byte)

P2CONH

232

E8H

R/W

00

0

00000

Port 2 Control Register (Low Byte)

P2CONL

233

E9H

R/W

00

0

00000

Port 3 Control Register (High Byte)

P3CONH

234

EAH

R/W

--

0

00000

Port 3 Control Register (Low Byte)

P3CONL

235

EBH

R/W

00

0

00000

P3PUR

236

ECH

R/W

-0

0

00000

Port Group 0 Control Register

PG0CON

237

EDH

R/W

00

0

00000

Port Group 1 Control Register

PG1CON

238

EEH

R/W

00

0

00000

Port Group 2 Control Register

PG2CON

239

EFH

R/W

00

0

00000

Port 0 Data Register

P0

240

F0H

R/W

-0

0

00000

Port 1 Data Register

P1

241

F1H

R/W

00

0

00000

Port 2 Data Register

P2

242

F2H

R/W

00

0

00000

Port 3 Data Register

P3

243

F3H

R/W

-0

0

00000

Port 4 Data Register

P4

244

F4H

R/W

00

0

00000

Port 5 Data Register

P5

245

F5H

R/W

00

0

00000

Port 6 Data Register

P6

246

F6H

R/W

00

0

00000

Port 7 Data Register

P7

247

F7H

R/W

00

0

00000

Port 8 Data Register

P8

248

F8H

R/W

00

0

00000

Port 9 Data Register

P9

249

F9H

R/W

00

0

00000

Port 10 Data Register

P10

250

FAH

R/W

00

0

00000

Timer 2 Control Register

T2CON

251

FBH

R/W

00

0

-0000

Timer 2 Counter Register (High Byte)

T2CNTH

252

FCH

R

00

0

00000

Timer 2 Counter Register (Low Byte)

T2CNTL

253

FDH

R

00

0

00000

Timer 2 Data Register (High Byte)

T2DATAH

254

FEH

R/W

11

1

11111

Timer 2 Data Register (Low Byte)

T2DATAL

255

FFH

R/W

11

1

11111

Port 1 Interrupt Control Register

Port 3 Pull-up Resistor Enable Register

4-5

CONTROL REGISTERS

S3F833B/F834B_UM_REV1.10

Bit number(s) that is/are appended to
the register name for bit addressing
Register ID

Name of individual
bit or related bits

Register location
in the internal
register file

Register address
(hexadecimal)

Full Register name

FLAGS - System Flags Register

D5H

Set 1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

Reset Value

x

x

x

x

x

x

x

0

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Bit Addressing

Register addressing mode only

Mode
.7

Carry Flag (C)
0

.6

Operation does not generate a carry or borrow condition

1

Operation generates carry-out or borrow into high-order bit 7

Zero Flag (Z)
0

Operation result is a non-zero value

1

Operation result is zero

.5
Sign Flag (S)
0

Operation generates positive number (MSB = &quot; 0 &quot; )

1

Operation generates negative number (MSB = &quot; 1 &quot; )

R = Read-only
W = Write-only
R/W = Read/write
'-' = Not used

Description of the
effect of specific
bit settings

Type of addressing
that must be used to
address the bit
(1-bit, 4-bit, or 8-bit)

nRESET value notation:
'-' = Not used
'x' = Undetermined value
'0' = Logic zero
'1' = Logic one

Figure 4-1. Register Description Format

4-6

Bit number:
MSB = Bit 7
LSB = Bit 0

S3F833B/F834B_UM_REV1.10

CONTROL REGISTER

ADCON -- A/D Converter Control Register

F9H

Set 1, Bank0

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7-.4

A/D Converter Input Selection Bits
0

0

0

AD0 (P2.0)

0

0

0

1

AD1 (P2.1)

0

0

1

0

AD2 (P2.2)

0

0

1

1

AD3 (P2.3)

0

1

0

0

AD4 (P2.4)

0

1

0

1

AD5 (P2.5)

0

1

1

0

AD6 (P2.6)

0

1

1

1

AD7 (P2.7)

1

0

0

0

AD8 (P1.4)

1

0

0

1

AD9 (P1.5)

1

0

1

0

AD10 (P1.6)

1
.3

0

0

1

1

AD11 (P1.7)

End-of-Conversion Bit (Read-only)
0
1

.2-.1

Conversion not complete
Conversion complete

A/D Converter Clock Source Selection Bits
0

fxx/16

0

1

fxx/8

1

0

fxx/4

1
.0

0

1

fxx/1

A/D Converter Start or Enable Bit
0

Disable operation

1

Start operation

4-7

CONTROL REGISTERS

S3F833B/F834B_UM_REV1.10

BTCON -- Basic Timer Control Register

D3H

Set 1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7-.4

Watchdog Timer Function Disable Code (for System Reset)
1

0

1

0

Others
.3-.2

Enable watchdog timer function

Basic Timer Input Clock Selection Bits (3)
0

0

fxx/4096

0

1

fxx/1024

1

0

fxx/128

1
.1

Disable watchdog timer function

1

fxx/16

Basic Timer Counter Clear Bit (1)
0
1

.0

No effect
Clear the basic timer counter value

Clock Frequency Divider Clear Bit for Basic Timer and Timer/Counters (2)
0

No effect

1

Clear both clock frequency dividers

NOTES:
1. When you write a "1" to BTCON.1, the basic timer counter value is cleared to &quot; 00H &quot; . Immediately following the write
operation, the BTCON.1 value is automatically cleared to "0".
2. When you write a &quot; 1 &quot; to BTCON.0, the corresponding frequency divider is cleared to &quot; 00H &quot; . Immediately following the
write operation, the BTCON.0 value is automatically cleared to &quot; 0 &quot; .
3. The fxx is selected clock for system (main OSC. or sub OSC.).

4-8

S3F833B/F834B_UM_REV1.10

CONTROL REGISTER

CLKCON -- System Clock Control Register

D4H

Set 1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

0

-

-

0

0

-

-

-

R/W

-

-

R/W

R/W

-

-

-

Read/Write
Addressing Mode

Register addressing mode only

.7

Oscillator IRQ Wake-up Function Bit
0

Enable IRQ for main wake-up in power down mode

1

Disable IRQ for main wake-up in power down mode

.6-.5

Not used for the S3F833B/F834B (must keep always "0")

.4-.3

CPU Clock (System Clock) Selection Bits (note)
0

1

fxx/8

1

0

fxx/2

1

NOTE:

fxx/16

0

.2-.0

0

1

fxx/1

Not used for the S3F833B/F834B (must keep always "0")
After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load
the appropriate values to CLKCON.3 and CLKCON.4.

4-9

CONTROL REGISTERS

S3F833B/F834B_UM_REV1.10

FLAGS -- System Flags Register

D5H

Set 1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

x

x

x

x

x

x

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7

Carry Flag (C)
0
1

.6

Operation does not generate a carry or borrow condition
Operation generates a carry-out or borrow into high-order bit 7

Zero Flag (Z)
0
1

.5

Operation result is a non-zero value
Operation result is zero

Sign Flag (S)
0
1

.4

Operation generates a positive number (MSB = &quot; 0 &quot; )
Operation generates a negative number (MSB = &quot; 1 &quot; )

Overflow Flag (V)
0
1

.3

Operation result is <= +127 or >= -128
Operation result is &amp; gt; +127 or &amp; lt; -128

Decimal Adjust Flag (D)
0
1

.2

Add operation completed
Subtraction operation completed

Half-Carry Flag (H)
0
1

.1

No carry-out of bit 3 or no borrow into bit 3 by addition or subtraction
Addition generated carry-out of bit 3 or subtraction generated borrow into bit 3

Fast Interrupt Status Flag (FIS)
0
1

.0

Interrupt return (IRET) in progress (when read)
Fast interrupt service routine in progress (when read)

Bank Address Selection Flag (BA)
0
1

4-10

Bank 0 is selected
Bank 1 is selected

S3F833B/F834B_UM_REV1.10

CONTROL REGISTER

IFMOD -- IF Counter Mode Register

F6H

Set 1, Bank0

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

0

0

-

0

0

0

0

0

R/W

R/W

-

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7-.6

System Clock Control Bit for Frequency Synthesizer, IF Counter, Watch Timer
0

0

The supplied clocks are not dived. (fxx = 4.5MHz)

0

1

The supplied clocks are dived by 2. (fxx = 9MHz)

1

0

The supplied clocks are dived by 5/8. (fxx = 7.2MHz)

1

1

Not available

NOTES:

1. If the main clock is 9MHz, IFMOD.7-.6 should be set to "01".
2. If the main clock is 7.2MHz, IFMOD.7-.6 should be set to "10".

.5

Not used for the S3F833B/F834B

.4

PLL/IFC Reference Frequency Source Selection Bit
0
1

.3-.2

Select fxx (4.5MHz, 7.2MHz, 9.0MHz)
Select fxt (75kHz)

IF Counter Mode Selection Bits
0

IFC is disabled; FMIF/AMIF are FMIF/AMIF's feed-back resistor are off.

0

1

Enable IFC operation; AMIF pin is selected; FMIF is FMIF's feed-back
resistor are off.

1

0

Enable IFC operation; FMIF pin is selected; AMIF is AMIF's feed-back
resistor are off.

1
.1-.0

0

1

Enable IFC operation; both AMIF and FMIF are selcted.

Gate Time Selection Bits (fxx = 4.5/7.2/9.0MHz or fxt = 75KHz)
0

0

Gate opens in 2-millisecond intervals

0

1

Gate opens in 8-millisecond intervals

1

0

Gate opens in 16-millisecond intervals

1

1

Gate remains opens continuously

4-11

CONTROL REGISTERS

S3F833B/F834B_UM_REV1.10

IMR -- Interrupt Mask Register

DDH

Set 1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

x

x

x

x

x

x

x

x

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

R/W
Register addressing mode only

.7

Interrupt Level 7 (IRQ7) Enable Bit; IF Interrupt
0
1

Disable (mask)
Enable (unmask)

.6

Interrupt Level 6 (IRQ6) Enable Bit; CE Interrupt
0 Disable (mask)
1 Enable (unmask)

.5

Interrupt Level 5 (IRQ5) Enable Bit; P1.4 - P1.7 Interrupt
0 Disable (mask)
1 Enable (unmask)

.4

Interrupt Level 4 (IRQ4) Enable Bit; P1.0 - P1.3 Interrupt
0 Disable (mask)
1 Enable (unmask)

.3

Interrupt Level 3 (IRQ3) Enable Bit;
UART0/1 Transmit, UART0/1 Receive, Watch Timer Interrupt
0 Disable (mask)
1 Enable (unmask)

.2

Interrupt Level 2 (IRQ2) Enable Bit; SIO0, SIO1 Interrupt
0 Disable (mask)
1 Enable (unmask)

.1

Interrupt Level 1 (IRQ1) Enable Bit; Timer 1, Timer 2 Match Interrupt
0 Disable (mask)
1 Enable (unmask)

.0

Interrupt Level 0 (IRQ0) Enable Bit; Timer 0 Match/Capture, Timer 0 Overflow
0 Disable (mask)
1 Enable (unmask)

NOTE:

4-12

When an interrupt level is masked, any interrupt requests that may be issued are not recognized by the CPU.

S3F833B/F834B_UM_REV1.10

CONTROL REGISTER

INTPND -- Interrupt Pending Register

D0H

Set 1, Bank0

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

-

-

0

0

0

0

0

0

Read/Write

-

-

R/W

R/W

R/W

R/W

R/W

R/W

Addressing Mode

Register addressing mode only

.7-.6

Not used for the S3F833B/F834B

.5

Rx Interrupt Pending Bit (for UART1)
0
1

.4

Interrupt request is not pending (when read); pending bit clear (when write 0)
Interrupt request is pending (when read)

Tx Interrupt Pending Bit (for UART1)
0
1

.3

Interrupt request is not pending (when read); pending bit clear (when write 0)
Interrupt request is pending (when read)

Rx Interrupt Pending Bit (for UART0)
0
1

.2

Interrupt request is not pending (when read); pending bit clear (when write 0)
Interrupt request is pending (when read)

Tx Interrupt Pending Bit (for UART0)
0
1

.1

Interrupt request is not pending (when read); pending bit clear (when write 0)
Interrupt request is pending (when read)

Timer 0 Match/Capture Interrupt Pending Bit
0
1

.0

Interrupt request is not pending (when read); pending bit clear (when write 0)
Interrupt request is pending (when read)

Timer 0 Overflow Interrupt Pending Bit
0

Interrupt request is not pending (when read); pending bit clear (when write 0)

1

Interrupt request is pending (when read)

4-13

CONTROL REGISTERS

S3F833B/F834B_UM_REV1.10

IPH -- Instruction Pointer (High Byte)

DAH

Set 1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

x

x

x

x

x

x

x

x

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7-.0

Instruction Pointer Address (High Byte)
The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction
pointer address (IP15-IP8). The lower byte of the IP address is located in the IPL
register (DBH).

IPL -- Instruction Pointer (Low Byte)

DBH

Set 1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

x

x

x

x

x

x

x

x

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7-.0

Instruction Pointer Address (Low Byte)
The low-byte instruction pointer value is the lower eight bits of the 16-bit instruction
pointer address (IP7-IP0). The upper byte of the IP address is located in the IPH
register (DAH).

4-14

S3F833B/F834B_UM_REV1.10

CONTROL REGISTER

IPR -- Interrupt Priority Register
Bit Identifier

.7

FFH

.6

.5

Set 1, Bank0

.4

.3

.2

.1

.0

x
R/W

x
R/W

x
R/W

x
R/W

x
R/W

RESET Value
Read/Write
Addressing Mode

x
x
x
R/W
R/W
R/W
Register addressing mode only

.7, .4, and .1

Priority Control Bits for Interrupt Groups A, B, and C
0

0

Group priority undefined

0

0

1

B

&amp; gt;

C

&amp; gt;

A

0

1

0

A

&amp; gt;

B

&amp; gt;

C

0

1

1

B

&amp; gt;

A

&amp; gt;

C

1

0

0

C

&amp; gt;

A

&amp; gt;

B

1

0

1

C

&amp; gt;

B

&amp; gt;

A

1

1

0

A

&amp; gt;

C

&amp; gt;

B

1
.6

0

1

1

Group priority undefined

Interrupt Subgroup C Priority Control Bit
0

&amp; gt;

IRQ7

1
.5

IRQ6
IRQ7

&amp; gt;

IRQ6

Interrupt Group C Priority Control Bit
0
1

.3

IRQ5

&amp; gt;

(IRQ6, IRQ7)

(IRQ6, IRQ7)

IRQ3

&amp; gt; IRQ4

1

IRQ4

&amp; gt; IRQ3

Interrupt Group B Priority Control Bit
0

IRQ2

1
.0

&amp; gt;

(IRQ3, IRQ4)

(IRQ3, IRQ4)

&amp; gt;

IRQ2

Interrupt Group A Priority Control Bit
0

IRQ0

&amp; gt;

IRQ1

1
NOTE:

IRQ5

Interrupt Subgroup B Priority Control Bit
0

.2

&amp; gt;

IRQ1

&amp; gt;

IRQ0

Interrupt group A -IRQ0, IRQ1
Interrupt group B -IRQ2, IRQ3, IRQ4
Interrupt group C -IRQ5, IRQ6, IRQ7

4-15

CONTROL REGISTERS

S3F833B/F834B_UM_REV1.10

IRQ -- Interrupt Request Register

DCH

Set 1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

0

0

0

0

0

0

0

0

Read/Write

R

R

R

R

R

R

R

R

Addressing Mode

Register addressing mode only

.7

Level 7 (IRQ7) Request Pending Bit; IF Interrupt
0
1

.6

Not pending
Pending

Level 6 (IRQ6) Request Pending Bit; CE Interrupt
0
1

.5

Not pending
Pending

Level 5 (IRQ5) Request Pending Bit; P1.4-P1.7 Interrupt
0
1

.4

Not pending
Pending

Level 4 (IRQ4) Request Pending Bit; P1.0-P1.3 Interrupt
0
1

.3

Not pending
Pending

Level 3 (IRQ3) Request Pending Bit; UART0/1 Transmit, UART0/1 Receive,
Watch Timer Interrupt
0
1

.2

Not pending
Pending

Level 2 (IRQ2) Request Pending Bit; SIO0, SIO1 Interrupt
0
1

.1

Not pending
Pending

Level 1 (IRQ1) Request Pending Bit; Timer 1, Timer 2 Match Interrupt
0
1

.0

Not pending
Pending

Level 0 (IRQ0) Request Pending Bit; Timer 0 Match/Capture, Timer 0 Overflow
0
1

4-16

Not pending
Pending

S3F833B/F834B_UM_REV1.10

CONTROL REGISTER

LCON -- LCD Control Register

EFH

Set 1, Bank0

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

0

-

-

-

0

0

0

0

R/W

-

-

-

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7

LCD Output Control Bit
0

LCD output is low and current to dividing resistors is cut off

1

If LMOD.3 = "0", LCD Display is turned off
If LMOD.3 = "1", output COM and SEG signals in display mode

.6-.4

Not used for the S3F833B/F834B

.3-.0

LCD Port Selection Bit
0

0

0

0

Select LCD COM0-3, COM4-7/SEG0-3, SEG4-39

0

0

0

1

Select LCD COM0-3, COM4-7/SEG0-3, SEG4-35.
P4.0-4.3 is I/O port.

0

0

1

0

Select LCD COM0-3, COM4-7/SEG0-3, SEG4-31.
P4 is I/O port.

0

0

1

1

Select LCD COM0-3, COM4-7/SEG0-3, SEG4-27.
P4 and P5.0-5.3 are I/O port.

0

1

0

0

Select LCD COM0-3, COM4-7/SEG0-3, SEG4-23.
P4 and P5 are I/O port.

0

1

0

1

Select LCD COM0-3, COM4-7/SEG0-3, SEG4-19.
P4, P5 and P6.0-6.3 are I/O port.

0

1

1

0

Select LCD COM0-3, COM4-7/SEG0-3, SEG4-15.
P4, P5 and P6 are I/O port

0

1

1

1

Select LCD COM0-3, COM4-7/SEG0-3, SEG4-11.
P4. P5, P6 and P7.0-7.3 are I/O port

1

0

0

0

Select LCD COM0-3, COM4-7/SEG0-3, SEG4-7.
P4. P5, P6 and P7 are I/O port

1

0

0

1

Select LCD COM0-3, COM4-7/SEG0-3.
P4. P5, P6, P7 and P9.0-9.3 as I/O port

1

0

1

0

All I/O port (P4, P5, P6, P7, P8, P9.0-P9.3)

4-17

CONTROL REGISTERS

S3F833B/F834B_UM_REV1.10

LMOD -- LCD Mode Control Register

F0H

Set 1, Bank0

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7

COM Signal Enable/Disable Bit
0
1

.6

Enable COM signal
Disable COM signal

LCD Voltage Dividing Resistor Control Bit
0
0

.5 -.4

Internal voltage dividing resistor
External voltage dividing resistor; Internal voltage dividing resistors are off

LCD Clock (LCDCK) Frequency Selection Bits (fw=75KHz)
0

234Hz

0

1

469Hz

1

0

938Hz

1
.3-.0

0

1

1875 Hz

LCD Duty and Bias Selection Bits
0

x

X

LCD display off (COM and SEG output low)

1

0

0

0

1/8duty, 1/4bias, COM0-COM7

1

0

0

1

1/4duty, 1/3bias, COM0-COM3, SEG0-SEG3

1

0

1

0

1/3duty, 1/3bias, COM0-COM2, SEG0-SEG3,
P8.4 can't be used normal I/O pin.

1

0

1

1

1/3duty, 1/2bias, COM0-COM2, SEG0-SEG3,
P8.4 can't be used normal I/O pin.

1

4-18

x

1

0

0

1/2duty, 1/2bias, COM0-COM1, SEG0-SEG3,
P8.4, P8.5 can't be used normal I/O pins.

S3F833B/F834B_UM_REV1.10

CONTROL REGISTER

OSCCON -- Oscillator Control Register

D2H

Set 1, Bank0

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

-

-

-

-

0

0

-

0

Read/Write

-

-

-

-

R/W

R/W

-

R/W

Addressing Mode

Register addressing mode only

.7-.4

Not used for the S3F833B/F834B

.3

Main Oscillator Control Bit
0
1

.2

Main oscillator RUN
Main oscillator STOP

Sub Oscillator Control Bit
0

Sub oscillator RUN

1

Sub oscillator STOP

.1

Not used for the S3F833B/F834B

.0

System Clock Selection Bit
0

Select main oscillator for system clock

1

Select sub oscillator for system clock

4-19

CONTROL REGISTERS

S3F833B/F834B_UM_REV1.10

OSCPLLR -- OSC PLL Control Register

D2H

Set 1, Bank1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7-.2

OSC PLL Setting Bits
0

0

0

0

0

Reset initial value

0

0

0

0

0

1

PLL OSC setting (4.5MHz)

0

0

0

0

1

0

PLL OSC setting (7.2MHz)

0
.1

0

0

0

0

1

1

PLL OSC setting (9MHz)

System Clock Selection Bit
0

Select sub OSC for system clock

1

Select OSC PLL clock (fout) for system clock

NOTE:

.0

When the sub oscillator is selected as system clock (OSCCON.0="1")

OSC PLL Operation Enable Bit
0

Disable OSC PLL

1

Enable OSC PLL

NOTE:

Phase comparator, filter and VCO activated

NOTES:
1. Where fout is the OSC PLL clock.
2. When the sub oscillator is selected as system clock / OSCCON.0 = 1
3. How to switch the system clock.
Main OSC -> Sub OSC -> Main OSC -> OSC PLL -> Main OSC
(It is impossible to switch between Sub OSC and OSC PLL)

4-20

S3F833B/F834B_UM_REV1.10

CONTROL REGISTER

P0CONH -- Port 0 Control Register (High Byte)

E0H

Set 1, Bank 1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

-

-

0

0

0

0

0

0

Read/Write

-

-

R/W

R/W

R/W

R/W

R/W

R/W

Addressing Mode

Register addressing mode only

.7-.6

Not used for the S3F833B/F834B

.5-.4

P0.6/T2OUT
0

Schmitt trigger input mode

0

1

Open-drain output mode

1

0

Alternative function (T2OUT)

1
.3-.2

0

1

Push-pull output mode

P0.5/T2CLK
0

Schmitt trigger input mode (T2CLK)

0

1

Open-drain output mode

1

0

Not available

1
.1-.0

0

1

Push-pull output mode

P0.4/T1OUT
0

0

Schmitt trigger input mode

0

1

Open-drain output mode

1

0

Alternative function (T1OUT)

1

1

Push-pull output mode

4-21

CONTROL REGISTERS

S3F833B/F834B_UM_REV1.10

P0CONL -- Port 0 Control Register (Low Byte)

E1H

Set 1, Bank 1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7-.6

P0.3/T1CLK
0

Schmitt trigger input mode (T1CLK)

0

1

Open-drain output mode

1

0

Not available

1
.5-.4

0

1

Push-pull output mode

P0.2/T0OUT/T0PWM
0

Schmitt trigger input mode

0

1

Open-drain output mode

1

0

Alternative function (T0OUT, T0PWM)

1
.3-.2

0

1

Push-pull output mode

P0.1/T0CAP/TXD1
0

Schmitt trigger input mode (T0CAP)

0

1

Open-drain output mode

1

0

Alternative function (TXD1)

1
.1-.0

0

1

Push-pull output mode

P0.0/T0CLK/RXD1
0

Schmitt trigger input mode (T0CLK/RXD1)

0

1

Open-drain output mode

1

0

Alternative function (RXD1 out)

1

4-22

0

1

Push-pull output mode

S3F833B/F834B_UM_REV1.10

CONTROL REGISTER

P0PUR -- Port 0 Pull-up Control Register

E2H

Set 1, Bank1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

-

0

0

0

0

0

0

0

Read/Write

-

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Addressing Mode

Register addressing mode only

.7

Not used for the S3F833B/F834B

.6

P0.6's Pull-up Resistor Enable Bit
0
1

.5

Disable pull-up resistor
Enable pull-up resistor

P0.5's Pull-up Resistor Enable Bit
0
1

.4

Disable pull-up resistor
Enable pull-up resistor

P0.4's Pull-up Resistor Enable Bit
0
1

.3

Disable pull-up resistor
Enable pull-up resistor

P0.3's Pull-up Resistor Enable Bit
0
1

.2

Disable pull-up resistor
Enable pull-up resistor

P0.2's Pull-up Resistor Enable Bit
0
1

.1

Disable pull-up resistor
Enable pull-up resistor

P0.1's Pull-up Resistor Enable Bit
0
1

.0

Disable pull-up resistor
Enable pull-up resistor

P0.0's Pull-up Resistor Enable Bit
0
1

NOTE:

Disable pull-up resistor
Enable pull-up resistor

A pull-up resistor of port 3 is automatically disabled only when the corresponding pin is selected as push-pull output
or alternative function

4-23

CONTROL REGISTERS

S3F833B/F834B_UM_REV1.10

P1CONH -- Port 1 Control Register (High Byte)

E4H

Set 1, Bank1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7-.6

P1.7/INT7/AD11
0

Input mode, pull-up, interrupt on falling edge

0

1

Input mode, interrupt on rising edge

1

0

Input mode, interrupt on rising or falling edge

1
.5-.4

0

1

Alternative function (AD11)

P1.6/INT6/AD10
0

Input mode, pull-up, interrupt on falling edge

0

1

Input mode, interrupt on rising edge

1

0

Input mode, interrupt on rising or falling edge

1
.3-.2

0

1

Alternative function (AD10)

P1.5/INT5/AD9
0

Input mode, pull-up, interrupt on falling edge

0

1

Input mode, interrupt on rising edge

1

0

Input mode, interrupt on rising or falling edge

1
.1-.0

0

1

Alternative function (AD9)

P1.4/ INT4/AD8
0

Input mode, pull-up, interrupt on falling edge

0

1

Input mode, interrupt on rising edge

1

0

Input mode, interrupt on rising or falling edge

1

4-24

0

1

Alternative function (AD8)

S3F833B/F834B_UM_REV1.10

CONTROL REGISTER

P1CONL -- Port 1 Control Register (Low Byte)

E5H

Set 1, Bank1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7-.6

P1.3/INT3
0

Schmitt trigger input mode, pull-up, interrupt on falling edge

0

1

Schmitt trigger input mode, interrupt on rising edge

1

0

Schmitt trigger input mode, interrupt on rising or falling edge

1
.5-.4

0

1

Push-pull output mode

P1.2/INT2
0

Schmitt trigger input mode, pull-up, interrupt on falling edge

0

1

Schmitt trigger input mode, interrupt on rising edge

1

0

Schmitt trigger input mode, interrupt on rising or falling edge

1
.3-.2

0

1

Push-pull output mode

P1.1/INT1
0

Schmitt trigger input mode, pull-up, interrupt on falling edge

0

1

Schmitt trigger input mode, interrupt on rising edge

1

0

Schmitt trigger input mode, interrupt on rising or falling edge

1
.1-.0

0

1

Push-pull output mode

P1.0/INT0
0

0

Schmitt trigger input mode, pull-up, interrupt on falling edge

0

1

Schmitt trigger input mode, interrupt on rising edge

1

0

Schmitt trigger input mode, interrupt on rising or falling edge

1

1

Push-pull output mode

4-25

CONTROL REGISTERS

S3F833B/F834B_UM_REV1.10

P1INT -- Port 1 Interrupt Control Register

E6H

Set 1, Bank1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7

P1.7 External Interrupt (INT7) Enable Bit
0
1

.6

Disable interrupt
Enable interrupt

P1.6 External Interrupt (INT6) Enable Bit
0
1

.5

Disable interrupt
Enable interrupt

P1.5 External Interrupt (INT5) Enable Bit
0
1

.4

Disable interrupt
Enable interrupt

P1.4 External Interrupt (INT4) Enable Bit
0
1

.3

Disable interrupt
Enable interrupt

P1.3 External Interrupt (INT3) Enable Bit
0
1

.2

Disable interrupt
Enable interrupt

P1.2 External Interrupt (INT2) Enable Bit
0
1

.1

Disable interrupt
Enable interrupt

P1.1 External Interrupt (INT1) Enable Bit
0
1

.0

Disable interrupt
Enable interrupt

P1.0 External Interrupt (INT0) Enable Bit
0
1

4-26

Disable interrupt
Enable interrupt

S3F833B/F834B_UM_REV1.10

CONTROL REGISTER

P1PND -- Port 1 Interrupt Pending Register

E3H

Set 1, Bank1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7

P1.7 External Interrupt (INT7) Pending Bit
0
1

.6

Interrupt request is not pending (when read); pending bit clear (when write 0)
Interrupt request is pending (when read)

P1.6 External Interrupt (INT6) Pending Bit
0
1

.5

Interrupt request is not pending (when read); pending bit clear (when write 0)
Interrupt request is pending (when read)

P1.5 External Interrupt (INT5) Pending Bit
0
1

.4

Interrupt request is not pending (when read); pending bit clear (when write 0)
Interrupt request is pending (when read)

P1.4 External Interrupt (INT4) Pending Bit
0
1

.3

Interrupt request is not pending (when read); pending bit clear (when write 0)
Interrupt request is pending (when read)

P1.3 External Interrupt (INT3) Pending Bit
0
1

.2

Interrupt request is not pending (when read); pending bit clear (when write 0)
Interrupt request is pending (when read)

P1.2 External Interrupt (INT2) Pending Bit
0
1

.1

Interrupt request is not pending (when read); pending bit clear (when write 0)
Interrupt request is pending (when read)

P1.1 External Interrupt (INT1) Pending Bit
0
1

.0

Interrupt request is not pending (when read); pending bit clear (when write 0)
Interrupt request is pending (when read)

P1.0 External Interrupt (INT0) Pending Bit
0

Interrupt request is not pending (when read); pending bit clear (when write 0)

1

Interrupt request is pending (when read)

4-27

CONTROL REGISTERS

S3F833B/F834B_UM_REV1.10

P2CONH -- Port 2 Control Register (High Byte)

E8H

Set 1, Bank1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7-.6

P2.7/AD7
0

Schmitt trigger input mode

0

1

Schmitt trigger input mode, pull-up

1

0

Alternative function (AD7)

1
.5-.4

0

1

Push-pull output mode

P2.6/AD6
0

Schmitt trigger input mode

0

1

Schmitt trigger input mode, pull-up

1

0

Alternative function (AD6)

1
.3-.2

0

1

Push-pull output mode

P2.5/AD5
0

Schmitt trigger input mode

0

1

Schmitt trigger input mode, pull-up

1

0

Alternative function (AD5)

1
.1-.0

0

1

Push-pull output mode

P2.4/AD4
0

Schmitt trigger input mode

0

1

Schmitt trigger input mode, pull-up

1

0

Alternative function (AD4)

1

4-28

0

1

Push-pull output mode

S3F833B/F834B_UM_REV1.10

CONTROL REGISTER

P2CONL -- Port 2 Control Register (Low Byte)

E9H

Set 1, Bank1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7-.6

P2.3/AD3
0

Schmitt trigger input mode

0

1

Schmitt trigger input mode, pull-up

1

0

Alternative function (AD3)

1
.5-.4

0

1

Push-pull output mode

P2.2/AD2
0

Schmitt trigger input mode

0

1

Schmitt trigger input mode, pull-up

1

0

Alternative function (AD2)

1
.3-.2

0

1

Push-pull output mode

P2.1/AD1
0

Schmitt trigger input mode

0

1

Schmitt trigger input mode, pull-up

1

0

Alternative function (AD1)

1
.1-.0

0

1

Push-pull output mode

P2.0/AD0
0

0

Schmitt trigger input mode

0

1

Schmitt trigger input mode, pull-up

1

0

Alternative function (AD0)

1

1

Push-pull output mode

4-29

CONTROL REGISTERS

S3F833B/F834B_UM_REV1.10

P3CONH -- Port 3 Control Register (High Byte)

EAH

Set 1, Bank1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

-

-

0

0

0

0

0

0

Read/Write

-

-

R/W

R/W

R/W

R/W

R/W

R/W

Addressing Mode

Register addressing mode only

.7-.6

Not used for the S3F833B/F834B

.5-.4

P3.6/SI1
0

Input mode (SI1)

0

1

Open-drain output mode

1

0

Not available

1
.3-.2

0

1

Push-pull output mode

P3.5/SO1
0

Input mode

0

1

Open-drain output mode

1

0

Alternative function (SO1)

1
.1-.0

0

1

Push-pull output mode

P3.4/SCK1
0

Input mode (SCK1)

0

1

Open-drain output mode

1

0

Alternative function (SCK1)

1

4-30

0

1

Push-pull output mode

S3F833B/F834B_UM_REV1.10

CONTROL REGISTER

P3CONL -- Port 3 Control Register (Low Byte)

EBH

Set 1, Bank1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7-.6

P3.3/SI0
0

Input mode (SI0)

0

1

Open-drain output mode

1

0

Not available

1
.5-.4

0

1

Push-pull output mode

P3.2/SO0
0

Input mode

0

1

Open-drain output mode

1

0

Alternative function (SO0)

1
.3-.2

0

1

Push-pull output mode

P3.1/SCK0
0

Input mode (SCK0)

0

1

Open-drain output mode

1

0

Alternative function (SCK0)

1
.1-.0

0

1

Push-pull output mode

P3.0/BUZ
0

0

Input mode

0

1

Open-drain output mode

1

0

Alternative function (BUZ)

1

1

Push-pull output mode

4-31

CONTROL REGISTERS

S3F833B/F834B_UM_REV1.10

P3PUR -- Port 3 Pull-up Control Register

ECH

Set 1, Bank1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

-

0

0

0

0

0

0

0

Read/Write

-

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Addressing Mode

Register addressing mode only

.7

Not used for the S3F833B/F834B

.6

P3.6's Pull-up Resistor Enable Bit
0
1

.5

Disable pull-up resistor
Enable pull-up resistor

P3.5's Pull-up Resistor Enable Bit
0
1

.4

Disable pull-up resistor
Enable pull-up resistor

P3.4's Pull-up Resistor Enable Bit
0
1

.3

Disable pull-up resistor
Enable pull-up resistor

P3.3's Pull-up Resistor Enable Bit
0
1

.2

Disable pull-up resistor
Enable pull-up resistor

P3.2's Pull-up Resistor Enable Bit
0
1

.1

Disable pull-up resistor
Enable pull-up resistor

P3.1's Pull-up Resistor Enable Bit
0
1

.0

Disable pull-up resistor
Enable pull-up resistor

P3.0's Pull-up Resistor Enable Bit
0

Disable pull-up resistor

1

Enable pull-up resistor

NOTE: A pull-up resistor of port 3 is automatically disabled only when the corresponding pin is selected as push-pull output
or alternative function

4-32

S3F833B/F834B_UM_REV1.10

CONTROL REGISTER

P9CONH -- Port 9 Control Register (High Byte)

E7H

Set 1, Bank1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7-.6

P9.7/VLC0
0

Input mode

0

1

Input mode, pull-up

1

0

Alternative function (VLC0)

1
.5-.4

0

1

Push-pull output mode

P9.6/ VLC1
0

Input mode

0

1

Input mode, pull-up

1

0

Alternative function (VLC1)

1
.3-.2

0

1

Push-pull output mode

P9.5/VLC2
0

Input mode

0

1

Input mode, pull-up

1

0

Alternative function (VLC2)

1
.1-.0

0

1

Push-pull output mode

P9.4/VLC3
0

0

Input mode

0

1

Input mode, pull-up

1

0

Alternative function (VLC3)

1

1

Push-pull output mode

4-33

CONTROL REGISTERS

S3F833B/F834B_UM_REV1.10

P10CONH -- Port 10 Control Register (High Byte)

D0H

Set 1, Bank1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7-.6

P10.7
0

Input mode

0

1

Input mode, pull-up

1

0

Not available

1
.5-.4

0

1

Push-pull output mode

P10.6/TXD0
0

Input mode

0

1

Input mode, pull-up

1

0

Alternative function (TXD0)

1
.3-.2

0

1

Push-pull output mode

P10.5/RXD0
0

Input mode (RXD0)

0

1

Input mode, pull-up

1

0

Alternative function (RXD0 out)

1
.1-.0

0

1

Push-pull output mode

P10.4/EO
0

1

Input mode, pull-up

1

0

Alternative function (EO) (note)

1

4-34

Input mode

0

NOTE:

0

1

Not available

When you selected PLL mode enable, Port10.0, Port10.1 and Port10.4 are automatically selected to
"alternative function".

S3F833B/F834B_UM_REV1.10

CONTROL REGISTER

P10CONL -- Port 10 Control Register (Low Byte)

D1H

Set 1, Bank1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7-.6

P10.3/FMIF
0

Input mode

0

1

Input mode, pull-up

1

0

Alternative function (FMIF)

1
.5-.4

0

1

Not available

(note1)

P10.2/AMIF
0

Input mode

0

1

Input mode, pull-up

1

0

Alternative function (AMIF) (note1)

1
.3-.2

0

1

Not available

P10.1/VCOAM
0

Input mode (RXD0)

0

1

Input mode, pull-up

1

0

Alternative function (VCOAM) (note2)

1
.1-.0

0

1

Not available

P10.0/VCOFM
0

0

Input mode

0

1

Input mode, pull-up

1

0

Alternative function (VCOFM) (note2)

1

1

Not available

NOTES:
1.
When you selected IFC mode enable, Port10.2 and Port10.3 are automatically selected to "alternative function".
2.
When you selected PLL mode enable, Port10.0, Port10.1 and Port10.4 are automatically selected to
"alternative function".

4-35

CONTROL REGISTERS

S3F833B/F834B_UM_REV1.10

PG0CON -- Port Group 0 Control Register

EDH

Set 1, Bank1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7-.6

P4.0-P4.3/SEG39-SEG36
0

Input mode

0

1

Input mode, pull-up

1

0

Open-drain output mode

1
.5-.4

0

1

Push-pull output mode

P4.4-P4.7/SEG35-SEG32
0

Input mode

0

1

Input mode, pull-up

1

0

Open-drain output mode

1
.3-.2

0

1

Push-pull output mode

P5.0-P5.3/SEG31- SEG28
0

Input mode

0

1

Input mode, pull-up

1

0

Open-drain output mode

1
.1-.0

0

1

Push-pull output mode

P5.4-P5.7/SEG27-SEG24
0

Input mode

0

1

Input mode, pull-up

1

0

Open-drain output mode

1

4-36

0

1

Push-pull output mode

S3F833B/F834B_UM_REV1.10

CONTROL REGISTER

PG1CON -- Port Group 1 Control Register

EEH

Set 1, Bank1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7-.6

P6.0-P6.3/SEG23-SEG20
0

Input mode

0

1

Input mode, pull-up

1

0

Open-drain output mode

1
.5-.4

0

1

Push-pull output mode

P6.4-P6.7/SEG19-SEG16
0

Input mode

0

1

Input mode, pull-up

1

0

Open-drain output mode

1
.3-.2

0

1

Push-pull output mode

P7.0-P7.3/ SEG15-SEG12
0

Input mode

0

1

Input mode, pull-up

1

0

Open-drain output mode

1
.1-.0

0

1

Push-pull output mode

P7.4-P7.7/SEG11-SEG8
0

0

Input mode

0

1

Input mode, pull-up

1

0

Open-drain output mode

1

1

Push-pull output mode

4-37

CONTROL REGISTERS

S3F833B/F834B_UM_REV1.10

PG2CON -- Port Group 2 Control Register

EFH

Set 1, Bank1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7

SIO1 Output Control Bit
0
1

.6

SO1, SCK1 output is selected as push-pull
SO1, SCK1 output is selected as open-drain

SIO0 Output Control Bit
0
1

.5

SO0, SCK0 output is selected as push-pull
SO0, SCK0 output is selected as open-drain

P1.4-P1.7 Input Enable bit
0
1

.4

Enable port 1.4-1.7 input
Disable port 1.4-1.7 input

P1.0-P1.3 Input Enable bit
0
1

.3-.2

Enable port 1.0-1.3 input
Disable port 1.0-1.3 input

P8.0-P8.3/SEG0-3/COM7-4 and P8.4-P8.7/COM3-0
0

Schmitt trigger input mode

0

1

Schmitt trigger input mode, pull-up

1

0

Open-drain output mode

1
.1-.0

0

1

Push-pull output mode

P9.0-P9.3/SEG7-SEG4
0

Schmitt trigger input mode

0

1

Schmitt trigger input mode, pull-up

1

0

Open-drain output mode

1

4-38

0

1

Push-pull output mode

S3F833B/F834B_UM_REV1.10

CONTROL REGISTER

PLLMOD -- PLL Mode Register

F7H

Set 1, Bank0

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

(note1)

0

(note1)

(note1)

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7 and .4

PLL Frequency Division method Selection Bits
0

Not available

0

1

Direct method for VCOAM input (0.5 to 5MHz)

1

0

Pulse swallow method for VCOAM input (5 to 30MHz)

1
.6

0

1

Pulse swallow method for VCOFM input (30 to 150MHz) (note2)

PLL Enable/Disable Bit
0
1

.5

Disable PLL
Enable PLL

Bit Value to be Loaded into PLLD0 Register
NF bit is loaded into the LSB of swallow counter

.3

INTIF Interrupt Enable Bit
0
1

.2

Disable INTIF interrupt
Enable INTIF interrupt

INTIF Interrupt Pending Bit
0
1

.1

No interrupt pending (when read), Clear pending bit (when write)
Interrupt is pending (when read)

INTCE Interrupt Enable Bit
0
1

.0

Disable INTCE interrupt request at the CE pin
Enable INTCE interrupt request at the CE pin

INTCE Interrupt Pending Bit
0

No interrupt pending (when read), Clear pending bit (when write)

1

Interrupt is pending (when read)

NOTES:
1.

If a system reset occurs during operation mode, the current value contained is retained. If a system reset occurs after
power-on, the value is undefined.

2.

Refer to "PLL electrical characteristics" in 20th chapter.

4-39

CONTROL REGISTERS

S3F833B/F834B_UM_REV1.10

PLLREF -- PLL Reference Frequency Selection Register

F8H

Set 1, Bank0

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

(1)

(1)

(1)

(2)

(1)

(1)

(1)

(1)

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7

PLL Frequency Synthesizer Locked/Unlocked Status Flag
0 PLL currently in locked state
1 PLL currently in unlocked state

.6

CE Pin level Status Flag
0
1

.5

IF Counter Gate Open/Close Status Flag
0
1

.4

Clear power-on flag bit (when write)
Power-on occurred (when read)

Reference Frequency Selection Bits (IFMOD.4 = 0)
0
0
0
0
0
0
0
0
1
1

4-40

Gate is currently open
Gate is currently close

Power on Flag (3)
0
1

.3-.0

CE pin is currently low level
CE pin is currently high level

0
0
0
0
1
1
1
1
0
0

0
0
1
1
0
0
1
1
0
0

0
1
0
1
0
1
0
1
0
1

1-kHz signal
3-kHz signal
5-kHz signal
6.25-kHz signal
9-kHz signal
10-kHz signal
12.5-kHz signal
25-kHz signal
50-kHz signal
100-kHz signal

S3F833B/F834B_UM_REV1.10

CONTROL REGISTER

PLLREF -- PLL Reference Frequency Selection Register (Concluded)
Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

(1)

(1)

(1)

(2)

(1)

(1)

(1)

(1)

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.3-.0

Reference Frequency Selection Bits (IFMOD.4 = 1)
x
x
x
x
x
x
x
x

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

1-kHz signal
3-kHz signal
3.15-kHz signal
5-kHz signal
6.25-kHz signal
12.5-kHz signal
15-kHz signal
25-kHz signal

NOTES:
1.
If a system reset occurs during operation mode, the current contained is retained. If a system reset occurs after
power-on, the value is undefined.
2.
If a system reset occurs during operation mode, the current contained is retained. If a system reset occurs after
power-on, the value is "1".
3.
The POF bit is read initially to check whether or not power has been turned on.
4.
If the main clock is 9MHz, IFMOD.7-.6 should be set to "01".
5.
If the main clock is 7.2MHz, IFMOD.7-.6 should be set to "10".
6.
Where "X" is don't care

4-41

CONTROL REGISTERS

S3F833B/F834B_UM_REV1.10

PP -- Register Page Pointer

DFH

Set 1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

R/W
Register addressing mode only

.7-.4

Destination Register Page Selection Bits
0
0
0
0 Destination: page 0
0
0
0
1 Destination: page 1
0
0
1
0 Destination: page 2
0
0
1
1 Destination: page 3
0
1
0
0 Destination: page 4
0
1
0
1 Destination: page 5
0
1
1
0 Destination: page 6
0
1
1
1 Destination: page 7
1
0
0
0 Destination: page 8
1
0
0
1 Destination: page 9

.3 -.0

Source Register Page Selection Bits
0
0
0
0 Source: page 0
0
0
0
1 Source: page 1
0
0
1
0 Source: page 2
0
0
1
1 Source: page 3
0
1
0
0 Source: page 4
0
1
0
1 Source: page 5
0
1
1
0 Source: page 6
0
1
1
1 Source: page 7
1
0
0
0 Source: page 8
1
0
0
1 Source: page 9

NOTE:

4-42

In the S3F833B/F834B microcontroller, the internal register file is configured as ten pages (pages 0-9). The pages
0-8 are used for general purpose register file, and page 9 is used for LCD data register or general purpose registers.

S3F833B/F834B_UM_REV1.10

CONTROL REGISTER

RP0 -- Register Pointer 0

D6H

Set 1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

1

1

0

0

0

-

-

-

R/W

R/W

R/W

R/W

R/W

-

-

-

Read/Write
Addressing Mode

Register addressing only

.7-.3

Register Pointer 0 Address Value
Register pointer 0 can independently point to one of the 256-byte working register
areas in the register file. Using the register pointers RP0 and RP1, you can select
two 8-byte register slices at one time as active working register space. After a reset,
RP0 points to address C0H in register set 1, selecting the 8-byte working register
slice C0H-C7H.

.2-.0

Not used for the S3F833B/F834B

RP1 -- Register Pointer 1

D7H

Set 1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

1

1

0

0

1

-

-

-

R/W

R/W

R/W

R/W

R/W

-

-

-

Read/Write
Addressing Mode

Register addressing only

.7 -.3

Register Pointer 1 Address Value
Register pointer 1 can independently point to one of the 256-byte working register
areas in the register file. Using the register pointers RP0 and RP1, you can select
two 8-byte register slices at one time as active working register space. After a reset,
RP1 points to address C8H in register set 1, selecting the 8-byte working register
slice C8H-CFH.

.2 -.0

Not used for the S3F833B/F834B

4-43

CONTROL REGISTERS

S3F833B/F834B_UM_REV1.10

SIO0CON -- SIO 0 Control Register

E7H

Set 1, Bank0

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7

SIO 0 Shift Clock Selection Bit
0
1

.6

Internal clock (P.S clock)
External clock (SCK0)

Data Direction Control Bit
0
1

.5

MSB-first mode
LSB-first mode

SIO 0 Mode Selection Bit
0
1

.4

Receive-only mode
Transmit/Receive mode

Shift Clock Edge Selection Bit
0
1

.3

Tx at falling edges, Rx at rising edges
Tx at rising edges, Rx at falling edges

SIO 0 Counter Clear and Shift Start Bit
0
1

.2

No action
Clear 3-bit counter and start shifting

SIO 0 Shift Operation Enable Bit
0
1

.1

Disable shifter and clock counter
Enable shifter and clock counter

SIO 0 Interrupt Enable Bit
0
1

.0

Disable SIO 0 Interrupt
Enable SIO 0 Interrupt

SIO 0 Interrupt Pending Bit
0
1

4-44

No interrupt pending (when read), Clear pending condition (when write)
Interrupt is pending

S3F833B/F834B_UM_REV1.10

CONTROL REGISTER

SIO1CON -- SIO 1 Control Register

EAH

Set 1, Bank0

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7

SIO 1 Shift Clock Selection Bit
0
1

.6

Internal clock (P.S clock)
External clock (SCK1)

Data Direction Control Bit
0
1

.5

MSB-first mode
LSB-first mode

SIO 1 Mode Selection Bit
0
1

.4

Receive-only mode
Transmit/Receive mode

Shift Clock Edge Selection Bit
0
1

.3

Tx at falling edges, Rx at rising edges
Tx at rising edges, Rx at falling edges

SIO 1 Counter Clear and Shift Start Bit
0
1

.2

No action
Clear 3-bit counter and start shifting

SIO 1 Shift Operation Enable Bit
0
1

.1

Disable shifter and clock counter
Enable shifter and clock counter

SIO 1 Interrupt Enable Bit
0
1

.0

Disable SIO Interrupt
Enable SIO Interrupt

SIO 1 Interrupt Pending Bit
0

No interrupt pending (when read), Clear pending condition (when write)

1

Interrupt is pending

4-45

CONTROL REGISTERS

S3F833B/F834B_UM_REV1.10

SPH -- Stack Pointer (High Byte)

D8H

Set 1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

x

x

x

x

x

x

x

x

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7-.0

Stack Pointer Address (High Byte)
The high-byte stack pointer value is the upper eight bits of the 16-bit stack pointer
address (SP15-SP8). The lower byte of the stack pointer value is located in register
SPL (D9H). The SP value is undefined following a reset.

SPL -- Stack Pointer (Low Byte)

D9H

Set 1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

x

x

x

x

x

x

x

x

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7-.0

Stack Pointer Address (Low Byte)
The low-byte stack pointer value is the lower eight bits of the 16-bit stack pointer
address (SP7-SP0). The upper byte of the stack pointer value is located in register
SPH (D8H). The SP value is undefined following a reset.

4-46

S3F833B/F834B_UM_REV1.10

CONTROL REGISTER

STPCON -- Stop Control Register

D1H

Set 1, Bank0

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7-.0

STOP Control Bits
10100101
Other values

NOTE:

Enable stop instruction
Disable stop instruction

Before execute the STOP instruction, set this STPCON register as "10100101b". Otherwise the STOP
instruction will not execute as well as reset will be generated.

4-47

CONTROL REGISTERS

S3F833B/F834B_UM_REV1.10

SYM -- System Mode Register

DEH

Set 1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

0

-

-

x

x

x

0

0

R/W

-

-

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7

Not used, But you must keep &quot; 0 &quot;

.6-.5

Not used for the S3F833B/F834B

.4-.2

Fast Interrupt Level Selection Bits (1)
0

0

IRQ0

0

0

1

IRQ1

0

1

0

IRQ2

0

1

1

IRQ3

1

0

0

IRQ4

1

0

1

IRQ5

1

1

0

IRQ6

1
.1

0

1

1

IRQ7

Fast Interrupt Enable Bit (2)
0
1

.0

Disable fast interrupt processing
Enable fast interrupt processing

Global Interrupt Enable Bit (3)
0

Disable all interrupt processing

1

Enable all interrupt processing

NOTES:
1.
You can select only one interrupt level at a time for fast interrupt processing.
2.
Setting SYM.1 to &quot; 1 &quot; enables fast interrupt processing for the interrupt level currently selected by SYM.2-SYM.4.
3.
Following a reset, you must enable global interrupt processing by executing an EI instruction
(not by writing a &quot; 1 &quot; to SYM.0).

4-48

S3F833B/F834B_UM_REV1.10

CONTROL REGISTER

T0CON -- Timer 0 Control Register

E2H

Set 1, Bank0

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7-.5

Timer 0 Input Clock Selection Bits
0

0

fxx/1024

0

0

1

fxx/256

0

1

0

fxx/64

0

1

1

fxx/8

1

0

0

fxx/1

1

0

1

External clock(T0CLK) falling edge

1

1

0

External clock(T0CLK) rising edge

1
.4-.3

0

1

1

Counter stop

Timer 0 Operating Mode Selection Bits
0

Interval mode (T0OUT)

0

1

Capture mode (capture on rising edge, counter running, OVF can occur)

1

0

Capture mode (capture on falling edge, counter running, OVF can occur)

1
.2

0

1

PWM mode (OVF and match interrupt can occur)

Timer 0 Counter Clear Bit
0
1

.1

Disable counting operation
Clear the timer 0 counter (When write, Automatically cleared to "0" after being
cleared counter)

Timer 0 Match/Capture Interrupt Enable Bit
0
1

.0

Disable interrupt
Enable interrupt

Timer 0 Overflow Interrupt Enable Bit
0

Disable interrupt

1

Enable interrupt

4-49

CONTROL REGISTERS

S3F833B/F834B_UM_REV1.10

T1CON -- Timer 1 Control Register

E5H

Set 1, Bank0

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

0

0

0

-

0

0

0

0

R/W

R/W

R/W

-

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7-.5

Timer 1 Input Clock Selection Bits
0

0

0

fxx/256

0

0

1

fxx/64

0

1

0

fxx/8

0

1

1

fxx/1

1

1

1

External clock (T1CLK) input

.4

Not used for the S3F833B/F834B

.3

Timer 1 Counter Clear Bit
0
0

.2

No effect
Clear the timer 1 counter(When write, Automatically cleared to "0" after being
cleared counter)

Timer 1 Count Enable Bit
0
1

.1

Disable counting operation
Enable counting operation

Timer 1 Match Interrupt Enable Bit
0
1

.0

Disable interrupt
Enable interrupt

Timer 1 Interrupt Pending Bit
0
1

4-50

Interrupt request is not pending; (when read) pending bit clear when write 0
Interrupt request is pending (when read)

S3F833B/F834B_UM_REV1.10

CONTROL REGISTER

T2CON -- Timer 2 Control Register

FBH

Set 1, Bank1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

0

0

0

-

0

0

0

0

R/W

R/W

R/W

-

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7-.5

Timer A Input Clock Selection Bits
0

0

0

fxx/256

0

0

1

fxx/64

0

1

0

fxx/8

0

1

1

fxx(system clock)

1

1

1

External clock (T2CLK) input

.4

Not used for the S3F833B/F834B

.3

Timer 2 Counter Clear Bit
0
0

.2

No effect
Clear the timer 2 counter(When write, Automatically cleared to "0" after being
cleared counter)

Timer 2 Count Enable Bit
0
1

.1

Disable counting operation
Enable counting operation

Timer 2 Match Interrupt Enable Bit
0
1

.0

Disable interrupt
Enable interrupt

Timer 2 Interrupt Pending Bit
0

Interrupt request is not pending; (when read) pending bit clear when write 0

1

Interrupt request is pending (when read)

4-51

CONTROL REGISTERS

S3F833B/F834B_UM_REV1.10

UART0CON -- UART 0 Control Register

00H

Page0

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode
.7-.6

R/W
Register addressing mode only

UART 0 Mode Selection Bits
0
0 Mode 0: shift register (fxx/(16 × (BRDATA0+1)))
0

1

Mode 1: 8-bit UART (fxx/(16 × (BRDATA0+1)))

1

0

Mode 2: 9-bit UART (fxx/16)

1

1

Mode 3: 9-bit UART (fxx/(16 × (BRDATA0+1)))

.5

Multiprocessor Communication Enable Bit (for modes 2 and 3 only)
0 Disable
1 Enable

.4

Serial Data Receive Enable Bit
0 Disable
1 Enable

.3

TB8
Location of the 9th data bit to be transmitted in UART 0 mode 2 or 3 ( &quot; 0 &quot; or &quot; 1 &quot; )

.2

RB8
Location of the 9th data bit to be transmitted in UART 0 mode 2 or 3 ( &quot; 0 &quot; or &quot; 1 &quot; )

.1

Receive Interrupt Enable Bit
0 Disable Rx interrupt
1 Enable Rx interrupt

.0

Transmit Interrupt Enable Bit
0 Disable Tx interrupt
1 Enable Tx interrupt

NOTES:
1.
In mode 2 and 3, if the MCE bit is set to &quot; 1 &quot; then the receive interrupt will not be activated if the received 9th data bit
&quot; 0 &quot; .
In mode 1, if MCE = &quot; 1 &quot; the receive interrupt will not be activated if a valid stop bit was not received. In mode 0, the
MCE bit should be &quot; 0 &quot; .
2.
The descriptions for 8-bit and 9-bit UART mode do not include start and stop bits for serial data receive and transmit.
3.
Rx/Tx interrupt pending bits are in INTPND register.

4-52

S3F833B/F834B_UM_REV1.10

CONTROL REGISTER

UART1CON -- UART 1 Control Register

03H

Page0

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode
.7-.6

R/W
Register addressing mode only

UART 1 Mode Selection Bits
0
0 Mode 0: shift register (fxx/(16 × (BRDATA1+1)))
0

1

Mode 1: 8-bit UART (fxx/(16 × (BRDATA1+1)))

1

0

Mode 2: 9-bit UART (fxx/16)

1

1

Mode 3: 9-bit UART (fxx/(16 × (BRDATA1+1)))

.5

Multiprocessor Communication Enable Bit (for modes 2 and 3 only)
0 Disable
1 Enable

.4

Serial Data Receive Enable Bit
0 Disable
1 Enable

.3

TB8
Location of the 9th data bit to be transmitted in UART 1 mode 2 or 3 ( &quot; 0 &quot; or &quot; 1 &quot; )

.2

RB8
Location of the 9th data bit to be transmitted in UART 1 mode 2 or 3 ( &quot; 0 &quot; or &quot; 1 &quot; )

.1

Receive Interrupt Enable Bit
0 Disable Rx interrupt
1 Enable Rx interrupt

.0

Transmit Interrupt Enable Bit
0 Disable Tx interrupt
1 Enable Tx interrupt

NOTES:
1.
In mode 2 and 3, if the MCE bit is set to &quot; 1 &quot; then the receive interrupt will not be activated if the received 9th data bit
&quot; 0 &quot; .
In mode 1, if MCE = &quot; 1 &quot; the receive interrupt will not be activated if a valid stop bit was not received. In mode 0, the
MCE bit should be &quot; 0 &quot; .
2.
The descriptions for 8-bit and 9-bit UART mode do not include start and stop bits for serial data receive and transmit.
3.
Rx/Tx interrupt pending bits are in INTPND register.

4-53

CONTROL REGISTERS

S3F833B/F834B_UM_REV1.10

WTCON -- Watch Timer Control Register

E6H

Set 1, Bank0

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET Value

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read/Write
Addressing Mode

Register addressing mode only

.7

Watch Timer Clock Selection Bit
0
1

.6

Select main clock divided by 60 (fx/60)
Sub system clock (fxt)

Watch Timer Enable/Disable Bit
0
1

.5-.4

Disable watch timer
Enable watch timer

Buzzer Signal Selection Bits (at fw=75KHz)
0

0.47 kHz

0

1

0.94 kHz

1

0

1.87 kHz

1
.3-.2

0

1

3.75 kHz

Watch Timer Speed Selection Bits (at fw=75KHz)
0

Set watch timer interrupt to 1.0s

0

1

Set watch timer interrupt to 0.5s

1

0

Set watch timer interrupt to 0.1s

1
.1

0

1

Set watch timer interrupt to 50ms

Watch Timer Interrupt Enable/Disable Bit
0
1

.0

Disable watch timer Interrupt
Enable watch timer Interrupt

Watch Timer Interrupt Pending Bit
0
1

4-54

Interrupt request is not pending (when read); pending bit clear (when write 0)
Interrupt request is pending (when read)

S3F833B/F834B_UM_REV1.10

5

INTERRUPT STRUCTURE

INTERRUPT STRUCTURE

OVERVIEW
The S3F8-series interrupt structure has three basic components: levels, vectors, and sources. The SAM8 CPU
recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific interrupt level has
more than one vector address, the vector priorities are established in hardware. A vector address can be
assigned to one or more sources.
Levels
Interrupt levels are the main unit for interrupt priority assignment and recognition. All peripherals and I/O blocks
can issue interrupt requests. In other words, peripheral and I/O operations are interrupt-driven. There are eight
possible interrupt levels: IRQ0-IRQ7, also called level 0-level 7. Each interrupt level directly corresponds to an
interrupt request number (IRQn). The total number of interrupt levels used in the interrupt structure varies from
device to device. The S3F833B/F834B interrupt structure recognizes eight interrupt levels.
The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels. They are just
identifiers for the interrupt levels that are recognized by the CPU. The relative priority of different interrupt levels is
determined by settings in the interrupt priority register, IPR. Interrupt group and subgroup logic controlled by IPR
settings lets you define more complex priority relationships between different levels.
Vectors
Each interrupt level can have one or more interrupt vectors, or it may have no vector address assigned at all. The
maximum number of vectors that can be supported for a given level is 128 (The actual number of vectors used for
S3F8-series devices is always much smaller). If an interrupt level has more than one vector address, the vector
priorities are set in hardware. S3F833B/F834B uses twenty-one vectors.
Sources
A source is any peripheral that generates an interrupt. A source can be an external pin or a counter overflow.
Each vector can have several interrupt sources. In the S3F833B/F834B interrupt structure, there are twenty-one
possible interrupt sources.
When a service routine starts, the respective pending bit should be either cleared automatically by hardware or
cleared &quot; manually &quot; by program software. The characteristics of the source's pending mechanism determine which
method would be used to clear its respective pending bit.

5-1

INTERRUPT STRUCTURE

S3F833B/F834B_UM_REV1.10

INTERRUPT TYPES
The three components of the S3F8 interrupt structure described before -- levels, vectors, and sources -- are
combined to determine the interrupt structure of an individual device and to make full use of its available interrupt
logic. There are three possible combinations of interrupt structure components, called interrupt types 1, 2, and 3.
The types differ in the number of vectors and interrupt sources assigned to each level (see Figure 5-1):
Type 1:

One level (IRQn) + one vector (V1) + one source (S1)

Type 2:

One level (IRQn) + one vector (V1) + multiple sources (S1 - Sn)

Type 3:

One level (IRQn) + multiple vectors (V1 - Vn) + multiple sources (S1 - Sn, Sn+1 - Sn+m)

In the S3F833B/F834B microcontroller, two interrupt types are implemented.

Levels
Type 1:

Vectors

Sources

IRQn

V1

S1
S1

Type 2:

IRQn

V1

S2
S3
Sn

V1

S2
S3

Vn

IRQn

V2
V3

Type 3:

S1

Sn
Sn + 1

NOTES:
1. The number of Sn and Vn value is expandable.
2. In the S3F833B/F834B
implementation, interrupt types 1 and 3 are used.

Figure 5-1. S3F8-Series Interrupt Types

5-2

Sn + 2
Sn + m

S3F833B/F834B_UM_REV1.10

INTERRUPT STRUCTURE

S3F833B/F834B INTERRUPT STRUCTURE
The S3F833B/F834B microcontroller supports nineteen interrupt sources. All twenty-one of the interrupt sources
have a corresponding interrupt vector address. Eight interrupt levels are recognized by the CPU in this devicespecific interrupt structure, as shown in Figure 5-2.
When multiple interrupt levels are active, the interrupt priority register (IPR) determines the order in which
contending interrupts are to be serviced. If multiple interrupts occur within the same interrupt level, the interrupt
with the lowest vector address is usually processed first (The relative priorities of multiple interrupts within a single
level are fixed in hardware).
When the CPU grants an interrupt request, interrupt processing starts. All other interrupts are disabled and the
program counter value and status flags are pushed to stack. The starting address of the service routine is fetched
from the appropriate vector address (plus the next 8-bit value to concatenate the full 16-bit address) and the
service routine is executed.

5-3

INTERRUPT STRUCTURE

LEVEL
RESET

S3F833B/F834B_UM_REV1.10

VECTOR

SOURCE

RESET/CLEAR

100H

Basic Timer overflow

H/W

E0H

Timer 0 match/capture

S/W

E2H

Timer 0 overflow

H / W, S / W

E4H

Timer 2 match

S/W

E6H

Timer 1 match

S/W

E8H

SIO1 interrupt

S/W

EAH

SIO0 interrupt

S/W

F0H

UART 0 data transmit

S/W

F2H

UART 0 data receive

S/W

F4H

UART 1 data transmit

S/W

F6H

UART 1 data receive

S/W

F8H

Watch timer interrupt

S/W

D0H

P1.0 External Interrupt

S/W

D2H

P1.1 External Interrupt

S/W

D4H

P1.2 External Interrupt

S/W

D6H

P1.3 External Interrupt

S/W

D8H

P1.4 External Interrupt

S/W

DAH

P1.5 External Interrupt

S/W

DCH

P1.6 External Interrupt

S/W

DEH

P1.7 External Interrupt

S/W

IRQ0

IRQ1

IRQ2

IRQ3

IRQ4

IRQ5

IRQ6

FAH

CE interrupt

S/W

IRQ7

FCH

IF interrupt

S/W

NOTES:
1. Within a given interrupt level, the low vector address has high priority.
For example, E0H has higher priority than E2H within the level IRQ.0 the priorities
within each level are set at the factory.
2. External interrupts are triggered by a rising or falling edge, depending on the
corresponding control register setting.

Figure 5-2. S3F833B/F834B Interrupt Structure

5-4

S3F833B/F834B_UM_REV1.10

INTERRUPT STRUCTURE

INTERRUPT VECTOR ADDRESSES
All interrupt vector addresses for the S3F833B/F834B interrupt structure are stored in the vector address area of
the first 256 bytes of the program memory (ROM).
You can allocate unused locations in the vector address area as normal program memory. If you do so, please be
careful not to overwrite any of the stored vector addresses (Table 5-1 lists all vector addresses).
The program reset address in the ROM is 0100H.

(Decimal)
65,535

(Hex)
FFFFH

64K-bytes Program
Memory Area

255

FFH

nRESET
address

Interrupt Vector Area

Smart Option
0

3FH
3CH
00H

Figure 5-3. ROM Vector Address Area

5-5

INTERRUPT STRUCTURE

S3F833B/F834B_UM_REV1.10

Table 5-1. Interrupt Vectors
Vector Address
Decimal
Value

Hex
Value

256

100H

226

Interrupt Source

Request

Reset/Clear

Interrupt
Level

Priority in
Level

H/W

Basic timer overflow

Reset

-

?

E2H

Timer 0 overflow

IRQ0

1

?

224

E0H

Timer 0 match/capture

230

E6H

Timer 1 match

228

E4H

Timer 2 match

2234

EAH

SIO0 interrupt

232

E8H

SIO1 interrupt

248

F8H

Watch timer interrupt

246

F6H

244

S/W

?

0

?

1

?

0

?

1

?

0

?

4

?

UART 1 data receive

3

?

F4H

UART 1 data transmit

2

?

242

F2H

UART 0 data receive

1

?

240

F0H

UART 0 data transmit

0

?

214

D6H

P1.3 external interrupt

3

?

212

D4H

P1.2 external interrupt

2

?

210

D2H

P1.1 external interrupt

1

?

208

D0H

P1.0 external interrupt

0

?

222

DEH

P1.7 external interrupt

3

?

220

DCH

P1.6 external interrupt

2

?

218

DAH

P1.5 external interrupt

1

?

216

D8H

P1.4 external interrupt

0

?

250

FAH

CE interrupt

IRQ6

-

?

252

FCH

IF interrupt

IRQ7

-

?

IRQ1
IRQ2
IRQ3

IRQ4

IRQ5

NOTES:
1. Interrupt priorities are identified in inverse order: &quot; 0 &quot; is the highest priority, &quot; 1 &quot; is the next highest, and so on.
2. If two or more interrupts within the same level contend, the interrupt with the lowest vector address usually has priority
over one with a higher vector address. The priorities within a given level are fixed in hardware.

5-6

S3F833B/F834B_UM_REV1.10

INTERRUPT STRUCTURE

ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI)
Executing the Enable Interrupts (EI) instruction globally enables the interrupt structure. All interrupts are then
serviced as they occur according to the established priorities.
NOTE
The system initialization routine executed after a reset must always contain an EI instruction to globally
enable the interrupt structure.
During the normal operation, you can execute the DI (Disable Interrupt) instruction at any time to globally disable
interrupt processing. The EI and DI instructions change the value of bit 0 in the SYM register.
SYSTEM-LEVEL INTERRUPT CONTROL REGISTERS
In addition to the control registers for specific interrupt sources, four system-level registers control interrupt
processing:
-- The interrupt mask register, IMR, enables (un-masks) or disables (masks) interrupt levels.
-- The interrupt priority register, IPR, controls the relative priorities of interrupt levels.
-- The interrupt request register, IRQ, contains interrupt pending flags for each interrupt level (as opposed to
each interrupt source).
-- The system mode register, SYM, enables or disables global interrupt processing (SYM settings also enable
fast interrupts and control the activity of external interface, if implemented).

Table 5-2. Interrupt Control Register Overview
Control Register

ID

R/W

Function Description

Interrupt mask register

IMR

R/W

Bit settings in the IMR register enable or disable interrupt
processing for each of the eight interrupt levels: IRQ0-IRQ7.

Interrupt priority register

IPR

R/W

Controls the relative processing priorities of the interrupt levels.
The seven levels of S3F833B/F834B are organized into three
groups: A, B, and C. Group A is IRQ0 and IRQ1, group B is
IRQ2, IRQ3 and IRQ4, and group C is IRQ5, IRQ6, and IRQ7.

Interrupt request register

IRQ

R

This register contains a request pending bit for each interrupt
level.

System mode register

SYM

R/W

This register enables/disables fast interrupt processing,
dynamic global interrupt processing, and external interface
control (An external memory interface is implemented in the
S3F833B/F834B microcontroller).

NOTE: Before IMR register is changed to any value, all interrupts must be disable. Using DI instruction is recommended.

5-7

INTERRUPT STRUCTURE

S3F833B/F834B_UM_REV1.10

INTERRUPT PROCESSING CONTROL POINTS
Interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source. The
system-level control points in the interrupt structure are:
-- Global interrupt enable and disable (by EI and DI instructions or by direct manipulation of SYM.0)
-- Interrupt level enable/disable settings (IMR register)
-- Interrupt level priority settings (IPR register)
-- Interrupt source enable/disable settings in the corresponding peripheral control registers
NOTE
When writing an application program that handles interrupt processing, be sure to include the necessary
register file address (register pointer) information.

EI

S

RESET

R

Q

Interrupt Request Register
(Read-only)

Polling
Cycle

IRQ0-IRQ7,
Interrupts
Interrupt Priority
Register

Vector
Interrupt
Cycle

Interrupt Mask
Register

Global Interrupt Control (EI,
DI or SYM.0 manipulation)

Figure 5-4. Interrupt Function Diagram

5-8

S3F833B/F834B_UM_REV1.10

INTERRUPT STRUCTURE

PERIPHERAL INTERRUPT CONTROL REGISTERS
For each interrupt source there is one or more corresponding peripheral control registers that let you control the
interrupt generated by the related peripheral (see Table 5-3).
Table 5-3. Interrupt Source Control and Data Registers
Interrupt Source

Interrupt Level

Register(s)

Location(s) in Set 1

Timer 0 match/capture
Timer 0 overflow

IRQ0

T0CON
T0CNT
T0DATA

E2H, bank 0
F0H, bank 0
E1H, bank 0

Timer 1 match

IRQ1

T1CON
T1CNT
T1DATA

E5H, bank 0
F3H, bank 0
E4H, bank 0

T2CON
T2CNTH, T2CNTL,
T2DATAH, T2DATAL

F8H, bank 1
FCH, FDH, bank 1
E6H, FFH, bank 1

SIO0CON
SIO0DATA
SIO0PS

E7H, bank 0
E8H, bank 0
E9H, bank 0

SIO1CON
SIO1DATA
SIO1PS

EAH, bank 0
EBH, bank 0
ECH, bank 0

UART0CON
UDATA0
BRDATA0

00H, Page 0
01H, Page 0
02H, Page 0

UART 1 data transmit
UART 1 data receive

UART1CON
UDATA1
BRDATA1

03H, Page 0
04H, Page 0
05H, Page 0

Watch timer

WTCON

E6H, bank 0

Timer 2 match

SIO0

IRQ2

SIO1

UART 0 data transmit
UART 0 data receive

IRQ3

P1.0 external interrupt
P1.1 external interrupt
P1.2 external interrupt
P1.3 external interrupt

IRQ4

P1CONL
P1INT
P1PND

E5H, bank 1
E6H, bank 1
E3H, bank 1

P1.4 external interrupt
P1.5 external interrupt
P1.6 external interrupt
P1.7 external interrupt

IRQ5

P1CONH
P1INT
P0PND

E4H, bank 1
E6H, bank 1
E3H, bank 1

CE interrupt

IRQ6

PLLMOD
PLLREF
PLLD1, PLLD0

F7H, bank 0
F4H, bank 0
F5H, bank 0

IF interrupt

IRQ7

IFMOD, IFCNT2
IFCNT1, IFCNT0
PLLMOD, PLLREF

F6H, F1H, bank 1
F2H, F3H, bank 1
F7H, F8H, bank 1

NOTE: If an interrupt is un-mask (Enable interrupt level) in the IMR register, the pending bit and enable bit of the interrupt
should be written after a DI instruction is executed.

5-9

INTERRUPT STRUCTURE

S3F833B/F834B_UM_REV1.10

SYSTEM MODE REGISTER (SYM)
The system mode register, SYM (set 1, DEH), is used to globally enable and disable interrupt processing and to
control fast interrupt processing (see Figure 5-5).
A reset clears SYM.1, and SYM.0 to &quot; 0 &quot; . The 3-bit value for fast interrupt level selection, SYM.4-SYM.2, is
undetermined.
The instructions EI and DI enable and disable global interrupt processing, respectively, by modifying the bit 0
value of the SYM register. In order to enable interrupt processing an Enable Interrupt (EI) instruction must be
included in the initialization routine, which follows a reset operation. Although you can manipulate SYM.0 directly
to enable and disable interrupts during the normal operation, it is recommended to use the EI and DI instructions
for this purpose.

System Mode Register (SYM)
DEH, Set 1, R/W
MSB

.7

.6

.5

.4

.3

Always logic &quot; 0 &quot;
Not used
Fast interrupt level
selection bits: (1)
0 0 0 = IRQ0
0 0 1 = IRQ1
0 1 0 = IRQ2
0 1 1 = IRQ3
1 0 0 = IRQ4
1 0 1 = IRQ5
1 1 0 = IRQ6
1 1 1 = IRQ7

.2

.1

.0

LSB

Global interrupt enable bit: (3)
0 = Disable all interrupts processing
1 = Enable all interrupts processing
Fast interrupt enable bit: (2)
0 = Disable fast interrupts processing
1 = Enable fast interrupts processing

NOTES:
1. You can select only one interrupt level at a time for fast interrupt processing.
2. Setting SYM.1 to &quot; 1 &quot; enables fast interrupt processing for the interrupt processing for the
interrupt level currently selected by SYM.2-SYM.4.
3. Following a reset, you must enable global interrupt processing by executing EI instruction
(not by writing a &quot; 1 &quot; to SYM.0)

Figure 5-5. System Mode Register (SYM)

5-10

S3F833B/F834B_UM_REV1.10

INTERRUPT STRUCTURE

INTERRUPT MASK REGISTER (IMR)
The interrupt mask register, IMR (set 1, DDH) is used to enable or disable interrupt processing for individual
interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required
settings by the initialization routine.
Each IMR bit corresponds to a specific interrupt level: bit 1 to IRQ1, bit 2 to IRQ2, and so on. When the IMR bit of
an interrupt level is cleared to &quot; 0 &quot; , interrupt processing for that level is disabled (masked). When you set a level's
IMR bit to &quot; 1 &quot; , interrupt processing for the level is enabled (not masked).
The IMR register is mapped to register location DDH in set 1. Bit values can be read and written by instructions
using the Register addressing mode.

Interrupt Mask Register (IMR)
DDH, Set 1, R/W
MSB

.7

.6

.5

.4

.3

.2

IRQ2

IRQ7

NOTE:

IRQ6

IRQ5

IRQ4

.1

IRQ1

.0

LSB

IRQ0

IRQ3
Interrupt level enable :
0 = Disable (mask) interrupt level
1 = Enable (un-mask) interrupt level

Before IMR register is changed to any value, all interrupts must be disable.
Using DI instruction is recommended.

Figure 5-6. Interrupt Mask Register (IMR)

5-11

INTERRUPT STRUCTURE

S3F833B/F834B_UM_REV1.10

INTERRUPT PRIORITY REGISTER (IPR)
The interrupt priority register, IPR (set 1, bank 0, FFH), is used to set the relative priorities of the interrupt levels in
the microcontroller's interrupt structure. After a reset, all IPR bit values are undetermined and must therefore be
written to their required settings by the initialization routine.
When more than one interrupt sources are active, the source with the highest priority level is serviced first. If two
sources belong to the same interrupt level, the source with the lower vector address usually has the priority (This
priority is fixed in hardware).
To support programming of the relative interrupt level priorities, they are organized into groups and subgroups by
the interrupt logic. Please note that these groups (and subgroups) are used only by IPR logic for the IPR register
priority definitions (see Figure 5-7):
Group A

IRQ0, IRQ1

Group B

IRQ2, IRQ3, IRQ4

Group C

IRQ5, IRQ6, IRQ7

IPR
Group A

A1

IPR
Group B

A2

B1

IPR
Group C

B2
B21

IRQ0

IRQ1

IRQ2 IRQ3

C1
B22

IRQ4

C2
C21

IRQ5 IRQ6

C22
IRQ7

Figure 5-7. Interrupt Request Priority Groups
As you can see in Figure 5-8, IPR.7, IPR.4, and IPR.1 control the relative priority of interrupt groups A, B, and C.
For example, the setting &quot; 001B &quot; for these bits would select the group relationship B &amp; gt; C &amp; gt; A. The setting &quot; 101B &quot;
would select the relationship C &amp; gt; B &amp; gt; A.
The functions of the other IPR bit settings are as follows:
-- IPR.5 controls the relative priorities of group C interrupts.
-- Interrupt group C includes a subgroup that has an additional priority relationship among the interrupt levels 5,
6, and 7. IPR.6 defines the subgroup C relationship. IPR.5 controls the interrupt group C.
-- IPR.0 controls the relative priority setting of IRQ0 and IRQ1 interrupts.

5-12

S3F833B/F834B_UM_REV1.10

INTERRUPT STRUCTURE

Interrupt Priority Register (IPR)
FFH, Set 1, Bank 0, R/W
MSB

.7

.6

.5

.4

.3

.2

.1

.0

Group priority:

Group A:
0 = IRQ0 &amp; gt; IRQ1
1 = IRQ1 &amp; gt; IRQ0

D7 D4 D1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

LSB

= Undefined
=B &amp; gt; C &amp; gt; A
=A &amp; gt; B &amp; gt; C
=B &amp; gt; A &amp; gt; C
=C &amp; gt; A &amp; gt; B
=C &amp; gt; B &amp; gt; A
=A &amp; gt; C &amp; gt; B
= Undefined

Group B:
0 = IRQ2 &amp; gt; (IRQ3, IRQ4)
1 = (IRQ3, IRQ4) &amp; gt; IRQ2
Subgroup B:
0 = IRQ3 &amp; gt; IRQ4
1 = IRQ4 &amp; gt; IRQ3
Group C:
0 = IRQ5 &amp; gt; (IRQ6, IRQ7)
1 = (IRQ6, IRQ7) &amp; gt; IRQ5
Subgroup C:
0 = IRQ6 &amp; gt; IRQ7
1 = IRQ7 &amp; gt; IRQ6

Figure 5-8. Interrupt Priority Register (IPR)

5-13

INTERRUPT STRUCTURE

S3F833B/F834B_UM_REV1.10

INTERRUPT REQUEST REGISTER (IRQ)
You can poll bit values in the interrupt request register, IRQ (set 1, DCH), to monitor interrupt request status for all
levels in the microcontroller's interrupt structure. Each bit corresponds to the interrupt level of the same number:
bit 0 to IRQ0, bit 1 to IRQ1, and so on. A &quot; 0 &quot; indicates that no interrupt request is currently being issued for that
level. A &quot; 1 &quot; indicates that an interrupt request has been generated for that level.
IRQ bit values are read-only addressable using Register addressing mode. You can read (test) the contents of the
IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific
interrupt levels. After a reset, all IRQ status bits are cleared to "0".
You can poll IRQ register values even if a DI instruction has been executed (that is, if global interrupt processing
is disabled). If an interrupt occurs while the interrupt structure is disabled, the CPU will not service it. You can,
however, still detect the interrupt request by polling the IRQ register. In this way, you can determine which events
occurred while the interrupt structure was globally disabled.

Interrupt Request Register (IRQ)
DCH, Set 1, Read-only
MSB

.7

IRQ7

.6

IRQ6

.5

IRQ5

.4

IRQ4

.3

IRQ3

.2

IRQ2

.1

IRQ1

.0

IRQ0

Interrupt level request pending bits:
0 = Interrupt level is not pending
1 = Interrupt level is pending

Figure 5-9. Interrupt Request Register (IRQ)

5-14

LSB

S3F833B/F834B_UM_REV1.10

INTERRUPT STRUCTURE

INTERRUPT PENDING FUNCTION TYPES
Overview
There are two types of interrupt pending bits: one type that is automatically cleared by hardware after the interrupt
service routine is acknowledged and executed; the other that must be cleared in the interrupt service routine.
Pending Bits Cleared Automatically by Hardware
For interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding
pending bit to &quot; 1 &quot; when a request occurs. It then issues an IRQ pulse to inform the CPU that an interrupt is waiting
to be serviced. The CPU acknowledges the interrupt source by sending an IACK, executes the service routine,
and clears the pending bit to &quot; 0 &quot; . This type of pending bit is not mapped and cannot, therefore, be read or written
by application software.
In the S3F833B/F834B interrupt structure, the timer A overflow interrupt (IRQ0) belongs to this category of
interrupts in which pending condition is cleared automatically by hardware.
Pending Bits Cleared by the Service Routine
The second type of pending bit is the one that should be cleared by program software. The service routine must
clear the appropriate pending bit before a return-from-interrupt subroutine (IRET) occurs. To do this, a &quot; 0 &quot; must be
written to the corresponding pending bit location in the source's mode or control register.

Programming Tip -- How to clear an interrupt pending bit
As the following examples are shown, a load instruction should be used to clear an interrupt pending bit.
Examples:

1.

SB1
LD

P1PND, #11111011B

; Clear P1.2's interrupt pending bit

INTPND, #11111101B

; Clear timer 0 match/capture interrupt pending bit

o
o
o

IRET
2.

SB0
LD
o
o
o

IRET

5-15

INTERRUPT STRUCTURE

S3F833B/F834B_UM_REV1.10

INTERRUPT SOURCE POLLING SEQUENCE
The interrupt request polling and servicing sequence is as follows:
1. A source generates an interrupt request by setting the interrupt request bit to &quot; 1 &quot; .
2. The CPU polling procedure identifies a pending condition for that source.
3. The CPU checks the source's interrupt level.
4. The CPU generates an interrupt acknowledge signal.
5. Interrupt logic determines the interrupt's vector address.
6. The service routine starts and the source's pending bit is cleared to &quot; 0 &quot; (by hardware or by software).
7. The CPU continues polling for interrupt requests.

INTERRUPT SERVICE ROUTINES
Before an interrupt request is serviced, the following conditions must be met:
-- Interrupt processing must be globally enabled (EI, SYM.0 = &quot; 1 &quot; )
-- The interrupt level must be enabled (IMR register)
-- The interrupt level must have the highest priority if more than one levels are currently requesting service
-- The interrupt must be enabled at the interrupt's source (peripheral control register)
When all the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle.
The CPU then initiates an interrupt machine cycle that completes the following processing sequence:
1. Reset (clear to &quot; 0 &quot; ) the interrupt enable bit in the SYM register (SYM.0) to disable all subsequent interrupts.
2. Save the program counter (PC) and status flags to the system stack.
3. Branch to the interrupt vector to fetch the address of the service routine.
4. Pass control to the interrupt service routine.
When the interrupt service routine is completed, the CPU issues an Interrupt Return (IRET). The IRET restores
the PC and status flags, setting SYM.0 to &quot; 1 &quot; . It allows the CPU to process the next interrupt request.

5-16

S3F833B/F834B_UM_REV1.10

INTERRUPT STRUCTURE

GENERATING INTERRUPT VECTOR ADDRESSES
The interrupt vector area in the ROM (00H-FFH) contains the addresses of interrupt service routines that
correspond to each level in the interrupt structure. Vectored interrupt processing follows this sequence:
1. Push the program counter's low-byte value to the stack.
2. Push the program counter's high-byte value to the stack.
3. Push the FLAG register values to the stack.
4. Fetch the service routine's high-byte address from the vector location.
5. Fetch the service routine's low-byte address from the vector location.
6. Branch to the service routine specified by the concatenated 16-bit vector address.
NOTE
A 16-bit vector address always begins at an even-numbered ROM address within the range of 00H-FFH.

NESTING OF VECTORED INTERRUPTS
It is possible to nest a higher-priority interrupt request while a lower-priority request is being serviced. To do this,
you must follow these steps:
1. Push the current 8-bit interrupt mask register (IMR) value to the stack (PUSH IMR).
2. Load the IMR register with a new mask value that enables only the higher priority interrupt.
3. Execute an EI instruction to enable interrupt processing (a higher priority interrupt will be processed if it
occurs).
4. When the lower-priority interrupt service routine ends, restore the IMR to its original value by returning the
previous mask value from the stack (POP IMR).
5. Execute an IRET.
Depending on the application, you may be able to simplify the procedure above to some extent.
INSTRUCTION POINTER (IP)
The instruction pointer (IP) is adopted by all the S3F8-series microcontrollers to control the optional high-speed
interrupt processing feature called fast interrupts. The IP consists of register pair DAH and DBH. The names of IP
registers are IPH (high byte, IP15-IP8) and IPL (low byte, IP7-IP0).
FAST INTERRUPT PROCESSING
The feature called fast interrupt processing allows an interrupt within a given level to be completed in
approximately 6 clock cycles rather than the usual 16 clock cycles. To select a specific interrupt level for fast
interrupt processing, you write the appropriate 3-bit value to SYM.4-SYM.2. Then, to enable fast interrupt
processing for the selected level, you set SYM.1 to "1".

5-17

INTERRUPT STRUCTURE

S3F833B/F834B_UM_REV1.10

FAST INTERRUPT PROCESSING (Continued)
Two other system registers support fast interrupt processing:
-- The instruction pointer (IP) contains the starting address of the service routine (and is later used to swap the
program counter values), and
-- When a fast interrupt occurs, the contents of the FLAGS register is stored in an unmapped, dedicated register
called FLAGS' ("FLAGS prime").
NOTE
For the S3F833B/F834B microcontroller, the service routine for any one of the eight interrupt levels:
IRQ0-IRQ7, can be selected for fast interrupt processing.
Procedure for Initiating Fast Interrupts
To initiate fast interrupt processing, follow these steps:
1. Load the start address of the service routine into the instruction pointer (IP).
2. Load the interrupt level number (IRQn) into the fast interrupt selection field (SYM.4-SYM.2)
3. Write a &quot; 1 &quot; to the fast interrupt enable bit in the SYM register.
Fast Interrupt Service Routine
When an interrupt occurs in the level selected for fast interrupt processing, the following events occur:
1. The contents of the instruction pointer and the PC are swapped.
2. The FLAG register values are written to the FLAGS' ("FLAGS prime") register.
3. The fast interrupt status bit in the FLAGS register is set.
4. The interrupt is serviced.
5. Assuming that the fast interrupt status bit is set, when the fast interrupt service routine ends, the instruction
pointer and PC values are swapped back.
6. The content of FLAGS' ("FLAGS prime") is copied automatically back to the FLAGS register.
7. The fast interrupt status bit in FLAGS is cleared automatically.
Relationship to Interrupt Pending Bit Types
As described previously, there are two types of interrupt pending bits: One type that is automatically cleared by
hardware after the interrupt service routine is acknowledged and executed; the other that must be cleared by the
application program's interrupt service routine. You can select fast interrupt processing for interrupts with either
type of pending condition clear function -- by hardware or by software.
Programming Guidelines
Remember that the only way to enable/disable a fast interrupt is to set/clear the fast interrupt enable bit in the
SYM register, SYM.1. Executing an EI or DI instruction globally enables or disables all interrupt processing,
including fast interrupts. If you use fast interrupts, remember to load the IP with a new start address when the fast
interrupt service routine ends.

5-18

S3F833B/F834B_UM_REV1.10

6

INSTRUCTION SET

INSTRUCTION SET

OVERVIEW
The SAM8 instruction set is specifically designed to support the large register files that are typical of most SAM8
microcontrollers. There are 78 instructions. The powerful data manipulation capabilities and features of the
instruction set include:
-- A full complement of 8-bit arithmetic and logic operations, including multiply and divide
-- No special I/O instructions (I/O control/data registers are mapped directly into the register file)
-- Decimal adjustment included in binary-coded decimal (BCD) operations
-- 16-bit (word) data can be incremented and decremented
-- Flexible instructions for bit addressing, rotate, and shift operations

DATA TYPES
The SAM8 CPU performs operations on bits, bytes, BCD digits, and two-byte words. Bits in the register file can
be set, cleared, complemented, and tested. Bits within a byte are numbered from 7 to 0, where bit 0 is the least
significant (right-most) bit.
REGISTER ADDRESSING
To access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is
specified. Paired registers can be used to construct 16-bit data or 16-bit program memory or data memory
addresses. For detailed information about register addressing, please refer to Section 2, &quot; Address Spaces. &quot;
ADDRESSING MODES
There are seven explicit addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA), Relative
(RA), Immediate (IM), and Indirect (IA). For detailed descriptions of these addressing modes, please refer to
Section 3, &quot; Addressing Modes. &quot;

6-1

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

Table 6-1. Instruction Group Summary
Mnemonic

Operands

Instruction

Load Instructions
CLR

dst

Clear

LD

dst,src

Load

LDB

dst,src

Load bit

LDE

dst,src

Load external data memory

LDC

dst,src

Load program memory

LDED

dst,src

Load external data memory and decrement

LDCD

dst,src

Load program memory and decrement

LDEI

dst,src

Load external data memory and increment

LDCI

dst,src

Load program memory and increment

LDEPD

dst,src

Load external data memory with pre-decrement

LDCPD

dst,src

Load program memory with pre-decrement

LDEPI

dst,src

Load external data memory with pre-increment

LDCPI

dst,src

Load program memory with pre-increment

LDW

dst,src

Load word

POP

dst

Pop from stack

POPUD

dst,src

Pop user stack (decrementing)

POPUI

dst,src

Pop user stack (incrementing)

PUSH

src

Push to stack

PUSHUD

dst,src

Push user stack (decrementing)

PUSHUI

dst,src

Push user stack (incrementing)

6-2

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

Table 6-1. Instruction Group Summary (Continued)
Mnemonic

Operands

Instruction

Arithmetic Instructions
ADC

dst,src

Add with carry

ADD

dst,src

Add

CP

dst,src

Compare

DA

dst

Decimal adjust

DEC

dst

Decrement

DECW

dst

Decrement word

DIV

dst,src

Divide

INC

dst

Increment

INCW

dst

Increment word

MULT

dst,src

Multiply

SBC

dst,src

Subtract with carry

SUB

dst,src

Subtract

AND

dst,src

Logical AND

COM

dst

Complement

OR

dst,src

Logical OR

XOR

dst,src

Logical exclusive OR

Logic Instructions

6-3

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

Table 6-1. Instruction Group Summary (Continued)
Mnemonic

Operands

Instruction

Program Control Instructions
BTJRF

dst,src

Bit test and jump relative on false

BTJRT

dst,src

Bit test and jump relative on true

CALL

dst

Call procedure

CPIJE

dst,src

Compare, increment and jump on equal

CPIJNE

dst,src

Compare, increment and jump on non-equal

DJNZ

r,dst

Decrement register and jump on non-zero

ENTER

Enter

EXIT

Exit

IRET

Interrupt return

JP

cc,dst

Jump on condition code

JP

dst

Jump unconditional

JR

cc,dst

Jump relative on condition code

NEXT

Next

RET

Return

WFI

Wait for interrupt

Bit Manipulation Instructions
BAND

dst,src

Bit AND

BCP

dst,src

Bit compare

BITC

dst

Bit complement

BITR

dst

Bit reset

BITS

dst

Bit set

BOR

dst,src

Bit OR

BXOR

dst,src

Bit XOR

TCM

dst,src

Test complement under mask

TM

dst,src

Test under mask

6-4

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

Table 6-1. Instruction Group Summary (Concluded)
Mnemonic

Operands

Instruction

Rotate and Shift Instructions
RL

dst

Rotate left

RLC

dst

Rotate left through carry

RR

dst

Rotate right

RRC

dst

Rotate right through carry

SRA

dst

Shift right arithmetic

SWAP

dst

Swap nibbles

CPU Control Instructions
CCF

Complement carry flag

DI

Disable interrupts

EI

Enable interrupts

IDLE

Enter Idle mode

NOP

No operation

RCF

Reset carry flag

SB0

Set bank 0

SB1

Set bank 1

SCF

Set carry flag

SRP

src

Set register pointers

SRP0

src

Set register pointer 0

SRP1

src

Set register pointer 1

STOP

Enter Stop mode

6-5

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

FLAGS REGISTER (FLAGS)
The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these
bits, FLAGS.7-FLAGS.4, can be tested and used with conditional jump instructions; two others FLAGS.3 and
FLAGS.2 are used for BCD arithmetic.
The FLAGS register also contains a bit to indicate the status of fast interrupt processing (FLAGS.1) and a bank
address status bit (FLAGS.0) to indicate whether bank 0 or bank 1 is currently being addressed. FLAGS register
can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction.
Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags register. For
example, the AND instruction updates the Zero, Sign and Overflow flags based on the outcome of the AND
instruction. If the AND instruction uses the Flags register as the destination, then simultaneously, two write will
occur to the Flags register producing an unpredictable result.

System Flags Register (FLAGS)
D5H, Set 1, R/W
MSB

.7

.6

.5

.4

.3

.2

.1

.0

Bank address
status flag (BA)

Carry flag (C)

First interrupt
status flag (FIS)

Zero flag (Z)

Sign flag (S)

Overflow (V)

Half-carry flag (H)

Decimal adjust flag (D)

Figure 6-1. System Flags Register (FLAGS)

6-6

LSB

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

FLAG DESCRIPTIONS

C

Carry Flag (FLAGS.7)
The C flag is set to &quot; 1 &quot; if the result from an arithmetic operation generates a carry-out from or a borrow to
the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the
specified register. Program instructions can set, clear, or complement the carry flag.

Z

Zero Flag (FLAGS.6)
For arithmetic and logic operations, the Z flag is set to &quot; 1 &quot; if the result of the operation is zero. For
operations that test register bits, and for shift and rotate operations, the Z flag is set to &quot; 1 &quot; if the result is
logic zero.

S

Sign Flag (FLAGS.5)
Following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the MSB of the
result. A logic zero indicates a positive number and a logic one indicates a negative number.

V

Overflow Flag (FLAGS.4)
The V flag is set to &quot; 1 &quot; when the result of a two's-complement operation is greater than + 127 or less than
- 128. It is also cleared to &quot; 0 &quot; following logic operations.

D

Decimal Adjust Flag (FLAGS.3)
The DA bit is used to specify what type of instruction was executed last during BCD operations, so that a
subsequent decimal adjust operation can execute correctly. The DA bit is not usually accessed by
programmers, and cannot be used as a test condition.

H

Half-Carry Flag (FLAGS.2)
The H bit is set to &quot; 1 &quot; whenever an addition generates a carry-out of bit 3, or when a subtraction borrows
out of bit 4. It is used by the Decimal Adjust (DA) instruction to convert the binary result of a previous
addition or subtraction into the correct decimal (BCD) result. The H flag is seldom accessed directly by a
program.

FIS

Fast Interrupt Status Flag (FLAGS.1)
The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing.
When set, it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET
instruction is executed.

BA

Bank Address Flag (FLAGS.0)
The BA flag indicates which register bank in the set 1 area of the internal register file is currently selected,
bank 0 or bank 1. The BA flag is cleared to &quot; 0 &quot; (select bank 0) when you execute the SB0 instruction and
is set to &quot; 1 &quot; (select bank 1) when you execute the SB1 instruction.

6-7

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET NOTATION
Table 6-2. Flag Notation Conventions
Flag

Description

C

Carry flag

Z

Zero flag

S

Sign flag

V

Overflow flag

D

Decimal-adjust flag

H

Half-carry flag

0

Cleared to logic zero

1

Set to logic one

*

Set or cleared according to operation

-

Value is unaffected

x

Value is undefined

Table 6-3. Instruction Set Symbols
Symbol

Description

dst

Destination operand

src

Source operand

@

Indirect register address prefix

PC

Program counter

IP

Instruction pointer

FLAGS
RP

Flags register (D5H)
Register pointer

#

Immediate operand or register address prefix

H

Hexadecimal number suffix

D

Decimal number suffix

B

Binary number suffix

opc

6-8

Opcode

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

Table 6-4. Instruction Notation Conventions
Notation
cc

Description

Actual Operand Range

Condition code

See list of condition codes in Table 6-6.

r

Working register only

Rn (n = 0-15)

rb

Bit (b) of working register

Rn.b (n = 0-15, b = 0-7)

r0

Bit 0 (LSB) of working register

Rn (n = 0-15)

rr

Working register pair

RRp (p = 0, 2, 4, ..., 14)

R

Register or working register

reg or Rn (reg = 0-255, n = 0-15)

Rb

Bit 'b' of register or working register

reg.b (reg = 0-255, b = 0-7)

RR

Register pair or working register pair

reg or RRp (reg = 0-254, even number only, where
p = 0, 2, ..., 14)

IA

Indirect addressing mode

addr (addr = 0-254, even number only)

Ir

Indirect working register only

@Rn (n = 0-15)

IR

Indirect register or indirect working register @Rn or @reg (reg = 0-255, n = 0-15)

Irr

Indirect working register pair only

@RRp (p = 0, 2, ..., 14)

Indirect register pair or indirect working
register pair

@RRp or @reg (reg = 0-254, even only, where
p = 0, 2, ..., 14)

Indexed addressing mode

#reg [Rn] (reg = 0-255, n = 0-15)

XS

Indexed (short offset) addressing mode

#addr [RRp] (addr = range -128 to +127, where
p = 0, 2, ..., 14)

xl

Indexed (long offset) addressing mode

#addr [RRp] (addr = range 0-65535, where
p = 0, 2, ..., 14)

da

Direct addressing mode

addr (addr = range 0-65535)

ra

Relative addressing mode

addr (addr = number in the range +127 to -128 that is
an offset relative to the address of the next instruction)

im

Immediate addressing mode

#data (data = 0-255)

iml

Immediate (long) addressing mode

#data (data = range 0-65535)

IRR
X

6-9

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

Table 6-5. Opcode Quick Reference
OPCODE MAP
LOWER NIBBLE (HEX)
-

0

1

2

3

4

5

6

7

U

0

DEC
R1

DEC
IR1

ADD
r1,r2

ADD
r1,Ir2

ADD
R2,R1

ADD
IR2,R1

ADD
R1,IM

BOR
r0-Rb

P

1

RLC
R1

RLC
IR1

ADC
r1,r2

ADC
r1,Ir2

ADC
R2,R1

ADC
IR2,R1

ADC
R1,IM

BCP
r1.b, R2

P

2

INC
R1

INC
IR1

SUB
r1,r2

SUB
r1,Ir2

SUB
R2,R1

SUB
IR2,R1

SUB
R1,IM

BXOR
r0-Rb

E

3

JP
IRR1

SRP/0/1
IM

SBC
r1,r2

SBC
r1,Ir2

SBC
R2,R1

SBC
IR2,R1

SBC
R1,IM

BTJR
r2.b, RA

R

4

DA
R1

DA
IR1

OR
r1,r2

OR
r1,Ir2

OR
R2,R1

OR
IR2,R1

OR
R1,IM

LDB
r0-Rb

5

POP
R1

POP
IR1

AND
r1,r2

AND
r1,Ir2

AND
R2,R1

AND
IR2,R1

AND
R1,IM

BITC
r1.b

N

6

COM
R1

COM
IR1

TCM
r1,r2

TCM
r1,Ir2

TCM
R2,R1

TCM
IR2,R1

TCM
R1,IM

BAND
r0-Rb

I

7

PUSH
R2

PUSH
IR2

TM
r1,r2

TM
r1,Ir2

TM
R2,R1

TM
IR2,R1

TM
R1,IM

BIT
r1.b

B

8

DECW
RR1

DECW
IR1

PUSHUD
IR1,R2

PUSHUI
IR1,R2

MULT
R2,RR1

MULT
IR2,RR1

MULT
IM,RR1

LD
r1, x, r2

B

9

RL
R1

RL
IR1

POPUD
IR2,R1

POPUI
IR2,R1

DIV
R2,RR1

DIV
IR2,RR1

DIV
IM,RR1

LD
r2, x, r1

L

A

INCW
RR1

INCW
IR1

CP
r1,r2

CP
r1,Ir2

CP
R2,R1

CP
IR2,R1

CP
R1,IM

LDC
r1, Irr2, xL

E

B

CLR
R1

CLR
IR1

XOR
r1,r2

XOR
r1,Ir2

XOR
R2,R1

XOR
IR2,R1

XOR
R1,IM

LDC
r2, Irr2, xL

C

RRC
R1

RRC
IR1

CPIJE
Ir,r2,RA

LDC
r1,Irr2

LDW
RR2,RR1

LDW
IR2,RR1

LDW
RR1,IML

LD
r1, Ir2

H

D

SRA
R1

SRA
IR1

CPIJNE
Irr,r2,RA

LDC
r2,Irr1

CALL
IA1

LD
IR1,IM

LD
Ir1, r2

E

E

RR
R1

RR
IR1

LDCD
r1,Irr2

LDCI
r1,Irr2

LD
R2,R1

LD
R2,IR1

LD
R1,IM

LDC
r1, Irr2, xs

X

F

SWAP
R1

SWAP
IR1

LDCPD
r2,Irr1

LDCPI
r2,Irr1

CALL
IRR1

LD
IR2,R1

CALL
DA1

LDC
r2, Irr1, xs

6-10

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

Table 6-5. Opcode Quick Reference (Continued)
OPCODE MAP
LOWER NIBBLE (HEX)
-

8

9

A

B

C

D

E

F

U

0

LD
r1,R2

LD
r2,R1

DJNZ
r1,RA

JR
cc,RA

LD
r1,IM

JP
cc,DA

INC
r1

NEXT

P

1

?

?

?

?

?

?

?

ENTER

P

2

EXIT

E

3

WFI

R

4

SB0

5

SB1

N

6

IDLE

I

7

B

8

DI

B

9

EI

L

A

RET

E

B

IRET

C

RCF

H

D

E

F

?

?

?

?

?

?

?

?

?

?

?

?

?

E

X

?

STOP

SCF
CCF

LD
r1,R2

LD
r2,R1

DJNZ
r1,RA

JR
cc,RA

LD
r1,IM

JP
cc,DA

INC
r1

NOP

6-11

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

CONDITION CODES
The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under
which conditions it is to execute the jump. For example, a conditional jump with the condition code for &quot; equal &quot;
after a compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6.
The carry (C), zero (Z), sign (S), and overflow (V) flags are used to control the operation of conditional jump
instructions.
Table 6-6. Condition Codes
Binary
0000

Mnemonic

Description

Flags Set

F

1000

Always false

-

T

Always true

-

0111

(note)

C

Carry

C=1

1111

(note)

NC

No carry

C=0

0110

(note)

Z

Zero

Z=1

1110

(note)

NZ

Not zero

Z=0

1101

PL

Plus

S=0

0101

MI

Minus

S=1

0100

OV

Overflow

V=1

1100

NOV

No overflow

V=0

(note)

EQ

Equal

Z=1

1110 (note)

NE

Not equal

Z=0

1001

GE

Greater than or equal

(S

XOR

V) = 0

0001

LT

Less than

(S

XOR

V) = 1

1010

GT

Greater than

(Z

OR (S

XOR

V)) = 0

0010

LE

Less than or equal

(Z

OR (S

XOR

V)) = 1

1111 (note)

UGE

Unsigned greater than or equal

C=0

0111 (note)

ULT

Unsigned less than

C=1

1011

UGT

Unsigned greater than

(C = 0

0011

ULE

Unsigned less than or equal

(C

0110

OR

AND

Z = 0) = 1

Z) = 1

NOTES:
1. It indicates condition codes that are related to two different mnemonics but which test the same flag. For
example, Z and EQ are both true if the zero flag (Z) is set, but after an ADD instruction, Z would probably be used;
after a CP instruction, however, EQ would probably be used.
2. For operations involving unsigned numbers, the special condition codes UGE, ULT, UGT, and ULE must be used.

6-12

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

INSTRUCTION DESCRIPTIONS
This section contains detailed information and programming examples for each instruction in the SAM8
instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The
following information is included in each instruction description:
-- Instruction name (mnemonic)
-- Full instruction name
-- Source/destination format of the instruction operand
-- Shorthand notation of the instruction's operation
-- Textual description of the instruction's effect
-- Specific flag settings affected by the instruction
-- Detailed description of the instruction's format, execution time, and addressing mode(s)
-- Programming example(s) explaining how to use the instruction

6-13

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

ADC -- Add with carry
ADC

dst,src

Operation:

dst

<-

dst

+

src

+

c

The source operand, along with the setting of the carry flag, is added to the destination operand
and the sum is stored in the destination. The contents of the source are unaffected. Two'scomplement addition is performed. In multiple precision arithmetic, this instruction permits the
carry from the addition of low-order operands to be carried into the addition of high-order
operands.
Flags:

C:
Z:
S:
V:

Set if there is a carry from the most significant bit of the result; cleared otherwise.
Set if the result is &quot; 0 &quot; ; cleared otherwise.
Set if the result is negative; cleared otherwise.
Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result
is of the opposite sign; cleared otherwise.
D: Always cleared to &quot; 0 &quot; .
H: Set if there is a carry from the most significant bit of the low-order four bits of the result;
cleared otherwise.

Format:
Bytes
2

4

12

r

r

13

r

lr

6

14

R

R

6

15

R

IR

6

16

R

IM

dst | src

opc

src

opc

Examples:

Opcode
(Hex)

6

opc

Cycles

dst

dst

3

src

3

Addr Mode
src
dst

Given: R1 = 10H, R2 = 03H, C flag = &quot; 1 &quot; , register 01H = 20H, register 02H = 03H, and register
03H = 0AH:
ADC

R1,R2

->

R1

=

14H, R2

=

03H

ADC

R1,@R2

->

R1

=

1BH, R2

=

03H

ADC

01H,02H

->

Register 01H

=

24H, register 02H

=

03H

ADC

01H,@02H

->

Register 01H

=

2BH, register 02H

=

03H

ADC

01H,#11H

->

Register 01H

=

32H

In the first example, destination register R1 contains the value 10H, the carry flag is set to &quot; 1 &quot; ,
and the source working register R2 contains the value 03H. The statement &quot; ADC R1,R2 &quot; adds
03H and the carry flag value ( &quot; 1 &quot; ) to the destination value 10H, leaving 14H in register R1.

6-14

S3F833B/F834B_UM_REV1.10

ADD

INSTRUCTION SET

-- Add

ADD

dst,src

Operation:

dst

<-

dst

+

src

The source operand is added to the destination operand and the sum is stored in the destination.
The contents of the source are unaffected. Two's-complement addition is performed.
Flags:

C:
Z:
S:
V:

Set if there is a carry from the most significant bit of the result; cleared otherwise.
Set if the result is &quot; 0 &quot; ; cleared otherwise.
Set if the result is negative; cleared otherwise.
Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the
result is of the opposite sign; cleared otherwise.
D: Always cleared to &quot; 0 &quot; .
H: Set if a carry from the low-order nibble occurred.

Format:
Bytes
2

4

02

r

r

03

r

lr

6

04

R

R

6

05

R

IR

6

06

R

IM

dst | src

opc

src

opc

Examples:

Opcode
(Hex)

6

opc

Cycles

dst

dst

3

src

3

Addr Mode
src
dst

Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:
ADD

R1,R2

->

R1

=

15H, R2

=

03H

ADD

R1,@R2

->

R1

=

1CH, R2

=

03H

ADD

01H,02H

->

Register 01H

=

24H, register 02H

=

03H

ADD

01H,@02H

->

Register 01H

=

2BH, register 02H

=

03H

ADD

01H,#25H

->

Register 01H

=

46H

In the first example, destination working register R1 contains 12H and the source working register
R2 contains 03H. The statement &quot; ADD R1,R2 &quot; adds 03H to 12H, leaving the value 15H in
register R1.

6-15

INSTRUCTION SET

AND

S3F833B/F834B_UM_REV1.10

-- Logical AND

AND

dst,src

Operation:

dst

<-

dst

AND

src

The source operand is logically ANDed with the destination operand. The result is stored in the
destination. The AND operation results in a &quot; 1 &quot; bit being stored whenever the corresponding bits
in the two operands are both logic ones; otherwise a &quot; 0 &quot; bit value is stored. The contents of the
source are unaffected.
Flags:

C:
Z:
S:
V:
D:
H:

Unaffected.
Set if the result is &quot; 0 &quot; ; cleared otherwise.
Set if the result bit 7 is set; cleared otherwise.
Always cleared to &quot; 0 &quot; .
Unaffected.
Unaffected.

Format:
Bytes
2

4

52

r

r

53

r

lr

6

54

R

R

6

55

R

IR

6

56

R

IM

dst | src

opc

src

opc

Examples:

Opcode
(Hex)

6

opc

Cycles

dst

dst

3

src

3

Addr Mode
src
dst

Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:
AND

R1,R2

->

R1

=

02H, R2

AND

R1,@R2

->

R1

=

02H, R2 =

AND

01H,02H

->

Register 01H

=

01H, register 02H

=

03H

AND

01H,@02H

->

Register 01H

=

00H, register 02H

=

03H

AND

01H,#25H

->

Register 01H

=

21H

=

03H
03H

In the first example, destination working register R1 contains the value 12H and the source
working register R2 contains 03H. The statement &quot; AND R1,R2 &quot; logically ANDs the source
operand 03H with the destination operand value 12H, leaving the value 02H in register R1.

6-16

S3F833B/F834B_UM_REV1.10

BAND

INSTRUCTION SET

-- Bit AND

BAND

dst,src.b

BAND

dst.b,src

Operation:

dst(0)

<-

dst(0)

AND

src(b)

dst(b)

AND

src(0)

or
dst(b)

<-

The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of
the destination (or source). The resultant bit is stored in the specified bit of the destination. No
other bits of the destination are affected. The source is unaffected.
Flags:

C:
Z:
S:
V:
D:
H:

Unaffected.
Set if the result is &quot; 0 &quot; ; cleared otherwise.
Cleared to &quot; 0 &quot; .
Undefined.
Unaffected.
Unaffected.

Format:
Bytes

Cycles

Opcode
(Hex)

Addr Mode
src
dst

opc

dst | b | 0

src

3

6

67

r0

Rb

opc

src | b | 1

dst

3

6

67

Rb

r0

NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits,
the bit address 'b' is three bits, and the LSB address value is one bit in length.

Examples:

Given: R1 = 07H and register 01H = 05H:
BAND R1,01H.1

->

R1

BAND 01H.1,R1

->

Register 01H

=

06H, register 01H =
=

05H, R1

05H
=

07H

In the first example, source register 01H contains the value 05H (00000101B) and destination
working register R1 contains 07H (00000111B). The statement &quot; BAND R1,01H.1 &quot; ANDs the bit
1 value of the source register ( &quot; 0 &quot; ) with the bit 0 value of register R1 (destination), leaving the
value 06H (00000110B) in register R1.

6-17

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

BCP -- Bit Compare
BCP

dst,src.b

Operation:

dst(0) - src(b)
The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination.
The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both
operands are unaffected by the comparison.

Flags:

C:
Z:
S:
V:
D:
H:

Unaffected.
Set if the two bits are the same; cleared otherwise.
Cleared to &quot; 0 &quot; .
Undefined.
Unaffected.
Unaffected.

Format:
Bytes
opc

dst | b | 0

Cycles

Opcode
(Hex)

3

6

17

src

Addr Mode
src
dst
r0

Rb

NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b' is
three bits, and the LSB address value is one bit in length.

Example:

Given: R1
BCP

=

07H and register 01H

R1,01H.1

->

R1

=

=

01H:

07H, register 01H

=

01H

If destination working register R1 contains the value 07H (00000111B) and the source register
01H contains the value 01H (00000001B), the statement &quot; BCP R1,01H.1 &quot; compares bit one of
the source register (01H) and bit zero of the destination register (R1). Because the bit values are
not identical, the zero flag bit (Z) is cleared in the FLAGS register (0D5H).

6-18

S3F833B/F834B_UM_REV1.10

BITC

INSTRUCTION SET

-- Bit Complement

BITC

dst.b

Operation:

dst(b) <-

NOT dst(b)

This instruction complements the specified bit within the destination without affecting any other
bits in the destination.
Flags:

C:
Z:
S:
V:
D:
H:

Unaffected.
Set if the result is &quot; 0 &quot; ; cleared otherwise.
Cleared to &quot; 0 &quot; .
Undefined.
Unaffected.
Unaffected.

Format:
Bytes
opc

Opcode
(Hex)

Addr Mode
dst

2

dst | b | 0

Cycles
4

57

rb

NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b'
is three bits, and the LSB address value is one bit in length.

Example:

Given: R1
BITC

R1.1

=

07H
->

R1

=

05H

If working register R1 contains the value 07H (00000111B), the statement &quot; BITC R1.1 &quot;
complements bit one of the destination and leaves the value 05H (00000101B) in register R1.
Because the result of the complement is not &quot; 0 &quot; , the zero flag (Z) in the FLAGS register (0D5H) is
cleared.

6-19

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

BITR -- Bit Reset
BITR

dst.b

Operation:

dst(b)

<-

0

The BITR instruction clears the specified bit within the destination without affecting any other bits
in the destination.
Flags:

No flags are affected.

Format:
Bytes
opc

Opcode
(Hex)

Addr Mode
dst

2

dst | b | 0

Cycles
4

77

rb

NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b'
is three bits, and the LSB address value is one bit in length.

Example:

Given: R1
BITR

R1.1

=

07H:
->

R1

=

05H

If the value of working register R1 is 07H (00000111B), the statement &quot; BITR
one of the destination register R1, leaving the value 05H (00000101B).

6-20

R1.1 &quot; clears bit

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

BITS -- Bit Set
BITS

dst.b

Operation:

dst(b)

<-

1

The BITS instruction sets the specified bit within the destination without affecting any other bits in
the destination.
Flags:

No flags are affected.

Format:
Bytes
opc

Opcode
(Hex)

Addr Mode
dst

2

dst | b | 1

Cycles
4

77

rb

NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b'
is three bits, and the LSB address value is one bit in length.

Example:

Given: R1
BITS

R1.3

=

07H:
->

R1

=

0FH

If working register R1 contains the value 07H (00000111B), the statement &quot; BITS
three of the destination register R1 to &quot; 1 &quot; , leaving the value 0FH (00001111B).

R1.3 &quot; sets bit

6-21

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

BOR -- Bit OR
BOR

dst,src.b

BOR

dst.b,src

Operation:

dst(0)

<-

dst(0)

OR

src(b)

dst(b)

OR

src(0)

or
dst(b)

<-

The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of the
destination (or the source). The resulting bit value is stored in the specified bit of the destination.
No other bits of the destination are affected. The source is unaffected.
Flags:

C:
Z:
S:
V:
D:
H:

Unaffected.
Set if the result is &quot; 0 &quot; ; cleared otherwise.
Cleared to &quot; 0 &quot; .
Undefined.
Unaffected.
Unaffected.

Format:
Bytes

Cycles

Opcode
(Hex)

Addr Mode
src
dst

opc

dst | b | 0

src

3

6

07

r0

Rb

opc

src | b | 1

dst

3

6

07

Rb

r0

NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits,
the bit address 'b' is three bits, and the LSB address value is one bit.

Examples:

Given: R1

=

07H and register 01H

=

03H:

BOR

R1, 01H.1

->

R1 = 07H, register 01H = 03H

BOR

01H.2, R1

->

Register 01H = 07H, R1 = 07H

In the first example, destination working register R1 contains the value 07H (00000111B) and
source register 01H the value 03H (00000011B). The statement &quot; BOR R1,01H.1 &quot; logically ORs
bit one of register 01H (source) with bit zero of R1 (destination). This leaves the same value
(07H) in working register R1.
In the second example, destination register 01H contains the value 03H (00000011B) and the
source working register R1 the value 07H (00000111B). The statement &quot; BOR 01H.2,R1 &quot; logically
ORs bit two of register 01H (destination) with bit zero of R1 (source). This leaves the value 07H
in register 01H.

6-22

S3F833B/F834B_UM_REV1.10

BTJRF

INSTRUCTION SET

-- Bit Test, Jump Relative on False

BTJRF

dst,src.b

Operation:

If src(b) is a &quot; 0 &quot; , then PC

<-

PC

+

dst

The specified bit within the source operand is tested. If it is a &quot; 0 &quot; , the relative address is added to
the program counter and control passes to the statement whose address is now in the PC;
otherwise, the instruction following the BTJRF instruction is executed.
Flags:

No flags are affected.

Format:
Bytes

Cycles

Opcode
(Hex)

3

10

37

(Note 1)

opc

src | b | 0

dst

Addr Mode
src
dst
RA

rb

NOTE: In the second byte of the instruction format, the source address is four bits, the bit address 'b' is
three bits, and the LSB address value is one bit in length.

Example:

Given: R1

=

07H:

BTJRF SKIP,R1.3

->

PC jumps to SKIP location

If working register R1 contains the value 07H (00000111B), the statement &quot; BTJRF SKIP,R1.3 &quot;
tests bit 3. Because it is &quot; 0 &quot; , the relative address is added to the PC and the PC jumps to the
memory location pointed to by the SKIP. (Remember that the memory location must be within the
allowed range of + 127 to - 128.)

6-23

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

BTJRT -- Bit Test, Jump Relative on True
BTJRT

dst,src.b

Operation:

If src(b) is a &quot; 1 &quot; , then PC

<-

PC

+

dst

The specified bit within the source operand is tested. If it is a &quot; 1 &quot; , the relative address is added to
the program counter and control passes to the statement whose address is now in the PC;
otherwise, the instruction following the BTJRT instruction is executed.
Flags:

No flags are affected.

Format:
Bytes

Cycles

Opcode
(Hex)

3

10

37

(Note 1)

opc

src | b | 1

dst

Addr Mode
src
dst
RA

rb

NOTE: In the second byte of the instruction format, the source address is four bits, the bit address 'b' is
three bits, and the LSB address value is one bit in length.

Example:

Given: R1
BTJRT

=

07H:

SKIP,R1.1

If working register R1 contains the value 07H (00000111B), the statement &quot; BTJRT SKIP,R1.1 &quot;
tests bit one in the source register (R1). Because it is a &quot; 1 &quot; , the relative address is added to the
PC and the PC jumps to the memory location pointed to by the SKIP. (Remember that the
memory location must be within the allowed range of + 127 to - 128.)

6-24

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

BXOR -- Bit XOR
BXOR

dst,src.b

BXOR

dst.b,src

Operation:

dst(0)

<-

dst(0)

XOR

src(b)

dst(b)

XOR

src(0)

or
dst(b)

<-

The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB)
of the destination (or source). The result bit is stored in the specified bit of the destination. No
other bits of the destination are affected. The source is unaffected.
Flags:

C:
Z:
S:
V:
D:
H:

Unaffected.
Set if the result is &quot; 0 &quot; ; cleared otherwise.
Cleared to &quot; 0 &quot; .
Undefined.
Unaffected.
Unaffected.

Format:
Bytes

Cycles

Opcode
(Hex)

Addr Mode
src
dst

opc

dst | b | 0

src

3

6

27

r0

Rb

opc

src | b | 1

dst

3

6

27

Rb

r0

NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits,
the bit address 'b' is three bits, and the LSB address value is one bit in length.

Examples:

Given: R1

=

07H (00000111B) and register 01H

BXOR R1,01H.1

->

R1

BXOR 01H.2,R1

->

Register 01H

=

=

03H (00000011B):

06H, register 01H
=

07H, R1

=
=

03H
07H

In the first example, destination working register R1 has the value 07H (00000111B) and source
register 01H has the value 03H (00000011B). The statement &quot; BXOR R1,01H.1 &quot; exclusive-ORs
bit one of register 01H (source) with bit zero of R1 (destination). The result bit value is stored in
bit zero of R1, changing its value from 07H to 06H. The value of source register 01H is
unaffected.

6-25

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

CALL -- Call Procedure
CALL

dst

Operation:

SP
@SP
SP
@SP
PC

<-
<-
<-
<-
<-

SP - 1
PCL
SP -1
PCH
dst

The current contents of the program counter are pushed onto the top of the stack. The program
counter value used is the address of the first instruction following the CALL instruction. The
specified destination address is then loaded into the program counter and points to the first
instruction of a procedure. At the end of the procedure the return instruction (RET) can be used
to return to the original program flow. RET pops the top of the stack back into the program
counter.
Flags:

No flags are affected.

Format:
Bytes
opc

Opcode
(Hex)

Addr Mode
dst

3

dst

Cycles
14

F6

DA

opc

2

12

F4

IRR

opc
Examples:

dst
dst

2

14

D4

IA

1A47H, and SP

=

Given: R0
CALL

=

35H, R1

= 21H, PC

=

3521H
->
SP = 0000H
(Memory locations 0000H = 1AH, 0001H =
4AH is the address that follows the instruction.)

CALL

@RR0 ->

CALL

#40H

->

SP = 0000H (0000H
SP

=

=

0000H (0000H

4AH, where

1AH, 0001H
=

0002H:

=

1AH, 0001H

49H)
=

49H)

In the first example, if the program counter value is 1A47H and the stack pointer contains the
value 0002H, the statement &quot; CALL 3521H &quot; pushes the current PC value onto the top of the
stack. The stack pointer now points to memory location 0000H. The PC is then loaded with the
value 3521H, the address of the first instruction in the program sequence to be executed.
If the contents of the program counter and stack pointer are the same as in the first example, the
statement &quot; CALL @RR0 &quot; produces the same result except that the 49H is stored in stack
location 0001H (because the two-byte instruction format was used). The PC is then loaded with
the value 3521H, the address of the first instruction in the program sequence to be executed.
Assuming that the contents of the program counter and stack pointer are the same as in the first
example, if program address 0040H contains 35H and program address 0041H contains 21H, the
statement &quot; CALL #40H &quot; produces the same result as in the second example.

6-26

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

CCF -- Complement Carry Flag
CCF
Operation:

C

<-

NOT

C

The carry flag (C) is complemented. If C = &quot; 1 &quot; , the value of the carry flag is changed to logic
zero; if C = &quot; 0 &quot; , the value of the carry flag is changed to logic one.
Flags:

C: Complemented.
No other flags are affected.

Format:
Bytes

Example:

Given: The carry flag

=

Opcode
(Hex)

1

opc

Cycles
4

EF

&quot; 0 &quot; :

CCF
If the carry flag = &quot; 0 &quot; , the CCF instruction complements it in the FLAGS register (0D5H),
changing its value from logic zero to logic one.

6-27

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

CLR -- Clear
CLR

dst

Operation:

dst

<-

&quot; 0 &quot;

The destination location is cleared to &quot; 0 &quot; .
Flags:

No flags are affected.

Format:
Bytes

Examples:

Given: Register 00H

=

4FH, register 01H

=

Addr Mode
dst

2

dst

Opcode
(Hex)

4

B0

R

4

opc

Cycles

B1

IR

02H, and register 02H

CLR

00H

->

Register 00H

=

@01H ->

Register 01H

=

02H, register 02H

5EH:

00H

CLR

=

=

00H

In Register (R) addressing mode, the statement &quot; CLR 00H &quot; clears the destination register 00H
value to 00H. In the second example, the statement &quot; CLR @01H &quot; uses Indirect Register (IR)
addressing mode to clear the 02H register value to 00H.

6-28

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

COM -- Complement
COM

dst

Operation:

dst

<-

NOT

dst

The contents of the destination location are complemented (one's complement); all &quot; 1s &quot; are
changed to &quot; 0s &quot; , and vice-versa.
Flags:

C:
Z:
S:
V:
D:
H:

Unaffected.
Set if the result is &quot; 0 &quot; ; cleared otherwise.
Set if the result bit 7 is set; cleared otherwise.
Always reset to &quot; 0 &quot; .
Unaffected.
Unaffected.

Format:
Bytes

Examples:

Opcode
(Hex)

Addr Mode
dst

2

4

60

R

4

opc

Cycles

61

IR

dst

Given: R1

=

07H and register 07H

=

0F1H:

COM

R1

->

R1

=

0F8H

COM

@R1

->

R1

=

07H, register 07H

=

0EH

In the first example, destination working register R1 contains the value 07H (00000111B). The
statement &quot; COM R1 &quot; complements all the bits in R1: all logic ones are changed to logic zeros,
and vice-versa, leaving the value 0F8H (11111000B).
In the second example, Indirect Register (IR) addressing mode is used to complement the value
of destination register 07H (11110001B), leaving the new value 0EH (00001110B).

6-29

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

CP -- Compare
CP

dst,src

Operation:

dst - src
The source operand is compared to (subtracted from) the destination operand, and the
appropriate flags are set accordingly. The contents of both operands are unaffected by the
comparison.

Flags:

C:
Z:
S:
V:
D:
H:

Set if a &quot; borrow &quot; occurred (src &amp; gt; dst); cleared otherwise.
Set if the result is &quot; 0 &quot; ; cleared otherwise.
Set if the result is negative; cleared otherwise.
Set if arithmetic overflow occurred; cleared otherwise.
Unaffected.
Unaffected.

Format:
Bytes

src

opc

dst

dst

1. Given: R1
CP

02H and

R1,R2 ->

A2

r

r

A3

r

lr

6

A4

R

R

A5

R

IR

6

A6

R

IM

3

src

=

4

6

opc

Examples:

2

dst | src

Opcode
(Hex)

6

opc

Cycles

3

R2

=

Addr Mode
src
dst

03H:

Set the C and S flags

Destination working register R1 contains the value 02H and source register R2 contains the value
03H. The statement &quot; CP R1,R2 &quot; subtracts the R2 value (source/subtrahend) from the R1 value
(destination/minuend). Because a &quot; borrow &quot; occurs and the difference is negative, C and S are
&quot; 1 &quot; .
2. Given: R1 = 05H and R2 = 0AH:
CP
JP
INC
SKIP

R1,R2
UGE,SKIP
R1
LD
R3,R1

In this example, destination working register R1 contains the value 05H which is less than the
contents of the source working register R2 (0AH). The statement &quot; CP R1,R2 &quot; generates C = &quot; 1 &quot;
and the JP instruction does not jump to the SKIP location. After the statement &quot; LD R3,R1 &quot;
executes, the value 06H remains in working register R3.

6-30

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

CPIJE -- Compare, Increment, and Jump on Equal
CPIJE

dst,src,RA

Operation:

If dst - src
Ir

<-

Ir

=
+

&quot; 0 &quot; , PC

<-

PC

+

RA

1

The source operand is compared to (subtracted from) the destination operand. If the result is &quot; 0 &quot; ,
the relative address is added to the program counter and control passes to the statement whose
address is now in the program counter. Otherwise, the instruction immediately following the
CPIJE instruction is executed. In either case, the source pointer is incremented by one before the
next instruction is executed.
Flags:

No flags are affected.

Format:
Bytes
opc

src

dst

Opcode
(Hex)

3

RA

Cycles
12

C2

Addr Mode
dst
src
r

Ir

NOTE: Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken.

Example:

Given: R1

=

02H, R2

CPIJE R1,@R2,SKIP ->

=

03H, and register 03H
R2

=

=

02H:

04H, PC jumps to SKIP location

In this example, working register R1 contains the value 02H, working register R2 the value 03H,
and register 03 contains 02H. The statement &quot; CPIJE R1,@R2,SKIP &quot; compares the @R2 value
02H (00000010B) to 02H (00000010B). Because the result of the comparison is equal, the
relative address is added to the PC and the PC then jumps to the memory location pointed to by
SKIP. The source register (R2) is incremented by one, leaving a value of 04H. (Remember that
the memory location must be within the allowed range of + 127 to - 128.)

6-31

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

CPIJNE -- Compare, Increment, and Jump on Non-Equal
CPIJNE

dst,src,RA

Operation:

If dst - src
Ir

<-

Ir

&quot; 0 &quot; , PC
+

<-

PC

+

RA

1

The source operand is compared to (subtracted from) the destination operand. If the result is not
&quot; 0 &quot; , the relative address is added to the program counter and control passes to the statement
whose address is now in the program counter; otherwise the instruction following the CPIJNE
instruction is executed. In either case the source pointer is incremented by one before the next
instruction.
Flags:

No flags are affected.

Format:
Bytes
opc

src

dst

Opcode
(Hex)

3

RA

Cycles
12

D2

Addr Mode
dst
src
r

Ir

NOTE: Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken.

Example:

Given: R1

=

02H, R2

CPIJNE R1,@R2,SKIP ->

=

03H, and register 03H
R2

=

=

04H:

04H, PC jumps to SKIP location

Working register R1 contains the value 02H, working register R2 (the source pointer) the value
03H, and general register 03 the value 04H. The statement &quot; CPIJNE R1,@R2,SKIP &quot; subtracts
04H (00000100B) from 02H (00000010B). Because the result of the comparison is non-equal, the
relative address is added to the PC and the PC then jumps to the memory location pointed to by
SKIP. The source pointer register (R2) is also incremented by one, leaving a value of 04H.
(Remember that the memory location must be within the allowed range of + 127 to - 128.)

6-32

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

DA -- Decimal Adjust
DA

dst

Operation:

dst

<-

DA

dst

The destination operand is adjusted to form two 4-bit BCD digits following an addition or
subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table
indicates the operation performed. (The operation is undefined if the destination operand was not
the result of a valid addition or subtraction of BCD digits):
Instruction

Carry
Before DA

Bits 4-7
Value (Hex)

H Flag
Before DA

Bits 0-3
Value (Hex)

Number Added
to Byte

Carry
After DA

0

0-9

0

0-9

00

0

0

0-8

0

A-F

06

0

0

0-9

1

0-3

06

0

ADD

0

A-F

0

0-9

60

1

ADC

0

9-F

0

A-F

66

1

0

A-F

1

0-3

66

1

1

0-2

0

0-9

60

1

1

0-2

0

A-F

66

1

1

0-3

1

0-3

66

1

0

0-9

0

0-9

00

=

- 00

0

SUB

0

0-8

1

6-F

FA

=

- 06

0

SBC

1

7-F

0

0-9

A0

=

- 60

1

1

6-F

1

6-F

9A

=

- 66

1

Flags:

C:
Z:
S:
V:
D:
H:

Set if there was a carry from the most significant bit; cleared otherwise (see table).
Set if result is &quot; 0 &quot; ; cleared otherwise.
Set if result bit 7 is set; cleared otherwise.
Undefined.
Unaffected.
Unaffected.

Format:
Bytes
opc

dst

Cycles

Opcode
(Hex)

Addr Mode
dst

2

4

40

R

4

41

IR

6-33

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

DA -- Decimal Adjust
DA

(Continued)

Example:

Given: Working register R0 contains the value 15 (BCD), working register R1 contains
27 (BCD), and address 27H contains 46 (BCD):
ADD
DA

R1,R0
R1

;
;

C <- &quot; 0 &quot; , H <- &quot; 0 &quot; , Bits 4-7 = 3, bits 0-3 = C, R1 <- 3CH
R1 <- 3CH + 06

If addition is performed using the BCD values 15 and 27, the result should be 42. The sum is
incorrect, however, when the binary representations are added in the destination location using
standard binary arithmetic:
0001
+ 0010

0101
0111
1100=

0011

15
27
3CH

The DA instruction adjusts this result so that the correct BCD representation is obtained:
0011
+ 0000

1100
0110

0100

0010=

42

Assuming the same values given above, the statements
SUB

27H,R0 ;

C <- &quot; 0 &quot; , H <- &quot; 0 &quot; , Bits 4-7 = 3, bits 0-3 = 1

DA

@R1

@R1 <- 31-0

;

leave the value 31 (BCD) in address 27H (@R1).

6-34

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

DEC -- Decrement
DEC

dst

Operation:

dst

<-

dst - 1

The contents of the destination operand are decremented by one.
Flags:

C:
Z:
S:
V:
D:
H:

Unaffected.
Set if the result is &quot; 0 &quot; ; cleared otherwise.
Set if result is negative; cleared otherwise.
Set if arithmetic overflow occurred; cleared otherwise.
Unaffected.
Unaffected.

Format:
Bytes

Examples:

Opcode
(Hex)

Addr Mode
dst

2

4

00

R

4

opc

Cycles

01

IR

dst

Given: R1

=

03H and register 03H

DEC

R1

->

R1

DEC

@R1

->

Register 03H

=

=

10H:

02H
=

0FH

In the first example, if working register R1 contains the value 03H, the statement &quot; DEC R1 &quot;
decrements the hexadecimal value by one, leaving the value 02H. In the second example, the
statement &quot; DEC @R1 &quot; decrements the value 10H contained in the destination register 03H by
one, leaving the value 0FH.

6-35

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

DECW -- Decrement Word
DECW

dst

Operation:

dst

<-

dst - 1

The contents of the destination location (which must be an even address) and the operand
following that location are treated as a single 16-bit value that is decremented by one.
Flags:

C:
Z:
S:
V:
D:
H:

Unaffected.
Set if the result is &quot; 0 &quot; ; cleared otherwise.
Set if the result is negative; cleared otherwise.
Set if arithmetic overflow occurred; cleared otherwise.
Unaffected.
Unaffected.

Format:
Bytes

Examples:

Addr Mode
dst

2

dst

Opcode
(Hex)

8

80

RR

8

opc

Cycles

81

IR

Given: R0 = 12H, R1 = 34H, R2 = 30H, register 30H = 0FH, and register 31H = 21H:
DECW RR0

->

R0

DECW @R2

->

Register 30H

=

12H, R1
=

=

33H

0FH, register 31H

=

20H

In the first example, destination register R0 contains the value 12H and register R1 the value
34H. The statement &quot; DECW RR0 &quot; addresses R0 and the following operand R1 as a 16-bit word
and decrements the value of R1 by one, leaving the value 33H.
NOTE:

A system malfunction may occur if you use a Zero flag (FLAGS.6) result together with a DECW
instruction. To avoid this problem, we recommend that you use DECW as shown in the following
example:
LOOP: DECW RR0
LD
OR

R2,R0

JR

6-36

R2,R1

NZ,LOOP

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

DI -- Disable Interrupts
DI
Operation:

SYM (0)

<-

0

Bit zero of the system mode control register, SYM.0, is cleared to &quot; 0 &quot; , globally disabling all
interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits,
but the CPU will not service them while interrupt processing is disabled.
Flags:

No flags are affected.

Format:
Bytes

Example:

Given: SYM

=

Opcode
(Hex)

1

opc

Cycles
4

8F

01H:

DI
If the value of the SYM register is 01H, the statement &quot; DI &quot; leaves the new value 00H in the
register and clears SYM.0 to &quot; 0 &quot; , disabling interrupt processing.
Before changing IMR, interrupt pending and interrupt source control register, be sure DI state.

6-37

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

DIV -- Divide (Unsigned)
DIV

dst,src

Operation:

dst

÷

dst

(UPPER)

<-

REMAINDER

dst

(LOWER)

<-

QUOTIENT

src

The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits)
is stored in the lower half of the destination. The remainder (8 bits) is stored in the upper half of
the destination. When the quotient is >= 28, the numbers stored in the upper and lower halves of
the destination for quotient and remainder are incorrect. Both operands are treated as unsigned
integers.
Flags:

C:
Z:
S:
V:
D:
H:

Set if the V flag is set and quotient is between 28 and 29 -1; cleared otherwise.
Set if divisor or quotient = &quot; 0 &quot; ; cleared otherwise.
Set if MSB of quotient = &quot; 1 &quot; ; cleared otherwise.
Set if quotient is >= 28 or if divisor = &quot; 0 &quot; ; cleared otherwise.
Unaffected.
Unaffected.

Format:
Bytes
3

26/10

94

RR

R

95

RR

IR

26/10

src

Opcode
(Hex)

26/10

opc

Cycles

96

RR

IM

dst

Addr Mode
src
dst

NOTE: Execution takes 10 cycles if the divide-by-zero is attempted; otherwise it takes 26 cycles.

Examples:

Given: R0

=

10H, R1

=

03H, R2

=

40H, register 40H

DIV

RR0,R2

->

R0

=

03H, R1

=

RR0,@R2

->

R0

=

03H, R1

=

20H

DIV

RR0,#20H

->

R0

=

03H, R1

=

80H:

40H

DIV

=

80H

In the first example, destination working register pair RR0 contains the values 10H (R0) and 03H
(R1), and register R2 contains the value 40H. The statement &quot; DIV RR0,R2 &quot; divides the 16-bit
RR0 value by the 8-bit value of the R2 (source) register. After the DIV instruction, R0 contains the
value 03H and R1 contains 40H. The 8-bit remainder is stored in the upper half of the destination
register RR0 (R0) and the quotient in the lower half (R1).

6-38

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

DJNZ -- Decrement and Jump if Non-Zero
DJNZ

r,dst

Operation:

r

<-

If

r

r

-

1

? 0, PC

<-

PC

+

dst

The working register being used as a counter is decremented. If the contents of the register are
not logic zero after decrementing, the relative address is added to the program counter and
control passes to the statement whose address is now in the PC. The range of the relative
address is +127 to -128, and the original value of the PC is taken to be the address of the
instruction byte following the DJNZ statement.
NOTE:

Flags:

In case of using DJNZ instruction, the working register being used as a counter should be set at
the one of location 0C0H to 0CFH with SRP, SRP0, or SRP1 instruction.

No flags are affected.

Format:
Bytes

Example:

|

opc

Given: R1

dst

=

Opcode
(Hex)

Addr Mode
dst

2

8 (jump taken)

rA

RA

8 (no jump)

r

Cycles

r = 0 to F

02H and LOOP is the label of a relative address:

SRP

#0C0H

DJNZ

R1,LOOP

DJNZ is typically used to control a &quot; loop &quot; of instructions. In many cases, a label is used as the
destination operand instead of a numeric relative address value. In the example, working register
R1 contains the value 02H, and LOOP is the label for a relative address.
The statement &quot; DJNZ R1, LOOP &quot; decrements register R1 by one, leaving the value 01H.
Because the contents of R1 after the decrement are non-zero, the jump is taken to the relative
address specified by the LOOP label.

6-39

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

EI -- Enable Interrupts
EI
Operation:

SYM (0)

<-

1

An EI instruction sets bit zero of the system mode register, SYM.0 to &quot; 1 &quot; . This allows interrupts to
be serviced as they occur (assuming they have highest priority). If an interrupt's pending bit was
set while interrupt processing was disabled (by executing a DI instruction), it will be serviced
when you execute the EI instruction.
Flags:

No flags are affected.

Format:
Bytes

Example:

Given: SYM

=

Opcode
(Hex)

1

opc

Cycles
4

9F

00H:

EI
If the SYM register contains the value 00H, that is, if interrupts are currently disabled, the
statement &quot; EI &quot; sets the SYM register to 01H, enabling all interrupts. (SYM.0 is the enable bit for
global interrupt processing.)

6-40

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

ENTER -- Enter
ENTER
Operation:

SP
@SP
IP
PC
IP

<-
IP
<-
<-
<-

<-

SP - 2
PC
@IP
IP + 2

This instruction is useful when implementing threaded-code languages. The contents of the
instruction pointer are pushed to the stack. The program counter (PC) value is then written to the
instruction pointer. The program memory word that is pointed to by the instruction pointer is
loaded into the PC, and the instruction pointer is incremented by two.
Flags:

No flags are affected.

Format:
Bytes

Cycles

Opcode
(Hex)

1

14

1F

opc

Example:

The diagram below shows one example of how to use an ENTER statement.

Before
Address
IP

After

Data

Address

0050

IP
Address

PC

0040

SP

0022

22

Data
Stack

40
41
42
43

Data
0043

Data
Enter
Address H
Address L
Address H

Memory

1F
01
10

Address
PC

0110

SP

0020

20
21
22

IPH
IPL
Data

40
41
42
43

00
50

110

Data
Enter
Address H
Address L
Address H

1F
01
10

Routine
Memory

Stack

6-41

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

EXIT -- Exit
EXIT
Operation:

<-
<-
<-
<-

IP
SP
PC
IP

@SP
SP + 2
@IP
IP + 2

This instruction is useful when implementing threaded-code languages. The stack value is
popped and loaded into the instruction pointer. The program memory word that is pointed to by
the instruction pointer is then loaded into the program counter, and the instruction pointer is
incremented by two.
Flags:

No flags are affected.

Format:
Bytes

Cycles

Opcode (Hex)

1

14 (internal stack)

2F

opc

16 (internal stack)

Example:

The diagram below shows one example of how to use an EXIT statement.

Before
Address

After

Data

IP

0050

PC

Address

0040

IP

50
51

IPH
IPL
Data
Stack

6-42

0060

Data
PCL old
PCH

Address

60
00

0022

60
SP

140
20
21
22

0052

PC

Address

SP

Data

00
50

Exit

Memory

Data

Main

0022

22

Data

2F

Stack

Memory

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

IDLE -- Idle Operation
IDLE
Operation:
The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle
mode can be released by an interrupt request (IRQ) or an external reset operation.
Flags:

No flags are affected.

Format:
Bytes
opc

Example:

Cycles

Opcode
(Hex)

1

4

6F

Addr Mode
src
dst
-

-

The instruction
IDLE
stops the CPU clock but not the system clock.

6-43

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

INC -- Increment
INC

dst

Operation:

dst

<-

dst

+

1

The contents of the destination operand are incremented by one.
Flags:

C:
Z:
S:
V:
D:
H:

Unaffected.
Set if the result is &quot; 0 &quot; ; cleared otherwise.
Set if the result is negative; cleared otherwise.
Set if arithmetic overflow occurred; cleared otherwise.
Unaffected.
Unaffected.

Format:
Bytes
dst

|

Cycles

Opcode
(Hex)

Addr Mode
dst

1

4

rE

r

opc

r = 0 to F
opc

Given: R0

=

2

1BH, register 00H

=

INC

R0

->

R0

INC

00H

->

Register 00H

INC

@R0

->

R0

=

=

4

20

R

4

Examples:

dst

21

IR

0CH, and register 1BH

=

0FH:

1CH
=

0DH

1BH, register 01H

=

10H

In the first example, if destination working register R0 contains the value 1BH, the statement &quot; INC
R0 &quot; leaves the value 1CH in that same register.
The next example shows the effect an INC instruction has on register 00H, assuming that it
contains the value 0CH.
In the third example, INC is used in Indirect Register (IR) addressing mode to increment the
value of register 1BH from 0FH to 10H.

6-44

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

INCW -- Increment Word
INCW

dst

Operation:

dst

<-

dst

+

1

The contents of the destination (which must be an even address) and the byte following that
location are treated as a single 16-bit value that is incremented by one.
Flags:

C:
Z:
S:
V:
D:
H:

Unaffected.
Set if the result is &quot; 0 &quot; ; cleared otherwise.
Set if the result is negative; cleared otherwise.
Set if arithmetic overflow occurred; cleared otherwise.
Unaffected.
Unaffected.

Format:
Bytes

Examples:

Opcode
(Hex)

Addr Mode
dst

2

8

A0

RR

8

opc

Cycles

A1

IR

dst

Given: R0

=

1AH, R1

=

02H, register 02H

INCW RR0

->

R0

INCW @R1

->

Register 02H

=

1AH, R1
=

=

0FH, and register 03H

=

0FFH:

= 03H
10H, register 03H

=

00H

In the first example, the working register pair RR0 contains the value 1AH in register R0 and 02H
in register R1. The statement &quot; INCW RR0 &quot; increments the 16-bit destination by one, leaving the
value 03H in register R1. In the second example, the statement &quot; INCW @R1 &quot; uses Indirect
Register (IR) addressing mode to increment the contents of general register 03H from 0FFH to
00H and register 02H from 0FH to 10H.
NOTE:

A system malfunction may occur if you use a Zero (Z) flag (FLAGS.6) result together with an
INCW instruction. To avoid this problem, we recommend that you use INCW as shown in the
following example:
LOOP:

INCW
LD
OR
JR

RR0
R2,R1
R2,R0
NZ,LOOP

6-45

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

IRET -- Interrupt Return
IRET

IRET (Normal)

Operation:

FLAGS
SP <-
PC <-
SP <-
SYM(0)

<- @SP
SP + 1
@SP
SP + 2
<-1

IRET (Fast)
PC <-> IP
FLAGS <- FLAGS'
FIS <- 0

This instruction is used at the end of an interrupt service routine. It restores the flag register and
the program counter. It also re-enables global interrupts. A &quot; normal IRET &quot; is executed only if the
fast interrupt status bit (FIS, bit one of the FLAGS register, 0D5H) is cleared (= &quot; 0 &quot; ). If a fast
interrupt occurred, IRET clears the FIS bit that was set at the beginning of the service routine.
Flags:

All flags are restored to their original settings (that is, the settings before the interrupt occurred).

Format:
IRET
(Normal)

Bytes

Cycles

Opcode (Hex)

opc

1

10 (internal stack)

BF

12 (internal stack)
IRET
(Fast)

Cycles

Opcode (Hex)

opc

Example:

Bytes
1

6

BF

In the figure below, the instruction pointer is initially loaded with 100H in the main program before
interrupts are enabled. When an interrupt occurs, the program counter and instruction pointer are
swapped. This causes the PC to jump to address 100H and the IP to keep the return address.
The last instruction in the service routine normally is a jump to IRET at address FFH. This causes
the instruction pointer to be loaded with 100H &quot; again &quot; and the program counter to jump back to
the main program. Now, the next interrupt can occur and the IP is still correct at 100H.
0H
FFH
100H

IRET
Interrupt
Service
Routine
JP to FFH

FFFFH
NOTE: In the fast interrupt example above, if the last instruction is not a jump to IRET, you must pay attention to the order of
the last two instructions. The IRET cannot be immediately proceeded by a clearing of the interrupt status (as with a
reset of the IPR register).

6-46

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

JP -- Jump
JP

cc,dst

(Conditional)

JP

dst

(Unconditional)

Operation:

If

cc

is true, PC

<-

dst

The conditional JUMP instruction transfers program control to the destination address if the
condition specified by the condition code (cc) is true; otherwise, the instruction following the JP
instruction is executed. The unconditional JP simply replaces the contents of the PC with the
contents of the specified register pair. Control then passes to the statement addressed by the
PC.
Flags:

No flags are affected.

Format: (1)
Bytes

Cycles

Opcode
(Hex)

Addr Mode
dst

3

8

ccD

DA

(2)

cc

|

opc

dst

cc = 0 to F
opc

dst

2

8

30

IRR

NOTES:
1. The 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump.
2. In the first byte of the three-byte instruction format (conditional jump), the condition code and the
opcode are both four bits.

Examples:

Given: The carry flag (C)

=

&quot; 1 &quot; , register 00

JP

C,LABEL_W

->

JP

@00H

->

=

01H, and register 01

LABEL_W
PC

=

=

1000H, PC

=
=

20H:
1000H

0120H

The first example shows a conditional JP. Assuming that the carry flag is set to &quot; 1 &quot; , the statement
&quot; JP C,LABEL_W &quot; replaces the contents of the PC with the value 1000H and transfers control to
that location. Had the carry flag not been set, control would then have passed to the statement
immediately following the JP instruction.
The second example shows an unconditional JP. The statement &quot; JP @00 &quot; replaces the
contents of the PC with the contents of the register pair 00H and 01H, leaving the value 0120H.

6-47

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

JR -- Jump Relative
JR

cc,dst

Operation:

If

cc

is true, PC

<-

PC

+

dst

If the condition specified by the condition code (cc) is true, the relative address is added to the
program counter and control passes to the statement whose address is now in the program
counter; otherwise, the instruction following the JR instruction is executed. (See list of condition
codes).
The range of the relative address is +127, -128, and the original value of the program counter
is taken to be the address of the first instruction byte following the JR statement.
Flags:

No flags are affected.

Format:
Bytes

Cycles

Opcode
(Hex)

Addr Mode
dst

2

6

ccB

RA

(1)

cc

|

opc

dst

cc = 0 to F
NOTE: In the first byte of the two-byte instruction format, the condition code and the opcode are each
four bits.

Example:

Given: The carry flag = &quot; 1 &quot; and LABEL_X
JR

C,LABEL_X

->

PC

=

=

1FF7H:

1FF7H

If the carry flag is set (that is, if the condition code is true), the statement &quot; JR C,LABEL_X &quot; will
pass control to the statement whose address is now in the PC. Otherwise, the program
instruction following the JR would be executed.

6-48

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

LD -- Load
LD

dst,src

Operation:

dst

<-

src

The contents of the source are loaded into the destination. The source's contents are unaffected.
Flags:

No flags are affected.

Format:
Bytes

src

|

|

opc

2

src

opc

dst

Opcode
(Hex)

4

rC

r

IM

4

dst

Cycles

r8

r

R

4

r9

R

r

2

Addr Mode
src
dst

r = 0 to F
opc

dst

src

dst

opc

src

src

3

3

r

lr

D7

Ir

r

6

E4

R

R

E5

R

IR

6

E6

R

IM

6

opc

dst

C7

6

src

2

4
4

opc

|

D6

IR

IM

dst

3

6

F5

IR

R

opc

dst

|

src

x

3

6

87

r

x [r]

opc

src

|

dst

x

3

6

97

x [r]

r

6-49

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

LD -- Load
LD

(Continued)

Examples:

Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H
register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH:

=

20H,

LD

->

R0 = 10H

LD

R0,01H

->

R0 = 20H, register 01H = 20H

LD

01H,R0

->

Register 01H = 01H, R0 = 01H

LD

R1,@R0

->

R1 = 20H, R0 = 01H

LD

@R0,R1

->

R0 = 01H, R1 = 0AH, register 01H = 0AH

LD

00H,01H

->

Register 00H = 20H, register 01H = 20H

LD

02H,@00H

->

Register 02H = 20H, register 00H = 01H

LD

00H,#0AH

->

Register 00H = 0AH

LD

@00H,#10H

->

Register 00H = 01H, register 01H = 10H

LD

@00H,02H

->

Register 00H = 01H, register 01H = 02, register 02H = 02H

LD

R0,#LOOP[R1] ->

R0 = 0FFH, R1 = 0AH

LD

6-50

R0,#10H

#LOOP[R0],R1 ->

Register 31H = 0AH, R0 = 01H, R1 = 0AH

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

LDB -- Load Bit
LDB

dst,src.b

LDB

dst.b,src

Operation:

dst(0)

<-

src(b)

or
dst(b)

<-

src(0)

The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the
source is loaded into the specified bit of the destination. No other bits of the destination are
affected. The source is unaffected.
Flags:

No flags are affected.

Format:
Bytes

Cycles

Opcode
(Hex)

Addr Mode
src
dst

opc

dst | b | 0

src

3

6

47

r0

Rb

opc

src | b | 1

dst

3

6

47

Rb

r0

NOTE: In the second byte of the instruction formats, the destination (or source) address is four bits, the bit
address 'b' is three bits, and the LSB address value is one bit in length.

Examples:

Given: R0

=

06H and general register 00H

=

05H:

LDB

R0,00H.2

->

R0

=

07H, register 00H

=

05H

LDB

00H.0,R0

->

R0

=

06H, register 00H

=

04H

In the first example, destination working register R0 contains the value 06H and the source
general register 00H the value 05H. The statement &quot; LD R0,00H.2 &quot; loads the bit two value of the
00H register into bit zero of the R0 register, leaving the value 07H in register R0.
In the second example, 00H is the destination register. The statement &quot; LD 00H.0,R0 &quot; loads bit
zero of register R0 to the specified bit (bit zero) of the destination register, leaving 04H in general
register 00H.

6-51

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

LDC/LDE -- Load Memory
LDC/LDE

dst,src

Operation:

dst

<-

src

This instruction loads a byte from program or data memory into a working register or vice-versa.
The source values are unaffected. LDC refers to program memory and LDE to data memory. The
assembler makes 'Irr' or 'rr' values an even number for program memory and odd an odd number
for data memory.
Flags:

No flags are affected.

Format:
Bytes

Cycles

Opcode
(Hex)

Addr Mode
src
dst

1.

opc

dst | src

2

10

C3

r

Irr

2.

opc

src | dst

2

10

D3

Irr

r

3.

opc

dst | src

XS

3

12

E7

r

XS [rr]

4.

opc

src | dst

XS

3

12

F7

XS [rr]

r

5.

opc

dst | src

XLL

XLH

4

14

A7

r

XL [rr]

6.

opc

src | dst

XLL

XLH

4

14

B7

XL [rr]

r

7.

opc

dst | 0000

DAL

DAH

4

14

A7

r

DA

8.

opc

src | 0000

DAL

DAH

4

14

B7

DA

r

9.

opc

dst | 0001

DAL

DAH

4

14

A7

r

DA

10.

opc

src | 0001

DAL

DAH

4

14

B7

DA

r

NOTES:
1. The source (src) or working register pair [rr] for formats 5 and 6 cannot use register pair 0-1.
2. For formats 3 and 4, the destination address 'XS [rr]' and the source address 'XS [rr]' are each one
byte.
3. For formats 5 and 6, the destination address 'XL [rr] and the source address 'XL [rr]' are each two
bytes.
4. The DA and r source values for formats 7 and 8 are used to address program memory; the second
set of values, used in formats 9 and 10, are used to address data memory.

6-52

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

LDC/LDE -- Load Memory
LDC/LDE

(Continued)

Examples:

Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations
0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory
locations 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H:
LDC

R0,@RR2

; R0
; R0

<- contents of program memory location 0104H
= 1AH, R2 = 01H, R3 = 04H

LDE

R0,@RR2

; R0
; R0

<- contents of external data memory location 0104H
= 2AH, R2 = 01H, R3 = 04H

LDC (note) @RR2,R0

; 11H (contents of R0) is loaded into program memory
; location 0104H (RR2),
; working registers R0, R2, R3 -> no change

LDE

@RR2,R0

; 11H (contents of R0) is loaded into external data memory
; location 0104H (RR2),
; working registers R0, R2, R3 -> no change

LDC

R0,#01H[RR2]

; R0
<- contents of program memory location 0105H
; (01H + RR2),
; R0 = 6DH, R2 = 01H, R3 = 04H

LDE

R0,#01H[RR2]

; R0 <- contents of external data memory location 0105H
; (01H + RR2), R0 = 7DH, R2 = 01H, R3 = 04H

LDC (note) #01H[RR2],R0

; 11H (contents of R0) is loaded into program memory location
; 0105H (01H + 0104H)

LDE

#01H[RR2],R0

; 11H (contents of R0) is loaded into external data memory
; location 0105H (01H + 0104H)

LDC

R0,#1000H[RR2] ; R0 <- contents of program memory location 1104H
; (1000H + 0104H), R0 = 88H, R2 = 01H, R3 = 04H

LDE

R0,#1000H[RR2] ; R0 <- contents of external data memory location 1104H
; (1000H + 0104H), R0 = 98H, R2 = 01H, R3 = 04H

LDC
88H

R0,1104H

; R0

<-

LDE

R0,1104H

; R0
; R0

<- contents of external data memory location 1104H,
= 98H

contents of program memory location 1104H, R0

=

LDC (note) 1105H,R0

; 11H (contents of R0) is loaded into program memory location
; 1105H, (1105H) <- 11H

LDE

; 11H (contents of R0) is loaded into external data memory
; location 1105H, (1105H) <- 11H

NOTE:

1105H,R0

These instructions are not supported by masked ROM type devices.

6-53

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

LDCD/LDED -- Load Memory and Decrement
LDCD/LDED

dst,src

Operation:

dst
rr

<-
<-

src
rr - 1

These instructions are used for user stacks or block transfers of data from program or data
memory to the register file. The address of the memory location is specified by a working register
pair. The contents of the source location are loaded into the destination location. The memory
address is then decremented. The contents of the source are unaffected.
LDCD references program memory and LDED references external data memory. The assembler
makes 'Irr' an even number for program memory and an odd number for data memory.
Flags:

No flags are affected.

Format:
Bytes
opc

Examples:

Cycles

Opcode
(Hex)

2

10

E2

dst | src

Addr Mode
src
dst
r

Irr

Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory location 1033H = 0CDH,
and external data memory location 1033H = 0DDH:
LDCD

R8,@RR6

; 0CDH (contents of program memory location 1033H) is loaded
; into R8 and RR6 is decremented by one
; R8

LDED

R8,@RR6

=

0CDH, R6

=

10H, R7

=

32H (RR6

RR6 - 1)

; 0DDH (contents of data memory location 1033H) is loaded
; into R8 and RR6 is decremented by one (RR6
; R8

6-54

<-

=

0DDH, R6

=

10H, R7

=

32H

<-

RR6 - 1)

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

LDCI/LDEI -- Load Memory and Increment
LDCI/LDEI

dst,src

Operation:

dst
rr

<-
<-

src
rr

+

1

These instructions are used for user stacks or block transfers of data from program or data
memory to the register file. The address of the memory location is specified by a working register
pair. The contents of the source location are loaded into the destination location. The memory
address is then incremented automatically. The contents of the source are unaffected.
LDCI refers to program memory and LDEI refers to external data memory. The assembler makes
'Irr' even for program memory and odd for data memory.
Flags:

No flags are affected.

Format:
Bytes
opc

Examples:

Cycles

Opcode
(Hex)

2

10

E3

dst | src

Addr Mode
src
dst
r

Irr

Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory locations 1033H = 0CDH and 1034H
= 0C5H; external data memory locations 1033H = 0DDH and 1034H = 0D5H:
LDCI

R8,@RR6

; 0CDH (contents of program memory location 1033H) is loaded
; into R8 and RR6 is incremented by one (RR6
; R8

LDEI

R8,@RR6

=

0CDH, R6

=

10H, R7

=

<-

RR6 + 1)

34H

; 0DDH (contents of data memory location 1033H) is loaded
; into R8 and RR6 is incremented by one (RR6
; R8

=

0DDH, R6

=

10H, R7

=

<-

RR6 + 1)

34H

6-55

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

LDCPD/LDEPD -- Load Memory with Pre-Decrement
LDCPD/
LDEPD

dst,src

Operation:

rr
dst

<-
<-

rr

-

1

src

These instructions are used for block transfers of data from program or data memory from the
register file. The address of the memory location is specified by a working register pair and is first
decremented. The contents of the source location are then loaded into the destination location.
The contents of the source are unaffected.
LDCPD refers to program memory and LDEPD refers to external data memory. The assembler
makes 'Irr' an even number for program memory and an odd number for external data memory.
Flags:

No flags are affected.

Format:
Bytes
opc

Examples:

Given: R0

=

77H, R6

=

30H, and R7

=

Opcode
(Hex)

2

src | dst

Cycles
14

F2

Addr Mode
src
dst
Irr

r

00H:

LDCPD

;
;
;
;

(RR6 <- RR6 - 1)
77H (contents of R0) is loaded into program memory location
2FFFH (3000H - 1H)
R0 = 77H, R6 = 2FH, R7 = 0FFH

LDEPD

6-56

@RR6,R0

@RR6,R0

;
;
;
;

(RR6 <- RR6 - 1)
77H (contents of R0) is loaded into external data memory
location 2FFFH (3000H - 1H)
R0 = 77H, R6 = 2FH, R7 = 0FFH

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

LDCPI/LDEPI -- Load Memory with Pre-Increment
LDCPI/
LDEPI

dst,src

Operation:

rr
dst

<-
<-

rr

+

1

src

These instructions are used for block transfers of data from program or data memory from the
register file. The address of the memory location is specified by a working register pair and is first
incremented. The contents of the source location are loaded into the destination location. The
contents of the source are unaffected.
LDCPI refers to program memory and LDEPI refers to external data memory. The assembler
makes 'Irr' an even number for program memory and an odd number for data memory.
Flags:

No flags are affected.

Format:
Bytes
opc

Examples:

Given: R0

=

7FH, R6

=

21H, and R7

=

Opcode
(Hex)

2

src | dst

Cycles
14

F3

Addr Mode
src
dst
Irr

r

0FFH:

LDCPI

@RR6,R0

;
;
;
;

(RR6 <- RR6 + 1)
7FH (contents of R0) is loaded into program memory
location 2200H (21FFH + 1H)
R0 = 7FH, R6 = 22H, R7 = 00H

LDEPI

@RR6,R0

;
;
;
;

(RR6 <- RR6 + 1)
7FH (contents of R0) is loaded into external data memory
location 2200H (21FFH + 1H)
R0 = 7FH, R6 = 22H, R7 = 00H

6-57

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

LDW -- Load Word
LDW

dst,src

Operation:

dst

<-

src

The contents of the source (a word) are loaded into the destination. The contents of the source
are unaffected.
Flags:

No flags are affected.

Format:
Bytes

opc

Examples:

src

dst

Opcode
(Hex)

3

8

C4

RR

RR

8

opc

Cycles

C5

RR

IR

8

C6

RR

IML

dst

src

4

Given: R4 = 06H, R5 = 1CH, R6 = 05H, R7 = 02H, register 00H
register 01H = 02H, register 02H = 03H, and register 03H = 0FH:

Addr Mode
src
dst

=

1AH,

LDW

RR6,RR4

->

R6

LDW

00H,02H

->

Register 00H = 03H, register 01H = 0FH,
register 02H = 03H, register 03H = 0FH

LDW

RR2,@R7

->

R2

LDW

04H,@01H

->

Register 04H

LDW

RR6,#1234H

->

R6

LDW

02H,#0FEDH

->

Register 02H

=

=

=

06H, R7

03H, R3
=

12H, R7
=

=

=

1CH, R4

=

=

1CH

0FH,

03H, register 05H
=

06H, R5

=

0FH

=

0EDH

34H

0FH, register 03H

In the second example, please note that the statement &quot; LDW 00H,02H &quot; loads the contents of
the source word 02H, 03H into the destination word 00H, 01H. This leaves the value 03H in
general register 00H and the value 0FH in register 01H.
The other examples show how to use the LDW instruction with various addressing modes and
formats.

6-58

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

MULT -- Multiply (Unsigned)
MULT

dst,src

Operation:

dst

<-

dst ×

src

The 8-bit destination operand (even register of the register pair) is multiplied by the source
operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination
address. Both operands are treated as unsigned integers.
Flags:

C:
Z:
S:
V:
D:
H:

Set if result is &amp; gt; 255; cleared otherwise.
Set if the result is &quot; 0 &quot; ; cleared otherwise.
Set if MSB of the result is a &quot; 1 &quot; ; cleared otherwise.
Cleared.
Unaffected.
Unaffected.

Format:
Bytes

Examples:

dst

3

22

84

RR

R

85

RR

IR

22

src

Opcode
(Hex)

22

opc

Cycles

Addr Mode
src
dst

86

RR

IM

Given: Register 00H = 20H, register 01H = 03H, register 02H = 09H, register 03H = 06H:
MULT

00H, 02H

->

Register 00H = 01H, register 01H = 20H, register 02H = 09H

MULT

00H, @01H

->

Register 00H = 00H, register 01H = 0C0H

MULT

00H, #30H

->

Register 00H = 06H, register 01H = 00H

In the first example, the statement &quot; MULT 00H,02H &quot; multiplies the 8-bit destination operand (in
the register 00H of the register pair 00H, 01H) by the source register 02H operand (09H). The
16-bit product, 0120H, is stored in the register pair 00H, 01H.

6-59

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

NEXT -- Next
NEXT
Operation:

PC
IP

<-
<-

@ IP
IP

+

2

The NEXT instruction is useful when implementing threaded-code languages. The program
memory word that is pointed to by the instruction pointer is loaded into the program counter. The
instruction pointer is then incremented by two.
Flags:

No flags are affected.

Format:
Bytes

Cycles

Opcode
(Hex)

1

10

0F

opc

Example:

The following diagram shows one example of how to use the

Before
Address
IP

After

Data

Address

0043

IP
Address

PC

0120

43
44
45

120

Data
0045

Data
Data
Address H
Address L
Address H

Next
Memory

6-60

NEXT instruction.

01
10

Address
PC

0130

43
44
45

130

Data
Address H
Address L
Address H

Routine
Memory

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

NOP -- No Operation
NOP
Operation:

No action is performed when the CPU executes this instruction. Typically, one or more NOPs are
executed in sequence in order to effect a timing delay of variable duration.

Flags:

No flags are affected.

Format:
Bytes
opc

Example:

Cycles

Opcode
(Hex)

1

4

FF

When the instruction
NOP
is encountered in a program, no operation occurs. Instead, there is a delay in instruction
execution time.

6-61

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

OR -- Logical OR
OR

dst,src

Operation:

dst

<-

dst

OR

src

The source operand is logically ORed with the destination operand and the result is stored in the
destination. The contents of the source are unaffected. The OR operation results in a &quot; 1 &quot; being
stored whenever either of the corresponding bits in the two operands is a &quot; 1 &quot; ; otherwise a &quot; 0 &quot; is
stored.
Flags:

C:
Z:
S:
V:
D:
H:

Unaffected.
Set if the result is &quot; 0 &quot; ; cleared otherwise.
Set if the result bit 7 is set; cleared otherwise.
Always cleared to &quot; 0 &quot; .
Unaffected.
Unaffected.

Format:
Bytes

opc

Examples:

2

4

42

r

r

43

r

lr

6

44

R

R

6

opc

Opcode
(Hex)

6

opc

Cycles

45

R

IR

6

46

R

IM

dst | src

src

dst

dst

3

src

3

Addr Mode
src
dst

Given: R0 = 15H, R1 = 2AH, R2 = 01H, register 00H = 08H, register 01H = 37H, and register
08H = 8AH:
OR

R0,R1

->

R0

=

3FH, R1

=

2AH

OR

R0,@R2

->

R0

=

37H, R2

=

01H, register 01H

OR

00H,01H

->

Register 00H

=

3FH, register 01H

=

37H

OR

01H,@00H

->

Register 00H

=

08H, register 01H

=

0BFH

OR

00H,#02H

->

Register 00H

=

0AH

=

37H

In the first example, if working register R0 contains the value 15H and register R1 the value 2AH,
the statement &quot; OR R0,R1 &quot; logical-ORs the R0 and R1 register contents and stores the result
(3FH) in destination register R0.
The other examples show the use of the logical OR instruction with the various addressing
modes and formats.

6-62

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

POP -- Pop From Stack
POP

dst

Operation:

dst

<-

@SP

SP

<-

SP

+

1

The contents of the location addressed by the stack pointer are loaded into the destination. The
stack pointer is then incremented by one.
Flags:

No flags affected.

Format:
Bytes

Examples:

Opcode
(Hex)

Addr Mode
dst

2

8

50

R

8

opc

Cycles

51

IR

dst

Given: Register 00H = 01H, register 01H
0FBH, and stack register 0FBH = 55H:

=

1BH, SPH (0D8H)

POP

00H

->

Register 00H

=

55H, SP

POP

@00H

->

Register 00H

=

01H, register 01H

=

=

00H, SPL (0D9H)

=

00FCH
=

55H, SP

=

00FCH

In the first example, general register 00H contains the value 01H. The statement &quot; POP 00H &quot;
loads the contents of location 00FBH (55H) into destination register 00H and then increments the
stack pointer by one. Register 00H then contains the value 55H and the SP points to location
00FCH.

6-63

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

POPUD -- Pop User Stack (Decrementing)
POPUD

dst,src

Operation:

dst
IR

<-
<-

src
IR - 1

This instruction is used for user-defined stacks in the register file. The contents of the register file
location addressed by the user stack pointer are loaded into the destination. The user stack
pointer is then decremented.
Flags:

No flags are affected.

Format:
Bytes
opc

Example:

src

Given: Register 00H =
register 02H = 70H:
POPUD
6FH

02H,@00H

Cycles

Opcode
(Hex)

3

8

92

dst

42H (user stack pointer register), register 42H
->

Register 00H

=

41H, register 02H

=

=

Addr Mode
src
dst
R

IR

6FH, and

6FH, register 42H

If general register 00H contains the value 42H and register 42H the value 6FH, the statement
&quot; POPUD 02H,@00H &quot; loads the contents of register 42H into the destination register 02H. The
user stack pointer is then decremented by one, leaving the value 41H.

6-64

=

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

POPUI -- Pop User Stack (Incrementing)
POPUI

dst,src

Operation:

dst
IR

<-
<-

src
IR + 1

The POPUI instruction is used for user-defined stacks in the register file. The contents of the
register file location addressed by the user stack pointer are loaded into the destination. The user
stack pointer is then incremented.
Flags:

No flags are affected.

Format:
Bytes
opc

Example:

src

Given: Register 00H
POPUI

02H,@00H

=

01H and register 01H
->

Opcode
(Hex)

3

dst

Cycles
8

93

=

Addr Mode
src
dst
R

IR

70H:

Register 00H = 02H, register 01H = 70H, register 02H = 70H

If general register 00H contains the value 01H and register 01H the value 70H, the statement
&quot; POPUI 02H,@00H &quot; loads the value 70H into the destination general register 02H. The user
stack pointer (register 00H) is then incremented by one, changing its value from 01H to 02H.

6-65

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

PUSH -- Push To Stack
PUSH

src

Operation:

SP

<-

@SP

SP
<-

-

1

src

A PUSH instruction decrements the stack pointer value and loads the contents of the source (src)
into the location addressed by the decremented stack pointer. The operation then adds the new
value to the top of the stack.
Flags:

No flags are affected.

Format:
Bytes
opc

Opcode
(Hex)

Addr Mode
dst

2

src

Cycles
8 (internal clock)

70

R

71

IR

8 (external clock)
8 (internal clock)
8 (external clock)

Examples:

Given: Register 40H

=

4FH, register 4FH

=

0AAH, SPH

=

00H, and SPL

=

00H:

PUSH

40H

->

Register 40H = 4FH, stack register 0FFH
SPH = 0FFH, SPL = 0FFH

PUSH

@40H

->

Register 40H = 4FH, register 4FH = 0AAH, stack register
0FFH = 0AAH, SPH = 0FFH, SPL = 0FFH

=

4FH,

In the first example, if the stack pointer contains the value 0000H, and general register 40H the
value 4FH, the statement &quot; PUSH 40H &quot; decrements the stack pointer from 0000 to 0FFFFH. It
then loads the contents of register 40H into location 0FFFFH and adds this new value to the top
of the stack.

6-66

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

PUSHUD -- Push User Stack (Decrementing)
PUSHUD

dst,src

Operation:

IR
dst

<-
<-

IR

-1

src

This instruction is used to address user-defined stacks in the register file. PUSHUD decrements
the user stack pointer and loads the contents of the source into the register addressed by the
decremented stack pointer.
Flags:

No flags are affected.

Format:
Bytes
opc

Example:

dst

Given: Register 00H
PUSHUD @00H,01H

=
->

03H, register 01H

=

Opcode
(Hex)

3

src

Cycles
8

82

05H, and register 02H

=

Addr Mode
src
dst
IR

R

1AH:

Register 00H = 02H, register 01H = 05H, register 02H = 05H

If the user stack pointer (register 00H, for example) contains the value 03H, the statement
&quot; PUSHUD @00H,01H &quot; decrements the user stack pointer by one, leaving the value 02H. The
01H register value, 05H, is then loaded into the register addressed by the decremented user
stack pointer.

6-67

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

PUSHUI -- Push User Stack (Incrementing)
PUSHUI

dst,src

Operation:

IR
dst

<-
<-

IR

+

1

src

This instruction is used for user-defined stacks in the register file. PUSHUI increments the user
stack pointer and then loads the contents of the source into the register location addressed by
the incremented user stack pointer.
Flags:

No flags are affected.

Format:
Bytes
opc

Example:

dst

Given: Register 00H
PUSHUI

@00H,01H

=
->

03H, register 01H

=

Opcode
(Hex)

3

src

Cycles
8

83

05H, and register 04H

=

Addr Mode
src
dst
IR

R

2AH:

Register 00H = 04H, register 01H = 05H, register 04H = 05H

If the user stack pointer (register 00H, for example) contains the value 03H, the statement
&quot; PUSHUI @00H,01H &quot; increments the user stack pointer by one, leaving the value 04H. The 01H
register value, 05H, is then loaded into the location addressed by the incremented user stack
pointer.

6-68

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

RCF -- Reset Carry Flag
RCF

RCF

Operation:

C

<-

0

The carry flag is cleared to logic zero, regardless of its previous value.
Flags:

C:

Cleared to &quot; 0 &quot; .

No other flags are affected.
Format:
Bytes

Example:

Given: C = &quot; 1 &quot;

or

Opcode
(Hex)

1

opc

Cycles
4

CF

&quot; 0 &quot; :

The instruction RCF clears the carry flag (C) to logic zero.

6-69

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

RET -- Return
RET
PC

<-

@SP

SP

Operation:

<-

SP

+

2

The RET instruction is normally used to return to the previously executing procedure at the end of
a procedure entered by a CALL instruction. The contents of the location addressed by the stack
pointer are popped into the program counter. The next statement that is executed is the one that
is addressed by the new program counter value.
Flags:

No flags are affected.

Format:
Bytes

Opcode (Hex)

1

opc

Cycles
8 (internal stack)

AF

10 (internal stack)

Example:

Given: SP
RET

->

=

00FCH, (SP)
PC

=

=

101AH, and PC

101AH, SP

=

=

1234:

00FEH

The statement &quot; RET &quot; pops the contents of stack pointer location 00FCH (10H) into the high byte
of the program counter. The stack pointer then pops the value in location 00FEH (1AH) into the
PC's low byte and the instruction at location 101AH is executed. The stack pointer now points to
memory location 00FEH.

6-70

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

RL -- Rotate Left
RL

dst

Operation:

C

<-

dst (7)

dst (0) <-

dst (7)

dst (n

1)

+

<-

dst (n),

n

=

0-6

The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is
moved to the bit zero (LSB) position and also replaces the carry flag.

7

0

C

Flags:

C:
Z:
S:
V:
D:
H:

Set if the bit rotated from the most significant bit position (bit 7) was &quot; 1 &quot; .
Set if the result is &quot; 0 &quot; ; cleared otherwise.
Set if the result bit 7 is set; cleared otherwise.
Set if arithmetic overflow occurred; cleared otherwise.
Unaffected.
Unaffected.

Format:
Bytes

Examples:

Opcode
(Hex)

Addr Mode
dst

2

4

90

R

4

opc

Cycles

91

IR

dst

Given: Register 00H

=

0AAH, register 01H

=

02H and register 02H

RL

00H

->

Register 00H

=

55H, C

RL

@01H

->

Register 01H

=

02H, register 02H

=

=

17H:

&quot; 1 &quot;
=

2EH, C

=

&quot; 0 &quot;

In the first example, if general register 00H contains the value 0AAH (10101010B), the statement
&quot; RL 00H &quot; rotates the 0AAH value left one bit position, leaving the new value 55H (01010101B)
and setting the carry and overflow flags.

6-71

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

RLC -- Rotate Left Through Carry
RLC

dst

Operation:

dst (0) <-
C

<-

dst (n

C

dst (7)
+

1)

<- dst (n), n

=

0-6

The contents of the destination operand with the carry flag are rotated left one bit position. The
initial value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero.

7

0

C

Flags:

C:
Z:
S:
V:

Set if the bit rotated from the most significant bit position (bit 7) was &quot; 1 &quot; .
Set if the result is &quot; 0 &quot; ; cleared otherwise.
Set if the result bit 7 is set; cleared otherwise.
Set if arithmetic overflow occurred, that is, if the sign of the destination changed during
rotation; cleared otherwise.
D: Unaffected.
H: Unaffected.

Format:
Bytes

Examples:

Opcode
(Hex)

Addr Mode
dst

2

4

10

R

4

opc

Cycles

11

IR

dst

Given: Register 00H = 0AAH, register 01H = 02H, and register 02H = 17H, C = &quot; 0 &quot; :
RLC

00H

->

Register 00H

=

54H, C

RLC

@01H

->

Register 01H

=

02H, register 02H

=

&quot; 1 &quot;
=

2EH, C

= &quot; 0 &quot;

In the first example, if general register 00H has the value 0AAH (10101010B), the statement
&quot; RLC 00H &quot; rotates 0AAH one bit position to the left. The initial value of bit 7 sets the carry flag
and the initial value of the C flag replaces bit zero of register 00H, leaving the value 55H
(01010101B). The MSB of register 00H resets the carry flag to &quot; 1 &quot; and sets the overflow flag.

6-72

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

RR -- Rotate Right
RR

dst

Operation:

C

<-

dst (7)

dst (0)
<-

dst (n) <-

dst (0)
dst (n

+

1), n

=

0-6

The contents of the destination operand are rotated right one bit position. The initial value of bit
zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).

7

0

C

Flags:

C:
Z:
S:
V:

Set if the bit rotated from the least significant bit position (bit zero) was &quot; 1 &quot; .
Set if the result is &quot; 0 &quot; ; cleared otherwise.
Set if the result bit 7 is set; cleared otherwise.
Set if arithmetic overflow occurred, that is, if the sign of the destination changed during
rotation; cleared otherwise.
D: Unaffected.
H: Unaffected.

Format:
Bytes

Examples:

Opcode
(Hex)

Addr Mode
dst

2

4

E0

R

4

opc

Cycles

E1

IR

dst

Given: Register 00H

=

31H, register 01H

=

RR

00H

->

Register 00H =

RR

@01H

->

Register 01H

02H, and register 02H
98H, C

=

=

=

17H:

&quot; 1 &quot;

02H, register 02H

=

8BH, C

=

&quot; 1 &quot;

In the first example, if general register 00H contains the value 31H (00110001B), the statement
&quot; RR 00H &quot; rotates this value one bit position to the right. The initial value of bit zero is moved to
bit 7, leaving the new value 98H (10011000B) in the destination register. The initial bit zero also
resets the C flag to &quot; 1 &quot; and the sign flag and overflow flag are also set to &quot; 1 &quot; .

6-73

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

RRC -- Rotate Right Through Carry
RRC

dst

Operation:

dst (7)
C

<-

dst (n)

<-

C

dst (0)
<-

dst (n

+

1), n

=

0-6

The contents of the destination operand and the carry flag are rotated right one bit position. The
initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit 7
(MSB).

7

0

C

Flags:

C:
Z:
S:
V:

Set if the bit rotated from the least significant bit position (bit zero) was &quot; 1 &quot; .
Set if the result is &quot; 0 &quot; cleared otherwise.
Set if the result bit 7 is set; cleared otherwise.
Set if arithmetic overflow occurred, that is, if the sign of the destination changed during
rotation; cleared otherwise.
D: Unaffected.
H: Unaffected.

Format:
Bytes

Examples:

Opcode
(Hex)

Addr Mode
dst

2

4

C0

R

4

opc

Cycles

C1

IR

dst

Given: Register 00H

=

55H, register 01H

=

02H, register 02H

RRC

00H

->

Register 00H

=

2AH, C

RRC

@01H

->

Register 01H

=

02H, register 02H

=

=

17H, and C

=

&quot; 0 &quot; :

&quot; 1 &quot;
=

0BH, C

=

&quot; 1 &quot;

In the first example, if general register 00H contains the value 55H (01010101B), the statement
&quot; RRC 00H &quot; rotates this value one bit position to the right. The initial value of bit zero ( &quot; 1 &quot; )
replaces the carry flag and the initial value of the C flag ( &quot; 1 &quot; ) replaces bit 7. This leaves the new
value 2AH (00101010B) in destination register 00H. The sign flag and overflow flag are both
cleared to &quot; 0 &quot; .

6-74

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

SB0 -- Select Bank 0
SB0
Operation:

BANK <-

0

The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0) to logic zero,
selecting bank 0 register addressing in the set 1 area of the register file.
Flags:

No flags are affected.

Format:
Bytes
opc

Example:

Cycles

Opcode
(Hex)

1

4

4F

The statement
SB0
clears FLAGS.0 to &quot; 0 &quot; , selecting bank 0 register addressing.

6-75

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

SB1 -- Select Bank 1
SB1
Operation:

BANK

<-1

The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to logic one,
selecting bank 1 register addressing in the set 1 area of the register file. (Bank 1 is not
implemented in some S3F8-series microcontrollers.)
Flags:

No flags are affected.

Format:
Bytes
opc

Example:

Cycles

Opcode
(Hex)

1

4

5F

The statement
SB1
sets FLAGS.0 to &quot; 1 &quot; , selecting bank 1 register addressing, if implemented.

6-76

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

SBC -- Subtract with Carry
SBC

dst,src

Operation:

dst

<-

dst

-

src

-

c

The source operand, along with the current value of the carry flag, is subtracted from the
destination operand and the result is stored in the destination. The contents of the source are
unaffected. Subtraction is performed by adding the two's-complement of the source operand to
the destination operand. In multiple precision arithmetic, this instruction permits the carry
( &quot; borrow &quot; ) from the subtraction of the low-order operands to be subtracted from the subtraction of
high-order operands.
Flags:

Set if a borrow occurred (src &amp; gt; dst); cleared otherwise.
Set if the result is &quot; 0 &quot; ; cleared otherwise.
Set if the result is negative; cleared otherwise.
Set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign
of the result is the same as the sign of the source; cleared otherwise.
D: Always set to &quot; 1 &quot; .
H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result;
set otherwise, indicating a &quot; borrow &quot; .
C:
Z:
S:
V:

Format:
Bytes

opc

Examples:

2

4

32

r

r

33

r

lr

6

34

R

R

6

opc

Opcode
(Hex)

6

opc

Cycles

35

R

IR

3

6

36

R

IM

&quot; 1 &quot; , register 01H

=

20H, register 02H

dst | src

src

dst

dst

3

src

Given: R1 = 10H, R2 =
and register 03H = 0AH:

03H, C

=

Addr Mode
src
dst

=

03H,

SBC

R1,R2

->

R1 = 0CH, R2 = 03H

SBC

R1,@R2

->

R1 = 05H, R2 = 03H, register 03H = 0AH

SBC

01H,02H

->

Register 01H = 1CH, register 02H = 03H

SBC

01H,@02H

->

Register 01H = 15H,register 02H = 03H, register 03H = 0AH

SBC

01H,#8AH

->

Register 01H =

5H; C, S, and V = &quot; 1 &quot;

In the first example, if working register R1 contains the value 10H and register R2 the value 03H,
the statement &quot; SBC R1,R2 &quot; subtracts the source value (03H) and the C flag value ( &quot; 1 &quot; ) from the
destination (10H) and then stores the result (0CH) in register R1.

6-77

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

SCF -- Set Carry Flag
SCF
Operation:

C<-

1

The carry flag (C) is set to logic one, regardless of its previous value.
Flags:

C: Set to &quot; 1 &quot; .
No other flags are affected.

Format:
Bytes
opc

Example:

The statement
SCF
sets the carry flag to logic one.

6-78

Cycles

Opcode
(Hex)

1

4

DF

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

SRA -- Shift Right Arithmetic
SRA

dst

Operation:

dst (7)
C

<-

dst (n)

<-

dst (7)

dst (0)
<-

dst (n

+

1), n

=

0-6

An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the
LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into bit
position 6.

7

6

0

C

Flags:

C:
Z:
S:
V:
D:
H:

Set if the bit shifted from the LSB position (bit zero) was &quot; 1 &quot; .
Set if the result is &quot; 0 &quot; ; cleared otherwise.
Set if the result is negative; cleared otherwise.
Always cleared to &quot; 0 &quot; .
Unaffected.
Unaffected.

Format:
Bytes

Examples:

Opcode
(Hex)

Addr Mode
dst

2

4

D0

R

4

opc

Cycles

D1

IR

dst

Given: Register 00H = 9AH, register 02H = 03H, register 03H = 0BCH, and C = &quot; 1 &quot; :
SRA

00H

->

Register 00H

=

0CD, C

SRA

@02H

->

Register 02H

=

03H, register 03H

=

&quot; 0 &quot;
=

0DEH, C

=

&quot; 0 &quot;

In the first example, if general register 00H contains the value 9AH (10011010B), the statement
&quot; SRA 00H &quot; shifts the bit values in register 00H right one bit position. Bit zero ( &quot; 0 &quot; ) clears the C
flag and bit 7 ( &quot; 1 &quot; ) is then shifted into the bit 6 position (bit 7 remains unchanged). This leaves the
value 0CDH (11001101B) in destination register 00H.

6-79

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

SRP/SRP0/SRP1 -- Set Register Pointer
SRP

src

SRP0

src

SRP1

src

Operation:

If src (1)

=

1 and src (0)

=

0 then:

RP0 (3-7)

<-

src (3-7)

If src (1)

=

0 and src (0)

=

1 then:

RP1 (3-7)

<-

src (3-7)

If src (1)

=

0 and src (0)

=

0 then:

RP0 (4-7)

<-

src (4-7),

RP0 (3)

<-

0

RP1 (4-7)

<-

src (4-7),

RP1 (3)

<-

1

The source data bits one and zero (LSB) determine whether to write one or both of the register
pointers, RP0 and RP1. Bits 3-7 of the selected register pointer are written unless both register
pointers are selected. RP0.3 is then cleared to logic zero and RP1.3 is set to logic one.
Flags:

No flags are affected.

Format:
Bytes
opc

Examples:

src

Cycles

Opcode
(Hex)

Addr Mode
src

2

4

31

IM

The statement
SRP

#40H

sets register pointer 0 (RP0) at location 0D6H to 40H and register pointer 1 (RP1) at location
0D7H to 48H.
The statement &quot; SRP0
68H.

6-80

#50H &quot; sets RP0 to 50H, and the statement &quot; SRP1

#68H &quot; sets RP1 to

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

STOP -- Stop Operation
STOP
Operation:
The STOP instruction stops the both the CPU clock and system clock and causes the
microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers,
peripheral registers, and I/O port control and data registers are retained. Stop mode can be
released by an external reset operation or by external interrupts. For the reset operation, the
RESET pin must be held to Low level until the required oscillation stabilization interval has
elapsed.
Flags:

No flags are affected.

Format:
Bytes
opc

Example:

Cycles

Opcode
(Hex)

1

4

7F

Addr Mode
src
dst
-

-

The statement
STOP
halts all microcontroller operations.

6-81

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

SUB -- Subtract
SUB

dst,src

Operation:

dst

<-

dst

- src

The source operand is subtracted from the destination operand and the result is stored in the
destination. The contents of the source are unaffected. Subtraction is performed by adding the
two's complement of the source operand to the destination operand.
Flags:

C:
Z:
S:
V:

Set if a &quot; borrow &quot; occurred; cleared otherwise.
Set if the result is &quot; 0 &quot; ; cleared otherwise.
Set if the result is negative; cleared otherwise.
Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the
sign of the result is of the same as the sign of the source operand; cleared otherwise.
D: Always set to &quot; 1 &quot; .
H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result;
set otherwise indicating a &quot; borrow &quot; .

Format:
Bytes

opc

Examples:

2

4

22

r

r

23

r

lr

6

24

R

R

6

opc

Opcode
(Hex)

6

opc

Cycles

25

R

IR

6

26

R

IM

dst | src

src

dst

dst

3

src

3

Addr Mode
src
dst

Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:
SUB

R1,R2

->

R1

=

0FH, R2

=

03H

SUB

R1,@R2

->

R1

=

08H, R2

=

03H

SUB

01H,02H

->

Register 01H

=

1EH, register 02H

=

03H

SUB

01H,@02H

->

Register 01H

=

17H, register 02H

=

03H

SUB

01H,#90H

->

Register 01H

=

91H; C, S, and V

SUB

01H,#65H

->

Register 01H

=

0BCH; C and S

=
=

&quot; 1 &quot;
&quot; 1 &quot; , V

=

&quot; 0 &quot;

In the first example, if working register R1 contains the value 12H and if register R2 contains the
value 03H, the statement &quot; SUB R1,R2 &quot; subtracts the source value (03H) from the destination
value (12H) and stores the result (0FH) in destination register R1.

6-82

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

SWAP -- Swap Nibbles
SWAP

dst

Operation:

dst (0

-

3)

<->

dst (4

- 7)

The contents of the lower four bits and upper four bits of the destination operand are swapped.

7

Flags:

C:
Z:
S:
V:
D:
H:

43

0

Undefined.
Set if the result is &quot; 0 &quot; ; cleared otherwise.
Set if the result bit 7 is set; cleared otherwise.
Undefined.
Unaffected.
Unaffected.

Format:
Bytes

Examples:

Opcode
(Hex)

Addr Mode
dst

2

4

F0

R

4

opc

Cycles

F1

IR

dst

Given: Register 00H

=

3EH, register 02H

=

03H, and register 03H

SWAP

00H

->

Register 00H

=

@02H

->

Register 02H

=

03H, register 03H

0A4H:

0E3H

SWAP

=

=

4AH

In the first example, if general register 00H contains the value 3EH (00111110B), the statement
&quot; SWAP 00H &quot; swaps the lower and upper four bits (nibbles) in the 00H register, leaving the
value 0E3H (11100011B).

6-83

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

TCM -- Test Complement Under Mask
TCM

dst,src

Operation:

(NOT dst)

AND

src

This instruction tests selected bits in the destination operand for a logic one value. The bits to be
tested are specified by setting a &quot; 1 &quot; bit in the corresponding position of the source operand
(mask). The TCM statement complements the destination operand, which is then ANDed with the
source mask. The zero (Z) flag can then be checked to determine the result. The destination and
source operands are unaffected.
Flags:

C:
Z:
S:
V:
D:
H:

Unaffected.
Set if the result is &quot; 0 &quot; ; cleared otherwise.
Set if the result bit 7 is set; cleared otherwise.
Always cleared to &quot; 0 &quot; .
Unaffected.
Unaffected.

Format:
Bytes

opc

Examples:

2

4

62

r

r

63

r

lr

6

64

R

R

6

opc

Opcode
(Hex)

6

opc

Cycles

65

R

IR

6

66

R

IM

dst | src

src

dst

dst

3

src

3

Given: R0 = 0C7H, R1 = 02H, R2
02H, and register 02H = 23H:

=

12H, register 00H

=

Addr Mode
src
dst

2BH, register 01H

TCM

R0,R1

->

R0

=

0C7H, R1

=

02H, Z

TCM

R0,@R1

->

R0

=

0C7H, R1

=

02H, register 02H

TCM

00H,01H

->

Register 00H

2BH, register 01H

=

02H, Z

TCM

00H,@01H

->

Register 00H = 2BH, register 01H
register 02H = 23H, Z = &quot; 1 &quot;

=

02H,

TCM

00H,#34

->

Register 00H

=

=

=

2BH, Z

=

=

&quot; 1 &quot;
=

23H, Z
=

=

&quot; 0 &quot;

&quot; 1 &quot;

&quot; 0 &quot;

In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1
the value 02H (00000010B), the statement &quot; TCM R0,R1 &quot; tests bit one in the destination register
for a &quot; 1 &quot; value. Because the mask value corresponds to the test bit, the Z flag is set to logic one
and can be tested to determine the result of the TCM operation.

6-84

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

TM -- Test Under Mask
TM

dst,src

Operation:

dst

AND

src

This instruction tests selected bits in the destination operand for a logic zero value. The bits to be
tested are specified by setting a &quot; 1 &quot; bit in the corresponding position of the source operand
(mask), which is ANDed with the destination operand. The zero (Z) flag can then be checked to
determine the result. The destination and source operands are unaffected.
Flags:

C:
Z:
S:
V:
D:
H:

Unaffected.
Set if the result is &quot; 0 &quot; ; cleared otherwise.
Set if the result bit 7 is set; cleared otherwise.
Always reset to &quot; 0 &quot; .
Unaffected.
Unaffected.

Format:
Bytes

opc

Examples:

2

4

72

r

r

73

r

lr

6

74

R

R

6

opc

Opcode
(Hex)

6

opc

Cycles

75

R

IR

6

76

R

IM

dst | src

src

dst

dst

3

src

3

Given: R0 = 0C7H, R1 = 02H, R2
02H, and register 02H = 23H:

=

18H, register 00H

=

2BH, register 01H

TM

R0,R1

->

R0

=

0C7H, R1

=

02H, Z

TM

R0,@R1

->

R0

=

0C7H, R1

=

02H, register 02H

TM

00H,01H

->

Register 00H

TM

00H,@01H

->

Register 00H = 2BH, register 01H =
register 02H = 23H, Z = &quot; 0 &quot;

TM

00H,#54H

->

Register 00H

=

=

=

=

=

&quot; 0 &quot;

2BH, register 01H

2BH, Z

Addr Mode
src
dst

=

=

23H, Z

02H, Z

=

=

&quot; 0 &quot;

&quot; 0 &quot;

02H,

&quot; 1 &quot;

In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1
the value 02H (00000010B), the statement &quot; TM R0,R1 &quot; tests bit one in the destination register
for a &quot; 0 &quot; value. Because the mask value does not match the test bit, the Z flag is cleared to logic
zero and can be tested to determine the result of the TM operation.

6-85

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

WFI -- Wait for Interrupt
WFI
Operation:
The CPU is effectively halted until an interrupt occurs, except that DMA transfers can still take
place during this wait state. The WFI status can be released by an internal interrupt, including a
fast interrupt .
Flags:

No flags are affected.

Format:
Bytes

Cycles

Opcode
(Hex)

1

4n

3F

opc

( n = 1, 2, 3, ... )

Example:

The following sample program structure shows the sequence of operations that follow a &quot; WFI &quot;
statement:
Main program

.
.
.

EI
WFI
(Next instruction)

(Enable global interrupt)
(Wait for interrupt)

.
.
.
Interrupt occurs
Interrupt service routine

.
.
.

Clear interrupt flag
IRET

Service routine completed

6-86

S3F833B/F834B_UM_REV1.10

INSTRUCTION SET

XOR -- Logical Exclusive OR
XOR

dst,src

Operation:

dst

<-

dst

XOR

src

The source operand is logically exclusive-ORed with the destination operand and the result is
stored in the destination. The exclusive-OR operation results in a &quot; 1 &quot; bit being stored whenever
the corresponding bits in the operands are different; otherwise, a &quot; 0 &quot; bit is stored.
Flags:

C:
Z:
S:
V:
D:
H:

Unaffected.
Set if the result is &quot; 0 &quot; ; cleared otherwise.
Set if the result bit 7 is set; cleared otherwise.
Always reset to &quot; 0 &quot; .
Unaffected.
Unaffected.

Format:
Bytes

opc

Examples:

2

4

B2

r

r

B3

r

lr

6

B4

R

R

6

opc

Opcode
(Hex)

6

opc

Cycles

B5

R

IR

6

B6

R

IM

dst | src

src

dst

dst

3

src

3

Given: R0 = 0C7H, R1 = 02H, R2
02H, and register 02H = 23H:

=

18H, register 00H

=

Addr Mode
src
dst

2BH, register 01H

=

XOR

R0,R1

->

R0

=

0C5H, R1

=

02H

XOR

R0,@R1

->

R0

=

0E4H, R1

=

02H, register 02H = 23H

XOR

00H,01H

->

Register 00H

=

29H, register 01H = 02H

XOR

00H,@01H

->

Register 00H

=

08H, register 01H = 02H, register 02H = 23H

XOR

00H,#54H

->

Register 00H

=

7FH

In the first example, if working register R0 contains the value 0C7H and if register R1 contains
the value 02H, the statement &quot; XOR R0,R1 &quot; logically exclusive-ORs the R1 value with the R0
value and stores the result (0C5H) in the destination register R0.

6-87

INSTRUCTION SET

S3F833B/F834B_UM_REV1.10

NOTES

6-88

S3F833B/F834B_UM_REV1.10

7

CLOCK CIRCUIT

CLOCK CIRCUIT

OVERVIEW
The S3F833B/F834B microcontroller has two oscillator circuits: a main clock and a sub clock circuit. The CPU
and peripheral hardware operate on the system clock frequency supplied through these circuits. The maximum
CPU clock frequency of S3F833B/F834B is determined by CLKCON register settings.
SYSTEM CLOCK CIRCUIT
The system clock circuit has the following components:
-- External crystal, ceramic resonator, RC oscillation source, OSC PLL clock source, or an external clock source
-- Oscillator stop and wake-up functions
-- Programmable frequency divider for the CPU clock (fxx divided by 1, 2, 8, or 16)
-- System clock control register, CLKCON
-- STOP control register, STPCON
-- OSC PLL control register, OSCPLLR
CPU Clock Notation
In this document, the following notation is used for descriptions of the CPU clock;
fx: main clock
fxt: sub clock
fxx: selected system clock

7-1

CLOCK CIRCUIT

S3F833B/F834B_UM_REV1.10

SUB OSCILLATOR CIRCUITS

MAIN OSCILLATOR CIRCUITS

XIN

XTIN

XOUT

XTOUT

Figure 7-1. Crystal/Ceramic Oscillator (fx)

XIN

XOUT

Figure 7-2. External Oscillator (fx)

XIN
R
XOUT

Figure 7-3. RC Oscillator (fx)

7-2

Figure 7-4. Crystal/Ceramic Oscillator (fxt)

XTIN

XTOUT

Figure 7-5. External Oscillator (fxt)

S3F833B/F834B_UM_REV1.10

CLOCK CIRCUIT

CLOCK STATUS DURING POWER-DOWN MODES
The two power-down modes, Stop mode and Idle mode, affect the system clock as follows:
-- In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator is started, by a reset
operation or an external interrupt (with RC delay noise filter).
-- In Idle mode, the internal clock signal is gated to the CPU, but not to interrupt structure, timers, timer/
counters, and watch timer. Idle mode is released by a reset or by an external or internal interrupt.

Stop Release

INT

PLL frequency
Synthesizer
IF Counter

Main-System
Oscillator
Circuit

fX

fXT

Sub Oscillator
and PLL Circuit

Watch Timer
PLL frequency Synthesizer
IF Counter
LCD Controller

Selector 1
fXX
Stop

OSCCON.3
Stop
OSCCON.0

OSCCON.2

1/1-1/ 4096
STOP OSC
inst.

Frequency
Dividing
Circuit

STPCON
1/1

CLKCON.4-.3

1/ 2

1/ 8

1/16

Basic Timer
Timer/Counter0, 1, 2
Watch Timer
LCD Controller
SIO0, 1
UART0, 1
A/D Converter

Selector 2
CPU

Figure 7-6. System Clock Circuit Diagram

7-3

CLOCK CIRCUIT

S3F833B/F834B_UM_REV1.10

SYSTEM CLOCK CONTROL REGISTER (CLKCON)
The system clock control register, CLKCON, is located in the set 1, address D4H. It is read/write addressable and
has the following functions:
-- Oscillator frequency divide-by value
After the main oscillator is activated, and the fxx/16 (the slowest clock speed) is selected as the CPU clock. If
necessary, you can then increase the CPU clock speed fxx/8, fxx/2, or fxx/1.

System Clock Control Register (CLKCON)
D4H, Set 1, R/W
MSB

.7

.6

.5

.4

Not used
(must keep always 0)

.3

.2

.1

.0

LSB

Not used
(must keep always 0)

Oscillator IRQ wake-up function bit:
0 = Enable IRQ for main wake-up in power down mode
1 = Disable IRQ for main wake-up in power down mode

Divide-by selection bits for
CPU clock frequency:
00 = fXX/16
01 = fXX/8
10 = fXX/2
11 = fXX/1 (non-divided)

Figure 7-7. System Clock Control Register (CLKCON)

7-4

S3F833B/F834B_UM_REV1.10

CLOCK CIRCUIT

OSCILLATOR CONTROL REGISTER (OSCCON)
The oscillator control register, OSCCON, is located in set 1, bank0, at address D2H. It is read/write addressable
and has the following functions:
-- System clock selection
-- Main oscillator control
-- Sub oscillator control
OSCCON.0 register settings select Main clock or Sub clock as system clock.
After a reset, Main clock is selected for system clock because the reset value of OSCCON.0 is &quot; 0 &quot; .
The main oscillator can be stopped or run by setting OSCCON.3.
The sub oscillator can be stopped or run by setting OSCCON.2.

Oscillator Control Register (OSCCON)
D2H, Set 1, Bank0, R/W
MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

System clock selection bit:
0 = Main select
1 = Sub select
Not used

Not used
Sub system oscillator control bit:
0 = Sub oscillator RUN
1 = Sub oscillator STOP
Main system oscillator control bit:
0 = Main oscillator RUN
1 = Main oscillator STOP

Figure 7-8. Oscillator Control Register (OSCCON)

7-5

CLOCK CIRCUIT

S3F833B/F834B_UM_REV1.10

SWITCHING THE CPU CLOCK
Data loading in the oscillator control register, OSCCON, determine whether a main or a sub clock is selected as
the CPU clock, and also how this frequency is to be divided by setting CLKCON. This makes it possible to switch
dynamically between main and sub clocks and to modify operating frequencies.
OSCCON.0 select the main clock (fx) or the sub clock (fxt) for the CPU clock. OSCCON .3 start or stop main
clock oscillation, and OSCCON.2 start or stop sub clock oscillation. CLKCON.4-.3 control the frequency divider
circuit, and divide the selected fxx clock by 1, 2, 8, 16. If fxt is selected for system clock, the CLKCON.4-.3 must
be set to "11".
For example, you are using the default CPU clock (normal operating mode and a main clock of fx/16) and you
want to switch from the fx clock to a sub clock and to stop the main clock. To do this, you need to set CLKCON.4.3 to &quot; 11 &quot; , OSCCON.0 to &quot; 1 &quot; , and OSCCON.3 to "1" by turns. This switches the clock from fx to fxt and stops main
clock oscillation.
The following steps must be taken to switch from a sub clock to the main clock: first, set OSCCON.3 to &quot; 0 &quot; to
enable main clock oscillation. Then, after a certain number of machine cycles has elapsed, select the main clock
by setting OSCCON.0 to &quot; 0 &quot; .

PROGRAMMING TIP -- Switching the CPU clock
1. This example shows how to change from the main clock to the sub clock:
MA2SUB

OR
LD
CALL
OR
RET

CLKCON,#18H
OSCCON,#01H
DLY16
OSCCON,#08H

;
;
;
;

Non-divided clock for system clock
Switches to the sub clock
Delay 16ms
Stop the main clock oscillation

2. This example shows how to change from sub clock to main clock:
SUB2MA

DLY16
DEL

7-6

AND
CALL
AND
RET
SRP
LD
NOP
DJNZ
RET

OSCCON,#07H
DLY16
OSCCON,#06H
#0C0H
R0,#20H
R0,DEL

; Start the main clock oscillation
; Delay 16 ms
; Switch to the main clock

S3F833B/F834B_UM_REV1.10

CLOCK CIRCUIT

STOP Control Register (STPCON)
D1H, Set 1, Bank 0, R/W
MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

STOP Control bits:
Other values = Disable STOP instruction
10100101 = Enable STOP instruction

NOTE: Before execute the STOP instruction, set this STPCON register as &quot; 10100101B &quot; .
Otherwise the STOP instruction will not execute as well as reset will be generated.

Figure 7-9. STOP Control Register (STPCON)

7-7

CLOCK CIRCUIT

S3F833B/F834B_UM_REV1.10

OSC PLL CONTROL REGISTER (OSCPLLR)
The OSC PLL control register, OSCPLLR, is located in set1, Bank1, at address D2H. It is read/write addressable
and has the following functions:
-- Pre-Scaler selection bit
-- Post-Scaler selection bit
-- System clock selection bit
-- Feedback divider selection bits

OSC PLL Control Register (OSCPLLR)
D2H, Set 1, Bank 1, R/W
MSB

.7

.6

.5

.4

OSC PLL setting bits
000001 = PLL OSC setting (4.5MHz)
000010 = PLL OSC setting (7.2MHz)
000011 = PLL OSC setting (9.0MHz)

.3

.2

.1

.0

LSB

OSC PLL operation enable bit:
0 = Disable OSC PLL
1 = Enable OSC PLL
(Phase comparator, filter and VCO are
activated)

System clock selection bit:
(when the sub oscillator is selected as system clock/OSCCON.0 = 1)
0 = Select sub OSC for system clock
1 = Select OSC PLL clock (fout) for system clock

Figure 7-10. OSC PLL Control Register (OSCPLLR)
NOTES:
1. Where fout is the OSC PLL clock.
2. When the sub oscillator is selected as system clock / OSCCON.0 = 1
3. How to switch the system clock.
Main OSC -> Sub OSC -> Main OSC -> OSC PLL -> Main OSC
(It is impossible to switch between Sub OSC and OSC PLL)

7-8

S3F833B/F834B_UM_REV1.10

CLOCK CIRCUIT

PROGRAMMING TIP - How to Switch the System Clock
The following example shows you how to switch the system clock. It is not possible to switch between Sub OSC
and OSC PLL. It is not possible to switch between Sub OSC and OSC PLL
Examples:
MAIN2OSCPLL:

; System clock is main OSC to OSC PLL clock

LD

OSCCON,#00H

OR

OSCPLLR,#07H

CALL
OR
CALL
OR

DLY200ms
OSCCON,#01H
DLY200ms
OSCCON,#08H

; Main and Sub OSC run, system clock is main
OSC
; Enable OSCPLL (4.5MHz)
; Selected as OSC PLL clock for system clock
; Delay 200ms
; Select Sub OSC for system clock
; Delay 200ms
; Stop main OSC
; The OSC PLL is run as system clock at this
point.

o
o
o

OSCPLL2MAIN:
AND
CALL
AND
NOP
NOP
NOP
AND

; System clock is OSC PLL clock to main OSC
OSCCON,#0F7H
DLY40ms
OSCCON,#0FEH

; Main OSC run
; Delay 40ms
; Select main OSC for system clock

OSCPLLR,#0FCH

; Disable OSC PLL
Main OSC for system clock

o
o
o
o
o

Dly200ms:
LD
Dly_1:

NOP
NOP
NOP
DJNZ
RET

0,#0FFH

R0,Dly_1

7-9

CLOCK CIRCUIT

S3F833B/F834B_UM_REV1.10

Dly4ms:
LD
Dly_2:

7-10

NOP
NOP
NOP
DJNZ
RET

0,#03FH

R0,Dly_2

S3F833B/F834B_UM_REV1.10

CLOCK CIRCUIT

fx

Main
OSC

0

OSCPLLR.0
fxx

Selector
Sub
OSC

75 kHz

PLLOSC

1
fxt

Selector

1

0
OSCCON.0
OSCPLLR.1

Figure 7-11. System Clock Selection Diagram

Watch Timer
LCD Controller

75 kHz

Sub OSC
75 kHz

OSCPLLR.0

fin

PLL

VCO

fvco

fout

4.5MHz
7.2MHz
9.0MHz

Feedback
Divider

To fxt
Selector

OSCPLLR.1

OSCPLLR.7-.2

Figure 7-12. OSC PLL Circuit Diagram
NOTES:
1. By a system reset, the PLL block is disabled and the 75 kHz is selected for the fxt with the PLLCON.0 = &quot; 0 &quot;
2. It should be written to the PLL output frequency, fout, as system clock.
3. If the PLL block is disabled with the PLLCON.0 = &quot; 0 &quot; , a current through the PLL block should be under 1uA.
4. The PLL block should be disabled by software before entering power down mode.

7-11

CLOCK CIRCUIT

S3F833B/F834B_UM_REV1.10

R
LPF

S3F833B/
F834B

C1

C2

VSS

Figure 7-13. LPF External Circuit Diagram

7-12

RESET and POWER-DOWN

S3F833B/F834B_UM_REV1.10

8

RESET and POWER-DOWN

SYSTEM RESET
OVERVIEW
During a power-on reset, the voltage at VDD goes to High level and the nRESET pin is forced to Low level. The
nRESET signal is input through a schmitt trigger circuit where it is then synchronized with the CPU clock. This
procedure brings the S3F833B/F834B into a known operating status.
To allow time for internal CPU clock oscillation to stabilize, the nRESET pin must be held to Low level for a
minimum time interval after the power supply comes within tolerance. The minimum required time of a reset
operation for oscillation stabilization is 1 millisecond.
Whenever a reset occurs during normal operation (that is, when both VDD and nRESET are High level), the
nRESET pin is forced Low level and the reset operation starts. All system and peripheral control registers are
then reset to their default hardware values
In summary, the following sequence of events occurs during a reset operation:
-- All interrupt is disabled.
-- The watchdog function (basic timer) is enabled.
-- Ports 0-10 and set to input mode, and all pull-up resistors are disabled for the I/O port.
-- Peripheral control and data register settings are disabled and reset to their default hardware values.
-- The program counter (PC) is loaded with the program reset address in the ROM, 0100H.
-- When the programmed oscillation stabilization time interval has elapsed, the instruction stored in ROM
location 0100H (and 0101H) is fetched and executed at normal mode by smart option.
.
NORMAL MODE RESET OPERATION
In normal (masked ROM) mode, the Test pin is tied to VSS. A reset enables access to the 64-Kbyte on-chip ROM.
NOTE
To program the duration of the oscillation stabilization interval, you make the appropriate settings to the
basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic
timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can
disable it by writing &quot; 1010B &quot; to the upper nibble of BTCON.

8-1

RESET and POWER-DOWN

S3F833B/F834B_UM_REV1.10

HARDWARE RESET VALUES
Table 8-1, 8-2, 8-3, 8-4 list the reset values for CPU and system registers, peripheral control registers, and
peripheral data registers following a reset operation. The following notation is used to represent reset values:
-- A &quot; 1 &quot; or a &quot; 0 &quot; shows the reset bit value as logic one or logic zero, respectively.
-- An &quot; x &quot; means that the bit value is undefined after a reset.
-- A dash ( &quot; - &quot; ) means that the bit is either not used or not mapped, but read 0 is the bit value.

Table 8-1. S3F833B/F834B Set 1 Register and Values After nRESET
Register Name

Basic timer control register
System clock control register
System flags register
Register pointer 0
Register pointer 1
Stack pointer (high byte)
Stack pointer (low byte)
Instruction pointer (high byte)
Instruction pointer (low byte)
Interrupt request register
Interrupt mask register
System mode register
Register page pointer

Mnemonic

Address
Dec
Hex
7
Locations D0H-D2H are not mapped.
BTCON
211
D3H
0
CLKCON
212
D4H
0
FLAGS
213
D5H
x
RP0
214
D6H
1
RP1
215
D7H
1
SPH
216
D8H
x
SPL
217
D9H
x
IPH
218
DAH
x
IPL
219
DBH
x
IRQ
220
DCH
0
IMR
221
DDH
x
SYM
222
DEH
0
PP
223
DFH
0

Bit Values After nRESET
6
5
4
3
2
1

0

0
-
x
1
1
x
x
x
x
0
x
-
0

0
-
0
-
-
x
x
x
x
0
x
0
0

0
-
0
-
-
x
x
x
x
0
x
0
0

Bit Values After nRESET
6
5
4
3
2
1
0
0
0
0
0
0
x
x
x
x
x
x
1
1
1
1
1
1
0
0
0
0
0
0
x
x
x
x
x
x
1
1
1
1
1
1

0
0
x
1
0
x
1

0
-
x
0
0
x
x
x
x
0
x
-
0

0
0
x
0
0
x
x
x
x
0
x
x
0

0
0
x
0
1
x
x
x
x
0
x
x
0

0
-
x
-
-
x
x
x
x
0
x
x
0

NOTES:
1. An 'x' means that the bit value is undefined following reset.
2. A dash ('-') means that the bit is neither used nor mapped, but the bit is read as "0".

Table 8-2. S3F833B/F834B Page 0 Register and Values After nRESET
Register Name
UART 0 Control Register
UART 0 Data Register
UART 0 Baud Rate Data Register
UART 1 Control Register
UART 1 Data Register
UART 1 Baud Rate Data Register

8-2

Mnemonic

Address
Dec Hex
7
UART0CON
0
00H
0
UDATA0
1
01H
x
BRDATA0
2
02H
1
UART1CON
3
03H
0
UDATA1
4
04H
x
BRDATA1
5
05H
1
Locations 06H-07H are not mapped.

RESET and POWER-DOWN

S3F833B/F834B_UM_REV1.10

Table 8-3. S3F833B/F834B Set 1, Bank 0 Register Values After nRESET
Register Name

Mnemonic

Address

Bit Values After nRESET

Dec

Hex

7

6

5

4

3

2

1

0

Interrupt Pending register

INTPND

208

D0H

-

-

0

0

0

0

0

0

STOP control register

STPCON

209

D1H

0

0

0

0

0

0

0

0

Oscillator control register

OSCCON

210

D2H

-

-

-

-

0

0

-

0

Timer 0 counter register

T0CNT

224

E0H

0

0

0

0

0

0

0

0

Timer 0 data register

T0DATA

225

E1H

1

1

1

1

1

1

1

1

Timer 0 control register

T0CON

226

E2H

0

0

0

0

0

0

0

0

Timer 1 counter register

T1CNT

227

E3H

0

0

0

0

0

0

0

0

Timer 1 data register

T1DATA

228

E4H

1

1

1

1

1

1

1

1

Timer 1 control register

T1CON

229

E5H

0

0

0

-

0

0

0

0

Watch timer control register

WTCON

230

E6H

0

0

0

0

0

0

0

0

SIO 0 control register

SIO0CON

231

E7H

0

0

0

0

0

0

0

0

SIO 0 data register

SIO0DATA

232

E8H

0

0

0

0

0

0

0

0

SIO 0 prescaler register

SIO0PS

233

E9H

0

0

0

0

0

0

0

0

SIO 1 control register

SIO1CON

234

EAH

0

0

0

0

0

0

0

0

SIO 1 data register

SIO1DATA

235

EBH

0

0

0

0

0

0

0

0

SIO1PS

236

ECH

0

0

0

0

0

0

0

0

SIO 1 prescaler register

Locations EDH-EEH are not mapped.
LCD control register

LCON

239

EFH

0

-

-

-

0

0

0

0

LCD mode register

LMOD

240

F0H

0

0

0

0

0

0

0

0

IF counter 2

IFCNT2

241

F1H

0

0

0

0

0

0

0

0

IF counter 1

IFCNT1

242

F2H

0

0

0

0

0

0

0

0

IF counter 0

IFCNT0

243

F3H

0

0

0

0

0

0

0

0

PLL data register 1

PLLD1

244

F4H

x

x

x

x

x

x

x

x

PLL data register 0

PLLD0

245

F5H

x

x

x

x

x

x

x

x

IF counter mode register

IFMOD

246

F6H

0

0

-

0

0

0

0

0

PLL mode register

PLLMOD

247

F7H

(note)

PLL reference frequency register

PLLREF

248

F8H

(note)

A/D Converter Control Register

ADCON

249

F9H

0

0

0

0

0

0

0

0

A/D Converter Data Register (High Byte)

ADDATAH

250

FAH

x

x

x

x

x

x

x

x

A/D Converter Data Register (Low Byte)

ADDATAL

251

FBH

-

-

-

-

-

-

x

x

0

0

0

0

0

0

0

0

x

x

x

x

x

x

x

x

Location FCH is not mapped.
Basic timer counter

BTCNT

253

FDH

Location FEH is not mapped.
Interrupt priority register

IPR

255

FFH

NOTE: Refer to the &quot; System control register chapter &quot; .

8-3

RESET and POWER-DOWN

S3F833B/F834B_UM_REV1.10

Table 8-4. S3F833B/F834B Set 1, Bank 1 Register and Values after nRESET
Register Name

Mnemonic

Address

Bit Values after nRESET

Dec

Hex

7

6

5

4

3

2

1

0

Port 10 Control Register (High Byte)

P10CONH

208

D0H

0

0

0

0

0

0

0

0

Port 10 Control Register (Low Byte)

P10CONL

209

D1H

0

0

0

0

0

0

0

0

OSC PLL Control Register

OSCPLLR

210

D2H

0

0

0

0

0

0

0

0

Port 0 Control Register (High Byte)

P0CONH

224

E0H

-

-

0

0

0

0

0

0

Port 0 Control Register (Low Byte)

P0CONL

225

E1H

0

0

0

0

0

0

0

0

Port 0 Pull-up Resistor Enable Register

P0PUR

226

E2H

-

0

0

0

0

0

0

0

Port 1 Interrupt pending Register

P1PND

227

E3H

0

0

0

0

0

0

0

0

Port 1 Control Register (High Byte)

P1CONH

228

E4H

0

0

0

0

0

0

0

0

Port 1 Control Register (Low Byte)

P1CONL

229

E5H

0

0

0

0

0

0

0

0

P1INT

230

E6H

0

0

0

0

0

0

0

0

Port 9 Control Register (High Byte)

P9CONH

231

E7H

0

0

0

0

0

0

0

0

Port 2 Control Register (High Byte)

P2CONH

232

E8H

0

0

0

0

0

0

0

0

Port 1 Interrupt Control Register

Port 2 Control Register (Low Byte)

P2CONL

233

E9H

0

0

0

0

0

0

0

0

Port 3 Control Register (High Byte)

P3CONH

234

EAH

-

-

0

0

0

0

0

0

Port 3 Control Register (Low Byte)

P3CONL

235

EBH

0

0

0

0

0

0

0

0

Port 3 Pull-up Resistor Enable Register

P3PUR

236

ECH

-

0

0

0

0

0

0

0

Port Group 0 Control Register

PG0CON

237

EDH

0

0

0

0

0

0

0

0

Port Group 1 Control Register

PG1CON

238

EEH

0

0

0

0

0

0

0

0

Port Group 2 Control Register

PG2CON

239

EFH

0

0

0

0

0

0

0

0

Port 0 Data Register

P0

240

F0H

-

0

0

0

0

0

0

0

Port 1 Data Register

P1

241

F1H

0

0

0

0

0

0

0

0

Port 2 Data Register

P2

242

F2H

0

0

0

0

0

0

0

0

Port 3 Data Register

P3

243

F3H

-

0

0

0

0

0

0

0

Port 4 Data Register

P4

244

F4H

0

0

0

0

0

0

0

0

Port 5 Data Register

P5

245

F5H

0

0

0

0

0

0

0

0

Port 6 Data Register

P6

246

F6H

0

0

0

0

0

0

0

0

Port 7 Data Register

P7

247

F7H

0

0

0

0

0

0

0

0

Port 8 Data Register

P8

248

F8H

0

0

0

0

0

0

0

0

Port 9 Data Register

P9

249

F9H

0

0

0

0

0

0

0

0

Port 10 Data Register

P10

250

FAH

0

0

0

0

0

0

0

0

Timer 2 Control Register

T2CON

251

FBH

0

0

0

-

0

0

0

0

Timer 2 Counter Register (High Byte)

T2CNTH

252

FCH

0

0

0

0

0

0

0

0

Timer 2 Counter Register (Low Byte)

T2CNTL

253

FDH

0

0

0

0

0

0

0

0

Timer 2 Data Register (High Byte)

T2DATAH

254

FEH

1

1

1

1

1

1

1

1

Timer 2 Data Register (Low Byte)

T2DATAL

255

FFH

1

1

1

1

1

1

1

1

8-4

RESET and POWER-DOWN

S3F833B/F834B_UM_REV1.10

POWER-DOWN MODES
STOP MODE
Stop mode is invoked by the instruction STOP (opcode 7FH). In Stop mode, the operation of the CPU and all
peripherals is halted. That is, the on-chip main oscillator stops and the supply current is reduced to less than
3?A. All system functions stop when the clock "freezes", but data stored in the internal register file is retained.
Stop mode can be released in one of two ways: by a reset or by interrupts, for more details see Figure 7-3.
NOTE
Do not use stop mode if you are using an external clock source because XIN input must be restricted
internally to VSS to reduce current leakage.
Using nRESET to Release Stop Mode
Stop mode is released when the nRESET signal is released and returns to high level: all system and peripheral
control registers are reset to their default hardware values and the contents of all data registers are retained. A
reset operation automatically selects a slow clock fxx/16 because CLKCON.3 and CLKCON.4 are cleared to
'00B'. After the programmed oscillation stabilization interval has elapsed, the CPU starts the system initialization
routine by fetching the program instruction stored in ROM location 0100H (and 0101H)
Using an External Interrupt to Release Stop Mode
External interrupts with an RC-delay noise filter circuit can be used to release Stop mode. Which interrupt you can
use to release Stop mode in a given situation depends on the microcontroller's current internal operating mode.
The external interrupts in the S3F833B/F834B interrupt structure that can be used to release Stop mode are:
-- External interrupts P1.0-P1.7 (INT0-INT7)
Please note the following conditions for Stop mode release:
-- If you release Stop mode using an external interrupt, the current values in system and peripheral control
registers are unchanged except STPCON register.
-- If you use an internal or external interrupt for Stop mode release, you can also program the duration of the
oscillation stabilization interval. To do this, you must make the appropriate control and clock settings before
entering Stop mode.
-- When the Stop mode is released by external interrupt, the CLKCON.4 and CLKCON.3 bit-pair setting remains
unchanged and the currently selected clock value is used.
-- The external interrupt is serviced when the Stop mode release occurs. Following the IRET from the service
routine, the instruction immediately following the one that initiated Stop mode is executed.
Using an Internal Interrupt to Release Stop Mode
Activate any enabled interrupt, causing Stop mode to be released. Other things are same as using external
interrupt.
How to Enter into Stop Mode
Handling STPCON register then writing STOP instruction (keep the order).
LD STPCON,#10100101B
STOP
NOP
NOP
NOP

8-5

RESET and POWER-DOWN

S3F833B/F834B_UM_REV1.10

IDLE MODE
Idle mode is invoked by the instruction IDLE (opcode 6FH). In idle mode, CPU operations are halted while some
peripherals remain active. During idle mode, the internal clock signal is gated away from the CPU, but all
peripherals timers remain active. Port pins retain the mode (input or output) they had at the time idle mode was
entered.
There are two ways to release idle mode:
1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents
of all data registers are retained. The reset automatically selects the slow clock fxx/16 because CLKCON.4
and CLKCON.3 are cleared to '00B'. If interrupts are masked, a reset is the only way to release idle mode.
2. Activate any enabled interrupt, causing idle mode to be released. When you use an interrupt to release idle
mode, the CLKCON.4 and CLKCON.3 register values remain unchanged, and the currently selected clock
value is used. The interrupt is then serviced. When the return-from-interrupt (IRET) occurs, the instruction
immediately following the one that initiated idle mode is executed.

8-6

S3F833B/F834B_UM_REV1.10

9

I/O PORTS

I/O PORTS

OVERVIEW
The S3F833B/F834B microcontroller has six bit-programmable, four nibble-programmable, and one wordprogrammable I/O ports, P0-P10.
The port 1, 3 are 7-bit port, and the others are 8-bit ports. This gives a total of 86 I/O pins. Each port can be
flexibly configured to meet application design requirements. The CPU accesses ports by directly writing or reading
port registers. No special I/O instructions are required. All ports of S3F833B/F834B can be configured to input or
output mode and P4-P9 are shared with LCD signals.
Table 9-1 gives you a general overview of the S3F833B/F834B I/O port functions.

9-1

I/O PORTS

S3F833B/F834B_UM_REV1.10

Table 9-1. S3F833B/F834B Port Configuration Overview
Port
0

1-bit programmable I/O port.
Schmitt trigger input or push-pull, open-drain output mode selected by software; software assignable
pull-ups.
Alternately P0.1-P0.6 can be used as T0CLK, T0CAP, T0OUT/T0PWM, T1CLK, T1OUT, T2CLK,
T2OUT, TXD1, RXD1.

1

1-bit programmable I/O port.
P1.0-P1.3 are Schmitt trigger input or push-pull output mode selected by software; software
assignable pull-ups. It can be used as inputs for external interrupts INT0-INT3 (with noise filter and
interrupt control).
P1.4-P1.7 are Input mode selected by software; software assignable pull-ups. It can be used as
inputs for external interrupts INT4-INT7 (with noise filter and interrupt control).
Alternately it can be used as AD8-AD11.

2

1-bit programmable I/O port.
Schmitt trigger input or push-pull output mode selected by software; software assignable pull-ups.
Alternately P2.0-P2.7 can be used as AD0-AD7.

3

1-bit programmable I/O port.
Input or push-pull, open-drain output mode selected by software; software assignable pull-ups.
Alternately P3.0-P3.6 can be used as BUZ, SCK0, SO0, SI0, SCK1, SO1, SI1.

4

4-bit programmable I/O port.
Input or push-pull, open drain output mode selected by software; software assignable pull-ups.
Alternately P4.0-P4.7 can be used as outputs for LCD SEG.

5

4-bit programmable I/O port.
Input or push-pull, open drain output mode selected by software; software assignable pull-ups.
Alternately P5.0-P5.7 can be used as outputs for LCD SEG.

6

4-bit programmable I/O port.
Input or push-pull, open drain output mode selected by software; software assignable pull-ups.
Alternately P6.0-P6.7 can be used as outputs for LCD SEG.

7

4-bit programmable I/O port.
Input or push-pull, open drain output mode selected by software; software assignable pull-ups.
Alternately P7.0-P7.3 can be used as outputs for LCD SEG.

8

8-bit programmable I/O port.
Schmitt trigger input or push-pull, open drain output mode selected by software; software assignable
pull-ups.
Alternately P8.0-P8.7 can be used as outputs for LCD COM/SEG.

9

1-bit or 4-bit programmable I/O port.
P9.0-P9.3 are Schmitt trigger input or push-pull, open drain output mode selected by software;
software assignable pull-ups.
P9.4-P9.7 are input or push-pull output mode selected by software; software assignable pull-ups.
Alternately P9.0-P9.7 can be used as outputs for LCD SEG, VLC0-VLC3.

10

9-2

Configuration Options

1-bit programmable I/O port.
P1.0-P1.4 are Input mode selected by software; software assignable pull-ups.
Alternately it can be used as VCOAM, VCOFM, FMIF, AMIF, and EO.
P10.5-P10.7 are input or push-pull output mode selected by software; software assignable pull-ups.
Alternately it can be used as RXD0, TXD0.

S3F833B/F834B_UM_REV1.10

I/O PORTS

PORT DATA REGISTERS
Table 9-2 gives you an overview of the register locations of all four S3F833B/F834B I/O port data registers. Data
registers for ports 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 and 10 have the general format shown in Figure 9-1.
Table 9-2. Port Data Register Summary
Register Name

Mnemonic

Decimal

Hex

Location

R/W

Port 0 data register

P0

240

F0H

Set 1, Bank 1

R/W

Port 1 data register

P1

241

F1H

Set 1, Bank 1

R/W

Port 2 data register

P2

242

F2H

Set 1, Bank 1

R/W

Port 3 data register

P3

243

F3H

Set 1, Bank 1

R/W

Port 4 data register

P4

244

F4H

Set 1, Bank 1

R/W

Port 5 data register

P5

245

F5H

Set 1, Bank 1

R/W

Port 6 data register

P6

246

F6H

Set 1, Bank 1

R/W

Port 7 data register

P7

247

F7H

Set 1, Bank 1

R/W

Port 8 data register

P8

248

F8H

Set 1, Bank 1

R/W

Port 9 data register

P9

249

F9H

Set 1, Bank 1

R/W

Port 10 data register

P10

250

FAH

Set 1, Bank 1

R/W

S3F833B/F834B I/O Port Data Register Format (n = 0-10)
MSB

.7

.6

.5

.4

.3

.2

.1

.0

Pn.7

Pn.6

Pn.5

Pn.4

Pn.3

Pn.2

Pn.1

LSB

Pn.0

Figure 9-1. S3F833B/F834B I/O Port Data Register Format

9-3

I/O PORTS

S3F833B/F834B_UM_REV1.10

PORT 0
Port 0 is a 7-bit I/O port with individually configurable pins. Port 0 pins are accessed directly by writing or reading
the port 0 data register, P0 at location F0H in set 1, bank 1. P0.0-P0.6 can serve inputs, as outputs
(push pull or open-drain) or you can configure the following alternative functions:
-- Low-nibble pins (P0.0-P0.3): T0CLK, T0OUT/T0PWM, T0CAP, T1CLK, TXD1, RXD1
-- High-nibble pins (P0.4-P0.6): T1OUT, T2CLK, T2OUT
Port 0 Control Register (P0CONH, P0CONL)
Port 0 has two 8-bit control registers: P0CONH for P0.4-P0.6 and P0CONL for P0.0-P0.3. A reset clears the
P0CONH and P0CONL registers to "00H", configuring all pins to input mode. You use control registers settings to
select Schmitt trigger input or output mode (push-pull or open drain) and enable the alternative functions.
When programming the port, please remember that any alternative peripheral I/O function you configure using the
port 0 control registers must also be enabled in the associated peripheral module.
Port 0 Pull-up Resistor Enable Register (P0PUR)
Using the port 0 pull-up resistor enable register, P0PUR (E2H, set 1, bank 1), you can configure pull-up resistors
to individual port 0 pins.

Port 0 Control Register, High Byte (P0CONH)
E0H, Set 1, Bank 1, R/W
MSB

.7

.6

.5

.4

.3

.2

P0.5/T2CLK

.1

.0

LSB

P0.4/T1OUT

P0.6/T2OUT
Not used
P0CONH bit-pair pin configuration settings:
00

Schmitt trigger input mode (T2CLK)

01

Open-drain Output mode

10

Alternative function (T1OUT, T2OUT)

11

Push-pull output mode

Figure 9-2. Port 0 High-Byte Control Register (P0CONH)

9-4

S3F833B/F834B_UM_REV1.10

I/O PORTS

Port 0 Control Register, Low Byte (P0CONL)
E1H, Set 1, Bank 1, R/W
MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P0.0/T0CLK/RXD1
P0.1/T0CAP/TXD1
P0.2/T0OUT/T0PWM
P0.3/T1CLK
P0CONL bit-pair pin configuration settings:
00

Schmitt trigger input mode (T1CLK, T0CAP, T0CLK, RXD1)

01

Open-drain Output mode

10

Alternative function (T0OUT/T0PWM, TXD1, RXD1)

11

Push-pull output mode

Figure 9-3. Port 0 Low-Byte Control Register (P0CONL)

Port 0 Pull-up Resistor Enable Register (P0PUR)
E2H, Set 1, Bank 1, R/W
MSB

.7

.6

.5

.4

.3

.2

.1

.0

P0.6

P0.5

P0.4

P0.3

P0.2

P0.1

LSB

P0.0

Not used
P0PUR bit configuration settings:
0

Pull-up Disable

1

Pull-up Enable

Figure 9-4. Port 0 Pull-up Resistor Enable Register (P0PUR)

9-5

I/O PORTS

S3F833B/F834B_UM_REV1.10

PORT 1
Port 1 is an 8-bit I/O Port that you can use two ways:
-- General-purpose I/O
-- External interrupt inputs for INT0-INT7
Port 1 is accessed directly by writing or reading the port 1 data register, P1 at location F1H in set 1, bank 1.
NOTE
The port 1 inputs can be disabled by PG2CON.5-.4 when the port is selected as input mode. Refer to the
PG2CON register.
Port 1 Control Register (P1CONH, P1CONL)
Port 1 pins are configured individually by bit-pair settings in two control registers located in set 1, bank 1:
P1CONL (low byte, E5H) and P1CONH (high byte, E4H).
When you select enable the alternative functions and output mode, a push-pull circuit is automatically configured.
In input mode, three different selections are available:
-- Input with interrupt generation on falling edges. (P1.0-.3: Schmitt trigger input)
-- Input with interrupt generation on rising edges. (P1.0-.3: Schmitt trigger input)
-- Input with interrupt generation on falling/rising edges. (P1.0-.3: Schmitt trigger input)
-- Alternative function. (P1.4-.7: AD8 - AD11)
Port 1 Interrupt Enable and Pending Registers (P1INT, P1PND)
To process external interrupts at the port 1 pins, two additional control registers are provided: the port 1 interrupt
enable register P1INT (E6H, set 1, bank 1) and the port 1 interrupt pending register P1PND (E3H, set 1, bank 1).
The port 1 interrupt pending register P1PND lets you check for interrupt pending conditions and clear the pending
condition when the interrupt service routine has been initiated. The application program detects interrupt requests
by polling the P1PND register at regular intervals.
When the interrupt enable bit of any port 1 pin is "1", a rising or falling edge at that pin will generate an interrupt
request. The corresponding P1PND bit is then automatically set to "1" and the IRQ level goes low to signal the
CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software
must the clear the pending condition by writing a "0" to the corresponding P1PND bit.

9-6

S3F833B/F834B_UM_REV1.10

I/O PORTS

Port 1 Control Register, High Byte (P1CONH)
E4H, Set 1, Bank 1, R/W
MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P1.4/INT4/AD8
P1.5/INT5/AD9
P1.6/INT6/AD10
P1.7/INT7/AD11
P1CONH bit-pair pin configuration settings:
00

Input mode, pull-up, interrupt on falling edge

01

Input mode, interrupt on rising edge

10

Input mode, interrupt on rising or falling edge

11

Alternative function (AD8-AD11)

Figure 9-5. Port 1 High-Byte Control Register (P1CONH)

Port 1 Control Register, Low Byte (P1CONL)
E5H, Set 1, Bank 1, R/W
MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT3
P1CONL bit-pair pin configuration settings:
00

Schmitt trigger input mode; pull-up, interrupt on falling edge

01

Schmitt trigger input mode; interrupt on rising edge

10

Schmitt trigger input mode; interrupt on rising or falling edge

11

Push-pull output mode

Figure 9-6. Port 1 Low-Byte Control Register (P1CONL)

9-7

I/O PORTS

S3F833B/F834B_UM_REV1.10

Port 1 Interrupt Control Resistor (P1INT)
E6H, Set 1, Bank 1, R/W
MSB

.7

.6

.5

.4

.3

.2

.1

.0

P1.7

P1.6

P1.5

P1.4

P1.3

P1.2

P1.1

LSB

P1.0

P1INT bit configuration settings:
0

Disable Interrupt

1

Enable Interrupt

Figure 9-7. Port 1 Interrupt Control Register (P1INT)

Port 1 Interrupt Pending Register (P1PND)
E3H, Set 1, Bank 1, R/W
MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

PND7 PND6 PND5 PND4 PND3 PND2 PND1 PND0

P1PND bit configuration settings:
0

Interrupt request is not pending, (when read)
pending bit clear when write 0

1

Interrupt request is pending (when read)

Figure 9-8. Port 1 Interrupt Pending Register (P1PND)

9-8

S3F833B/F834B_UM_REV1.10

I/O PORTS

PORT 2
Port 2 is an 8-bit I/O port that can be used for general-purpose I/O as A/D converter inputs, ADC0-ADC7. The
pins are accessed directly by writing or reading the port 2 data register, P2 at location F2H in set 1, bank 1.
To individually configure the port 2 pins P2.0-P2.7, you make bit-pair settings in two control registers located in
set 1, bank 1: P2CONL (low byte, E9H) and P2CONH (high byte, E8H). In input mode, ADC voltage inputs are
also available.
Port 2 Control Registers (P2CONH, P2CONL)
Two 8-bit control registers are used to configure port 2 pins: P2CONL (E9H, set 1, Bank 1) for pins P2.0-P2.3 and
P2CONH (E8H, set 1, Bank 1) for pins P2.4-P2.7. Each byte contains four bit-pairs and each bit-pair configures
one port 2 pins. The P2CONH and the P2CONL registers also control the alternative functions.

Port 2 Control Register, High Byte (P2CONH)
E8H, Set 1, Bank 1, R/W
MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P2.4/AD4
P2.6/AD6

P2.5/AD5

P2.7/AD7
P2CONH bit-pair pin configuration settings:
00
01
10
11

Schmitt trigger input mode
Schmitt trigger input mode; pull-up
Alternative function (ADC mode)
Push-pull output mode

Figure 9-9. Port 2 High-Byte Control Register (P2CONH)

9-9

I/O PORTS

S3F833B/F834B_UM_REV1.10

Port 2 Control Register, Low Byte (P2CONL)
E9H, Set 1, Bank 1, R/W
MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P2.0/AD0
P2.2/AD2

P2.1/AD1

P2.3/AD3
P2CONL bit-pair pin configuration settings:
00
01
10
11

Schmitt trigger input mode
Schmitt trigger input mode; pull-up
Alternative function (ADC mode)
Push-pull output mode

Figure 9-10. Port 2 Low-Byte Control Register (P2CONL)

9-10

S3F833B/F834B_UM_REV1.10

I/O PORTS

PORT 3
Port 3 is a 7-bit I/O port with individually configurable pins. Port 3 pins are accessed directly by writing or reading
the port 3 data register, P3 at location F3H in set 1, bank 1. P3.0-P3.6 can serve as inputs or as push-pull, opendrain outputs. You can configure the following alternative functions:
-- Low-byte pins (P3.0-P3.3): SI0, SO0, SCK0, BUZ
-- High-byte pins (P3.4-P3.6): SI1, SO1, SCK1
Port 3 Control Registers (P3CONH, P3CONL)
Port 3 has two 8-bit control registers: P3CONH for P3.4-P3.6 and P3CONL for P3.0-P3.3. A reset clears the
P3CONH and P3CONL registers to "00H", configuring all pins to input mode. You use control registers settings to
select input or output mode, enable pull-up resistors, and enable the alternative functions.
When programming this port, please remember that any alternative peripheral I/O function you configure using the
port 3 control registers must also be enabled in the associated peripheral module.

Port 3 Control Register, High Byte (P3CONH)
EAH, Set 1, Bank 1, R/W
MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P3.4/SCK1
P3.6/SI1

P3.5/SO1

Not used
P3CONH bit-pair pin configuration settings:
00
01
10
11

Input mode (SI1, SCK1)
Open-drain output mode
Alternative function (SO1, SCK1)
Push-pull output mode

Figure 9-11. Port 3 High-Byte Control Register (P3CONH)

9-11

I/O PORTS

S3F833B/F834B_UM_REV1.10

Port 3 Control Register, Low Byte (P3CONL)
EBH, Set 1, Bank 1, R/W
MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P3.0/BUZ
P3.1/SCK0
P3.2/SO0
P3.3/SI0
P3CONL bit-pair pin configuration settings:
00
01
10
11

Input mode (SI0, SCK0)
Open-drain output mode
Alternative function (SO0, SCK0, BUZ)
Push-pull output mode

Figure 9-12. Port 3 Low-Byte Control Register (P3CONL)

Port 3 Pull-up Resistor Enable Register (P3PUR)
ECH, Set 1, Bank 1, R/W
MSB

.7

.6

.5

.4

.3

.2

.1

.0

P3.6

P3.5

P3.4

P3.3

P3.2

P3.1

LSB

P3.0

Not used
P3PUR bit configuration settings:
0

Pull-up Disable

1

Pull-up Enable

Figure 9-13. Port 3 Pull-up Resistor Enable Register (P3PUR)

9-12

S3F833B/F834B_UM_REV1.10

I/O PORTS

PORT 4, 5
Port 4 and 5 are 8-bit I/O ports with nibble configurable pins, respectively. Port 4 and 5 pins are accessed directly
by writing or reading the port 4 and 5 data registers, P4 at location F4H and P5 at location F5H in set 1, bank 1.
P4.0-P4.7 and P5.0-P5.7 can serve as inputs (with or without pull-ups), as output (open drain or push-pull). And
they can serve as segment pins for LCD, also.
Port Group 0 Control Register (PG0CON)
Port 4 and 5 have a 8-bit control register: PG0CON.4-.7 for P4.0-P4.7 and PG0CON.0-.3 for P5.0-P5.7. A reset
clears the PG0CON register to "00H", configuring all pins to input mode.

Port Group 0 Control Register
EDH, Set 1, Bank 1, R/W
MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P5.4-P5.7
/SEG27-SEG24
P5.0-P5.3
/SEG31-SEG28
P4.4-P4.7
/SEG35-SEG32
P4.0-P4.3
/SEG39-SEG36
PG0CON bit-pair pin configuration settings:
00

Input mode

01

Input mode, pull-up

10

Open-drain output mode

11

Push-pull output mode

NOTE:

The shared I/O ports with LCD segments should
be selected as one of two by LCON.3-.0.

Figure 9-14. Port Group 0 Control Register (PG0CON)

9-13

I/O PORTS

S3F833B/F834B_UM_REV1.10

PORT 6, 7
Port 6 and 7 are 8-bit I/O port with nibble configurable pins, respectively. Port 6 and 7 pins are accessed directly
by writing or reading the port 6 and 7 data registers, P6 at location F6H and P7 at location F7H in set 1, bank 1.
P6.0-P6.7 and P7.0-P7.7 can serve as inputs (with or without pull-ups), as output (open drain or push-pull). And
they can serve as segment pins for LCD also.
Port Group 1 Control Register (PG1CON)
Port 6 and 7 have a 8-bit control register: PG1CON.4-.7 for P6.0-P6.7 and PG1CON.0-.3 for P7.0-P7.7. A reset
clears the PG1CON register to "00H", configuring all pins to input mode.

Port Group 1 Control Register
EEH, Set 1, Bank 1, R/W
MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P7.4-P7.7
P7.0-P7.3 /SEG11-SEG8
/SEG15-SEG12

P6.4-P6.7
/SEG19-SEG16

P6.0-P6.3
/SEG23-SEG20

PG1CON bit-pair pin configuration settings:
00

Input mode

01

Input mode, pull-up

10

Open-drain output mode

11

Push-pull output mode

NOTE:

The shared I/O ports with LCD segments should be
slelected as one of two by LCON.3-.0.

Figure 9-15. Port Group 1 Control Register (PG1CON)

9-14

S3F833B/F834B_UM_REV1.10

I/O PORTS

PORT 8, 9
Port 8 and 9 are an 8-bit I/O port with word and nibble configurable pins. Port 8 and 9 pins are accessed directly
by writing or reading the port 8 and 9 data registers, P8 at location F8H and P9 at location F9H in set 1, bank 1.
P8.0-P8.7 and P9.0-P9.3 can serve as inputs (with or without pull-ups), as output (open drain or push-pull). And
they can serve as segment pins for LCD also. P9.4-P9.7 can serve as input (with or without pull-up), as push-pull
outputs. And you can configure the following alternative functions:
-- VLC0, VLC1, VLC2, VLC3
Port Group 2 Control Register (PG2CON)
Port 8 and 9 low byte have a 8-bit control register: PG2CON.3-.2 for P8.0-P8.7 and PG2CON.1-.0 for P9.0-
P9.3. A reset clears the PG2CON register to "00H", configuring all pins to input mode.
Port 9 Control Registers (P9CONH)
Port 9 high byte has one 8-bit control registers: P9CONH for P9.4-P9.7. A reset clears the P9CONH registers to
"00H", configuring all pins to input mode. You use control registers settings to select input (with or without pull-up),
as push-pull outputs, and enable the alternative functions.

Port Group 2 Control Register
EFH, Set 1, Bank 1, R/W
MSB

.7

.6

.5

.4

SIO1 output control bit:
0 = SO1, SCK1 output is selected
as push-pull.
1 = SO1, SCK1 output is selected
as open-drain.

.3

.2

.1

.0

LSB

P9.0-P9.3
/SEG7-SEG4
P8.0-P8.3/SEG0-3/COM7-4
and P8.4-P8.7/COM3-0

SIO0 output control bit:
0 = SO0, SCK0 output is selected
as push-pull.
1 = SO0, SCK0 output is selected
as open-drain.

P1.0-P1.3 input enable bit:
0: Enable port 1.0-1.3 input
1: Disable port 1.0-1.3 input

P1.4-P1.7 input enable bit:
0: Enable port 1.4-1.7 input
1: Disable port 1.4-1.7 input
PG2CON bit-pair pin configuration settings:
00

Input mode

01

Input mode, pull-up

10

Open-drain output mode

11

Push-pull output mode

NOTE:

The shared I/O ports with LCD segments should be
slelected as one of two by LCON.3-.0.

Figure 9-16. Port Group 2 Control Register (PG2CON)

9-15

I/O PORTS

S3F833B/F834B_UM_REV1.10

Port 9 Control Register, High Byte (P9CONH)
E7H, Set 1, Bank 1, R/W
MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P9.4/VLC3
P9.5/VLC2
P9.6/VLC1
P9.7/VLC0

P9CONH bit-pair pin configuration settings:
00

Input mode

01

Input mode, pull-up

10

Alternative function (VLC0-VLC3)

11

Push-pull output mode

Figure 9-17. Port 9 High-byte Control Register (P9CONH)

9-16

S3F833B/F834B_UM_REV1.10

I/O PORTS

PORT 10
Port 10 is an 8-bit I/O port with individually configurable pins. Port 10 pins are accessed directly by writing or
reading the port 10 data register, P10 at location FAH in set 1, bank 1. P10.5-P10.7 can serve as inputs (with
without pull-ups), as push-pull outputs. And you can configure the following alternative functions:
-- TXD0, RXD0
P10.0-P10.4 can serve as inputs (with or without pull-ups). And you can configure the following alternative
functions:
-- EO, FMIF, AMIF, VCOFM, VCOAM
Port 10 Control Register (P10CONH, P10CONL)
Port 10 has two 8-bit control registers: P10CONH for P10.4-P10.7 and P10CONL for P10.0-P10.3. A reset clears
the P10CONH and P10CONL registers to "00H", configuring all pins to input mode. You use control registers
settings to select input (with or without pull-ups) or push-pull output mode and enable the alternative functions.
When programming the port, please remember that any alternative peripheral I/O function you configure using the
port 10 control registers must also be enabled in the associated peripheral module.

Port 10 Control Register, High Byte (P10CONH)
D1H, Set 1, Bank 1, R/W
MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P10.4/EO
P10.5/RXD0
P10.6/TXD0
P10.7

P10CONH bit-pair pin configuration settings:
00

Input mode, pull-up

10

Alternative function (TXD0, RXD0, EO)

11

NOTE:

Input mode (RXD0)

01

Push-pull output mode

W hen you selected PLL mode enable, P10.4 is
automatically selected to &quot; Alternative function &quot; .

Figure 9-18. Port 10 High-Byte Control Register (P10CONH)

9-17

I/O PORTS

S3F833B/F834B_UM_REV1.10

Port 10 Control Register, Low Byte (P10CONL)
D2H, Set 1, Bank 1, R/W
MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P10.0/VCOFM
P10.1/VCOAM
P10.2/AMIF
P10.3/FMIF
P10CONL bit-pair pin configuration settings:
00
01

Input mode, pull-up

10

Alternative function (AMIF, FMIF, VCOAM, VCOFM)

11

NOTES:

Input mode

Not available

1. When you selected IFC mode enable, P10.2 and P10.3 are
automatically selected to &quot; Alternative function &quot; .
2. When you selected PLL mode enable, P10.0, P10.1 and P10.4
are automatically selected to &quot; Alternative function &quot; .

Figure 9-19. Port 10 Low-Byte Control Register (P10CONL)

9-18

S3F833B/F834B_UM_REV1.10

10

BASIC TIMER and TIMER 0

BASIC TIMER AND TIMER 0

OVERVIEW
The S3F833B/F834B has two default timers: an 8-bit basic timer and one 8-bit general-purpose timer/counter.
The 8-bit timer/counter is called timer 0.

BASIC TIMER (BT)
You can use the basic timer (BT) in two different ways:
-- As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction.
-- To signal the end of the required oscillation stabilization interval after a reset or a stop mode release.
The functional components of the basic timer block are:
-- Clock frequency divider (fxx divided by 4096, 1024, 128, or 16) with multiplexer
-- 8-bit basic timer counter, BTCNT (set 1, bank 0, FDH, read-only)
-- Basic timer control register, BTCON (set 1, D3H, read/write)

10-1

BASIC TIMER and TIMER 0

S3F833B/F834B_UM_REV1.10

BASIC TIMER CONTROL REGISTER (BTCON)
The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer
counter and frequency dividers, and to enable or disable the watchdog timer function. It is located in set 1,
address D3H, and is read/write addressable using Register addressing mode.
A reset clears BTCON to "00H". This enables the watchdog function and selects a basic timer clock frequency of
fxx/4096. To disable the watchdog function, you must write the signature code "1010B" to the basic timer register
control bits BTCON.7-BTCON.4.
The 8-bit basic timer counter, BTCNT (set 1, bank 0, FDH), can be cleared at any time during normal operation by
writing a &quot; 1 &quot; to BTCON.1. To clear the frequency dividers for all timers input clock, you write a &quot; 1 &quot; to BTCON.0.

Basic TImer Control Register (BTCON)
D3H, Set 1, R/W
MSB

.7

.6

.5

.4

.3

Watchdog timer enable bits:
1010B
= Disable watchdog function
Other value = Enable watchdog function

.2

.1

.0

LSB

Divider clear bit:
0 = No effect
1= Clear dvider (Automatically cleared to &quot; 0 &quot; )
Basic timer counter clear bit:
0 = No effect
1= Clear BTCNT (Automatically cleared to &quot; 0 &quot; )

Basic timer input clock selection bits:
00 = fXX/4096
01 = fXX/1024
10 = fXX/128
11 = fXX/16

Figure 10-1. Basic Timer Control Register (BTCON)

10-2

S3F833B/F834B_UM_REV1.10

BASIC TIMER and TIMER 0

BASIC TIMER FUNCTION DESCRIPTION
Watchdog Timer Function
You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7-BTCON.4 to
any value other than "1010B". (The "1010B" value disables the watchdog function.) A reset clears BTCON to
"00H", automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by
the current CLKCON register setting), divided by 4096, as the BT clock.
A reset whenever a basic timer counter overflow occurs. During normal operation, the application program must
prevent the overflow, and the accompanying reset operation, from occurring. To do this, the BTCNT value must
be cleared (by writing a &quot; 1 &quot; to BTCON.1) at regular intervals.
If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation
will not be executed and a basic timer overflow will occur, initiating a reset. In other words, during normal
operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always broken
by a BTCNT clear instruction. If a malfunction does occur, a reset is triggered automatically.
Oscillation Stabilization Interval Timer Function
You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when
stop mode has been released by an external interrupt.
In stop mode, whenever a reset or an internal and an external interrupt occurs, the oscillator starts. The BTCNT
value then starts increasing at the rate of fxx/4096 (for reset), or at the rate of the preset clock source (for an
internal and an external interrupt). When BTCNT.3 overflows, a signal is generated to indicate that the
stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal
operation.
In summary, the following events occur when stop mode is released:
1. During stop mode, a power-on reset or an internal and an external interrupt occurs to trigger the stop mode
release and oscillation starts.
2. If a power-on reset occurred, the basic timer counter will increase at the rate of fxx/4096. If an internal and an
external interrupt is used to release stop mode, the BTCNT value increases at the rate of the preset clock
source.
3. Clock oscillation stabilization interval begins and continues until bit 3 of the basic timer counter overflows.
4. When a BTCNT.3 overflow occurs, normal CPU operation resumes.

10-3

BASIC TIMER and TIMER 0

S3F833B/F834B_UM_REV1.10

RESETor STOP
Bit 1
Bits 3, 2

Basic Timer Control Register
(Write '1010xxxxB' to Disable)
Data Bus

fXX/4096

Clear

fXX/1024
fXX

DIV

fXX/128

MUX

8-Bit Up Counter
(BTCNT, Read-Only)

OVF

fXX/16
R

Start the CPU (note)

Bit 0

NOTE:

During a power-on reset operation, the CPU is idle during the required oscillation
stabilization interval (until bit 4 of the basic timer counter overflows).

Figure 10-2. Basic Timer Block Diagram

10-4

RESET

S3F833B/F834B_UM_REV1.10

BASIC TIMER and TIMER 0

8-BIT TIMER/COUNTER 0
Timer/counter 0 has three operating modes, one of which you select using the appropriate T0CON setting:
-- Interval timer mode
-- Capture input mode with a rising or falling edge trigger at the P0.1 pin
-- PWM mode
Timer/counter 0 has the following functional components:
-- Clock frequency divider (fxx divided by 1024, 256, 64, 8, or 1) with multiplexer
-- External clock input (P0.0, T0CLK)
-- 8-bit counter (T0CNT), 8-bit comparator, and 8-bit reference data register (T0DATA)
-- I/O pins for capture input, match output, or PWM output (P0.1/T0CAP, P0.2/T0OUT/T0PWM)
-- Timer 0 overflow interrupt (IRQ0, vector E2H) and match/capture interrupt (IRQ0, vector E0H) generation
-- Timer 0 control register, T0CON (set 1, E2H, bank 0, read/write)

TIMER/COUNTER 0 CONTROL REGISTER (T0CON)
You use the timer 0 control register, T0CON, to
-- Select the timer 0 operating mode (interval timer, capture mode, or PWM mode)
-- Select the timer 0 input clock frequency
-- Clear the timer 0 counter, T0CNT
-- Enable the timer 0 overflow interrupt or timer 0 match/capture interrupt
-- Clear timer 0 match/capture interrupt pending condition

10-5

BASIC TIMER and TIMER 0

S3F833B/F834B_UM_REV1.10

T0CON is located in set 1, bank 0, at address E2H, and is read/write addressable using Register addressing
mode.
A reset clears T0CON to "00H". This sets timer 0 to normal interval timer mode, selects an input clock frequency
of fxx/1024, and disables all timer 0 interrupts. You can clear the timer 0 counter at any time during normal
operation by writing a &quot; 1 &quot; to T0CON.2.
The timer 0 overflow interrupt (T0OVF) is interrupt level IRQ0 and has the vector address E2H. When a timer 0
overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by hardware
or must be cleared by software.
To enable the timer 0 match/capture interrupt (IRQ0, vector E0H), you must write T0CON.1 to &quot; 1 &quot; . To detect a
match/capture interrupt pending condition, the application program polls INTPND.1. When a &quot; 1 &quot; is detected, a
timer 0 match or capture interrupt is pending. When the interrupt request has been serviced, the pending
condition must be cleared by software by writing a &quot; 0 &quot; to the timer 0 match/capture interrupt pending bit,
INTPND.1.

Timer 0 Control Register (T0CON)
E2H, Set 1, Bank 0, R/W
MSB

.7

.6

.5

Timer 0 input clock selection bits:
000 = fxx/1024
001 = fxx/256
010 = fxx/64
011 = fxx/8
100 = fxx
101 = External clock
(P0.0/T0CLK) falling edge
110 = External clock
(P0.0/T0CLK) rising edge
111 = Counter stop

.4

.3

.2

.1

.0

LSB

Timer 0 overflow interrupt enable bit:
0 = Disable overflow interrupt
1 = Enable overflow interrupt
Timer 0 match/capture interrupt enable bit:
0 = Disable interrupt
1 = Enable interrupt
Timer 0 counter clear bit:
0 = No effect
1 = Clear the timer 0 counter (when write)

Timer 0 operating mode selection bits:
00 = Interval mode (P0.2/T0OUT)
01 = Capture mode (capture on rising edge,
counter running, OVF can occur)
10 = Capture mode (capture on falling edge,
counter running, OVF can occur)
11 = PWM mode (OVF and match
interrupt can occur)

Figure 10-3. Timer 0 Control Register (T0CON)

10-6

S3F833B/F834B_UM_REV1.10

BASIC TIMER and TIMER 0

Interrupt Pending Register (INTPND)
D0H, Set 1, Bank 0, R/W
MSB

.7

.6

.5

.4

.3

.2

Not used

.1

.0

LSB

Timer 0 overflow interrupt pending bit:
Timer 0 match/capture pending bit:
Tx interrupt pending bit (for UART0):
Rx interrupt pending bit (for UART0):
Tx interrupt pending bit (for UART1):
Rx interrupt pending bit (for UART1):

INTPND bit configuration settings:
0

Interrupt request is not pending, (when read)
pending bit clear when write 0

1

Interrupt request is pending (when read)

Figure 10-4. Interrupt Pending Register (INTPND)

10-7

BASIC TIMER and TIMER 0

S3F833B/F834B_UM_REV1.10

TIMER 0 FUNCTION DESCRIPTION
Timer 0 Interrupts (IRQ0, Vectors E0H and E2H)
The timer 0 can generate two interrupts: the timer 0 overflow interrupt (T0OVF), and the timer 0 match/ capture
interrupt (T0INT). T0OVF is belongs to interrupt level IRQ0, vector E2H. T0INT also belongs to interrupt level
IRQ0, but is assigned the separate vector address, E0H.
A timer 0 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced or
should be cleared by software in the interrupt service routine by writing a "0" to the INTPND.0 interrupt pending
bit. However, the timer 0 match/capture interrupt pending condition must be cleared by the application's interrupt
service routine by writing a &quot; 0 &quot; to the INTPND.1 interrupt pending bit.
Interval Timer Mode
In interval timer mode, a match signal is generated when the counter value is identical to the value written to the
timer 0 reference data register, T0DATA. The match signal generates a timer 0 match interrupt (T0INT, vector
E0H) and clears the counter.
If, for example, you write the value &quot; 10H &quot; to T0DATA, the counter will increment until it reaches "10H". At this
point, the timer 0 interrupt request is generated, the counter value is reset, and counting resumes. With each
match, the level of the signal at the timer 0 output pin is inverted (see Figure 10-5).

Interrupt Enable/Disable

Capture Signal
CLK

8-Bit Up Counter

8-Bit Comparator

T0CON.1

R (Clear)

M
U
X

Match

T0INT (IRQ0)
INTPND.1

(Match INT)

Pending
T0OUT (P0.2)

Timer 0 Buffer Register

T0CON.4-.3
Match Signal
T0CON.2
T0OVF

Timer 0 Data Register

Figure 10-5. Simplified Timer 0 Function Diagram: Interval Timer Mode

10-8

S3F833B/F834B_UM_REV1.10

BASIC TIMER and TIMER 0

Pulse Width Modulation Mode
Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the
T0PWM (P0.2) pin. As in interval timer mode, a match signal is generated when the counter value is identical to
the value written to the timer 0 data register. In PWM mode, however, the match signal does not clear the counter.
Instead, it runs continuously, overflowing at &quot; FFH &quot; , and then continues incrementing from &quot; 00H &quot; .
Although you can use the match signal to generate a timer 0 overflow interrupt, interrupts are not typically used in
PWM-type applications. Instead, the pulse at the T0PWM (P0.2) pin is held to Low level as long as the reference
data value is less than or equal to ( <= ) the counter value and then the pulse is held to High level for as long as the
data value is greater than ( &amp; gt; ) the counter value. One pulse width is equal to tCLK × 256 (see Figure 10-6).

T0CON.0

Capture Signal

Interrupt Enable/Disable
T0CON.1

T0OVF(IRQ0)
CLK

8-Bit Up Counter

8-Bit Comparator

INTPND.0

(Overflow INT)
M
U
X

Match

Timer 0 Buffer Register

T0INT (IRQ0)
INTPND.1
Pending

T0CON.4-.3
Match Signal
T0CON.2
T0OVF

(Match INT)
T0PWM
Output (P0.2)
High level when
data &amp; gt; counter,
Lower level when
data &amp; lt; counter

Timer 0 Data Register

Figure 10-6. Simplified Timer 0 Function Diagram: PWM Mode

10-9

BASIC TIMER and TIMER 0

S3F833B/F834B_UM_REV1.10

Capture Mode
In capture mode, a signal edge that is detected at the T0CAP (P0.1) pin opens a gate and loads the current
counter value into the timer 0 data register. You can select rising or falling edges to trigger this operation.
Timer 0 also gives you capture input source: the signal edge at the T0CAP (P0.1) pin. You select the capture
input by setting the values of the timer 0 capture input selection bits in the port 0 control register, P0CONL.3-.2,
(set 1, bank 1, E1H). When P0CONL.3-.2 is &quot; 00 &quot; , the T0CAP input is selected.
Both kinds of timer 0 interrupts can be used in capture mode: the timer 0 overflow interrupt is generated whenever
a counter overflow occurs; the timer 0 match/capture interrupt is generated whenever the counter value is loaded
into the timer 0 data register.
By reading the captured data value in T0DATA, and assuming a specific value for the timer 0 clock frequency, you
can calculate the pulse width (duration) of the signal that is being input at the T0CAP pin (see Figure 10-7).

T0CON.0
T0OVF(IRQ0)
CLK

8-Bit Up Counter

INTPND.0

(Overflow INT)

Interrupt Enable/Disable
T0CON.1

T0CAP input
(P0.1)

Match Signal
T0CON.4-.3

M
U
X

T0INT (IRQ0)
INTPND.1
Pending

T0CON.4-.3
Timer 0 Data Register

Figure 10-7. Simplified Timer 0 Function Diagram: Capture Mode

10-10

(Capture INT)

S3F833B/F834B_UM_REV1.10

BASIC TIMER and TIMER 0

T0CON.0
T0CON.7-.5
Data BUS
fxx/1024
fxx/256
fxx/64
fxx/8
fxx/1

8

MUX
T0CLK

8-Bit Up Counter
R
(Read-Only)

T0OVF
(IRQ0)

INTPND.0

OVF

T0CON.2
Clear
T0CON.1

8-Bit Comparator
Match

T0CAP

M
U
X

T0INT

M
U
X

INTPND.1

(IRQ0)
T0OUT/
T0PWM

Timer 0 Buffer Register
T0CON.4-.3
Match signal
T0CON.2
T0OVF

T0CON.4-.3
Timer 0 Data Register
8
Data BUS

Figure 10-8. Timer 0 Block Diagram

10-11

BASIC TIMER and TIMER 0

S3F833B/F834B_UM_REV1.10

NOTES

10-12

S3F833B/F834B_UM_REV1.10

11

8-BIT TIMER 1

8-BIT TIMER 1

OVERVIEW
The 8-bit timer 1 is an 8-bit general-purpose timer. Timer 1 has the interval timer mode by using the appropriate
T1CON setting.
Timer 1 has the following functional components:
-- Clock frequency divider (fxx divided by 256, 64, 8 or 1) with multiplexer
-- External clock input (P0.3/T1CLK)
-- 8-bit counter (T1CNT), 8-bit comparator, and 8-bit reference data register (T1DATA)
-- Timer 1 interrupt (IRQ1, vector E6H) generation
-- Timer 1 control register, T1CON (set 1, Bank 0, E5H, read/write)

FUNCTION DESCRIPTION
Interval Timer Function
The timer 1 can generate an interrupt, the timer 1 match interrupt (T1INT). T1INT belongs to interrupt level IRQ1,
and is assigned the separate vector address, E6H.
The T1INT pending condition should be cleared by software when it has been serviced. Even though T1INT is
disabled, the application's service routine can detect a pending condition of T1INT by the software and execute
it's sub-routine. When this case is used, the T1INT pending bit must be cleared by the application subroutine by
writing a "0" to the T1CON.0 pending bit.
In interval timer mode, a match signal is generated when the counter value is identical to the values written to the
Timer 1 reference data registers, T1DATA. The match signal generates a timer 1 match interrupt (T1INT, vector
E6H) and clears the counter.
If, for example, you write the value 10H to T1DATA and 0EH to T1CON, the counter will increment until it reaches
10H. At this point, the Timer 1 interrupt request is generated, the counter value is reset, and counting resumes.

11-1

8-BIT TIMER 1

S3F833B/F834B_UM_REV1.10

TIMER 1 CONTROL REGISTER (T1CON)
You use the timer 1 control register, T1CON, to
-- Enable the timer 1 operating (interval timer)
-- Select the timer 1 input clock frequency
-- Clear the timer 1 counter, T1CNT
-- Enable the timer 1 interrupt and clear timer 1 interrupt pending condition
T1CON is located in set 1, bank 0, at address E5H, and is read/write addressable using register addressing
mode.
A reset clears T1CON to &quot; 00H &quot; . This sets timer 1 to disable interval timer mode, and disables timer 1 interrupt.
You can clear the timer 1 counter at any time during normal operation by writing a "1" to T1CON.3
To enable the timer 1 interrupt (IRQ1, vector E6H), you must write T1CON.2, and T1CON.1 to &quot; 1 &quot; . To detect an
interrupt pending condition when T1INT is disabled, the application program polls pending bit, T1CON.0. When a
&quot; 1 &quot; is detected, a timer 1 interrupt is pending. When the T1INT sub-routine has been serviced, the pending
condition must be cleared by software by writing a &quot; 0 &quot; to the timer 1 interrupt pending bit, T1CON.0.

Timer 1 Control Register
E5H, Set 1, Bank 0, R/W
MSB

.7

.6

.5

Timer 1 input clock selection bits:
000 = fxx/256
001 = fxx/64
010 = fxx/8
011 = fxx
111=External clock (T1CLK) input
Not used
Timer 1 counter clear bit:
0 = No affect
1 = Clear the timer 1 counter
(when write)

.4

.3

.2

.1

.0

LSB

Timer 1 interrupt pending bit:
0 = Interrupt request is not pending, (when read)
pending bit clear when write 0
1 = Interrupt is pending
Timer 1 interrupt enable bit:
0 = Disable interrupt
1 = Enable interrupt
Timer 1 count enable bit:
0 = Disable counting operation
1 = Enable counting operation

Figure 11-1. Timer 1 Control Register (T1CON)

11-2

S3F833B/F834B_UM_REV1.10

8-BIT TIMER 1

BLOCK DIAGRAM

T1CON.7-.5
Data Bus
T1CON.3

8
fxx/256
M

fxx/64
fxx/8

U

fxx/1
T1CLK

8-bit up-Counter
(Read Only)

R

X

Clear
Pending
8-bit Comparator

T1CON.0
Match

T1INT
IRQ1

T1CON.2
T1CON.1
Timer 1 Buffer Register
T1OUT
Counter clear signal
(T1CON.3) only

Timer 1 Data Register
(Read/Write)

8
Data Bus
NOTE:

To be loaded T1DATA value to buffer register for comparing, T1CON.3 bit must be set 1.

Figure 11-2. Timer 1 Functional Block Diagram

11-3

8-BIT TIMER 1

S3F833B/F834B_UM_REV1.10

NOTES

11-4

S3F833B/F834B_UM_REV1.10

12

16-BIT TIMER 2

16-BIT TIMER 2

OVERVIEW
The 16-bit timer 2 is an 16-bit general-purpose timer. Timer 2 has the interval timer mode by using the
appropriate T2CON setting.
Timer 2 has the following functional components:
-- Clock frequency divider (fxx divided by 256, 64, 8 or 1) with multiplexer
-- External clock input (T2CLK)
-- 16-bit counter (T2CNTH/L), 16-bit comparator, and 16-bit reference data register (T2DATAH/L)
-- Timer 2 interrupt (IRQ1, vector E4H) generation
-- Timer 2 control register, T2CON (set 1, Bank 1, FBH, read/write)

FUNCTION DESCRIPTION
Interval Timer Function
The timer 2 can generate an interrupt, the timer 2 match interrupt (T2INT). T2INT belongs to interrupt level IRQ1,
and is assigned the separate vector address, E4H.
The T2INT pending condition should be cleared by software when it has been serviced. Even though T2INT is
disabled, the application's service routine can detect a pending condition of T2INT by the software and execute
it's sub-routine. When this case is used, the T2INT pending bit must be cleared by the application subroutine by
writing a "0" to the T2CON.0 pending bit.
In interval timer mode, a match signal is generated when the counter value is identical to the values written to the
Timer 2 reference data registers, T2DATA. The match signal generates a timer 2 match interrupt (T2INT, vector
E4H) and clears the counter.
If, for example, you write the value 0010H to T2DATAH/L and 0EH to T2CON, the counter will increment until it
reaches 10H. At this point, the Timer 2 interrupt request is generated, the counter value is reset, and counting
resumes.

12-1

16-BIT TIMER 2

S3F833B/F834B_UM_REV1.10

TIMER 2 CONTROL REGISTER (T2CON)
You use the timer 2 control register, T2CON, to
-- Enable the timer 2 operating (interval timer)
-- Select the timer 2 input clock frequency
-- Clear the timer 2 counter, T2CNTH/L
-- Enable the timer 2 interrupt and clear timer 2 interrupt pending condition
T2CON is located in set 1, bank 1, at address FBH, and is read/write addressable using register addressing
mode.
A reset clears T2CON to &quot; 00H &quot; . This sets timer 2 to disable interval timer mode, and disables timer 2 interrupt.
You can clear the timer 2 counter at any time during normal operation by writing a "1" to T2CON.3
To enable the timer 2 interrupt (IRQ1, vector E4H), you must write T2CON.2, and T2CON.1 to &quot; 1 &quot; . To detect an
interrupt pending condition when T2INT is disabled, the application program polls pending bit, T2CON.0. When a
&quot; 1 &quot; is detected, a timer 2 interrupt is pending. When the T2INT sub-routine has been serviced, the pending
condition must be cleared by software by writing a &quot; 0 &quot; to the timer 2 interrupt pending bit, T2CON.0.

Timer 2 Control Registers
FBH, Set 1, Bank 1, R/W
MSB

.7

.6

.5

.4

Timer 0 input clock selection bits:
000 = fxx/256
001 = fxx/64
010 = fxx/8
011 = fxx
111 = External clock (T2CLK) input

.3

.2

.1

.0

LSB

Timer 2 interrupt pending bit:
0 = Interrupt request is not pending, (when read)
pending bit clear when write 0
1 = Interrupt is pending
Timer 2 interrupt enable bit:
0 = Disable interrupt
1 = Enable interrupt
Not used

Timer 2 count enable bit:
0 = Disable counting operation
1 = Enable counting operation

Timer 2 counter clear bit:
0 = No affect
1 = Clear the timer 2 counter (when write)

Figure 12-1. Timer 2 Control Register (T2CON)

12-2

S3F833B/F834B_UM_REV1.10

16-BIT TIMER 2

BLOCK DIAGRAM

T2CON.7-.5
Data Bus
T2CON.3

8
fxx/256
fxx/64

M

fxx/8

U

fxx/1
T2CLK

16-bit up-Counter
(Read Only)

R

X

Clear
Pending
16-bit Comparator

T2CON.0
Match

T2INT
IRQ1

T2CON.2
T2CON.1
Timer 2 Buffer Register
T2OUT
Counter clear signal (T2CON.3) only

Timer 2 Data Register
(Read/Write)

8
Data Bus
NOTE:

To be loaded T2DATAH/L value to buffer register for comparing, T2CON.3 bit must be set 1.

Figure 12-2. Timer 2 Functional Block Diagram

12-3

16-BIT TIMER 2

S3F833B/F834B_UM_REV1.10

NOTES

12-4

S3F833B/F834B_UM_REV1.10

13

WATCH TIMER

WATCH TIMER

OVERVIEW
Watch timer functions include real-time and watch-time measurement and interval timing for the system clock. To
start watch timer operation, set bit 1 of the watch timer control register, WTCON.6 to &quot; 1 &quot; .
And if you want to service watch timer overflow interrupt (IRQ3, vector F8H), then set the WTCON.1 to "1".
The watch timer overflow interrupt pending condition (WTCON.0) must be cleared by software in the application's
interrupt service routine by means of writing a &quot; 0 &quot; to the WTCON.0 interrupt pending bit.
After the watch timer starts and elapses a time, the watch timer interrupt pending bit (WTCON.0) is automatically
set to &quot; 1 &quot; , and interrupt requests commence in 50 ms, 0.1, 0.5 and 1-second intervals by setting Watch timer
speed selection bits (WTCON.3-.2).
The watch timer can generate a steady 0.47 kHz, 0.94 kHz, 1.87 kHz, or 3.75 kHz signal to BUZ output pin for
Buzzer. By setting WTCON.3 and WTCON.2 to &quot; 11b &quot; , the watch timer will function in high-speed mode,
generating an interrupt every 50 ms. High-speed mode is useful for timing events for program debugging
sequences.
The watch timer supplies the clock frequency for the LCD controller (fLCD). Therefore, if the watch timer is
disabled, the LCD controller does not operate.
Watch timer has the following functional components:
-- Real Time and Watch-Time Measurement
-- Using a Main Clock Source or Sub clock
-- Clock Source Generation for LCD Controller (fLCD)
-- I/O pin for Buzzer Output Frequency Generator (BUZ)
-- Timing Tests in High-Speed Mode
-- Watch timer overflow interrupt (IRQ3, vector F8H) generation
-- Watch timer control register, WTCON (set 1, bank 0, E6H, read/write)

13-1

WATCH TIMER

S3F833B/F834B_UM_REV1.10

WATCH TIMER CONTROL REGISTER (WTCON)
The watch timer control register, WTCON is used to select the watch timer interrupt time and Buzzer signal, to
enable or disable the watch timer function. It is located in set 1, bank 0 at address E6H, and is read/write
addressable using register addressing mode.
A reset clears WTCON to &quot; 00H &quot; . This disable the watch timer.
So, if you want to use the watch timer, you must write appropriate value to WTCON.

Watch Timer Control Register (WTCON)
E6H, Set 1, Bank 0, R/W
MSB .7

.6

.5

.4

Watch timer clock selection bit:
0 = Select main clock divided by 60 (fx/60)
1 = Select sub clock (fxt)
Watch timer Enable/Disable bit:
0 = Disable watch timer
1 = Enable watch timer
Buzzer signal selection bits:
00 = 0.47 kHz
01 = 0.94 kHz
10 = 1.87 kHz
11 = 3.75 kHz

.3

.2

.1

.0

LSB

Watch timer interrupt pending bit:
0 = Interrupt request is not pending;(when read)
pending bit clear when write 0
1 = Interrupt request is pending (when read)
Watch timer Interrupt Enable/Disable bit:
0 = Disable watch timer Interrupt
1 = Enable watch timer Interrupt
Watch timer speed selection bits:
00 = Set watch timer interrupt to 1.0 s
01 = Set watch timer interrupt to 0.5 s
10 = Set watch timer interrupt to 0.1 s
11 = Set watch timer interrupt to 50 ms

Figure 13-1. Watch Timer Control Register (WTCON)

13-2

S3F833B/F834B_UM_REV1.10

WATCH TIMER

WATCH TIMER CIRCUIT DIAGRAM

WTCON.7
WTCON.6

Enable /Disable
BUZ

WTCON.5
MUX

WTCON.4
8

0.47 kHz
0.94 kHz
1.87 kHz
3.75 kHz

WTCON.3
WTCON.2

WTCON.1
WTINT

SELECTOR
CIRCUIT

WTCON.1
INT Enable /Disable

WTCON.0

IRQ 3

WTCON.0
(Pending bit)

1 Sec

CLOCK
SELECTOR

fxt

fxw/60

fw

FREQUENCY 0.5 Sec
0.1 Sec
DIVIDING
50 mSec
CIRCUIT
fLCD=1875Hz
fxw = 4.5MHz (Where fx=4.5MHz and IFMOD.7-.6 = 00)
= 4.5MHz (Where fx=9.0MHz and IFMOD.7-.6 = 01)
= 4.5MHz (Where fx=7.2MHz and IFMOD.7-.6 = 10)
fxt = Sub clock (75kHz)
fw = Watch timer frequency (75KHz)

Figure 13-2. Watch Timer Circuit Diagram

13-3

WATCH TIMER

S3F833B/F834B_UM_REV1.10

NOTES

13-4

S3F833B/F834B_UM_REV1.10

14

LCD CONTROLLER/DRIVER

LCD CONTROLLER/DRIVER

OVERVIEW
The S3F833B/F834B microcontroller can directly drive an up-to-288-dot (36 segments x 8 commons) LCD panel.
Its LCD block has the following components:
-- LCD controller/driver
-- Display RAM for storing display data
-- 4 common/segment output pins (COM4/SEG0-COM7/SEG3)
-- 36 segment output pins (SEG4-SEG39)
-- 4 common output pins (COM0-COM3)
-- Four LCD operating power supply pins (VLC0-VLC3)
-- LCD bias by internal/external register
The LCD control register, LCON, is used to turn the LCD display on and off, switch the current to the dividing
resistors for the LCD display, and frame frequency. Data written to the LCD display RAM can be automatically
transferred to the segment signal pins without any program control.
When a subsystem clock is selected as the LCD clock source, the LCD display is enabled even in the main clock
stop or idle mode.

VLC0-VLC3
4
8-Bit Data Bus

LCD
Controller/

8

COM0-COM3
4

Driver
4

COM4-COM7
/SEG0-SEG3
SEG4-SEG39

36

Figure 14-1. LCD Function Diagram

14-1

LCD CONTROLLER/DRIVER

S3F833B/F834B_UM_REV1.10

LCD CIRCUIT DIAGRAM

Port
Latch

Display
RAM
(Page 9)

SEG39/P4.0
SEG38/P4.1

36
MUX
40

36

Selector

Data Bus

SEG5/P9.2
SEG4/P9.3

4

LCON

4

COM
Control
or
Selector

COM7/SEG3/P8.0
COM6/SEG2/P8.1

COM4/SEG0/P8.3
fLCD

LMOD

Timing
Controller

4

COM
Control
or
Selector

COM3/P8.4
COM2/P8.5

COM0/P8.7
VLC3
LCD
Voltage
Control
VLC0

Figure 14-2. LCD Circuit Diagram

14-2

S3F833B/F834B_UM_REV1.10

LCD CONTROLLER/DRIVER

LCD RAM ADDRESS AREA
RAM addresses of page 9 are used as LCD data memory. These locations can be addressed by 1-bit or 8-bit
instructions. If the bit value of a display segment is &quot; 1 &quot; , the LCD display is turned on. If the bit value is &quot; 0 &quot; , the
display is turned off.
Display RAM data are sent out through the segment pins, SEG0-SEG39, using the direct memory access (DMA)
method that is synchronized with the fLCD signal. RAM addresses in this location that are not used for LCD
display can be allocated to general-purpose use.

COM

Bit

COM0

.0

COM1

.1

COM2

.2

COM3

.3

COM4

.4

COM5

.5

COM6

.6

COM7

.7

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG37

SEG38

SEG39

900H

901H

902H

903H

904H

905H

925H

926H

927H

Figure 14-3. LCD Display Data RAM Organization

14-3

LCD CONTROLLER/DRIVER

S3F833B/F834B_UM_REV1.10

LCD MODE CONTROL REGISTER (LMOD)
A LMOD is located in bank 0 of set 1 at address F0H, and is read/write addressable using register addressing
mode. It has the following control functions.
-- LCD duty and bias selection
-- LCD clock selection
-- LCD dividing resistor selection
-- LCD COM signal control

The LMOD register is used to turn the LCD display on/off, and to select duty and bias, and to select LCD clock
and to select dividing resistor, and to select COM signal control. Following an nRESET, all LMOD values are
cleared to &quot; 0 &quot; . This turns off the LCD display signal output, selects 234Hz for LCD clock, internal dividing resistor
select, and COM signal enable.
The LCD clock signal determines the frequency of COM signal scanning of each segment output. This is also
referred as the LCD frame frequency. Since the LCD clock is generated by watch timer clock (fw). The watch
timer should be enabled when the LCD display is turned on.

LCD Mode Control Register (LMOD)
F0H, Set 1, Bank 0, R/W
MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

COM signal Enable/Disable Bit:
0 = Enable COM signal
1 = Disable COM signal
LCD Voltage Dividing Resistor Control Bit:
0 = Internal voltage dividng resistor
1 = External voltage dividng resistor,
Internal voltage dividng resistors are off
LCD clock(LCDCK) frequency selection
bits: (fw = 75 kHz)
00 = 234 Hz
01 = 469 Hz
10 = 938 Hz
11 = 1875 Hz

Duty and bias selection for LCD
display
0xxx = LCD display off (COM and SEG output low)
1000 = 1/8 duty, 1/4 bias; COM0-COM7
1001 = 1/4 duty, 1/3 bias; COM0-COM3, SEG0-SEG3
1010 = 1/3 duty, 1/3 bias; COM0-COM2, SEG0-SEG3,
P8.4 can't be used normal I/O pin.
1011 = 1/3 duty, 1/2 bias; COM0-COM2, SEG0-SEG3,
P8.4 can't be used normal I/O pin.
1100 = 1/2 duty, 1/2 bias; COM0-COM1, SEG0-SEG3,
P8.4, P8.5 can't be used normal I/O pin.

Figure 14-4. LCD Mode Control Register (LMOD)

14-4

S3F833B/F834B_UM_REV1.10

LCD CONTROLLER/DRIVER

LCD CONTROL REGISTER (LCON)
The LCD control register for the LCD controller/driver is called LCON, EFH of bank 0 in set 1, and is read/write
addressable using register addressing mode. It has the following control functions:
-- LCD display control
-- LCD voltage dividing resistor selection
The LCD control register, LCON is used to turn the LCD display on/off, and to select LCD voltage dividing
resistor. Following a nRESET, all LCON values are cleared to &quot; 0 &quot; . This turns off the LCD display, and normal LCD
dividing resistor.
LCD Control Register (LCON)
EFH, Set 1, Bank 0, R/W
MSB

.7

.6

.5

LCD output control bit:
0 = LCD output is low and current to
dividing resistors is cut off
1 = If LMOD.3 = &quot; 0 &quot; , LCD Display is
turned off
If LMOD.3 = &quot; 1 &quot; , output COM
and SEG signals in display mode

Not used

.4

.3

.2

.1

.0

LSB

LCD port selection bits:
0000 = Select LCD COM0-3, COM4-7/SEG0-3, SEG4-39
0001= Select LCD COM0-3, COM4-7/SEG0-3, SEG4-35,
P4.0-P4.3 is I/O port
0010= Select LCD COM0-3, COM4-7/SEG0-3, SEG4-31,
P4 is I/O port
0011= Select LCD COM0-3, COM4-7/SEG0-3, SEG4-27,
P4 and P5.0-P5.3 are I/O port
0100= Select LCD COM0-3, COM4-7/SEG0-3, SEG4-23,
P4 and P5 are I/O port
0101= Select LCD COM0-3, COM4-7/SEG0-3, SEG4-19,
P4, P5 and P6.0-P6.3 are I/O port
0110= Select LCD COM0-3, COM4-7/SEG0-3, SEG4-15,
P4, P5 and P6 are I/O port
0111= Select LCD COM0-3, COM4-7/SEG0-3, SEG4-11,
P4, P5, P6 and P7.0-P7.3 are I/O port
1000= Select LCD COM0-3, COM4-7/SEG0-3, SEG4-7,
P4, P5, P6 and P7 are I/O port
1001= Select LCD COM0-3, COM4-7/SEG0-3, SEG4-3,
P4, P5, P6, P7 and P9.0-P9.3 are I/O port
1010= All I/O port (P4, P5, P6, P7, P8, P9.0-P9.3)

Figure 14-5. LCD Control Register (LCON)

14-5

LCD CONTROLLER/DRIVER

S3F833B/F834B_UM_REV1.10

LCD VOLTAGE DIVIDING RESISTOR

1/3 Bias

1/4 Bisa

(LMOD.3-.0 = 9H or 0AH)

VDD

VDD
LCON.7

LCON.7

VLC0

VLC0
R

VLC1

LMOD.6=0: Enable internal resistors

R

VLC2

R

VLCD

VLC3

R

R

P9CONH

P9CONH

VSS

1/2 Bias

LMOD.6=0: Enable internal resistors

R

VLC2

VLCD

VLC3

R

VLC1

VSS

(LMOD.3-.0 = 0BH or 0CH)

Voltage Dividing Resistor Adjustment

VDD

VDD
LCON.7

LCON.7

VLC0
VLC1

VLC0
R

LMOD.6=0: Enable internal resistors

R'

LMOD.6=0: Disable internal resistors

VLC1
R'

VLC2

VLC2

VLCD
R'

VLC3
R
P9CONH

VLCD

VLC3

R'
P9CONH

VSS

VSS

NOTES:
1. R = Internal LCD dividing resistors. The resistors can be disconnected by LMOD.6.
2. R' = External LCD dividing
3. When LMOD.6 is selected to '1', P9CONH is selected alternative function mode (VLCn). (n = 0-3)

Figure 14-6. LCD Voltage Dividing Resistor Connection

14-6

S3F833B/F834B_UM_REV1.10

LCD CONTROLLER/DRIVER

COMMON (COM) SIGNALS
The common signal output pin selection (COM pin selection) varies according to the selected duty cycle.
-- In 1/8 duty mode, COM0-COM7 (SEG4-SEG39) pins are selected.
-- In 1/4 duty mode, COM0-COM3 (SEG0-SEG39) pins are selected.
-- In 1/3 duty mode, COM0-COM2 (SEG0-SEG39) pins are selected.
-- In 1/2 duty mode, COM0-COM1 (SEG0-SEG39) pins are selected.

SEGMENT (SEG) SIGNALS
The 40 LCD segment signal pins are connected to corresponding display RAM locations at page 9. Bits of the
display RAM are synchronized with the common signal output pins.
When the bit value of a display RAM location is &quot; 1 &quot; , a select signal is sent to the corresponding segment pin.
When the display bit is &quot; 0 &quot; , a 'no-select' signal to the corresponding segment pin.

14-7

LCD CONTROLLER/DRIVER

S3F833B/F834B_UM_REV1.10

COM0

0

1

0

1

VDD
SEG0
V SS
1 Frame
COM1

VLC0
V LC1(VLC2, VLC3)

COM0

V SS
SEG1

SEG2

SEG3
VLC0
V LC1(VLC2, VLC3)

COM1

V SS

VLC0
SEG0

V LC1(VLC2, VLC3)
V SS

VLC0
SEG1

V LC1(VLC2, VLC3)
V SS

+ VLC0
+ V LC1(VLC2, VLC3)
COM0-SEG0

V SS
- V LC1(VLC2, VLC3)
- VLC0

Figure 14-7. LCD Signal Waveforms (1/2 Duty, 1/2Bias)

14-8

S3F833B/F834B_UM_REV1.10

SEG2

SEG1

LCD CONTROLLER/DRIVER

SEG0

0

1

2

0

1

2

VDD
COM0
VSS
1 Frame

COM0

VLC0
V LC1
V LC2 (VLC3)
V SS

COM1

VLC0
V LC1
V LC2 (VLC3)
V SS

COM2

VLC0
V LC1
V LC2 (VLC3)
V SS

SEG0

VLC0
V LC1
V LC2 (VLC3)
V SS

SEG1

VLC0
V LC1
V LC2 (VLC3)
V SS

SEG0-COM0

+ VLC0
+ V LC1
+ V LC2 (VLC3)
V SS
- V LC2 (VLC3)
- VLC1
- V LC0

COM1
COM2

Figure 14-8. LCD Signal Waveforms (1/3 Duty, 1/3 Bias)

14-9

LCD CONTROLLER/DRIVER

SEG1

S3F833B/F834B_UM_REV1.10

SEG0
0

1

2

3

0

1

2

3

VDD
COM0
V SS
COM1

1 Frame

COM0

VLC0
V LC1
V LC2 (VLC3)
V SS

COM1

VLC0
V LC1
V LC2 (VLC3)
V SS

COM2

VLC0
V LC1
V LC2 (VLC3)
V SS

SEG0

VLC0
V LC1
V LC2 (VLC3)
V SS

SEG1

VLC0
V LC1
V LC2 (VLC3)
V SS

SEG0-COM0

+ VLC0
+ V LC1
+ V LC2 (VLC3)
V SS
- V LC2 (VLC3)
- VLC1
- V LC0

COM2
COM3

Figure 14-9 LCD Signal Waveforms (1/4 Duty, 1/3 Bias)

14-10

S3F833B/F834B_UM_REV1.10

LCD CONTROLLER/DRIVER

0123456701234567

COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7

VDD
V SS
1 Frame

COM0

S
E
G
0

S
E
G
1

S
E
G
2

S
E
G
3

S
E
G
4

VLC0
VLC1
VLC2
VLC3
VSS

COM1

VLC0
VLC1
VLC2
VLC3
VSS

COM2

VLC0
VLC1
VLC2
VLC3
VSS

SEG0

VLC0
VLC1
VLC2
VLC3
VSS

SEG0COM0

+VLC0
+VLC1
+VLC2
+VLC3
VSS
-VLC3
-VLC2
-VLC1
-VLC0

Figure 14-10. LCD Signal Waveforms (1/8 Duty, 1/4 Bias)

14-11

LCD CONTROLLER/DRIVER

S3F833B/F834B_UM_REV1.10

NOTES

14-12

S3F833B/F834B_UM_REV1.10

15

A/D CONVERTER

10-BIT ANALOG-TO-DIGITAL CONVERTER

OVERVIEW
The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at
one of the twelve input channels to equivalent 10-bit digital values. The analog input level must lie between the
AVDD and AVSS values. The A/D converter has the following components:
-- Analog comparator with successive approximation logic
-- D/A converter logic (resistor string type)
-- ADC control register (ADCON)
-- Twelve multiplexed analog data input pins (AD0-AD11)
-- 10-bit A/D conversion data output register (ADDATAH/L)
-- 12-bit digital input port (Alternately, I/O port.)
-- AVDD pin is internally connected to VDD

FUNCTION DESCRIPTION
To initiate an analog-to-digital conversion procedure, at the first you must set ADCEN signal for ADC input enable
at port 2 and port 1.4-7, the pin set with alternative function can be used for ADC analog input. And you write the
channel selection data in the A/D converter control register ADCON.4-7 to select one of the twelve analog input
pins (ADC0-11) and set the conversion start or enable bit, ADCON.0. The read-write ADCON register is located
in set 1, bank 0, at address F9H. The pins witch are not used for ADC can be used for normal I/O.
During a normal conversion, ADC logic initially sets the successive approximation register to 200H (the
approximate half-way point of an 10-bit register). This register is then updated automatically during each
conversion step. The successive approximation block performs 10-bit conversions for one input channel at a time.
You can dynamically select different channels by manipulating the channel selection bit value (ADCON.7-4) in
the ADCON register. To start the A/D conversion, you should set the enable bit, ADCON.0. When a conversion is
completed, ADCON.3, the end-of-conversion (EOC) bit is automatically set to 1 and the result is dumped into the
ADDATAH/L register where it can be read. The A/D converter then enters an idle state. Remember to read the
contents of ADDATAH/L before another conversion starts. Otherwise, the previous result will be overwritten by
the next conversion result.
NOTE
Because the A/D converter has no sample-and-hold circuitry, it is very important that fluctuation in the
analog level at the AD0-AD11 input pins during a conversion procedure be kept to an absolute minimum.
Any change in the input level, perhaps due to noise, will invalidate the result. If the chip enters to STOP or
IDLE mode in conversion process, there will be a leakage current path in A/D block. You must use STOP
or IDLE mode after ADC operation is finished.

15-1

A/D CONVERTER

S3F833B/F834B_UM_REV1.10

CONVERSION TIMING
The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set-up A/D
conversion. Therefore, total of 50 clocks are required to complete an 10-bit conversion: When fxx/8 is selected for
conversion clock with an 4.5 MHz fxx clock frequency, one clock cycle is 1.78 us. Each bit conversion requires 4
clocks, the conversion rate is calculated as follows:
4 clocks/bit

×

10 bits + set-up time = 50 clocks, 50 clock × 1.78us = 89 ?s at 0.56 MHz (4.5MHz/8)

A/D CONVERTER CONTROL REGISTER (ADCON)
The A/D converter control register, ADCON, is located at address F9H in set 1, bank 0. It has three functions:
-- Analog input pin selection (ADCON.7-.4)
-- End-of-conversion status detection (ADCON.3)
-- ADC clock selection (ADCON.2-.1)
-- A/D operation start or enable (ADCCON.0)
After a reset, the start bit is turned off. You can select only one analog input channel at a time. Other analog input
pins (AD0-AD11) can be selected dynamically by manipulating the ADCON.4-.7 bits. And the pins not used for
analog input can be used for normal I/O function.

A/D Converter Control Register (ADCON)
F9H, Set 1, Bank 0, R/W (EOC bit is read-only)
MSB

.7

.6

.5

.4

A/D input pin selection bits:
0 00 0 = AD0
00 0 1 = AD1
00 1 0 = AD2
00 1 1 = AD3
01 0 0 = AD4
01 0 1 = AD5
01 1 0 = AD6
01 1 1 = AD7
10 0 0 = AD8
10 0 1 = AD9
10 1 0 = AD10
10 1 1 = AD11

.3

.2

.1

.0

LSB

Start or enable bit:
0 = Disable operation
1 = Start operation
Clock Selection bit:
0 0 = fxx/16
0 1 = fxx/8
1 0 = fxx/4
1 1 = fxx/1

End-of-conversion bit:
0 = Conversion not complete
1 = Conversion complete

Figure 15-1. A/D Converter Control Register (ADCON)

15-2

S3F833B/F834B_UM_REV1.10

A/D CONVERTER

Conversion Data Register ADDATAH/ADDATAL
FAH/FBH, SET 1, BANK 0, READ Only

MSB

.9

.8

.7

.6

.5

.4

.3

.2

LSB

(ADDATAH)

MSB

-

-

-

-

-

-

.1

.0

LSB

(ADDATAL)

Figure 15-2. A/D Converter Data Register (ADDATAH/L)

INTERNAL REFERENCE VOLTAGE LEVELS
In the ADC function block, the analog input voltage level is compared to the reference voltage. The analog input
level must remain within the range AVSS to AVDD (The AVDD pin is internally connected with VDD).
Different reference voltage levels are generated internally along the resistor tree during the analog conversion
process for each conversion step. The reference voltage level for the first conversion bit is always 1/2 AVDD.

15-3

A/D CONVERTER

S3F833B/F834B_UM_REV1.10

BLOCK DIAGRAM

ADCON.2-.1
ADCON.4-.7
(Select one input pin of the assigned pins)
Clock
Selector
ADCON.0
(AD/C Enable)

Input Pins
AD0-AD7
(P2.0-P2.7)
AD8-AD11
(P1.4-P1.7)

M
-

.
.
.

U

Analog
Comparator

+

Successive
Approximation
Logic &amp; Register

X
ADCON.0
(AD/C Enable)

P1CONH,
P2CONH/L
( Assign Pins to ADC Input)

10-bit D/A
Converter

AVDD
V SS

Conversion
Result
(ADDATAH,ADDATAL)

Figure 15-3. A/D Converter Functional Block Diagram

15-4

To ADCON.3
(EOC Flag)

S3F833B/F834B_UM_REV1.10

A/D CONVERTER

VDD
Analog Input Pin
(VSS <= ADC input <= VDD)

AD0-AD11
C 101

S3F833B/F834B

Figure 15-4. Recommended A/D Converter Circuit for Highest Absolute Accuracy

15-5

A/D CONVERTER

S3F833B/F834B_UM_REV1.10

NOTES

15-6

S3F833B/F834B_UM_REV1.10

16

SERIAL I/O INTERFACE

SERIAL I/O INTERFACE

OVERVIEW
Serial I/O modules, SIO0 and SIO1 can interface with various types of external device that require serial data
transfer. The components of SIO0 and SIO1 function block are:
-- 8-bit control register (SIO0CON, SIO1CON)
-- Clock selector logic
-- 8-bit data buffer (SIO0DATA, SIO1DATA)
-- 8-bit prescaler (SIO0PS, SIO1PS)
-- 3-bit serial clock counter
-- Serial data I/O pins (SI0, SO0, SI1, SO1)
-- Serial clock input/output pins (SCK0, SCK1)
-- Serial data and clock output type selection (PG2CON.7-.6)
The SIO modules can transmit or receive 8-bit serial data at a frequency determined by its corresponding control
register settings. To ensure flexible data transmission rates, you can select an internal or external clock source.
PROGRAMMING PROCEDURE
To program the SIO modules, follow these basic steps:
1. Configure the I/O pins at port (SCK0/SI0/SO0, SCK1/SI1/SO1) by loading the appropriate value to the
P3CONH and P3CONL register if necessary.
2. Configure the output type (SCK0/SO0, SCK1/SO1) by manipulating PG2CON.7-.6 if necessary.
3. Load an 8-bit value to the SIO0CON and SIO1CON control registers to properly configure the serial I/O
modules. In this operation, SIO0CON.2 and SIO1CON.2 must be set to &quot; 1 &quot; to enable the data shifters,
respectively.
4. For interrupt generation, set the serial I/O interrupt enable bits (SIO0CON.1, SIO1CON.1) to &quot; 1 &quot; , respectively.
5. When you transmit data to the serial buffer, write data to SIO0DATA or SIO1DATA and set SIO0CON.3 or
SIO1CON.3 to 1, the shift operation starts.
6. When the shift operation (transmit/receive) is completed, the SIO0 and SIO1 pending bits (SIO0CON.0 and
SIO1CON.0) are set to &quot; 1 &quot; and SIO interrupt requests are generated, respectively.

16-1

SERIAL I/O INTERFACE

S3F833B/F834B_UM_REV1.10

SIO0 AND SIO1 CONTROL REGISTERS (SIO0CON, SIO1CON)
The control registers for serial I/O interface modules, SIO0CON, is located at E7H and SIO1CON, is located at
EAH in set 1, bank 0. They have the control settings for SIO modules, respectively.
-- Clock source selection (internal or external) for shift clock
-- Interrupt enable
-- Edge selection for shift operation
-- Clear 3-bit counter and start shift operation
-- Shift operation (transmit) enable
-- Mode selection (transmit/receive or receive-only)
-- Data direction selection (MSB first or LSB first)
A reset clears the SIO0CON and SIO1CON values to &quot; 00H &quot; . This configures the corresponding modules with an
internal clock source at the SCK0 and SCK1, selects receive-only operating mode, and clears the 3-bit counter,
respectively. The data shift operation and the interrupt are disabled. The selected data direction is MSB-first.

Serial I/O Module Control Register (SIO0CON)
E7H, Set 1, Bank 0, R/W
MSB

.7

.6

.5

SIO0 shift clock selection bit:
0 = Internal clock (P.S Clock)
1 = External clock (SCK0)

Data direction control bit:
0 = MSB-first mode
1 = LSB-first mode
SIO0 mode selection bit:
0 = Receive only mode
1 = Transmit/receive mode
Shift clock edge selection bit:
0 = tX at falling edeges, rx at rising edges.
1 = tX at rising edeges, rx at falling edges.
NOTE:

.4

.3

.2

.1

.0

LSB

SIO0 interrupt pending bit:
0 = No interrupt pending
0 = Clear pending condition
(when write)
1 = Interrupt is pending
SIO0 interrupt enable bit:
0 = Disable SIO0 interrupt
1 = Enable SIO0 interrupt
SIO0 shift operation enable bit:
0 = Disable shifter and clock counter
1 = Enable shifter and clock counter
SIO0 counter clear and shift start bit:
0 = No action
1 = Clear 3-bit counter and start shifting

It is selected SCK0 and SO0 output type (push-pull or open-drain) by PG2CON.6.

Figure 16-1. Serial I/O Module Control Register (SIO0CON)

16-2

S3F833B/F834B_UM_REV1.10

SERIAL I/O INTERFACE

Serial I/O Module Control Register (SIO1CON)
EAH, Set 1, Bank 0, R/W
MSB

.7

.6

.5

SIO1 shift clock selection bit:
0 = Internal clock (P.S Clock)
1 = External clock (SCK1)

Data direction control bit:
0 = MSB-first mode
1 = LSB-first mode
SIO1 mode selection bit:
0 = Receive only mode
1 = Transmit/receive mode
Shift clock edge selection bit:
0 = tX at falling edeges, rx at rising edges.
1 = tX at rising edeges, rx at falling edges.
NOTE:

.4

.3

.2

.1

.0

LSB

SIO1 interrupt pending bit:
0 = No interrupt pending
0 = Clear pending condition
(when write)
1 = Interrupt is pending
SIO1 interrupt enable bit:
0 = Disable SIO1 interrupt
1 = Enable SIO1 interrupt
SIO1 shift operation enable bit:
0 = Disable shifter and clock counter
1 = Enable shifter and clock counter
SIO1 counter clear and shift start bit:
0 = No action
1 = Clear 3-bit counter and start shifting

It is selected SCK1 and SO1 output type (push-pull or open-drain) by PG2CON.7.

Figure 16-2. Serial I/O Module Control Register (SIO1CON)

16-3

SERIAL I/O INTERFACE

S3F833B/F834B_UM_REV1.10

SIO0 AND SIO1 PRE-SCALER REGISTER (SIO0PS, SIO1PS)
The prescaler registers for serial I/O interface modules, SIO0PS and SIO1PS, are located at E9H and ECH in set
1, bank 0, respectively.
The values stored in the SIO0 and SIO1 pre-scale registers, SIO0PS and SIO1PS, lets you determine the SIO0
and SIO1 clock rate (baud rate) as follows, respectively:
Baud rate = Input clock (fxx/4)/(Pre-scaler value + 1), or SCK0 and SCK1 input clock.

SIO0 Pre-scaler Register (SIO0PS)
E9H, Set 1, Bank 0, R/W
MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Baud rate = (fXX/4)/(SIO0PS + 1)

Figure 16-3. SIO0 Pre-scaler Register (SIO0PS)

SIO1 Pre-scaler Register (SIO1PS)
ECH, Set 1, Bank 0, R/W
MSB

.7

.6

.5

.4

.3

.2

.1

.0

Baud rate = (fXX/4)/(SIO1PS + 1)

Figure 16-4. SIO1 Pre-scaler Register (SIO1PS)

16-4

LSB

S3F833B/F834B_UM_REV1.10

SERIAL I/O INTERFACE

SIO BLOCK DIAGRAM (SIO0, SIO1)

CLK

SIO0 INT

3-Bit Counter
Clear

SIO0CON.0

IRQ2

Pending
SIO0CON.1
(Interrupt Enable)

SIO0CON.3
SIO0CON.7
SIO0CON.4
(Edge Select)
M

SCK0
SIO0PS (E9H, bank 0)
fxx/2

SIO0CON.2
(Shift Enable)

8-bit P.S.

1/2

U

SIO0CON.5
(Mode Select)

CLK 8-Bit SIO0 Shift Buffer
(SIO0DATA, E8H, bank 0)

X

Prescaler Value = 1/(SIO0PS +1)

SO0
SIO0CON.6
(LSB/MSB First
Mode Select)

8

SI0

Data Bus

Figure 16-5. SIO0 Functional Block Diagram

CLK

SIO1 INT

3-Bit Counter
Clear

SIO1CON.0

IRQ2

Pending
SIO1CON.1
(Interrupt Enable)

SIO1CON.3
SIO1CON.7
SIO1CON.4
(Edge Select)
M

SCK1
SIO1PS (ECH, bank 0)
fxx/2

SIO1CON.2
(Shift Enable)

8-bit P.S.

1/2

U
X

Prescaler Value = 1/(SIO1PS +1)

SIO1CON.5
(Mode Select)

CLK 8-Bit SIO1 Shift Buffer
(SIO1DATA, EBH, bank 0)

8

SO1
SIO1CON.6
(LSB/MSB First
Mode Select)

SI1

Data Bus

Figure 16-6. SIO1 Functional Block Diagram

16-5

SERIAL I/O INTERFACE

S3F833B/F834B_UM_REV1.10

SERIAL I/O TIMING DIAGRAM (SIO0, SIO1)

SCK0/SCK1

SI0/SI1

DI7

DI6

DI5

DI4

DI3

DI2

DI1

DI0

SO0/SO1

DO7

DO6

DO5

DO4

DO3

DO2

DO1

DO0

Transmit
Complete

IRQ2
Set SIO0CON.3 or SIO1CON.3

Figure 16-7. Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIO0CON.4 or SIO1CON.4 = 0)

SCK0/SCK1

SI0/SI1

DI7

DI6

DI5

DI4

DI3

DI2

DI1

DI0

SO0/SO1

DO7

DO6

DO5

DO4

DO3

DO2

DO1

DO0

Transmit
Complete

IRQ2
Set SIO0CON.3 or SIO1CON.3

Figure 16-8. Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIO0CON.4 or SIO1CON.4 = 1)

16-6

S3F833B/F834B_UM_REV1.10

17

UART

UART

OVERVIEW
The UART0 and UART1 modules have a full-duplex serial port with programmable operating modes: There is one
synchronous mode and three UART (Universal Asynchronous Receiver/Transmitter) modes:
-- Serial I/O with baud rate of fxx/(16 × (BRDATA+1))
-- 8-bit UART mode; variable baud rate
-- 9-bit UART mode; fxx/16
-- 9-bit UART mode, variable baud rate
UART0 and UART1 modules receive and transmit buffers are both accessed via the data register, UDATA0, is
page 0 at address 01H and UDATA1, is page 0 at address 04H. Writing to the UART0 and UART1 data register
loads the transmit buffer; reading the UART0 and UART1 data register accesses a physically separate receive
buffer.
When accessing a receive data buffer (shift register), reception of the next byte can begin before the previously
received byte has been read from the receive register. However, if the first byte has not been read by the time the
next byte has been completely received, one of the bytes will be lost.
In all operating modes, transmission is started when any instruction (usually a write operation) uses the UDATA0
and UDATA1 register as its destination address. In mode 0, serial data reception starts when the receive interrupt
pending bit (INTPND.5 and INTPND.3) is &quot; 0 &quot; and the receive enable bit (UART0CON.4 and UART1CON.4) is &quot; 1 &quot; .
In mode 1, 2, and 3, reception starts whenever an incoming start bit ( &quot; 0 &quot; ) is received and the receive enable bit
(UART0CON.4 and UART1CON.4) is set to &quot; 1 &quot; .
PROGRAMMING PROCEDURE
To program the UART0/UART1 modules, follow these basic steps:
1. Configure P10.5, P10.6, P0.0 and P0.1 to alternative function (RXD0/ RxD1 (P10.5/P0.0), TXD0/ TXD1
(P10.6/P0.1)) for UART module by setting the P10CONH and P0CONL register to appropriately value.
2. Load an 8-bit value to the UART0CON and UART1CON control register to properly configure the UART0/
UART1 I/O module.
3. For interrupt generation, set the UART0 and UART1 I/O interrupt enable bit (UART0CON.1/ UART1CON.1 or
UART0CON.0/ UART1CON.0) to &quot; 1 &quot; .
4. When you transmit data to the UART0 and UART1 buffer, write data to UDATA0 and UDATA1, the shift
operation starts.
5. When the shift operation (transmit/receive) is completed, UART0/UART1 pending bit (INTPND.2/INTPND.4 or
INTPND.3/ INTPND.5) is set to &quot; 1 &quot; and an UART interrupt request is generated.

17-1

UART

S3F833B/F834B_UM_REV1.10

UART0 CONTROL REGISTER (UART0CON)
The control register for the UART0 is called UART0CON in page 0 at address 00H. It has the following control
functions:
-- Operating mode and baud rate selection
-- Multiprocessor communication and interrupt control
-- Serial receive enable/disable control
-- 9th data bit location for transmit and receive operations (modes 2 and 3 only)
-- UART0 transmit and receive interrupt control
A reset clears the UART0CON value to &quot; 00H &quot; . So, if you want to use UART0 module, you must write appropriate
value to UART0CON.

UART0 Control Register (UART0CON)
00H, Page 0, R/W
MSB

MS1

MS0 MCE

RE

TB8

RB8

RIE

Operating mode and
baud rate selection bits:
(see table below)

TIE

LSB

UART0 Transmit interrupt enable bit:
0 = Disable
1 = Enable

Multiprocessor communication(1)
enable bit (for modes 2 and 3 only):
0 = Disable
1 = Enable
Serial data receive enable bit:
0 = Disable
1 = Enable

UART0 Received interrupt enable bit:
0 = Disable
1 = Enable
Location of the 9th data bit that was
received in UART0 mode 2 or 3 ( &quot; 0 &quot; or &quot; 1 &quot; )

Location of the 9th data bit to be
transmitted in UART0 mode 2 or 3 ( &quot; 0 &quot; or &quot; 1 &quot; )
MS1 MS0 Mode Description(2) Baud Rate
0
0
1
1

0
1
0
1

0
1
2
3

Shift register
8-bit UART
9-bit UART
9-bit UART

(fxx /(16 x (BRDATA + 1)))
(fxx /(16 x (BRDATA + 1)))
(fxx /16)
(fxx /(16 x (BRDATA + 1)))

NOTES:
1. In mode 2 or 3, if the UART0CON.5 bit is set to &quot; 1 &quot; then the receive interrupt will not be
activated if the received 9th data bit is &quot; 0 &quot; . In mode 1, if UART0CON.5 = &quot; 1 &quot; then the
receive interrut will not be activated if a valid stop bit was not received.
In mode 0, the UART0CON.5 bit should be &quot; 0 &quot;
2. The descriptions for 8-bit and 9-bit UART0 mode do not include start and stop bits
for serial data receive and transmit.
3. The interrupt pending bits of Rx and Tx are in the INTPND register.

Figure 17-1. UART0 Control Register (UART0CON)

17-2

S3F833B/F834B_UM_REV1.10

UART

UART1 CONTROL REGISTER (UART1CON)
The control register for the UART1 is called UART1CON in page0 at address 03H. It has the following control
functions:
-- Operating mode and baud rate selection
-- Multiprocessor communication and interrupt control
-- Serial receive enable/disable control
-- 9th data bit location for transmit and receive operations (modes 2 and 3 only)
-- UART1 transmit and receive interrupt control
A reset clears the UART1CON value to &quot; 00H &quot; . So, if you want to use UART1 module, you must write appropriate
value to UART1CON.

UART1 Control Register (UART1CON)
03H, Page 0, R/W
MSB

MS1

MS0 MCE

RE

TB8

RB8

RIE

Operating mode and
baud rate selection bits:
(see table below)

TIE

LSB

UART1Transmit interrupt enable bit:
0 = Disable
1 = Enable

Multiprocessor communication(1)
enable bit (for modes 2 and 3 only):
0 = Disable
1 = Enable
Serial data receive enable bit:
0 = Disable
1 = Enable

UART1 Received interrupt enable bit:
0 = Disable
1 = Enable
Location of the 9th data bit that was
received in UART1 mode 2 or 3 ( &quot; 0 &quot; or &quot; 1 &quot; )

Location of the 9th data bit to be
transmitted in UART1 mode 2 or 3 ( &quot; 0 &quot; or &quot; 1 &quot; )
MS1 MS0 Mode Description(2) Baud Rate
0
0
1
1

0
1
0
1

0
1
2
3

Shift register
8-bit UART
9-bit UART
9-bit UART

(fxx /(16 x (BRDATA + 1)))
(fxx /(16 x (BRDATA + 1)))
(fxx /16)
(fxx /(16 x (BRDATA + 1)))

NOTES:
1. In mode 2 or 3, if the UART1CON.5 bit is set to &quot; 1 &quot; then the receive interrupt will not be
activated if the received 9th data bit is &quot; 0 &quot; . In mode 1, if UART1CON.5 = &quot; 1 &quot; then the
receive interrut will not be activated if a valid stop bit was not received.
In mode 0, the UART1CON.5 bit should be &quot; 0 &quot;
2. The descriptions for 8-bit and 9-bit UART1 mode do not include start and stop bits
for serial data receive and transmit.
3. The interrupt pending bits of Rx and Tx are in the INTPND register.

Figure 17-2. UART1 Control Register (UART1CON)

17-3

UART

S3F833B/F834B_UM_REV1.10

UART0 INTERRUPT PENDING BITS
The UART0 interrupt pending bits, INTPND.2-.3, are located in set 1, bank 0 at address D0H, it contains the
UART0 data transmit interrupt pending bit (INTPND.2) and the receive interrupt pending bit (INTPND.3).
In mode 0, the receive interrupt pending bit INTPND.3 is set to &quot; 1 &quot; when the 8th receive data bit has been shifted.
In mode 1, 2, and 3, the INTPND.3 bit is set to &quot; 1 &quot; at the halfway point of the stop bit's shift time. When the CPU
has acknowledged the receive interrupt pending condition, the INTPND.3 bit must then be cleared by software in
the interrupt service routine.
In mode 0, the transmit interrupt pending bit INTPND.2 is set to &quot; 1 &quot; when the 8th transmit data bit has been
shifted. In mode 1, 2, or 3, the INTPND.2 bit is set at the start of the stop bit. When the CPU has acknowledged
the transmit interrupt pending condition, the INTPND.2 bit must then be cleared by software in the interrupt
service routine.

Interrupt Pending Register (INTPND)
D0H, Set 1, Bank 0, R/W
MSB

.7

.6

.5

.4

.3

.2

Not used

.1

.0

LSB

Timer 0 overflow interrupt pending bit:
Timer 0 match/capture pending bit:
Tx interrupt pending bit (for UART0):
Rx interrupt pending bit (for UART0):
Tx interrupt pending bit (for UART1):
Rx interrupt pending bit (for UART1):

INTPND bit configuration settings:
0

Interrupt request is not pending, (when read)
pending bit clear when write 0

1

Interrupt request is pending (when read)

Figure 17-3. UART0 Interrupt Pending Bits (INTPND.2-.3)

17-4

S3F833B/F834B_UM_REV1.10

UART

UART1 INTERRUPT PENDING BITS
The UART1 interrupt pending bits, INTPND.5-.4, are located in set 1, bank 0 at address D0H, it contains the
UART1 data transmit interrupt pending bit (INTPND.4) and the receive interrupt pending bit (INTPND.5).
In mode 0, the receive interrupt pending bit INTPND.5 is set to &quot; 1 &quot; when the 8th receive data bit has been shifted.
In mode 1, 2, and 3, the INTPND.5 bit is set to &quot; 1 &quot; at the halfway point of the stop bit's shift time. When the CPU
has acknowledged the receive interrupt pending condition, the INTPND.5 bit must then be cleared by software in
the interrupt service routine.
In mode 0, the transmit interrupt pending bit INTPND.4 is set to &quot; 1 &quot; when the 8th transmit data bit has been
shifted. In mode 1, 2, or 3, the INTPND.4 bit is set at the start of the stop bit. When the CPU has acknowledged
the transmit interrupt pending condition, the INTPND.4 bit must then be cleared by software in the interrupt
service routine.

Interrupt Pending Register (INTPND)
D0H, Set 1, Bank 0, R/W
MSB

.7

.6

.5

.4

.3

.2

Not used

.1

.0

LSB

Timer 0 overflow interrupt pending bit:
Timer 0 match/capture pending bit:
Tx interrupt pending bit (for UART0):
Rx interrupt pending bit (for UART0):
Tx interrupt pending bit (for UART1):
Rx interrupt pending bit (for UART1):

INTPND bit configuration settings:
0

Interrupt request is not pending, (when read)
pending bit clear when write 0

1

Interrupt request is pending (when read)

Figure 17-4. UART1 Interrupt Pending Bits (INTPND.5-.4)

17-5

UART

S3F833B/F834B_UM_REV1.10

UART0 DATA REGISTER (UDATA0)

UART0 Data Register (UDATA0)
01H, Page 0, R/W
MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Transmit or receive data

Figure 17-5. UART0 Data Register (UDATA0)

UART1 DATA REGISTER (UDATA1)

UART1 Data Register (UDATA1)
04H, Page 0, R/W
MSB

.7

.6

.5

.4

.3

.2

.1

.0

Transmit or receive data

Figure 17-6. UART1 Data Register (UDATA1)

17-6

LSB

S3F833B/F834B_UM_REV1.10

UART

UART0 BAUD RATE DATA REGISTER (BRDATA0)
The value stored in the UART0 baud rate register, BRDATA0, lets you determine the UART0 clock rate (baud
rate).

UART0 Baud Rate Data Register (BRDATA0)
02H, Page 0, R/W
MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Baud rate data

Figure 17-7. UART0 Baud Rate Data Register (BRDATA0)
UART1 BAUD RATE DATA REGISTER (BRDATA1)
The value stored in the UART1 baud rate register, BRDATA1, lets you determine the UART1 clock rate (baud
rate).

UART1 Baud Rate Data Register (BRDATA1)
05H, Page 0, R/W
MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Baud rate data

Figure 17-8. UART1 Baud Rate Data Register (BRDATA1)
BAUD RATE CALCULATIONS
Mode 0 Baud Rate Calculation
In mode 0, the baud rate is determined by the UART0/ UART1 baud rate data register, BRDATA0/ BRDATA1 in
page 0 at address 02H/05H: Mode 0 baud rate = fxx/(16 × (BRDATA + 1)).
Mode 2 Baud Rate Calculation
The baud rate in mode 2 is fixed at the fOSC clock frequency divided by 16: Mode 2 baud rate = fxx/16
Modes 1 and 3 Baud Rate Calculation
In modes 1 and 3, the baud rate is determined by the UART0/ UART1 baud rate data register, BRDATA0/
BRDATA1 in page 0 at address 02H/05HH: Mode 1 and 3 baud rate = fxx/(16 × (BRDATA + 1))

17-7

UART

S3F833B/F834B_UM_REV1.10

Table 17-1. Commonly Used Baud Rates Generated by BRDATA0/ BRDATA1
Mode

Baud Rate

Oscillation Clock

BRDATA
Decimal

Hexdecimal

x

x

Mode 2

0.5 MHz

8 MHz

Mode 0
Mode 1
Mode 3

230.400 Hz

11.0592 MHz

02

02H

115.200 Hz

11.0592 MHz

05

05H

57.600 Hz

11.0592 MHz

11

0BH

38.400 Hz

11.0592 MHz

17

11H

19.200 Hz

11.0592 MHz

35

23H

9.600 Hz

11.0592 MHz

71

47H

4.800 Hz

11.0592 MHz

143

8FH

62.500 Hz

10 MHz

09

09H

9.615 Hz

10 MHz

64

40H

38.461 Hz

8 MHz

12

0CH

12.500 Hz

8 MHz

39

27H

19.230 Hz

4 MHz

12

0CH

9.615 Hz

4 MHz

25

19H

17-8

S3F833B/F834B_UM_REV1.10

UART

BLOCK DIAGRAM

Data Bus
TB8

fxx

MS0
MS1

BRDATA0

S
D
Q
CLK

CLK

Baud Rate
Generator

Write to
UDATA0

UART 0 DATA
MS0
MS1

RXD0 (P10.5)

Zero Detector

Start

TX Clock

TIP

UART0CON.0

UART 0 data receive INT
IRQ 3

Rx Clock

EN
Send
TXD0 (P10.6)

UART 0 data transmit INT
IRQ 3

RE
UART0CON.1

TXD0 (P10.6)

Shift

TX Control

UART0CON.1

RIP

Shift
Clock

Receive

Rx Control
Shift

Start
1-to-0
Transition
Detector

Shift
Value

Bit Detector

Shift
Register

MS0
MS1

UART 0 DATA
RxD0 (P10.5)
Data Bus

Figure 17-9. UART0 Functional Block Diagram

17-9

UART

S3F833B/F834B_UM_REV1.10

Data Bus
TB8

fxx

MS0
MS1

BRDATA 1

S
D
Q
CLK

CLK

Baud Rate
Generator

Write to
UDATA1

UART 1 DATA

Start

TIP

Rx Clock

EN
Send
TXD1 ( P0.1)

UART1CON.0

UART 1 data receive INT
IRQ 3

RE
UART1CON.1

TXD1 ( P0.1)

Shift

TX Control

UART 1 data transmit INT
IRQ 3

UART1CON.1

RIP

Receive

Rx Control
Shift

Start

Shift
Value

Bit Detector

Shift
Register

MS0
MS1

UART 1 DATA
RxD1 ( P0.0)
Data Bus

Figure 17-10. UART1 Functional Block Diagram

17-10

RXD1 ( P0.0)

Zero Detector

TX Clock

1-to-0
Transition
Detector

MS0
MS1

Shift
Clock

S3F833B/F834B_UM_REV1.10

UART

UART0/ UART1 MODE 0 FUNCTION DESCRIPTION
In mode 0, UART0/UART1 are input and output through the RxD0/ RxD1 (P10.5/P0.0) pins and TxD0/ TxD1
(P10.6/P0.1) pins outputs the shift clock. Data is transmitted or received in 8-bit units only. The LSB of the 8-bit
value is transmitted (or received) first.
Mode 0 Transmit Procedure
1. Select mode 0 by setting UART0CON.6 and .7/ UART1CON.6 and .7 to &quot; 00B &quot; .
2. Write transmission data to the shift register UDATA0/UDATA1 (01H/04H, page 0) to start the transmission
operation.
Mode 0 Receive Procedure
1. Select mode 0 by setting UART0CON.6 and .7/ UART1CON.6 and .7 to &quot; 00B &quot; .
2. Clear the receive interrupt pending bit (INTPND.3/INTPND.5) by writing a &quot; 0 &quot; to INTPND.3/INTPND.5.
3.

Set the UART0/ UART1 receive enable bit (UART0CON.4/ UART1CON.4) to &quot; 1 &quot; .

4. The shift clock will now be output to the TxD0/ TxD1 (P10.6/P0.1) pins and will read the data at the RxD0/
RxD1 (P10.5/P0.0) pins. The UART0/UART1 receive interrupt (IRQ3, vector F2H/F6H) occurs when
UART0CON.1/ UART1CON.1 is set to &quot; 1 &quot; .

17-11

UART

S3F833B/F834B_UM_REV1.10

Write to Shift Register (UDATA)

RxD (Data Out)

D0

D1

D2

D3

D4

D5

D6

Transmit

Shift

D7

TxD (Shift Clock)

TIP
Write to UARTPND (Clear RIP and set RE)

RIP

Receive

RE

Shift
D0

RxD (Data In)

D1

D2

D3

D4

D5

D6

D7

TxD (Shift Clock)
1

2

3

4

5

6

7

Figure 17-11. Timing Diagram for Serial Port Mode 0 Operation

17-12

8

S3F833B/F834B_UM_REV1.10

UART

SERIAL PORT MODE 1 FUNCTION DESCRIPTION
In mode 1, 10-bits are transmitted (through the TxD0/ TxD1 (P10.6/P0.1) pin) or received (through the RxD0/
RxD1 (P10.5/P0.0) pin). Each data frame has three components:
-- Start bit ( &quot; 0 &quot; )
-- 8 data bits (LSB first)
-- Stop bit ( &quot; 1 &quot; )
When receiving, the stop bit is written to the RB8 bit in the UART0CON/ UART1CON register. The baud rate for
mode 1 is variable.
Mode 1 Transmit Procedure
1. Select the baud rate generated by BRDATA0/ BRDATA1.
2. Select mode 1 (8-bit UART) by setting UART0CON bits 7 and 6/ UART1CON bits 7 and 6 to '01B'.
3. Write transmission data to the shift register UDATA0/ UDATA1 (01H/04H, page 0). The start and stop bits are
generated automatically by hardware.
Mode 1 Receive Procedure
1. Select the baud rate to be generated by BRDATA0/ BRDATA1.
2. Select mode 1 and set the RE (Receive Enable) bit in the UART0CON/ UART1CON register to &quot; 1 &quot; .
3. The start bit low ( &quot; 0 &quot; ) condition at the RxD0/ RxD1 (P10.5/P0.0) pin will cause the UART module to start the
serial data receive operation.
Tx
Clock

Shift
TxD

D0

D1

D2

D3

D4

D5

D6

D7

Start Bit

D0

D1

D2

D3

D4

D5

D6

Start Bit

Stop Bit

Transmit

Write to Shift Register (UDATA)

TIP

Rx
Clock
RxD

D7

Stop Bit

Receive

Bit Detect Sample Time
Shift
RIP

Figure 17-12. Timing Diagram for Serial Port Mode 1 Operation

17-13

UART

S3F833B/F834B_UM_REV1.10

SERIAL PORT MODE 2 FUNCTION DESCRIPTION
In mode 2, 11-bits are transmitted (through the TxD0/ TxD1 (P10.6/P0.1) pin) or received (through the RxD0/
RxD1 (P10.5/P0.0) pin). Each data frame has four components:
-- Start bit ( &quot; 0 &quot; )
-- 8 data bits (LSB first)
-- Programmable 9th data bit
-- Stop bit ( &quot; 1 &quot; )
The 9th data bit to be transmitted can be assigned a value of &quot; 0 &quot; or &quot; 1 &quot; by writing the TB8 bit (UART0CON.3/
UART1CON.3).
When receiving, the 9th data bit that is received is written to the RB8 bit (UART0CON.2/ UART1CON.2), while the
stop bit is ignored. The baud rate for mode 2 is fosc/16 clock frequency.
Mode 2 Transmit Procedure
1. Select mode 2 (9-bit UART) by setting UART0CON bits 6 and 7/UART1CON bits 6 and 7 to '10B'. Also, select
the 9th data bit to be transmitted by writing TB8 to &quot; 0 &quot; or &quot; 1 &quot; .
2. Write transmission data to the shift register, UDATA0/ UDATA1 (01H/04H, page 0), to start the transmit
operation.
Mode 2 Receive Procedure
1. Select mode 2 and set the receive enable bit (RE) in the UART0CON/ UART1CON register to &quot; 1 &quot; .
2. The receive operation starts when the signal at the RxD0/ RxD1 (P10.5/P0.0) pin goes to low level.
Tx
Clock
Write to Shift Register (UARTDATA)

TxD

D0

D1

D2

D3

D4

D5

D6

D7

TB8

Start Bit

D0

D1

D2

D3

D4

D5

D6

D7

Start Bit

Transmit

Shift
Stop Bit

TIP

Rx
Clock
RxD

RB8

Stop
Bit

Receive

Bit Detect Sample Time
Shift
RIP

Figure 17-13. Timing Diagram for Serial Port Mode 2 Operation

17-14

S3F833B/F834B_UM_REV1.10

UART

SERIAL PORT MODE 3 FUNCTION DESCRIPTION
In mode 3, 11-bits are transmitted (through the TxD0/ TxD1 (P10.6/P0.1) pin) or received (through the RxD0/
RxD1 (P10.5/P0.0) pin). Mode 3 is identical to mode 2 except for baud rate, which is variable. Each data frame
has four components:
-- Start bit ( &quot; 0 &quot; )
-- 8 data bits (LSB first)
-- Programmable 9th data bit
-- Stop bit ( &quot; 1 &quot; )
Mode 3 Transmit Procedure
1. Select the baud rate generated by BRDATA0/BRDATA1.
2. Select mode 3 operation (9-bit UART) by setting UART0CON bits 6 and 7/ UART1CON bits 6 and 7 to '11B'.
Also, select the 9th data bit to be transmitted by writing UART0CON.3/ UART1CON.3 (TB8) to &quot; 0 &quot; or &quot; 1 &quot; .
3. Write transmission data to the shift register, UDATA0/ UDATA1 (01H/04H, page 0), to start the transmit
operation.
Mode 3 Receive Procedure
1. Select the baud rate to be generated by BRDATA0/BRDATA1.
2. Select mode 3 and set the RE (Receive Enable) bit in the UART0CON/UART1CON register to &quot; 1 &quot; .
3. The receive operation will be started when the signal at the RxD0/ RxD1 (P10.5/P0.0) pin goes to low level.

17-15

UART

S3F833B/F834B_UM_REV1.10

Tx
Clock

Shift
TxD

D0

D1

D2

D3

D4

D5

D6

D7

TB8

Stop Bit

Start Bit

D0

D1

D2

D3

D4

D5

D6

D7

RB8

Start Bit

Transmit

Write to Shift Register (UARTDATA)

TIP

Rx
Clock
RxD

Stop
Bit

Receive

Bit Detect Sample Time
Shift
RIP

Figure 17-14. Timing Diagram for Serial Port Mode 3 Operation

17-16

S3F833B/F834B_UM_REV1.10

UART

SERIAL COMMUNICATION FOR MULTIPROCESSOR CONFIGURATIONS
The S3F8-series multiprocessor communication features lets a &quot; master &quot; S3F833B/F834B send a multiple-frame
serial message to a &quot; slave &quot; device in a multi- S3F833B/F834B configuration. It does this without interrupting other
slave devices that may be on the same serial line.
This feature can be used only in UART0/UART1 modes 2 or 3. In these modes 2 and 3, 9 data bits are received.
The 9th bit value is written to RB8 (UART0CON.2/ UART1CON.2). The data receive operation is concluded with a
stop bit. You can program this function so that when the stop bit is received, the serial interrupt will be generated
only if RB8 = &quot; 1 &quot; .
To enable this feature, you set the MCE bit in the UART0CON/ UART1CON register. When the MCE bit is &quot; 1 &quot; ,
serial data frames that are received with the 9th bit = &quot; 0 &quot; do not generate an interrupt. In this case, the 9th bit
simply separates the address from the serial data.
Sample Protocol for Master/Slave Interaction
When the master device wants to transmit a block of data to one of several slaves on a serial line, it first sends
out an address byte to identify the target slave. Note that in this case, an address byte differs from a data byte: In
an address byte, the 9th bit is &quot; 1 &quot; and in a data byte, it is &quot; 0 &quot; .
The address byte interrupts all slaves so that each slave can examine the received byte and see if it is being
addressed. The addressed slave then clears its MCE bit and prepares to receive incoming data bytes.
The MCE bits of slaves that were not addressed remain set, and they continue operating normally while ignoring
the incoming data bytes.
While the MCE bit setting has no effect in mode 0, it can be used in mode 1 to check the validity of the stop bit.
For mode 1 reception, if MCE is &quot; 1 &quot; , the receive interrupt will be issue unless a valid stop bit is received.

17-17

UART

S3F833B/F834B_UM_REV1.10

Setup Procedure for Multiprocessor Communications
Follow these steps to configure multiprocessor communications:
1. Set all S3F833B/F834B devices (masters and slaves) to UART0/UART1 mode 2 or 3.
2. Write the MCE bit of all the slave devices to &quot; 1 &quot; .
3. The master device's transmission protocol is:
-- First byte: the address
identifying the target
slave device (9th bit = &quot; 1 &quot; )
-- Next bytes: data
(9th bit = &quot; 0 &quot; )
4. When the target slave receives the first byte, all of the slaves are interrupted because the 9th data bit is &quot; 1 &quot; .
The targeted slave compares the address byte to its own address and then clears its MCE bit in order to
receive incoming data. The other slaves continue operating normally.

Full-Duplex Multi-S3F833B/F834B Interconnect

TxD
RxD
Master
S3F833B/
F834B

TxD
RxD
Slave1

TxD
RxD
Slave2

S3F833B/
F834B

S3F833B/
F834B

..
.

TxD
RxD
Slaven
S3F833B/
F834B

Figure 17-15. Connection Example for Multiprocessor Serial Data Communications

17-18

S3F833B/F834B_UM_REV1.10

18

PLL FREQUENCY SYNTHESIZER

PLL FREQUENCY SYNTHESIZER

OVERVIEW
The phase locked loop (PLL) frequency synthesizer locks medium frequency (MF), high frequency (HF), and very
high frequency (VHF) signals to a fixed frequency using a phase difference comparison system. As shown in
Figure 18-1, the PLL frequency synthesizer consists of an input selection circuit, programmable divider, phase
detector, reference frequency generator, and a charge pump.

PLLD (16-bit)

PLLMOD
NF

PLLMOD. 6

4

12

PLLMOD.7 and .4
VCOFM

Input
Circuit

VCOAM

Input
Circuit

Prescaler

Swallow
Counter

Selector

Programmable
Counter

Phase
Comparator

Charge
Pump

EO

PLLMOD.7 and .4
Reference Frequency
Generator
Unlock
Detector
PLLREF
ULFG

Figure 18-1. Block Diagram of the PLL Frequency Synthesizer

18-1

PLL FREQUENCY SYNTHESIZER

S3F833B/F834B_UM_REV1.10

PLL FREQUENCY SYNTHESIZER FUNCTION
The PLL frequency synthesizer divides the signal frequency at the VCOAM or VCOFM pin using the
programmable divider. It then outputs the phase difference between the divided frequency and reference
frequency at the EO.
NOTE
The PLL frequency synthesizer operates only when the CE pin is High level. When the CE pin is Low
level, the synthesizer is disable.
Input Selection Circuit
The input selection circuit consists of the VCOAM pin and VCOFM pins, an FM/AM selector, and two amplifiers.
The input selection circuit selects the frequency division method and the input pin of the PLL frequency.
You can choose one of two frequency division methods using the PLL mode register: 1) direct frequency division
method, or 2) pulse swallow method. The PLL mode register is also used to select the VCOAM or VCOFM pin as
the frequency input pin.
Programmable Divider
The programmable divider divides the frequency of the signal from the VCOAM and VCOFM pins in accordance
with the values contained in the swallow counter and programmable counter. The programmable divider consists
of prescalers, a swallow counter, and a programmable counter.
When the PLL operation starts, the contents of the PLL data registers (PLLD0-PLLD1) and the NF bit in the
PLLMOD register are automatically loaded into the 12-bit programmable counter and the 5-bit swallow counter.
When the 12-bit programmable down counter reaches zero, the contents of the data register are automatically
reloaded into the programmable counter and the swallow counter for the next counting operation.
If you modify the data register value while the PLL is operating, the new values are not immediately loaded into
the two counters; the new data are loaded into the two counters when the current count operation has been
completed.
The contents of the data register undetermined after initial power-on. However, the data register retains its current
value when the reset operation is initiated by an external reset or a change in level at the CE pin.
The swallow counter is a 5-bit binary down counter; the programmable counter is a 12-bit binary down counter.
The swallow counter is for FM, or AM mode. The swallow counter and programmable counter start counting down
simultaneously. When the swallow counter starts counting down, the 1/33 prescaler is selected. When the
swallow counter reaches zero, it stop operation and selects the 1/32 prescaler.

18-2

S3F833B/F834B_UM_REV1.10

PLL FREQUENCY SYNTHESIZER

PLL DATA REGISTER (PLLD)
The frequency division value of the swallow counter and programmable counter is set in the PLL data register
(PLLD0-PLLD1). PLL data register configuration is shown in Figure 18-2.

Programmable Counter
(Upper 12 bits)
16 15 14 13 12 11 10

9

Swallow Counter
(Lower 5 bits)
8

7

6

5

4

3

2

1

0

PLLMOD.5
PLLD b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
PLLD1(F4H/SET1, BANK0)

PLLD0(F5H/SET1, BANK0)

Figure 18-2. PLL Register Configuration
Direct Frequency Division and Pulse Swallow Formulas
In the direct frequency division method, the upper 12 bits are valid. In the pulse swallow method, all 16 bits are
valid. The upper 12 bit are set in the programmable counter and the lower 4 bits and the NF bit are set in the
swallow counter. The frequency division formulas for both methods, as set in the PLL data register, are shown
below:
-- Direct frequency division (AM) is
fR =

fVCOAM
N

Where the frequency division value (N) is 12 bits; fVCOAM = input frequency at the VCOAM pin
-- Pulse swallow system (AM, FM) is
fR =

fVCOFM
(N×32+M)

fR =

fVCOAM
(N×32+M)

where the frequency division values (N and M) are 12 bits and 5 bits, respectively; fVCOFM = input frequency at
the VCOFM pin. (fVCOAM = input frequency at the VCOAM pin)

18-3

PLL FREQUENCY SYNTHESIZER

S3F833B/F834B_UM_REV1.10

REFERENCE FREQUENCY GENERATOR
The reference frequency generator produce reference frequency which are then compared by the phase
compactor. As shown in Figure 18-3, the reference frequency generator divides a crystal oscillation frequency of
75 kHz or 4.5 MHz and generates the reference frequency (fR) for the PLL frequency synthesizer. Using the
PLLREF register, you can select from ten or eight different reference frequencies.

Data Bus
4

PLLREF
4
1 KHz
3 KHz
5 KHz
6.25 KHz

fxx
fxx/2

4.5MHz
MUX

Frequency
Divider

Selector

fxx * (5/8)
50 KHz

fxw

100 KHz

IFMOD.7-.6

Data Bus
4

PLLREF
4
1 KHz
3 KHz
3.125 KHz
6.25 KHz
75 KHz

Frequency
Divider

Selector

15 KHz
25 KHz

Figure 18-3. Reference Frequency Generator

18-4

IFMOD.4 MUX

To Phase
Detector

S3F833B/F834B_UM_REV1.10

PLL FREQUENCY SYNTHESIZER

PLL MODE REGISTER (PLLMOD)
The PLL mode register (PLLMOD) is used to start and stop PLL operation and to enable or disable 4-bit counter
for FVCOAM. PLLMOD values also determine the frequency dividing method.
PLLMOD PLLMOD.7 PLLMOD.6

NF

PLLMOD.4

PLLMOD.3 PLLMOD.2 PLLMOD.1 PLLMOD.0

PLLMOD.7-.4 selects the frequency dividing method. The basic configurations for the two frequency dividing
methods are as follows:
Direct Method
-- Used for AM mode
-- Swallow counter is not used
-- VCOAM pin is selected for input
Pulse Swallow Method
-- Used for FM, AM mode
-- Swallow counter is used
-- VCOFM pin and VCOAM pin are selected for input
The input frequency at the VCOAM or VCOFM pin is divided by the programmable divider. The frequency division
value of the programmable divider is written to the PLL data register.
When the pulse swallow method is selected by setting PLLMOD.7and .4, the input signal is first divided by a 1/32
or 1/33 prescaler and the divided frequency is input to the programmable divider. Table 18-1 shows PLLMOD
organization.

18-5

PLL FREQUENCY SYNTHESIZER

S3F833B/F834B_UM_REV1.10

Table 18-1. PLLMOD Organization
PLL Enable and INTIF/INTCE Interrupt Control Bits
0

INTIF interrupt is not pending (when read).;
Clear INTIF pending bit (when write).

1

INTIF interrupt is pending (when read).

0

Disable INTCE interrupt requests at CE pin.

1

Enable INTCE interrupt requests at CE pin.

0

INTCE interrupt is not pending (when read).;
Clear INTCE pending bit (when write).

1

PLLMOD.0

Enable INTIF interrupt.

0

PLLMOD.1

Disable INTIF interrupt.

1
PLLMOD.2

Enable PLL.

0

PLLMOD.3

Disable PLL.

1

PLLMOD.6

INTCE interrupt is pending (when read).

Frequency Division Method Selection Bit
PLLMOD.7
and
PLLMOD.4

Frequency Division
Method

Selected
Pin

Input
Voltage

Input
Frequency

Division
Value

-

-

-

-

0, 0

Not available

0, 1

Direct method for AM

VCOAM selected;
VCOFM pulled Low

100mVPP

0.5-5 MHz

16 to (212-1)

1, 0

Pulse swallow method
for AM

VCOAM selected;
VCOFM pulled Low

100mVPP

5-30 MHz

210 to (217-2)

1, 1

Pulse swallow method
for FM

VCOFM selected;
VCOAM pulled Low

100mVPP

30-130 MHz

210 to (217-2)

150mVPP

30-150 MHz

210 to (217-2)

NOTE: The NF bit, a one-bit frequency division value, is written to bit 0 in the swallow counter.

18-6

S3F833B/F834B_UM_REV1.10

PLL FREQUENCY SYNTHESIZER

PLL REFERENCE FREQUENCY SELECTION REGISTER (PLLREF)
The PLL reference frequency selection register (PLLREF) used to determine the reference frequency. You can
select one of ten reference frequencies by setting bits PLLREF.2-PLLREF.0 to the appropriate value.
PLLREF

PLLREF.7

PLLREF.6

PLLREF.5

PLLREF.4

PLLREF.3 PLLREF.2

PLLREF.1

PLLREF.0

You can select one of the reference frequencies by setting bits PLLREF.3-PLLREF.0.
Table 18-2. PLLREF Register Organization (When IFMOD.4=0))
PLLREF.3

PLLREF.2

PLLREF.1

PLLREF.0

Reference Frequency Selection

0

0

0

0

Select 1 kHz as reference frequency

0

0

0

1

Select 3 kHz as reference frequency

0

0

1

0

Select 5 kHz as reference frequency

0

0

1

1

Select 6.25 kHz as reference frequency

0

1

0

0

Select 9 kHz as reference frequency

0

1

0

1

Select 10 kHz as reference frequency

0

1

1

0

Select 12.5 kHz as reference frequency

0

1

1

1

Select 25 kHz as reference frequency

1

0

0

0

Select 50 kHz as reference frequency

1

0

0

1

Select 100 kHz as reference frequency

Table 18-3. PLLREF Register Organization (When IFMOD.4=1)
PLLREF.3

PLLREF.2

PLLREF.1

PLLREF.0

Reference Frequency Selection

X

0

0

0

Select 1 kHz as reference frequency

X

0

0

1

Select 3 kHz as reference frequency

X

0

1

0

Select 3.125 kHz as reference frequency

X

0

1

1

Select 5 kHz as reference frequency

X

1

0

0

Select 6.25 kHz as reference frequency

X

1

0

1

Select 12.5 kHz as reference frequency

X

1

1

0

Select 15 kHz as reference frequency

X

1

1

1

Select 25 kHz as reference frequency

NOTES:
1. If a system reset occurs during operation mode, the current contained is retained. If a system reset occurs after power-on,
the value is undefined.
2. If a system reset occurs during operation mode, the current contained is retained. If a system reset occurs after poweron, the value is "1".
3. The POF bit is read initially to check whether or not power has been turned on.
4. If the main clock is 9MHz, IFMOD.7-.6 should be set to "01".
5. If the main clock is 7.2MHz, IFMOD.7-.6 should be set to "10".
6. Where "X" is don't care

18-7

PLL FREQUENCY SYNTHESIZER

S3F833B/F834B_UM_REV1.10

PHASE DETECTOR, CHARGE PUMP, AND UNLOCK DETECTOR
The phase comparator compare the phase difference between divided frequency (fN) output from the
programmable divider and the reference frequency (fR) output from the reference frequency generator.
The charge pump outputs the phase comparator's output from error output pins EO. The relation between the
error output pin, divided frequency fN, and reference frequency fR is shown below:
fR &amp; gt; fN = Low level output
fR &amp; lt; fN = High level output
fR = fN = Floating level
A PLL operation starts when a value is loaded to the PLLMOD register, The PLL unlock flag (ULFG) in the PLL
reference register, PLLREF, provides status information regarding the reference frequency and divided frequency.
The unlock detector detects the unlock state of the PLL frequency synthesizer. The unlock flag in the PLLREF
register is set to "1" in an unlock state. When ULFG = "0", the PLL locked state is selected.
PLLREF.7-.4

ULFG

CEFG

IFCFG

POFG

F8H at bank 0 of set 1

The ULFG flag is set continuously at a period of reference frequency fR by the unlock detector. You must
therefore read the ULFG flag in the PLLREF register at periods longer than 1/fR of the reference frequency. ULFG
is reset wherever it is read.
PLL operation is controlled by the state of the CE (chip enable) pin. The PLL frequency synthesizer is disabled
and the error output pin is set to floating state whenever the CE pin is Low. When CE pin is High level, the PLL
operates normally.
The chip enable flag in the PLLREF register, CEFG, provides the status of the current level of the CE pin.
Whenever the state of the CE pin goes from Low to High, the CEFG flag is set to "1" and a CE reset operation
occurs. When the CE pin goes from High to Low, the CEFG flag is cleared to "0" and a CE interrupt is generated.
The power on flag in the PLLREF register, POFG, is set by initiated power-on reset, but it is not set when a reset
occurs on the normal operation. The POFG flag is cleared to "0" by writing "0" to POFG flag bit in PLLREF.

18-8

S3F833B/F834B_UM_REV1.10

PLL FREQUENCY SYNTHESIZER

USING THE PLL FREQUENCY SYNTHESIZER
This section describes the steps you should follow when using the PLL direct frequency division method and the
pulse swallow method. In each case, you must make the following selections in this order:
1. Frequency division method:

Direct frequency division (AM, AM/5) or pulse swallow (AM, FM)

2. Input pin:

VCOAM or VCOFM

3. Reference frequency:

fR

4. Frequency division value:

N

Direct Frequency Division Method
Select the direct frequency division method by writing a "00" or "01" to PLLMOD.7 and .4.
The VCOAM pin is configured for input when you select the direct frequency division method.
Select the reference frequency by writing the appropriate values to the PLLREF register.
The frequency division value is
N=

fVCOAM
fR

Where fVCOAM are the input frequency at the VCOAM pin, and fR is the reference frequency.
Example:
The following data are used to receive an AM-band broadcasting station:
Receive frequency:
Reference frequency:
Intermediate frequency:

1422 kHz
3 kHz
+ 450 kHz

The frequency division value N is calculated as follows:
N=

fVCOAM (1422+450)×103
=
= 624 (decimal)
fR
3×103
= 270H (hexadecimal)

You would modify the PLL data register and PLLMOD.7-.4 register as follows:

PLLD0

PLLD1
0

0

1

0

0

1

1

1

0

0

0

0

x

PLMOD.7-.4
x

x

x

0

0

1

x
NF

2
NOTE:

7

0

In the direct method, the contents of PLLD0.3-PLLD0.0 and NF are not evaluated.

18-9

PLL FREQUENCY SYNTHESIZER

S3F833B/F834B_UM_REV1.10

Pulse Swallow Method
1. Select the pulse swallow method by writing a &quot; 10 &quot; or &quot; 11 &quot; to PLLMOD.7and .4.
2. The VCOFM or VCOAM pins are configured for input when you select the pulse swallow method.
3. Select the reference frequency by writing the appropriate value to the PLLREF register.
4. Calculate the frequency division value as follows:

32N + M =

fVCOAM
fVCOFM
or 32N + M =
fR
fR

Where fVCOFM and fVCOAM are the input frequency at the VCOFM pin and the VCOAM pin, respectively and fR is the
fVCOFM
fVCOAM
fVCOFM
fVCOAM
reference frequency, N is the quotient of 32f
or 32f
and M is the remainder of 32f
or 32f
.
R
R
R
R
Example:
The following data are used to receive an FM-band broadcasting station:
Receive frequency:
Reference frequency:
Intermediate frequency:

100.0 MHz
25 kHz
10.7 MHz

The frequency division value N and M are calculated as follows:
fVCOFM (100.0 + 10.7) × 106
=
= 4428 = 138 × 32 + 12
fR
25 × 103
N = 138 (decimal) = 8AH (hexadecimal)
M = 12 (decimal) = 0CH (hexadecimal)
You would modify the PLL data register and PLLMOD.7-.4 register as follows:

PLLD0

PLLD1
0

0

0
0

18-10

0

1

0

0
8

0

1

0

1
A

0

0
0

PLLMOD.7-.4
1

1

0
C

0

0

1

1

0
NF

S3F833B/F834B_UM_REV1.10

19

INTERMEDIATE FREQUENCY COUNTER

INTERMEDIATE FREQUENCY COUNTER

OVERVIEW
The S3F833B/F834B uses an intermediate frequency counter (IFC) to counter the frequency of the AM or FM
signal at FMIF or AMIF pin. The IFC block consists of a 1/2 divider, gate control circuit, IFC mode register
(IFMOD) and a 20-bit binary counter. The gate control circuit, which controls the frequency counting time, is
programmed using the IFMOD register. Four different gate times can be selected using IFMOD register settings.
During gate time, the 20-bit IFC counts the input frequency at the FMIF or AMIF pins. The FMIF or AMIF pin input
signal for the 20-bit counter is selected using IFMOD register settings.
The 20-bit binary counter (IFCNT2-IFCNT0) can be read by 8-bit register addressing mode only. When the FMIF
pin input signal is selected, the signal is divided by two. When the AMIF pin input signal is directly connected to
the IFC, it is not divided.
By setting IFMOD register, the gate is opened for 2-ms, 8-ms, or 16-ms periods. During the open period of the
gate, input frequency is counted by the 20-bit counter. When the gate is closed, the counting operation is
complete, and an interrupt is generated.

1/2
Divider

FMIF

IF Counter
(20 bit)

Selector

8

AMIF
Gate Control
Circuit

Clock
Source Select

Data Bus
IRQIF

IFMOD

4

3

2

1

2 mS
8 mS
16 mS

0
Gate Signal
Generator

Data Bus
500 Hz Internal Signal
(when fxx =4.5/7.2/9.0 MHz, or fxt = 75 kHz)
NOTES:
1.
If the main clock is 9MHz, IFMOD.7-.6 should be set to &quot; 01 &quot; .
2.
If the main clock is 7.2MHz, IFMOD.7-.6 should be set to &quot; 10 &quot; .

Figure 19-1. IF Counter Block Diagram

19-1

INTERMEDIATE FREQUENCY COUNTER

S3F833B/F834B_UM_REV1.10

IFC MODE REGISTER (IFMOD)
The IFC mode register (IFMOD) is a 8-bit register that is used to select the input pin, FMIF input select for FMIF or
AMIF counter mode, PLL/IFC operation voltage, clock divider for PLL/IFC, and gate time. Setting IFMOD register
reset IFC value and IFC gate flag value, and starts IFC operation.
IFMOD IFMOD.7 IFMOD.6 Not used IFMOD.4 IFMOD.3 IFMOD.2 IFMOD.1 IFMOD.0

F6H at bank 0 of set 1

IFC operation starts when you select AMIF or FMIF as the IFC input pin. A reset operation clears all IFMOD
values to &quot; 0 &quot; .
Table 19-1. IFMOD Organization
Pin Selection Bits
IFMOD.3

IFMOD.2

Effect of Control Setting

0

0

IFC is disabled; FMIF/AMIF are pulled down and FMIF/AMIF's feed-back
resistor are off.

0

1

Enable IFC operation; AMIF pin is selected; FMIF is pulled down and FMIF's
feed-back resistor is off.

1

0

Enable IFC operation; FMIF is selected; AMIF is pulled down and AMIF's feedback resistor is off.

1

1

Enable IFC operation; Both AMIF and FMIF are selected.

Gate Time Select Bits
IFMOD.1

IFMOD.0

0

0

Gate time is 2 ms.

0

1

Gate time is 8 ms.

1

0

Gate time is 16 ms.

1

1

Gate is open

19-2

Select Gate Time

S3F833B/F834B_UM_REV1.10

INTERMEDIATE FREQUENCY COUNTER

IFC GATE FLAG REGISTER (PLLREF.5)
PLLREF.7-.4

ULFG

CEFG

IFCFG

POFG

F8H at bank 0 of set 1

When IFC operation is started by setting IFMOD, the IFC gate flag (IFCFG) is cleared to "0". After a specified gate
time has elapsed, the IFCFG bit is automatically set to "1". This lets you check whether a IFC counting operation
has been completed or not.
The IFC interrupt can also be used to check whether or not a IFC counting operation is complete.
Table 19-1. IFMOD Organization (Continued)
System Clock Control Bit for Frequency Synthesizer, IF Counter, Watch Timer
IFMOD.7

IFMOD.6

PLL, IFC, Watch Timer Clock Setting

0

0

The supplied clocks are not dived. (fxx = 4.5 MHz)

0

1

The supplied clocks are dived by 2. (fxx = 9 MHz)

1

0

The supplied clocks are dived by 8/5. (fxx = 7.2 MHz)

1

1

Not available

NOTES:
1. If the main clock is 9MHz, IFMOD.7-.6 should be set to "01".
2. If the main clock is 7.2MHz, IFMOD.7-.6 should be set to "10".

PLL/IFC Clock Selection Bit
IFMOD.4

PLL, IFC Clock Selection

0

Select fxx (4.5 MHz, 7.2 MHz, 9.0 MHz)

1

Select fxt (75 kHz)

NOTE: When the CPU clock is supplied from PLL-OSC, the PLL/IFC clock should be from sub clock (IFMOD.4=1)

19-3

INTERMEDIATE FREQUENCY COUNTER

S3F833B/F834B_UM_REV1.10

GATE TIMES
When you write a value to IFMOD, the IFC gate is opened for a 2-millisecond, 8-millisecond, or 16-millisecond
interval, setting with a rising clock edge. When the gate is open, the frequency at the AMIF or FMIF pin is counted
by the 20-bit counter. When the gate closes, the IFC gate flag (IFCFG) is set to &quot; 1". An interrupt is then generated
and the IFC interrupt pending bit (PLLMOD.2) is set.
Figure 19-2 shows gate timings with a 1 kHz internal clock.

Gate Time

Clock (1 kHz)

2 ms

8 ms

16 ms
Counting Period
Gate open here
IFMOD is written;
IFCFG flag is cleared to &quot; 0 &quot; .

Figure 19-2. Gate Timing (2, 8, or 16 ms)

19-4

Counting ends;
IFCFG flag is set to &quot; 1 &quot; and
PLLMOD.2 is set to &quot; 1 &quot; .

S3F833B/F834B_UM_REV1.10

INTERMEDIATE FREQUENCY COUNTER

Selecting "Gate Remains Open"
If you select "gate remain open" (IFMOD.0, and IFMOD.1 = &quot; 11 &quot; , the IFC counts the input signal during the open
period of the gate. The gate closes the next time a value is written to IFMOD.

Clock (1 kHz)

~~
~~

Gate Time
Counting Period
The gate closes when IFMOD is rewritten
Gate is opened by writing IFMOD

Figure 19-3. Gate Timing (When Open)
When you select "gate remains open" as the gating time, you can control the opening and closing of the gate in
one of two ways:
-- Set the gate time to a specific interval (2-ms, 8-ms, or 16-ms) by setting bits IFMOD.1 and IFMOD.0.

Gate Time

Set IFMOD.1 to IFMOD.0 = &quot; 1 &quot;

Set non-open gate time (2-, 8-, 16-ms) by
bit IFMOD.1 and IFMOD.0

-- Disable IFC operation by clearing bits IFMOD.3 and IFMOD.2 to "0". This method lets the gate remain open,
and stops the counting operation.

Gate Time

Set IFMOD.1 and IFMOD.0 = &quot; 1 &quot;

Set IFMOD.3 and IFMOD.2 = &quot; 0 &quot; ,
IFC counting operation is stopped.

19-5

INTERMEDIATE FREQUENCY COUNTER

S3F833B/F834B_UM_REV1.10

Gate Time Errors
A gate time error occurs whenever the gate signals are not synchronized to the interval instruction clock. That is,
the IFC does not start counter operation until a rising edge of the gate signal is detected, even though the counter
start instruction (setting bits IFMOD.3 and IFMOD.2) has been executed. Therefore, there is a maximum 1-ms
timing error (see Figure 19-4).
After you have executed the IFC start instruction, you can check the gate state at any time. Please note, however
that the IFC does not actually start its counting operation until stabilization time for the gate control signal has
elapsed.

Instruction Execution
(IFMOD Setting)
1ms
Clock (1 kHz)

Actual Gate
Signal (1 ms)

Resulting
Gate Signal

Gate Time Errors

Actual Counting Period

Figure 19-4. Gate Timing (1-ms Error)
Counting Errors
The IF counter counts the rising edges of the input signal in order to determine the frequency. If the input signal is
High level when the gate is open, one additional pulse is counted. When the gate is close, however, counting is
not affected by the input signal status. In other words, the counting error is "+1, 0".

19-6

S3F833B/F834B_UM_REV1.10

INTERMEDIATE FREQUENCY COUNTER

IF COUNTER (IFC) OPERATION
IFMOD register bits 3 and 2 are used to select the input pin and to start or stop IFC counting operation. You stop
the counting operation by clearing IFMOD.3 and IFMOD.2 to "0". The IFC retains its previous value until IFMOD
register values are specified.
Setting bits IFMOD.3 and IFMOD.2 starts the frequency counting operation. Counting continues as long as the
gate is open. The 20-bit counter value is automatically cleared to 00000H after it overflows (at FFFFFH), and
continues counting from zero. The 20-bit count value (IFCNT2-IFCNT0) can be read by register addressing mode.
A reset operation clears the counter to zero.
IFCNT0

IFCNT0.7

IFCNT0.6

IFCNT0.5

IFCNT0.4

IFCNT0.3

IFCNT0.2

IFCNT0.1

IFCNT0.0

IFCNT1

IFCNT1.7

IFCNT1.6

IFCNT1.5

IFCNT1.4

IFCNT1.3

IFCNT1.2

IFCNT1.1

IFCNT1.0

IFCNT2

Not used

Not used

Not used

Not used

IFCNT2.3

IFCNT2.2

IFCNT2.1

IFCNT2.0

When the specified gate open time has elapsed, the gate closes in order to complete the counter operation. At
this time, the IFC interrupt pending bit (PLLMOD.2) is automatically set to "1" and an interrupt is generated. The
pending bit must be cleared to "0" by software when the interrupt is serviced. The IFC gate flag (IFCFG) is set to
"1" at the same time the gate is closed. Since the IFCFG flag is cleared to "0" when IFC operation start, you can
check the IFCFG flag to determine when IFC operation stops (that is, when the specified gate open time has
elapsed).
The frequency applied to FMIF or AMIF pin is counted while the gate is open. The relationship between the count
value (N) and input frequencies fAMIF and fFMIF is shown below.
-- FMIF pin input frequency is
fFMIF

=

N (DEC)
X2
TG

when TG = gate time (2 ms, 8 ms, 16 ms)
-- AMIF pin input frequency is
fAMIF

=

N (DEC)
TG

when TG = gate time (2 ms, 8 ms, 16 ms)
Table 19-2 shows the range of frequency that you can apply to the AMIF and FMIF pins.
Table 19-2. IF Counter Frequency Characteristics
Pin

Voltage Level

Frequency Range

AMIF

100 m VPP (min)

0.1 MHz to 1 MHz

FMIF

100 m VPP (min)

5 MHz to 15 MHz

19-7

INTERMEDIATE FREQUENCY COUNTER

S3F833B/F834B_UM_REV1.10

INPUT PIN CONFIGURATION
The AMIF and FMIF pins have built-in AC amplifiers (see Figure 19-5). The DC component of the input signal
must be stripped off by the external capacitor.
When the AMIF or FMIF pin is selected for the IFC function and the switch is turned on voltage of each pin
increases to approximately 1/2 VDD after a sufficiently long time. If the pin voltage does not increase to
approximately 1/2 VDD, the AC amplifier exceeds its operating range, possibly causing an IFC malfunction. To
prevent this from occurring, you should program a sufficiently long time delay interval before starting the count
operation.

SW

External
Frequency

C
FMIF
AMIF

Figure 19-5. AMIF and FMIF Pin Configuration

19-8

To Internal
Counter

S3F833B/F834B_UM_REV1.10

INTERMEDIATE FREQUENCY COUNTER

IFC DATA CALCULATION
Selecting the FMIF pin for IFC Input
First, divide the signal at the FMIF pin, and then apply this value to the IF counter. This means that the IF counter
value is equal to one-half of the input signal frequency.
FMIF input frequency (fFMIF): 10.7 MHz
Gate time (TG): 8 ms
IFC counter value (N):
N = (fFMIF/2) × TG
= 10.7 × 106/2 × 8 × 10-3
= 42800
= A730H
Bin

0

0

0

Dec

1

0

0

IFCNT

0

1

IFCNT2

0

0

1

A

1

1

0

0

7

1

1

0

0

3

0

0

0

0

0

IFCNT1

IFCNT0

Selecting the AMIF Pin for IFC Input
The signal at AMIF pin is directly input to the IF counter.
AMIF input frequency (fAMIF): 450 kHz
Gate time (TG): 8 ms
IFC counter value (N):
N = (fAMIF) × TG
= 450 × 103 × 8 × 10-3
= 3600
= E10H
Bin

0

0

0

Dec

0

IFCNT

IFCNT2

0

0

0

0

0

1

0

1

1
E

IFCNT1

0

0

0

0

1

0

1

0
0

IFCNT0

19-9

INTERMEDIATE FREQUENCY COUNTER

S3F833B/F834B_UM_REV1.10

NOTES

19-10

S3F833B/F834B_UM_REV1.10

20

ELECTRICAL DATA

ELECTRICAL DATA

OVERVIEW
In this chapter, S3F833B/F834B electrical characteristics are presented in tables and graphs. The information is
arranged in the following order:
--

Absolute maximum ratings

--

D.C. electrical characteristics

--

A.C. electrical characteristics

--

Input/output capacitance

--

Data retention supply voltage in stop mode

--

A/D converter electrical characteristics

--

LVR timing characteristics

--

PLL electrical characteristics

--

PLL oscillation characteristics

--

Serial I/O timing characteristics

--

UART timing characteristics

--

Oscillation characteristics

--

Oscillation stabilization time

20-1

ELECTRICAL DATA

S3F833B/F834B_UM_REV1.10

Table 20-1. Absolute Maximum Ratings
(TA= 25 °C)
Parameter

Symbol

Conditions

Rating

Unit

VDD

-

- 0.3 to + 4.6

V

Supply voltage
Input voltage

VI

Output voltage

VO

Output current high

IOH

- 0.3 to VDD + 0.3

Ports 0 - 10

- 0.3 to VDD + 0.3

-

- 60

One I/O pin active

+ 30

Total pin current for ports

IOL

+ 100

TA

Operating temperature

mA

- 15

All I/O pins active
Output current low

One I/O pin active

°C

- 25 to + 85

-

- 40 to + 85
TSTG

Storage temperature

-

- 65 to + 150

Table 20-2. D.C. Electrical Characteristics
(TA = - 25 °C to + 85 °C at VDD = 2.0 V to 3.6 V, TA = - 40 °C to + 85 °C at VDD = 2.4 V to 3.6 V)
Parameter

Typ

Max

Unit

fx = 0 - 4.2MHz,
TA = -25? to +85?

2.0

-

3.6

V

2.4

-

3.6

fx = 0 - 12.0MHz

2.7

-

3.6

PLL/IFC operation

VDD

Min

fx = 0 - 4.2MHz,

Operating voltage

Symbol

Conditions

2.7

-

3.6

TA = -40? to +85?

0.7VDD

-

VDD

All ports except for VIH1

0.8 VDD

-

VDD

nRESET, CE

0.8 VDD

-

VDD

VIH4

Xin, Xout, XTin, XTout

VDD - 0.1

-

VDD

VIL1

P1.4-P1.7, P3, P4, P5, P9.4-P9.7,
P10

-

-

0.3 VDD

VIL2

All ports except for VIH1

-

-

0.2 VDD

VIL3

nRESET, CE

-

-

0.2 VDD

VIL4

20-2

P1.4-P1.7, P3, P4, P5, P9.4-P9.7,
P10

VIH3

Input low voltage

VIH1
VIH2

Input high voltage

Xin, Xout, XTin, XTout

-

-

0.1

V

V

S3F833B/F834B_UM_REV1.10

ELECTRICAL DATA

Table 20-2. D.C. Electrical Characteristics (Continued)
(TA = - 25 °C to + 85 °C at VDD = 2.0 V to 3.6 V, TA = - 40 °C to + 85 °C at VDD = 2.4 V to 3.6 V)
Parameter

Symbol

Conditions

Min

Typ

Max

Unit
V

VOH1

VDD = 2.7 V to 3.6 V
EO; IOH1 = -1 mA

VDD - 2.0

-

-

VOH2

VDD = 2.7 V to 3.6 V
All output ports
IOH2 = -1 mA,

VDD - 1.0

-

-

VOL1

VDD = 2.7 V to 3.6 V
EO; IOL1 = 1 mA

-

-

1.0

VOL2

VDD = 2.7 V to 3.6 V
All output ports
IOL2 = 10 mA,

-

-

1.5

ILIH1

VI = VDD
All input pins except for ILIH2

-

-

3

ILIH2

VI = VDD
Xin, Xout, XTin, XTout

ILIL1

VI = 0 V
All input pins except for
nRESET, ILIL2

ILIL2

VI = 0 V
Xin, Xout, XTin, XTout

Output high
leakage current

ILOH

VOUT = VDD
All output pins

-

-

3

uA

Output low
leakage current

ILOL

VOUT = 0 V
All output pins

-

-

-3

uA

Pull-Up
Resistors

RL1

VI = 0 V; VDD = 3 V,

40

70

140

k?

200

450

800

Output High
Voltage

Output low
voltage

Input High
Leakage Current

Input low
leakage current

V

uA

20
-

-

-3

uA

-20

TA = 25 °C, Ports 0 - 10
RL2

VI = 0 V; VDD = 3 V,
TA = 25 °C, nRESET

ROSC1

VDD = 3 V, TA = 25 °C
XIN = VDD, XOUT = 0V

600

1600

3000

ROSC2

VDD = 3 V, TA = 25 °C
XTIN = VDD, XTOUT = 0 V

3000

6000

12000

LCD Voltage
Dividing Resistor

RLCD

TA = 25 °C

40

80

120

k?

? VLCD-COMi?
Voltage Drop
(i = 0-7)

VDC

-15uA per common pin

-

-

120

mV

Oscillator Feed
Back Resistors

k?

20-3

ELECTRICAL DATA

S3F833B/F834B_UM_REV1.10

Table 20-2. D.C. Electrical Characteristics (Continued)
(TA = - 25 °C to + 85 °C at VDD = 2.0 V to 3.6 V, TA = - 40 °C to + 85 °C at VDD = 2.4 V to 3.6 V)
Parameter

Symbol

Conditions

Min

Typ

Max

Unit

-

-

120

mV

0.75VDD-0.2

0.75VDD

0.75VDD+0.2

V

0.5VDD-0.2

0.5VDD

0.5VDD+0.2

0.25VDD-0.2

0.25VDD

0.25VDD+0.2

-

4.0

9.0

12.0 MHz

12.0

27.0

Run mode; CE= 0V, 4.5 MHz
VDD = 3.3 V,
12.0 MHz
Crystal oscillator
C1 = C2 = 22pF

1.5

3.5

4.5

10.5

4.5 MHz

0.5

1.2

12.0 MHz

1.5

3.6

40.0

80.0

12.0

25.0

0.5

2.0

-

10

? VLCD-SEGx?
Voltage Drop
(x = 0-39)

VDS

-15uA per segment pin

Middle Output
Voltage (1)

VLC1

VDD = 2.7V to 3.6V, 1/4 bias
LCD clock = 0Hz, VLC0 = VDD

VLC2
VLC3

Supply
Current (2)

IDD1(3)

IDD2 (3)

IDD3 (3)

Run mode;
PLL operating
CE= VDD,
VDD = 3.3 V,
Crystal oscillator
C1 = C2 = 22pF

4.5 MHz

Idle mode; CE= 0V,
VDD = 3.3 V,
Crystal oscillator
C1 = C2 = 22pF

IDD4 (4)

Sub Operating mode; CE = 0V,
75kHz Crystal Oscillator,
VDD = 3.3 V, TA = 25°C

IDD5 (4)

Sub Idle mode; CE= 0V,
75kHz Crystal Oscillator,
VDD = 3.3 V, TA = 25°C

IDD6 (5)

Stop mode;
VDD = 3.3 V

TA = 25°C
TA =
-40°C~+85°C

-

mA

?A

NOTES:
1. It is middle output voltage when the VDD and VLC0 pin are connected.
2. Supply current does not include current drawn through internal pull-up resistors, LCD voltage dividing resistors, the LVR
block, and external output current loads.
3. IDD1, IDD2 and IDD3 include power consumption for sub clock oscillation.
4. IDD4 and IDD5 are current when main clock oscillation stops and the sub clock is used (OSCCON.7=1).
5. IDD6 is current when main and sub clock oscillation stops.
6. Every values in this table is measured when bits 4-3 of the system clock control register (CLKCON.4-.3) is set to 11B.

20-4

S3F833B/F834B_UM_REV1.10

ELECTRICAL DATA

Table 20-3. A.C. Electrical Characteristics
(TA = - 25 °C to + 85 °C at VDD = 2.0 V to 3.6 V, TA = - 40 °C to + 85 °C at VDD = 2.4 V to 3.6 V)
Parameter

Symbol

Interrupt input high, low
width (P0.0-P0.7)

tINTH, tINTL

nRESET input low width

tRSL

Conditions

Min

Typ

Max

Unit

All interrupt, VDD = 3 V

500

-

-

ns

VDD = 3 V

10

-

-

?s

tINTL

External
Interrupt

tINTH

0.8 VDD
0.2 VDD

Figure 20-1. Input Timing for External Interrupts

tRSL

nRESET
0.2 VDD

Figure 20-2. Input Timing for nRESET

20-5

ELECTRICAL DATA

S3F833B/F834B_UM_REV1.10

Table 20-4. Input/Output Capacitance
(TA = - 40 °C to + 85 °C at VDD = 0 V)
Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Input
capacitance

CIN

f = 1 MHz; unmeasured pins
are returned to VSS

-

-

10

pF

Output
capacitance

COUT

I/O capacitance

CIO

Table 20-5. Data Retention Supply Voltage in Stop Mode
(TA = - 40 °C to + 85 °C)
Parameter

Symbol

Data retention
supply voltage

IDDDR

Max

Unit

-

3.6

V

-

1

uA

Stop mode, TA = 25 °C
Disable LVR block

~
~

Stop Mode
Data Retention Mode

~
~

VDD

Typ

-

VDDDR = 2V

Min
2.0

VDDDR

Data retention
supply current

Conditions

nRESET
Occurs Oscillation
Stabilization
Time
Normal
Operating Mode

VDDDR
Execution of
STOP Instrction
nRESET

0.8 VDD
0.2 VDD

NOTE:

tWAIT

tWAIT is the same as 4096 x 16 x 1/fxx.

Figure 20-3. Stop Mode Release Timing Initiated by RESET

20-6

S3F833B/F834B_UM_REV1.10

ELECTRICAL DATA

VDD

~
~

~
~

Oscillation
Stabillization TIme
IDLE Mode

Stop Mode

Data Retention Mode
VDDDR

Normal
Operation Mode

Execution of
STOP Instruction
Interrupt
0.2VDD
tWAIT
NOTE:

tWAIT is the same as 16 x 1/fBT. (fBT is basic timer clock selected)

Figure 20-4. Stop Mode Release Timing Initiated by Interrupts

20-7

ELECTRICAL DATA

S3F833B/F834B_UM_REV1.10

Table 20-6. A/D Converter Electrical Characteristics
(TA = - 40 °C to + 85 °C, VDD = 2.7 V to 3.6 V, VSS = 0 V)
Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Resolution

-

-

10

-

bit

Total accuracy

-

-

-

?3

LSB

-

-

?2

-

?1

VDD = 3.072 V
VSS = 0 V
CPU clock = 11.1 MHz

Integral linearity error

ILE

Differential linearity
error

DLE

Offset error of top

EOT

?1

?3

Offset error of bottom

EOB

?1

?3

25

-

-

?S

Conversion time

(1)

TCON

10-bit resolution
50 x fxx/4, fxx = 8 MHz

Analog input voltage

VIAN

-

VSS

-

VDD

V

Analog input
impedance

RAN

-

2.0

1000

-

M?

Analog ground

AVSS

-

VSS

-

VSS + 0.3

V

Analog input current

IADIN

VDD = 3.3 V

-

-

10

?A

Analog block current (2)

IADC

VDD = 3.3 V

-

0.5

1.5

mA

100

500

nA

VDD = 3.3 V
When power down mode

NOTES:
1. 'Conversion time' is the time required from the moment a conversion operation starts until it ends.
2. IADC is an operating current during A/D conversion.

20-8

S3F833B/F834B_UM_REV1.10

ELECTRICAL DATA

Table 20-7. Low Voltage Reset Electrical Characteristics
(TA = - 25 °C to + 85 °C at VDD = 2.0 V to 3.6 V, TA = - 40 °C to + 85 °C at VDD = 2.4 V to 3.6 V, VSS = 0 V)
Parameter

Symbol

Min

Max

Unit

2.1

TA = 25 °C

Typ
2.3

2.4

V

2.4

VLVR

Voltage of LVR

Test Condition

2.6

2.8

tR

-

10

-

-

?S

VDD voltage off time

tOFF

-

0.5

-

-

S

Hysteresis voltage of LVR

?V

-

-

10

100

mV

-

70

120

?A

Min

Typ

Max

Unit

Sine wave input

0.1

-

VDD

V

VCOAM mode, sine wave input;
VIN = 0.1Vp-p

0.5

-

5

MHz

VCOAM mode, sine wave input;
VIN = 0.1Vp-p

5

-

30

VCOFM mode, sine wave input;
VIN = 0.1Vp-p

30

-

130

VCOFM mode, sine wave input;
VIN = 0.15Vp-p

30

-

150

fAMIF

AMIF mode, sine wave input;
VIN = 0.1Vp-p

0.1

-

1.0

fFMIF

FMIF mode, sine wave input;
VIN = 0.1Vp-p

5

-

15

VDD voltage rising time

IDDPR

Current consumption

VDD = 3.3 V

NOTE: The current of LVR circuit is consumed when LVR is enabled by "Smart Option".

tOFF

tR

VDD

0.9VDD
0.1VDD

Figure 20-5. LVR (Low Voltage Reset) Timing
Table 20-8. PLL Electrical Characteristics
(TA = - 40 °C to + 85 °C, VDD = 2.7 V to 3.6 V, VSS = 0 V)
Parameter
VCOFM, VCOAM, FMIF
and AMIF input voltage
(peak to peak)
Frequency

Symbol
VIN

fVCOAM

fVCOFM

Conditions

20-9

ELECTRICAL DATA

S3F833B/F834B_UM_REV1.10

Table 20-9. PLL Oscillator Electrical Characteristics
(TA = - 40 °C to + 85 °C, VDD = 2.7 V to 3.6 V, VSS = 0 V)
Parameter

Symbol

PLL current

FIN

Conditions

FVCO

Output clock frequency

C1

Typ

Max

Unit

-

1.8

3.0

mA

C1 = 22nF,

-

75

-

kHz

C2 = 2.2nF

LPF

VSS

Min

R = 20k?,

IPLL

Input clock frequency

Circuit

-

4.5

-

MHz

7.2

R

9.0
Output clock duty

-

Accuracy

60

%

30

200

mS

-

-

-

-

TD

Setting time

40

C2

2

4

%

Table 20-10. Synchronous SIO Electrical Characteristics
(TA = - 25 °C to + 85 °C at VDD = 2.0 V to 3.6 V, TA = - 40 °C to + 85 °C at VDD = 2.4 V to 3.6 V)
Parameter

SI setup time to

Min

Typ

Max

Unit

tKCY

External SCK0/ SCK1 source

1,000

-

-

ns

1,000

External SCK0/ SCK1 source

500

-

-

Internal SCK0/ SCK1 source

SCK0/ SCK1 high, low width

Conditions
Internal SCK0/ SCK1 source

SCK0/ SCK1 cycle time

Symbol

tKCY/2-50

External SCK0/SCK1 source

250

-

-

Internal SCK0/SCK1 source

250

tKSI

External SCK0/SCK1 source

400

-

-

Internal SCK0/SCK1 source

400

tKSO

External SCK0/SCK1 source

-

-

300

tKH, tKL
tSIK

SCK0/SCK1 high
SI hold time to
SCK0/SCK1 high
Output delay for
SCK0/SCK1 to SO

20-10

Internal SCK0/SCK1 source

250

ns

S3F833B/F834B_UM_REV1.10

ELECTRICAL DATA

tCKY
tKL

tKH

SCK0/
SCK1

0.7VDD
0.3VDD
tSIK

tKSI
0.7VDD

SI0/
SI1

Input Data
0.3VDD
tKSO

SO0/
SO1

Output Data

Figure 20-6. Serial Data Transfer Timing

20-11

ELECTRICAL DATA

S3F833B/F834B_UM_REV1.10

Table 20-11. UART Timing Characteristics in Mode 0 (11.1 MHz)
(TA = - 25°C to + 85°C at VDD = 2.0 V to 3.6 V, TA = - 40°C to + 85°C at VDD = 2.4 V to 3.6 V,
Load Capacitance = 80pF)
Parameter

Symbol

Min

Typ

Max

Unit

tSCK

1,160

tCPU × 16

1,500

ns

Output data setup to clock rising edge

tS1

500

tCPU × 13

-

Clock rising edge to input data valid

tS2

-

-

500

Output data hold after clock rising edge

tH1

tCPU - 50

tCPU

-

Input data hold after clock rising edge

tH2

0

-

-

Serial port clock High, Low level width

tHIGH, tLOW

450

tCPU × 8

890

Serial port clock cycle time

NOTES:
1. All timings are in nanoseconds (ns) and assume a 11.1-MHz CPU clock frequency.
2. The unit tCPU means one CPU clock period.

tHIGH

tSCK
tLOW

VIH
VIL

Figure 20-7. Waveform for UART Timing Characteristics

20-12

S3F833B/F834B_UM_REV1.10

ELECTRICAL DATA

tSCK

Shift
Clock

tH1
Data
Out

tS1
D0

D1

tS2
Data
In

D3

D4

D5

D6

D7

tH2

Valid

NOTE:

D2

Valid

Valid

Valid

Valid

Valid

Valid

Valid

The symbols shown in this diagram are defined as follows:
fSCK
tS1
tS2
tH1
tH2

Serial port clock cycle time
Output data setup to clock rising edge
Clock rising edge to input data valid
Output data hold after clock rising edge
Input data hold after clock rising edge

Figure 20-8. Timing Waveform for the UART Module

20-13

ELECTRICAL DATA

S3F833B/F834B_UM_REV1.10

Table 20-12. Main Oscillator Characteristics
(TA = - 25 °C to + 85 °C at VDD = 2.0 V to 3.6 V, TA = - 40 °C to + 85 °C at VDD = 2.4 V to 3.6 V)
Oscillator

Clock Configuration

Typ

Max

Units

Main oscillation
frequency

2.0 V - 3.6 V,
TA = -25? to +85?

0.4

-

4.2

MHz

2.4 V - 3.6 V,
TA = -40? to +85?

0.4

-

4.2

0.4

-

12.0

2.0 V - 3.6 V,
TA = -25? to +85?

0.4

-

4.2

2.4 V - 3.6 V,
TA = -40? to +85?

0.4

-

4.2

0.4

-

12.0

2.0 V - 3.6 V,
TA = -25? to +85?

0.4

-

4.2

2.4 V - 3.6 V,
TA = -40? to +85?

0.4

-

4.2

2.7 V - 3.6 V

XIN

Min

2.7 V - 3.6 V

C1

Test Condition

2.7 V - 3.6 V

Crystal

Parameter

0.4

-

12.0

3.3 V

0.4

-

1

MHz

XOUT

Ceramic
Oscillator

C1
XIN

Main oscillation
frequency

XOUT

External
Clock

XIN

XIN input
frequency

XOUT

Frequency

RC
Oscillator

XIN
R
XOUT

Table 20-13. Sub Oscillation Characteristics
(TA = - 25 °C to + 85 °C at VDD = 2.0 V to 3.6 V, TA = - 40 °C to + 85 °C at VDD = 2.4 V to 3.6 V)
Oscillator
Crystal

Clock Configuration
C1
XT IN

Parameter

Test Condition

Min

Typ

Max

Units

Sub oscillation
frequency

2.0 V - 3.6 V,
TA = -25? to +85?

-

75.0

-

kHz

2.4 V - 3.6 V,
TA = -40? to +85?

-

75.0

-

2.0 V - 3.6 V,
TA = -25? to +85?

32

-

100

2.4 V - 3.6 V,
TA = -40? to +85?

32

-

100

XT OUT

External
clock

XT IN
XT OUT

20-14

XTIN input
frequency

S3F833B/F834B_UM_REV1.10

ELECTRICAL DATA

Table 20-14. Main Oscillation Stabilization Time
(TA = - 25 °C to + 85 °C at VDD = 2.0 V to 3.6 V, TA = - 40 °C to + 85 °C at VDD = 2.4 V to 3.6 V)
Oscillator

Test Condition

Min

Typ

Max

Unit

-

-

40

ms

Ceramic

fx &amp; gt; 1 MHz
Oscillation stabilization occurs when VDD is
equal to the minimum oscillator voltage range.

-

-

10

ms

External clock

XIN input high and low width (tXH, tXL)

62.5

-

1250

ns

Crystal

1/fx
tXL

t XH

XIN

VDD-0.1V
0.1 V

Figure 20-9. Clock Timing Measurement at XIN

Table 20-15. Sub Oscillation Stabilization Time
(TA = - 25 °C to + 85 °C at VDD = 2.0 V to 3.6 V, TA = - 40 °C to + 85 °C at VDD = 2.4 V to 3.6 V)
Oscillator

Test Condition

Min

Typ

Max

Unit

-

-

-

10

s

5

-

15

?s

Crystal
External clock

XTIN input high and low width (tXH, tXL)

1/fxt
tXTL

tXTH

XT IN

VDD-0.1V
0.1 V

Figure 20-10. Clock Timing Measurement at XTIN

20-15

ELECTRICAL DATA

S3F833B/F834B_UM_REV1.10

Instruction Clock

Main oscillation frequency

4.0 MHz

12.0 MHz
9.0 MHz
7.2 MHz

1.125 MHz

4.5 MHz
4.2 MHz

100 kHz

400 kHz

2

3

3.5

4
3.6V

2.7V
Supply Voltage (V)

CPU Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16)
PLL/IFC operating voltage range is 2.7V to 3.6V.

Figure 20-11. Operating Voltage Range (TA = -25 °C to + 85 °C)

Main oscillation frequency

Instruction Clock

12.0 MHz

4.0 MHz

9.0 MHz
7.2 MHz
1.125 MHz

4.5 MHz
4.2 MHz

100 kHz

400 kHz

2

3
2.4V

2.7V

3.5

4
3.6V

Supply Voltage (V)
CPU Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16)
PLL/IFC operating voltage range is 2.7V to 3.6V.

Figure 20-12. Operating Voltage Range (TA = -40 °C to + 85 °C)

20-16

S3F833B/F834B_UM_REV1.10

21

MECHANICAL DATA

MECHANICAL DATA

OVERVIEW
The S3F833B/F834B microcontroller is currently available in 100-pin-QFP/TQFP package.
23.90 ? 0.30
0-8

20.00 ? 0.20

+ 0.10

14.00 ? 0.20

0.10 MAX

100-QFP-1420C

#100

#1
0.65

0.80 ? 0.20

(0.83)

17.90 ? 0.30

0.15 - 0.05

+ 0.10

0.30 - 0.05
0.15 MAX

0.05 MIN
(0.58)
2.65 ? 0.10
3.00 MAX

0.10 MAX
0.80 ? 0.20
NOTE: Dimensions are in millimeters.

Figure 21-1. Package Dimensions (100-QFP-1420C)

21-1

MECHANICAL DATA

S3F833B/F834B_UM_REV1.10

16.00 ? 0.20
0-7

14.00

14.00

+ 0.073
- 0.037

0.08 MAX

100-TQFP-1414

0.45-0.75

16.00 ? 0.20

0.127

#100

#1
0.50

0.20

+ 0.07
- 0.03

0.08 MAX

0.05-0.15
(1.00)
1.00 ? 0.05
1.20 MAX

NOTE: Dimensions are in millimeters.

Figure 21-2. Package Dimensions (100-TQFP-1414)

21-2

S3F833B/F834B_UM_REV1.10

22

S3F833B/F834B FLASH MCU

S3F833B/F834B FLASH MCU

OVERVIEW
The S3F833B/F834B single-chip CMOS microcontroller is the Flash MCU version. It has an on-chip Flash MCU
ROM instead of a masked ROM. The Flash ROM is accessed by serial data format.
The S3F833B/F834B is fully compatible with the S3F833B/F834B, both in function and in pin configuration.
Because of its simple programming requirements, the S3F833B/F834B is ideal as an evaluation chip for the
S3F833B/F834B.

22-1

S3F833B/F834B FLASH MCU

S3F833B/F834B_UM_REV1.10

VDDPLL0
CE
P10.5/RXD0
P10.6/TXD0
P10.7
P0.0/T0CLK/RXD1
P0.1/T0CAP/TXD1
P0.2/T0OUT/T0PWM
P0.3/T1CLK
P0.4/T1OUT
P0.5/T2CLK
P0.6/T2OUT
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT3
P1.4/AD8/INT4
P1.5/AD9/INT5
P1.6/AD10/INT6
P1.7/AD11/INT7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4/AD4
P2.5/AD5
P2.6/AD6
P2.7/AD7
P3.0/BUZ
P3.1/SCK0
P3.2/SO0
P3.3/SI0
SDAT/P3.4/SCK1
SCLK/P3.5/SO1
VDD
VSS
XOUT
XIN
VPP/TEST
XTIN
XTOUT
nRESET/nRESET
LPF
AVDD
P3.6/SI
P4.0/SEG39
P4.1/SEG38
P4.2/SEG37
P4.3/SEG36
P4.4/SEG35

S3F833B
100-QFP 1420C

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

EO/P10.4
FMIF/P10.3
AMIF/P10.2
VSSPLL
VCOAM/P10.1
VCOFM/P10.0
VDDPLL1
VLC0/P9.7
VLC1/P9.6
VLC2/P9.5
VLC3/P9.4
COM0/P8.7
COM1/P8.6
COM2/P8.5
COM3/P8.4
COM4/SEG0/P8.3
COM5/SEG1/P8.2
COM6/SEG2/P8.1
COM7/SEG3/P8.0
SEG4/P9.3
SEG5/P9.2
SEG6/P9.1
SEG7/P9.0
SEG8/P7.7
SEG9/P7.6
SEG10/P7.5
SEG11/P7.4
SEG12/P7.3
SEG13/P7.2
SEG14/P7.1

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
SEG15/P7.0
SEG16/P6.7
SEG17/P6.6
SEG18/P6.5
SEG19/P6.4
SEG20/P6.3
SEG21/P6.2
SEG22/P6.1
SEG23/P6.0
SEG24/P5.7
SEG25/P5.6
SEG26/P5.5
SEG27/P5.4
SEG28/P5.3
SEG29/P5.2
SEG30/P5.1
SEG31/P5.0
SEG32/P4.7
SEG33/P4.6
SEG34/P4.5

Figure 22-1. S3F833B Pin Assignments (100-QFP-1420C)

22-2

S3F833B/F834B_UM_REV1.10

S3F833B/F834B FLASH MCU

AMIF/P10.2
FMIF/P10.3
P10.4/EO
VDDPLL0
CE
P10.5/RXD0
P10.6/TXD0
P10.7
P0.0/T0CLK/RXD1
P0.1/T0CAP/TXD1
P0.2/T0OUT/T0PWM
P0.3/T1CLK
P0.4/T1OUT
P0.5/T2CLK
P0.6/T2OUT
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT3
P1.4/AD8/INT4
P1.5/AD9/INT5
P1.6/AD10/INT6
P1.7/AD11/INT7
P2.0/AD0
P2.1/AD1
76
77
78
79
70
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

P2.2/AD2
P2.3/AD3
P2.4/AD4
P2.5/AD5
P2.6/AD6
P2.7/AD7
P3.0/BUZ
P3.1/SCK0
P3.2/SO0
P3.3/SI0
SDAT/P3.4/SCK1
SCLK/P3.5/SO1
VDD
VSS
XOUT
XIN
VPP/TEST
XTIN
XTOUT
nRESET/nRESET
LPF
AVDD
P3.6/SI
P4.0/SEG39
P4.1/SEG38

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

S3F834B
100-TQFP 1414

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

VSSPLL
VCOAM/P10.1
VCOFM/P10.0
VDDPLL1
VLC0/P9.7
VLC1/P9.6
VLC2/P9.5
VLC3/P9.4
COM0/P8.7
COM1/P8.6
COM2/P8.5
COM3/P8.4
COM4/SEG0/P8.3
COM5/SEG1/P8.2
COM6/SEG2/P8.1
COM7/SEG3/P8.0
SEG4/P9.3
SEG5/P9.2
SEG6/P9.1
SEG7/P9.0
SEG8/P7.7
SEG9/P7.6
SEG10/P7.5
SEG11/P7.4
SEG12/P7.3

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
SEG13/P7.2
SEG14/P7.1
SEG15/P7.0
SEG16/P6.7
SEG17/P6.6
SEG18/P6.5
SEG19/P6.4
SEG20/P6.3
SEG21/P6.2
SEG22/P6.1
SEG23/P6.0
SEG24/P5.7
SEG25/P5.6
SEG26/P5.5
SEG27/P5.4
SEG28/P5.3
SEG29/P5.2
SEG30/P5.1
SEG31/P5.0
SEG32/P4.7
SEG33/P4.6
SEG34/P4.5
SEG35/P4.4
SEG36/P4.3
SEG37/P4.2

Figure 22-2. S3F834B Pin Assignments (100-TQFP-1414)

22-3

S3F833B/F834B FLASH MCU

S3F833B/F834B_UM_REV1.10

Table 22-1. Descriptions of Pins Used to Read/Write the Flash ROM
Main Chip

During Programming

Pin Name

Pin Name

Pin No.

I/O

Function

P3.4

SDAT

13(11)

I/O

Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input/push-pull output port.

P3.5

SCLK

14(12)

I/O

Serial clock pin. Input only pin.

TEST

VPP

19(17)

I

Power supply pin for Flash ROM cell writing
(indicates that FLASH MCU enters into the
writing mode). When 12.5 V is applied, FLASH
MCU is in writing mode and when 3.3 V is
applied, FLASH MCU is in reading mode.
(Option)

nRESET

nRESET

22(20)

I

Chip Initialization

VDD, VSS

VDD, VSS

15(13)
16(14)

-

Power supply pin for logic circuit. VDD should be
tied to +3.3V during programming.

NOTES: Parentheses indicate pin number for 100-TQFP-1414 package.

22-4

S3F833B/F834B_UM_REV1.10

S3F833B/F834B FLASH MCU

ON BOARD WRITING
The S3F833B/F834B needs only 6 signal lines including VDD and GND pins for writing internal flash memory with
serial protocol. Therefore the on-board writing is possible if the writing signal lines are considered when the PCB
of application board is designed.

Circuit design guide
At the flash writing, the writing tool needs 6 signal lines that are GND, VDD, nRESET, TEST, SDAT and SCLK.
When you design the PCB circuits, you should consider the usage of these signal lines for the on-board writing.
In case of TEST pin, normally test pin is connected to GND but in writing mode the programming these two cases,
a resistor should be inserted between the TEST pin and GND. The nRESET, SDAT and SCLK should be treated
under the same consideration.
Please be careful to design the related circuit of these signal pins because rising/falling timing of VPP, SCLK and
SDAT is very important for proper programming.

R

SCLK

To Application circuit

SCLK(I/O)
R

SDAT

SDAT(I/O)

To Application circuit
R

nRESET

nRESET

To Application circuit
R

VPP

VPP(TEST)
C VPP

C nRESET

VDD

VPP

SDAT

VSS
VDD
GND

nRESET

SCLK
C nRESET and C VPP are used to
improve the noise effect.

SPW-uni , GW-uni , AS-pro, US-pro

Figure 22-3. PCB Design Guide for on Board Programming

22-5

S3F833B/F834B FLASH MCU

S3F833B/F834B_UM_REV1.10

Reference Table for Connection
Table 22-2. Reference Table for Connection
Pin Name

I/O mode
in Applications

Resistor
(need)

VPP (TEST)

Input

Yes

nRESET

Input

Yes

Input

Yes

SDAT(I/O)
SCLK(I/O)

Output
Input
Output

(NOTE)

No

Yes
(NOTE)

No

Required value
RVpp is 10 Kohm ~ 50 Kohm.
CVpp is 0.01uF ~ 0.02uF.
RnRESET is 2 Kohm ~ 5 Kohm.
CnRESET is 0.01uF ~ 0.02uF.
RSDAT is 2 Kohm ~ 5 Kohm.
-
RSCLK is 2 Kohm ~ 5 Kohm.
-

NOTES:
1. In on-board writing mode, very high-speed signal will be provided to pin SCLK and SDAT. And it will cause

some damages to the application circuits connected to SCLK or SDAT port if the application circuit is designed
as high speed response such as relay control circuit. If possible, the I/O configuration of SDAT, SCLK pins had
better be set to input mode.
2. The value of R, C in this table is recommended value. It varies with circuit of system.

22-6

S3F833B/F834B_UM_REV1.10

23

DEVELOPMENT TOOLS

DEVELOPMENT TOOLS

OVERVIEW
Samsung provides a powerful and easy-to-use development support system on a turnkey basis. The development
support system is composed of a host system, debugging tools, and supporting software. For a host system, any
standard computer that employs Win95/98/2000/XP as its operating system can be used. A sophisticated
debugging tool is provided both in hardware and software: the powerful in-circuit emulator, OPENice-i500 and SK1200, for the S3C7-, S3C9-, and S3C8- microcontroller families. Samsung also offers supporting software that
includes, debugger, an assembler, and a program for setting options.
TARGET BOARDS
Target boards are available for all the S3C8/S3F8-series microcontrollers. All the required target system cables
and adapters are included on the device-specific target board. TB833B/834B is a specific target board for the
development of application systems using TB833B/834B.
PROGRAMMING SOCKET ADAPTER
When you program S3F833B/834B's flash memory by using an emulator or OTP/MTP writer, you need a specific
programming socket adapter for S3F833B/834B.

23-1

DEVELOPMENT TOOLS

S3F833B/F834B_UM_REV1.10

IBM-PC AT or Compatible
Emulator [SK-1200 (RS-232, USB)
or OPENice i-500 (RS-232) ]

RS-232C/USB

Target
Application
System

OTP/MTP Writer Block

RAM Break/Display Block

BUS

Probe
Adapter
Trace/Timer Block

SAM8 Base Block

POD

TB833B/834B
Target
Board
EVAChip

Power Supply Block

Figure 23-1. Emulator Product Configuration

23-2

S3F833B/F834B_UM_REV1.10

DEVELOPMENT TOOLS

TB833B/834B TARGET BOARD
The TB833B/834B target board can be used for development of the S3F833B/F834B microcontroller.
The TB833B/834B target board is operated as target CPU with Emulator (SK-1200, OPENice-i500)).

Off

VDD

TB833B/834B

To User_VCC

On
IDLE

STOP

+

RESET

JP2

CN1
25

Y1

4

LPF

50

1

J102

J101

60

2

1

51

52

200

208 QFP
S3E8330
EVA Chip
1

160

100
110

J4

J3

Y1
(sub-clock)

FMIF
AMIF
VCOAM
VCOFM
EO

J5
J6

150

On
CE
50 99

100

JP1
ON

1

JP8

49

Off

SW1
SMDS2+

SMDS2

50-Pin Connector

100-Pin Connector

100-Pin Connector

J2

7411

50-Pin Connector

CN1

U2

+

GND

In-Circuit Emulator
(SK-1200, OPENice-i500)

2

3

4

Smart Option
Selection

Figure 23-2. TB833B/834B Target Board Configuration
NOTE : The symbol '

' marks start point of jumper signals.

23-3

DEVELOPMENT TOOLS

S3F833B/F834B_UM_REV1.10

Table 23-1. Components of TB833B/834B
Symbols

Usage

Description

CN1

100-pin connector

Connection between emulator and TB833B/834B target
board.

J101, J102

50-pin connector

Connection between target board and user application
system

RESET

Push button

Generation low active reset signal to TB833B/834B EVAchip

VCC, GND

POWER connector

External power connector for TB833B/834B

STOP, IDLE LED

STOP/IDLE Display

Indicate the status of STOP or IDLE of S3F833B/834B
EVA-chip on TB833B/834B target board

Table 23-2. Setting of the Jumper in TB833B/834B
JP#

Description

1-2 Connection

2-3 Connection

Default
Setting

JP2

Clock source selection

When using the internal clock source which is generated from
Emulator, join connector 2-3 and 4-5 pin. If user wants to use
the external clock source like a crystal, user should change the
jumper setting from 1-2 to 5-6 and connect J1 to an external
clock source.

Y1

External clock source

Connecting points for external clock source

SW1

Smart option selection

The Smart Option can be selected by this switch when
the Smart Option source is selected by external. The
SW1.3-SW1.1 are comparable to the 003FH.3-.1. The
SW1.4 is comparable to the 003FH.0.

JP8

MDS version

SMDS2+,SK-1200,
OPENIce I-500

SMDS2

Join 1-2

Target Board is not supplied
VDD from user System.

Target Board is supplied VDD

Join 2-3

Target System is supplied VDD
To
User_Vcc

o

IDLE LED
This LED is ON when the evaluation chip (S3E8330) is in idle mode.

o

STOP LED
This LED is ON when the evaluation chip (S3E8330) is in stop mode

23-4

from user System.

Emulator
2-3
4-5

S3F833B/F834B_UM_REV1.10

DEVELOPMENT TOOLS

J101
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

P2.1/AD1
P2.3/AD3
P2.5/AD5
P2.7/AD7
P3.1/SCK0
P3.3/SI0
P3.5/SO1
VSS
N.C
N.C
nRESET
AVDD
P4.0/SEG39
P4.2/SEG37
P4.4/SEG35
P4.6/SEG33
P5.0/SEG31
P5.2/SEG29
P5.4/SEG27
P5.6/SEG25
P6.0/SEG23
P6.2/SEG21
P6.4/SEG19
P6.5/SEG17
P7.0/SEG15

P7.1/SEG14
P7.3/SEG12
P7.5/SEG10
P7.7/SEG8
P9.1/SEG6
P9.3/SEG4
P8.1/COM6/SEG2
P8.3/COM4/SEG0
P8.5/COM2
P8.7/COM0
P9.5/VLC2
P9.7/VLC0
P10.0/VCOFM
VSSPLL
P10.3/FMIF
VDDPLL0
P10.5/RXD0
P10.7
P0.1/T0CAP/TXD1
P0.3/T1CLK
P0.5/T2CLK
P1.0/INT0
P1.2/INT2
P1.4/INT4/AD8
P1.6/INT6/AD10

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

50-Pin DIP Connector

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

50-Pin DIP Connector

P2.0/AD0
P2.2/AD2
P2.4/AD4
P2.6/AD6
P3.0/BUZ
P3.2/SO0
P3.4/SCK1
VDD
N.C
TEST
N.C
LPF
P3.6/SI1
P4.1/SEG38
P4.3/SEG36
P4.5/SEG34
P4.7/SEG32
P5.1/SEG30
P5.3/SEG28
P5.5/SEG26
P5.7/SEG24
P6.1/SEG22
P6.3/SEG20
P6.5/SEG18
P6.7/SEG16

J102
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

P7.2/SEG13
P7.4/SEG11
P7.6/SEG9
P9.0/SEG7
P9.2/SEG5
P8.0/COM7/SEG3
P8.2/COM5/SEG1
P8.4/COM3
P8.6/COM1
P9.4/VLC3
P9.6/VLC1
VDDPLL1
VCOAM/P10.1
P10.2/AMIF
P10.4/EO
CE
P10.6/TXD0
P0.0/T0CLK/RXD1
P0.2/T0OUT/T0PWM
P0.4/T1OUT
P0.6/T2OUT
P1.1/INT1
P1.3/INT3
P1.5/INT5/AD9
P1.7/INT7/AD11

Figure 23-3. 50-Pin Connectors (J101, J102) for TB833B/834B

Target Board

1

J102

J102
2

51

52

51

52

J101

50-Pin DIP
Connector

1

2

49

50

50-Pin DIP
Connectors

J101

Target System

Target Cable for 50-Pin Connector

49

50

99 100

99 100

Figure 23-4. S3E8330 Cables for 100-QFP Package

23-5

DEVELOPMENT TOOLS

S3F833B/F834B_UM_REV1.10

THIRD PARTIES FOR DEVELOPMENT TOOLS
SAMSUNG provides a complete line of development tools for SAMSUNG's microcontroller. With long experience
in developing MCU systems, our third parties are leading companies in the tool's technology. SAMSUNG In-circuit
emulator solution covers a wide range of capabilities and prices, from a low cost ICE to a complete system with
an OTP/MTP programmer.
In-Circuit Emulator for SAM8 family
o

OPENice-i500

o

SmartKit SK-1200

OTP/MTP Programmer
o

SPW-uni

o

GW-uni

o

AS-pro

o

US-pro

Development Tools Suppliers
Please contact our local sales offices or the 3rd party tool suppliers directly as shown below for getting
development tools.
8-bit In-Circuit Emulator
OPENice - i500

AIJI System
o
o
o
o

SK-1200

Seminix
o
o
o
o

23-6

TEL: 82-31-223-6611
FAX: 82-331-223-6613
E-mail : openice@aijisystem.com
URL : http://www.aijisystem.com

TEL: 82-2-539-7891
FAX: 82-2-539-7819
E-mail: sales@seminix.com
URL: http://www.seminix.com

S3F833B/F834B_UM_REV1.10

DEVELOPMENT TOOLS

OTP/MTP PROGRAMMER (WRITER)

SPW-uni

SEMINIX

Single OTP/ MTP/FLASH Programmer

o
o
o

o
o
o
o
o
o
o
o
o

Download/Upload and data edit function
PC-based operation with USB port
Full function regarding OTP/MTP/FLASH MCU
programmer
(Read, Program, Verify, Blank, Protection..)
Fast programming speed (4Kbyte/sec)
Support all of SAMSUNG OTP/MTP/FLASH MCU
devices
Low-cost
NOR Flash memory (SST,Samsung...)
NAND Flash memory (SLC)
New devices will be supported just by adding
device files or upgrading the software.

o

TEL: 82-2-539-7891
FAX: 82-2-539-7819.
E-mail:
sales@seminix.com
URL:
http://www.seminix.com

GW-uni

SEMINIX

Gang Programmer for OTP/MTP/FLASH MCU

o
o
o

o
o
o
o
o
o
o
o
o
o
o

8 devices programming at one time
Download/Upload and data edit function
PC-based operation with USB port
Full function regarding OTP/MTP/FLASH MCU
programmer
(Read, Program, Verify, Blank, Protection..)
Fast programming speed (4Kbyte/sec)
Support all of SAMSUNG OTP/MTP/FLASH MCU
devices
Low-cost
NOR Flash memory (SST,Samsung...)
NAND Flash memory (SLC)
New devices will be supported just by adding
device files or upgrading the software.
Will be developed in March, 2008.

o

TEL: 82-2-539-7891
FAX: 82-2-539-7819.
E-mail:
sales@seminix.com
URL:
http://www.seminix.com

23-7

DEVELOPMENT TOOLS

S3F833B/F834B_UM_REV1.10

OTP/MTP PROGRAMMER (WRITER) (Continued)

AS-pro

SEMINIX

On-board programmer for Samsung Flash MCU

o
o
o

o

Portable &amp; Stand alone Samsung
OTP/MTP/FLASH Programmer for After Service
o Small size and Light for the portable use
o Support all of SAMSUNG OTP/MTP/FLASH
devices
o HEX file download via USB port from PC
o Very fast program and verify time
( OTP:2Kbytes per second, MTP:10Kbytes per
second)
o Internal large buffer memory (118M Bytes)
o Driver software run under various O/S
(Windows 95/98/2000/XP)
o Full function regarding OTP/MTP programmer
(Read, Program, Verify, Blank, Protection..)
o Two kind of Power Supplies
(User system power or USB power adapter)
o Support Firmware upgrade

o

TEL: 82-2-539-7891
FAX: 82-2-539-7819.
E-mail:
sales@seminix.com
URL:
http://www.seminix.com

US-pro

o
o
o

Flash writing adapter board

SEMINIX

o

Specific flash writing socket only for S3F833B

o

23-8

SEMINIX

Portable Samsung OTP/MTP/FLASH Programmer
o Portable Samsung OTP/MTP/FLASH Programmer
o Small size and Light for the portable use
o Support all of SAMSUNG OTP/MTP/FLASH
devices
o Convenient USB connection to any IBM compatible
PC or Laptop computers.
o Operated by USB power of PC
o PC-based menu-drive software for simple operation
o Very fast program and verify time
( OTP:2Kbytes per second, MTP:10Kbytes per
second)
o Support Samsung standard Hex or Intel Hex format
o Driver software run under various O/S
(Windows 95/98/2000/XP)
o Full function regarding OTP/MTP programmer
(Read, Program, Verify, Blank, Protection..)
o Support Firmware upgrade

- 100QFP
Specific flash writing socket only for S3F834B
- 100TQFP

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TEL: 82-2-539-7891
FAX: 82-2-539-7819.
E-mail:
sales@seminix.com
URL:
http://www.seminix.com

TEL: 82-2-539-7891
FAX: 82-2-539-7819.
E-mail:
sales@seminix.com
URL:
http://www.seminix.com


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