wma_dec.ZIP

Mały odtwarzacz MP3,AAC,MP4 na AT91SAM7S256

Witam ponownie Wprowadziłem poprawki do dekodera WMA, które pozwoliły na odtwarzanie plików CBR oraz VBR z fsample od 8kHz do 48kHz i bitrate od 8kb/s do 320kb/s. Ponadto wprowadziłem odczyt strumienia WMA z 1kB bufora RAM uzupełnianego na bież±co danymi odczytywanymi z pliku WMA zapisanego we Flash (poprzednio był odczyt danych wprost z pamięci Flash) w ramach przygotowania do póĽniejszego odczytu strumienia WMA np. z karty SD. Niestety, dekoder ten (jak na razie) uniemożliwia odtwarzanie plików WMA Lossless. Przyczyn± tego jest zwrot warto¶ci NULL przez funkcję avcodec_find_decoder(wma->codec_id) w pliku main.c, gdyż jej argumentem jest wtedy wma->codec_id == CODEC_ID_NONE i póki co, nie wiem, co z tym dalej zrobić... Może kto¶ będzie mieć jaki¶ pomysł :) Dla pozostałych WMA argumentem tej funkcji jest wma->codec_id == CODEC_ID_WMAV2 i dekoder pracuje normalnie. Do projektu dekodera doł±czam paczkę z kilkoma przykładowymi strumieniami WMA w plikach *.c. Trzeba doł±czyć do projektu jeden z tych plików, odkomentować odpowiedni± linię w pliku demo.h, skompilować i wgrać do mikrokontrolera. Wówczas ten będzie w kółko odtwarzał materiał dĽwiękowy z tego strumienia WMA (teraz demo z Winamp-a). Acha, w poprzednim opisie nie dodałem, oprócz 125kB heap i 1,5kB stack dekoder wykorzystuje też 64kB pamięć TCM Data RAM w tym mikrokontrolerze (STM32F407 na płytce Discovery). Pozdrawiam, KT

  • wma_dec.ZIP
    • asf.c
    • asf.h
    • stm32f4xx.h
    • stm32f4xx_dac.h
    • dma.c
    • avformat.h
    • Array
    • demo.c
    • parser.c
    • i2c.h
    • wmadeci.h
    • includes.h
    • utils.c
    • spi3_i2s.c
    • codeccontext.h
    • main.c
    • avio.h
    • Array
    • stm32f4xx_spi.h
    • wmadec_tab.c
    • wmadec_tab.h
    • stm32f4xx_conf.h
    • global_variables.h
    • i2c.c
    • misc.h
    • futils.c
    • demo44_1.c
    • aviobuf.c
    • wma_dec.hzp
    • stm32f4xx_i2c.h
    • IO_init.c
    • Czterdziestolatek_44_1.c
    • IO_init.h
    • wma_dec.hzs
    • stm32f4xx_rcc.h
    • Czterdziestolatek.c
    • wmadeci.c
    • defines.h
    • misc.c
    • stm32f4xx_dma.h
    • demo.h
    • spi3_i2s.h


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wma_dec.ZIP > asf.c

#include " avformat.h "
#include " wmadeci.h "
#include " asf.h "
#include & lt; string.h & gt;
#include & lt; stdio.h & gt;
#include & lt; ctype.h & gt;


#define MP3_FRAME_SIZE 1152
#define PACKET_SIZE 3200
#define PACKET_HEADER_SIZE 12
#define FRAME_HEADER_SIZE 17


static const GUID asf_header = {
0x75B22630, 0x668E, 0x11CF, { 0xA6, 0xD9, 0x00, 0xAA, 0x00, 0x62, 0xCE, 0x6C },
};

static const GUID file_header = {
0x8CABDCA1, 0xA947, 0x11CF, { 0x8E, 0xE4, 0x00, 0xC0, 0x0C, 0x20, 0x53, 0x65 },
};

static const GUID stream_header = {
0xB7DC0791, 0xA9B7, 0x11CF, { 0x8E, 0xE6, 0x00, 0xC0, 0x0C, 0x20, 0x53, 0x65 },
};

static const GUID audio_stream = {
0xF8699E40, 0x5B4D, 0x11CF, { 0xA8, 0xFD, 0x00, 0x80, 0x5F, 0x5C, 0x44, 0x2B },
};

static const GUID audio_conceal_none = {
// 0x49f1a440, 0x4ece, 0x11d0, { 0xa3, 0xac, 0x00, 0xa0, 0xc9, 0x03, 0x48, 0xf6 },
// New value lifted from avifile
0x20fb5700, 0x5b55, 0x11cf, { 0xa8, 0xfd, 0x00, 0x80, 0x5f, 0x5c, 0x44, 0x2b },
};

static const GUID video_stream = {
0xBC19EFC0, 0x5B4D, 0x11CF, { 0xA8, 0xFD, 0x00, 0x80, 0x5F, 0x5C, 0x44, 0x2B },
};

static const GUID video_conceal_none = {
0x20FB5700, 0x5B55, 0x11CF, { 0xA8, 0xFD, 0x00, 0x80, 0x5F, 0x5C, 0x44, 0x2B },
};


static const GUID comment_header = {
0x75b22633, 0x668e, 0x11cf, { 0xa6, 0xd9, 0x00, 0xaa, 0x00, 0x62, 0xce, 0x6c },
};

static const GUID codec_comment_header = {
0x86D15240, 0x311D, 0x11D0, { 0xA3, 0xA4, 0x00, 0xA0, 0xC9, 0x03, 0x48, 0xF6 },
};
static const GUID codec_comment1_header = {
0x86d15241, 0x311d, 0x11d0, { 0xa3, 0xa4, 0x00, 0xa0, 0xc9, 0x03, 0x48, 0xf6 },
};

static const GUID data_header = {
0x75b22636, 0x668e, 0x11cf, { 0xa6, 0xd9, 0x00, 0xaa, 0x00, 0x62, 0xce, 0x6c },
};

static const GUID index_guid = {
0x33000890, 0xe5b1, 0x11cf, { 0x89, 0xf4, 0x00, 0xa0, 0xc9, 0x03, 0x49, 0xcb },
};

static const GUID head1_guid = {
0x5fbf03b5, 0xa92e, 0x11cf, { 0x8e, 0xe3, 0x00, 0xc0, 0x0c, 0x20, 0x53, 0x65 },
};

static const GUID head2_guid = {
0xabd3d211, 0xa9ba, 0x11cf, { 0x8e, 0xe6, 0x00, 0xc0, 0x0c, 0x20, 0x53, 0x65 },
};

static const GUID extended_content_header = {
0xD2D0A440, 0xE307, 0x11D2, { 0x97, 0xF0, 0x00, 0xA0, 0xC9, 0x5E, 0xA8, 0x50 },
};

/* I am not a number !!! This GUID is the one found on the PC used to
generate the stream */
static const GUID my_guid = {
0, 0, 0, { 0, 0, 0, 0, 0, 0, 0, 0 },
};

const CodecTag codec_wav_tags[] = {
{ CODEC_ID_MP2, 0x50 },
{ CODEC_ID_MP3, 0x55 },
{ CODEC_ID_AC3, 0x2000 },
{ CODEC_ID_PCM_S16LE, 0x01 },
{ CODEC_ID_PCM_U8, 0x01 }, /* must come after s16le in this list */
{ CODEC_ID_PCM_ALAW, 0x06 },
{ CODEC_ID_PCM_MULAW, 0x07 },
{ CODEC_ID_ADPCM_MS, 0x02 },
{ CODEC_ID_ADPCM_IMA_WAV, 0x11 },
{ CODEC_ID_ADPCM_IMA_DK4, 0x61 }, /* rogue format number */
{ CODEC_ID_ADPCM_IMA_DK3, 0x62 }, /* rogue format number */
{ CODEC_ID_WMAV1, 0x160 },
{ CODEC_ID_WMAV2, 0x161 },
{ 0, 0 },
};


enum CodecID codec_get_id(const CodecTag *tags, unsigned int tag)
{
while (tags- & gt; id != 0) {
if( toupper((tag & gt; & gt; 0) & 0xFF) == toupper((tags- & gt; tag & gt; & gt; 0) & 0xFF)
& & toupper((tag & gt; & gt; 8) & 0xFF) == toupper((tags- & gt; tag & gt; & gt; 8) & 0xFF)
& & toupper((tag & gt; & gt; 16) & 0xFF) == toupper((tags- & gt; tag & gt; & gt; 16) & 0xFF)
& & toupper((tag & gt; & gt; 24) & 0xFF) == toupper((tags- & gt; tag & gt; & gt; 24) & 0xFF))
return tags- & gt; id;
tags++;
}
return CODEC_ID_NONE;
}


static void get_guid(ByteIOContext *s, GUID *g)
{
int i;

g- & gt; v1 = get_le32(s);
g- & gt; v2 = get_le16(s);
g- & gt; v3 = get_le16(s);
for(i=0;i & lt; 8;i++)
g- & gt; v4[i] = get_byte(s);
}


int wav_codec_get_id(unsigned int tag, int bps)
{
int id;
id = codec_get_id(codec_wav_tags, tag);
if (id & lt; = 0)
return id;
/* handle specific u8 codec */
if (id == CODEC_ID_PCM_S16LE & & bps == 8)
id = CODEC_ID_PCM_U8;
return id;
}


void get_wav_header(ByteIOContext *pb, CodecContext *codec, int size)
{
int id;

id = get_le16(pb);
codec- & gt; codec_type = CODEC_TYPE_AUDIO;
//codec- & gt; codec_tag = id;
codec- & gt; channels = get_le16(pb);
codec- & gt; sample_rate = get_le32(pb);
codec- & gt; bit_rate = get_le32(pb) * 8;
codec- & gt; block_align = get_le16(pb);
if (size == 14) { /* We're dealing with plain vanilla WAVEFORMAT */
codec- & gt; bits_per_sample = 8;
}else
codec- & gt; bits_per_sample = get_le16(pb);
codec- & gt; codec_id = wav_codec_get_id(id, codec- & gt; bits_per_sample);

if (size & gt; 16) { /* We're obviously dealing with WAVEFORMATEX */
codec- & gt; extradata_size = get_le16(pb);
if (codec- & gt; extradata_size & gt; 0) {
if (codec- & gt; extradata_size & gt; size - 18)
codec- & gt; extradata_size = size - 18;
codec- & gt; extradata = av_mallocz(codec- & gt; extradata_size);
get_buffer(pb, codec- & gt; extradata, codec- & gt; extradata_size);
} else
codec- & gt; extradata_size = 0;

/* It is possible for the chunk to contain garbage at the end */
if (size - codec- & gt; extradata_size - 18 & gt; 0)
url_fskip(pb, size - codec- & gt; extradata_size - 18);
}
}


static void get_str16_nolen(ByteIOContext *pb, int len, char *buf, int buf_size)
{
int c, lenz;
char *q;

q = buf;
lenz = len;
while (len & gt; 0) {
c = get_byte(pb);
if ((q - buf) & lt; buf_size-1)
*q++ = c;
len--;
}
// tag_recode(buf, lenz); //jacky 2006/10/18
}


static int asf_probe(AVProbeData *pd)
{
GUID g;
const unsigned char *p;
int i;

/* check file header */
if (pd- & gt; buf_size & lt; = 32)
return 0;
p = pd- & gt; buf;
g.v1 = p[0] | (p[1] & lt; & lt; 8) | (p[2] & lt; & lt; 16) | (p[3] & lt; & lt; 24);
p += 4;
g.v2 = p[0] | (p[1] & lt; & lt; 8);
p += 2;
g.v3 = p[0] | (p[1] & lt; & lt; 8);
p += 2;
for(i=0;i & lt; 8;i++)
g.v4[i] = *p++;

if (!memcmp( & g, & asf_header, sizeof(GUID)))
return AVPROBE_SCORE_MAX;
else
return 0;
}


static int asf_read_header(AVFormatContext *s/*, AVFormatParameters *ap*/)
{
ASFContext *asf = s- & gt; priv_data;
GUID g;
ByteIOContext *pb = & s- & gt; pb;
AVStream *st;
ASFStream *asf_st;
//int size, i;
int i;
long long gsize;

av_set_pts_info(s, 32, 1, 1000); /* 32 bit pts in ms */

get_guid(pb, & g); //w zmiennej g jest GUID ASF Header Object
if (memcmp( & g, & asf_header, sizeof(GUID)))
goto fail;
get_le64(pb); //przeskoczenie 8 bajtów (czyli zwi?kszenie pb- & gt; buf_ptr o 8)
get_le32(pb); //przeskoczenie 4 bajtów (czyli zwi?kszenie pb- & gt; buf_ptr o 4)
get_byte(pb); //przeskoczenie 1 bajta (czyli zwi?kszenie pb- & gt; buf_ptr o 1)
get_byte(pb); //przeskoczenie 1 bajta (czyli zwi?kszenie pb- & gt; buf_ptr o 1)
memset( & asf- & gt; asfid2avid, -1, sizeof(asf- & gt; asfid2avid));
for(;;) { //w tej p?tli zbieranie GUID'ów
get_guid(pb, & g); /*pobranie GUID'ów (pb- & gt; buf_ptr b?dzie ka?dorazowo powi?kszony o 16)
GUID File Properties Object
GUID Header Extension Object
GUID Extended Content Description Object
GUID Stream Properties Object
GUID Content Description Object
GUID Data Object*/
gsize = get_le64(pb); //gsize = size of GUID File Properties Object (pb- & gt; buf_ptr b?dzie powi?kszony o 8)
/*#ifdef DEBUG
debug_printf( " %08Lx: " , url_ftell(pb) - 24);
print_guid( & g);
debug_printf( " size=0x%Lx\n " , gsize);
#endif */
if (gsize & lt; 24)
goto fail;
if (!memcmp( & g, & file_header, sizeof(GUID))) { //gdy w zmiennej g jest GUID File Properties Object, to:
get_guid(pb, & asf- & gt; hdr.guid); //w zmiennej hdr.guid jest GUID File ID (pb- & gt; buf_ptr b?dzie powi?kszony o 16)
asf- & gt; hdr.file_size = get_le64(pb); //(pb- & gt; buf_ptr b?dzie powi?kszony o 8)
asf- & gt; hdr.create_time = get_le64(pb);
asf- & gt; hdr.packets_count = get_le64(pb);
asf- & gt; hdr.play_time = get_le64(pb);
asf- & gt; hdr.send_time = get_le64(pb);
asf- & gt; hdr.preroll = get_le32(pb); //(pb- & gt; buf_ptr b?dzie powi?kszony o 4)
asf- & gt; hdr.ignore = get_le32(pb);
asf- & gt; hdr.flags = get_le32(pb);
asf- & gt; hdr.min_pktsize = get_le32(pb);
asf- & gt; hdr.max_pktsize = get_le32(pb);
asf- & gt; hdr.max_bitrate = get_le32(pb);
asf- & gt; packet_size = asf- & gt; hdr.max_pktsize;
asf- & gt; nb_packets = asf- & gt; hdr.packets_count;
} else if (!memcmp( & g, & stream_header, sizeof(GUID))) { //w zmiennej g jest GUID Stream Properties Object
int type, type_specific_size;
long long pos1, pos2, time_offset;

pos1 = url_ftell(pb);
st = av_new_stream(s, 0);
if (!st)
goto fail;
asf_st = av_mallocz(sizeof(ASFStream));
if (!asf_st)
goto fail;
st- & gt; priv_data = asf_st;
st- & gt; start_time = asf- & gt; hdr.preroll / (10000000 / AV_TIME_BASE);
st- & gt; duration = (asf- & gt; hdr.send_time - asf- & gt; hdr.preroll) /
(10000000 / AV_TIME_BASE);
get_guid(pb, & g);
if (!memcmp( & g, & audio_stream, sizeof(GUID))) {
type = CODEC_TYPE_AUDIO; //gdy w zmiennej g jest GUID Audio Stream Type
} else if (!memcmp( & g, & video_stream, sizeof(GUID))) {
type = CODEC_TYPE_VIDEO; //gdy w zmiennej g jest GUID Video Stream Type
} else {
goto fail; //gdy GUID nierozpoznany jako jeden z dwóch powy?szych
}
get_guid(pb, & g); //w zmiennej g jest GUID Error Correction Type - ASF_Audio_Spread
time_offset = get_le64(pb);
type_specific_size = get_le32(pb);
get_le32(pb); //pomini?cie pola Error Correction Data Length, tylko zwi?kszenie wskaźnika pb- & gt; buf_ptr o 4
st- & gt; id = get_le16(pb) & 0x7f; /*extract stream number from flags */
// mapping of asf ID to AV stream ID;
asf- & gt; asfid2avid[st- & gt; id] = s- & gt; nb_streams - 1;

get_le32(pb); //pomini?cie pola Reserved, tylko zwi?kszenie wskaźnika pb- & gt; buf_ptr o 4
st- & gt; codec.codec_type = type;
/* 1 fps default (XXX: put 0 fps instead) */
//st- & gt; codec.frame_rate = 1;
//st- & gt; codec.frame_rate_base = 1;
if (type == CODEC_TYPE_AUDIO) {
get_wav_header(pb, & st- & gt; codec, type_specific_size); //st?d mo?na dowiedzieae si? w st- & gt; codec bitrate, fsample, nb_channels
st- & gt; need_parsing = 1;
/* We have to init the frame size at some point .... */
pos2 = url_ftell(pb);
if (gsize & gt; (pos2 + 8 - pos1 + 24)) {
asf_st- & gt; ds_span = get_byte(pb);
asf_st- & gt; ds_packet_size = get_le16(pb);
asf_st- & gt; ds_chunk_size = get_le16(pb);
asf_st- & gt; ds_data_size = get_le16(pb);
asf_st- & gt; ds_silence_data = get_byte(pb);
}
/*debug_printf( " Descrambling: ps:%d cs:%d ds:%d s:%d sd:%d\n " ,
asf_st- & gt; ds_packet_size, asf_st- & gt; ds_chunk_size,
asf_st- & gt; ds_data_size, asf_st- & gt; ds_span, asf_st- & gt; ds_silence_data); */
if (asf_st- & gt; ds_span & gt; 1) {
if (!asf_st- & gt; ds_chunk_size
|| (asf_st- & gt; ds_packet_size/asf_st- & gt; ds_chunk_size & lt; = 1))
asf_st- & gt; ds_span = 0; // disable descrambling
}
switch (st- & gt; codec.codec_id) {
case CODEC_ID_MP3:
st- & gt; codec.frame_size = MP3_FRAME_SIZE;
break;
case CODEC_ID_PCM_S16LE:
case CODEC_ID_PCM_S16BE:
case CODEC_ID_PCM_U16LE:
case CODEC_ID_PCM_U16BE:
case CODEC_ID_PCM_S8:
case CODEC_ID_PCM_U8:
case CODEC_ID_PCM_ALAW:
case CODEC_ID_PCM_MULAW:
st- & gt; codec.frame_size = 1;
break;
default:
/* This is probably wrong, but it prevents a crash later */
st- & gt; codec.frame_size = 1;
break;
}
//s- & gt; data = st- & gt; codec; //dopisa?em,by zwróciae dane potrzebne do dekodowania
}
#if 0
} else {
get_le32(pb);
get_le32(pb);
get_byte(pb);
size = get_le16(pb); /* size */
get_le32(pb); /* size */
st- & gt; codec.width = get_le32(pb);
st- & gt; codec.height = get_le32(pb);
/* not available for asf */
get_le16(pb); /* panes */
st- & gt; codec.bits_per_sample = get_le16(pb); /* depth */
tag1 = get_le32(pb);
url_fskip(pb, 20);
if (size & gt; 40) {
st- & gt; codec.extradata_size = size - 40;
st- & gt; codec.extradata = av_mallocz(st- & gt; codec.extradata_size);
adresy[indeksy] = st- & gt; codec.extradata;
indeksy++;
get_buffer(pb, st- & gt; codec.extradata, st- & gt; codec.extradata_size);
}

/* Extract palette from extradata if bpp & lt; = 8 */
/* This code assumes that extradata contains only palette */
/* This is true for all paletted codecs implemented in ffmpeg */
if (st- & gt; codec.extradata_size & & (st- & gt; codec.bits_per_sample & lt; = 8)) {
st- & gt; codec.palctrl = av_mallocz(sizeof(AVPaletteControl));
#ifdef WORDS_BIGENDIAN
for (i = 0; i FFMIN(st- & gt; codec.extradata_size, AVPALETTE_SIZE)/4; i++)
st- & gt; codec.palctrl- & gt; palette[i] = bswap_32(((uint32_t*)st- & gt; codec.extradata)[i]);
#else
memcpy(st- & gt; codec.palctrl- & gt; palette, st- & gt; codec.extradata,
FFMIN(st- & gt; codec.extradata_size, AVPALETTE_SIZE));
#endif
st- & gt; codec.palctrl- & gt; palette_changed = 1;
}

st- & gt; codec.codec_tag = tag1;
st- & gt; codec.codec_id = codec_get_id(codec_bmp_tags, tag1);
}
#endif
pos2 = url_ftell(pb);
url_fskip(pb, gsize - (pos2 - pos1 + 24));
} else if (!memcmp( & g, & data_header, sizeof(GUID))) { //w zmiennej g jest GUID Data Object
break;
} else if (!memcmp( & g, & comment_header, sizeof(GUID))) { //w zmiennej g jest GUID Content_Description_Object
int len1, len2, len3, len4, len5;

len1 = get_le16(pb);
len2 = get_le16(pb);
len3 = get_le16(pb);
len4 = get_le16(pb);
len5 = get_le16(pb);
url_fskip(pb, len1); // get_str16_nolen(pb, len1, s- & gt; title, sizeof(s- & gt; title));
url_fskip(pb, len2); // get_str16_nolen(pb, len2, s- & gt; author, sizeof(s- & gt; author));
url_fskip(pb, len3); // get_str16_nolen(pb, len3, s- & gt; copyright, sizeof(s- & gt; copyright));
url_fskip(pb, len4); // get_str16_nolen(pb, len4, s- & gt; comment, sizeof(s- & gt; comment));
url_fskip(pb, len5);
} else if (!memcmp( & g, & extended_content_header, sizeof(GUID))) { //w zmiennej g jest GUID Extended_Content_Description_Object - obiekt tekstowy opisuj?cy plik WMA
int desc_count, i;

desc_count = get_le16(pb); //pb- & gt; buf_ptr b?dzie powi?kszony o 2
for(i=0;i & lt; desc_count;i++)
{
int name_len,value_type,value_len,value_num = 0;
char *name, *value;

name_len = get_le16(pb);
name = (char *)av_mallocz(name_len);
get_str16_nolen(pb, name_len, name, name_len); //pozbieranie znaków w ilości name_len i wpisanie ich do tablicy name (s- & gt; buf_ptr powi?kszony o name_len)
value_type = get_le16(pb);
value_len = get_le16(pb);
if ((value_type == 0) || (value_type == 1)) // unicode or byte
{
value = (char *)av_mallocz(value_len);
get_str16_nolen(pb, value_len, value, value_len); //pozbieranie znaków w ilości value_len i wpisanie ich do tablicy value (s- & gt; buf_ptr powi?kszony o value_len)
//if (strcmp(name, " WM/AlbumTitle " )==0) { strcpy(s- & gt; album, value); }
//if (strcmp(name, " WM/Genre " )==0) { strcpy(s- & gt; genre, value); }
//if (strcmp(name, " WM/Year " )==0) s- & gt; year = atoi(value);
av_free(value);
}
//if ((value_type & gt; = 2) || (value_type & lt; = 5)) // boolean or DWORD or QWORD or WORD //niby źle (cannot play ASF (WMA) files, if the header contains year,album and tracknumber infos), na podstawie: http://lists.mplayerhq.hu/pipermail/ffmpeg-devel/2005-June/002761.html
if ((value_type & gt; = 2) & & (value_type & lt; = 5)) // boolean or DWORD or QWORD or WORD //to poprawione:

{
if (value_type==2) value_num = get_le32(pb);
if (value_type==3) value_num = get_le32(pb);
if (value_type==4) value_num = get_le64(pb);
if (value_type==5) value_num = get_le16(pb);
// if (strcmp(name, " WM/Track " )==0) s- & gt; track = value_num + 1;
// if (strcmp(name, " WM/TrackNumber " )==0) s- & gt; track = value_num;
}
av_free(name);
}

} else if (url_feof(pb)) {
goto fail;
} else { //gdy jesteśmy tutaj, to powy?ej nie znaleziono potrzebnego GUID'a lub w bie??cym buforze przechowuj?cym dane pliku WMA nie ma nast?pnego GUID-u po tym ostatnio znalezionym
url_fseek(pb, gsize - 24, SEEK_CUR); //i wtedy odpowiednio trzeba dalej szukaae w bie?acym buforze lub trzeba za?adowaae bufor nast?pnymi danymi z pliku WMA. Do odczytania w?aściwych danych nale?y wykorzystaae zmienn? gsize
}
}
get_guid(pb, & g); //GUID File ID
get_le64(pb);
get_byte(pb);
get_byte(pb);
if (url_feof(pb))
goto fail;
asf- & gt; data_offset = url_ftell(pb);
asf- & gt; packet_size_left = 0;

return 0;

fail:
for(i=0;i & lt; s- & gt; nb_streams;i++) {
AVStream *st = s- & gt; streams[i];
if (st) {
av_free(st- & gt; priv_data);
av_free(st- & gt; codec.extradata);
}
av_free(st);
}
return -1;
}


#define DO_2BITS(bits, var, defval) \
switch (bits & 3) \
{ \
case 3: var = get_le32(pb); rsize += 4; break; \
case 2: var = get_le16(pb); rsize += 2; break; \
case 1: var = get_byte(pb); rsize++; break; \
default: var = defval; break; \
}


static int asf_get_packet(AVFormatContext *s)
{
ASFContext *asf = s- & gt; priv_data;
ByteIOContext *pb = & s- & gt; pb;
unsigned int packet_length, padsize;
int rsize = 9;
int c;

//assert((url_ftell( & s- & gt; pb) - s- & gt; data_offset) % asf- & gt; packet_size == 0);

c = get_byte(pb);
/* if (c != 0x82) {
if (!url_feof(pb))
debug_printf( " ff asf bad header %x at:%lld\n " , c, url_ftell(pb));
} */
if ((c & 0x0f) == 2) { // always true for now
if (get_le16(pb) != 0) {
if (!url_feof(pb))
//debug_printf( " ff asf bad non zero\n " );
//return -EIO;
return -1; //jacky 2006/10/18
}
rsize+=2;
}else{
if (!url_feof(pb))
// debug_printf( " ff asf bad header %x at:%lld\n " , c, url_ftell(pb));
//return -EIO;
return -1;
}

asf- & gt; packet_flags = get_byte(pb);
asf- & gt; packet_property = get_byte(pb);

DO_2BITS(asf- & gt; packet_flags & gt; & gt; 5, packet_length, asf- & gt; packet_size);
DO_2BITS(asf- & gt; packet_flags & gt; & gt; 1, padsize, 0); // sequence ignored
DO_2BITS(asf- & gt; packet_flags & gt; & gt; 3, padsize, 0); // padding length

asf- & gt; packet_timestamp = get_le32(pb);
get_le16(pb); /* duration */
// rsize has at least 11 bytes which have to be present

if (asf- & gt; packet_flags & 0x01) {
asf- & gt; packet_segsizetype = get_byte(pb); rsize++;
asf- & gt; packet_segments = asf- & gt; packet_segsizetype & 0x3f;
} else {
asf- & gt; packet_segments = 1;
asf- & gt; packet_segsizetype = 0x80;
}
asf- & gt; packet_size_left = packet_length - padsize - rsize;
if (packet_length & lt; asf- & gt; hdr.min_pktsize)
padsize += asf- & gt; hdr.min_pktsize - packet_length;
asf- & gt; packet_padsize = padsize;
/*#ifdef DEBUG
debug_printf( " packet: size=%d padsize=%d left=%d\n " , asf- & gt; packet_size, asf- & gt; packet_padsize, asf- & gt; packet_size_left);
#endif */
return 0;
}


static int asf_read_packet(AVFormatContext *s, AVPacket *pkt)
{
ASFContext *asf = s- & gt; priv_data;
ASFStream *asf_st = 0;
ByteIOContext *pb = & s- & gt; pb;
//static int pc = 0;
for (;;) {
int rsize = 0;
if (asf- & gt; packet_size_left & lt; FRAME_HEADER_SIZE
|| asf- & gt; packet_segments & lt; 1) {
//asf- & gt; packet_size_left = asf- & gt; packet_padsize) {
int ret = asf- & gt; packet_size_left + asf- & gt; packet_padsize;
//debug_printf( " PacketLeftSize:%d Pad:%d Pos:%Ld\n " , asf- & gt; packet_size_left, asf- & gt; packet_padsize, url_ftell(pb));
/* fail safe */
url_fskip(pb, ret);
asf- & gt; packet_pos= url_ftell( & s- & gt; pb);
ret = asf_get_packet(s);
//debug_printf( " READ ASF PACKET %d r:%d c:%d\n " , ret, asf- & gt; packet_size_left, pc++);
if (ret & lt; 0 || url_feof(pb))
//return -EIO;
return -1; //jacky 2006/10/18
asf- & gt; packet_time_start = 0;
continue;
}
if (asf- & gt; packet_time_start == 0) {
/* read frame header */
int num = get_byte(pb);
asf- & gt; packet_segments--;
rsize++;
asf- & gt; packet_key_frame = (num & 0x80) & gt; & gt; 7;
asf- & gt; stream_index = asf- & gt; asfid2avid[num & 0x7f];
// sequence should be ignored!
DO_2BITS(asf- & gt; packet_property & gt; & gt; 4, asf- & gt; packet_seq, 0);
DO_2BITS(asf- & gt; packet_property & gt; & gt; 2, asf- & gt; packet_frag_offset, 0);
DO_2BITS(asf- & gt; packet_property, asf- & gt; packet_replic_size, 0);
//debug_printf( " key:%d stream:%d seq:%d offset:%d replic_size:%d\n " , asf- & gt; packet_key_frame, asf- & gt; stream_index, asf- & gt; packet_seq, asf- & gt; packet_frag_offset, asf- & gt; packet_replic_size);
if (asf- & gt; packet_replic_size & gt; 1) {
//assert(asf- & gt; packet_replic_size & gt; = 8);
// it should be always at least 8 bytes - FIXME validate
asf- & gt; packet_obj_size = get_le32(pb);
asf- & gt; packet_frag_timestamp = get_le32(pb); // timestamp
if (asf- & gt; packet_replic_size & gt; 8)
url_fskip(pb, asf- & gt; packet_replic_size - 8);
rsize += asf- & gt; packet_replic_size; // FIXME - check validity
} else if (asf- & gt; packet_replic_size == 1){
// multipacket - frag_offset is begining timestamp
asf- & gt; packet_time_start = asf- & gt; packet_frag_offset;
asf- & gt; packet_frag_offset = 0;
asf- & gt; packet_frag_timestamp = asf- & gt; packet_timestamp;

asf- & gt; packet_time_delta = get_byte(pb);
rsize++;
}else{
//assert(asf- & gt; packet_replic_size==0);
}
if (asf- & gt; packet_flags & 0x01) {
DO_2BITS(asf- & gt; packet_segsizetype & gt; & gt; 6, asf- & gt; packet_frag_size, 0); // 0 is illegal
#undef DO_2BITS
//debug_printf( " Fragsize %d\n " , asf- & gt; packet_frag_size);
} else {
asf- & gt; packet_frag_size = asf- & gt; packet_size_left - rsize;
//debug_printf( " Using rest %d %d %d\n " , asf- & gt; packet_frag_size, asf- & gt; packet_size_left, rsize);
}
if (asf- & gt; packet_replic_size == 1) {
asf- & gt; packet_multi_size = asf- & gt; packet_frag_size;
if (asf- & gt; packet_multi_size & gt; asf- & gt; packet_size_left) {
asf- & gt; packet_segments = 0;
continue;
}
}
asf- & gt; packet_size_left -= rsize;
//debug_printf( " ___objsize____ %d %d rs:%d\n " , asf- & gt; packet_obj_size, asf- & gt; packet_frag_offset, rsize);

if (asf- & gt; stream_index & lt; 0) {
asf- & gt; packet_time_start = 0;
/* unhandled packet (should not happen) */
url_fskip(pb, asf- & gt; packet_frag_size);
asf- & gt; packet_size_left -= asf- & gt; packet_frag_size;
//debug_printf( " ff asf skip %d %d\n " , asf- & gt; packet_frag_size, num & 0x7f);
continue;
}
asf- & gt; asf_st = s- & gt; streams[asf- & gt; stream_index]- & gt; priv_data;
}
asf_st = asf- & gt; asf_st;

if ((asf- & gt; packet_frag_offset != asf_st- & gt; frag_offset
|| (asf- & gt; packet_frag_offset
& & asf- & gt; packet_seq != asf_st- & gt; seq)) // seq should be ignored
) {
/* cannot continue current packet: free it */
// FIXME better check if packet was already allocated
/*debug_printf( " ff asf parser skips: %d - %d o:%d - %d %d %d fl:%d\n " ,
asf_st- & gt; pkt.size,
asf- & gt; packet_obj_size,
asf- & gt; packet_frag_offset, asf_st- & gt; frag_offset,
asf- & gt; packet_seq, asf_st- & gt; seq, asf- & gt; packet_frag_size); */
if (asf_st- & gt; pkt.size)
av_free_packet( & asf_st- & gt; pkt);
asf_st- & gt; frag_offset = 0;
if (asf- & gt; packet_frag_offset != 0) {
url_fskip(pb, asf- & gt; packet_frag_size);
//debug_printf( " ff asf parser skiping %db\n " , asf- & gt; packet_frag_size);
asf- & gt; packet_size_left -= asf- & gt; packet_frag_size;
continue;
}
}
if (asf- & gt; packet_replic_size == 1) {
// frag_offset is here used as the begining timestamp
asf- & gt; packet_frag_timestamp = asf- & gt; packet_time_start;
asf- & gt; packet_time_start += asf- & gt; packet_time_delta;
asf- & gt; packet_obj_size = asf- & gt; packet_frag_size = get_byte(pb);
asf- & gt; packet_size_left--;
asf- & gt; packet_multi_size--;
if (asf- & gt; packet_multi_size & lt; asf- & gt; packet_obj_size)
{
asf- & gt; packet_time_start = 0;
url_fskip(pb, asf- & gt; packet_multi_size);
asf- & gt; packet_size_left -= asf- & gt; packet_multi_size;
continue;
}
asf- & gt; packet_multi_size -= asf- & gt; packet_obj_size;
//debug_printf( " COMPRESS size %d %d %d ms:%d\n " , asf- & gt; packet_obj_size, asf- & gt; packet_frag_timestamp, asf- & gt; packet_size_left, asf- & gt; packet_multi_size);
}
if (asf_st- & gt; frag_offset == 0) {
/* new packet */
av_new_packet( & asf_st- & gt; pkt, asf- & gt; packet_obj_size);
asf_st- & gt; seq = asf- & gt; packet_seq;
asf_st- & gt; pkt.pts = asf- & gt; packet_frag_timestamp - asf- & gt; hdr.preroll;
asf_st- & gt; pkt.stream_index = asf- & gt; stream_index;
asf_st- & gt; packet_pos= asf- & gt; packet_pos;
/*debug_printf( " new packet: stream:%d key:%d packet_key:%d audio:%d size:%d\n " ,
asf- & gt; stream_index, asf- & gt; packet_key_frame, asf_st- & gt; pkt.flags & PKT_FLAG_KEY,
s- & gt; streams[asf- & gt; stream_index]- & gt; codec.codec_type == CODEC_TYPE_AUDIO, asf- & gt; packet_obj_size); */
if (s- & gt; streams[asf- & gt; stream_index]- & gt; codec.codec_type == CODEC_TYPE_AUDIO)
asf- & gt; packet_key_frame = 1;
if (asf- & gt; packet_key_frame)
asf_st- & gt; pkt.flags |= PKT_FLAG_KEY;
}

/* read data */
/*debug_printf( " READ PACKET s:%d os:%d o:%d,%d l:%d DATA:%p\n " ,
asf- & gt; packet_size, asf_st- & gt; pkt.size, asf- & gt; packet_frag_offset,
asf_st- & gt; frag_offset, asf- & gt; packet_frag_size, asf_st- & gt; pkt.data); */
asf- & gt; packet_size_left -= asf- & gt; packet_frag_size;
if (asf- & gt; packet_size_left & lt; 0)
continue;
get_buffer(pb, asf_st- & gt; pkt.data + asf- & gt; packet_frag_offset,
asf- & gt; packet_frag_size);
asf_st- & gt; frag_offset += asf- & gt; packet_frag_size;
/* test if whole packet is read */
if (asf_st- & gt; frag_offset == asf_st- & gt; pkt.size) {
/* return packet */
if (asf_st- & gt; ds_span & gt; 1) {
/* packet descrambling */
char* newdata = av_malloc(asf_st- & gt; pkt.size);
if (newdata) {
int offset = 0;
while (offset & lt; asf_st- & gt; pkt.size) {
int off = offset / asf_st- & gt; ds_chunk_size;
int row = off / asf_st- & gt; ds_span;
int col = off % asf_st- & gt; ds_span;
int idx = row + col * asf_st- & gt; ds_packet_size / asf_st- & gt; ds_chunk_size;
//debug_printf( " off:%d row:%d col:%d idx:%d\n " , off, row, col, idx);
memcpy(newdata + offset,
asf_st- & gt; pkt.data + idx * asf_st- & gt; ds_chunk_size,
asf_st- & gt; ds_chunk_size);
offset += asf_st- & gt; ds_chunk_size;
}
av_free(asf_st- & gt; pkt.data);
asf_st- & gt; pkt.data = newdata;
}
}
asf_st- & gt; frag_offset = 0;
memcpy(pkt, & asf_st- & gt; pkt, sizeof(AVPacket));
//debug_printf( " packet %d %d\n " , asf_st- & gt; pkt.size, asf- & gt; packet_frag_size);
asf_st- & gt; pkt.size = 0;
asf_st- & gt; pkt.data = 0;
break; // packet completed
}
}
return 0;
}

static int asf_read_close(AVFormatContext *s)
{
int i;

for(i=0;i & lt; s- & gt; nb_streams;i++) {
AVStream *st = s- & gt; streams[i];
av_free(st- & gt; priv_data);
av_free(st- & gt; codec.extradata);
//av_free(st- & gt; codec.palctrl);
}
return 0;
}



void asf_reset_header(AVFormatContext *s)
{
ASFContext *asf = s- & gt; priv_data;
ASFStream *asf_st;
int i;

//asf- & gt; packet_nb_frames = 0;
//asf- & gt; packet_timestamp_start = -1;
//asf- & gt; packet_timestamp_end = -1;
asf- & gt; packet_size_left = 0;
asf- & gt; packet_segments = 0;
asf- & gt; packet_flags = 0;
asf- & gt; packet_property = 0;
asf- & gt; packet_timestamp = 0;
asf- & gt; packet_segsizetype = 0;
asf- & gt; packet_segments = 0;
asf- & gt; packet_seq = 0;
asf- & gt; packet_replic_size = 0;
asf- & gt; packet_key_frame = 0;
asf- & gt; packet_padsize = 0;
asf- & gt; packet_frag_offset = 0;
asf- & gt; packet_frag_size = 0;
asf- & gt; packet_frag_timestamp = 0;
asf- & gt; packet_multi_size = 0;
asf- & gt; packet_obj_size = 0;
asf- & gt; packet_time_delta = 0;
asf- & gt; packet_time_start = 0;

for(i=0; i & lt; s- & gt; nb_streams; i++){
asf_st= s- & gt; streams[i]- & gt; priv_data;
av_free_packet( & asf_st- & gt; pkt);
asf_st- & gt; frag_offset=0;
asf_st- & gt; seq=0;
}
asf- & gt; asf_st= NULL;
}



static long long asf_read_pts(AVFormatContext *s, long long *ppos, int stream_index)
{
ASFContext *asf = s- & gt; priv_data;
AVPacket pkt1, *pkt = & pkt1;
ASFStream *asf_st;
long long pts;
long long pos= *ppos;
int i;
//int64_t start_pos[s- & gt; nb_streams];
long long start_pos[1]; //jacky 2006/10/18

for(i=0; i & lt; s- & gt; nb_streams; i++){
start_pos[i]= pos;
}

//debug_printf( " asf_read_pts\n " );
url_fseek( & s- & gt; pb, pos*asf- & gt; packet_size + s- & gt; data_offset, SEEK_SET);
asf_reset_header(s);
for(;;){
if (av_read_frame(s, pkt) & lt; 0){
//debug_printf( " seek failed\n " );
return AV_NOPTS_VALUE;
}
pts= pkt- & gt; pts;

av_free_packet(pkt);
if(pkt- & gt; flags & PKT_FLAG_KEY){
i= pkt- & gt; stream_index;

asf_st= s- & gt; streams[i]- & gt; priv_data;

//assert((asf_st- & gt; packet_pos - s- & gt; data_offset) % asf- & gt; packet_size == 0);
pos= (asf_st- & gt; packet_pos - s- & gt; data_offset) / asf- & gt; packet_size;

av_add_index_entry(s- & gt; streams[i], pos, pts, pos - start_pos[i] + 1, AVINDEX_KEYFRAME);
start_pos[i]= pos + 1;

if(pkt- & gt; stream_index == stream_index)
break;
}
}

*ppos= pos;
//debug_printf( " found keyframe at %Ld stream %d stamp:%Ld\n " , *ppos, stream_index, pts);

return pts;
}



static int asf_read_seek(AVFormatContext *s, int stream_index, long long pts)
{
ASFContext *asf = s- & gt; priv_data;
AVStream *st;
long long pos;
long long pos_min, pos_max, pts_min, pts_max, cur_pts, pos_limit;
int no_change;

if (stream_index == -1)
stream_index= av_find_default_stream_index(s);

if (asf- & gt; packet_size & lt; = 0)
return -1;

pts_max = pts_min = AV_NOPTS_VALUE;
pos_max= pos_limit= -1; // gcc thinks its uninitalized

st= s- & gt; streams[stream_index];
if(st- & gt; index_entries){
AVIndexEntry *e;
int index;

index= av_index_search_timestamp(st, pts);
e= & st- & gt; index_entries[index];
if(e- & gt; timestamp & lt; = pts){
pos_min= e- & gt; pos;
pts_min= e- & gt; timestamp;
/*#ifdef DEBUG_SEEK
debug_printf( " unsing cached pos_min=0x%llx dts_min=%0.3f\n " ,
pos_min,pts_min / 90000.0);
#endif */
}else{
//assert(index==0);
}
index++;
if(index & lt; st- & gt; nb_index_entries){
e= & st- & gt; index_entries[index];
//assert(e- & gt; timestamp & gt; = pts);
pos_max= e- & gt; pos;
pts_max= e- & gt; timestamp;
pos_limit= pos_max - e- & gt; min_distance;
/*#ifdef DEBUG_SEEK
debug_printf( " unsing cached pos_max=0x%llx dts_max=%0.3f\n " ,
pos_max,pts_max / 90000.0);
#endif */
}
}

if(pts_min == AV_NOPTS_VALUE){
pos_min = 0;
pts_min = asf_read_pts(s, & pos_min, stream_index);
if (pts_min == AV_NOPTS_VALUE) return -1;
}
if(pts_max == AV_NOPTS_VALUE){
pos_max = (url_filesize(url_fileno( & s- & gt; pb)) - 1 - s- & gt; data_offset) / asf- & gt; packet_size; //FIXME wrong
pts_max = s- & gt; duration; //FIXME wrong
pos_limit= pos_max;
}

no_change = 0;
while (pos_min & lt; pos_limit) {
long long start_pos;
//assert(pos_limit = pos_max);

if(no_change == 0){
long long approximate_keyframe_distance= pos_max - pos_limit;
// interpolate position (better than dichotomy)
pos = (long long)((double)(pos_max - pos_min) *
(double)(pts - pts_min) /
(double)(pts_max - pts_min)) + pos_min - approximate_keyframe_distance;
}else if(no_change == 1){
// bisection, if interpolation failed to change min or max pos last time
pos = (pos_min + pos_limit) & gt; & gt; 1;
}else{
// linear search if bisection failed, can only happen if there are very few or no keyframes between min/max
pos=pos_min;
}
if(pos & lt; = pos_min)
pos = pos_min + 1;
else if(pos & gt; pos_limit)
pos= pos_limit;
start_pos = pos;

// read the next timestamp
cur_pts = asf_read_pts(s, & pos, stream_index);
if(pos == pos_max)
no_change++;
else
no_change=0;

/*#ifdef DEBUG_SEEK
debug_printf( " %Ld %Ld %Ld / %Ld %Ld %Ld target:%Ld limit:%Ld start:%Ld\n " , pos_min, pos, pos_max, pts_min, cur_pts, pts_max, pts, pos_limit, start_pos);
#endif */
//assert (cur_pts != AV_NOPTS_VALUE);
if (pts & lt; cur_pts) {
pos_limit = start_pos - 1;
pos_max = pos;
pts_max = cur_pts;
} else {
pos_min = pos;
pts_min = cur_pts;
/* check if we are lucky */
if (pts == cur_pts)
break;
}
}
pos = pos_min;
url_fseek( & s- & gt; pb, pos*asf- & gt; packet_size + s- & gt; data_offset, SEEK_SET);
asf_reset_header(s);
return 0;
}

/*static*/const AVInputFormat asf_iformat = {
" asf " ,
" asf format " ,
sizeof(ASFContext),
asf_probe,
asf_read_header,
asf_read_packet,
asf_read_close,
asf_read_seek,
};


int asf_init(void)
{
av_register_input_format((AVInputFormat*) & asf_iformat);
return 0;
}


wma_dec.ZIP > asf.h

#ifndef ASF_H
#define ASF_H

/*typedef struct AVPacket {
int64_t pts;
int64_t dts;
uint8_t *data;
int size;
int stream_index;
int flags;
int duration;
void (*destruct)(struct AVPacket *);
void *priv;
int64_t pos;
int64_t convergence_duration;
} AVPacket;*/

typedef struct {
unsigned int v1;
unsigned short v2;
unsigned short v3;
unsigned char v4[8];
} GUID;



typedef struct {
// int num;
unsigned char seq;
/* use for reading */
AVPacket pkt;
int frag_offset;
// int timestamp;
// long long duration;
int ds_span; /* descrambling */
int ds_packet_size;
int ds_chunk_size;
int ds_data_size;
int ds_silence_data;

long long packet_pos;
// unsigned short stream_language_index;
} ASFStream;


/* typedef struct AVRational{
int num;
int den;
} AVRational;*/


// typedef unsigned char ff_asf_guid[16];

typedef struct {
GUID guid; // generated by client computer
unsigned int file_size; // in bytes
// invalid if broadcasting
unsigned long long create_time; // time of creation, in 100-nanosecond units since 1.1.1601
// invalid if broadcasting
unsigned int packets_count; // how many packets are there in the file
// invalid if broadcasting
unsigned long long play_time; // play time, in 100-nanosecond units
// invalid if broadcasting
unsigned long long send_time; // time to send file, in 100-nanosecond units
// invalid if broadcasting (could be ignored)
unsigned int preroll; // timestamp of the first packet, in milliseconds
// if nonzero - substract from time
unsigned int ignore; // preroll is 64bit - but let's just ignore it
unsigned int flags; // 0x01 - broadcast
// 0x02 - seekable
// rest is reserved should be 0
unsigned int min_pktsize; // size of a data packet
// invalid if broadcasting
unsigned int max_pktsize; // shall be the same as for min_pktsize
// invalid if broadcasting
unsigned int max_bitrate; // bandwith of stream in bps
// should be the sum of bitrates of the
// individual media streams
} ASFMainHeader;

typedef struct {
int packet_size;
long long nb_packets;
int asfid2avid[2/*128*/];
// ASFStream streams[2/*128*/];
// uint32_t stream_bitrates[128];
// AVRational dar[128];
// char stream_languages[128][6];
/* non streamed additonnal info */
/* packet filling */
int packet_size_left;
/* only for reading */
unsigned int data_offset;
// unsigned int data_object_offset;
// unsigned int data_object_size;
// int index_read;

ASFMainHeader hdr;

int packet_flags;
int packet_property;
int packet_timestamp;
int packet_segsizetype;
int packet_segments;
int packet_seq;
int packet_replic_size;
int packet_key_frame;
int packet_padsize;
unsigned int packet_frag_offset;
unsigned int packet_frag_size;
unsigned int packet_frag_timestamp;
int packet_multi_size;
int packet_obj_size;
int packet_time_delta;
int packet_time_start;
unsigned int packet_pos;
int stream_index;
ASFStream* asf_st;
} ASFContext;




void asf_reset_header(AVFormatContext *s);
int asf_init(void);

#endif


wma_dec.ZIP > stm32f4xx.h

/**
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F4xx devices.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The device used in the target application
* - To use or not the peripheral’s drivers in application code(i.e.
* code will be based on direct access to peripheral’s registers
* rather than drivers API), this option is controlled by
* " #define USE_STDPERIPH_DRIVER "
* - To change few application-specific parameters such as the HSE
* crystal frequency
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
* - Macros to access peripheral’s registers hardware
*
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* & lt; h2 & gt; & lt; center & gt; & copy; COPYRIGHT 2011 STMicroelectronics & lt; /center & gt; & lt; /h2 & gt;
******************************************************************************
*/

/** @addtogroup CMSIS
* @{
*/

/** @addtogroup stm32f4xx
* @{
*/

#ifndef __STM32F4xx_H
#define __STM32F4xx_H

#ifdef __cplusplus
extern " C " {
#endif /* __cplusplus */

/** @addtogroup Library_configuration_section
* @{
*/

/* Uncomment the line below according to the target STM32 device used in your
application
*/

#if !defined (STM32F4XX)
#define STM32F4XX
#endif

/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
*/

#if !defined (STM32F4XX)
#error " Please select first the target STM32F4XX device used in your application (in stm32f4xx.h file) "
#endif

#if !defined (USE_STDPERIPH_DRIVER)
/**
* @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
/*#define USE_STDPERIPH_DRIVER*/
#endif /* USE_STDPERIPH_DRIVER */

/**
* @brief In the following line adjust the value of External High Speed oscillator (HSE)
used in your application

Tip: To avoid modifying this file each time you need to use different HSE, you
can define the HSE value in your toolchain compiler preprocessor.
*/

#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)25000000) /*! & lt; Value of the External oscillator in Hz */
#endif /* HSE_VALUE */

/**
* @brief In the following line adjust the External High Speed oscillator (HSE) Startup
Timeout value
*/
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*! & lt; Time out for HSE start up */
#endif /* HSE_STARTUP_TIMEOUT */

#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*! & lt; Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */

/**
* @brief STM32F4XX Standard Peripherals Library version number V1.0.0
*/
#define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*! & lt; [31:24] main version */
#define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x00) /*! & lt; [23:16] sub1 version */
#define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /*! & lt; [15:8] sub2 version */
#define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /*! & lt; [7:0] release candidate */
#define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN & lt; & lt; 24)\
|(__STM32F4XX_STDPERIPH_VERSION_SUB1 & lt; & lt; 16)\
|(__STM32F4XX_STDPERIPH_VERSION_SUB2 & lt; & lt; 8)\
|(__STM32F4XX_STDPERIPH_VERSION_RC))

/**
* @}
*/

/** @addtogroup Configuration_section_for_CMSIS
* @{
*/

/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
#define __CM4_REV 0x0001 /*! & lt; Core revision r0p1 */
#define __MPU_PRESENT 1 /*! & lt; STM32F4XX provides an MPU */
#define __NVIC_PRIO_BITS 4 /*! & lt; STM32F4XX uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*! & lt; Set to 1 if different SysTick Config is used */

#if !defined (__FPU_PRESENT)
#define __FPU_PRESENT 1 /*! & lt; FPU present */
#endif /* __FPU_PRESENT */



/**
* @brief STM32F4XX Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum IRQn
{
/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
NonMaskableInt_IRQn = -14, /*! & lt; 2 Non Maskable Interrupt */
MemoryManagement_IRQn = -12, /*! & lt; 4 Cortex-M4 Memory Management Interrupt */
BusFault_IRQn = -11, /*! & lt; 5 Cortex-M4 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*! & lt; 6 Cortex-M4 Usage Fault Interrupt */
SVCall_IRQn = -5, /*! & lt; 11 Cortex-M4 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*! & lt; 12 Cortex-M4 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*! & lt; 14 Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /*! & lt; 15 Cortex-M4 System Tick Interrupt */
/****** STM32 specific Interrupt Numbers **********************************************************************/
WWDG_IRQn = 0, /*! & lt; Window WatchDog Interrupt */
PVD_IRQn = 1, /*! & lt; PVD through EXTI Line detection Interrupt */
TAMP_STAMP_IRQn = 2, /*! & lt; Tamper and TimeStamp interrupts through the EXTI line */
RTC_WKUP_IRQn = 3, /*! & lt; RTC Wakeup interrupt through the EXTI line */
FLASH_IRQn = 4, /*! & lt; FLASH global Interrupt */
RCC_IRQn = 5, /*! & lt; RCC global Interrupt */
EXTI0_IRQn = 6, /*! & lt; EXTI Line0 Interrupt */
EXTI1_IRQn = 7, /*! & lt; EXTI Line1 Interrupt */
EXTI2_IRQn = 8, /*! & lt; EXTI Line2 Interrupt */
EXTI3_IRQn = 9, /*! & lt; EXTI Line3 Interrupt */
EXTI4_IRQn = 10, /*! & lt; EXTI Line4 Interrupt */
DMA1_Stream0_IRQn = 11, /*! & lt; DMA1 Stream 0 global Interrupt */
DMA1_Stream1_IRQn = 12, /*! & lt; DMA1 Stream 1 global Interrupt */
DMA1_Stream2_IRQn = 13, /*! & lt; DMA1 Stream 2 global Interrupt */
DMA1_Stream3_IRQn = 14, /*! & lt; DMA1 Stream 3 global Interrupt */
DMA1_Stream4_IRQn = 15, /*! & lt; DMA1 Stream 4 global Interrupt */
DMA1_Stream5_IRQn = 16, /*! & lt; DMA1 Stream 5 global Interrupt */
DMA1_Stream6_IRQn = 17, /*! & lt; DMA1 Stream 6 global Interrupt */
ADC_IRQn = 18, /*! & lt; ADC1, ADC2 and ADC3 global Interrupts */
CAN1_TX_IRQn = 19, /*! & lt; CAN1 TX Interrupt */
CAN1_RX0_IRQn = 20, /*! & lt; CAN1 RX0 Interrupt */
CAN1_RX1_IRQn = 21, /*! & lt; CAN1 RX1 Interrupt */
CAN1_SCE_IRQn = 22, /*! & lt; CAN1 SCE Interrupt */
EXTI9_5_IRQn = 23, /*! & lt; External Line[9:5] Interrupts */
TIM1_BRK_TIM9_IRQn = 24, /*! & lt; TIM1 Break interrupt and TIM9 global interrupt */
TIM1_UP_TIM10_IRQn = 25, /*! & lt; TIM1 Update Interrupt and TIM10 global interrupt */
TIM1_TRG_COM_TIM11_IRQn = 26, /*! & lt; TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
TIM1_CC_IRQn = 27, /*! & lt; TIM1 Capture Compare Interrupt */
TIM2_IRQn = 28, /*! & lt; TIM2 global Interrupt */
TIM3_IRQn = 29, /*! & lt; TIM3 global Interrupt */
TIM4_IRQn = 30, /*! & lt; TIM4 global Interrupt */
I2C1_EV_IRQn = 31, /*! & lt; I2C1 Event Interrupt */
I2C1_ER_IRQn = 32, /*! & lt; I2C1 Error Interrupt */
I2C2_EV_IRQn = 33, /*! & lt; I2C2 Event Interrupt */
I2C2_ER_IRQn = 34, /*! & lt; I2C2 Error Interrupt */
SPI1_IRQn = 35, /*! & lt; SPI1 global Interrupt */
SPI2_IRQn = 36, /*! & lt; SPI2 global Interrupt */
USART1_IRQn = 37, /*! & lt; USART1 global Interrupt */
USART2_IRQn = 38, /*! & lt; USART2 global Interrupt */
USART3_IRQn = 39, /*! & lt; USART3 global Interrupt */
EXTI15_10_IRQn = 40, /*! & lt; External Line[15:10] Interrupts */
RTC_Alarm_IRQn = 41, /*! & lt; RTC Alarm (A and B) through EXTI Line Interrupt */
OTG_FS_WKUP_IRQn = 42, /*! & lt; USB OTG FS Wakeup through EXTI line interrupt */
TIM8_BRK_TIM12_IRQn = 43, /*! & lt; TIM8 Break Interrupt and TIM12 global interrupt */
TIM8_UP_TIM13_IRQn = 44, /*! & lt; TIM8 Update Interrupt and TIM13 global interrupt */
TIM8_TRG_COM_TIM14_IRQn = 45, /*! & lt; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
TIM8_CC_IRQn = 46, /*! & lt; TIM8 Capture Compare Interrupt */
DMA1_Stream7_IRQn = 47, /*! & lt; DMA1 Stream7 Interrupt */
FSMC_IRQn = 48, /*! & lt; FSMC global Interrupt */
SDIO_IRQn = 49, /*! & lt; SDIO global Interrupt */
TIM5_IRQn = 50, /*! & lt; TIM5 global Interrupt */
SPI3_IRQn = 51, /*! & lt; SPI3 global Interrupt */
UART4_IRQn = 52, /*! & lt; UART4 global Interrupt */
UART5_IRQn = 53, /*! & lt; UART5 global Interrupt */
TIM6_DAC_IRQn = 54, /*! & lt; TIM6 global and DAC1 & 2 underrun error interrupts */
TIM7_IRQn = 55, /*! & lt; TIM7 global interrupt */
DMA2_Stream0_IRQn = 56, /*! & lt; DMA2 Stream 0 global Interrupt */
DMA2_Stream1_IRQn = 57, /*! & lt; DMA2 Stream 1 global Interrupt */
DMA2_Stream2_IRQn = 58, /*! & lt; DMA2 Stream 2 global Interrupt */
DMA2_Stream3_IRQn = 59, /*! & lt; DMA2 Stream 3 global Interrupt */
DMA2_Stream4_IRQn = 60, /*! & lt; DMA2 Stream 4 global Interrupt */
ETH_IRQn = 61, /*! & lt; Ethernet global Interrupt */
ETH_WKUP_IRQn = 62, /*! & lt; Ethernet Wakeup through EXTI line Interrupt */
CAN2_TX_IRQn = 63, /*! & lt; CAN2 TX Interrupt */
CAN2_RX0_IRQn = 64, /*! & lt; CAN2 RX0 Interrupt */
CAN2_RX1_IRQn = 65, /*! & lt; CAN2 RX1 Interrupt */
CAN2_SCE_IRQn = 66, /*! & lt; CAN2 SCE Interrupt */
OTG_FS_IRQn = 67, /*! & lt; USB OTG FS global Interrupt */
DMA2_Stream5_IRQn = 68, /*! & lt; DMA2 Stream 5 global interrupt */
DMA2_Stream6_IRQn = 69, /*! & lt; DMA2 Stream 6 global interrupt */
DMA2_Stream7_IRQn = 70, /*! & lt; DMA2 Stream 7 global interrupt */
USART6_IRQn = 71, /*! & lt; USART6 global interrupt */
I2C3_EV_IRQn = 72, /*! & lt; I2C3 event interrupt */
I2C3_ER_IRQn = 73, /*! & lt; I2C3 error interrupt */
OTG_HS_EP1_OUT_IRQn = 74, /*! & lt; USB OTG HS End Point 1 Out global interrupt */
OTG_HS_EP1_IN_IRQn = 75, /*! & lt; USB OTG HS End Point 1 In global interrupt */
OTG_HS_WKUP_IRQn = 76, /*! & lt; USB OTG HS Wakeup through EXTI interrupt */
OTG_HS_IRQn = 77, /*! & lt; USB OTG HS global interrupt */
DCMI_IRQn = 78, /*! & lt; DCMI global interrupt */
CRYP_IRQn = 79, /*! & lt; CRYP crypto global interrupt */
HASH_RNG_IRQn = 80, /*! & lt; Hash and Rng global interrupt */
FPU_IRQn = 81 /*! & lt; FPU global interrupt */
} IRQn_Type;

/**
* @}
*/

#include " core_cm4.h " /* Cortex-M4 processor and core peripherals */
#include " system_stm32f4xx.h "
#include & lt; stdint.h & gt;

/** @addtogroup Exported_types
* @{
*/
/*! & lt; STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
typedef int32_t s32;
typedef int16_t s16;
typedef int8_t s8;

typedef const int32_t sc32; /*! & lt; Read Only */
typedef const int16_t sc16; /*! & lt; Read Only */
typedef const int8_t sc8; /*! & lt; Read Only */

typedef __IO int32_t vs32;
typedef __IO int16_t vs16;
typedef __IO int8_t vs8;

typedef __I int32_t vsc32; /*! & lt; Read Only */
typedef __I int16_t vsc16; /*! & lt; Read Only */
typedef __I int8_t vsc8; /*! & lt; Read Only */

typedef uint32_t u32;
typedef uint16_t u16;
typedef uint8_t u8;

typedef const uint32_t uc32; /*! & lt; Read Only */
typedef const uint16_t uc16; /*! & lt; Read Only */
typedef const uint8_t uc8; /*! & lt; Read Only */

typedef __IO uint32_t vu32;
typedef __IO uint16_t vu16;
typedef __IO uint8_t vu8;

typedef __I uint32_t vuc32; /*! & lt; Read Only */
typedef __I uint16_t vuc16; /*! & lt; Read Only */
typedef __I uint8_t vuc8; /*! & lt; Read Only */

typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;

typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))

typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;

/**
* @}
*/

/** @addtogroup Peripheral_registers_structures
* @{
*/

/**
* @brief Analog to Digital Converter
*/

typedef struct
{
__IO uint32_t SR; /*! & lt; ADC status register, Address offset: 0x00 */
__IO uint32_t CR1; /*! & lt; ADC control register 1, Address offset: 0x04 */
__IO uint32_t CR2; /*! & lt; ADC control register 2, Address offset: 0x08 */
__IO uint32_t SMPR1; /*! & lt; ADC sample time register 1, Address offset: 0x0C */
__IO uint32_t SMPR2; /*! & lt; ADC sample time register 2, Address offset: 0x10 */
__IO uint32_t JOFR1; /*! & lt; ADC injected channel data offset register 1, Address offset: 0x14 */
__IO uint32_t JOFR2; /*! & lt; ADC injected channel data offset register 2, Address offset: 0x18 */
__IO uint32_t JOFR3; /*! & lt; ADC injected channel data offset register 3, Address offset: 0x1C */
__IO uint32_t JOFR4; /*! & lt; ADC injected channel data offset register 4, Address offset: 0x20 */
__IO uint32_t HTR; /*! & lt; ADC watchdog higher threshold register, Address offset: 0x24 */
__IO uint32_t LTR; /*! & lt; ADC watchdog lower threshold register, Address offset: 0x28 */
__IO uint32_t SQR1; /*! & lt; ADC regular sequence register 1, Address offset: 0x2C */
__IO uint32_t SQR2; /*! & lt; ADC regular sequence register 2, Address offset: 0x30 */
__IO uint32_t SQR3; /*! & lt; ADC regular sequence register 3, Address offset: 0x34 */
__IO uint32_t JSQR; /*! & lt; ADC injected sequence register, Address offset: 0x38*/
__IO uint32_t JDR1; /*! & lt; ADC injected data register 1, Address offset: 0x3C */
__IO uint32_t JDR2; /*! & lt; ADC injected data register 2, Address offset: 0x40 */
__IO uint32_t JDR3; /*! & lt; ADC injected data register 3, Address offset: 0x44 */
__IO uint32_t JDR4; /*! & lt; ADC injected data register 4, Address offset: 0x48 */
__IO uint32_t DR; /*! & lt; ADC regular data register, Address offset: 0x4C */
} ADC_TypeDef;

typedef struct
{
__IO uint32_t CSR; /*! & lt; ADC Common status register, Address offset: ADC1 base address + 0x300 */
__IO uint32_t CCR; /*! & lt; ADC common control register, Address offset: ADC1 base address + 0x304 */
__IO uint32_t CDR; /*! & lt; ADC common regular data register for dual
AND triple modes, Address offset: ADC1 base address + 0x308 */
} ADC_Common_TypeDef;


/**
* @brief Controller Area Network TxMailBox
*/

typedef struct
{
__IO uint32_t TIR; /*! & lt; CAN TX mailbox identifier register */
__IO uint32_t TDTR; /*! & lt; CAN mailbox data length control and time stamp register */
__IO uint32_t TDLR; /*! & lt; CAN mailbox data low register */
__IO uint32_t TDHR; /*! & lt; CAN mailbox data high register */
} CAN_TxMailBox_TypeDef;

/**
* @brief Controller Area Network FIFOMailBox
*/

typedef struct
{
__IO uint32_t RIR; /*! & lt; CAN receive FIFO mailbox identifier register */
__IO uint32_t RDTR; /*! & lt; CAN receive FIFO mailbox data length control and time stamp register */
__IO uint32_t RDLR; /*! & lt; CAN receive FIFO mailbox data low register */
__IO uint32_t RDHR; /*! & lt; CAN receive FIFO mailbox data high register */
} CAN_FIFOMailBox_TypeDef;

/**
* @brief Controller Area Network FilterRegister
*/

typedef struct
{
__IO uint32_t FR1; /*! & lt; CAN Filter bank register 1 */
__IO uint32_t FR2; /*! & lt; CAN Filter bank register 1 */
} CAN_FilterRegister_TypeDef;

/**
* @brief Controller Area Network
*/

typedef struct
{
__IO uint32_t MCR; /*! & lt; CAN master control register, Address offset: 0x00 */
__IO uint32_t MSR; /*! & lt; CAN master status register, Address offset: 0x04 */
__IO uint32_t TSR; /*! & lt; CAN transmit status register, Address offset: 0x08 */
__IO uint32_t RF0R; /*! & lt; CAN receive FIFO 0 register, Address offset: 0x0C */
__IO uint32_t RF1R; /*! & lt; CAN receive FIFO 1 register, Address offset: 0x10 */
__IO uint32_t IER; /*! & lt; CAN interrupt enable register, Address offset: 0x14 */
__IO uint32_t ESR; /*! & lt; CAN error status register, Address offset: 0x18 */
__IO uint32_t BTR; /*! & lt; CAN bit timing register, Address offset: 0x1C */
uint32_t RESERVED0[88]; /*! & lt; Reserved, 0x020 - 0x17F */
CAN_TxMailBox_TypeDef sTxMailBox[3]; /*! & lt; CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*! & lt; CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
uint32_t RESERVED1[12]; /*! & lt; Reserved, 0x1D0 - 0x1FF */
__IO uint32_t FMR; /*! & lt; CAN filter master register, Address offset: 0x200 */
__IO uint32_t FM1R; /*! & lt; CAN filter mode register, Address offset: 0x204 */
uint32_t RESERVED2; /*! & lt; Reserved, 0x208 */
__IO uint32_t FS1R; /*! & lt; CAN filter scale register, Address offset: 0x20C */
uint32_t RESERVED3; /*! & lt; Reserved, 0x210 */
__IO uint32_t FFA1R; /*! & lt; CAN filter FIFO assignment register, Address offset: 0x214 */
uint32_t RESERVED4; /*! & lt; Reserved, 0x218 */
__IO uint32_t FA1R; /*! & lt; CAN filter activation register, Address offset: 0x21C */
uint32_t RESERVED5[8]; /*! & lt; Reserved, 0x220-0x23F */
CAN_FilterRegister_TypeDef sFilterRegister[28]; /*! & lt; CAN Filter Register, Address offset: 0x240-0x31C */
} CAN_TypeDef;

/**
* @brief CRC calculation unit
*/

typedef struct
{
__IO uint32_t DR; /*! & lt; CRC Data register, Address offset: 0x00 */
__IO uint8_t IDR; /*! & lt; CRC Independent data register, Address offset: 0x04 */
uint8_t RESERVED0; /*! & lt; Reserved, 0x05 */
uint16_t RESERVED1; /*! & lt; Reserved, 0x06 */
__IO uint32_t CR; /*! & lt; CRC Control register, Address offset: 0x08 */
} CRC_TypeDef;

/**
* @brief Digital to Analog Converter
*/

typedef struct
{
__IO uint32_t CR; /*! & lt; DAC control register, Address offset: 0x00 */
__IO uint32_t SWTRIGR; /*! & lt; DAC software trigger register, Address offset: 0x04 */
__IO uint32_t DHR12R1; /*! & lt; DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
__IO uint32_t DHR12L1; /*! & lt; DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
__IO uint32_t DHR8R1; /*! & lt; DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
__IO uint32_t DHR12R2; /*! & lt; DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
__IO uint32_t DHR12L2; /*! & lt; DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
__IO uint32_t DHR8R2; /*! & lt; DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
__IO uint32_t DHR12RD; /*! & lt; Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
__IO uint32_t DHR12LD; /*! & lt; DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
__IO uint32_t DHR8RD; /*! & lt; DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
__IO uint32_t DOR1; /*! & lt; DAC channel1 data output register, Address offset: 0x2C */
__IO uint32_t DOR2; /*! & lt; DAC channel2 data output register, Address offset: 0x30 */
__IO uint32_t SR; /*! & lt; DAC status register, Address offset: 0x34 */
} DAC_TypeDef;

/**
* @brief Debug MCU
*/

typedef struct
{
__IO uint32_t IDCODE; /*! & lt; MCU device ID code, Address offset: 0x00 */
__IO uint32_t CR; /*! & lt; Debug MCU configuration register, Address offset: 0x04 */
__IO uint32_t APB1FZ; /*! & lt; Debug MCU APB1 freeze register, Address offset: 0x08 */
__IO uint32_t APB2FZ; /*! & lt; Debug MCU APB2 freeze register, Address offset: 0x0C */
}DBGMCU_TypeDef;

/**
* @brief DCMI
*/

typedef struct
{
__IO uint32_t CR; /*! & lt; DCMI control register 1, Address offset: 0x00 */
__IO uint32_t SR; /*! & lt; DCMI status register, Address offset: 0x04 */
__IO uint32_t RISR; /*! & lt; DCMI raw interrupt status register, Address offset: 0x08 */
__IO uint32_t IER; /*! & lt; DCMI interrupt enable register, Address offset: 0x0C */
__IO uint32_t MISR; /*! & lt; DCMI masked interrupt status register, Address offset: 0x10 */
__IO uint32_t ICR; /*! & lt; DCMI interrupt clear register, Address offset: 0x14 */
__IO uint32_t ESCR; /*! & lt; DCMI embedded synchronization code register, Address offset: 0x18 */
__IO uint32_t ESUR; /*! & lt; DCMI embedded synchronization unmask register, Address offset: 0x1C */
__IO uint32_t CWSTRTR; /*! & lt; DCMI crop window start, Address offset: 0x20 */
__IO uint32_t CWSIZER; /*! & lt; DCMI crop window size, Address offset: 0x24 */
__IO uint32_t DR; /*! & lt; DCMI data register, Address offset: 0x28 */
} DCMI_TypeDef;

/**
* @brief DMA Controller
*/

typedef struct
{
__IO uint32_t CR; /*! & lt; DMA stream x configuration register */
__IO uint32_t NDTR; /*! & lt; DMA stream x number of data register */
__IO uint32_t PAR; /*! & lt; DMA stream x peripheral address register */
__IO uint32_t M0AR; /*! & lt; DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*! & lt; DMA stream x memory 1 address register */
__IO uint32_t FCR; /*! & lt; DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

typedef struct
{
__IO uint32_t LISR; /*! & lt; DMA low interrupt status register, Address offset: 0x00 */
__IO uint32_t HISR; /*! & lt; DMA high interrupt status register, Address offset: 0x04 */
__IO uint32_t LIFCR; /*! & lt; DMA low interrupt flag clear register, Address offset: 0x08 */
__IO uint32_t HIFCR; /*! & lt; DMA high interrupt flag clear register, Address offset: 0x0C */
} DMA_TypeDef;

/**
* @brief Ethernet MAC
*/

typedef struct
{
__IO uint32_t MACCR;
__IO uint32_t MACFFR;
__IO uint32_t MACHTHR;
__IO uint32_t MACHTLR;
__IO uint32_t MACMIIAR;
__IO uint32_t MACMIIDR;
__IO uint32_t MACFCR;
__IO uint32_t MACVLANTR; /* 8 */
uint32_t RESERVED0[2];
__IO uint32_t MACRWUFFR; /* 11 */
__IO uint32_t MACPMTCSR;
uint32_t RESERVED1[2];
__IO uint32_t MACSR; /* 15 */
__IO uint32_t MACIMR;
__IO uint32_t MACA0HR;
__IO uint32_t MACA0LR;
__IO uint32_t MACA1HR;
__IO uint32_t MACA1LR;
__IO uint32_t MACA2HR;
__IO uint32_t MACA2LR;
__IO uint32_t MACA3HR;
__IO uint32_t MACA3LR; /* 24 */
uint32_t RESERVED2[40];
__IO uint32_t MMCCR; /* 65 */
__IO uint32_t MMCRIR;
__IO uint32_t MMCTIR;
__IO uint32_t MMCRIMR;
__IO uint32_t MMCTIMR; /* 69 */
uint32_t RESERVED3[14];
__IO uint32_t MMCTGFSCCR; /* 84 */
__IO uint32_t MMCTGFMSCCR;
uint32_t RESERVED4[5];
__IO uint32_t MMCTGFCR;
uint32_t RESERVED5[10];
__IO uint32_t MMCRFCECR;
__IO uint32_t MMCRFAECR;
uint32_t RESERVED6[10];
__IO uint32_t MMCRGUFCR;
uint32_t RESERVED7[334];
__IO uint32_t PTPTSCR;
__IO uint32_t PTPSSIR;
__IO uint32_t PTPTSHR;
__IO uint32_t PTPTSLR;
__IO uint32_t PTPTSHUR;
__IO uint32_t PTPTSLUR;
__IO uint32_t PTPTSAR;
__IO uint32_t PTPTTHR;
__IO uint32_t PTPTTLR;
__IO uint32_t RESERVED8;
__IO uint32_t PTPTSSR;
uint32_t RESERVED9[565];
__IO uint32_t DMABMR;
__IO uint32_t DMATPDR;
__IO uint32_t DMARPDR;
__IO uint32_t DMARDLAR;
__IO uint32_t DMATDLAR;
__IO uint32_t DMASR;
__IO uint32_t DMAOMR;
__IO uint32_t DMAIER;
__IO uint32_t DMAMFBOCR;
__IO uint32_t DMARSWTR;
uint32_t RESERVED10[8];
__IO uint32_t DMACHTDR;
__IO uint32_t DMACHRDR;
__IO uint32_t DMACHTBAR;
__IO uint32_t DMACHRBAR;
} ETH_TypeDef;

/**
* @brief External Interrupt/Event Controller
*/

typedef struct
{
__IO uint32_t IMR; /*! & lt; EXTI Interrupt mask register, Address offset: 0x00 */
__IO uint32_t EMR; /*! & lt; EXTI Event mask register, Address offset: 0x04 */
__IO uint32_t RTSR; /*! & lt; EXTI Rising trigger selection register, Address offset: 0x08 */
__IO uint32_t FTSR; /*! & lt; EXTI Falling trigger selection register, Address offset: 0x0C */
__IO uint32_t SWIER; /*! & lt; EXTI Software interrupt event register, Address offset: 0x10 */
__IO uint32_t PR; /*! & lt; EXTI Pending register, Address offset: 0x14 */
} EXTI_TypeDef;

/**
* @brief FLASH Registers
*/

typedef struct
{
__IO uint32_t ACR; /*! & lt; FLASH access control register, Address offset: 0x00 */
__IO uint32_t KEYR; /*! & lt; FLASH key register, Address offset: 0x04 */
__IO uint32_t OPTKEYR; /*! & lt; FLASH option key register, Address offset: 0x08 */
__IO uint32_t SR; /*! & lt; FLASH status register, Address offset: 0x0C */
__IO uint32_t CR; /*! & lt; FLASH control register, Address offset: 0x10 */
__IO uint32_t OPTCR; /*! & lt; FLASH option control register, Address offset: 0x14 */
} FLASH_TypeDef;

/**
* @brief Flexible Static Memory Controller
*/

typedef struct
{
__IO uint32_t BTCR[8]; /*! & lt; NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
} FSMC_Bank1_TypeDef;

/**
* @brief Flexible Static Memory Controller Bank1E
*/

typedef struct
{
__IO uint32_t BWTR[7]; /*! & lt; NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
} FSMC_Bank1E_TypeDef;

/**
* @brief Flexible Static Memory Controller Bank2
*/

typedef struct
{
__IO uint32_t PCR2; /*! & lt; NAND Flash control register 2, Address offset: 0x60 */
__IO uint32_t SR2; /*! & lt; NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
__IO uint32_t PMEM2; /*! & lt; NAND Flash Common memory space timing register 2, Address offset: 0x68 */
__IO uint32_t PATT2; /*! & lt; NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
uint32_t RESERVED0; /*! & lt; Reserved, 0x70 */
__IO uint32_t ECCR2; /*! & lt; NAND Flash ECC result registers 2, Address offset: 0x74 */
} FSMC_Bank2_TypeDef;

/**
* @brief Flexible Static Memory Controller Bank3
*/

typedef struct
{
__IO uint32_t PCR3; /*! & lt; NAND Flash control register 3, Address offset: 0x80 */
__IO uint32_t SR3; /*! & lt; NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
__IO uint32_t PMEM3; /*! & lt; NAND Flash Common memory space timing register 3, Address offset: 0x88 */
__IO uint32_t PATT3; /*! & lt; NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
uint32_t RESERVED0; /*! & lt; Reserved, 0x90 */
__IO uint32_t ECCR3; /*! & lt; NAND Flash ECC result registers 3, Address offset: 0x94 */
} FSMC_Bank3_TypeDef;

/**
* @brief Flexible Static Memory Controller Bank4
*/

typedef struct
{
__IO uint32_t PCR4; /*! & lt; PC Card control register 4, Address offset: 0xA0 */
__IO uint32_t SR4; /*! & lt; PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
__IO uint32_t PMEM4; /*! & lt; PC Card Common memory space timing register 4, Address offset: 0xA8 */
__IO uint32_t PATT4; /*! & lt; PC Card Attribute memory space timing register 4, Address offset: 0xAC */
__IO uint32_t PIO4; /*! & lt; PC Card I/O space timing register 4, Address offset: 0xB0 */
} FSMC_Bank4_TypeDef;

/**
* @brief General Purpose I/O
*/

typedef struct
{
__IO uint32_t MODER; /*! & lt; GPIO port mode register, Address offset: 0x00 */
__IO uint32_t OTYPER; /*! & lt; GPIO port output type register, Address offset: 0x04 */
__IO uint32_t OSPEEDR; /*! & lt; GPIO port output speed register, Address offset: 0x08 */
__IO uint32_t PUPDR; /*! & lt; GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*! & lt; GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*! & lt; GPIO port output data register, Address offset: 0x14 */
__IO uint16_t BSRRL; /*! & lt; GPIO port bit set/reset low register, Address offset: 0x18 */
__IO uint16_t BSRRH; /*! & lt; GPIO port bit set/reset high register, Address offset: 0x1A */
__IO uint32_t LCKR; /*! & lt; GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*! & lt; GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef;

/**
* @brief System configuration controller
*/

typedef struct
{
__IO uint32_t MEMRMP; /*! & lt; SYSCFG memory remap register, Address offset: 0x00 */
__IO uint32_t PMC; /*! & lt; SYSCFG peripheral mode configuration register, Address offset: 0x04 */
__IO uint32_t EXTICR[4]; /*! & lt; SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
uint32_t RESERVED[2]; /*! & lt; Reserved, 0x18-0x1C */
__IO uint32_t CMPCR; /*! & lt; SYSCFG Compensation cell control register, Address offset: 0x20 */
} SYSCFG_TypeDef;

/**
* @brief Inter-integrated Circuit Interface
*/

typedef struct
{
__IO uint16_t CR1; /*! & lt; I2C Control register 1, Address offset: 0x00 */
uint16_t RESERVED0; /*! & lt; Reserved, 0x02 */
__IO uint16_t CR2; /*! & lt; I2C Control register 2, Address offset: 0x04 */
uint16_t RESERVED1; /*! & lt; Reserved, 0x06 */
__IO uint16_t OAR1; /*! & lt; I2C Own address register 1, Address offset: 0x08 */
uint16_t RESERVED2; /*! & lt; Reserved, 0x0A */
__IO uint16_t OAR2; /*! & lt; I2C Own address register 2, Address offset: 0x0C */
uint16_t RESERVED3; /*! & lt; Reserved, 0x0E */
__IO uint16_t DR; /*! & lt; I2C Data register, Address offset: 0x10 */
uint16_t RESERVED4; /*! & lt; Reserved, 0x12 */
__IO uint16_t SR1; /*! & lt; I2C Status register 1, Address offset: 0x14 */
uint16_t RESERVED5; /*! & lt; Reserved, 0x16 */
__IO uint16_t SR2; /*! & lt; I2C Status register 2, Address offset: 0x18 */
uint16_t RESERVED6; /*! & lt; Reserved, 0x1A */
__IO uint16_t CCR; /*! & lt; I2C Clock control register, Address offset: 0x1C */
uint16_t RESERVED7; /*! & lt; Reserved, 0x1E */
__IO uint16_t TRISE; /*! & lt; I2C TRISE register, Address offset: 0x20 */
uint16_t RESERVED8; /*! & lt; Reserved, 0x22 */
} I2C_TypeDef;

/**
* @brief Independent WATCHDOG
*/

typedef struct
{
__IO uint32_t KR; /*! & lt; IWDG Key register, Address offset: 0x00 */
__IO uint32_t PR; /*! & lt; IWDG Prescaler register, Address offset: 0x04 */
__IO uint32_t RLR; /*! & lt; IWDG Reload register, Address offset: 0x08 */
__IO uint32_t SR; /*! & lt; IWDG Status register, Address offset: 0x0C */
} IWDG_TypeDef;

/**
* @brief Power Control
*/

typedef struct
{
__IO uint32_t CR; /*! & lt; PWR power control register, Address offset: 0x00 */
__IO uint32_t CSR; /*! & lt; PWR power control/status register, Address offset: 0x04 */
} PWR_TypeDef;

/**
* @brief Reset and Clock Control
*/

typedef struct
{
__IO uint32_t CR; /*! & lt; RCC clock control register, Address offset: 0x00 */
__IO uint32_t PLLCFGR; /*! & lt; RCC PLL configuration register, Address offset: 0x04 */
__IO uint32_t CFGR; /*! & lt; RCC clock configuration register, Address offset: 0x08 */
__IO uint32_t CIR; /*! & lt; RCC clock interrupt register, Address offset: 0x0C */
__IO uint32_t AHB1RSTR; /*! & lt; RCC AHB1 peripheral reset register, Address offset: 0x10 */
__IO uint32_t AHB2RSTR; /*! & lt; RCC AHB2 peripheral reset register, Address offset: 0x14 */
__IO uint32_t AHB3RSTR; /*! & lt; RCC AHB3 peripheral reset register, Address offset: 0x18 */
uint32_t RESERVED0; /*! & lt; Reserved, 0x1C */
__IO uint32_t APB1RSTR; /*! & lt; RCC APB1 peripheral reset register, Address offset: 0x20 */
__IO uint32_t APB2RSTR; /*! & lt; RCC APB2 peripheral reset register, Address offset: 0x24 */
uint32_t RESERVED1[2]; /*! & lt; Reserved, 0x28-0x2C */
__IO uint32_t AHB1ENR; /*! & lt; RCC AHB1 peripheral clock register, Address offset: 0x30 */
__IO uint32_t AHB2ENR; /*! & lt; RCC AHB2 peripheral clock register, Address offset: 0x34 */
__IO uint32_t AHB3ENR; /*! & lt; RCC AHB3 peripheral clock register, Address offset: 0x38 */
uint32_t RESERVED2; /*! & lt; Reserved, 0x3C */
__IO uint32_t APB1ENR; /*! & lt; RCC APB1 peripheral clock enable register, Address offset: 0x40 */
__IO uint32_t APB2ENR; /*! & lt; RCC APB2 peripheral clock enable register, Address offset: 0x44 */
uint32_t RESERVED3[2]; /*! & lt; Reserved, 0x48-0x4C */
__IO uint32_t AHB1LPENR; /*! & lt; RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
__IO uint32_t AHB2LPENR; /*! & lt; RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
__IO uint32_t AHB3LPENR; /*! & lt; RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
uint32_t RESERVED4; /*! & lt; Reserved, 0x5C */
__IO uint32_t APB1LPENR; /*! & lt; RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
__IO uint32_t APB2LPENR; /*! & lt; RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
uint32_t RESERVED5[2]; /*! & lt; Reserved, 0x68-0x6C */
__IO uint32_t BDCR; /*! & lt; RCC Backup domain control register, Address offset: 0x70 */
__IO uint32_t CSR; /*! & lt; RCC clock control & status register, Address offset: 0x74 */
uint32_t RESERVED6[2]; /*! & lt; Reserved, 0x78-0x7C */
__IO uint32_t SSCGR; /*! & lt; RCC spread spectrum clock generation register, Address offset: 0x80 */
__IO uint32_t PLLI2SCFGR; /*! & lt; RCC PLLI2S configuration register, Address offset: 0x84 */
} RCC_TypeDef;

/**
* @brief Real-Time Clock
*/

typedef struct
{
__IO uint32_t TR; /*! & lt; RTC time register, Address offset: 0x00 */
__IO uint32_t DR; /*! & lt; RTC date register, Address offset: 0x04 */
__IO uint32_t CR; /*! & lt; RTC control register, Address offset: 0x08 */
__IO uint32_t ISR; /*! & lt; RTC initialization and status register, Address offset: 0x0C */
__IO uint32_t PRER; /*! & lt; RTC prescaler register, Address offset: 0x10 */
__IO uint32_t WUTR; /*! & lt; RTC wakeup timer register, Address offset: 0x14 */
__IO uint32_t CALIBR; /*! & lt; RTC calibration register, Address offset: 0x18 */
__IO uint32_t ALRMAR; /*! & lt; RTC alarm A register, Address offset: 0x1C */
__IO uint32_t ALRMBR; /*! & lt; RTC alarm B register, Address offset: 0x20 */
__IO uint32_t WPR; /*! & lt; RTC write protection register, Address offset: 0x24 */
__IO uint32_t SSR; /*! & lt; RTC sub second register, Address offset: 0x28 */
__IO uint32_t SHIFTR; /*! & lt; RTC shift control register, Address offset: 0x2C */
__IO uint32_t TSTR; /*! & lt; RTC time stamp time register, Address offset: 0x30 */
__IO uint32_t TSDR; /*! & lt; RTC time stamp date register, Address offset: 0x34 */
__IO uint32_t TSSSR; /*! & lt; RTC time-stamp sub second register, Address offset: 0x38 */
__IO uint32_t CALR; /*! & lt; RTC calibration register, Address offset: 0x3C */
__IO uint32_t TAFCR; /*! & lt; RTC tamper and alternate function configuration register, Address offset: 0x40 */
__IO uint32_t ALRMASSR;/*! & lt; RTC alarm A sub second register, Address offset: 0x44 */
__IO uint32_t ALRMBSSR;/*! & lt; RTC alarm B sub second register, Address offset: 0x48 */
uint32_t RESERVED7; /*! & lt; Reserved, 0x4C */
__IO uint32_t BKP0R; /*! & lt; RTC backup register 1, Address offset: 0x50 */
__IO uint32_t BKP1R; /*! & lt; RTC backup register 1, Address offset: 0x54 */
__IO uint32_t BKP2R; /*! & lt; RTC backup register 2, Address offset: 0x58 */
__IO uint32_t BKP3R; /*! & lt; RTC backup register 3, Address offset: 0x5C */
__IO uint32_t BKP4R; /*! & lt; RTC backup register 4, Address offset: 0x60 */
__IO uint32_t BKP5R; /*! & lt; RTC backup register 5, Address offset: 0x64 */
__IO uint32_t BKP6R; /*! & lt; RTC backup register 6, Address offset: 0x68 */
__IO uint32_t BKP7R; /*! & lt; RTC backup register 7, Address offset: 0x6C */
__IO uint32_t BKP8R; /*! & lt; RTC backup register 8, Address offset: 0x70 */
__IO uint32_t BKP9R; /*! & lt; RTC backup register 9, Address offset: 0x74 */
__IO uint32_t BKP10R; /*! & lt; RTC backup register 10, Address offset: 0x78 */
__IO uint32_t BKP11R; /*! & lt; RTC backup register 11, Address offset: 0x7C */
__IO uint32_t BKP12R; /*! & lt; RTC backup register 12, Address offset: 0x80 */
__IO uint32_t BKP13R; /*! & lt; RTC backup register 13, Address offset: 0x84 */
__IO uint32_t BKP14R; /*! & lt; RTC backup register 14, Address offset: 0x88 */
__IO uint32_t BKP15R; /*! & lt; RTC backup register 15, Address offset: 0x8C */
__IO uint32_t BKP16R; /*! & lt; RTC backup register 16, Address offset: 0x90 */
__IO uint32_t BKP17R; /*! & lt; RTC backup register 17, Address offset: 0x94 */
__IO uint32_t BKP18R; /*! & lt; RTC backup register 18, Address offset: 0x98 */
__IO uint32_t BKP19R; /*! & lt; RTC backup register 19, Address offset: 0x9C */
} RTC_TypeDef;

/**
* @brief SD host Interface
*/

typedef struct
{
__IO uint32_t POWER; /*! & lt; SDIO power control register, Address offset: 0x00 */
__IO uint32_t CLKCR; /*! & lt; SDI clock control register, Address offset: 0x04 */
__IO uint32_t ARG; /*! & lt; SDIO argument register, Address offset: 0x08 */
__IO uint32_t CMD; /*! & lt; SDIO command register, Address offset: 0x0C */
__I uint32_t RESPCMD; /*! & lt; SDIO command response register, Address offset: 0x10 */
__I uint32_t RESP1; /*! & lt; SDIO response 1 register, Address offset: 0x14 */
__I uint32_t RESP2; /*! & lt; SDIO response 2 register, Address offset: 0x18 */
__I uint32_t RESP3; /*! & lt; SDIO response 3 register, Address offset: 0x1C */
__I uint32_t RESP4; /*! & lt; SDIO response 4 register, Address offset: 0x20 */
__IO uint32_t DTIMER; /*! & lt; SDIO data timer register, Address offset: 0x24 */
__IO uint32_t DLEN; /*! & lt; SDIO data length register, Address offset: 0x28 */
__IO uint32_t DCTRL; /*! & lt; SDIO data control register, Address offset: 0x2C */
__I uint32_t DCOUNT; /*! & lt; SDIO data counter register, Address offset: 0x30 */
__I uint32_t STA; /*! & lt; SDIO status register, Address offset: 0x34 */
__IO uint32_t ICR; /*! & lt; SDIO interrupt clear register, Address offset: 0x38 */
__IO uint32_t MASK; /*! & lt; SDIO mask register, Address offset: 0x3C */
uint32_t RESERVED0[2]; /*! & lt; Reserved, 0x40-0x44 */
__I uint32_t FIFOCNT; /*! & lt; SDIO FIFO counter register, Address offset: 0x48 */
uint32_t RESERVED1[13]; /*! & lt; Reserved, 0x4C-0x7C */
__IO uint32_t FIFO; /*! & lt; SDIO data FIFO register, Address offset: 0x80 */
} SDIO_TypeDef;

/**
* @brief Serial Peripheral Interface
*/

typedef struct
{
__IO uint16_t CR1; /*! & lt; SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
uint16_t RESERVED0; /*! & lt; Reserved, 0x02 */
__IO uint16_t CR2; /*! & lt; SPI control register 2, Address offset: 0x04 */
uint16_t RESERVED1; /*! & lt; Reserved, 0x06 */
__IO uint16_t SR; /*! & lt; SPI status register, Address offset: 0x08 */
uint16_t RESERVED2; /*! & lt; Reserved, 0x0A */
__IO uint16_t DR; /*! & lt; SPI data register, Address offset: 0x0C */
uint16_t RESERVED3; /*! & lt; Reserved, 0x0E */
__IO uint16_t CRCPR; /*! & lt; SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
uint16_t RESERVED4; /*! & lt; Reserved, 0x12 */
__IO uint16_t RXCRCR; /*! & lt; SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
uint16_t RESERVED5; /*! & lt; Reserved, 0x16 */
__IO uint16_t TXCRCR; /*! & lt; SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
uint16_t RESERVED6; /*! & lt; Reserved, 0x1A */
__IO uint16_t I2SCFGR; /*! & lt; SPI_I2S configuration register, Address offset: 0x1C */
uint16_t RESERVED7; /*! & lt; Reserved, 0x1E */
__IO uint16_t I2SPR; /*! & lt; SPI_I2S prescaler register, Address offset: 0x20 */
uint16_t RESERVED8; /*! & lt; Reserved, 0x22 */
} SPI_TypeDef;

/**
* @brief TIM
*/

typedef struct
{
__IO uint16_t CR1; /*! & lt; TIM control register 1, Address offset: 0x00 */
uint16_t RESERVED0; /*! & lt; Reserved, 0x02 */
__IO uint16_t CR2; /*! & lt; TIM control register 2, Address offset: 0x04 */
uint16_t RESERVED1; /*! & lt; Reserved, 0x06 */
__IO uint16_t SMCR; /*! & lt; TIM slave mode control register, Address offset: 0x08 */
uint16_t RESERVED2; /*! & lt; Reserved, 0x0A */
__IO uint16_t DIER; /*! & lt; TIM DMA/interrupt enable register, Address offset: 0x0C */
uint16_t RESERVED3; /*! & lt; Reserved, 0x0E */
__IO uint16_t SR; /*! & lt; TIM status register, Address offset: 0x10 */
uint16_t RESERVED4; /*! & lt; Reserved, 0x12 */
__IO uint16_t EGR; /*! & lt; TIM event generation register, Address offset: 0x14 */
uint16_t RESERVED5; /*! & lt; Reserved, 0x16 */
__IO uint16_t CCMR1; /*! & lt; TIM capture/compare mode register 1, Address offset: 0x18 */
uint16_t RESERVED6; /*! & lt; Reserved, 0x1A */
__IO uint16_t CCMR2; /*! & lt; TIM capture/compare mode register 2, Address offset: 0x1C */
uint16_t RESERVED7; /*! & lt; Reserved, 0x1E */
__IO uint16_t CCER; /*! & lt; TIM capture/compare enable register, Address offset: 0x20 */
uint16_t RESERVED8; /*! & lt; Reserved, 0x22 */
__IO uint32_t CNT; /*! & lt; TIM counter register, Address offset: 0x24 */
__IO uint16_t PSC; /*! & lt; TIM prescaler, Address offset: 0x28 */
uint16_t RESERVED9; /*! & lt; Reserved, 0x2A */
__IO uint32_t ARR; /*! & lt; TIM auto-reload register, Address offset: 0x2C */
__IO uint16_t RCR; /*! & lt; TIM repetition counter register, Address offset: 0x30 */
uint16_t RESERVED10; /*! & lt; Reserved, 0x32 */
__IO uint32_t CCR1; /*! & lt; TIM capture/compare register 1, Address offset: 0x34 */
__IO uint32_t CCR2; /*! & lt; TIM capture/compare register 2, Address offset: 0x38 */
__IO uint32_t CCR3; /*! & lt; TIM capture/compare register 3, Address offset: 0x3C */
__IO uint32_t CCR4; /*! & lt; TIM capture/compare register 4, Address offset: 0x40 */
__IO uint16_t BDTR; /*! & lt; TIM break and dead-time register, Address offset: 0x44 */
uint16_t RESERVED11; /*! & lt; Reserved, 0x46 */
__IO uint16_t DCR; /*! & lt; TIM DMA control register, Address offset: 0x48 */
uint16_t RESERVED12; /*! & lt; Reserved, 0x4A */
__IO uint16_t DMAR; /*! & lt; TIM DMA address for full transfer, Address offset: 0x4C */
uint16_t RESERVED13; /*! & lt; Reserved, 0x4E */
__IO uint16_t OR; /*! & lt; TIM option register, Address offset: 0x50 */
uint16_t RESERVED14; /*! & lt; Reserved, 0x52 */
} TIM_TypeDef;

/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
*/

typedef struct
{
__IO uint16_t SR; /*! & lt; USART Status register, Address offset: 0x00 */
uint16_t RESERVED0; /*! & lt; Reserved, 0x02 */
__IO uint16_t DR; /*! & lt; USART Data register, Address offset: 0x04 */
uint16_t RESERVED1; /*! & lt; Reserved, 0x06 */
__IO uint16_t BRR; /*! & lt; USART Baud rate register, Address offset: 0x08 */
uint16_t RESERVED2; /*! & lt; Reserved, 0x0A */
__IO uint16_t CR1; /*! & lt; USART Control register 1, Address offset: 0x0C */
uint16_t RESERVED3; /*! & lt; Reserved, 0x0E */
__IO uint16_t CR2; /*! & lt; USART Control register 2, Address offset: 0x10 */
uint16_t RESERVED4; /*! & lt; Reserved, 0x12 */
__IO uint16_t CR3; /*! & lt; USART Control register 3, Address offset: 0x14 */
uint16_t RESERVED5; /*! & lt; Reserved, 0x16 */
__IO uint16_t GTPR; /*! & lt; USART Guard time and prescaler register, Address offset: 0x18 */
uint16_t RESERVED6; /*! & lt; Reserved, 0x1A */
} USART_TypeDef;

/**
* @brief Window WATCHDOG
*/

typedef struct
{
__IO uint32_t CR; /*! & lt; WWDG Control register, Address offset: 0x00 */
__IO uint32_t CFR; /*! & lt; WWDG Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*! & lt; WWDG Status register, Address offset: 0x08 */
} WWDG_TypeDef;

/**
* @brief Crypto Processor
*/

typedef struct
{
__IO uint32_t CR; /*! & lt; CRYP control register, Address offset: 0x00 */
__IO uint32_t SR; /*! & lt; CRYP status register, Address offset: 0x04 */
__IO uint32_t DR; /*! & lt; CRYP data input register, Address offset: 0x08 */
__IO uint32_t DOUT; /*! & lt; CRYP data output register, Address offset: 0x0C */
__IO uint32_t DMACR; /*! & lt; CRYP DMA control register, Address offset: 0x10 */
__IO uint32_t IMSCR; /*! & lt; CRYP interrupt mask set/clear register, Address offset: 0x14 */
__IO uint32_t RISR; /*! & lt; CRYP raw interrupt status register, Address offset: 0x18 */
__IO uint32_t MISR; /*! & lt; CRYP masked interrupt status register, Address offset: 0x1C */
__IO uint32_t K0LR; /*! & lt; CRYP key left register 0, Address offset: 0x20 */
__IO uint32_t K0RR; /*! & lt; CRYP key right register 0, Address offset: 0x24 */
__IO uint32_t K1LR; /*! & lt; CRYP key left register 1, Address offset: 0x28 */
__IO uint32_t K1RR; /*! & lt; CRYP key right register 1, Address offset: 0x2C */
__IO uint32_t K2LR; /*! & lt; CRYP key left register 2, Address offset: 0x30 */
__IO uint32_t K2RR; /*! & lt; CRYP key right register 2, Address offset: 0x34 */
__IO uint32_t K3LR; /*! & lt; CRYP key left register 3, Address offset: 0x38 */
__IO uint32_t K3RR; /*! & lt; CRYP key right register 3, Address offset: 0x3C */
__IO uint32_t IV0LR; /*! & lt; CRYP initialization vector left-word register 0, Address offset: 0x40 */
__IO uint32_t IV0RR; /*! & lt; CRYP initialization vector right-word register 0, Address offset: 0x44 */
__IO uint32_t IV1LR; /*! & lt; CRYP initialization vector left-word register 1, Address offset: 0x48 */
__IO uint32_t IV1RR; /*! & lt; CRYP initialization vector right-word register 1, Address offset: 0x4C */
} CRYP_TypeDef;

/**
* @brief HASH
*/

typedef struct
{
__IO uint32_t CR; /*! & lt; HASH control register, Address offset: 0x00 */
__IO uint32_t DIN; /*! & lt; HASH data input register, Address offset: 0x04 */
__IO uint32_t STR; /*! & lt; HASH start register, Address offset: 0x08 */
__IO uint32_t HR[5]; /*! & lt; HASH digest registers, Address offset: 0x0C-0x1C */
__IO uint32_t IMR; /*! & lt; HASH interrupt enable register, Address offset: 0x20 */
__IO uint32_t SR; /*! & lt; HASH status register, Address offset: 0x24 */
uint32_t RESERVED[52]; /*! & lt; Reserved, 0x28-0xF4 */
__IO uint32_t CSR[51]; /*! & lt; HASH context swap registers, Address offset: 0x0F8-0x1C0 */
} HASH_TypeDef;

/**
* @brief HASH
*/

typedef struct
{
__IO uint32_t CR; /*! & lt; RNG control register, Address offset: 0x00 */
__IO uint32_t SR; /*! & lt; RNG status register, Address offset: 0x04 */
__IO uint32_t DR; /*! & lt; RNG data register, Address offset: 0x08 */
} RNG_TypeDef;

/**
* @}
*/

/** @addtogroup Peripheral_memory_map
* @{
*/
#define FLASH_BASE ((uint32_t)0x08000000) /*! & lt; FLASH(up to 1 MB) base address in the alias region */
#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*! & lt; CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
#define SRAM1_BASE ((uint32_t)0x20000000) /*! & lt; SRAM1(112 KB) base address in the alias region */
#define SRAM2_BASE ((uint32_t)0x2001C000) /*! & lt; SRAM2(16 KB) base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*! & lt; Peripheral base address in the alias region */
#define BKPSRAM_BASE ((uint32_t)0x40024000) /*! & lt; Backup SRAM(4 KB) base address in the alias region */
#define FSMC_R_BASE ((uint32_t)0xA0000000) /*! & lt; FSMC registers base address */

#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*! & lt; CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*! & lt; SRAM1(112 KB) base address in the bit-band region */
#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*! & lt; SRAM2(16 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*! & lt; Peripheral base address in the bit-band region */
#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*! & lt; Backup SRAM(4 KB) base address in the bit-band region */

/* Legacy defines */
#define SRAM_BASE SRAM1_BASE
#define SRAM_BB_BASE SRAM1_BB_BASE


/*! & lt; Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)

/*! & lt; APB1 peripherals */
#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
#define DAC_BASE (APB1PERIPH_BASE + 0x7400)

/*! & lt; APB2 peripherals */
#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
#define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
#define ADC_BASE (APB2PERIPH_BASE + 0x2300)
#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
#define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)

/*! & lt; AHB1 peripherals */
#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
#define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
#define ETH_MAC_BASE (ETH_BASE)
#define ETH_MMC_BASE (ETH_BASE + 0x0100)
#define ETH_PTP_BASE (ETH_BASE + 0x0700)
#define ETH_DMA_BASE (ETH_BASE + 0x1000)

/*! & lt; AHB2 peripherals */
#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000)
#define HASH_BASE (AHB2PERIPH_BASE + 0x60400)
#define RNG_BASE (AHB2PERIPH_BASE + 0x60800)

/*! & lt; FSMC Bankx registers base address */
#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)
#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)

/* Debug MCU registers base address */
#define DBGMCU_BASE ((uint32_t )0xE0042000)

/**
* @}
*/

/** @addtogroup Peripheral_declaration
* @{
*/
#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
#define RTC ((RTC_TypeDef *) RTC_BASE)
#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
#define USART2 ((USART_TypeDef *) USART2_BASE)
#define USART3 ((USART_TypeDef *) USART3_BASE)
#define UART4 ((USART_TypeDef *) UART4_BASE)
#define UART5 ((USART_TypeDef *) UART5_BASE)
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
#define DAC ((DAC_TypeDef *) DAC_BASE)
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
#define USART1 ((USART_TypeDef *) USART1_BASE)
#define USART6 ((USART_TypeDef *) USART6_BASE)
#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define RCC ((RCC_TypeDef *) RCC_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
#define ETH ((ETH_TypeDef *) ETH_BASE)
#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
#define HASH ((HASH_TypeDef *) HASH_BASE)
#define RNG ((RNG_TypeDef *) RNG_BASE)
#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

/**
* @}
*/

/** @addtogroup Exported_constants
* @{
*/

/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/

/******************************************************************************/
/* Peripheral Registers_Bits_Definition */
/******************************************************************************/

/******************************************************************************/
/* */
/* Analog to Digital Converter */
/* */
/******************************************************************************/
/******************** Bit definition for ADC_SR register ********************/
#define ADC_SR_AWD ((uint8_t)0x01) /*! & lt; Analog watchdog flag */
#define ADC_SR_EOC ((uint8_t)0x02) /*! & lt; End of conversion */
#define ADC_SR_JEOC ((uint8_t)0x04) /*! & lt; Injected channel end of conversion */
#define ADC_SR_JSTRT ((uint8_t)0x08) /*! & lt; Injected channel Start flag */
#define ADC_SR_STRT ((uint8_t)0x10) /*! & lt; Regular channel Start flag */
#define ADC_SR_OVR ((uint8_t)0x20) /*! & lt; Overrun flag */

/******************* Bit definition for ADC_CR1 register ********************/
#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*! & lt; AWDCH[4:0] bits (Analog watchdog channel select bits) */
#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*! & lt; Bit 0 */
#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*! & lt; Bit 1 */
#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*! & lt; Bit 2 */
#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*! & lt; Bit 3 */
#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*! & lt; Bit 4 */
#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*! & lt; Interrupt enable for EOC */
#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*! & lt; AAnalog Watchdog interrupt enable */
#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*! & lt; Interrupt enable for injected channels */
#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*! & lt; Scan mode */
#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*! & lt; Enable the watchdog on a single channel in scan mode */
#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*! & lt; Automatic injected group conversion */
#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*! & lt; Discontinuous mode on regular channels */
#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*! & lt; Discontinuous mode on injected channels */
#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*! & lt; DISCNUM[2:0] bits (Discontinuous mode channel count) */
#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*! & lt; Bit 0 */
#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*! & lt; Bit 1 */
#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*! & lt; Bit 2 */
#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*! & lt; Analog watchdog enable on injected channels */
#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*! & lt; Analog watchdog enable on regular channels */
#define ADC_CR1_RES ((uint32_t)0x03000000) /*! & lt; RES[2:0] bits (Resolution) */
#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*! & lt; Bit 0 */
#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*! & lt; Bit 1 */
#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*! & lt; overrun interrupt enable */

/******************* Bit definition for ADC_CR2 register ********************/
#define ADC_CR2_ADON ((uint32_t)0x00000001) /*! & lt; A/D Converter ON / OFF */
#define ADC_CR2_CONT ((uint32_t)0x00000002) /*! & lt; Continuous Conversion */
#define ADC_CR2_DMA ((uint32_t)0x00000100) /*! & lt; Direct Memory access mode */
#define ADC_CR2_DDS ((uint32_t)0x00000200) /*! & lt; DMA disable selection (Single ADC) */
#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*! & lt; End of conversion selection */
#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*! & lt; Data Alignment */
#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*! & lt; JEXTSEL[3:0] bits (External event select for injected group) */
#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*! & lt; Bit 0 */
#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*! & lt; Bit 1 */
#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*! & lt; Bit 2 */
#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*! & lt; Bit 3 */
#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*! & lt; JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*! & lt; Bit 0 */
#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*! & lt; Bit 1 */
#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*! & lt; Start Conversion of injected channels */
#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*! & lt; EXTSEL[3:0] bits (External Event Select for regular group) */
#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*! & lt; Bit 0 */
#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*! & lt; Bit 1 */
#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*! & lt; Bit 2 */
#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*! & lt; Bit 3 */
#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*! & lt; EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*! & lt; Bit 0 */
#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*! & lt; Bit 1 */
#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*! & lt; Start Conversion of regular channels */

/****************** Bit definition for ADC_SMPR1 register *******************/
#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*! & lt; SMP10[2:0] bits (Channel 10 Sample time selection) */
#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*! & lt; Bit 0 */
#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*! & lt; Bit 1 */
#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*! & lt; Bit 2 */
#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*! & lt; SMP11[2:0] bits (Channel 11 Sample time selection) */
#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*! & lt; Bit 0 */
#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*! & lt; Bit 1 */
#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*! & lt; Bit 2 */
#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*! & lt; SMP12[2:0] bits (Channel 12 Sample time selection) */
#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*! & lt; Bit 0 */
#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*! & lt; Bit 1 */
#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*! & lt; Bit 2 */
#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*! & lt; SMP13[2:0] bits (Channel 13 Sample time selection) */
#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*! & lt; Bit 0 */
#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*! & lt; Bit 1 */
#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*! & lt; Bit 2 */
#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*! & lt; SMP14[2:0] bits (Channel 14 Sample time selection) */
#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*! & lt; Bit 0 */
#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*! & lt; Bit 1 */
#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*! & lt; Bit 2 */
#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*! & lt; SMP15[2:0] bits (Channel 15 Sample time selection) */
#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*! & lt; Bit 0 */
#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*! & lt; Bit 1 */
#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*! & lt; Bit 2 */
#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*! & lt; SMP16[2:0] bits (Channel 16 Sample time selection) */
#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*! & lt; Bit 0 */
#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*! & lt; Bit 1 */
#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*! & lt; Bit 2 */
#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*! & lt; SMP17[2:0] bits (Channel 17 Sample time selection) */
#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*! & lt; Bit 0 */
#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*! & lt; Bit 1 */
#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*! & lt; Bit 2 */
#define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*! & lt; SMP18[2:0] bits (Channel 18 Sample time selection) */
#define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*! & lt; Bit 0 */
#define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*! & lt; Bit 1 */
#define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*! & lt; Bit 2 */

/****************** Bit definition for ADC_SMPR2 register *******************/
#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*! & lt; SMP0[2:0] bits (Channel 0 Sample time selection) */
#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*! & lt; Bit 0 */
#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*! & lt; Bit 1 */
#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*! & lt; Bit 2 */
#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*! & lt; SMP1[2:0] bits (Channel 1 Sample time selection) */
#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*! & lt; Bit 0 */
#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*! & lt; Bit 1 */
#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*! & lt; Bit 2 */
#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*! & lt; SMP2[2:0] bits (Channel 2 Sample time selection) */
#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*! & lt; Bit 0 */
#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*! & lt; Bit 1 */
#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*! & lt; Bit 2 */
#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*! & lt; SMP3[2:0] bits (Channel 3 Sample time selection) */
#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*! & lt; Bit 0 */
#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*! & lt; Bit 1 */
#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*! & lt; Bit 2 */
#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*! & lt; SMP4[2:0] bits (Channel 4 Sample time selection) */
#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*! & lt; Bit 0 */
#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*! & lt; Bit 1 */
#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*! & lt; Bit 2 */
#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*! & lt; SMP5[2:0] bits (Channel 5 Sample time selection) */
#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*! & lt; Bit 0 */
#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*! & lt; Bit 1 */
#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*! & lt; Bit 2 */
#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*! & lt; SMP6[2:0] bits (Channel 6 Sample time selection) */
#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*! & lt; Bit 0 */
#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*! & lt; Bit 1 */
#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*! & lt; Bit 2 */
#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*! & lt; SMP7[2:0] bits (Channel 7 Sample time selection) */
#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*! & lt; Bit 0 */
#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*! & lt; Bit 1 */
#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*! & lt; Bit 2 */
#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*! & lt; SMP8[2:0] bits (Channel 8 Sample time selection) */
#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*! & lt; Bit 0 */
#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*! & lt; Bit 1 */
#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*! & lt; Bit 2 */
#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*! & lt; SMP9[2:0] bits (Channel 9 Sample time selection) */
#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*! & lt; Bit 0 */
#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*! & lt; Bit 1 */
#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*! & lt; Bit 2 */

/****************** Bit definition for ADC_JOFR1 register *******************/
#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*! & lt; Data offset for injected channel 1 */

/****************** Bit definition for ADC_JOFR2 register *******************/
#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*! & lt; Data offset for injected channel 2 */

/****************** Bit definition for ADC_JOFR3 register *******************/
#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*! & lt; Data offset for injected channel 3 */

/****************** Bit definition for ADC_JOFR4 register *******************/
#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*! & lt; Data offset for injected channel 4 */

/******************* Bit definition for ADC_HTR register ********************/
#define ADC_HTR_HT ((uint16_t)0x0FFF) /*! & lt; Analog watchdog high threshold */

/******************* Bit definition for ADC_LTR register ********************/
#define ADC_LTR_LT ((uint16_t)0x0FFF) /*! & lt; Analog watchdog low threshold */

/******************* Bit definition for ADC_SQR1 register *******************/
#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*! & lt; SQ13[4:0] bits (13th conversion in regular sequence) */
#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*! & lt; Bit 0 */
#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*! & lt; Bit 1 */
#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*! & lt; Bit 2 */
#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*! & lt; Bit 3 */
#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*! & lt; Bit 4 */
#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*! & lt; SQ14[4:0] bits (14th conversion in regular sequence) */
#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*! & lt; Bit 0 */
#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*! & lt; Bit 1 */
#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*! & lt; Bit 2 */
#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*! & lt; Bit 3 */
#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*! & lt; Bit 4 */
#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*! & lt; SQ15[4:0] bits (15th conversion in regular sequence) */
#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*! & lt; Bit 0 */
#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*! & lt; Bit 1 */
#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*! & lt; Bit 2 */
#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*! & lt; Bit 3 */
#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*! & lt; Bit 4 */
#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*! & lt; SQ16[4:0] bits (16th conversion in regular sequence) */
#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*! & lt; Bit 0 */
#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*! & lt; Bit 1 */
#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*! & lt; Bit 2 */
#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*! & lt; Bit 3 */
#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*! & lt; Bit 4 */
#define ADC_SQR1_L ((uint32_t)0x00F00000) /*! & lt; L[3:0] bits (Regular channel sequence length) */
#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*! & lt; Bit 0 */
#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*! & lt; Bit 1 */
#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*! & lt; Bit 2 */
#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*! & lt; Bit 3 */

/******************* Bit definition for ADC_SQR2 register *******************/
#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*! & lt; SQ7[4:0] bits (7th conversion in regular sequence) */
#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*! & lt; Bit 0 */
#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*! & lt; Bit 1 */
#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*! & lt; Bit 2 */
#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*! & lt; Bit 3 */
#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*! & lt; Bit 4 */
#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*! & lt; SQ8[4:0] bits (8th conversion in regular sequence) */
#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*! & lt; Bit 0 */
#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*! & lt; Bit 1 */
#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*! & lt; Bit 2 */
#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*! & lt; Bit 3 */
#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*! & lt; Bit 4 */
#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*! & lt; SQ9[4:0] bits (9th conversion in regular sequence) */
#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*! & lt; Bit 0 */
#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*! & lt; Bit 1 */
#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*! & lt; Bit 2 */
#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*! & lt; Bit 3 */
#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*! & lt; Bit 4 */
#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*! & lt; SQ10[4:0] bits (10th conversion in regular sequence) */
#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*! & lt; Bit 0 */
#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*! & lt; Bit 1 */
#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*! & lt; Bit 2 */
#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*! & lt; Bit 3 */
#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*! & lt; Bit 4 */
#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*! & lt; SQ11[4:0] bits (11th conversion in regular sequence) */
#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*! & lt; Bit 0 */
#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*! & lt; Bit 1 */
#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*! & lt; Bit 2 */
#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*! & lt; Bit 3 */
#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*! & lt; Bit 4 */
#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*! & lt; SQ12[4:0] bits (12th conversion in regular sequence) */
#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*! & lt; Bit 0 */
#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*! & lt; Bit 1 */
#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*! & lt; Bit 2 */
#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*! & lt; Bit 3 */
#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*! & lt; Bit 4 */

/******************* Bit definition for ADC_SQR3 register *******************/
#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*! & lt; SQ1[4:0] bits (1st conversion in regular sequence) */
#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*! & lt; Bit 0 */
#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*! & lt; Bit 1 */
#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*! & lt; Bit 2 */
#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*! & lt; Bit 3 */
#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*! & lt; Bit 4 */
#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*! & lt; SQ2[4:0] bits (2nd conversion in regular sequence) */
#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*! & lt; Bit 0 */
#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*! & lt; Bit 1 */
#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*! & lt; Bit 2 */
#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*! & lt; Bit 3 */
#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*! & lt; Bit 4 */
#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*! & lt; SQ3[4:0] bits (3rd conversion in regular sequence) */
#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*! & lt; Bit 0 */
#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*! & lt; Bit 1 */
#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*! & lt; Bit 2 */
#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*! & lt; Bit 3 */
#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*! & lt; Bit 4 */
#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*! & lt; SQ4[4:0] bits (4th conversion in regular sequence) */
#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*! & lt; Bit 0 */
#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*! & lt; Bit 1 */
#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*! & lt; Bit 2 */
#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*! & lt; Bit 3 */
#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*! & lt; Bit 4 */
#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*! & lt; SQ5[4:0] bits (5th conversion in regular sequence) */
#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*! & lt; Bit 0 */
#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*! & lt; Bit 1 */
#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*! & lt; Bit 2 */
#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*! & lt; Bit 3 */
#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*! & lt; Bit 4 */
#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*! & lt; SQ6[4:0] bits (6th conversion in regular sequence) */
#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*! & lt; Bit 0 */
#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*! & lt; Bit 1 */
#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*! & lt; Bit 2 */
#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*! & lt; Bit 3 */
#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*! & lt; Bit 4 */

/******************* Bit definition for ADC_JSQR register *******************/
#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*! & lt; JSQ1[4:0] bits (1st conversion in injected sequence) */
#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*! & lt; Bit 0 */
#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*! & lt; Bit 1 */
#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*! & lt; Bit 2 */
#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*! & lt; Bit 3 */
#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*! & lt; Bit 4 */
#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*! & lt; JSQ2[4:0] bits (2nd conversion in injected sequence) */
#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*! & lt; Bit 0 */
#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*! & lt; Bit 1 */
#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*! & lt; Bit 2 */
#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*! & lt; Bit 3 */
#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*! & lt; Bit 4 */
#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*! & lt; JSQ3[4:0] bits (3rd conversion in injected sequence) */
#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*! & lt; Bit 0 */
#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*! & lt; Bit 1 */
#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*! & lt; Bit 2 */
#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*! & lt; Bit 3 */
#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*! & lt; Bit 4 */
#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*! & lt; JSQ4[4:0] bits (4th conversion in injected sequence) */
#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*! & lt; Bit 0 */
#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*! & lt; Bit 1 */
#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*! & lt; Bit 2 */
#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*! & lt; Bit 3 */
#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*! & lt; Bit 4 */
#define ADC_JSQR_JL ((uint32_t)0x00300000) /*! & lt; JL[1:0] bits (Injected Sequence length) */
#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*! & lt; Bit 0 */
#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*! & lt; Bit 1 */

/******************* Bit definition for ADC_JDR1 register *******************/
#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*! & lt; Injected data */

/******************* Bit definition for ADC_JDR2 register *******************/
#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*! & lt; Injected data */

/******************* Bit definition for ADC_JDR3 register *******************/
#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*! & lt; Injected data */

/******************* Bit definition for ADC_JDR4 register *******************/
#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*! & lt; Injected data */

/******************** Bit definition for ADC_DR register ********************/
#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*! & lt; Regular data */
#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*! & lt; ADC2 data */

/******************* Bit definition for ADC_CSR register ********************/
#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*! & lt; ADC1 Analog watchdog flag */
#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*! & lt; ADC1 End of conversion */
#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*! & lt; ADC1 Injected channel end of conversion */
#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*! & lt; ADC1 Injected channel Start flag */
#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*! & lt; ADC1 Regular channel Start flag */
#define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*! & lt; ADC1 DMA overrun flag */
#define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*! & lt; ADC2 Analog watchdog flag */
#define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*! & lt; ADC2 End of conversion */
#define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*! & lt; ADC2 Injected channel end of conversion */
#define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*! & lt; ADC2 Injected channel Start flag */
#define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*! & lt; ADC2 Regular channel Start flag */
#define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*! & lt; ADC2 DMA overrun flag */
#define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*! & lt; ADC3 Analog watchdog flag */
#define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*! & lt; ADC3 End of conversion */
#define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*! & lt; ADC3 Injected channel end of conversion */
#define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*! & lt; ADC3 Injected channel Start flag */
#define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*! & lt; ADC3 Regular channel Start flag */
#define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*! & lt; ADC3 DMA overrun flag */

/******************* Bit definition for ADC_CCR register ********************/
#define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*! & lt; MULTI[4:0] bits (Multi-ADC mode selection) */
#define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*! & lt; Bit 0 */
#define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*! & lt; Bit 1 */
#define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*! & lt; Bit 2 */
#define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*! & lt; Bit 3 */
#define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*! & lt; Bit 4 */
#define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*! & lt; DELAY[3:0] bits (Delay between 2 sampling phases) */
#define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*! & lt; Bit 0 */
#define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*! & lt; Bit 1 */
#define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*! & lt; Bit 2 */
#define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*! & lt; Bit 3 */
#define ADC_CCR_DDS ((uint32_t)0x00002000) /*! & lt; DMA disable selection (Multi-ADC mode) */
#define ADC_CCR_DMA ((uint32_t)0x0000C000) /*! & lt; DMA[1:0] bits (Direct Memory Access mode for multimode) */
#define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*! & lt; Bit 0 */
#define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*! & lt; Bit 1 */
#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*! & lt; ADCPRE[1:0] bits (ADC prescaler) */
#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*! & lt; Bit 0 */
#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*! & lt; Bit 1 */
#define ADC_CCR_VBATE ((uint32_t)0x00400000) /*! & lt; VBAT Enable */
#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*! & lt; Temperature Sensor and VREFINT Enable */

/******************* Bit definition for ADC_CDR register ********************/
#define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*! & lt; 1st data of a pair of regular conversions */
#define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*! & lt; 2nd data of a pair of regular conversions */

/******************************************************************************/
/* */
/* Controller Area Network */
/* */
/******************************************************************************/
/*! & lt; CAN control and status registers */
/******************* Bit definition for CAN_MCR register ********************/
#define CAN_MCR_INRQ ((uint16_t)0x0001) /*! & lt; Initialization Request */
#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*! & lt; Sleep Mode Request */
#define CAN_MCR_TXFP ((uint16_t)0x0004) /*! & lt; Transmit FIFO Priority */
#define CAN_MCR_RFLM ((uint16_t)0x0008) /*! & lt; Receive FIFO Locked Mode */
#define CAN_MCR_NART ((uint16_t)0x0010) /*! & lt; No Automatic Retransmission */
#define CAN_MCR_AWUM ((uint16_t)0x0020) /*! & lt; Automatic Wakeup Mode */
#define CAN_MCR_ABOM ((uint16_t)0x0040) /*! & lt; Automatic Bus-Off Management */
#define CAN_MCR_TTCM ((uint16_t)0x0080) /*! & lt; Time Triggered Communication Mode */
#define CAN_MCR_RESET ((uint16_t)0x8000) /*! & lt; bxCAN software master reset */

/******************* Bit definition for CAN_MSR register ********************/
#define CAN_MSR_INAK ((uint16_t)0x0001) /*! & lt; Initialization Acknowledge */
#define CAN_MSR_SLAK ((uint16_t)0x0002) /*! & lt; Sleep Acknowledge */
#define CAN_MSR_ERRI ((uint16_t)0x0004) /*! & lt; Error Interrupt */
#define CAN_MSR_WKUI ((uint16_t)0x0008) /*! & lt; Wakeup Interrupt */
#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*! & lt; Sleep Acknowledge Interrupt */
#define CAN_MSR_TXM ((uint16_t)0x0100) /*! & lt; Transmit Mode */
#define CAN_MSR_RXM ((uint16_t)0x0200) /*! & lt; Receive Mode */
#define CAN_MSR_SAMP ((uint16_t)0x0400) /*! & lt; Last Sample Point */
#define CAN_MSR_RX ((uint16_t)0x0800) /*! & lt; CAN Rx Signal */

/******************* Bit definition for CAN_TSR register ********************/
#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*! & lt; Request Completed Mailbox0 */
#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*! & lt; Transmission OK of Mailbox0 */
#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*! & lt; Arbitration Lost for Mailbox0 */
#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*! & lt; Transmission Error of Mailbox0 */
#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*! & lt; Abort Request for Mailbox0 */
#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*! & lt; Request Completed Mailbox1 */
#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*! & lt; Transmission OK of Mailbox1 */
#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*! & lt; Arbitration Lost for Mailbox1 */
#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*! & lt; Transmission Error of Mailbox1 */
#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*! & lt; Abort Request for Mailbox 1 */
#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*! & lt; Request Completed Mailbox2 */
#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*! & lt; Transmission OK of Mailbox 2 */
#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*! & lt; Arbitration Lost for mailbox 2 */
#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*! & lt; Transmission Error of Mailbox 2 */
#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*! & lt; Abort Request for Mailbox 2 */
#define CAN_TSR_CODE ((uint32_t)0x03000000) /*! & lt; Mailbox Code */

#define CAN_TSR_TME ((uint32_t)0x1C000000) /*! & lt; TME[2:0] bits */
#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*! & lt; Transmit Mailbox 0 Empty */
#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*! & lt; Transmit Mailbox 1 Empty */
#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*! & lt; Transmit Mailbox 2 Empty */

#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*! & lt; LOW[2:0] bits */
#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*! & lt; Lowest Priority Flag for Mailbox 0 */
#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*! & lt; Lowest Priority Flag for Mailbox 1 */
#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*! & lt; Lowest Priority Flag for Mailbox 2 */

/******************* Bit definition for CAN_RF0R register *******************/
#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*! & lt; FIFO 0 Message Pending */
#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*! & lt; FIFO 0 Full */
#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*! & lt; FIFO 0 Overrun */
#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*! & lt; Release FIFO 0 Output Mailbox */

/******************* Bit definition for CAN_RF1R register *******************/
#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*! & lt; FIFO 1 Message Pending */
#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*! & lt; FIFO 1 Full */
#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*! & lt; FIFO 1 Overrun */
#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*! & lt; Release FIFO 1 Output Mailbox */

/******************** Bit definition for CAN_IER register *******************/
#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*! & lt; Transmit Mailbox Empty Interrupt Enable */
#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*! & lt; FIFO Message Pending Interrupt Enable */
#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*! & lt; FIFO Full Interrupt Enable */
#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*! & lt; FIFO Overrun Interrupt Enable */
#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*! & lt; FIFO Message Pending Interrupt Enable */
#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*! & lt; FIFO Full Interrupt Enable */
#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*! & lt; FIFO Overrun Interrupt Enable */
#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*! & lt; Error Warning Interrupt Enable */
#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*! & lt; Error Passive Interrupt Enable */
#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*! & lt; Bus-Off Interrupt Enable */
#define CAN_IER_LECIE ((uint32_t)0x00000800) /*! & lt; Last Error Code Interrupt Enable */
#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*! & lt; Error Interrupt Enable */
#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*! & lt; Wakeup Interrupt Enable */
#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*! & lt; Sleep Interrupt Enable */

/******************** Bit definition for CAN_ESR register *******************/
#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*! & lt; Error Warning Flag */
#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*! & lt; Error Passive Flag */
#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*! & lt; Bus-Off Flag */

#define CAN_ESR_LEC ((uint32_t)0x00000070) /*! & lt; LEC[2:0] bits (Last Error Code) */
#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*! & lt; Bit 0 */
#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*! & lt; Bit 1 */
#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*! & lt; Bit 2 */

#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*! & lt; Least significant byte of the 9-bit Transmit Error Counter */
#define CAN_ESR_REC ((uint32_t)0xFF000000) /*! & lt; Receive Error Counter */

/******************* Bit definition for CAN_BTR register ********************/
#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*! & lt; Baud Rate Prescaler */
#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*! & lt; Time Segment 1 */
#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*! & lt; Time Segment 2 */
#define CAN_BTR_SJW ((uint32_t)0x03000000) /*! & lt; Resynchronization Jump Width */
#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*! & lt; Loop Back Mode (Debug) */
#define CAN_BTR_SILM ((uint32_t)0x80000000) /*! & lt; Silent Mode */

/*! & lt; Mailbox registers */
/****************** Bit definition for CAN_TI0R register ********************/
#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*! & lt; Transmit Mailbox Request */
#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*! & lt; Remote Transmission Request */
#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*! & lt; Identifier Extension */
#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*! & lt; Extended Identifier */
#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*! & lt; Standard Identifier or Extended Identifier */

/****************** Bit definition for CAN_TDT0R register *******************/
#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*! & lt; Data Length Code */
#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*! & lt; Transmit Global Time */
#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*! & lt; Message Time Stamp */

/****************** Bit definition for CAN_TDL0R register *******************/
#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*! & lt; Data byte 0 */
#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*! & lt; Data byte 1 */
#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*! & lt; Data byte 2 */
#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*! & lt; Data byte 3 */

/****************** Bit definition for CAN_TDH0R register *******************/
#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*! & lt; Data byte 4 */
#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*! & lt; Data byte 5 */
#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*! & lt; Data byte 6 */
#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*! & lt; Data byte 7 */

/******************* Bit definition for CAN_TI1R register *******************/
#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*! & lt; Transmit Mailbox Request */
#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*! & lt; Remote Transmission Request */
#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*! & lt; Identifier Extension */
#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*! & lt; Extended Identifier */
#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*! & lt; Standard Identifier or Extended Identifier */

/******************* Bit definition for CAN_TDT1R register ******************/
#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*! & lt; Data Length Code */
#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*! & lt; Transmit Global Time */
#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*! & lt; Message Time Stamp */

/******************* Bit definition for CAN_TDL1R register ******************/
#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*! & lt; Data byte 0 */
#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*! & lt; Data byte 1 */
#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*! & lt; Data byte 2 */
#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*! & lt; Data byte 3 */

/******************* Bit definition for CAN_TDH1R register ******************/
#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*! & lt; Data byte 4 */
#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*! & lt; Data byte 5 */
#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*! & lt; Data byte 6 */
#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*! & lt; Data byte 7 */

/******************* Bit definition for CAN_TI2R register *******************/
#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*! & lt; Transmit Mailbox Request */
#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*! & lt; Remote Transmission Request */
#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*! & lt; Identifier Extension */
#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*! & lt; Extended identifier */
#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*! & lt; Standard Identifier or Extended Identifier */

/******************* Bit definition for CAN_TDT2R register ******************/
#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*! & lt; Data Length Code */
#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*! & lt; Transmit Global Time */
#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*! & lt; Message Time Stamp */

/******************* Bit definition for CAN_TDL2R register ******************/
#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*! & lt; Data byte 0 */
#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*! & lt; Data byte 1 */
#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*! & lt; Data byte 2 */
#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*! & lt; Data byte 3 */

/******************* Bit definition for CAN_TDH2R register ******************/
#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*! & lt; Data byte 4 */
#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*! & lt; Data byte 5 */
#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*! & lt; Data byte 6 */
#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*! & lt; Data byte 7 */

/******************* Bit definition for CAN_RI0R register *******************/
#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*! & lt; Remote Transmission Request */
#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*! & lt; Identifier Extension */
#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*! & lt; Extended Identifier */
#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*! & lt; Standard Identifier or Extended Identifier */

/******************* Bit definition for CAN_RDT0R register ******************/
#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*! & lt; Data Length Code */
#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*! & lt; Filter Match Index */
#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*! & lt; Message Time Stamp */

/******************* Bit definition for CAN_RDL0R register ******************/
#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*! & lt; Data byte 0 */
#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*! & lt; Data byte 1 */
#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*! & lt; Data byte 2 */
#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*! & lt; Data byte 3 */

/******************* Bit definition for CAN_RDH0R register ******************/
#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*! & lt; Data byte 4 */
#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*! & lt; Data byte 5 */
#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*! & lt; Data byte 6 */
#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*! & lt; Data byte 7 */

/******************* Bit definition for CAN_RI1R register *******************/
#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*! & lt; Remote Transmission Request */
#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*! & lt; Identifier Extension */
#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*! & lt; Extended identifier */
#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*! & lt; Standard Identifier or Extended Identifier */

/******************* Bit definition for CAN_RDT1R register ******************/
#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*! & lt; Data Length Code */
#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*! & lt; Filter Match Index */
#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*! & lt; Message Time Stamp */

/******************* Bit definition for CAN_RDL1R register ******************/
#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*! & lt; Data byte 0 */
#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*! & lt; Data byte 1 */
#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*! & lt; Data byte 2 */
#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*! & lt; Data byte 3 */

/******************* Bit definition for CAN_RDH1R register ******************/
#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*! & lt; Data byte 4 */
#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*! & lt; Data byte 5 */
#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*! & lt; Data byte 6 */
#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*! & lt; Data byte 7 */

/*! & lt; CAN filter registers */
/******************* Bit definition for CAN_FMR register ********************/
#define CAN_FMR_FINIT ((uint8_t)0x01) /*! & lt; Filter Init Mode */

/******************* Bit definition for CAN_FM1R register *******************/
#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*! & lt; Filter Mode */
#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*! & lt; Filter Init Mode bit 0 */
#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*! & lt; Filter Init Mode bit 1 */
#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*! & lt; Filter Init Mode bit 2 */
#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*! & lt; Filter Init Mode bit 3 */
#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*! & lt; Filter Init Mode bit 4 */
#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*! & lt; Filter Init Mode bit 5 */
#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*! & lt; Filter Init Mode bit 6 */
#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*! & lt; Filter Init Mode bit 7 */
#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*! & lt; Filter Init Mode bit 8 */
#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*! & lt; Filter Init Mode bit 9 */
#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*! & lt; Filter Init Mode bit 10 */
#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*! & lt; Filter Init Mode bit 11 */
#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*! & lt; Filter Init Mode bit 12 */
#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*! & lt; Filter Init Mode bit 13 */

/******************* Bit definition for CAN_FS1R register *******************/
#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*! & lt; Filter Scale Configuration */
#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*! & lt; Filter Scale Configuration bit 0 */
#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*! & lt; Filter Scale Configuration bit 1 */
#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*! & lt; Filter Scale Configuration bit 2 */
#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*! & lt; Filter Scale Configuration bit 3 */
#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*! & lt; Filter Scale Configuration bit 4 */
#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*! & lt; Filter Scale Configuration bit 5 */
#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*! & lt; Filter Scale Configuration bit 6 */
#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*! & lt; Filter Scale Configuration bit 7 */
#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*! & lt; Filter Scale Configuration bit 8 */
#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*! & lt; Filter Scale Configuration bit 9 */
#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*! & lt; Filter Scale Configuration bit 10 */
#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*! & lt; Filter Scale Configuration bit 11 */
#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*! & lt; Filter Scale Configuration bit 12 */
#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*! & lt; Filter Scale Configuration bit 13 */

/****************** Bit definition for CAN_FFA1R register *******************/
#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*! & lt; Filter FIFO Assignment */
#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*! & lt; Filter FIFO Assignment for Filter 0 */
#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*! & lt; Filter FIFO Assignment for Filter 1 */
#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*! & lt; Filter FIFO Assignment for Filter 2 */
#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*! & lt; Filter FIFO Assignment for Filter 3 */
#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*! & lt; Filter FIFO Assignment for Filter 4 */
#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*! & lt; Filter FIFO Assignment for Filter 5 */
#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*! & lt; Filter FIFO Assignment for Filter 6 */
#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*! & lt; Filter FIFO Assignment for Filter 7 */
#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*! & lt; Filter FIFO Assignment for Filter 8 */
#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*! & lt; Filter FIFO Assignment for Filter 9 */
#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*! & lt; Filter FIFO Assignment for Filter 10 */
#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*! & lt; Filter FIFO Assignment for Filter 11 */
#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*! & lt; Filter FIFO Assignment for Filter 12 */
#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*! & lt; Filter FIFO Assignment for Filter 13 */

/******************* Bit definition for CAN_FA1R register *******************/
#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*! & lt; Filter Active */
#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*! & lt; Filter 0 Active */
#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*! & lt; Filter 1 Active */
#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*! & lt; Filter 2 Active */
#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*! & lt; Filter 3 Active */
#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*! & lt; Filter 4 Active */
#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*! & lt; Filter 5 Active */
#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*! & lt; Filter 6 Active */
#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*! & lt; Filter 7 Active */
#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*! & lt; Filter 8 Active */
#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*! & lt; Filter 9 Active */
#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*! & lt; Filter 10 Active */
#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*! & lt; Filter 11 Active */
#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*! & lt; Filter 12 Active */
#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*! & lt; Filter 13 Active */

/******************* Bit definition for CAN_F0R1 register *******************/
#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*! & lt; Filter bit 0 */
#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*! & lt; Filter bit 1 */
#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*! & lt; Filter bit 2 */
#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*! & lt; Filter bit 3 */
#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*! & lt; Filter bit 4 */
#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*! & lt; Filter bit 5 */
#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*! & lt; Filter bit 6 */
#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*! & lt; Filter bit 7 */
#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*! & lt; Filter bit 8 */
#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*! & lt; Filter bit 9 */
#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*! & lt; Filter bit 10 */
#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*! & lt; Filter bit 11 */
#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*! & lt; Filter bit 12 */
#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*! & lt; Filter bit 13 */
#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*! & lt; Filter bit 14 */
#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*! & lt; Filter bit 15 */
#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*! & lt; Filter bit 16 */
#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*! & lt; Filter bit 17 */
#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*! & lt; Filter bit 18 */
#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*! & lt; Filter bit 19 */
#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*! & lt; Filter bit 20 */
#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*! & lt; Filter bit 21 */
#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*! & lt; Filter bit 22 */
#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*! & lt; Filter bit 23 */
#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*! & lt; Filter bit 24 */
#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*! & lt; Filter bit 25 */
#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*! & lt; Filter bit 26 */
#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*! & lt; Filter bit 27 */
#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*! & lt; Filter bit 28 */
#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*! & lt; Filter bit 29 */
#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*! & lt; Filter bit 30 */
#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*! & lt; Filter bit 31 */

/******************* Bit definition for CAN_F1R1 register *******************/
#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*! & lt; Filter bit 0 */
#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*! & lt; Filter bit 1 */
#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*! & lt; Filter bit 2 */
#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*! & lt; Filter bit 3 */
#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*! & lt; Filter bit 4 */
#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*! & lt; Filter bit 5 */
#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*! & lt; Filter bit 6 */
#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*! & lt; Filter bit 7 */
#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*! & lt; Filter bit 8 */
#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*! & lt; Filter bit 9 */
#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*! & lt; Filter bit 10 */
#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*! & lt; Filter bit 11 */
#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*! & lt; Filter bit 12 */
#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*! & lt; Filter bit 13 */
#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*! & lt; Filter bit 14 */
#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*! & lt; Filter bit 15 */
#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*! & lt; Filter bit 16 */
#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*! & lt; Filter bit 17 */
#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*! & lt; Filter bit 18 */
#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*! & lt; Filter bit 19 */
#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*! & lt; Filter bit 20 */
#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*! & lt; Filter bit 21 */
#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*! & lt; Filter bit 22 */
#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*! & lt; Filter bit 23 */
#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*! & lt; Filter bit 24 */
#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*! & lt; Filter bit 25 */
#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*! & lt; Filter bit 26 */
#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*! & lt; Filter bit 27 */
#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*! & lt; Filter bit 28 */
#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*! & lt; Filter bit 29 */
#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*! & lt; Filter bit 30 */
#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*! & lt; Filter bit 31 */

/******************* Bit definition for CAN_F2R1 register *******************/
#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*! & lt; Filter bit 0 */
#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*! & lt; Filter bit 1 */
#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*! & lt; Filter bit 2 */
#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*! & lt; Filter bit 3 */
#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*! & lt; Filter bit 4 */
#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*! & lt; Filter bit 5 */
#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*! & lt; Filter bit 6 */
#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*! & lt; Filter bit 7 */
#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*! & lt; Filter bit 8 */
#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*! & lt; Filter bit 9 */
#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*! & lt; Filter bit 10 */
#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*! & lt; Filter bit 11 */
#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*! & lt; Filter bit 12 */
#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*! & lt; Filter bit 13 */
#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*! & lt; Filter bit 14 */
#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*! & lt; Filter bit 15 */
#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*! & lt; Filter bit 16 */
#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*! & lt; Filter bit 17 */
#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*! & lt; Filter bit 18 */
#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*! & lt; Filter bit 19 */
#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*! & lt; Filter bit 20 */
#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*! & lt; Filter bit 21 */
#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*! & lt; Filter bit 22 */
#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*! & lt; Filter bit 23 */
#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*! & lt; Filter bit 24 */
#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*! & lt; Filter bit 25 */
#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*! & lt; Filter bit 26 */
#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*! & lt; Filter bit 27 */
#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*! & lt; Filter bit 28 */
#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*! & lt; Filter bit 29 */
#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*! & lt; Filter bit 30 */
#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*! & lt; Filter bit 31 */

/******************* Bit definition for CAN_F3R1 register *******************/
#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*! & lt; Filter bit 0 */
#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*! & lt; Filter bit 1 */
#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*! & lt; Filter bit 2 */
#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*! & lt; Filter bit 3 */
#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*! & lt; Filter bit 4 */
#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*! & lt; Filter bit 5 */
#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*! & lt; Filter bit 6 */
#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*! & lt; Filter bit 7 */
#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*! & lt; Filter bit 8 */
#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*! & lt; Filter bit 9 */
#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*! & lt; Filter bit 10 */
#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*! & lt; Filter bit 11 */
#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*! & lt; Filter bit 12 */
#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*! & lt; Filter bit 13 */
#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*! & lt; Filter bit 14 */
#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*! & lt; Filter bit 15 */
#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*! & lt; Filter bit 16 */
#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*! & lt; Filter bit 17 */
#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*! & lt; Filter bit 18 */
#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*! & lt; Filter bit 19 */
#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*! & lt; Filter bit 20 */
#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*! & lt; Filter bit 21 */
#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*! & lt; Filter bit 22 */
#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*! & lt; Filter bit 23 */
#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*! & lt; Filter bit 24 */
#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*! & lt; Filter bit 25 */
#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*! & lt; Filter bit 26 */
#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*! & lt; Filter bit 27 */
#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*! & lt; Filter bit 28 */
#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*! & lt; Filter bit 29 */
#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*! & lt; Filter bit 30 */
#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*! & lt; Filter bit 31 */

/******************* Bit definition for CAN_F4R1 register *******************/
#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*! & lt; Filter bit 0 */
#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*! & lt; Filter bit 1 */
#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*! & lt; Filter bit 2 */
#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*! & lt; Filter bit 3 */
#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*! & lt; Filter bit 4 */
#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*! & lt; Filter bit 5 */
#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*! & lt; Filter bit 6 */
#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*! & lt; Filter bit 7 */
#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*! & lt; Filter bit 8 */
#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*! & lt; Filter bit 9 */
#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*! & lt; Filter bit 10 */
#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*! & lt; Filter bit 11 */
#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*! & lt; Filter bit 12 */
#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*! & lt; Filter bit 13 */
#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*! & lt; Filter bit 14 */
#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*! & lt; Filter bit 15 */
#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*! & lt; Filter bit 16 */
#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*! & lt; Filter bit 17 */
#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*! & lt; Filter bit 18 */
#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*! & lt; Filter bit 19 */
#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*! & lt; Filter bit 20 */
#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*! & lt; Filter bit 21 */
#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*! & lt; Filter bit 22 */
#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*! & lt; Filter bit 23 */
#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*! & lt; Filter bit 24 */
#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*! & lt; Filter bit 25 */
#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*! & lt; Filter bit 26 */
#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*! & lt; Filter bit 27 */
#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*! & lt; Filter bit 28 */
#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*! & lt; Filter bit 29 */
#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*! & lt; Filter bit 30 */
#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*! & lt; Filter bit 31 */

/******************* Bit definition for CAN_F5R1 register *******************/
#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*! & lt; Filter bit 0 */
#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*! & lt; Filter bit 1 */
#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*! & lt; Filter bit 2 */
#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*! & lt; Filter bit 3 */
#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*! & lt; Filter bit 4 */
#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*! & lt; Filter bit 5 */
#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*! & lt; Filter bit 6 */
#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*! & lt; Filter bit 7 */
#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*! & lt; Filter bit 8 */
#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*! & lt; Filter bit 9 */
#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*! & lt; Filter bit 10 */
#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*! & lt; Filter bit 11 */
#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*! & lt; Filter bit 12 */
#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*! & lt; Filter bit 13 */
#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*! & lt; Filter bit 14 */
#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*! & lt; Filter bit 15 */
#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*! & lt; Filter bit 16 */
#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*! & lt; Filter bit 17 */
#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*! & lt; Filter bit 18 */
#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*! & lt; Filter bit 19 */
#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*! & lt; Filter bit 20 */
#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*! & lt; Filter bit 21 */
#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*! & lt; Filter bit 22 */
#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*! & lt; Filter bit 23 */
#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*! & lt; Filter bit 24 */
#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*! & lt; Filter bit 25 */
#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*! & lt; Filter bit 26 */
#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*! & lt; Filter bit 27 */
#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*! & lt; Filter bit 28 */
#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*! & lt; Filter bit 29 */
#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*! & lt; Filter bit 30 */
#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*! & lt; Filter bit 31 */

/******************* Bit definition for CAN_F6R1 register *******************/
#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*! & lt; Filter bit 0 */
#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*! & lt; Filter bit 1 */
#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*! & lt; Filter bit 2 */
#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*! & lt; Filter bit 3 */
#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*! & lt; Filter bit 4 */
#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*! & lt; Filter bit 5 */
#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*! & lt; Filter bit 6 */
#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*! & lt; Filter bit 7 */
#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*! & lt; Filter bit 8 */
#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*! & lt; Filter bit 9 */
#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*! & lt; Filter bit 10 */
#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*! & lt; Filter bit 11 */
#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*! & lt; Filter bit 12 */
#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*! & lt; Filter bit 13 */
#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*! & lt; Filter bit 14 */
#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*! & lt; Filter bit 15 */
#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*! & lt; Filter bit 16 */
#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*! & lt; Filter bit 17 */
#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*! & lt; Filter bit 18 */
#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*! & lt; Filter bit 19 */
#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*! & lt; Filter bit 20 */
#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*! & lt; Filter bit 21 */
#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*! & lt; Filter bit 22 */
#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*! & lt; Filter bit 23 */
#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*! & lt; Filter bit 24 */
#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*! & lt; Filter bit 25 */
#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*! & lt; Filter bit 26 */
#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*! & lt; Filter bit 27 */
#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*! & lt; Filter bit 28 */
#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*! & lt; Filter bit 29 */
#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*! & lt; Filter bit 30 */
#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*! & lt; Filter bit 31 */

/******************* Bit definition for CAN_F7R1 register *******************/
#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*! & lt; Filter bit 0 */
#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*! & lt; Filter bit 1 */
#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*! & lt; Filter bit 2 */
#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*! & lt; Filter bit 3 */
#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*! & lt; Filter bit 4 */
#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*! & lt; Filter bit 5 */
#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*! & lt; Filter bit 6 */
#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*! & lt; Filter bit 7 */
#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*! & lt; Filter bit 8 */
#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*! & lt; Filter bit 9 */
#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*! & lt; Filter bit 10 */
#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*! & lt; Filter bit 11 */
#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*! & lt; Filter bit 12 */
#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*! & lt; Filter bit 13 */
#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*! & lt; Filter bit 14 */
#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*! & lt; Filter bit 15 */
#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*! & lt; Filter bit 16 */
#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*! & lt; Filter bit 17 */
#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*! & lt; Filter bit 18 */
#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*! & lt; Filter bit 19 */
#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*! & lt; Filter bit 20 */
#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*! & lt; Filter bit 21 */
#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*! & lt; Filter bit 22 */
#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*! & lt; Filter bit 23 */
#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*! & lt; Filter bit 24 */
#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*! & lt; Filter bit 25 */
#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*! & lt; Filter bit 26 */
#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*! & lt; Filter bit 27 */
#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*! & lt; Filter bit 28 */
#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*! & lt; Filter bit 29 */
#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*! & lt; Filter bit 30 */
#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*! & lt; Filter bit 31 */

/******************* Bit definition for CAN_F8R1 register *******************/
#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*! & lt; Filter bit 0 */
#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*! & lt; Filter bit 1 */
#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*! & lt; Filter bit 2 */
#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*! & lt; Filter bit 3 */
#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*! & lt; Filter bit 4 */
#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*! & lt; Filter bit 5 */
#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*! & lt; Filter bit 6 */
#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*! & lt; Filter bit 7 */
#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*! & lt; Filter bit 8 */
#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*! & lt; Filter bit 9 */
#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*! & lt; Filter bit 10 */
#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*! & lt; Filter bit 11 */
#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*! & lt; Filter bit 12 */
#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*! & lt; Filter bit 13 */
#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*! & lt; Filter bit 14 */
#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*! & lt; Filter bit 15 */
#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*! & lt; Filter bit 16 */
#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*! & lt; Filter bit 17 */
#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*! & lt; Filter bit 18 */
#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*! & lt; Filter bit 19 */
#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*! & lt; Filter bit 20 */
#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*! & lt; Filter bit 21 */
#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*! & lt; Filter bit 22 */
#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*! & lt; Filter bit 23 */
#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*! & lt; Filter bit 24 */
#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*! & lt; Filter bit 25 */
#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*! & lt; Filter bit 26 */
#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*! & lt; Filter bit 27 */
#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*! & lt; Filter bit 28 */
#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*! & lt; Filter bit 29 */
#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*! & lt; Filter bit 30 */
#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*! & lt; Filter bit 31 */

/******************* Bit definition for CAN_F9R1 register *******************/
#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*! & lt; Filter bit 0 */
#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*! & lt; Filter bit 1 */
#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*! & lt; Filter bit 2 */
#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*! & lt; Filter bit 3 */
#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*! & lt; Filter bit 4 */
#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*! & lt; Filter bit 5 */
#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*! & lt; Filter bit 6 */
#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*! & lt; Filter bit 7 */
#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*! & lt; Filter bit 8 */
#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*! & lt; Filter bit 9 */
#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*! & lt; Filter bit 10 */
#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*! & lt; Filter bit 11 */
#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*! & lt; Filter bit 12 */
#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*! & lt; Filter bit 13 */
#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*! & lt; Filter bit 14 */
#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*! & lt; Filter bit 15 */
#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*! & lt; Filter bit 16 */
#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*! & lt; Filter bit 17 */
#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*! & lt; Filter bit 18 */
#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*! & lt; Filter bit 19 */
#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*! & lt; Filter bit 20 */
#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*! & lt; Filter bit 21 */
#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*! & lt; Filter bit 22 */
#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*! & lt; Filter bit 23 */
#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*! & lt; Filter bit 24 */
#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*! & lt; Filter bit 25 */
#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*! & lt; Filter bit 26 */
#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*! & lt; Filter bit 27 */
#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*! & lt; Filter bit 28 */
#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*! & lt; Filter bit 29 */
#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*! & lt; Filter bit 30 */
#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*! & lt; Filter bit 31 */

/******************* Bit definition for CAN_F10R1 register ******************/
#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*! & lt; Filter bit 0 */
#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*! & lt; Filter bit 1 */
#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*! & lt; Filter bit 2 */
#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*! & lt; Filter bit 3 */
#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*! & lt; Filter bit 4 */
#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*! & lt; Filter bit 5 */
#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*! & lt; Filter bit 6 */
#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*! & lt; Filter bit 7 */
#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*! & lt; Filter bit 8 */
#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*! & lt; Filter bit 9 */
#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*! & lt; Filter bit 10 */
#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*! & lt; Filter bit 11 */
#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*! & lt; Filter bit 12 */
#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*! & lt; Filter bit 13 */
#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*! & lt; Filter bit 14 */
#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*! & lt; Filter bit 15 */
#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*! & lt; Filter bit 16 */
#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*! & lt; Filter bit 17 */
#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*! & lt; Filter bit 18 */
#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*! & lt; Filter bit 19 */
#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*! & lt; Filter bit 20 */
#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*! & lt; Filter bit 21 */
#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*! & lt; Filter bit 22 */
#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*! & lt; Filter bit 23 */
#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*! & lt; Filter bit 24 */
#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*! & lt; Filter bit 25 */
#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*! & lt; Filter bit 26 */
#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*! & lt; Filter bit 27 */
#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*! & lt; Filter bit 28 */
#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*! & lt; Filter bit 29 */
#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*! & lt; Filter bit 30 */
#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*! & lt; Filter bit 31 */

/******************* Bit definition for CAN_F11R1 register ******************/
#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*! & lt; Filter bit 0 */
#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*! & lt; Filter bit 1 */
#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*! & lt; Filter bit 2 */
#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*! & lt; Filter bit 3 */
#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*! & lt; Filter bit 4 */
#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*! & lt; Filter bit 5 */
#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*! & lt; Filter bit 6 */
#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*! & lt; Filter bit 7 */
#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*! & lt; Filter bit 8 */
#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*! & lt; Filter bit 9 */
#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*! & lt; Filter bit 10 */
#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*! & lt; Filter bit 11 */
#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*! & lt; Filter bit 12 */
#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*! & lt; Filter bit 13 */
#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*! & lt; Filter bit 14 */
#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*! & lt; Filter bit 15 */
#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*! & lt; Filter bit 16 */
#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*! & lt; Filter bit 17 */
#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*! & lt; Filter bit 18 */
#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*! & lt; Filter bit 19 */
#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*! & lt; Filter bit 20 */
#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*! & lt; Filter bit 21 */
#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*! & lt; Filter bit 22 */
#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*! & lt; Filter bit 23 */
#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*! & lt; Filter bit 24 */
#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*! & lt; Filter bit 25 */
#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*! & lt; Filter bit 26 */
#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*! & lt; Filter bit 27 */
#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*! & lt; Filter bit 28 */
#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*! & lt; Filter bit 29 */
#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*! & lt; Filter bit 30 */
#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*! & lt; Filter bit 31 */

/******************* Bit definition for CAN_F12R1 register ******************/
#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*! & lt; Filter bit 0 */
#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*! & lt; Filter bit 1 */
#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*! & lt; Filter bit 2 */
#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*! & lt; Filter bit 3 */
#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*! & lt; Filter bit 4 */
#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*! & lt; Filter bit 5 */
#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*! & lt; Filter bit 6 */
#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*! & lt; Filter bit 7 */
#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*! & lt; Filter bit 8 */
#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*! & lt; Filter bit 9 */
#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*! & lt; Filter bit 10 */
#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*! & lt; Filter bit 11 */
#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*! & lt; Filter bit 12 */
#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*! & lt; Filter bit 13 */
#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*! & lt; Filter bit 14 */
#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*! & lt; Filter bit 15 */
#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*! & lt; Filter bit 16 */
#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*! & lt; Filter bit 17 */
#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*! & lt; Filter bit 18 */
#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*! & lt; Filter bit 19 */
#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*! & lt; Filter bit 20 */
#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*! & lt; Filter bit 21 */
#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*! & lt; Filter bit 22 */
#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*! & lt; Filter bit 23 */
#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*! & lt; Filter bit 24 */
#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*! & lt; Filter bit 25 */
#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*! & lt; Filter bit 26 */
#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*! & lt; Filter bit 27 */
#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*! & lt; Filter bit 28 */
#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*! & lt; Filter bit 29 */
#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*! & lt; Filter bit 30 */
#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*! & lt; Filter bit 31 */

/******************* Bit definition for CAN_F13R1 register ******************/
#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*! & lt; Filter bit 0 */
#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*! & lt; Filter bit 1 */
#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*! & lt; Filter bit 2 */
#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*! & lt; Filter bit 3 */
#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*! & lt; Filter bit 4 */
#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*! & lt; Filter bit 5 */
#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*! & lt; Filter bit 6 */
#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*! & lt; Filter bit 7 */
#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*! & lt; Filter bit 8 */
#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*! & lt; Filter bit 9 */
#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*! & lt; Filter bit 10 */
#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*! & lt; Filter bit 11 */
#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*! & lt; Filter bit 12 */
#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*! & lt; Filter bit 13 */
#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*! & lt; Filter bit 14 */
#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*! & lt; Filter bit 15 */
#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*! & lt; Filter bit 16 */
#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*! & lt; Filter bit 17 */
#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*! & lt; Filter bit 18 */
#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*! & lt; Filter bit 19 */
#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*! & lt; Filter bit 20 */
#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*! & lt; Filter bit 21 */
#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*! & lt; Filter bit 22 */
#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*! & lt; Filter bit 23 */
#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*! & lt; Filter bit 24 */
#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*! & lt; Filter bit 25 */
#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*! & lt; Filter bit 26 */
#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*! & lt; Filter bit 27 */
#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*! & lt; Filter bit 28 */
#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*! & lt; Filter bit 29 */
#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*! & lt; Filter bit 30 */
#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*! & lt; Filter bit 31 */

/******************* Bit definition for CAN_F0R2 register *******************/
#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*! & lt; Filter bit 0 */
#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*! & lt; Filter bit 1 */
#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*! & lt; Filter bit 2 */
#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*! & lt; Filter bit 3 */
#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*! & lt; Filter bit 4 */
#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*! & lt; Filter bit 5 */
#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*! & lt; Filter bit 6 */
#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*! & lt; Filter bit 7 */
#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*! & lt; Filter bit 8 */
#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*! & lt; Filter bit 9 */
#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*! & lt; Filter bit 10 */
#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*! & lt; Filter bit 11 */
#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*! & lt; Filter bit 12 */
#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*! & lt; Filter bit 13 */
#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*! & lt; Filter bit 14 */
#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*! & lt; Filter bit 15 */
#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*! & lt; Filter bit 16 */
#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*! & lt; Filter bit 17 */
#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*! & lt; Filter bit 18 */
#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*! & lt; Filter bit 19 */
#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*! & lt; Filter bit 20 */
#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*! & lt; Filter bit 21 */
#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*! & lt; Filter bit 22 */
#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*! & lt; Filter bit 23 */
#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*! & lt; Filter bit 24 */
#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*! & lt; Filter bit 25 */
#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*! & lt; Filter bit 26 */
#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*! & lt; Filter bit 27 */
#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*! & lt; Filter bit 28 */
#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*! & lt; Filter bit 29 */
#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*! & lt; Filter bit 30 */
#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*! & lt; Filter bit 31 */

/******************* Bit definition for CAN_F1R2 register *******************/
#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*! & lt; Filter bit 0 */
#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*! & lt; Filter bit 1 */
#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*! & lt; Filter bit 2 */
#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*! & lt; Filter bit 3 */
#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*! & lt; Filter bit 4 */
#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*! & lt; Filter bit 5 */
#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*! & lt; Filter bit 6 */
#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*! & lt; Filter bit 7 */
#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*! & lt; Filter bit 8 */
#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*! & lt; Filter bit 9 */
#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*! & lt; Filter bit 10 */
#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*! & lt; Filter bit 11 */
#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*! & lt; Filter bit 12 */
#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*! & lt; Filter bit 13 */
#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*! & lt; Filter bit 14 */
#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*! & lt; Filter bit 15 */
#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*! & lt; Filter bit 16 */
#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*! & lt; Filter bit 17 */
#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*! & lt; Filter bit 18 */
#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*! & lt; Filter bit 19 */
#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*! & lt; Filter bit 20 */
#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*! & lt; Filter bit 21 */
#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*! & lt; Filter bit 22 */
#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*! & lt; Filter bit 23 */
#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*! & lt; Filter bit 24 */
#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*! & lt; Filter bit 25 */
#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*! & lt; Filter bit 26 */
#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*! & lt; Filter bit 27 */
#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*! & lt; Filter bit 28 */
#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*! & lt; Filter bit 29 */
#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*! & lt; Filter bit 30 */
#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*! & lt; Filter bit 31 */

/******************* Bit definition for CAN_F2R2 register *******************/
#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*! & lt; Filter bit 0 */
#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*! & lt; Filter bit 1 */
#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*! & lt; Filter bit 2 */
#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*! & lt; Filter bit 3 */
#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*! & lt; Filter bit 4 */
#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*! & lt; Filter bit 5 */
#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*! & lt; Filter bit 6 */
#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*! & lt; Filter bit 7 */
#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*! & lt; Filter bit 8 */
#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*! & lt; Filter bit 9 */
#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*! & lt; Filter bit 10 */
#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*! & lt; Filter bit 11 */
#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*! & lt; Filter bit 12 */
#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*! & lt; Filter bit 13 */
#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*! & lt; Filter bit 14 */
#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*! & lt; Filter bit 15 */
#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*! & lt; Filter bit 16 */
#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*! & lt; Filter bit 17 */
#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*! & lt; Filter bit 18 */
#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*! & lt; Filter bit 19 */
#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*! & lt; Filter bit 20 */
#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*! & lt; Filter bit 21 */
#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*! & lt; Filter bit 22 */
#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*! & lt; Filter bit 23 */
#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*! & lt; Filter bit 24 */
#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*! & lt; Filter bit 25 */
#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*! & lt; Filter bit 26 */
#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*! & lt; Filter bit 27 */
#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*! & lt; Filter bit 28 */
#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*! & lt; Filter bit 29 */
#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*! & lt; Filter bit 30 */
#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*! & lt; Filter bit 31 */

/******************* Bit definition for CAN_F3R2 register *******************/
#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*! & lt; Filter bit 0 */
#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*! & lt; Filter bit 1 */
#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*! & lt; Filter bit 2 */
#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*! & lt; Filter bit 3 */
#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*! & lt; Filter bit 4 */
#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*! & lt; Filter bit 5 */
#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*! & lt; Filter bit 6 */
#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*! & lt; Filter bit 7 */
#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*! & lt; Filter bit 8 */
#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*! & lt; Filter bit 9 */
#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*! & lt; Filter bit 10 */
#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*! & lt; Filter bit 11 */
#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*! & lt; Filter bit 12 */
#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*! & lt; Filter bit 13 */
#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*! & lt; Filter bit 14 */
#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*! & lt; Filter bit 15 */
#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*! & lt; Filter bit 16 */
#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*! & lt; Filter bit 17 */
#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*! & lt; Filter bit 18 */
#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*! & lt; Filter bit 19 */
#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*! & lt; Filter bit 20 */
#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*! & lt; Filter bit 21 */
#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*! & lt; Filter bit 22 */
#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*! & lt; Filter bit 23 */
#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*! & lt; Filter bit 24 */
#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*! & lt; Filter bit 25 */
#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*! & lt; Filter bit 26 */
#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*! & lt; Filter bit 27 */
#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*! & lt; Filter bit 28 */
#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*! & lt; Filter bit 29 */
#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*! & lt; Filter bit 30 */
#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*! & lt; Filter bit 31 */

/******************* Bit definition for CAN_F4R2 register *******************/
#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*! & lt; Filter bit 0 */
#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*! & lt; Filter bit 1 */
#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*! & lt; Filter bit 2 */
#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*! & lt; Filter bit 3 */
#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*! & lt; Filter bit 4 */
#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*! & lt; Filter bit 5 */
#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*! & lt; Filter bit 6 */
#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*! & lt; Filter bit 7 */
#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*! & lt; Filter bit 8 */
#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*! & lt; Filter bit 9 */
#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*! & lt; Filter bit 10 */
#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*! & lt; Filter bit 11 */
#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*! & lt; Filter bit 12 */
#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*! & lt; Filter bit 13 */
#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*! & lt; Filter bit 14 */
#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*! & lt; Filter bit 15 */
#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*! & lt; Filter bit 16 */
#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*! & lt; Filter bit 17 */
#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*! & lt; Filter bit 18 */
#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*! & lt; Filter bit 19 */
#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*! & lt; Filter bit 20 */
#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*! & lt; Filter bit 21 */
#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*! & lt; Filter bit 22 */
#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*! & lt; Filter bit 23 */
#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*! & lt; Filter bit 24 */
#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*! & lt; Filter bit 25 */
#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*! & lt; Filter bit 26 */
#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*! & lt; Filter bit 27 */
#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*! & lt; Filter bit 28 */
#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*! & lt; Filter bit 29 */
#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*! & lt; Filter bit 30 */
#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*! & lt; Filter bit 31 */

/******************* Bit definition for CAN_F5R2 register *******************/
#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*! & lt; Filter bit 0 */
#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*! & lt; Filter bit 1 */
#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*! & lt; Filter bit 2 */
#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*! & lt; Filter bit 3 */
#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*! & lt; Filter bit 4 */
#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*! & lt; Filter bit 5 */
#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*! & lt; Filter bit 6 */
#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*! & lt; Filter bit 7 */
#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*! & lt; Filter bit 8 */
#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*! & lt; Filter bit 9 */
#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*! & lt; Filter bit 10 */
#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*! & lt; Filter bit 11 */
#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*! & lt; Filter bit 12 */
#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*! & lt; Filter bit 13 */
#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*! & lt; Filter bit 14 */
#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*! & lt; Filter bit 15 */
#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*! & lt; Filter bit 16 */
#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*! & lt; Filter bit 17 */
#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*! & lt; Filter bit 18 */
#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*! & lt; Filter bit 19 */
#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*! & lt; Filter bit 20 */
#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*! & lt; Filter bit 21 */
#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*! & lt; Filter bit 22 */
#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*! & lt; Filter bit 23 */
#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*! & lt; Filter bit 24 */
#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*! & lt; Filter bit 25 */
#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*! & lt; Filter bit 26 */
#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*! & lt; Filter bit 27 */
#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*! & lt; Filter bit 28 */
#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*! & lt; Filter bit 29 */
#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*! & lt; Filter bit 30 */
#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*! & lt; Filter bit 31 */

/******************* Bit definition for CAN_F6R2 register *******************/
#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*! & lt; Filter bit 0 */
#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*! & lt; Filter bit 1 */
#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*! & lt; Filter bit 2 */
#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*! & lt; Filter bit 3 */
#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*! & lt; Filter bit 4 */
#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*! & lt; Filter bit 5 */
#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*! & lt; Filter bit 6 */
#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*! & lt; Filter bit 7 */
#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*! & lt; Filter bit 8 */
#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*! & lt; Filter bit 9 */
#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*! & lt; Filter bit 10 */
#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*! & lt; Filter bit 11 */
#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*! & lt; Filter bit 12 */
#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*! & lt; Filter bit 13 */
#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*! & lt; Filter bit 14 */
#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*! & lt; Filter bit 15 */
#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*! & lt; Filter bit 16 */
#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*! & lt; Filter bit 17 */
#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*! & lt; Filter bit 18 */
#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*! & lt; Filter bit 19 */
#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*! & lt; Filter bit 20 */
#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*! & lt; Filter bit 21 */
#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*! & lt; Filter bit 22 */
#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*! & lt; Filter bit 23 */
#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*! & lt; Filter bit 24 */
#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*! & lt; Filter bit 25 */
#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*! & lt; Filter bit 26 */
#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*! & lt; Filter bit 27 */
#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*! & lt; Filter bit 28 */
#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*! & lt; Filter bit 29 */
#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*! & lt; Filter bit 30 */
#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*! & lt; Filter bit 31 */

/******************* Bit definition for CAN_F7R2 register *******************/
#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*! & lt; Filter bit 0 */
#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*! & lt; Filter bit 1 */
#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*! & lt; Filter bit 2 */
#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*! & lt; Filter bit 3 */
#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*! & lt; Filter bit 4 */
#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*! & lt; Filter bit 5 */
#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*! & lt; Filter bit 6 */
#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*! & lt; Filter bit 7 */
#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*! & lt; Filter bit 8 */
#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*! & lt; Filter bit 9 */
#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*! & lt; Filter bit 10 */
#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*! & lt; Filter bit 11 */
#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*! & lt; Filter bit 12 */
#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*! & lt; Filter bit 13 */
#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*! & lt; Filter bit 14 */
#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*! & lt; Filter bit 15 */
#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*! & lt; Filter bit 16 */
#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*! & lt; Filter bit 17 */
#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*! & lt; Filter bit 18 */
#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*! & lt; Filter bit 19 */
#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*! & lt; Filter bit 20 */
#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*! & lt; Filter bit 21 */
#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*! & lt; Filter bit 22 */
#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*! & lt; Filter bit 23 */
#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*! & lt; Filter bit 24 */
#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*! & lt; Filter bit 25 */
#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*! & lt; Filter bit 26 */
#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*! & lt; Filter bit 27 */
#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*! & lt; Filter bit 28 */
#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*! & lt; Filter bit 29 */
#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*! & lt; Filter bit 30 */
#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*! & lt; Filter bit 31 */

/******************* Bit definition for CAN_F8R2 register *******************/
#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*! & lt; Filter bit 0 */
#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*! & lt; Filter bit 1 */
#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*! & lt; Filter bit 2 */
#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*! & lt; Filter bit 3 */
#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*! & lt; Filter bit 4 */
#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*! & lt; Filter bit 5 */
#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*! & lt; Filter bit 6 */
#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*! & lt; Filter bit 7 */
#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*! & lt; Filter bit 8 */
#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*! & lt; Filter bit 9 */
#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*! & lt; Filter bit 10 */
#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*! & lt; Filter bit 11 */
#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*! & lt; Filter bit 12 */
#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*! & lt; Filter bit 13 */
#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*! & lt; Filter bit 14 */
#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*! & lt; Filter bit 15 */
#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*! & lt; Filter bit 16 */
#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*! & lt; Filter bit 17 */
#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*! & lt; Filter bit 18 */
#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*! & lt; Filter bit 19 */
#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*! & lt; Filter bit 20 */
#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*! & lt; Filter bit 21 */
#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*! & lt; Filter bit 22 */
#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*! & lt; Filter bit 23 */
#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*! & lt; Filter bit 24 */
#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*! & lt; Filter bit 25 */
#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*! & lt; Filter bit 26 */
#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*! & lt; Filter bit 27 */
#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*! & lt; Filter bit 28 */
#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*! & lt; Filter bit 29 */
#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*! & lt; Filter bit 30 */
#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*! & lt; Filter bit 31 */

/******************* Bit definition for CAN_F9R2 register *******************/
#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*! & lt; Filter bit 0 */
#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*! & lt; Filter bit 1 */
#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*! & lt; Filter bit 2 */
#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*! & lt; Filter bit 3 */
#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*! & lt; Filter bit 4 */
#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*! & lt; Filter bit 5 */
#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*! & lt; Filter bit 6 */
#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*! & lt; Filter bit 7 */
#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*! & lt; Filter bit 8 */
#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*! & lt; Filter bit 9 */
#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*! & lt; Filter bit 10 */
#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*! & lt; Filter bit 11 */
#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*! & lt; Filter bit 12 */
#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*! & lt; Filter bit 13 */
#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*! & lt; Filter bit 14 */
#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*! & lt; Filter bit 15 */
#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*! & lt; Filter bit 16 */
#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*! & lt; Filter bit 17 */
#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*! & lt; Filter bit 18 */
#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*! & lt; Filter bit 19 */
#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*! & lt; Filter bit 20 */
#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*! & lt; Filter bit 21 */
#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*! & lt; Filter bit 22 */
#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*! & lt; Filter bit 23 */
#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*! & lt; Filter bit 24 */
#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*! & lt; Filter bit 25 */
#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*! & lt; Filter bit 26 */
#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*! & lt; Filter bit 27 */
#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*! & lt; Filter bit 28 */
#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*! & lt; Filter bit 29 */
#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*! & lt; Filter bit 30 */
#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*! & lt; Filter bit 31 */

/******************* Bit definition for CAN_F10R2 register ******************/
#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*! & lt; Filter bit 0 */
#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*! & lt; Filter bit 1 */
#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*! & lt; Filter bit 2 */
#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*! & lt; Filter bit 3 */
#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*! & lt; Filter bit 4 */
#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*! & lt; Filter bit 5 */
#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*! & lt; Filter bit 6 */
#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*! & lt; Filter bit 7 */
#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*! & lt; Filter bit 8 */
#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*! & lt; Filter bit 9 */
#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*! & lt; Filter bit 10 */
#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*! & lt; Filter bit 11 */
#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*! & lt; Filter bit 12 */
#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*! & lt; Filter bit 13 */
#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*! & lt; Filter bit 14 */
#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*! & lt; Filter bit 15 */
#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*! & lt; Filter bit 16 */
#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*! & lt; Filter bit 17 */
#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*! & lt; Filter bit 18 */
#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*! & lt; Filter bit 19 */
#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*! & lt; Filter bit 20 */
#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*! & lt; Filter bit 21 */
#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*! & lt; Filter bit 22 */
#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*! & lt; Filter bit 23 */
#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*! & lt; Filter bit 24 */
#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*! & lt; Filter bit 25 */
#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*! & lt; Filter bit 26 */
#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*! & lt; Filter bit 27 */
#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*! & lt; Filter bit 28 */
#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*! & lt; Filter bit 29 */
#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*! & lt; Filter bit 30 */
#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*! & lt; Filter bit 31 */

/******************* Bit definition for CAN_F11R2 register ******************/
#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*! & lt; Filter bit 0 */
#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*! & lt; Filter bit 1 */
#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*! & lt; Filter bit 2 */
#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*! & lt; Filter bit 3 */
#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*! & lt; Filter bit 4 */
#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*! & lt; Filter bit 5 */
#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*! & lt; Filter bit 6 */
#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*! & lt; Filter bit 7 */
#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*! & lt; Filter bit 8 */
#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*! & lt; Filter bit 9 */
#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*! & lt; Filter bit 10 */
#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*! & lt; Filter bit 11 */
#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*! & lt; Filter bit 12 */
#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*! & lt; Filter bit 13 */
#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*! & lt; Filter bit 14 */
#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*! & lt; Filter bit 15 */
#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*! & lt; Filter bit 16 */
#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*! & lt; Filter bit 17 */
#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*! & lt; Filter bit 18 */
#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*! & lt; Filter bit 19 */
#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*! & lt; Filter bit 20 */
#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*! & lt; Filter bit 21 */
#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*! & lt; Filter bit 22 */
#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*! & lt; Filter bit 23 */
#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*! & lt; Filter bit 24 */
#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*! & lt; Filter bit 25 */
#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*! & lt; Filter bit 26 */
#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*! & lt; Filter bit 27 */
#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*! & lt; Filter bit 28 */
#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*! & lt; Filter bit 29 */
#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*! & lt; Filter bit 30 */
#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*! & lt; Filter bit 31 */

/******************* Bit definition for CAN_F12R2 register ******************/
#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*! & lt; Filter bit 0 */
#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*! & lt; Filter bit 1 */
#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*! & lt; Filter bit 2 */
#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*! & lt; Filter bit 3 */
#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*! & lt; Filter bit 4 */
#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*! & lt; Filter bit 5 */
#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*! & lt; Filter bit 6 */
#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*! & lt; Filter bit 7 */
#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*! & lt; Filter bit 8 */
#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*! & lt; Filter bit 9 */
#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*! & lt; Filter bit 10 */
#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*! & lt; Filter bit 11 */
#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*! & lt; Filter bit 12 */
#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*! & lt; Filter bit 13 */
#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*! & lt; Filter bit 14 */
#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*! & lt; Filter bit 15 */
#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*! & lt; Filter bit 16 */
#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*! & lt; Filter bit 17 */
#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*! & lt; Filter bit 18 */
#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*! & lt; Filter bit 19 */
#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*! & lt; Filter bit 20 */
#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*! & lt; Filter bit 21 */
#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*! & lt; Filter bit 22 */
#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*! & lt; Filter bit 23 */
#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*! & lt; Filter bit 24 */
#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*! & lt; Filter bit 25 */
#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*! & lt; Filter bit 26 */
#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*! & lt; Filter bit 27 */
#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*! & lt; Filter bit 28 */
#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*! & lt; Filter bit 29 */
#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*! & lt; Filter bit 30 */
#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*! & lt; Filter bit 31 */

/******************* Bit definition for CAN_F13R2 register ******************/
#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*! & lt; Filter bit 0 */
#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*! & lt; Filter bit 1 */
#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*! & lt; Filter bit 2 */
#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*! & lt; Filter bit 3 */
#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*! & lt; Filter bit 4 */
#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*! & lt; Filter bit 5 */
#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*! & lt; Filter bit 6 */
#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*! & lt; Filter bit 7 */
#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*! & lt; Filter bit 8 */
#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*! & lt; Filter bit 9 */
#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*! & lt; Filter bit 10 */
#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*! & lt; Filter bit 11 */
#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*! & lt; Filter bit 12 */
#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*! & lt; Filter bit 13 */
#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*! & lt; Filter bit 14 */
#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*! & lt; Filter bit 15 */
#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*! & lt; Filter bit 16 */
#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*! & lt; Filter bit 17 */
#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*! & lt; Filter bit 18 */
#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*! & lt; Filter bit 19 */
#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*! & lt; Filter bit 20 */
#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*! & lt; Filter bit 21 */
#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*! & lt; Filter bit 22 */
#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*! & lt; Filter bit 23 */
#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*! & lt; Filter bit 24 */
#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*! & lt; Filter bit 25 */
#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*! & lt; Filter bit 26 */
#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*! & lt; Filter bit 27 */
#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*! & lt; Filter bit 28 */
#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*! & lt; Filter bit 29 */
#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*! & lt; Filter bit 30 */
#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*! & lt; Filter bit 31 */

/******************************************************************************/
/* */
/* CRC calculation unit */
/* */
/******************************************************************************/
/******************* Bit definition for CRC_DR register *********************/
#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*! & lt; Data register bits */


/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR ((uint8_t)0xFF) /*! & lt; General-purpose 8-bit data register bits */


/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET ((uint8_t)0x01) /*! & lt; RESET bit */

/******************************************************************************/
/* */
/* Crypto Processor */
/* */
/******************************************************************************/
/******************* Bits definition for CRYP_CR register ********************/
#define CRYP_CR_ALGODIR ((uint32_t)0x00000004)

#define CRYP_CR_ALGOMODE ((uint32_t)0x00000038)
#define CRYP_CR_ALGOMODE_0 ((uint32_t)0x00000008)
#define CRYP_CR_ALGOMODE_1 ((uint32_t)0x00000010)
#define CRYP_CR_ALGOMODE_2 ((uint32_t)0x00000020)
#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
#define CRYP_CR_ALGOMODE_TDES_CBC ((uint32_t)0x00000008)
#define CRYP_CR_ALGOMODE_DES_ECB ((uint32_t)0x00000010)
#define CRYP_CR_ALGOMODE_DES_CBC ((uint32_t)0x00000018)
#define CRYP_CR_ALGOMODE_AES_ECB ((uint32_t)0x00000020)
#define CRYP_CR_ALGOMODE_AES_CBC ((uint32_t)0x00000028)
#define CRYP_CR_ALGOMODE_AES_CTR ((uint32_t)0x00000030)
#define CRYP_CR_ALGOMODE_AES_KEY ((uint32_t)0x00000038)

#define CRYP_CR_DATATYPE ((uint32_t)0x000000C0)
#define CRYP_CR_DATATYPE_0 ((uint32_t)0x00000040)
#define CRYP_CR_DATATYPE_1 ((uint32_t)0x00000080)
#define CRYP_CR_KEYSIZE ((uint32_t)0x00000300)
#define CRYP_CR_KEYSIZE_0 ((uint32_t)0x00000100)
#define CRYP_CR_KEYSIZE_1 ((uint32_t)0x00000200)
#define CRYP_CR_FFLUSH ((uint32_t)0x00004000)
#define CRYP_CR_CRYPEN ((uint32_t)0x00008000)
/****************** Bits definition for CRYP_SR register *********************/
#define CRYP_SR_IFEM ((uint32_t)0x00000001)
#define CRYP_SR_IFNF ((uint32_t)0x00000002)
#define CRYP_SR_OFNE ((uint32_t)0x00000004)
#define CRYP_SR_OFFU ((uint32_t)0x00000008)
#define CRYP_SR_BUSY ((uint32_t)0x00000010)
/****************** Bits definition for CRYP_DMACR register ******************/
#define CRYP_DMACR_DIEN ((uint32_t)0x00000001)
#define CRYP_DMACR_DOEN ((uint32_t)0x00000002)
/***************** Bits definition for CRYP_IMSCR register ******************/
#define CRYP_IMSCR_INIM ((uint32_t)0x00000001)
#define CRYP_IMSCR_OUTIM ((uint32_t)0x00000002)
/****************** Bits definition for CRYP_RISR register *******************/
#define CRYP_RISR_OUTRIS ((uint32_t)0x00000001)
#define CRYP_RISR_INRIS ((uint32_t)0x00000002)
/****************** Bits definition for CRYP_MISR register *******************/
#define CRYP_MISR_INMIS ((uint32_t)0x00000001)
#define CRYP_MISR_OUTMIS ((uint32_t)0x00000002)

/******************************************************************************/
/* */
/* Digital to Analog Converter */
/* */
/******************************************************************************/
/******************** Bit definition for DAC_CR register ********************/
#define DAC_CR_EN1 ((uint32_t)0x00000001) /*! & lt; DAC channel1 enable */
#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*! & lt; DAC channel1 output buffer disable */
#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*! & lt; DAC channel1 Trigger enable */

#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*! & lt; TSEL1[2:0] (DAC channel1 Trigger selection) */
#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*! & lt; Bit 0 */
#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*! & lt; Bit 1 */
#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*! & lt; Bit 2 */

#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*! & lt; WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*! & lt; Bit 0 */
#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*! & lt; Bit 1 */

#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*! & lt; MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*! & lt; Bit 0 */
#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*! & lt; Bit 1 */
#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*! & lt; Bit 2 */
#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*! & lt; Bit 3 */

#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*! & lt; DAC channel1 DMA enable */
#define DAC_CR_EN2 ((uint32_t)0x00010000) /*! & lt; DAC channel2 enable */
#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*! & lt; DAC channel2 output buffer disable */
#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*! & lt; DAC channel2 Trigger enable */

#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*! & lt; TSEL2[2:0] (DAC channel2 Trigger selection) */
#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*! & lt; Bit 0 */
#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*! & lt; Bit 1 */
#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*! & lt; Bit 2 */

#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*! & lt; WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*! & lt; Bit 0 */
#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*! & lt; Bit 1 */

#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*! & lt; MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*! & lt; Bit 0 */
#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*! & lt; Bit 1 */
#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*! & lt; Bit 2 */
#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*! & lt; Bit 3 */

#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*! & lt; DAC channel2 DMA enabled */

/***************** Bit definition for DAC_SWTRIGR register ******************/
#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*! & lt; DAC channel1 software trigger */
#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*! & lt; DAC channel2 software trigger */

/***************** Bit definition for DAC_DHR12R1 register ******************/
#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*! & lt; DAC channel1 12-bit Right aligned data */

/***************** Bit definition for DAC_DHR12L1 register ******************/
#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*! & lt; DAC channel1 12-bit Left aligned data */

/****************** Bit definition for DAC_DHR8R1 register ******************/
#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*! & lt; DAC channel1 8-bit Right aligned data */

/***************** Bit definition for DAC_DHR12R2 register ******************/
#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*! & lt; DAC channel2 12-bit Right aligned data */

/***************** Bit definition for DAC_DHR12L2 register ******************/
#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*! & lt; DAC channel2 12-bit Left aligned data */

/****************** Bit definition for DAC_DHR8R2 register ******************/
#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*! & lt; DAC channel2 8-bit Right aligned data */

/***************** Bit definition for DAC_DHR12RD register ******************/
#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*! & lt; DAC channel1 12-bit Right aligned data */
#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*! & lt; DAC channel2 12-bit Right aligned data */

/***************** Bit definition for DAC_DHR12LD register ******************/
#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*! & lt; DAC channel1 12-bit Left aligned data */
#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*! & lt; DAC channel2 12-bit Left aligned data */

/****************** Bit definition for DAC_DHR8RD register ******************/
#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*! & lt; DAC channel1 8-bit Right aligned data */
#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*! & lt; DAC channel2 8-bit Right aligned data */

/******************* Bit definition for DAC_DOR1 register *******************/
#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*! & lt; DAC channel1 data output */

/******************* Bit definition for DAC_DOR2 register *******************/
#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*! & lt; DAC channel2 data output */

/******************** Bit definition for DAC_SR register ********************/
#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*! & lt; DAC channel1 DMA underrun flag */
#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*! & lt; DAC channel2 DMA underrun flag */

/******************************************************************************/
/* */
/* Debug MCU */
/* */
/******************************************************************************/

/******************************************************************************/
/* */
/* DCMI */
/* */
/******************************************************************************/
/******************** Bits definition for DCMI_CR register ******************/
#define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
#define DCMI_CR_CM ((uint32_t)0x00000002)
#define DCMI_CR_CROP ((uint32_t)0x00000004)
#define DCMI_CR_JPEG ((uint32_t)0x00000008)
#define DCMI_CR_ESS ((uint32_t)0x00000010)
#define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
#define DCMI_CR_HSPOL ((uint32_t)0x00000040)
#define DCMI_CR_VSPOL ((uint32_t)0x00000080)
#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
#define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
#define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
#define DCMI_CR_CRE ((uint32_t)0x00001000)
#define DCMI_CR_ENABLE ((uint32_t)0x00004000)

/******************** Bits definition for DCMI_SR register ******************/
#define DCMI_SR_HSYNC ((uint32_t)0x00000001)
#define DCMI_SR_VSYNC ((uint32_t)0x00000002)
#define DCMI_SR_FNE ((uint32_t)0x00000004)

/******************** Bits definition for DCMI_RISR register ****************/
#define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
#define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
#define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
#define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
#define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)

/******************** Bits definition for DCMI_IER register *****************/
#define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
#define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
#define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
#define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
#define DCMI_IER_LINE_IE ((uint32_t)0x00000010)

/******************** Bits definition for DCMI_MISR register ****************/
#define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
#define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
#define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
#define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
#define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)

/******************** Bits definition for DCMI_ICR register *****************/
#define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
#define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
#define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
#define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
#define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)

/******************************************************************************/
/* */
/* DMA Controller */
/* */
/******************************************************************************/
/******************** Bits definition for DMA_SxCR register *****************/
#define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
#define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
#define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
#define DMA_SxCR_MBURST ((uint32_t)0x01800000)
#define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
#define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
#define DMA_SxCR_PBURST ((uint32_t)0x00600000)
#define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
#define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
#define DMA_SxCR_ACK ((uint32_t)0x00100000)
#define DMA_SxCR_CT ((uint32_t)0x00080000)
#define DMA_SxCR_DBM ((uint32_t)0x00040000)
#define DMA_SxCR_PL ((uint32_t)0x00030000)
#define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
#define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
#define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
#define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
#define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
#define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
#define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
#define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
#define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
#define DMA_SxCR_MINC ((uint32_t)0x00000400)
#define DMA_SxCR_PINC ((uint32_t)0x00000200)
#define DMA_SxCR_CIRC ((uint32_t)0x00000100)
#define DMA_SxCR_DIR ((uint32_t)0x000000C0)
#define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
#define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
#define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
#define DMA_SxCR_TCIE ((uint32_t)0x00000010)
#define DMA_SxCR_HTIE ((uint32_t)0x00000008)
#define DMA_SxCR_TEIE ((uint32_t)0x00000004)
#define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
#define DMA_SxCR_EN ((uint32_t)0x00000001)

/******************** Bits definition for DMA_SxCNDTR register **************/
#define DMA_SxNDT ((uint32_t)0x0000FFFF)
#define DMA_SxNDT_0 ((uint32_t)0x00000001)
#define DMA_SxNDT_1 ((uint32_t)0x00000002)
#define DMA_SxNDT_2 ((uint32_t)0x00000004)
#define DMA_SxNDT_3 ((uint32_t)0x00000008)
#define DMA_SxNDT_4 ((uint32_t)0x00000010)
#define DMA_SxNDT_5 ((uint32_t)0x00000020)
#define DMA_SxNDT_6 ((uint32_t)0x00000040)
#define DMA_SxNDT_7 ((uint32_t)0x00000080)
#define DMA_SxNDT_8 ((uint32_t)0x00000100)
#define DMA_SxNDT_9 ((uint32_t)0x00000200)
#define DMA_SxNDT_10 ((uint32_t)0x00000400)
#define DMA_SxNDT_11 ((uint32_t)0x00000800)
#define DMA_SxNDT_12 ((uint32_t)0x00001000)
#define DMA_SxNDT_13 ((uint32_t)0x00002000)
#define DMA_SxNDT_14 ((uint32_t)0x00004000)
#define DMA_SxNDT_15 ((uint32_t)0x00008000)

/******************** Bits definition for DMA_SxFCR register ****************/
#define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
#define DMA_SxFCR_FS ((uint32_t)0x00000038)
#define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
#define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
#define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
#define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
#define DMA_SxFCR_FTH ((uint32_t)0x00000003)
#define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
#define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)

/******************** Bits definition for DMA_LISR register *****************/
#define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
#define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
#define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
#define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
#define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
#define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
#define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
#define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
#define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
#define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
#define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
#define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
#define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
#define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
#define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
#define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
#define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
#define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
#define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
#define DMA_LISR_FEIF0 ((uint32_t)0x00000001)

/******************** Bits definition for DMA_HISR register *****************/
#define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
#define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
#define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
#define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
#define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
#define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
#define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
#define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
#define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
#define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
#define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
#define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
#define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
#define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
#define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
#define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
#define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
#define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
#define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
#define DMA_HISR_FEIF4 ((uint32_t)0x00000001)

/******************** Bits definition for DMA_LIFCR register ****************/
#define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
#define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
#define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
#define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
#define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
#define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
#define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
#define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
#define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
#define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
#define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
#define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
#define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
#define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
#define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
#define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
#define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
#define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
#define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
#define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)

/******************** Bits definition for DMA_HIFCR register ****************/
#define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
#define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
#define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
#define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
#define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
#define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
#define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
#define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
#define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
#define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
#define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
#define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
#define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
#define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
#define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
#define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
#define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
#define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
#define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
#define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)

/******************************************************************************/
/* */
/* External Interrupt/Event Controller */
/* */
/******************************************************************************/
/******************* Bit definition for EXTI_IMR register *******************/
#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*! & lt; Interrupt Mask on line 0 */
#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*! & lt; Interrupt Mask on line 1 */
#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*! & lt; Interrupt Mask on line 2 */
#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*! & lt; Interrupt Mask on line 3 */
#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*! & lt; Interrupt Mask on line 4 */
#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*! & lt; Interrupt Mask on line 5 */
#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*! & lt; Interrupt Mask on line 6 */
#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*! & lt; Interrupt Mask on line 7 */
#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*! & lt; Interrupt Mask on line 8 */
#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*! & lt; Interrupt Mask on line 9 */
#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*! & lt; Interrupt Mask on line 10 */
#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*! & lt; Interrupt Mask on line 11 */
#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*! & lt; Interrupt Mask on line 12 */
#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*! & lt; Interrupt Mask on line 13 */
#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*! & lt; Interrupt Mask on line 14 */
#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*! & lt; Interrupt Mask on line 15 */
#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*! & lt; Interrupt Mask on line 16 */
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*! & lt; Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*! & lt; Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*! & lt; Interrupt Mask on line 19 */

/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*! & lt; Event Mask on line 0 */
#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*! & lt; Event Mask on line 1 */
#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*! & lt; Event Mask on line 2 */
#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*! & lt; Event Mask on line 3 */
#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*! & lt; Event Mask on line 4 */
#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*! & lt; Event Mask on line 5 */
#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*! & lt; Event Mask on line 6 */
#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*! & lt; Event Mask on line 7 */
#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*! & lt; Event Mask on line 8 */
#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*! & lt; Event Mask on line 9 */
#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*! & lt; Event Mask on line 10 */
#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*! & lt; Event Mask on line 11 */
#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*! & lt; Event Mask on line 12 */
#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*! & lt; Event Mask on line 13 */
#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*! & lt; Event Mask on line 14 */
#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*! & lt; Event Mask on line 15 */
#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*! & lt; Event Mask on line 16 */
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*! & lt; Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*! & lt; Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*! & lt; Event Mask on line 19 */

/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*! & lt; Rising trigger event configuration bit of line 0 */
#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*! & lt; Rising trigger event configuration bit of line 1 */
#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*! & lt; Rising trigger event configuration bit of line 2 */
#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*! & lt; Rising trigger event configuration bit of line 3 */
#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*! & lt; Rising trigger event configuration bit of line 4 */
#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*! & lt; Rising trigger event configuration bit of line 5 */
#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*! & lt; Rising trigger event configuration bit of line 6 */
#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*! & lt; Rising trigger event configuration bit of line 7 */
#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*! & lt; Rising trigger event configuration bit of line 8 */
#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*! & lt; Rising trigger event configuration bit of line 9 */
#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*! & lt; Rising trigger event configuration bit of line 10 */
#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*! & lt; Rising trigger event configuration bit of line 11 */
#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*! & lt; Rising trigger event configuration bit of line 12 */
#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*! & lt; Rising trigger event configuration bit of line 13 */
#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*! & lt; Rising trigger event configuration bit of line 14 */
#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*! & lt; Rising trigger event configuration bit of line 15 */
#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*! & lt; Rising trigger event configuration bit of line 16 */
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*! & lt; Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*! & lt; Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*! & lt; Rising trigger event configuration bit of line 19 */

/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*! & lt; Falling trigger event configuration bit of line 0 */
#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*! & lt; Falling trigger event configuration bit of line 1 */
#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*! & lt; Falling trigger event configuration bit of line 2 */
#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*! & lt; Falling trigger event configuration bit of line 3 */
#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*! & lt; Falling trigger event configuration bit of line 4 */
#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*! & lt; Falling trigger event configuration bit of line 5 */
#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*! & lt; Falling trigger event configuration bit of line 6 */
#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*! & lt; Falling trigger event configuration bit of line 7 */
#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*! & lt; Falling trigger event configuration bit of line 8 */
#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*! & lt; Falling trigger event configuration bit of line 9 */
#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*! & lt; Falling trigger event configuration bit of line 10 */
#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*! & lt; Falling trigger event configuration bit of line 11 */
#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*! & lt; Falling trigger event configuration bit of line 12 */
#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*! & lt; Falling trigger event configuration bit of line 13 */
#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*! & lt; Falling trigger event configuration bit of line 14 */
#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*! & lt; Falling trigger event configuration bit of line 15 */
#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*! & lt; Falling trigger event configuration bit of line 16 */
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*! & lt; Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*! & lt; Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*! & lt; Falling trigger event configuration bit of line 19 */

/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*! & lt; Software Interrupt on line 0 */
#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*! & lt; Software Interrupt on line 1 */
#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*! & lt; Software Interrupt on line 2 */
#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*! & lt; Software Interrupt on line 3 */
#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*! & lt; Software Interrupt on line 4 */
#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*! & lt; Software Interrupt on line 5 */
#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*! & lt; Software Interrupt on line 6 */
#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*! & lt; Software Interrupt on line 7 */
#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*! & lt; Software Interrupt on line 8 */
#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*! & lt; Software Interrupt on line 9 */
#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*! & lt; Software Interrupt on line 10 */
#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*! & lt; Software Interrupt on line 11 */
#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*! & lt; Software Interrupt on line 12 */
#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*! & lt; Software Interrupt on line 13 */
#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*! & lt; Software Interrupt on line 14 */
#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*! & lt; Software Interrupt on line 15 */
#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*! & lt; Software Interrupt on line 16 */
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*! & lt; Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*! & lt; Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*! & lt; Software Interrupt on line 19 */

/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*! & lt; Pending bit for line 0 */
#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*! & lt; Pending bit for line 1 */
#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*! & lt; Pending bit for line 2 */
#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*! & lt; Pending bit for line 3 */
#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*! & lt; Pending bit for line 4 */
#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*! & lt; Pending bit for line 5 */
#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*! & lt; Pending bit for line 6 */
#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*! & lt; Pending bit for line 7 */
#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*! & lt; Pending bit for line 8 */
#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*! & lt; Pending bit for line 9 */
#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*! & lt; Pending bit for line 10 */
#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*! & lt; Pending bit for line 11 */
#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*! & lt; Pending bit for line 12 */
#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*! & lt; Pending bit for line 13 */
#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*! & lt; Pending bit for line 14 */
#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*! & lt; Pending bit for line 15 */
#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*! & lt; Pending bit for line 16 */
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*! & lt; Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*! & lt; Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*! & lt; Pending bit for line 19 */

/******************************************************************************/
/* */
/* FLASH */
/* */
/******************************************************************************/
/******************* Bits definition for FLASH_ACR register *****************/
#define FLASH_ACR_LATENCY ((uint32_t)0x00000007)
#define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
#define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
#define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
#define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
#define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
#define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
#define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
#define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)

#define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
#define FLASH_ACR_ICEN ((uint32_t)0x00000200)
#define FLASH_ACR_DCEN ((uint32_t)0x00000400)
#define FLASH_ACR_ICRST ((uint32_t)0x00000800)
#define FLASH_ACR_DCRST ((uint32_t)0x00001000)
#define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
#define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)

/******************* Bits definition for FLASH_SR register ******************/
#define FLASH_SR_EOP ((uint32_t)0x00000001)
#define FLASH_SR_SOP ((uint32_t)0x00000002)
#define FLASH_SR_WRPERR ((uint32_t)0x00000010)
#define FLASH_SR_PGAERR ((uint32_t)0x00000020)
#define FLASH_SR_PGPERR ((uint32_t)0x00000040)
#define FLASH_SR_PGSERR ((uint32_t)0x00000080)
#define FLASH_SR_BSY ((uint32_t)0x00010000)

/******************* Bits definition for FLASH_CR register ******************/
#define FLASH_CR_PG ((uint32_t)0x00000001)
#define FLASH_CR_SER ((uint32_t)0x00000002)
#define FLASH_CR_MER ((uint32_t)0x00000004)
#define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
#define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
#define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
#define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
#define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
#define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
#define FLASH_CR_STRT ((uint32_t)0x00010000)
#define FLASH_CR_EOPIE ((uint32_t)0x01000000)
#define FLASH_CR_LOCK ((uint32_t)0x80000000)

/******************* Bits definition for FLASH_OPTCR register ***************/
#define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
#define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
#define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
#define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
#define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
#define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
#define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
#define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
#define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
#define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
#define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
#define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
#define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
#define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
#define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
#define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
#define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
#define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
#define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
#define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
#define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
#define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
#define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
#define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
#define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
#define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
#define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
#define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)

/******************************************************************************/
/* */
/* Flexible Static Memory Controller */
/* */
/******************************************************************************/
/****************** Bit definition for FSMC_BCR1 register *******************/
#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*! & lt; Memory bank enable bit */
#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*! & lt; Address/data multiplexing enable bit */

#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*! & lt; MTYP[1:0] bits (Memory type) */
#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*! & lt; Bit 0 */
#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*! & lt; Bit 1 */

#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*! & lt; MWID[1:0] bits (Memory data bus width) */
#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*! & lt; Bit 0 */
#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*! & lt; Bit 1 */

#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*! & lt; Flash access enable */
#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*! & lt; Burst enable bit */
#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*! & lt; Wait signal polarity bit */
#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*! & lt; Wrapped burst mode support */
#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*! & lt; Wait timing configuration */
#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*! & lt; Write enable bit */
#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*! & lt; Wait enable bit */
#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*! & lt; Extended mode enable */
#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*! & lt; Asynchronous wait */
#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*! & lt; Write burst enable */

/****************** Bit definition for FSMC_BCR2 register *******************/
#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*! & lt; Memory bank enable bit */
#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*! & lt; Address/data multiplexing enable bit */

#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*! & lt; MTYP[1:0] bits (Memory type) */
#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*! & lt; Bit 0 */
#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*! & lt; Bit 1 */

#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*! & lt; MWID[1:0] bits (Memory data bus width) */
#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*! & lt; Bit 0 */
#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*! & lt; Bit 1 */

#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*! & lt; Flash access enable */
#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*! & lt; Burst enable bit */
#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*! & lt; Wait signal polarity bit */
#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*! & lt; Wrapped burst mode support */
#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*! & lt; Wait timing configuration */
#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*! & lt; Write enable bit */
#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*! & lt; Wait enable bit */
#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*! & lt; Extended mode enable */
#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*! & lt; Asynchronous wait */
#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*! & lt; Write burst enable */

/****************** Bit definition for FSMC_BCR3 register *******************/
#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*! & lt; Memory bank enable bit */
#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*! & lt; Address/data multiplexing enable bit */

#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*! & lt; MTYP[1:0] bits (Memory type) */
#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*! & lt; Bit 0 */
#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*! & lt; Bit 1 */

#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*! & lt; MWID[1:0] bits (Memory data bus width) */
#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*! & lt; Bit 0 */
#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*! & lt; Bit 1 */

#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*! & lt; Flash access enable */
#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*! & lt; Burst enable bit */
#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*! & lt; Wait signal polarity bit. */
#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*! & lt; Wrapped burst mode support */
#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*! & lt; Wait timing configuration */
#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*! & lt; Write enable bit */
#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*! & lt; Wait enable bit */
#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*! & lt; Extended mode enable */
#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*! & lt; Asynchronous wait */
#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*! & lt; Write burst enable */

/****************** Bit definition for FSMC_BCR4 register *******************/
#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*! & lt; Memory bank enable bit */
#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*! & lt; Address/data multiplexing enable bit */

#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*! & lt; MTYP[1:0] bits (Memory type) */
#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*! & lt; Bit 0 */
#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*! & lt; Bit 1 */

#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*! & lt; MWID[1:0] bits (Memory data bus width) */
#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*! & lt; Bit 0 */
#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*! & lt; Bit 1 */

#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*! & lt; Flash access enable */
#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*! & lt; Burst enable bit */
#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*! & lt; Wait signal polarity bit */
#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*! & lt; Wrapped burst mode support */
#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*! & lt; Wait timing configuration */
#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*! & lt; Write enable bit */
#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*! & lt; Wait enable bit */
#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*! & lt; Extended mode enable */
#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*! & lt; Asynchronous wait */
#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*! & lt; Write burst enable */

/****************** Bit definition for FSMC_BTR1 register ******************/
#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*! & lt; ADDSET[3:0] bits (Address setup phase duration) */
#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*! & lt; Bit 0 */
#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*! & lt; Bit 1 */
#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*! & lt; Bit 2 */
#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*! & lt; Bit 3 */

#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*! & lt; ADDHLD[3:0] bits (Address-hold phase duration) */
#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*! & lt; Bit 0 */
#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*! & lt; Bit 1 */
#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*! & lt; Bit 2 */
#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*! & lt; Bit 3 */

#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*! & lt; DATAST [3:0] bits (Data-phase duration) */
#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*! & lt; Bit 0 */
#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*! & lt; Bit 1 */
#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*! & lt; Bit 2 */
#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*! & lt; Bit 3 */

#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*! & lt; BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*! & lt; Bit 0 */
#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*! & lt; Bit 1 */
#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*! & lt; Bit 2 */
#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*! & lt; Bit 3 */

#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*! & lt; CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*! & lt; Bit 0 */
#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*! & lt; Bit 1 */
#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*! & lt; Bit 2 */
#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*! & lt; Bit 3 */

#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*! & lt; DATLA[3:0] bits (Data latency) */
#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*! & lt; Bit 0 */
#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*! & lt; Bit 1 */
#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*! & lt; Bit 2 */
#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*! & lt; Bit 3 */

#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*! & lt; ACCMOD[1:0] bits (Access mode) */
#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*! & lt; Bit 0 */
#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*! & lt; Bit 1 */

/****************** Bit definition for FSMC_BTR2 register *******************/
#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*! & lt; ADDSET[3:0] bits (Address setup phase duration) */
#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*! & lt; Bit 0 */
#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*! & lt; Bit 1 */
#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*! & lt; Bit 2 */
#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*! & lt; Bit 3 */

#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*! & lt; ADDHLD[3:0] bits (Address-hold phase duration) */
#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*! & lt; Bit 0 */
#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*! & lt; Bit 1 */
#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*! & lt; Bit 2 */
#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*! & lt; Bit 3 */

#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*! & lt; DATAST [3:0] bits (Data-phase duration) */
#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*! & lt; Bit 0 */
#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*! & lt; Bit 1 */
#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*! & lt; Bit 2 */
#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*! & lt; Bit 3 */

#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*! & lt; BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*! & lt; Bit 0 */
#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*! & lt; Bit 1 */
#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*! & lt; Bit 2 */
#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*! & lt; Bit 3 */

#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*! & lt; CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*! & lt; Bit 0 */
#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*! & lt; Bit 1 */
#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*! & lt; Bit 2 */
#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*! & lt; Bit 3 */

#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*! & lt; DATLA[3:0] bits (Data latency) */
#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*! & lt; Bit 0 */
#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*! & lt; Bit 1 */
#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*! & lt; Bit 2 */
#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*! & lt; Bit 3 */

#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*! & lt; ACCMOD[1:0] bits (Access mode) */
#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*! & lt; Bit 0 */
#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*! & lt; Bit 1 */

/******************* Bit definition for FSMC_BTR3 register *******************/
#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*! & lt; ADDSET[3:0] bits (Address setup phase duration) */
#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*! & lt; Bit 0 */
#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*! & lt; Bit 1 */
#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*! & lt; Bit 2 */
#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*! & lt; Bit 3 */

#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*! & lt; ADDHLD[3:0] bits (Address-hold phase duration) */
#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*! & lt; Bit 0 */
#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*! & lt; Bit 1 */
#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*! & lt; Bit 2 */
#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*! & lt; Bit 3 */

#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*! & lt; DATAST [3:0] bits (Data-phase duration) */
#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*! & lt; Bit 0 */
#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*! & lt; Bit 1 */
#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*! & lt; Bit 2 */
#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*! & lt; Bit 3 */

#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*! & lt; BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*! & lt; Bit 0 */
#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*! & lt; Bit 1 */
#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*! & lt; Bit 2 */
#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*! & lt; Bit 3 */

#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*! & lt; CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*! & lt; Bit 0 */
#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*! & lt; Bit 1 */
#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*! & lt; Bit 2 */
#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*! & lt; Bit 3 */

#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*! & lt; DATLA[3:0] bits (Data latency) */
#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*! & lt; Bit 0 */
#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*! & lt; Bit 1 */
#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*! & lt; Bit 2 */
#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*! & lt; Bit 3 */

#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*! & lt; ACCMOD[1:0] bits (Access mode) */
#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*! & lt; Bit 0 */
#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*! & lt; Bit 1 */

/****************** Bit definition for FSMC_BTR4 register *******************/
#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*! & lt; ADDSET[3:0] bits (Address setup phase duration) */
#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*! & lt; Bit 0 */
#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*! & lt; Bit 1 */
#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*! & lt; Bit 2 */
#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*! & lt; Bit 3 */

#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*! & lt; ADDHLD[3:0] bits (Address-hold phase duration) */
#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*! & lt; Bit 0 */
#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*! & lt; Bit 1 */
#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*! & lt; Bit 2 */
#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*! & lt; Bit 3 */

#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*! & lt; DATAST [3:0] bits (Data-phase duration) */
#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*! & lt; Bit 0 */
#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*! & lt; Bit 1 */
#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*! & lt; Bit 2 */
#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*! & lt; Bit 3 */

#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*! & lt; BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*! & lt; Bit 0 */
#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*! & lt; Bit 1 */
#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*! & lt; Bit 2 */
#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*! & lt; Bit 3 */

#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*! & lt; CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*! & lt; Bit 0 */
#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*! & lt; Bit 1 */
#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*! & lt; Bit 2 */
#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*! & lt; Bit 3 */

#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*! & lt; DATLA[3:0] bits (Data latency) */
#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*! & lt; Bit 0 */
#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*! & lt; Bit 1 */
#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*! & lt; Bit 2 */
#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*! & lt; Bit 3 */

#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*! & lt; ACCMOD[1:0] bits (Access mode) */
#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*! & lt; Bit 0 */
#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*! & lt; Bit 1 */

/****************** Bit definition for FSMC_BWTR1 register ******************/
#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*! & lt; ADDSET[3:0] bits (Address setup phase duration) */
#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*! & lt; Bit 0 */
#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*! & lt; Bit 1 */
#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*! & lt; Bit 2 */
#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*! & lt; Bit 3 */

#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*! & lt; ADDHLD[3:0] bits (Address-hold phase duration) */
#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*! & lt; Bit 0 */
#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*! & lt; Bit 1 */
#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*! & lt; Bit 2 */
#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*! & lt; Bit 3 */

#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*! & lt; DATAST [3:0] bits (Data-phase duration) */
#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*! & lt; Bit 0 */
#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*! & lt; Bit 1 */
#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*! & lt; Bit 2 */
#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*! & lt; Bit 3 */

#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*! & lt; CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*! & lt; Bit 0 */
#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*! & lt; Bit 1 */
#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*! & lt; Bit 2 */
#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*! & lt; Bit 3 */

#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*! & lt; DATLA[3:0] bits (Data latency) */
#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*! & lt; Bit 0 */
#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*! & lt; Bit 1 */
#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*! & lt; Bit 2 */
#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*! & lt; Bit 3 */

#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*! & lt; ACCMOD[1:0] bits (Access mode) */
#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*! & lt; Bit 0 */
#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*! & lt; Bit 1 */

/****************** Bit definition for FSMC_BWTR2 register ******************/
#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*! & lt; ADDSET[3:0] bits (Address setup phase duration) */
#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*! & lt; Bit 0 */
#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*! & lt; Bit 1 */
#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*! & lt; Bit 2 */
#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*! & lt; Bit 3 */

#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*! & lt; ADDHLD[3:0] bits (Address-hold phase duration) */
#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*! & lt; Bit 0 */
#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*! & lt; Bit 1 */
#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*! & lt; Bit 2 */
#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*! & lt; Bit 3 */

#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*! & lt; DATAST [3:0] bits (Data-phase duration) */
#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*! & lt; Bit 0 */
#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*! & lt; Bit 1 */
#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*! & lt; Bit 2 */
#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*! & lt; Bit 3 */

#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*! & lt; CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*! & lt; Bit 0 */
#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*! & lt; Bit 1*/
#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*! & lt; Bit 2 */
#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*! & lt; Bit 3 */

#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*! & lt; DATLA[3:0] bits (Data latency) */
#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*! & lt; Bit 0 */
#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*! & lt; Bit 1 */
#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*! & lt; Bit 2 */
#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*! & lt; Bit 3 */

#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*! & lt; ACCMOD[1:0] bits (Access mode) */
#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*! & lt; Bit 0 */
#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*! & lt; Bit 1 */

/****************** Bit definition for FSMC_BWTR3 register ******************/
#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*! & lt; ADDSET[3:0] bits (Address setup phase duration) */
#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*! & lt; Bit 0 */
#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*! & lt; Bit 1 */
#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*! & lt; Bit 2 */
#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*! & lt; Bit 3 */

#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*! & lt; ADDHLD[3:0] bits (Address-hold phase duration) */
#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*! & lt; Bit 0 */
#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*! & lt; Bit 1 */
#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*! & lt; Bit 2 */
#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*! & lt; Bit 3 */

#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*! & lt; DATAST [3:0] bits (Data-phase duration) */
#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*! & lt; Bit 0 */
#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*! & lt; Bit 1 */
#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*! & lt; Bit 2 */
#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*! & lt; Bit 3 */

#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*! & lt; CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*! & lt; Bit 0 */
#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*! & lt; Bit 1 */
#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*! & lt; Bit 2 */
#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*! & lt; Bit 3 */

#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*! & lt; DATLA[3:0] bits (Data latency) */
#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*! & lt; Bit 0 */
#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*! & lt; Bit 1 */
#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*! & lt; Bit 2 */
#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*! & lt; Bit 3 */

#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*! & lt; ACCMOD[1:0] bits (Access mode) */
#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*! & lt; Bit 0 */
#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*! & lt; Bit 1 */

/****************** Bit definition for FSMC_BWTR4 register ******************/
#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*! & lt; ADDSET[3:0] bits (Address setup phase duration) */
#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*! & lt; Bit 0 */
#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*! & lt; Bit 1 */
#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*! & lt; Bit 2 */
#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*! & lt; Bit 3 */

#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*! & lt; ADDHLD[3:0] bits (Address-hold phase duration) */
#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*! & lt; Bit 0 */
#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*! & lt; Bit 1 */
#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*! & lt; Bit 2 */
#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*! & lt; Bit 3 */

#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*! & lt; DATAST [3:0] bits (Data-phase duration) */
#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*! & lt; Bit 0 */
#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*! & lt; Bit 1 */
#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*! & lt; Bit 2 */
#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*! & lt; Bit 3 */

#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*! & lt; CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*! & lt; Bit 0 */
#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*! & lt; Bit 1 */
#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*! & lt; Bit 2 */
#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*! & lt; Bit 3 */

#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*! & lt; DATLA[3:0] bits (Data latency) */
#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*! & lt; Bit 0 */
#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*! & lt; Bit 1 */
#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*! & lt; Bit 2 */
#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*! & lt; Bit 3 */

#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*! & lt; ACCMOD[1:0] bits (Access mode) */
#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*! & lt; Bit 0 */
#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*! & lt; Bit 1 */

/****************** Bit definition for FSMC_PCR2 register *******************/
#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*! & lt; Wait feature enable bit */
#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*! & lt; PC Card/NAND Flash memory bank enable bit */
#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*! & lt; Memory type */

#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*! & lt; PWID[1:0] bits (NAND Flash databus width) */
#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*! & lt; Bit 0 */
#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*! & lt; Bit 1 */

#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*! & lt; ECC computation logic enable bit */

#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*! & lt; TCLR[3:0] bits (CLE to RE delay) */
#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*! & lt; Bit 0 */
#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*! & lt; Bit 1 */
#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*! & lt; Bit 2 */
#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*! & lt; Bit 3 */

#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*! & lt; TAR[3:0] bits (ALE to RE delay) */
#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*! & lt; Bit 0 */
#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*! & lt; Bit 1 */
#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*! & lt; Bit 2 */
#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*! & lt; Bit 3 */

#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*! & lt; ECCPS[1:0] bits (ECC page size) */
#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*! & lt; Bit 0 */
#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*! & lt; Bit 1 */
#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*! & lt; Bit 2 */

/****************** Bit definition for FSMC_PCR3 register *******************/
#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*! & lt; Wait feature enable bit */
#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*! & lt; PC Card/NAND Flash memory bank enable bit */
#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*! & lt; Memory type */

#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*! & lt; PWID[1:0] bits (NAND Flash databus width) */
#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*! & lt; Bit 0 */
#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*! & lt; Bit 1 */

#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*! & lt; ECC computation logic enable bit */

#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*! & lt; TCLR[3:0] bits (CLE to RE delay) */
#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*! & lt; Bit 0 */
#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*! & lt; Bit 1 */
#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*! & lt; Bit 2 */
#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*! & lt; Bit 3 */

#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*! & lt; TAR[3:0] bits (ALE to RE delay) */
#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*! & lt; Bit 0 */
#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*! & lt; Bit 1 */
#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*! & lt; Bit 2 */
#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*! & lt; Bit 3 */

#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*! & lt; ECCPS[2:0] bits (ECC page size) */
#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*! & lt; Bit 0 */
#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*! & lt; Bit 1 */
#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*! & lt; Bit 2 */

/****************** Bit definition for FSMC_PCR4 register *******************/
#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*! & lt; Wait feature enable bit */
#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*! & lt; PC Card/NAND Flash memory bank enable bit */
#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*! & lt; Memory type */

#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*! & lt; PWID[1:0] bits (NAND Flash databus width) */
#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*! & lt; Bit 0 */
#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*! & lt; Bit 1 */

#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*! & lt; ECC computation logic enable bit */

#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*! & lt; TCLR[3:0] bits (CLE to RE delay) */
#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*! & lt; Bit 0 */
#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*! & lt; Bit 1 */
#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*! & lt; Bit 2 */
#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*! & lt; Bit 3 */

#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*! & lt; TAR[3:0] bits (ALE to RE delay) */
#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*! & lt; Bit 0 */
#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*! & lt; Bit 1 */
#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*! & lt; Bit 2 */
#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*! & lt; Bit 3 */

#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*! & lt; ECCPS[2:0] bits (ECC page size) */
#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*! & lt; Bit 0 */
#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*! & lt; Bit 1 */
#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*! & lt; Bit 2 */

/******************* Bit definition for FSMC_SR2 register *******************/
#define FSMC_SR2_IRS ((uint8_t)0x01) /*! & lt; Interrupt Rising Edge status */
#define FSMC_SR2_ILS ((uint8_t)0x02) /*! & lt; Interrupt Level status */
#define FSMC_SR2_IFS ((uint8_t)0x04) /*! & lt; Interrupt Falling Edge status */
#define FSMC_SR2_IREN ((uint8_t)0x08) /*! & lt; Interrupt Rising Edge detection Enable bit */
#define FSMC_SR2_ILEN ((uint8_t)0x10) /*! & lt; Interrupt Level detection Enable bit */
#define FSMC_SR2_IFEN ((uint8_t)0x20) /*! & lt; Interrupt Falling Edge detection Enable bit */
#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*! & lt; FIFO empty */

/******************* Bit definition for FSMC_SR3 register *******************/
#define FSMC_SR3_IRS ((uint8_t)0x01) /*! & lt; Interrupt Rising Edge status */
#define FSMC_SR3_ILS ((uint8_t)0x02) /*! & lt; Interrupt Level status */
#define FSMC_SR3_IFS ((uint8_t)0x04) /*! & lt; Interrupt Falling Edge status */
#define FSMC_SR3_IREN ((uint8_t)0x08) /*! & lt; Interrupt Rising Edge detection Enable bit */
#define FSMC_SR3_ILEN ((uint8_t)0x10) /*! & lt; Interrupt Level detection Enable bit */
#define FSMC_SR3_IFEN ((uint8_t)0x20) /*! & lt; Interrupt Falling Edge detection Enable bit */
#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*! & lt; FIFO empty */

/******************* Bit definition for FSMC_SR4 register *******************/
#define FSMC_SR4_IRS ((uint8_t)0x01) /*! & lt; Interrupt Rising Edge status */
#define FSMC_SR4_ILS ((uint8_t)0x02) /*! & lt; Interrupt Level status */
#define FSMC_SR4_IFS ((uint8_t)0x04) /*! & lt; Interrupt Falling Edge status */
#define FSMC_SR4_IREN ((uint8_t)0x08) /*! & lt; Interrupt Rising Edge detection Enable bit */
#define FSMC_SR4_ILEN ((uint8_t)0x10) /*! & lt; Interrupt Level detection Enable bit */
#define FSMC_SR4_IFEN ((uint8_t)0x20) /*! & lt; Interrupt Falling Edge detection Enable bit */
#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*! & lt; FIFO empty */

/****************** Bit definition for FSMC_PMEM2 register ******************/
#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*! & lt; MEMSET2[7:0] bits (Common memory 2 setup time) */
#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*! & lt; Bit 0 */
#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*! & lt; Bit 1 */
#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*! & lt; Bit 2 */
#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*! & lt; Bit 3 */
#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*! & lt; Bit 4 */
#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*! & lt; Bit 5 */
#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*! & lt; Bit 6 */
#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*! & lt; Bit 7 */

#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*! & lt; MEMWAIT2[7:0] bits (Common memory 2 wait time) */
#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*! & lt; Bit 0 */
#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*! & lt; Bit 1 */
#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*! & lt; Bit 2 */
#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*! & lt; Bit 3 */
#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*! & lt; Bit 4 */
#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*! & lt; Bit 5 */
#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*! & lt; Bit 6 */
#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*! & lt; Bit 7 */

#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*! & lt; MEMHOLD2[7:0] bits (Common memory 2 hold time) */
#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*! & lt; Bit 0 */
#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*! & lt; Bit 1 */
#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*! & lt; Bit 2 */
#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*! & lt; Bit 3 */
#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*! & lt; Bit 4 */
#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*! & lt; Bit 5 */
#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*! & lt; Bit 6 */
#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*! & lt; Bit 7 */

#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*! & lt; MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*! & lt; Bit 0 */
#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*! & lt; Bit 1 */
#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*! & lt; Bit 2 */
#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*! & lt; Bit 3 */
#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*! & lt; Bit 4 */
#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*! & lt; Bit 5 */
#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*! & lt; Bit 6 */
#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*! & lt; Bit 7 */

/****************** Bit definition for FSMC_PMEM3 register ******************/
#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*! & lt; MEMSET3[7:0] bits (Common memory 3 setup time) */
#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*! & lt; Bit 0 */
#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*! & lt; Bit 1 */
#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*! & lt; Bit 2 */
#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*! & lt; Bit 3 */
#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*! & lt; Bit 4 */
#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*! & lt; Bit 5 */
#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*! & lt; Bit 6 */
#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*! & lt; Bit 7 */

#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*! & lt; MEMWAIT3[7:0] bits (Common memory 3 wait time) */
#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*! & lt; Bit 0 */
#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*! & lt; Bit 1 */
#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*! & lt; Bit 2 */
#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*! & lt; Bit 3 */
#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*! & lt; Bit 4 */
#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*! & lt; Bit 5 */
#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*! & lt; Bit 6 */
#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*! & lt; Bit 7 */

#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*! & lt; MEMHOLD3[7:0] bits (Common memory 3 hold time) */
#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*! & lt; Bit 0 */
#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*! & lt; Bit 1 */
#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*! & lt; Bit 2 */
#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*! & lt; Bit 3 */
#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*! & lt; Bit 4 */
#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*! & lt; Bit 5 */
#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*! & lt; Bit 6 */
#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*! & lt; Bit 7 */

#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*! & lt; MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*! & lt; Bit 0 */
#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*! & lt; Bit 1 */
#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*! & lt; Bit 2 */
#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*! & lt; Bit 3 */
#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*! & lt; Bit 4 */
#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*! & lt; Bit 5 */
#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*! & lt; Bit 6 */
#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*! & lt; Bit 7 */

/****************** Bit definition for FSMC_PMEM4 register ******************/
#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*! & lt; MEMSET4[7:0] bits (Common memory 4 setup time) */
#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*! & lt; Bit 0 */
#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*! & lt; Bit 1 */
#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*! & lt; Bit 2 */
#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*! & lt; Bit 3 */
#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*! & lt; Bit 4 */
#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*! & lt; Bit 5 */
#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*! & lt; Bit 6 */
#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*! & lt; Bit 7 */

#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*! & lt; MEMWAIT4[7:0] bits (Common memory 4 wait time) */
#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*! & lt; Bit 0 */
#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*! & lt; Bit 1 */
#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*! & lt; Bit 2 */
#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*! & lt; Bit 3 */
#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*! & lt; Bit 4 */
#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*! & lt; Bit 5 */
#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*! & lt; Bit 6 */
#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*! & lt; Bit 7 */

#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*! & lt; MEMHOLD4[7:0] bits (Common memory 4 hold time) */
#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*! & lt; Bit 0 */
#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*! & lt; Bit 1 */
#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*! & lt; Bit 2 */
#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*! & lt; Bit 3 */
#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*! & lt; Bit 4 */
#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*! & lt; Bit 5 */
#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*! & lt; Bit 6 */
#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*! & lt; Bit 7 */

#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*! & lt; MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*! & lt; Bit 0 */
#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*! & lt; Bit 1 */
#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*! & lt; Bit 2 */
#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*! & lt; Bit 3 */
#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*! & lt; Bit 4 */
#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*! & lt; Bit 5 */
#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*! & lt; Bit 6 */
#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*! & lt; Bit 7 */

/****************** Bit definition for FSMC_PATT2 register ******************/
#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*! & lt; ATTSET2[7:0] bits (Attribute memory 2 setup time) */
#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*! & lt; Bit 0 */
#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*! & lt; Bit 1 */
#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*! & lt; Bit 2 */
#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*! & lt; Bit 3 */
#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*! & lt; Bit 4 */
#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*! & lt; Bit 5 */
#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*! & lt; Bit 6 */
#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*! & lt; Bit 7 */

#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*! & lt; ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*! & lt; Bit 0 */
#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*! & lt; Bit 1 */
#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*! & lt; Bit 2 */
#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*! & lt; Bit 3 */
#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*! & lt; Bit 4 */
#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*! & lt; Bit 5 */
#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*! & lt; Bit 6 */
#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*! & lt; Bit 7 */

#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*! & lt; ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*! & lt; Bit 0 */
#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*! & lt; Bit 1 */
#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*! & lt; Bit 2 */
#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*! & lt; Bit 3 */
#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*! & lt; Bit 4 */
#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*! & lt; Bit 5 */
#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*! & lt; Bit 6 */
#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*! & lt; Bit 7 */

#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*! & lt; ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*! & lt; Bit 0 */
#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*! & lt; Bit 1 */
#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*! & lt; Bit 2 */
#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*! & lt; Bit 3 */
#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*! & lt; Bit 4 */
#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*! & lt; Bit 5 */
#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*! & lt; Bit 6 */
#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*! & lt; Bit 7 */

/****************** Bit definition for FSMC_PATT3 register ******************/
#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*! & lt; ATTSET3[7:0] bits (Attribute memory 3 setup time) */
#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*! & lt; Bit 0 */
#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*! & lt; Bit 1 */
#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*! & lt; Bit 2 */
#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*! & lt; Bit 3 */
#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*! & lt; Bit 4 */
#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*! & lt; Bit 5 */
#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*! & lt; Bit 6 */
#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*! & lt; Bit 7 */

#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*! & lt; ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*! & lt; Bit 0 */
#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*! & lt; Bit 1 */
#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*! & lt; Bit 2 */
#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*! & lt; Bit 3 */
#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*! & lt; Bit 4 */
#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*! & lt; Bit 5 */
#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*! & lt; Bit 6 */
#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*! & lt; Bit 7 */

#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*! & lt; ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*! & lt; Bit 0 */
#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*! & lt; Bit 1 */
#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*! & lt; Bit 2 */
#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*! & lt; Bit 3 */
#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*! & lt; Bit 4 */
#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*! & lt; Bit 5 */
#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*! & lt; Bit 6 */
#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*! & lt; Bit 7 */

#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*! & lt; ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*! & lt; Bit 0 */
#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*! & lt; Bit 1 */
#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*! & lt; Bit 2 */
#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*! & lt; Bit 3 */
#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*! & lt; Bit 4 */
#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*! & lt; Bit 5 */
#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*! & lt; Bit 6 */
#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*! & lt; Bit 7 */

/****************** Bit definition for FSMC_PATT4 register ******************/
#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*! & lt; ATTSET4[7:0] bits (Attribute memory 4 setup time) */
#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*! & lt; Bit 0 */
#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*! & lt; Bit 1 */
#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*! & lt; Bit 2 */
#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*! & lt; Bit 3 */
#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*! & lt; Bit 4 */
#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*! & lt; Bit 5 */
#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*! & lt; Bit 6 */
#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*! & lt; Bit 7 */

#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*! & lt; ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*! & lt; Bit 0 */
#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*! & lt; Bit 1 */
#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*! & lt; Bit 2 */
#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*! & lt; Bit 3 */
#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*! & lt; Bit 4 */
#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*! & lt; Bit 5 */
#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*! & lt; Bit 6 */
#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*! & lt; Bit 7 */

#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*! & lt; ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*! & lt; Bit 0 */
#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*! & lt; Bit 1 */
#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*! & lt; Bit 2 */
#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*! & lt; Bit 3 */
#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*! & lt; Bit 4 */
#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*! & lt; Bit 5 */
#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*! & lt; Bit 6 */
#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*! & lt; Bit 7 */

#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*! & lt; ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*! & lt; Bit 0 */
#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*! & lt; Bit 1 */
#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*! & lt; Bit 2 */
#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*! & lt; Bit 3 */
#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*! & lt; Bit 4 */
#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*! & lt; Bit 5 */
#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*! & lt; Bit 6 */
#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*! & lt; Bit 7 */

/****************** Bit definition for FSMC_PIO4 register *******************/
#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*! & lt; IOSET4[7:0] bits (I/O 4 setup time) */
#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*! & lt; Bit 0 */
#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*! & lt; Bit 1 */
#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*! & lt; Bit 2 */
#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*! & lt; Bit 3 */
#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*! & lt; Bit 4 */
#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*! & lt; Bit 5 */
#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*! & lt; Bit 6 */
#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*! & lt; Bit 7 */

#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*! & lt; IOWAIT4[7:0] bits (I/O 4 wait time) */
#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*! & lt; Bit 0 */
#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*! & lt; Bit 1 */
#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*! & lt; Bit 2 */
#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*! & lt; Bit 3 */
#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*! & lt; Bit 4 */
#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*! & lt; Bit 5 */
#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*! & lt; Bit 6 */
#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*! & lt; Bit 7 */

#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*! & lt; IOHOLD4[7:0] bits (I/O 4 hold time) */
#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*! & lt; Bit 0 */
#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*! & lt; Bit 1 */
#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*! & lt; Bit 2 */
#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*! & lt; Bit 3 */
#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*! & lt; Bit 4 */
#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*! & lt; Bit 5 */
#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*! & lt; Bit 6 */
#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*! & lt; Bit 7 */

#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*! & lt; IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*! & lt; Bit 0 */
#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*! & lt; Bit 1 */
#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*! & lt; Bit 2 */
#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*! & lt; Bit 3 */
#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*! & lt; Bit 4 */
#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*! & lt; Bit 5 */
#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*! & lt; Bit 6 */
#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*! & lt; Bit 7 */

/****************** Bit definition for FSMC_ECCR2 register ******************/
#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*! & lt; ECC result */

/****************** Bit definition for FSMC_ECCR3 register ******************/
#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*! & lt; ECC result */

/******************************************************************************/
/* */
/* General Purpose I/O */
/* */
/******************************************************************************/
/****************** Bits definition for GPIO_MODER register *****************/
#define GPIO_MODER_MODER0 ((uint32_t)0x00000003) //analog mode (both bits set)
#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001) //general purpose output
#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002) //alternate function

#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C) //analog mode (both bits set)
#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)//general purpose output
#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)//alternate function

#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)//analog mode (both bits set)
#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)//general purpose output
#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)//alternate function

#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)//analog mode (both bits set)
#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)//general purpose output
#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)//alternate function

#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)//analog mode (both bits set)
#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)//general purpose output
#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)//alternate function

#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)//analog mode (both bits set)
#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)//general purpose output
#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)//alternate function

#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)//analog mode (both bits set)
#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)//general purpose output
#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)//alternate function

#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)//analog mode (both bits set)
#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)//general purpose output
#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)//alternate function

#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)//analog mode (both bits set)
#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)//general purpose output
#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)//alternate function

#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)//analog mode (both bits set)
#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)//general purpose output
#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)//alternate function

#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)//analog mode (both bits set)
#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)//general purpose output
#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)//alternate function

#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)//analog mode (both bits set)
#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)//general purpose output
#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)//alternate function

#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)//analog mode (both bits set)
#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)//general purpose output
#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)//alternate function

#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)//analog mode (both bits set)
#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)//general purpose output
#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)//alternate function

#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)//analog mode (both bits set)
#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)//general purpose output
#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)//alternate function

#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)//analog mode (both bits set)
#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)//general purpose output
#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)//alternate function

/****************** Bits definition for GPIO_OTYPER register ****************/
#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)//this bit set - open drain output; this bit clear - push pull output
#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)

/****************** Bits definition for GPIO_OSPEEDR register ***************/
#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)//both bits set - High speed 100MHz
#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)//medium speed 25MHz
#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)//fast speed 50MHz

#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)//both bits set - High speed 100MHz
#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)//medium speed 25MHz
#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)//fast speed 50MHz

#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)//both bits set - High speed 100MHz
#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)//medium speed 25MHz
#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)//fast speed 50MHz

#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)//both bits set - High speed 100MHz
#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)//medium speed 25MHz
#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)//fast speed 50MHz

#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)//both bits set - High speed 100MHz
#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)//medium speed 25MHz
#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)//fast speed 50MHz

#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)//both bits set - High speed 100MHz
#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)//medium speed 25MHz
#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)//fast speed 50MHz

#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)//both bits set - High speed 100MHz
#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)//medium speed 25MHz
#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)//fast speed 50MHz

#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)//both bits set - High speed 100MHz
#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)//medium speed 25MHz
#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)//fast speed 50MHz

#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)//both bits set - High speed 100MHz
#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)//medium speed 25MHz
#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)//fast speed 50MHz

#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)//both bits set - High speed 100MHz
#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)//medium speed 25MHz
#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)//fast speed 50MHz

#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)//both bits set - High speed 100MHz
#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)//medium speed 25MHz
#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)//fast speed 50MHz

#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)//both bits set - High speed 100MHz
#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)//medium speed 25MHz
#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)//fast speed 50MHz

#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)//both bits set - High speed 100MHz
#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)//medium speed 25MHz
#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)//fast speed 50MHz

#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)//both bits set - High speed 100MHz
#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)//medium speed 25MHz
#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)//fast speed 50MHz

#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)//both bits set - High speed 100MHz
#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)//medium speed 25MHz
#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)//fast speed 50MHz

#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)//both bits set - High speed 100MHz
#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)//medium speed 25MHz
#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)//fast speed 50MHz

/****************** Bits definition for GPIO_PUPDR register *****************/
#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)//reserved
#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)//pull-up
#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)//pull-down

#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)//reserved
#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)//pull-up
#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)//pull-down

#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)//reserved
#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)//pull-up
#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)//pull-down

#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)//reserved
#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)//pull-up
#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)//pull-down

#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)//reserved
#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)//pull-up
#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)//pull-down

#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)//reserved
#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)//pull-up
#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)//pull-down

#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)//reserved
#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)//pull-up
#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)//pull-down

#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)//reserved
#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)//pull-up
#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)//pull-down

#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)//reserved
#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)//pull-up
#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)//pull-down

#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)//reserved
#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)//pull-up
#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)//pull-down

#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)//reserved
#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)//pull-up
#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)//pull-down

#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)//reserved
#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)//pull-up
#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)//pull-down

#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)//reserved
#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)//pull-up
#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)//pull-down

#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)//reserved
#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)//pull-up
#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)//pull-down

#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)//reserved
#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)//pull-up
#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)//pull-down

#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)//reserved
#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)//pull-up
#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)//pull-down

/****************** Bits definition for GPIO_IDR register *******************/
#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15

/****************** Bits definition for GPIO_ODR register *******************/
#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15

/****************** Bits definition for GPIO_BSRR register ******************/
#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)

/******************************************************************************/
/* */
/* HASH */
/* */
/******************************************************************************/
/****************** Bits definition for HASH_CR register ********************/
#define HASH_CR_INIT ((uint32_t)0x00000004)
#define HASH_CR_DMAE ((uint32_t)0x00000008)
#define HASH_CR_DATATYPE ((uint32_t)0x00000030)
#define HASH_CR_DATATYPE_0 ((uint32_t)0x00000010)
#define HASH_CR_DATATYPE_1 ((uint32_t)0x00000020)
#define HASH_CR_MODE ((uint32_t)0x00000040)
#define HASH_CR_ALGO ((uint32_t)0x00000080)
#define HASH_CR_NBW ((uint32_t)0x00000F00)
#define HASH_CR_NBW_0 ((uint32_t)0x00000100)
#define HASH_CR_NBW_1 ((uint32_t)0x00000200)
#define HASH_CR_NBW_2 ((uint32_t)0x00000400)
#define HASH_CR_NBW_3 ((uint32_t)0x00000800)
#define HASH_CR_DINNE ((uint32_t)0x00001000)
#define HASH_CR_LKEY ((uint32_t)0x00010000)

/****************** Bits definition for HASH_STR register *******************/
#define HASH_STR_NBW ((uint32_t)0x0000001F)
#define HASH_STR_NBW_0 ((uint32_t)0x00000001)
#define HASH_STR_NBW_1 ((uint32_t)0x00000002)
#define HASH_STR_NBW_2 ((uint32_t)0x00000004)
#define HASH_STR_NBW_3 ((uint32_t)0x00000008)
#define HASH_STR_NBW_4 ((uint32_t)0x00000010)
#define HASH_STR_DCAL ((uint32_t)0x00000100)

/****************** Bits definition for HASH_IMR register *******************/
#define HASH_IMR_DINIM ((uint32_t)0x00000001)
#define HASH_IMR_DCIM ((uint32_t)0x00000002)

/****************** Bits definition for HASH_SR register ********************/
#define HASH_SR_DINIS ((uint32_t)0x00000001)
#define HASH_SR_DCIS ((uint32_t)0x00000002)
#define HASH_SR_DMAS ((uint32_t)0x00000004)
#define HASH_SR_BUSY ((uint32_t)0x00000008)

/******************************************************************************/
/* */
/* Inter-integrated Circuit Interface */
/* */
/******************************************************************************/
/******************* Bit definition for I2C_CR1 register ********************/
#define I2C_CR1_PE ((uint16_t)0x0001) /*! & lt; Peripheral Enable */
#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*! & lt; SMBus Mode */
#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*! & lt; SMBus Type */
#define I2C_CR1_ENARP ((uint16_t)0x0010) /*! & lt; ARP Enable */
#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*! & lt; PEC Enable */
#define I2C_CR1_ENGC ((uint16_t)0x0040) /*! & lt; General Call Enable */
#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*! & lt; Clock Stretching Disable (Slave mode) */
#define I2C_CR1_START ((uint16_t)0x0100) /*! & lt; Start Generation */
#define I2C_CR1_STOP ((uint16_t)0x0200) /*! & lt; Stop Generation */
#define I2C_CR1_ACK ((uint16_t)0x0400) /*! & lt; Acknowledge Enable */
#define I2C_CR1_POS ((uint16_t)0x0800) /*! & lt; Acknowledge/PEC Position (for data reception) */
#define I2C_CR1_PEC ((uint16_t)0x1000) /*! & lt; Packet Error Checking */
#define I2C_CR1_ALERT ((uint16_t)0x2000) /*! & lt; SMBus Alert */
#define I2C_CR1_SWRST ((uint16_t)0x8000) /*! & lt; Software Reset */

/******************* Bit definition for I2C_CR2 register ********************/
#define I2C_CR2_FREQ ((uint16_t)0x003F) /*! & lt; FREQ[5:0] bits (Peripheral Clock Frequency) */
#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*! & lt; Bit 0 */
#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*! & lt; Bit 1 */
#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*! & lt; Bit 2 */
#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*! & lt; Bit 3 */
#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*! & lt; Bit 4 */
#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*! & lt; Bit 5 */

#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*! & lt; Error Interrupt Enable */
#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*! & lt; Event Interrupt Enable */
#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*! & lt; Buffer Interrupt Enable */
#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*! & lt; DMA Requests Enable */
#define I2C_CR2_LAST ((uint16_t)0x1000) /*! & lt; DMA Last Transfer */

/******************* Bit definition for I2C_OAR1 register *******************/
#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*! & lt; Interface Address */
#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*! & lt; Interface Address */

#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*! & lt; Bit 0 */
#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*! & lt; Bit 1 */
#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*! & lt; Bit 2 */
#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*! & lt; Bit 3 */
#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*! & lt; Bit 4 */
#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*! & lt; Bit 5 */
#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*! & lt; Bit 6 */
#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*! & lt; Bit 7 */
#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*! & lt; Bit 8 */
#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*! & lt; Bit 9 */

#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*! & lt; Addressing Mode (Slave mode) */

/******************* Bit definition for I2C_OAR2 register *******************/
#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*! & lt; Dual addressing mode enable */
#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*! & lt; Interface address */

/******************** Bit definition for I2C_DR register ********************/
#define I2C_DR_DR ((uint8_t)0xFF) /*! & lt; 8-bit Data Register */

/******************* Bit definition for I2C_SR1 register ********************/
#define I2C_SR1_SB ((uint16_t)0x0001) /*! & lt; Start Bit (Master mode) */
#define I2C_SR1_ADDR ((uint16_t)0x0002) /*! & lt; Address sent (master mode)/matched (slave mode) */
#define I2C_SR1_BTF ((uint16_t)0x0004) /*! & lt; Byte Transfer Finished */
#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*! & lt; 10-bit header sent (Master mode) */
#define I2C_SR1_STOPF ((uint16_t)0x0010) /*! & lt; Stop detection (Slave mode) */
#define I2C_SR1_RXNE ((uint16_t)0x0040) /*! & lt; Data Register not Empty (receivers) */
#define I2C_SR1_TXE ((uint16_t)0x0080) /*! & lt; Data Register Empty (transmitters) */
#define I2C_SR1_BERR ((uint16_t)0x0100) /*! & lt; Bus Error */
#define I2C_SR1_ARLO ((uint16_t)0x0200) /*! & lt; Arbitration Lost (master mode) */
#define I2C_SR1_AF ((uint16_t)0x0400) /*! & lt; Acknowledge Failure */
#define I2C_SR1_OVR ((uint16_t)0x0800) /*! & lt; Overrun/Underrun */
#define I2C_SR1_PECERR ((uint16_t)0x1000) /*! & lt; PEC Error in reception */
#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*! & lt; Timeout or Tlow Error */
#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*! & lt; SMBus Alert */

/******************* Bit definition for I2C_SR2 register ********************/
#define I2C_SR2_MSL ((uint16_t)0x0001) /*! & lt; Master/Slave */
#define I2C_SR2_BUSY ((uint16_t)0x0002) /*! & lt; Bus Busy */
#define I2C_SR2_TRA ((uint16_t)0x0004) /*! & lt; Transmitter/Receiver */
#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*! & lt; General Call Address (Slave mode) */
#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*! & lt; SMBus Device Default Address (Slave mode) */
#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*! & lt; SMBus Host Header (Slave mode) */
#define I2C_SR2_DUALF ((uint16_t)0x0080) /*! & lt; Dual Flag (Slave mode) */
#define I2C_SR2_PEC ((uint16_t)0xFF00) /*! & lt; Packet Error Checking Register */

/******************* Bit definition for I2C_CCR register ********************/
#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*! & lt; Clock Control Register in Fast/Standard mode (Master mode) */
#define I2C_CCR_DUTY ((uint16_t)0x4000) /*! & lt; Fast Mode Duty Cycle */
#define I2C_CCR_FS ((uint16_t)0x8000) /*! & lt; I2C Master Mode Selection */

/****************** Bit definition for I2C_TRISE register *******************/
#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*! & lt; Maximum Rise Time in Fast/Standard mode (Master mode) */

/******************************************************************************/
/* */
/* Independent WATCHDOG */
/* */
/******************************************************************************/
/******************* Bit definition for IWDG_KR register ********************/
#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*! & lt; Key value (write only, read 0000h) */

/******************* Bit definition for IWDG_PR register ********************/
#define IWDG_PR_PR ((uint8_t)0x07) /*! & lt; PR[2:0] (Prescaler divider) */
#define IWDG_PR_PR_0 ((uint8_t)0x01) /*! & lt; Bit 0 */
#define IWDG_PR_PR_1 ((uint8_t)0x02) /*! & lt; Bit 1 */
#define IWDG_PR_PR_2 ((uint8_t)0x04) /*! & lt; Bit 2 */

/******************* Bit definition for IWDG_RLR register *******************/
#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*! & lt; Watchdog counter reload value */

/******************* Bit definition for IWDG_SR register ********************/
#define IWDG_SR_PVU ((uint8_t)0x01) /*! & lt; Watchdog prescaler value update */
#define IWDG_SR_RVU ((uint8_t)0x02) /*! & lt; Watchdog counter reload value update */

/******************************************************************************/
/* */
/* Power Control */
/* */
/******************************************************************************/
/******************** Bit definition for PWR_CR register ********************/
#define PWR_CR_LPDS ((uint16_t)0x0001) /*! & lt; Low-Power Deepsleep */
#define PWR_CR_PDDS ((uint16_t)0x0002) /*! & lt; Power Down Deepsleep */
#define PWR_CR_CWUF ((uint16_t)0x0004) /*! & lt; Clear Wakeup Flag */
#define PWR_CR_CSBF ((uint16_t)0x0008) /*! & lt; Clear Standby Flag */
#define PWR_CR_PVDE ((uint16_t)0x0010) /*! & lt; Power Voltage Detector Enable */

#define PWR_CR_PLS ((uint16_t)0x00E0) /*! & lt; PLS[2:0] bits (PVD Level Selection) */
#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*! & lt; Bit 0 */
#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*! & lt; Bit 1 */
#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*! & lt; Bit 2 */


/*! & lt; PVD level configuration */
#define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) /*! & lt; PVD level 0 */
#define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) /*! & lt; PVD level 1 */
#define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) /*! & lt; PVD level 2 */
#define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) /*! & lt; PVD level 3 */
#define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) /*! & lt; PVD level 4 */
#define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) /*! & lt; PVD level 5 */
#define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) /*! & lt; PVD level 6 */
#define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) /*! & lt; PVD level 7 */

#define PWR_CR_DBP ((uint16_t)0x0100) /*! & lt; Disable Backup Domain write protection */
#define PWR_CR_FPDS ((uint16_t)0x0200) /*! & lt; Flash power down in Stop mode */
#define PWR_CR_VOS ((uint16_t)0x4000) /*! & lt; Regulator voltage scaling output selection */
/* Legacy define */
#define PWR_CR_PMODE PWR_CR_VOS

/******************* Bit definition for PWR_CSR register ********************/
#define PWR_CSR_WUF ((uint16_t)0x0001) /*! & lt; Wakeup Flag */
#define PWR_CSR_SBF ((uint16_t)0x0002) /*! & lt; Standby Flag */
#define PWR_CSR_PVDO ((uint16_t)0x0004) /*! & lt; PVD Output */
#define PWR_CSR_BRR ((uint16_t)0x0008) /*! & lt; Backup regulator ready */
#define PWR_CSR_EWUP ((uint16_t)0x0100) /*! & lt; Enable WKUP pin */
#define PWR_CSR_BRE ((uint16_t)0x0200) /*! & lt; Backup regulator enable */
#define PWR_CSR_VOSRDY ((uint16_t)0x4000) /*! & lt; Regulator voltage scaling output selection ready */
/* Legacy define */
#define PWR_CSR_REGRDY PWR_CSR_VOSRDY

/******************************************************************************/
/* */
/* Reset and Clock Control */
/* */
/******************************************************************************/
/******************** Bit definition for RCC_CR register ********************/
#define RCC_CR_HSION ((uint32_t)0x00000001)
#define RCC_CR_HSIRDY ((uint32_t)0x00000002)

#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*! & lt; Bit 0 */
#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*! & lt; Bit 1 */
#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*! & lt; Bit 2 */
#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*! & lt; Bit 3 */
#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*! & lt; Bit 4 */

#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*! & lt; Bit 0 */
#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*! & lt; Bit 1 */
#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*! & lt; Bit 2 */
#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*! & lt; Bit 3 */
#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*! & lt; Bit 4 */
#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*! & lt; Bit 5 */
#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*! & lt; Bit 6 */
#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*! & lt; Bit 7 */

#define RCC_CR_HSEON ((uint32_t)0x00010000)
#define RCC_CR_HSERDY ((uint32_t)0x00020000)
#define RCC_CR_HSEBYP ((uint32_t)0x00040000)
#define RCC_CR_CSSON ((uint32_t)0x00080000)
#define RCC_CR_PLLON ((uint32_t)0x01000000)
#define RCC_CR_PLLRDY ((uint32_t)0x02000000)
#define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
#define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)

/******************** Bit definition for RCC_PLLCFGR register ***************/
#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)

#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)

#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000) //Main PLL (PLL) division factor (8) for main system clock
#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000) //Main PLL (PLL) division factor (4) for main system clock
#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000) //Main PLL (PLL) division factor (6) for main system clock

#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000) //this bit set - HSE clock selected as PLL input clock; this bit clear - HSI clock selected as PLL input clock
#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)

#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)

/******************** Bit definition for RCC_CFGR register ******************/
/*! & lt; SW configuration */
#define RCC_CFGR_SW ((uint32_t)0x00000003) /*! & lt; SW[1:0] bits (System clock Switch) */
#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*! & lt; Bit 0 */
#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*! & lt; Bit 1 */

#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*! & lt; HSI selected as system clock */
#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*! & lt; HSE selected as system clock */
#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*! & lt; PLL selected as system clock */

/*! & lt; SWS configuration */
#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*! & lt; SWS[1:0] bits (System Clock Switch Status) */
#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*! & lt; Bit 0 */
#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*! & lt; Bit 1 */

#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*! & lt; HSI oscillator used as system clock */
#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*! & lt; HSE oscillator used as system clock */
#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*! & lt; PLL used as system clock */

/*! & lt; HPRE configuration */
#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*! & lt; HPRE[3:0] bits (AHB prescaler) */
#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*! & lt; Bit 0 */
#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*! & lt; Bit 1 */
#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*! & lt; Bit 2 */
#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*! & lt; Bit 3 */

#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*! & lt; SYSCLK not divided */
#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*! & lt; SYSCLK divided by 2 */
#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*! & lt; SYSCLK divided by 4 */
#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*! & lt; SYSCLK divided by 8 */
#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*! & lt; SYSCLK divided by 16 */
#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*! & lt; SYSCLK divided by 64 */
#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*! & lt; SYSCLK divided by 128 */
#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*! & lt; SYSCLK divided by 256 */
#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*! & lt; SYSCLK divided by 512 */

/*! & lt; PPRE1 configuration */
#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*! & lt; PRE1[2:0] bits (APB1 prescaler) */
#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*! & lt; Bit 0 */
#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*! & lt; Bit 1 */
#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*! & lt; Bit 2 */

#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*! & lt; HCLK not divided */
#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*! & lt; HCLK divided by 2 */
#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*! & lt; HCLK divided by 4 */
#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*! & lt; HCLK divided by 8 */
#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*! & lt; HCLK divided by 16 */

/*! & lt; PPRE2 configuration */
#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*! & lt; PRE2[2:0] bits (APB2 prescaler) */
#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*! & lt; Bit 0 */
#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*! & lt; Bit 1 */
#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*! & lt; Bit 2 */

#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*! & lt; HCLK not divided */
#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*! & lt; HCLK divided by 2 */
#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*! & lt; HCLK divided by 4 */
#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*! & lt; HCLK divided by 8 */
#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*! & lt; HCLK divided by 16 */

/*! & lt; RTCPRE configuration */
#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)

/*! & lt; MCO1 configuration */
#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)

#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)

#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)

#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)

#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)

/******************** Bit definition for RCC_CIR register *******************/
#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
#define RCC_CIR_CSSF ((uint32_t)0x00000080)
#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
#define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
#define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
#define RCC_CIR_CSSC ((uint32_t)0x00800000)

/******************** Bit definition for RCC_AHB1RSTR register **************/
#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
#define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
#define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
#define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)

/******************** Bit definition for RCC_AHB2RSTR register **************/
#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
#define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010)
#define RCC_AHB2RSTR_HSAHRST ((uint32_t)0x00000020)
#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)

/******************** Bit definition for RCC_AHB3RSTR register **************/
#define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001)

/******************** Bit definition for RCC_APB1RSTR register **************/
#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
#define RCC_APB1RSTR_WWDGEN ((uint32_t)0x00000800)
#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)//by?o, chyba b??d((uint32_t)0x00008000)
#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)//by?o, chyba b??d((uint32_t)0x00010000)
#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)

/******************** Bit definition for RCC_APB2RSTR register **************/
#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
#define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
/* Old SPI1RST bit definition, maintained for legacy purpose */
#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST

/******************** Bit definition for RCC_AHB1ENR register ***************/
#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
#define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
#define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
#define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
#define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
#define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
#define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
#define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
#define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
#define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
#define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
#define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
#define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)

/******************** Bit definition for RCC_AHB2ENR register ***************/
#define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
#define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010)
#define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020)
#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)

/******************** Bit definition for RCC_AHB3ENR register ***************/
#define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001)

/******************** Bit definition for RCC_APB1ENR register ***************/
#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)

/******************** Bit definition for RCC_APB2ENR register ***************/
#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
#define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)

/******************** Bit definition for RCC_AHB1LPENR register *************/
#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
#define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
#define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
#define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
#define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
#define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
#define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
#define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
#define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
#define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
#define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
#define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)

/******************** Bit definition for RCC_AHB2LPENR register *************/
#define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
#define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010)
#define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020)
#define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)

/******************** Bit definition for RCC_AHB3LPENR register *************/
#define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001)

/******************** Bit definition for RCC_APB1LPENR register *************/
#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
#define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
#define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
#define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
#define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
#define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)

/******************** Bit definition for RCC_APB2LPENR register *************/
#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
#define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
#define RCC_APB2LPENR_ADC2PEN ((uint32_t)0x00000200)
#define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
#define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)

/******************** Bit definition for RCC_BDCR register ******************/
#define RCC_BDCR_LSEON ((uint32_t)0x00000001)
#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)

#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)

#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
#define RCC_BDCR_BDRST ((uint32_t)0x00010000)

/******************** Bit definition for RCC_CSR register *******************/
#define RCC_CSR_LSION ((uint32_t)0x00000001)
#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
#define RCC_CSR_RMVF ((uint32_t)0x01000000)
#define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
#define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
#define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)

/******************** Bit definition for RCC_SSCGR register *****************/
#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)

/******************** Bit definition for RCC_PLLI2SCFGR register ************/
#define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
#define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)

/******************************************************************************/
/* */
/* RNG */
/* */
/******************************************************************************/
/******************** Bits definition for RNG_CR register *******************/
#define RNG_CR_RNGEN ((uint32_t)0x00000004)
#define RNG_CR_IE ((uint32_t)0x00000008)

/******************** Bits definition for RNG_SR register *******************/
#define RNG_SR_DRDY ((uint32_t)0x00000001)
#define RNG_SR_CECS ((uint32_t)0x00000002)
#define RNG_SR_SECS ((uint32_t)0x00000004)
#define RNG_SR_CEIS ((uint32_t)0x00000020)
#define RNG_SR_SEIS ((uint32_t)0x00000040)

/******************************************************************************/
/* */
/* Real-Time Clock (RTC) */
/* */
/******************************************************************************/
/******************** Bits definition for RTC_TR register *******************/
#define RTC_TR_PM ((uint32_t)0x00400000)
#define RTC_TR_HT ((uint32_t)0x00300000)
#define RTC_TR_HT_0 ((uint32_t)0x00100000)
#define RTC_TR_HT_1 ((uint32_t)0x00200000)
#define RTC_TR_HU ((uint32_t)0x000F0000)
#define RTC_TR_HU_0 ((uint32_t)0x00010000)
#define RTC_TR_HU_1 ((uint32_t)0x00020000)
#define RTC_TR_HU_2 ((uint32_t)0x00040000)
#define RTC_TR_HU_3 ((uint32_t)0x00080000)
#define RTC_TR_MNT ((uint32_t)0x00007000)
#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
#define RTC_TR_MNU ((uint32_t)0x00000F00)
#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
#define RTC_TR_ST ((uint32_t)0x00000070)
#define RTC_TR_ST_0 ((uint32_t)0x00000010)
#define RTC_TR_ST_1 ((uint32_t)0x00000020)
#define RTC_TR_ST_2 ((uint32_t)0x00000040)
#define RTC_TR_SU ((uint32_t)0x0000000F)
#define RTC_TR_SU_0 ((uint32_t)0x00000001)
#define RTC_TR_SU_1 ((uint32_t)0x00000002)
#define RTC_TR_SU_2 ((uint32_t)0x00000004)
#define RTC_TR_SU_3 ((uint32_t)0x00000008)

/******************** Bits definition for RTC_DR register *******************/
#define RTC_DR_YT ((uint32_t)0x00F00000)
#define RTC_DR_YT_0 ((uint32_t)0x00100000)
#define RTC_DR_YT_1 ((uint32_t)0x00200000)
#define RTC_DR_YT_2 ((uint32_t)0x00400000)
#define RTC_DR_YT_3 ((uint32_t)0x00800000)
#define RTC_DR_YU ((uint32_t)0x000F0000)
#define RTC_DR_YU_0 ((uint32_t)0x00010000)
#define RTC_DR_YU_1 ((uint32_t)0x00020000)
#define RTC_DR_YU_2 ((uint32_t)0x00040000)
#define RTC_DR_YU_3 ((uint32_t)0x00080000)
#define RTC_DR_WDU ((uint32_t)0x0000E000)
#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
#define RTC_DR_MT ((uint32_t)0x00001000)
#define RTC_DR_MU ((uint32_t)0x00000F00)
#define RTC_DR_MU_0 ((uint32_t)0x00000100)
#define RTC_DR_MU_1 ((uint32_t)0x00000200)
#define RTC_DR_MU_2 ((uint32_t)0x00000400)
#define RTC_DR_MU_3 ((uint32_t)0x00000800)
#define RTC_DR_DT ((uint32_t)0x00000030)
#define RTC_DR_DT_0 ((uint32_t)0x00000010)
#define RTC_DR_DT_1 ((uint32_t)0x00000020)
#define RTC_DR_DU ((uint32_t)0x0000000F)
#define RTC_DR_DU_0 ((uint32_t)0x00000001)
#define RTC_DR_DU_1 ((uint32_t)0x00000002)
#define RTC_DR_DU_2 ((uint32_t)0x00000004)
#define RTC_DR_DU_3 ((uint32_t)0x00000008)

/******************** Bits definition for RTC_CR register *******************/
#define RTC_CR_COE ((uint32_t)0x00800000)
#define RTC_CR_OSEL ((uint32_t)0x00600000)
#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
#define RTC_CR_POL ((uint32_t)0x00100000)
#define RTC_CR_COSEL ((uint32_t)0x00080000)
#define RTC_CR_BCK ((uint32_t)0x00040000)
#define RTC_CR_SUB1H ((uint32_t)0x00020000)
#define RTC_CR_ADD1H ((uint32_t)0x00010000)
#define RTC_CR_TSIE ((uint32_t)0x00008000)
#define RTC_CR_WUTIE ((uint32_t)0x00004000)
#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
#define RTC_CR_TSE ((uint32_t)0x00000800)
#define RTC_CR_WUTE ((uint32_t)0x00000400)
#define RTC_CR_ALRBE ((uint32_t)0x00000200)
#define RTC_CR_ALRAE ((uint32_t)0x00000100)
#define RTC_CR_DCE ((uint32_t)0x00000080)
#define RTC_CR_FMT ((uint32_t)0x00000040)
#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
#define RTC_CR_REFCKON ((uint32_t)0x00000010)
#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)

/******************** Bits definition for RTC_ISR register ******************/
#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
#define RTC_ISR_TSF ((uint32_t)0x00000800)
#define RTC_ISR_WUTF ((uint32_t)0x00000400)
#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
#define RTC_ISR_INIT ((uint32_t)0x00000080)
#define RTC_ISR_INITF ((uint32_t)0x00000040)
#define RTC_ISR_RSF ((uint32_t)0x00000020)
#define RTC_ISR_INITS ((uint32_t)0x00000010)
#define RTC_ISR_SHPF ((uint32_t)0x00000008)
#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)

/******************** Bits definition for RTC_PRER register *****************/
#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)

/******************** Bits definition for RTC_WUTR register *****************/
#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)

/******************** Bits definition for RTC_CALIBR register ***************/
#define RTC_CALIBR_DCS ((uint32_t)0x00000080)
#define RTC_CALIBR_DC ((uint32_t)0x0000001F)

/******************** Bits definition for RTC_ALRMAR register ***************/
#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)

/******************** Bits definition for RTC_ALRMBR register ***************/
#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)

/******************** Bits definition for RTC_WPR register ******************/
#define RTC_WPR_KEY ((uint32_t)0x000000FF)

/******************** Bits definition for RTC_SSR register ******************/
#define RTC_SSR_SS ((uint32_t)0x0000FFFF)

/******************** Bits definition for RTC_SHIFTR register ***************/
#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)

/******************** Bits definition for RTC_TSTR register *****************/
#define RTC_TSTR_PM ((uint32_t)0x00400000)
#define RTC_TSTR_HT ((uint32_t)0x00300000)
#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
#define RTC_TSTR_HU ((uint32_t)0x000F0000)
#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
#define RTC_TSTR_MNT ((uint32_t)0x00007000)
#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
#define RTC_TSTR_ST ((uint32_t)0x00000070)
#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
#define RTC_TSTR_SU ((uint32_t)0x0000000F)
#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)

/******************** Bits definition for RTC_TSDR register *****************/
#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
#define RTC_TSDR_MT ((uint32_t)0x00001000)
#define RTC_TSDR_MU ((uint32_t)0x00000F00)
#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
#define RTC_TSDR_DT ((uint32_t)0x00000030)
#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
#define RTC_TSDR_DU ((uint32_t)0x0000000F)
#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)

/******************** Bits definition for RTC_TSSSR register ****************/
#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)

/******************** Bits definition for RTC_CAL register *****************/
#define RTC_CALR_CALP ((uint32_t)0x00008000)
#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
#define RTC_CALR_CALM ((uint32_t)0x000001FF)
#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)

/******************** Bits definition for RTC_TAFCR register ****************/
#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
#define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
#define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)

/******************** Bits definition for RTC_ALRMASSR register *************/
#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)

/******************** Bits definition for RTC_ALRMBSSR register *************/
#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)

/******************** Bits definition for RTC_BKP0R register ****************/
#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)

/******************** Bits definition for RTC_BKP1R register ****************/
#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)

/******************** Bits definition for RTC_BKP2R register ****************/
#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)

/******************** Bits definition for RTC_BKP3R register ****************/
#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)

/******************** Bits definition for RTC_BKP4R register ****************/
#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)

/******************** Bits definition for RTC_BKP5R register ****************/
#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)

/******************** Bits definition for RTC_BKP6R register ****************/
#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)

/******************** Bits definition for RTC_BKP7R register ****************/
#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)

/******************** Bits definition for RTC_BKP8R register ****************/
#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)

/******************** Bits definition for RTC_BKP9R register ****************/
#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)

/******************** Bits definition for RTC_BKP10R register ***************/
#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)

/******************** Bits definition for RTC_BKP11R register ***************/
#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)

/******************** Bits definition for RTC_BKP12R register ***************/
#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)

/******************** Bits definition for RTC_BKP13R register ***************/
#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)

/******************** Bits definition for RTC_BKP14R register ***************/
#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)

/******************** Bits definition for RTC_BKP15R register ***************/
#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)

/******************** Bits definition for RTC_BKP16R register ***************/
#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)

/******************** Bits definition for RTC_BKP17R register ***************/
#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)

/******************** Bits definition for RTC_BKP18R register ***************/
#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)

/******************** Bits definition for RTC_BKP19R register ***************/
#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)

/******************************************************************************/
/* */
/* SD host Interface */
/* */
/******************************************************************************/
/****************** Bit definition for SDIO_POWER register ******************/
#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*! & lt; PWRCTRL[1:0] bits (Power supply control bits) */
#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*! & lt; Bit 0 */
#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*! & lt; Bit 1 */

/****************** Bit definition for SDIO_CLKCR register ******************/
#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*! & lt; Clock divide factor */
#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*! & lt; Clock enable bit */
#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*! & lt; Power saving configuration bit */
#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*! & lt; Clock divider bypass enable bit */

#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*! & lt; WIDBUS[1:0] bits (Wide bus mode enable bit) */
#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*! & lt; Bit 0 */
#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*! & lt; Bit 1 */

#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*! & lt; SDIO_CK dephasing selection bit */
#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*! & lt; HW Flow Control enable */

/******************* Bit definition for SDIO_ARG register *******************/
#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*! & lt; Command argument */

/******************* Bit definition for SDIO_CMD register *******************/
#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*! & lt; Command Index */

#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*! & lt; WAITRESP[1:0] bits (Wait for response bits) */
#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*! & lt; Bit 0 */
#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*! & lt; Bit 1 */

#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*! & lt; CPSM Waits for Interrupt Request */
#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*! & lt; CPSM Waits for ends of data transfer (CmdPend internal signal) */
#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*! & lt; Command path state machine (CPSM) Enable bit */
#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*! & lt; SD I/O suspend command */
#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*! & lt; Enable CMD completion */
#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*! & lt; Not Interrupt Enable */
#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*! & lt; CE-ATA command */

/***************** Bit definition for SDIO_RESPCMD register *****************/
#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*! & lt; Response command index */

/****************** Bit definition for SDIO_RESP0 register ******************/
#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*! & lt; Card Status */

/****************** Bit definition for SDIO_RESP1 register ******************/
#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*! & lt; Card Status */

/****************** Bit definition for SDIO_RESP2 register ******************/
#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*! & lt; Card Status */

/****************** Bit definition for SDIO_RESP3 register ******************/
#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*! & lt; Card Status */

/****************** Bit definition for SDIO_RESP4 register ******************/
#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*! & lt; Card Status */

/****************** Bit definition for SDIO_DTIMER register *****************/
#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*! & lt; Data timeout period. */

/****************** Bit definition for SDIO_DLEN register *******************/
#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*! & lt; Data length value */

/****************** Bit definition for SDIO_DCTRL register ******************/
#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*! & lt; Data transfer enabled bit */
#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*! & lt; Data transfer direction selection */
#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*! & lt; Data transfer mode selection */
#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*! & lt; DMA enabled bit */

#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*! & lt; DBLOCKSIZE[3:0] bits (Data block size) */
#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*! & lt; Bit 0 */
#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*! & lt; Bit 1 */
#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*! & lt; Bit 2 */
#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*! & lt; Bit 3 */

#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*! & lt; Read wait start */
#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*! & lt; Read wait stop */
#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*! & lt; Read wait mode */
#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*! & lt; SD I/O enable functions */

/****************** Bit definition for SDIO_DCOUNT register *****************/
#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*! & lt; Data count value */

/****************** Bit definition for SDIO_STA register ********************/
#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*! & lt; Command response received (CRC check failed) */
#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*! & lt; Data block sent/received (CRC check failed) */
#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*! & lt; Command response timeout */
#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*! & lt; Data timeout */
#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*! & lt; Transmit FIFO underrun error */
#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*! & lt; Received FIFO overrun error */
#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*! & lt; Command response received (CRC check passed) */
#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*! & lt; Command sent (no response required) */
#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*! & lt; Data end (data counter, SDIDCOUNT, is zero) */
#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*! & lt; Start bit not detected on all data signals in wide bus mode */
#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*! & lt; Data block sent/received (CRC check passed) */
#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*! & lt; Command transfer in progress */
#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*! & lt; Data transmit in progress */
#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*! & lt; Data receive in progress */
#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*! & lt; Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*! & lt; Receive FIFO Half Full: there are at least 8 words in the FIFO */
#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*! & lt; Transmit FIFO full */
#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*! & lt; Receive FIFO full */
#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*! & lt; Transmit FIFO empty */
#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*! & lt; Receive FIFO empty */
#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*! & lt; Data available in transmit FIFO */
#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*! & lt; Data available in receive FIFO */
#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*! & lt; SDIO interrupt received */
#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*! & lt; CE-ATA command completion signal received for CMD61 */

/******************* Bit definition for SDIO_ICR register *******************/
#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*! & lt; CCRCFAIL flag clear bit */
#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*! & lt; DCRCFAIL flag clear bit */
#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*! & lt; CTIMEOUT flag clear bit */
#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*! & lt; DTIMEOUT flag clear bit */
#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*! & lt; TXUNDERR flag clear bit */
#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*! & lt; RXOVERR flag clear bit */
#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*! & lt; CMDREND flag clear bit */
#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*! & lt; CMDSENT flag clear bit */
#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*! & lt; DATAEND flag clear bit */
#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*! & lt; STBITERR flag clear bit */
#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*! & lt; DBCKEND flag clear bit */
#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*! & lt; SDIOIT flag clear bit */
#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*! & lt; CEATAEND flag clear bit */

/****************** Bit definition for SDIO_MASK register *******************/
#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*! & lt; Command CRC Fail Interrupt Enable */
#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*! & lt; Data CRC Fail Interrupt Enable */
#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*! & lt; Command TimeOut Interrupt Enable */
#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*! & lt; Data TimeOut Interrupt Enable */
#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*! & lt; Tx FIFO UnderRun Error Interrupt Enable */
#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*! & lt; Rx FIFO OverRun Error Interrupt Enable */
#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*! & lt; Command Response Received Interrupt Enable */
#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*! & lt; Command Sent Interrupt Enable */
#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*! & lt; Data End Interrupt Enable */
#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*! & lt; Start Bit Error Interrupt Enable */
#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*! & lt; Data Block End Interrupt Enable */
#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*! & lt; CCommand Acting Interrupt Enable */
#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*! & lt; Data Transmit Acting Interrupt Enable */
#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*! & lt; Data receive acting interrupt enabled */
#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*! & lt; Tx FIFO Half Empty interrupt Enable */
#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*! & lt; Rx FIFO Half Full interrupt Enable */
#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*! & lt; Tx FIFO Full interrupt Enable */
#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*! & lt; Rx FIFO Full interrupt Enable */
#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*! & lt; Tx FIFO Empty interrupt Enable */
#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*! & lt; Rx FIFO Empty interrupt Enable */
#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*! & lt; Data available in Tx FIFO interrupt Enable */
#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*! & lt; Data available in Rx FIFO interrupt Enable */
#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*! & lt; SDIO Mode Interrupt Received interrupt Enable */
#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*! & lt; CE-ATA command completion signal received Interrupt Enable */

/***************** Bit definition for SDIO_FIFOCNT register *****************/
#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*! & lt; Remaining number of words to be written to or read from the FIFO */

/****************** Bit definition for SDIO_FIFO register *******************/
#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*! & lt; Receive and transmit FIFO data */

/******************************************************************************/
/* */
/* Serial Peripheral Interface */
/* */
/******************************************************************************/
/******************* Bit definition for SPI_CR1 register ********************/
#define SPI_CR1_CPHA ((uint16_t)0x0001) /*! & lt; Clock Phase */
#define SPI_CR1_CPOL ((uint16_t)0x0002) /*! & lt; Clock Polarity */
#define SPI_CR1_MSTR ((uint16_t)0x0004) /*! & lt; Master Selection */

#define SPI_CR1_BR ((uint16_t)0x0038) /*! & lt; BR[2:0] bits (Baud Rate Control) */
#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*! & lt; Bit 0 */
#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*! & lt; Bit 1 */
#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*! & lt; Bit 2 */

#define SPI_CR1_SPE ((uint16_t)0x0040) /*! & lt; SPI Enable */
#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*! & lt; Frame Format */
#define SPI_CR1_SSI ((uint16_t)0x0100) /*! & lt; Internal slave select */
#define SPI_CR1_SSM ((uint16_t)0x0200) /*! & lt; Software slave management */
#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*! & lt; Receive only */
#define SPI_CR1_DFF ((uint16_t)0x0800) /*! & lt; Data Frame Format */
#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*! & lt; Transmit CRC next */
#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*! & lt; Hardware CRC calculation enable */
#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*! & lt; Output enable in bidirectional mode */
#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*! & lt; Bidirectional data mode enable */

/******************* Bit definition for SPI_CR2 register ********************/
#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*! & lt; Rx Buffer DMA Enable */
#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*! & lt; Tx Buffer DMA Enable */
#define SPI_CR2_SSOE ((uint8_t)0x04) /*! & lt; SS Output Enable */
#define SPI_CR2_ERRIE ((uint8_t)0x20) /*! & lt; Error Interrupt Enable */
#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*! & lt; RX buffer Not Empty Interrupt Enable */
#define SPI_CR2_TXEIE ((uint8_t)0x80) /*! & lt; Tx buffer Empty Interrupt Enable */

/******************** Bit definition for SPI_SR register ********************/
#define SPI_SR_RXNE ((uint8_t)0x01) /*! & lt; Receive buffer Not Empty */
#define SPI_SR_TXE ((uint8_t)0x02) /*! & lt; Transmit buffer Empty */
#define SPI_SR_CHSIDE ((uint8_t)0x04) /*! & lt; Channel side */
#define SPI_SR_UDR ((uint8_t)0x08) /*! & lt; Underrun flag */
#define SPI_SR_CRCERR ((uint8_t)0x10) /*! & lt; CRC Error flag */
#define SPI_SR_MODF ((uint8_t)0x20) /*! & lt; Mode fault */
#define SPI_SR_OVR ((uint8_t)0x40) /*! & lt; Overrun flag */
#define SPI_SR_BSY ((uint8_t)0x80) /*! & lt; Busy flag */

/******************** Bit definition for SPI_DR register ********************/
#define SPI_DR_DR ((uint16_t)0xFFFF) /*! & lt; Data Register */

/******************* Bit definition for SPI_CRCPR register ******************/
#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*! & lt; CRC polynomial register */

/****************** Bit definition for SPI_RXCRCR register ******************/
#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*! & lt; Rx CRC Register */

/****************** Bit definition for SPI_TXCRCR register ******************/
#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*! & lt; Tx CRC Register */

/****************** Bit definition for SPI_I2SCFGR register *****************/
#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*! & lt; Channel length (number of bits per audio channel) */

#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*! & lt; DATLEN[1:0] bits (Data length to be transferred) */
#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*! & lt; Bit 0 */
#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*! & lt; Bit 1 */

#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*! & lt; steady state clock polarity */

#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*! & lt; I2SSTD[1:0] bits (I2S standard selection) */
#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*! & lt; Bit 0 */
#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*! & lt; Bit 1 */

#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*! & lt; PCM frame synchronization */

#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*! & lt; I2SCFG[1:0] bits (I2S configuration mode) */
#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*! & lt; Bit 0 */
#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*! & lt; Bit 1 */

#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*! & lt; I2S Enable */
#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*! & lt; I2S mode selection */

/****************** Bit definition for SPI_I2SPR register *******************/
#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*! & lt; I2S Linear prescaler */
#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*! & lt; Odd factor for the prescaler */
#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*! & lt; Master Clock Output Enable */

/******************************************************************************/
/* */
/* SYSCFG */
/* */
/******************************************************************************/
/****************** Bit definition for SYSCFG_MEMRMP register ***************/
#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003) /*! & lt; SYSCFG_Memory Remap Config */
#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)

/****************** Bit definition for SYSCFG_PMC register ******************/
#define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*! & lt; Ethernet PHY interface selection */
/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
#define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL

/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*! & lt; EXTI 0 configuration */
#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*! & lt; EXTI 1 configuration */
#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*! & lt; EXTI 2 configuration */
#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*! & lt; EXTI 3 configuration */
/**
* @brief EXTI0 configuration
*/
#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*! & lt; PA[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*! & lt; PB[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*! & lt; PC[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*! & lt; PD[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*! & lt; PE[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*! & lt; PF[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*! & lt; PG[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0007) /*! & lt; PH[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PI ((uint16_t)0x0008) /*! & lt; PI[0] pin */
/**
* @brief EXTI1 configuration
*/
#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*! & lt; PA[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*! & lt; PB[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*! & lt; PC[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*! & lt; PD[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*! & lt; PE[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*! & lt; PF[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*! & lt; PG[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0070) /*! & lt; PH[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PI ((uint16_t)0x0080) /*! & lt; PI[1] pin */
/**
* @brief EXTI2 configuration
*/
#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*! & lt; PA[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*! & lt; PB[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*! & lt; PC[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*! & lt; PD[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*! & lt; PE[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*! & lt; PF[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*! & lt; PG[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0700) /*! & lt; PH[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PI ((uint16_t)0x0800) /*! & lt; PI[2] pin */
/**
* @brief EXTI3 configuration
*/
#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*! & lt; PA[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*! & lt; PB[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*! & lt; PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*! & lt; PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*! & lt; PE[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*! & lt; PF[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*! & lt; PG[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PH ((uint16_t)0x7000) /*! & lt; PH[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PI ((uint16_t)0x8000) /*! & lt; PI[3] pin */

/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*! & lt; EXTI 4 configuration */
#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*! & lt; EXTI 5 configuration */
#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*! & lt; EXTI 6 configuration */
#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*! & lt; EXTI 7 configuration */
/**
* @brief EXTI4 configuration
*/
#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*! & lt; PA[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*! & lt; PB[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*! & lt; PC[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*! & lt; PD[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*! & lt; PE[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*! & lt; PF[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*! & lt; PG[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PH ((uint16_t)0x0007) /*! & lt; PH[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PI ((uint16_t)0x0008) /*! & lt; PI[4] pin */
/**
* @brief EXTI5 configuration
*/
#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*! & lt; PA[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*! & lt; PB[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*! & lt; PC[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*! & lt; PD[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*! & lt; PE[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*! & lt; PF[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*! & lt; PG[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PH ((uint16_t)0x0070) /*! & lt; PH[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PI ((uint16_t)0x0080) /*! & lt; PI[5] pin */
/**
* @brief EXTI6 configuration
*/
#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*! & lt; PA[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*! & lt; PB[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*! & lt; PC[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*! & lt; PD[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*! & lt; PE[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*! & lt; PF[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*! & lt; PG[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PH ((uint16_t)0x0700) /*! & lt; PH[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PI ((uint16_t)0x0800) /*! & lt; PI[6] pin */
/**
* @brief EXTI7 configuration
*/
#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*! & lt; PA[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*! & lt; PB[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*! & lt; PC[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*! & lt; PD[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*! & lt; PE[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*! & lt; PF[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*! & lt; PG[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PH ((uint16_t)0x7000) /*! & lt; PH[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PI ((uint16_t)0x8000) /*! & lt; PI[7] pin */

/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*! & lt; EXTI 8 configuration */
#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*! & lt; EXTI 9 configuration */
#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*! & lt; EXTI 10 configuration */
#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*! & lt; EXTI 11 configuration */

/**
* @brief EXTI8 configuration
*/
#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*! & lt; PA[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*! & lt; PB[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*! & lt; PC[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*! & lt; PD[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*! & lt; PE[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*! & lt; PF[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*! & lt; PG[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PH ((uint16_t)0x0007) /*! & lt; PH[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PI ((uint16_t)0x0008) /*! & lt; PI[8] pin */
/**
* @brief EXTI9 configuration
*/
#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*! & lt; PA[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*! & lt; PB[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*! & lt; PC[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*! & lt; PD[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*! & lt; PE[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*! & lt; PF[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*! & lt; PG[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PH ((uint16_t)0x0070) /*! & lt; PH[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PI ((uint16_t)0x0080) /*! & lt; PI[9] pin */
/**
* @brief EXTI10 configuration
*/
#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*! & lt; PA[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*! & lt; PB[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*! & lt; PC[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*! & lt; PD[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*! & lt; PE[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*! & lt; PF[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*! & lt; PG[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PH ((uint16_t)0x0700) /*! & lt; PH[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PI ((uint16_t)0x0800) /*! & lt; PI[10] pin */
/**
* @brief EXTI11 configuration
*/
#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*! & lt; PA[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*! & lt; PB[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*! & lt; PC[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*! & lt; PD[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*! & lt; PE[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*! & lt; PF[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*! & lt; PG[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PH ((uint16_t)0x7000) /*! & lt; PH[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PI ((uint16_t)0x8000) /*! & lt; PI[11] pin */

/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*! & lt; EXTI 12 configuration */
#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*! & lt; EXTI 13 configuration */
#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*! & lt; EXTI 14 configuration */
#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*! & lt; EXTI 15 configuration */
/**
* @brief EXTI12 configuration
*/
#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*! & lt; PA[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*! & lt; PB[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*! & lt; PC[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*! & lt; PD[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*! & lt; PE[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*! & lt; PF[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*! & lt; PG[12] pin */
#define SYSCFG_EXTICR3_EXTI12_PH ((uint16_t)0x0007) /*! & lt; PH[12] pin */
/**
* @brief EXTI13 configuration
*/
#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*! & lt; PA[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*! & lt; PB[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*! & lt; PC[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*! & lt; PD[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*! & lt; PE[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*! & lt; PF[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*! & lt; PG[13] pin */
#define SYSCFG_EXTICR3_EXTI13_PH ((uint16_t)0x0070) /*! & lt; PH[13] pin */
/**
* @brief EXTI14 configuration
*/
#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*! & lt; PA[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*! & lt; PB[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*! & lt; PC[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*! & lt; PD[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*! & lt; PE[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*! & lt; PF[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*! & lt; PG[14] pin */
#define SYSCFG_EXTICR3_EXTI14_PH ((uint16_t)0x0700) /*! & lt; PH[14] pin */
/**
* @brief EXTI15 configuration
*/
#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*! & lt; PA[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*! & lt; PB[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*! & lt; PC[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*! & lt; PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*! & lt; PE[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*! & lt; PF[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*! & lt; PG[15] pin */
#define SYSCFG_EXTICR3_EXTI15_PH ((uint16_t)0x7000) /*! & lt; PH[15] pin */

/****************** Bit definition for SYSCFG_CMPCR register ****************/
#define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*! & lt; Compensation cell ready flag */
#define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*! & lt; Compensation cell power-down */

/******************************************************************************/
/* */
/* TIM */
/* */
/******************************************************************************/
/******************* Bit definition for TIM_CR1 register ********************/
#define TIM_CR1_CEN ((uint16_t)0x0001) /*! & lt; Counter enable */
#define TIM_CR1_UDIS ((uint16_t)0x0002) /*! & lt; Update disable */
#define TIM_CR1_URS ((uint16_t)0x0004) /*! & lt; Update request source */
#define TIM_CR1_OPM ((uint16_t)0x0008) /*! & lt; One pulse mode */
#define TIM_CR1_DIR ((uint16_t)0x0010) /*! & lt; Direction */

#define TIM_CR1_CMS ((uint16_t)0x0060) /*! & lt; CMS[1:0] bits (Center-aligned mode selection) */
#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*! & lt; Bit 0 */
#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*! & lt; Bit 1 */

#define TIM_CR1_ARPE ((uint16_t)0x0080) /*! & lt; Auto-reload preload enable */

#define TIM_CR1_CKD ((uint16_t)0x0300) /*! & lt; CKD[1:0] bits (clock division) */
#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*! & lt; Bit 0 */
#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*! & lt; Bit 1 */

/******************* Bit definition for TIM_CR2 register ********************/
#define TIM_CR2_CCPC ((uint16_t)0x0001) /*! & lt; Capture/Compare Preloaded Control */
#define TIM_CR2_CCUS ((uint16_t)0x0004) /*! & lt; Capture/Compare Control Update Selection */
#define TIM_CR2_CCDS ((uint16_t)0x0008) /*! & lt; Capture/Compare DMA Selection */

#define TIM_CR2_MMS ((uint16_t)0x0070) /*! & lt; MMS[2:0] bits (Master Mode Selection) */
#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*! & lt; Bit 0 */
#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*! & lt; Bit 1 */
#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*! & lt; Bit 2 */

#define TIM_CR2_TI1S ((uint16_t)0x0080) /*! & lt; TI1 Selection */
#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*! & lt; Output Idle state 1 (OC1 output) */
#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*! & lt; Output Idle state 1 (OC1N output) */
#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*! & lt; Output Idle state 2 (OC2 output) */
#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*! & lt; Output Idle state 2 (OC2N output) */
#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*! & lt; Output Idle state 3 (OC3 output) */
#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*! & lt; Output Idle state 3 (OC3N output) */
#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*! & lt; Output Idle state 4 (OC4 output) */

/******************* Bit definition for TIM_SMCR register *******************/
#define TIM_SMCR_SMS ((uint16_t)0x0007) /*! & lt; SMS[2:0] bits (Slave mode selection) */
#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*! & lt; Bit 0 */
#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*! & lt; Bit 1 */
#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*! & lt; Bit 2 */

#define TIM_SMCR_TS ((uint16_t)0x0070) /*! & lt; TS[2:0] bits (Trigger selection) */
#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*! & lt; Bit 0 */
#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*! & lt; Bit 1 */
#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*! & lt; Bit 2 */

#define TIM_SMCR_MSM ((uint16_t)0x0080) /*! & lt; Master/slave mode */

#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*! & lt; ETF[3:0] bits (External trigger filter) */
#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*! & lt; Bit 0 */
#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*! & lt; Bit 1 */
#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*! & lt; Bit 2 */
#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*! & lt; Bit 3 */

#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*! & lt; ETPS[1:0] bits (External trigger prescaler) */
#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*! & lt; Bit 0 */
#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*! & lt; Bit 1 */

#define TIM_SMCR_ECE ((uint16_t)0x4000) /*! & lt; External clock enable */
#define TIM_SMCR_ETP ((uint16_t)0x8000) /*! & lt; External trigger polarity */

/******************* Bit definition for TIM_DIER register *******************/
#define TIM_DIER_UIE ((uint16_t)0x0001) /*! & lt; Update interrupt enable */
#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*! & lt; Capture/Compare 1 interrupt enable */
#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*! & lt; Capture/Compare 2 interrupt enable */
#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*! & lt; Capture/Compare 3 interrupt enable */
#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*! & lt; Capture/Compare 4 interrupt enable */
#define TIM_DIER_COMIE ((uint16_t)0x0020) /*! & lt; COM interrupt enable */
#define TIM_DIER_TIE ((uint16_t)0x0040) /*! & lt; Trigger interrupt enable */
#define TIM_DIER_BIE ((uint16_t)0x0080) /*! & lt; Break interrupt enable */
#define TIM_DIER_UDE ((uint16_t)0x0100) /*! & lt; Update DMA request enable */
#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*! & lt; Capture/Compare 1 DMA request enable */
#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*! & lt; Capture/Compare 2 DMA request enable */
#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*! & lt; Capture/Compare 3 DMA request enable */
#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*! & lt; Capture/Compare 4 DMA request enable */
#define TIM_DIER_COMDE ((uint16_t)0x2000) /*! & lt; COM DMA request enable */
#define TIM_DIER_TDE ((uint16_t)0x4000) /*! & lt; Trigger DMA request enable */

/******************** Bit definition for TIM_SR register ********************/
#define TIM_SR_UIF ((uint16_t)0x0001) /*! & lt; Update interrupt Flag */
#define TIM_SR_CC1IF ((uint16_t)0x0002) /*! & lt; Capture/Compare 1 interrupt Flag */
#define TIM_SR_CC2IF ((uint16_t)0x0004) /*! & lt; Capture/Compare 2 interrupt Flag */
#define TIM_SR_CC3IF ((uint16_t)0x0008) /*! & lt; Capture/Compare 3 interrupt Flag */
#define TIM_SR_CC4IF ((uint16_t)0x0010) /*! & lt; Capture/Compare 4 interrupt Flag */
#define TIM_SR_COMIF ((uint16_t)0x0020) /*! & lt; COM interrupt Flag */
#define TIM_SR_TIF ((uint16_t)0x0040) /*! & lt; Trigger interrupt Flag */
#define TIM_SR_BIF ((uint16_t)0x0080) /*! & lt; Break interrupt Flag */
#define TIM_SR_CC1OF ((uint16_t)0x0200) /*! & lt; Capture/Compare 1 Overcapture Flag */
#define TIM_SR_CC2OF ((uint16_t)0x0400) /*! & lt; Capture/Compare 2 Overcapture Flag */
#define TIM_SR_CC3OF ((uint16_t)0x0800) /*! & lt; Capture/Compare 3 Overcapture Flag */
#define TIM_SR_CC4OF ((uint16_t)0x1000) /*! & lt; Capture/Compare 4 Overcapture Flag */

/******************* Bit definition for TIM_EGR register ********************/
#define TIM_EGR_UG ((uint8_t)0x01) /*! & lt; Update Generation */
#define TIM_EGR_CC1G ((uint8_t)0x02) /*! & lt; Capture/Compare 1 Generation */
#define TIM_EGR_CC2G ((uint8_t)0x04) /*! & lt; Capture/Compare 2 Generation */
#define TIM_EGR_CC3G ((uint8_t)0x08) /*! & lt; Capture/Compare 3 Generation */
#define TIM_EGR_CC4G ((uint8_t)0x10) /*! & lt; Capture/Compare 4 Generation */
#define TIM_EGR_COMG ((uint8_t)0x20) /*! & lt; Capture/Compare Control Update Generation */
#define TIM_EGR_TG ((uint8_t)0x40) /*! & lt; Trigger Generation */
#define TIM_EGR_BG ((uint8_t)0x80) /*! & lt; Break Generation */

/****************** Bit definition for TIM_CCMR1 register *******************/
#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*! & lt; CC1S[1:0] bits (Capture/Compare 1 Selection) */
#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*! & lt; Bit 0 */
#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*! & lt; Bit 1 */

#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*! & lt; Output Compare 1 Fast enable */
#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*! & lt; Output Compare 1 Preload enable */

#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*! & lt; OC1M[2:0] bits (Output Compare 1 Mode) */
#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*! & lt; Bit 0 */
#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*! & lt; Bit 1 */
#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*! & lt; Bit 2 */

#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*! & lt; Output Compare 1Clear Enable */

#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*! & lt; CC2S[1:0] bits (Capture/Compare 2 Selection) */
#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*! & lt; Bit 0 */
#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*! & lt; Bit 1 */

#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*! & lt; Output Compare 2 Fast enable */
#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*! & lt; Output Compare 2 Preload enable */

#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*! & lt; OC2M[2:0] bits (Output Compare 2 Mode) */
#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*! & lt; Bit 0 */
#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*! & lt; Bit 1 */
#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*! & lt; Bit 2 */

#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*! & lt; Output Compare 2 Clear Enable */

/*----------------------------------------------------------------------------*/

#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*! & lt; IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*! & lt; Bit 0 */
#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*! & lt; Bit 1 */

#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*! & lt; IC1F[3:0] bits (Input Capture 1 Filter) */
#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*! & lt; Bit 0 */
#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*! & lt; Bit 1 */
#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*! & lt; Bit 2 */
#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*! & lt; Bit 3 */

#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*! & lt; IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*! & lt; Bit 0 */
#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*! & lt; Bit 1 */

#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*! & lt; IC2F[3:0] bits (Input Capture 2 Filter) */
#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*! & lt; Bit 0 */
#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*! & lt; Bit 1 */
#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*! & lt; Bit 2 */
#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*! & lt; Bit 3 */

/****************** Bit definition for TIM_CCMR2 register *******************/
#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*! & lt; CC3S[1:0] bits (Capture/Compare 3 Selection) */
#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*! & lt; Bit 0 */
#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*! & lt; Bit 1 */

#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*! & lt; Output Compare 3 Fast enable */
#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*! & lt; Output Compare 3 Preload enable */

#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*! & lt; OC3M[2:0] bits (Output Compare 3 Mode) */
#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*! & lt; Bit 0 */
#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*! & lt; Bit 1 */
#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*! & lt; Bit 2 */

#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*! & lt; Output Compare 3 Clear Enable */

#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*! & lt; CC4S[1:0] bits (Capture/Compare 4 Selection) */
#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*! & lt; Bit 0 */
#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*! & lt; Bit 1 */

#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*! & lt; Output Compare 4 Fast enable */
#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*! & lt; Output Compare 4 Preload enable */

#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*! & lt; OC4M[2:0] bits (Output Compare 4 Mode) */
#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*! & lt; Bit 0 */
#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*! & lt; Bit 1 */
#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*! & lt; Bit 2 */

#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*! & lt; Output Compare 4 Clear Enable */

/*----------------------------------------------------------------------------*/

#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*! & lt; IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*! & lt; Bit 0 */
#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*! & lt; Bit 1 */

#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*! & lt; IC3F[3:0] bits (Input Capture 3 Filter) */
#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*! & lt; Bit 0 */
#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*! & lt; Bit 1 */
#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*! & lt; Bit 2 */
#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*! & lt; Bit 3 */

#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*! & lt; IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*! & lt; Bit 0 */
#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*! & lt; Bit 1 */

#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*! & lt; IC4F[3:0] bits (Input Capture 4 Filter) */
#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*! & lt; Bit 0 */
#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*! & lt; Bit 1 */
#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*! & lt; Bit 2 */
#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*! & lt; Bit 3 */

/******************* Bit definition for TIM_CCER register *******************/
#define TIM_CCER_CC1E ((uint16_t)0x0001) /*! & lt; Capture/Compare 1 output enable */
#define TIM_CCER_CC1P ((uint16_t)0x0002) /*! & lt; Capture/Compare 1 output Polarity */
#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*! & lt; Capture/Compare 1 Complementary output enable */
#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*! & lt; Capture/Compare 1 Complementary output Polarity */
#define TIM_CCER_CC2E ((uint16_t)0x0010) /*! & lt; Capture/Compare 2 output enable */
#define TIM_CCER_CC2P ((uint16_t)0x0020) /*! & lt; Capture/Compare 2 output Polarity */
#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*! & lt; Capture/Compare 2 Complementary output enable */
#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*! & lt; Capture/Compare 2 Complementary output Polarity */
#define TIM_CCER_CC3E ((uint16_t)0x0100) /*! & lt; Capture/Compare 3 output enable */
#define TIM_CCER_CC3P ((uint16_t)0x0200) /*! & lt; Capture/Compare 3 output Polarity */
#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*! & lt; Capture/Compare 3 Complementary output enable */
#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*! & lt; Capture/Compare 3 Complementary output Polarity */
#define TIM_CCER_CC4E ((uint16_t)0x1000) /*! & lt; Capture/Compare 4 output enable */
#define TIM_CCER_CC4P ((uint16_t)0x2000) /*! & lt; Capture/Compare 4 output Polarity */
#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*! & lt; Capture/Compare 4 Complementary output Polarity */

/******************* Bit definition for TIM_CNT register ********************/
#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*! & lt; Counter Value */

/******************* Bit definition for TIM_PSC register ********************/
#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*! & lt; Prescaler Value */

/******************* Bit definition for TIM_ARR register ********************/
#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*! & lt; actual auto-reload Value */

/******************* Bit definition for TIM_RCR register ********************/
#define TIM_RCR_REP ((uint8_t)0xFF) /*! & lt; Repetition Counter Value */

/******************* Bit definition for TIM_CCR1 register *******************/
#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*! & lt; Capture/Compare 1 Value */

/******************* Bit definition for TIM_CCR2 register *******************/
#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*! & lt; Capture/Compare 2 Value */

/******************* Bit definition for TIM_CCR3 register *******************/
#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*! & lt; Capture/Compare 3 Value */

/******************* Bit definition for TIM_CCR4 register *******************/
#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*! & lt; Capture/Compare 4 Value */

/******************* Bit definition for TIM_BDTR register *******************/
#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*! & lt; DTG[0:7] bits (Dead-Time Generator set-up) */
#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*! & lt; Bit 0 */
#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*! & lt; Bit 1 */
#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*! & lt; Bit 2 */
#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*! & lt; Bit 3 */
#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*! & lt; Bit 4 */
#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*! & lt; Bit 5 */
#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*! & lt; Bit 6 */
#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*! & lt; Bit 7 */

#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*! & lt; LOCK[1:0] bits (Lock Configuration) */
#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*! & lt; Bit 0 */
#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*! & lt; Bit 1 */

#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*! & lt; Off-State Selection for Idle mode */
#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*! & lt; Off-State Selection for Run mode */
#define TIM_BDTR_BKE ((uint16_t)0x1000) /*! & lt; Break enable */
#define TIM_BDTR_BKP ((uint16_t)0x2000) /*! & lt; Break Polarity */
#define TIM_BDTR_AOE ((uint16_t)0x4000) /*! & lt; Automatic Output enable */
#define TIM_BDTR_MOE ((uint16_t)0x8000) /*! & lt; Main Output enable */

/******************* Bit definition for TIM_DCR register ********************/
#define TIM_DCR_DBA ((uint16_t)0x001F) /*! & lt; DBA[4:0] bits (DMA Base Address) */
#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*! & lt; Bit 0 */
#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*! & lt; Bit 1 */
#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*! & lt; Bit 2 */
#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*! & lt; Bit 3 */
#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*! & lt; Bit 4 */

#define TIM_DCR_DBL ((uint16_t)0x1F00) /*! & lt; DBL[4:0] bits (DMA Burst Length) */
#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*! & lt; Bit 0 */
#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*! & lt; Bit 1 */
#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*! & lt; Bit 2 */
#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*! & lt; Bit 3 */
#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*! & lt; Bit 4 */

/******************* Bit definition for TIM_DMAR register *******************/
#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*! & lt; DMA register for burst accesses */

/******************* Bit definition for TIM_OR register *********************/
#define TIM_OR_TI4_RMP ((uint16_t)0x00C0) /*! & lt; TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
#define TIM_OR_TI4_RMP_0 ((uint16_t)0x0040) /*! & lt; Bit 0 */
#define TIM_OR_TI4_RMP_1 ((uint16_t)0x0080) /*! & lt; Bit 1 */
#define TIM_OR_ITR1_RMP ((uint16_t)0x0C00) /*! & lt; ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
#define TIM_OR_ITR1_RMP_0 ((uint16_t)0x0400) /*! & lt; Bit 0 */
#define TIM_OR_ITR1_RMP_1 ((uint16_t)0x0800) /*! & lt; Bit 1 */


/******************************************************************************/
/* */
/* Universal Synchronous Asynchronous Receiver Transmitter */
/* */
/******************************************************************************/
/******************* Bit definition for USART_SR register *******************/
#define USART_SR_PE ((uint16_t)0x0001) /*! & lt; Parity Error */
#define USART_SR_FE ((uint16_t)0x0002) /*! & lt; Framing Error */
#define USART_SR_NE ((uint16_t)0x0004) /*! & lt; Noise Error Flag */
#define USART_SR_ORE ((uint16_t)0x0008) /*! & lt; OverRun Error */
#define USART_SR_IDLE ((uint16_t)0x0010) /*! & lt; IDLE line detected */
#define USART_SR_RXNE ((uint16_t)0x0020) /*! & lt; Read Data Register Not Empty */
#define USART_SR_TC ((uint16_t)0x0040) /*! & lt; Transmission Complete */
#define USART_SR_TXE ((uint16_t)0x0080) /*! & lt; Transmit Data Register Empty */
#define USART_SR_LBD ((uint16_t)0x0100) /*! & lt; LIN Break Detection Flag */
#define USART_SR_CTS ((uint16_t)0x0200) /*! & lt; CTS Flag */

/******************* Bit definition for USART_DR register *******************/
#define USART_DR_DR ((uint16_t)0x01FF) /*! & lt; Data value */

/****************** Bit definition for USART_BRR register *******************/
#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*! & lt; Fraction of USARTDIV */
#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*! & lt; Mantissa of USARTDIV */

/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_SBK ((uint16_t)0x0001) /*! & lt; Send Break */
#define USART_CR1_RWU ((uint16_t)0x0002) /*! & lt; Receiver wakeup */
#define USART_CR1_RE ((uint16_t)0x0004) /*! & lt; Receiver Enable */
#define USART_CR1_TE ((uint16_t)0x0008) /*! & lt; Transmitter Enable */
#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*! & lt; IDLE Interrupt Enable */
#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*! & lt; RXNE Interrupt Enable */
#define USART_CR1_TCIE ((uint16_t)0x0040) /*! & lt; Transmission Complete Interrupt Enable */
#define USART_CR1_TXEIE ((uint16_t)0x0080) /*! & lt; PE Interrupt Enable */
#define USART_CR1_PEIE ((uint16_t)0x0100) /*! & lt; PE Interrupt Enable */
#define USART_CR1_PS ((uint16_t)0x0200) /*! & lt; Parity Selection */
#define USART_CR1_PCE ((uint16_t)0x0400) /*! & lt; Parity Control Enable */
#define USART_CR1_WAKE ((uint16_t)0x0800) /*! & lt; Wakeup method */
#define USART_CR1_M ((uint16_t)0x1000) /*! & lt; Word length */
#define USART_CR1_UE ((uint16_t)0x2000) /*! & lt; USART Enable */
#define USART_CR1_OVER8 ((uint16_t)0x8000) /*! & lt; USART Oversampling by 8 enable */

/****************** Bit definition for USART_CR2 register *******************/
#define USART_CR2_ADD ((uint16_t)0x000F) /*! & lt; Address of the USART node */
#define USART_CR2_LBDL ((uint16_t)0x0020) /*! & lt; LIN Break Detection Length */
#define USART_CR2_LBDIE ((uint16_t)0x0040) /*! & lt; LIN Break Detection Interrupt Enable */
#define USART_CR2_LBCL ((uint16_t)0x0100) /*! & lt; Last Bit Clock pulse */
#define USART_CR2_CPHA ((uint16_t)0x0200) /*! & lt; Clock Phase */
#define USART_CR2_CPOL ((uint16_t)0x0400) /*! & lt; Clock Polarity */
#define USART_CR2_CLKEN ((uint16_t)0x0800) /*! & lt; Clock Enable */

#define USART_CR2_STOP ((uint16_t)0x3000) /*! & lt; STOP[1:0] bits (STOP bits) */
#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*! & lt; Bit 0 */
#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*! & lt; Bit 1 */

#define USART_CR2_LINEN ((uint16_t)0x4000) /*! & lt; LIN mode enable */

/****************** Bit definition for USART_CR3 register *******************/
#define USART_CR3_EIE ((uint16_t)0x0001) /*! & lt; Error Interrupt Enable */
#define USART_CR3_IREN ((uint16_t)0x0002) /*! & lt; IrDA mode Enable */
#define USART_CR3_IRLP ((uint16_t)0x0004) /*! & lt; IrDA Low-Power */
#define USART_CR3_HDSEL ((uint16_t)0x0008) /*! & lt; Half-Duplex Selection */
#define USART_CR3_NACK ((uint16_t)0x0010) /*! & lt; Smartcard NACK enable */
#define USART_CR3_SCEN ((uint16_t)0x0020) /*! & lt; Smartcard mode enable */
#define USART_CR3_DMAR ((uint16_t)0x0040) /*! & lt; DMA Enable Receiver */
#define USART_CR3_DMAT ((uint16_t)0x0080) /*! & lt; DMA Enable Transmitter */
#define USART_CR3_RTSE ((uint16_t)0x0100) /*! & lt; RTS Enable */
#define USART_CR3_CTSE ((uint16_t)0x0200) /*! & lt; CTS Enable */
#define USART_CR3_CTSIE ((uint16_t)0x0400) /*! & lt; CTS Interrupt Enable */
#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*! & lt; USART One bit method enable */

/****************** Bit definition for USART_GTPR register ******************/
#define USART_GTPR_PSC ((uint16_t)0x00FF) /*! & lt; PSC[7:0] bits (Prescaler value) */
#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*! & lt; Bit 0 */
#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*! & lt; Bit 1 */
#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*! & lt; Bit 2 */
#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*! & lt; Bit 3 */
#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*! & lt; Bit 4 */
#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*! & lt; Bit 5 */
#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*! & lt; Bit 6 */
#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*! & lt; Bit 7 */

#define USART_GTPR_GT ((uint16_t)0xFF00) /*! & lt; Guard time value */

/******************************************************************************/
/* */
/* Window WATCHDOG */
/* */
/******************************************************************************/
/******************* Bit definition for WWDG_CR register ********************/
#define WWDG_CR_T ((uint8_t)0x7F) /*! & lt; T[6:0] bits (7-Bit counter (MSB to LSB)) */
#define WWDG_CR_T0 ((uint8_t)0x01) /*! & lt; Bit 0 */
#define WWDG_CR_T1 ((uint8_t)0x02) /*! & lt; Bit 1 */
#define WWDG_CR_T2 ((uint8_t)0x04) /*! & lt; Bit 2 */
#define WWDG_CR_T3 ((uint8_t)0x08) /*! & lt; Bit 3 */
#define WWDG_CR_T4 ((uint8_t)0x10) /*! & lt; Bit 4 */
#define WWDG_CR_T5 ((uint8_t)0x20) /*! & lt; Bit 5 */
#define WWDG_CR_T6 ((uint8_t)0x40) /*! & lt; Bit 6 */

#define WWDG_CR_WDGA ((uint8_t)0x80) /*! & lt; Activation bit */

/******************* Bit definition for WWDG_CFR register *******************/
#define WWDG_CFR_W ((uint16_t)0x007F) /*! & lt; W[6:0] bits (7-bit window value) */
#define WWDG_CFR_W0 ((uint16_t)0x0001) /*! & lt; Bit 0 */
#define WWDG_CFR_W1 ((uint16_t)0x0002) /*! & lt; Bit 1 */
#define WWDG_CFR_W2 ((uint16_t)0x0004) /*! & lt; Bit 2 */
#define WWDG_CFR_W3 ((uint16_t)0x0008) /*! & lt; Bit 3 */
#define WWDG_CFR_W4 ((uint16_t)0x0010) /*! & lt; Bit 4 */
#define WWDG_CFR_W5 ((uint16_t)0x0020) /*! & lt; Bit 5 */
#define WWDG_CFR_W6 ((uint16_t)0x0040) /*! & lt; Bit 6 */

#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*! & lt; WDGTB[1:0] bits (Timer Base) */
#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*! & lt; Bit 0 */
#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*! & lt; Bit 1 */

#define WWDG_CFR_EWI ((uint16_t)0x0200) /*! & lt; Early Wakeup Interrupt */

/******************* Bit definition for WWDG_SR register ********************/
#define WWDG_SR_EWIF ((uint8_t)0x01) /*! & lt; Early Wakeup Interrupt Flag */


/******************************************************************************/
/* */
/* DBG */
/* */
/******************************************************************************/
/******************** Bit definition for DBGMCU_IDCODE register *************/
#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)

/******************** Bit definition for DBGMCU_CR register *****************/
#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)

#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*! & lt; Bit 0 */
#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*! & lt; Bit 1 */

/******************** Bit definition for DBGMCU_APB1_FZ register ************/
#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
#define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
#define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
#define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
/* Old IWDGSTOP bit definition, maintained for legacy purpose */
#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP

/******************** Bit definition for DBGMCU_APB2_FZ register ************/
#define DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
#define DBGMCU_APB1_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
#define DBGMCU_APB1_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
#define DBGMCU_APB1_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
#define DBGMCU_APB1_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)

/******************************************************************************/
/* */
/* Ethernet MAC Registers bits definitions */
/* */
/******************************************************************************/
/* Bit definition for Ethernet MAC Control Register register */
#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
#define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
#define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
#define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
#define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
#define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
#define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
#define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
#define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
a transmission attempt during retries after a collision: 0 = & lt; r & lt; 2^k */
#define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
#define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
#define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
#define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */

/* Bit definition for Ethernet MAC Frame Filter Register */
#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
#define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
#define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */

/* Bit definition for Ethernet MAC Hash Table High Register */
#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */

/* Bit definition for Ethernet MAC Hash Table Low Register */
#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */

/* Bit definition for Ethernet MAC MII Address Register */
#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
#define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
#define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
#define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
#define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
#define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */

/* Bit definition for Ethernet MAC MII Data Register */
#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */

/* Bit definition for Ethernet MAC Flow Control Register */
#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
#define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
#define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
#define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
#define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */

/* Bit definition for Ethernet MAC VLAN Tag Register */
#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */

/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
RSVD - Filter1 Command - RSVD - Filter0 Command
Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */

/* Bit definition for Ethernet MAC PMT Control and Status Register */
#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */

/* Bit definition for Ethernet MAC Status Register */
#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */

/* Bit definition for Ethernet MAC Interrupt Mask Register */
#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */

/* Bit definition for Ethernet MAC Address0 High Register */
#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */

/* Bit definition for Ethernet MAC Address0 Low Register */
#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */

/* Bit definition for Ethernet MAC Address1 High Register */
#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
#define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
#define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
#define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
#define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
#define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
#define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */

/* Bit definition for Ethernet MAC Address1 Low Register */
#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */

/* Bit definition for Ethernet MAC Address2 High Register */
#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
#define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
#define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
#define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
#define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
#define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
#define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */

/* Bit definition for Ethernet MAC Address2 Low Register */
#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */

/* Bit definition for Ethernet MAC Address3 High Register */
#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
#define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
#define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
#define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
#define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
#define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
#define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */

/* Bit definition for Ethernet MAC Address3 Low Register */
#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */

/******************************************************************************/
/* Ethernet MMC Registers bits definition */
/******************************************************************************/

/* Bit definition for Ethernet MMC Contol Register */
#define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
#define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */

/* Bit definition for Ethernet MMC Receive Interrupt Register */
#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */

/* Bit definition for Ethernet MMC Transmit Interrupt Register */
#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */

/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */

/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */

/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */

/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */

/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */

/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */

/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */

/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */

/******************************************************************************/
/* Ethernet PTP Registers bits definition */
/******************************************************************************/

/* Bit definition for Ethernet PTP Time Stamp Contol Register */
#define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
#define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
#define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
#define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
#define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
#define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
#define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
#define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
#define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */

#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */

/* Bit definition for Ethernet PTP Sub-Second Increment Register */
#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */

/* Bit definition for Ethernet PTP Time Stamp High Register */
#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */

/* Bit definition for Ethernet PTP Time Stamp Low Register */
#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */

/* Bit definition for Ethernet PTP Time Stamp High Update Register */
#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */

/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */

/* Bit definition for Ethernet PTP Time Stamp Addend Register */
#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */

/* Bit definition for Ethernet PTP Target Time High Register */
#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */

/* Bit definition for Ethernet PTP Target Time Low Register */
#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */

/* Bit definition for Ethernet PTP Time Stamp Status Register */
#define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
#define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */

/******************************************************************************/
/* Ethernet DMA Registers bits definition */
/******************************************************************************/

/* Bit definition for Ethernet DMA Bus Mode Register */
#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
#define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
#define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
#define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
#define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
#define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
#define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
#define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
#define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
#define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
#define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
#define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
#define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
#define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
#define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
#define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
#define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
#define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
#define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
#define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
#define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
#define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
#define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
#define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
#define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
#define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
#define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
#define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
#define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
#define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */

/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */

/* Bit definition for Ethernet DMA Receive Poll Demand Register */
#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */

/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */

/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */

/* Bit definition for Ethernet DMA Status Register */
#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
/* combination with EBS[2:0] for GetFlagStatus function */
#define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
#define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
#define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
#define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
#define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
#define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
#define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
#define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
#define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
#define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
#define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
#define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
#define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
#define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
#define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */

/* Bit definition for Ethernet DMA Operation Mode Register */
#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
#define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
#define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
#define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
#define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
#define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
#define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
#define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
#define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
#define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
#define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
#define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
#define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */

/* Bit definition for Ethernet DMA Interrupt Enable Register */
#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */

/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */

/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */

/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */

/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */

/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */

/**
* @}
*/

/**
* @}
*/

#ifdef USE_STDPERIPH_DRIVER
#include " stm32f4xx_conf.h "
#endif /* USE_STDPERIPH_DRIVER */

/** @addtogroup Exported_macro
* @{
*/

#define SET_BIT(REG, BIT) ((REG) |= (BIT))

#define CLEAR_BIT(REG, BIT) ((REG) & = ~(BIT))

#define READ_BIT(REG, BIT) ((REG) & (BIT))

#define CLEAR_REG(REG) ((REG) = (0x0))

#define WRITE_REG(REG, VAL) ((REG) = (VAL))

#define READ_REG(REG) ((REG))

#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))

/**
* @}
*/

#ifdef __cplusplus
}
#endif /* __cplusplus */

#endif /* __STM32F4xx_H */

/**
* @}
*/

/**
* @}
*/

/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


wma_dec.ZIP > stm32f4xx_dac.h

/**
******************************************************************************
* @file stm32f4xx_dac.h
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the DAC firmware
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* & lt; h2 & gt; & lt; center & gt; & copy; COPYRIGHT 2011 STMicroelectronics & lt; /center & gt; & lt; /h2 & gt;
******************************************************************************
*/

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_DAC_H
#define __STM32F4xx_DAC_H

#ifdef __cplusplus
extern " C " {
#endif

/* Includes ------------------------------------------------------------------*/
#include " stm32f4xx.h "

/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/

/** @addtogroup DAC
* @{
*/

/* Exported types ------------------------------------------------------------*/

/**
* @brief DAC Init structure definition
*/

typedef struct
{
uint32_t DAC_Trigger; /*! & lt; Specifies the external trigger for the selected DAC channel.
This parameter can be a value of @ref DAC_trigger_selection */

uint32_t DAC_WaveGeneration; /*! & lt; Specifies whether DAC channel noise waves or triangle waves
are generated, or whether no wave is generated.
This parameter can be a value of @ref DAC_wave_generation */

uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*! & lt; Specifies the LFSR mask for noise wave generation or
the maximum amplitude triangle generation for the DAC channel.
This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */

uint32_t DAC_OutputBuffer; /*! & lt; Specifies whether the DAC channel output buffer is enabled or disabled.
This parameter can be a value of @ref DAC_output_buffer */
}DAC_InitTypeDef;

/* Exported constants --------------------------------------------------------*/

/** @defgroup DAC_Exported_Constants
* @{
*/

/** @defgroup DAC_trigger_selection
* @{
*/

#define DAC_Trigger_None ((uint32_t)0x00000000) /*! & lt; Conversion is automatic once the DAC1_DHRxxxx register
has been loaded, and not by external trigger */
#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*! & lt; TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*! & lt; TIM4 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*! & lt; TIM5 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*! & lt; TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*! & lt; TIM7 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*! & lt; TIM8 TRGO selected as external conversion trigger for DAC channel */

#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*! & lt; EXTI Line9 event selected as external conversion trigger for DAC channel */
#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*! & lt; Conversion started by software trigger for DAC channel */

#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
((TRIGGER) == DAC_Trigger_T6_TRGO) || \
((TRIGGER) == DAC_Trigger_T8_TRGO) || \
((TRIGGER) == DAC_Trigger_T7_TRGO) || \
((TRIGGER) == DAC_Trigger_T5_TRGO) || \
((TRIGGER) == DAC_Trigger_T2_TRGO) || \
((TRIGGER) == DAC_Trigger_T4_TRGO) || \
((TRIGGER) == DAC_Trigger_Ext_IT9) || \
((TRIGGER) == DAC_Trigger_Software))

/**
* @}
*/

/** @defgroup DAC_wave_generation
* @{
*/

#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
((WAVE) == DAC_WaveGeneration_Noise) || \
((WAVE) == DAC_WaveGeneration_Triangle))
/**
* @}
*/

/** @defgroup DAC_lfsrunmask_triangleamplitude
* @{
*/

#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*! & lt; Unmask DAC channel LFSR bit0 for noise wave generation */
#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*! & lt; Unmask DAC channel LFSR bit[1:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*! & lt; Unmask DAC channel LFSR bit[2:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*! & lt; Unmask DAC channel LFSR bit[3:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*! & lt; Unmask DAC channel LFSR bit[4:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*! & lt; Unmask DAC channel LFSR bit[5:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*! & lt; Unmask DAC channel LFSR bit[6:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*! & lt; Unmask DAC channel LFSR bit[7:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*! & lt; Unmask DAC channel LFSR bit[8:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*! & lt; Unmask DAC channel LFSR bit[9:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*! & lt; Unmask DAC channel LFSR bit[10:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*! & lt; Unmask DAC channel LFSR bit[11:0] for noise wave generation */
#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*! & lt; Select max triangle amplitude of 1 */
#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*! & lt; Select max triangle amplitude of 3 */
#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*! & lt; Select max triangle amplitude of 7 */
#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*! & lt; Select max triangle amplitude of 15 */
#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*! & lt; Select max triangle amplitude of 31 */
#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*! & lt; Select max triangle amplitude of 63 */
#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*! & lt; Select max triangle amplitude of 127 */
#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*! & lt; Select max triangle amplitude of 255 */
#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*! & lt; Select max triangle amplitude of 511 */
#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*! & lt; Select max triangle amplitude of 1023 */
#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*! & lt; Select max triangle amplitude of 2047 */
#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*! & lt; Select max triangle amplitude of 4095 */

#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
((VALUE) == DAC_TriangleAmplitude_1) || \
((VALUE) == DAC_TriangleAmplitude_3) || \
((VALUE) == DAC_TriangleAmplitude_7) || \
((VALUE) == DAC_TriangleAmplitude_15) || \
((VALUE) == DAC_TriangleAmplitude_31) || \
((VALUE) == DAC_TriangleAmplitude_63) || \
((VALUE) == DAC_TriangleAmplitude_127) || \
((VALUE) == DAC_TriangleAmplitude_255) || \
((VALUE) == DAC_TriangleAmplitude_511) || \
((VALUE) == DAC_TriangleAmplitude_1023) || \
((VALUE) == DAC_TriangleAmplitude_2047) || \
((VALUE) == DAC_TriangleAmplitude_4095))
/**
* @}
*/

/** @defgroup DAC_output_buffer
* @{
*/

#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
((STATE) == DAC_OutputBuffer_Disable))
/**
* @}
*/

/** @defgroup DAC_Channel_selection
* @{
*/

#define DAC_Channel_1 ((uint32_t)0x00000000)
#define DAC_Channel_2 ((uint32_t)0x00000010)
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
((CHANNEL) == DAC_Channel_2))
/**
* @}
*/

/** @defgroup DAC_data_alignement
* @{
*/

#define DAC_Align_12b_R ((uint32_t)0x00000000)
#define DAC_Align_12b_L ((uint32_t)0x00000004)
#define DAC_Align_8b_R ((uint32_t)0x00000008)
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
((ALIGN) == DAC_Align_12b_L) || \
((ALIGN) == DAC_Align_8b_R))
/**
* @}
*/

/** @defgroup DAC_wave_generation
* @{
*/

#define DAC_Wave_Noise ((uint32_t)0x00000040)
#define DAC_Wave_Triangle ((uint32_t)0x00000080)
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
((WAVE) == DAC_Wave_Triangle))
/**
* @}
*/

/** @defgroup DAC_data
* @{
*/

#define IS_DAC_DATA(DATA) ((DATA) & lt; = 0xFFF0)
/**
* @}
*/

/** @defgroup DAC_interrupts_definition
* @{
*/
#define DAC_IT_DMAUDR ((uint32_t)0x00002000)
#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))

/**
* @}
*/

/** @defgroup DAC_flags_definition
* @{
*/

#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000)
#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))

/**
* @}
*/

/**
* @}
*/

/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/

/* Function used to set the DAC configuration to the default reset state *****/
void DAC_DeInit(void);

/* DAC channels configuration: trigger, output buffer, data format functions */
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);

/* DMA management functions ***************************************************/
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);

/* Interrupts and flags management functions **********************************/
void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);

#ifdef __cplusplus
}
#endif

#endif /*__STM32F4xx_DAC_H */

/**
* @}
*/

/**
* @}
*/

/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


wma_dec.ZIP > dma.c

#include " includes.h "


/**
* @brief Deinitialize the DMAy Streamx registers to their default reset values.
* @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
* to 7 to select the DMA Stream.
* @retval None
*/
void DMA_DeInit(DMA_Stream_TypeDef *DMAy_Streamx)
{
DMAy_Streamx- & gt; CR & = ~((uint32_t)DMA_SxCR_EN); /* Disable the selected DMAy Streamx */
DMAy_Streamx- & gt; CR = 0; /* Reset DMAy Streamx control register */
DMAy_Streamx- & gt; NDTR = 0; /* Reset DMAy Streamx Number of Data to Transfer register */
DMAy_Streamx- & gt; PAR = 0; /* Reset DMAy Streamx peripheral address register */
DMAy_Streamx- & gt; M0AR = 0; /* Reset DMAy Streamx memory 0 address register */
DMAy_Streamx- & gt; M1AR = 0; /* Reset DMAy Streamx memory 1 address register */
DMAy_Streamx- & gt; FCR = (uint32_t)0x00000021; /* Reset DMAy Streamx FIFO control register */
/* Reset interrupt pending bits for the selected stream */
if (DMAy_Streamx == DMA1_Stream0)
{
DMA1- & gt; LIFCR = DMA_Stream0_IT_MASK; /* Reset interrupt pending bits for DMA1 Stream0 */
}
else if (DMAy_Streamx == DMA1_Stream1)
{
DMA1- & gt; LIFCR = DMA_Stream1_IT_MASK; /* Reset interrupt pending bits for DMA1 Stream1 */
}
else if (DMAy_Streamx == DMA1_Stream2)
{
DMA1- & gt; LIFCR = DMA_Stream2_IT_MASK; /* Reset interrupt pending bits for DMA1 Stream2 */
}
else if (DMAy_Streamx == DMA1_Stream3)
{
DMA1- & gt; LIFCR = DMA_Stream3_IT_MASK; /* Reset interrupt pending bits for DMA1 Stream3 */
}
else if (DMAy_Streamx == DMA1_Stream4)
{
DMA1- & gt; HIFCR = DMA_Stream4_IT_MASK; /* Reset interrupt pending bits for DMA1 Stream4 */
}
else if (DMAy_Streamx == DMA1_Stream5)
{
DMA1- & gt; HIFCR = DMA_Stream5_IT_MASK; /* Reset interrupt pending bits for DMA1 Stream5 */
}
else if (DMAy_Streamx == DMA1_Stream6)
{
DMA1- & gt; HIFCR = (uint32_t)DMA_Stream6_IT_MASK; /* Reset interrupt pending bits for DMA1 Stream6 */
}
else if (DMAy_Streamx == DMA1_Stream7)
{
DMA1- & gt; HIFCR = DMA_Stream7_IT_MASK; /* Reset interrupt pending bits for DMA1 Stream7 */
}
else if (DMAy_Streamx == DMA2_Stream0)
{
DMA2- & gt; LIFCR = DMA_Stream0_IT_MASK; /* Reset interrupt pending bits for DMA2 Stream0 */
}
else if (DMAy_Streamx == DMA2_Stream1)
{
DMA2- & gt; LIFCR = DMA_Stream1_IT_MASK; /* Reset interrupt pending bits for DMA2 Stream1 */
}
else if (DMAy_Streamx == DMA2_Stream2)
{
DMA2- & gt; LIFCR = DMA_Stream2_IT_MASK; /* Reset interrupt pending bits for DMA2 Stream2 */
}
else if (DMAy_Streamx == DMA2_Stream3)
{
DMA2- & gt; LIFCR = DMA_Stream3_IT_MASK; /* Reset interrupt pending bits for DMA2 Stream3 */
}
else if (DMAy_Streamx == DMA2_Stream4)
{
DMA2- & gt; HIFCR = DMA_Stream4_IT_MASK; /* Reset interrupt pending bits for DMA2 Stream4 */
}
else if (DMAy_Streamx == DMA2_Stream5)
{
DMA2- & gt; HIFCR = DMA_Stream5_IT_MASK; /* Reset interrupt pending bits for DMA2 Stream5 */
}
else if (DMAy_Streamx == DMA2_Stream6)
{
DMA2- & gt; HIFCR = DMA_Stream6_IT_MASK; /* Reset interrupt pending bits for DMA2 Stream6 */
}
else
{
if (DMAy_Streamx == DMA2_Stream7)
{
DMA2- & gt; HIFCR = DMA_Stream7_IT_MASK; /* Reset interrupt pending bits for DMA2 Stream7 */
}
}
}




/**
* @brief Initializes the DMAy Streamx according to the specified parameters in
* the DMA_InitStruct structure.
* @note Before calling this function, it is recommended to check that the Stream
* is actually disabled using the function DMA_GetCmdStatus().
* @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
* to 7 to select the DMA Stream.
* @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval None
*/
void DMA_Init(DMA_Stream_TypeDef *DMAy_Streamx, DMA_InitTypeDef *DMA_InitStruct)
{
uint32_t tmpreg = 0;
/*------------------------- DMAy Streamx CR Configuration ------------------*/
tmpreg = DMAy_Streamx- & gt; CR; // Get the DMAy_Streamx CR value
/* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
tmpreg & = ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
DMA_SxCR_DIR));
/* Configure DMAy Streamx: */
/* Set CHSEL bits according to DMA_CHSEL value */
/* Set DIR bits according to DMA_DIR value */
/* Set PINC bit according to DMA_PeripheralInc value */
/* Set MINC bit according to DMA_MemoryInc value */
/* Set PSIZE bits according to DMA_PeripheralDataSize value */
/* Set MSIZE bits according to DMA_MemoryDataSize value */
/* Set CIRC bit according to DMA_Mode value */
/* Set PL bits according to DMA_Priority value */
/* Set MBURST bits according to DMA_MemoryBurst value */
/* Set PBURST bits according to DMA_PeripheralBurst value */
tmpreg = tmpreg | (DMA_InitStruct- & gt; DMA_Channel | DMA_InitStruct- & gt; DMA_DIR |
DMA_InitStruct- & gt; DMA_PeripheralInc | DMA_InitStruct- & gt; DMA_MemoryInc |
DMA_InitStruct- & gt; DMA_PeripheralDataSize | DMA_InitStruct- & gt; DMA_MemoryDataSize |
DMA_InitStruct- & gt; DMA_Mode | DMA_InitStruct- & gt; DMA_Priority |
DMA_InitStruct- & gt; DMA_MemoryBurst | DMA_InitStruct- & gt; DMA_PeripheralBurst);
DMAy_Streamx- & gt; CR = tmpreg; // Write to DMAy Streamx CR register
/*------------------------- DMAy Streamx FCR Configuration -----------------*/
tmpreg = DMAy_Streamx- & gt; FCR; // Get the DMAy_Streamx FCR value
tmpreg = tmpreg & (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); // Clear DMDIS and FTH bits
/* Configure DMAy Streamx FIFO:
Set DMDIS bits according to DMA_FIFOMode value
Set FTH bits according to DMA_FIFOThreshold value */
tmpreg = tmpreg | (DMA_InitStruct- & gt; DMA_FIFOMode | DMA_InitStruct- & gt; DMA_FIFOThreshold);
DMAy_Streamx- & gt; FCR = tmpreg; // Write to DMAy Streamx FCR
/*------------------------- DMAy Streamx NDTR Configuration ----------------*/
DMAy_Streamx- & gt; NDTR = DMA_InitStruct- & gt; DMA_BufferSize; // Write to DMAy Streamx NDTR register
/*------------------------- DMAy Streamx PAR Configuration -----------------*/
DMAy_Streamx- & gt; PAR = DMA_InitStruct- & gt; DMA_PeripheralBaseAddr;// Write to DMAy Streamx PAR
/*------------------------- DMAy Streamx M0AR Configuration ----------------*/
DMAy_Streamx- & gt; M0AR = DMA_InitStruct- & gt; DMA_Memory0BaseAddr; // Write to DMAy Streamx M0AR
}




/**
* @brief Enables or disables the specified DMAy Streamx interrupts.
* @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
* to 7 to select the DMA Stream.
* @param DMA_IT: specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer complete interrupt mask
* @arg DMA_IT_TE: Transfer error interrupt mask
* @arg DMA_IT_FE: FIFO error interrupt mask
* @param NewState: new state of the specified DMA interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState)
{
if ((DMA_IT & DMA_IT_FE) != 0) // Check if the DMA_IT parameter contains a FIFO interrupt
{
if (NewState != DISABLE)
{
DMAy_Streamx- & gt; FCR |= (uint32_t)DMA_IT_FE; //Enable the selected DMA FIFO interrupts
}
else
{
DMAy_Streamx- & gt; FCR & = ~(uint32_t)DMA_IT_FE; // Disable the selected DMA FIFO interrupts
}
}
if (DMA_IT != DMA_IT_FE) /* Check if the DMA_IT parameter contains a Transfer interrupt */
{
if (NewState != DISABLE)
{
DMAy_Streamx- & gt; CR |= (uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK); //Enable the selected DMA transfer interrupts
}
else
{
DMAy_Streamx- & gt; CR & = ~(uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK); // Disable the selected DMA transfer interrupts
}
}
}



/**
* @brief Checks whether the specified DMAy Streamx flag is set or not.
* @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
* to 7 to select the DMA Stream.
* @param DMA_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg DMA_FLAG_TCIFx: Streamx transfer complete flag
* @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag
* @arg DMA_FLAG_TEIFx: Streamx transfer error flag
* @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag
* @arg DMA_FLAG_FEIFx: Streamx FIFO error flag
* Where x can be 0 to 7 to select the DMA Stream.
* @retval The new state of DMA_FLAG (SET or RESET).
*/
FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_FLAG)
{
FlagStatus bitstatus = RESET;
DMA_TypeDef *DMAy;
uint32_t tmpreg = 0;
/* Determine the DMA to which belongs the stream */
if (DMAy_Streamx & lt; DMA2_Stream0)
{
/* DMAy_Streamx belongs to DMA1 */
DMAy = DMA1;
}
else
{
/* DMAy_Streamx belongs to DMA2 */
DMAy = DMA2;
}

/* Check if the flag is in HISR or LISR */
if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET)
{
/* Get DMAy HISR register value */
tmpreg = DMAy- & gt; HISR;
}
else
{
/* Get DMAy LISR register value */
tmpreg = DMAy- & gt; LISR;
}

/* Mask the reserved bits */
tmpreg & = (uint32_t)RESERVED_MASK;

/* Check the status of the specified DMA flag */
if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)
{
/* DMA_FLAG is set */
bitstatus = SET;
}
else
{
/* DMA_FLAG is reset */
bitstatus = RESET;
}

/* Return the DMA_FLAG status */
return bitstatus;
}


/**
* @brief Returns the status of EN bit for the specified DMAy Streamx.
* @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
* to 7 to select the DMA Stream.
*
* @note After configuring the DMA Stream (DMA_Init() function) and enabling
* the stream, it is recommended to check (or wait until) the DMA Stream
* is effectively enabled. A Stream may remain disabled if a configuration
* parameter is wrong.
* After disabling a DMA Stream, it is also recommended to check (or wait
* until) the DMA Stream is effectively disabled. If a Stream is disabled
* while a data transfer is ongoing, the current data will be transferred
* and the Stream will be effectively disabled only after the transfer
* of this single data is finished.
*
* @retval Current state of the DMAy Streamx (ENABLE or DISABLE).
*/
FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx)
{
FunctionalState state = DISABLE;
if ((DMAy_Streamx- & gt; CR & (uint32_t)DMA_SxCR_EN) != 0)
{
state = ENABLE; // The selected DMAy Streamx EN bit is set (DMA is still transferring)
}
else
{
state = DISABLE; // The selected DMAy Streamx EN bit is cleared (DMA is disabled and all transfers are complete)
}
return state;
}



/**
* @brief Clears the DMAy Streamx's pending flags.
* @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
* to 7 to select the DMA Stream.
* @param DMA_FLAG: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCIFx: Streamx transfer complete flag
* @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag
* @arg DMA_FLAG_TEIFx: Streamx transfer error flag
* @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag
* @arg DMA_FLAG_FEIFx: Streamx FIFO error flag
* Where x can be 0 to 7 to select the DMA Stream.
* @retval None
*/
void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG)
{
DMA_TypeDef* DMAy;
if (DMAy_Streamx & lt; DMA2_Stream0) // Determine the DMA to which belongs the stream
{
DMAy = DMA1; // DMAy_Streamx belongs to DMA1
}
else
{
DMAy = DMA2; //* DMAy_Streamx belongs to DMA2 */
}
if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET) // Check if LIFCR or HIFCR register is targeted
{
DMAy- & gt; HIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK);//Set DMAy HIFCR register clear flag bits
}
else
{
DMAy- & gt; LIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK);// Set DMAy LIFCR register clear flag bits
}
}



/**
* @brief Enables or disables the specified DMAy Streamx.
* @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
* to 7 to select the DMA Stream.
* @param NewState: new state of the DMAy Streamx.
* This parameter can be: ENABLE or DISABLE.
*
* @note This function may be used to perform Pause-Resume operation. When a
* transfer is ongoing, calling this function to disable the Stream will
* cause the transfer to be paused. All configuration registers and the
* number of remaining data will be preserved. When calling again this
* function to re-enable the Stream, the transfer will be resumed from
* the point where it was paused.
*
* @note After configuring the DMA Stream (DMA_Init() function) and enabling the
* stream, it is recommended to check (or wait until) the DMA Stream is
* effectively enabled. A Stream may remain disabled if a configuration
* parameter is wrong.
* After disabling a DMA Stream, it is also recommended to check (or wait
* until) the DMA Stream is effectively disabled. If a Stream is disabled
* while a data transfer is ongoing, the current data will be transferred
* and the Stream will be effectively disabled only after the transfer of
* this single data is finished.
*
* @retval None
*/
void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState)
{
if (NewState != DISABLE)
{
DMAy_Streamx- & gt; CR |= (uint32_t)DMA_SxCR_EN; // Enable the selected DMAy Streamx by setting EN bit
}
else
{
DMAy_Streamx- & gt; CR & = ~(uint32_t)DMA_SxCR_EN; // Disable the selected DMAy Streamx by clearing EN bit
}
}


wma_dec.ZIP > avformat.h

#ifndef AVFORMAT_H
#define AVFORMAT_H


#include " avio.h "
#include " codeccontext.h "

#define AVFMT_NOFILE 0x0001 /* no file should be opened */

#define int64_t_C(c) (c ## LL)
#define uint64_t_C(c) (c ## ULL)


#ifndef MININT64
#define MININT64 int64_t_C(0x8000000000000000)
#endif

#define AV_NOPTS_VALUE MININT64
#define AV_TIME_BASE 1000000

typedef struct AVPacket {
long long pts; /* presentation time stamp in AV_TIME_BASE units (or
pts_den units in muxers or demuxers) */
long long dts; /* decompression time stamp in AV_TIME_BASE units (or
pts_den units in muxers or demuxers) */
unsigned char *data;
int size;
int stream_index;
int flags;
int duration; /* presentation duration (0 if not available) */
void (*destruct)(struct AVPacket *);
void *priv;
} AVPacket;

#define PKT_FLAG_KEY 0x0001


/* initialize optional fields of a packet */
//static inline void av_init_packet(AVPacket *pkt) //jacky 2006/10/18
static __inline void av_init_packet(AVPacket *pkt)
{
pkt- & gt; pts = AV_NOPTS_VALUE;
pkt- & gt; dts = AV_NOPTS_VALUE;
pkt- & gt; duration = 0;
pkt- & gt; flags = 0;
pkt- & gt; stream_index = 0;
}



int av_new_packet(AVPacket *pkt, int size);


/**
* Free a packet
*
* @param pkt packet to free
*/
//static inline void av_free_packet(AVPacket *pkt)
static __inline void av_free_packet(AVPacket *pkt) //jacky 2006/10/18
{
if (pkt & & pkt- & gt; destruct) {
pkt- & gt; destruct(pkt);
}
}



/*************************************************/
/* fractional numbers for exact pts handling */

/* the exact value of the fractional number is: 'val + num / den'. num
is assumed to be such as 0 = num den */
/*typedef struct AVFrac {
long long val, num, den;
} AVFrac; */

/*void av_frac_init(AVFrac *f, int64_t val, int64_t num, int64_t den);
void av_frac_add(AVFrac *f, int64_t incr);
void av_frac_set(AVFrac *f, int64_t val); */

/*************************************************/

typedef struct AVIndexEntry {
long long pos;
long long timestamp;
#define AVINDEX_KEYFRAME 0x0001
/* the following 2 flags indicate that the next/prev keyframe is known, and scaning for it isnt needed */
int flags;
int min_distance; /* min distance between this and the previous keyframe, used to avoid unneeded searching */
} AVIndexEntry;



typedef struct AVStream {
int index; /* stream index in AVFormatContext */
int id; /* format specific stream id */
CodecContext codec; /* codec context */
// int r_frame_rate; /* real frame rate of the stream */
//int r_frame_rate_base;/* real frame rate base of the stream */
void *priv_data;
/* internal data used in av_find_stream_info() */
// long long codec_info_duration;
// int codec_info_nb_frames;
/* encoding: PTS generation when outputing stream */
// AVFrac pts;
/* ffmpeg.c private use */
int stream_copy; /* if TRUE, just copy stream */
/* quality, as it has been removed from AVCodecContext and put in AVVideoFrame
* MN:dunno if thats the right place, for it */
// float quality;
/* decoding: position of the first frame of the component, in
AV_TIME_BASE fractional seconds. */
long long start_time;
/* decoding: duration of the stream, in AV_TIME_BASE fractional
seconds. */
long long duration;

/* av_read_frame() support */
int need_parsing;
struct AVCodecParserContext *parser;

long long cur_dts;
int last_IP_duration;
/* av_seek_frame() support */
AVIndexEntry *index_entries; /* only used if the format does not
//support seeking natively */
int nb_index_entries;
int index_entries_allocated_size;
} AVStream;

//struct AVFormatContext;

#define MAX_STREAMS 2//20

/* format I/O context */
typedef struct AVFormatContext {
/* can only be iformat or oformat, not both at the same time */
struct AVInputFormat *iformat;
// struct AVOutputFormat *oformat;
void *priv_data;
ByteIOContext pb;
AVStream *streams[1/*MAX_STREAMS*/];
unsigned char/*int*/ nb_streams;
// char filename[15/*1024*/]; /* input or output filename */
/* stream info */
// char title[1/*512*/];
// char author[1/*512*/];
// char copyright[1/*512*/];
// char comment[1/*512*/];
// char album[1/*512*/];
// int year; /* ID3 year, 0 if none */
// int track; /* track number, 0 if none */
// char genre[1/*32*/]; /* ID3 genre */

// int ctx_flags; /* format specific flags, see AVFMTCTX_xx */
/* private data for pts handling (do not modify directly) */
unsigned short pts_wrap_bits; /* number of bits in pts (used for wrapping control) */
unsigned short pts_num/*, pts_den*/; /* value to convert to seconds */
/* This buffer is only needed when packets were already buffered but
not decoded, for example to get the codec parameters in mpeg
streams */
unsigned int pts_den;
struct AVPacketList *packet_buffer;

/* decoding: position of the first frame of the component, in
AV_TIME_BASE fractional seconds. NEVER set this value directly:
it is deduced from the AVStream values. */
long long start_time;
/* decoding: duration of the stream, in AV_TIME_BASE fractional
seconds. NEVER set this value directly: it is deduced from the
AVStream values. */
long long duration;
/* decoding: total file size. 0 if unknown */
// unsigned int file_size;
/* decoding: total stream bitrate in bit/s, 0 if not
available. Never set it directly if the file_size and the
duration are known as ffmpeg can compute it automatically. */
// int bit_rate;

/* av_read_frame() support */
AVStream *cur_st;
const unsigned char *cur_ptr;
int cur_len;
AVPacket cur_pkt;

/* the following are used for pts/dts unit conversion */
long long last_pkt_stream_pts;
long long last_pkt_stream_dts;
long long last_pkt_pts;
long long last_pkt_dts;
short/*int*/ last_pkt_pts_frac;
short/*int*/ last_pkt_dts_frac;

/* av_seek_frame() support */
long long data_offset; /* offset of the first packet */
int index_built;
} AVFormatContext;

/* this structure contains the data a format has to probe a file */
typedef struct AVProbeData {
const char *filename;
unsigned char *buf;
int buf_size;
} AVProbeData;

#define AVPROBE_SCORE_MAX 100

//typedef struct AVFormatParameters {
// int frame_rate;
// int frame_rate_base;
// int sample_rate;
// int channels;
// int width;
// int height;
//enum PixelFormat pix_fmt;
// struct AVImageFormat *image_format;
// int channel; /* used to select dv channel */
// const char *device; /* video4linux, audio or DV device */
// const char *standard; /* tv standard, NTSC, PAL, SECAM */
// int mpeg2ts_raw:1; /* force raw MPEG2 transport stream output, if possible */
// int mpeg2ts_compute_pcr:1; /* compute exact PCR for each transport
//stream packet (only meaningful if
//mpeg2ts_raw is TRUE */
// int initial_pause:1; /* do not begin to play the stream
//immediately (RTSP only) */
//} AVFormatParameters;




typedef struct AVInputFormat {
const char *name;
const char *long_name;
/* size of private data so that it can be allocated in the wrapper */
int priv_data_size;
/* tell if a given file has a chance of being parsing by this format */
int (*read_probe)(AVProbeData *);
/* read the format header and initialize the AVFormatContext
structure. Return 0 if OK. 'ap' if non NULL contains
additionnal paramters. Only used in raw format right
now. 'av_new_stream' should be called to create new streams. */
int (*read_header)(struct AVFormatContext */*,
AVFormatParameters *ap*/);
/* read one packet and put it in 'pkt'. pts and flags are also
set. 'av_new_stream' can be called only if the flag
AVFMTCTX_NOHEADER is used. */
int (*read_packet)(struct AVFormatContext *, AVPacket *pkt);
/* close the stream. The AVFormatContext and AVStreams are not
freed by this function */
int (*read_close)(struct AVFormatContext *);
/* seek at or before a given timestamp (given in AV_TIME_BASE
units) relative to the frames in stream component stream_index */
int (*read_seek)(struct AVFormatContext *,
int stream_index, long long timestamp);
/* can use flags: AVFMT_NOFILE, AVFMT_NEEDNUMBER */
int flags;
/* if extensions are defined, then no probe is done. You should
usually not use extension format guessing because it is not
reliable enough */
// const char *extensions;
/* general purpose read only value that the format can use */
// int value;

/* start/resume playing - only meaningful if using a network based format
(RTSP) */
// int (*read_play)(struct AVFormatContext *);

/* pause playing - only meaningful if using a network based format
(RTSP) */
// int (*read_pause)(struct AVFormatContext *);

/* private fields */
struct AVInputFormat *next;
} AVInputFormat;


typedef struct AVPacketList {
AVPacket pkt;
struct AVPacketList *next;
} AVPacketList;

extern AVInputFormat *first_iformat;


#define AVERROR_UNKNOWN (-1) /* unknown error */
#define AVERROR_IO (-2) /* i/o error */
#define AVERROR_NUMEXPECTED (-3) /* number syntax expected in filename */
#define AVERROR_INVALIDDATA (-4) /* invalid data found */
#define AVERROR_NOMEM (-5) /* not enough memory */
#define AVERROR_NOFMT (-6) /* unknown format */
#define AVERROR_NOTSUPP (-7) /* operation not supported */


int av_read_packet(AVFormatContext *s, AVPacket *pkt);
int av_read_frame(AVFormatContext *s, AVPacket *pkt);


void av_set_pts_info(AVFormatContext *s, int pts_wrap_bits,
int pts_num, int pts_den);
int av_find_default_stream_index(AVFormatContext *s);
int av_index_search_timestamp(AVStream *st, int timestamp);
int av_add_index_entry(AVStream *st, long long pos, long long timestamp, int distance, int flags);


AVStream *av_new_stream(AVFormatContext *s, int id);


/* media file input */
AVInputFormat *av_find_input_format(const char *short_name);
AVInputFormat *av_probe_input_format(AVProbeData *pd, int is_opened);
int av_open_input_stream(AVFormatContext **ic_ptr,
ByteIOContext *pb, const char *filename,
AVInputFormat *fmt/*, AVFormatParameters *ap*/);



/* futils.c */
void av_register_input_format(AVInputFormat *format);
void av_register_all(void);


int match_ext(const char *filename, const char *extensions);
void pstrcpy(char *buf, int buf_size, const char *str);
#endif


wma_dec.ZIP > demo.c

/* K:\instalki\edytor hex\demo(1).wma (2011-01-22 19:15:04)
StartOffset: 00000000, EndOffset: 00007E31, D?ugośae: 00007E32 */
const unsigned char rawData[32306] = {
0x30, 0x26, 0xB2, 0x75, 0x8E, 0x66, 0xCF, 0x11, 0xA6, 0xD9, 0x00, 0xAA,
0x00, 0x62, 0xCE, 0x6C, 0x44, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x3A, 0x4F, 0x8E, 0xE4, 0xD1, 0x46, 0x16, 0xA2, 0xA2, 0xE7, 0x32, 0x7E,
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0x41, 0x94, 0x13, 0x54, 0x24, 0x26, 0x6A, 0x15, 0x5A, 0x13, 0x2D, 0x8A,
0x8D, 0x04, 0x16, 0x36, 0x5B, 0x24, 0x2C, 0x20, 0xC9, 0x88, 0x20, 0xC9,
0x41, 0x06, 0x6A, 0x10, 0x82, 0x08, 0x6A, 0x45, 0x20, 0x93, 0xB0, 0x46,
0x14, 0x44, 0xEC, 0x41, 0x83, 0x50, 0xC1, 0x09, 0x83, 0x25, 0xA0, 0xBA,
0xA4, 0x82, 0x12, 0x0B, 0x44, 0x13, 0x1B, 0x8C, 0x30, 0x50, 0x26, 0x18,
0x4B, 0x75, 0x13, 0x33, 0x2C, 0x82, 0x43, 0x1A, 0x40, 0x83, 0x20, 0x12,
0x4C, 0x19, 0x98, 0x0A, 0x01, 0x55, 0x04, 0x16, 0xFF, 0x88, 0x62, 0x77,
0xA3, 0x2D, 0x0F, 0x35, 0xC8, 0x86, 0xFA, 0x9E, 0x72, 0x2C, 0xF0, 0xDF,
0x49, 0x4F, 0x4A, 0x54, 0x46, 0x9A, 0xE3, 0x89, 0xD2, 0x02, 0x47, 0xFB,
0xC2, 0x69, 0xE5, 0x0B, 0x19, 0x43, 0x28, 0x22, 0xA8, 0x04, 0xC6, 0x58,
0x4A, 0x1C, 0x8D, 0x34, 0xEB, 0xA4, 0x4A, 0xC8, 0xC4, 0x58, 0x84, 0x42,
0x4D, 0x0A, 0x9C, 0x2D, 0xC0, 0xDA, 0x45, 0x9E, 0x46, 0x43, 0x69, 0x31,
0x25, 0x87, 0x0B, 0xC8, 0x91, 0x65, 0x01, 0x03, 0x3A, 0x1E, 0x5E, 0x45,
0xFC, 0x22, 0xB3, 0xE2, 0xF7, 0xA5, 0xDC, 0xB0, 0x81, 0x29, 0x09, 0xEF,
0x4B, 0xB9, 0x61, 0x02, 0x52, 0x12, 0x08, 0x7D, 0xFB, 0x08, 0x7D, 0x52,
0x5D, 0xBA, 0x4D, 0x12, 0x83, 0x09, 0x44, 0x93, 0x24, 0x26, 0xA8, 0x82,
0x60, 0x19, 0xD3, 0x06, 0xC1, 0x99, 0x95, 0x48, 0x12, 0x40, 0x61, 0x32,
0x0C, 0x92, 0x01, 0x32, 0x03, 0x35, 0x30, 0xA8, 0xBA, 0x74, 0x62, 0x03,
0x6F, 0x67, 0x6A, 0x41, 0x24, 0x08, 0x37, 0xCC, 0x58, 0xAB, 0x97, 0x68,
0xD1, 0x24, 0x13, 0x1A, 0x24, 0x48, 0x85, 0x24, 0x40, 0x21, 0x56, 0x80,
0xA8, 0x05, 0x59, 0x9A, 0xBB, 0x96, 0x99, 0x50, 0x4C, 0xAE, 0x0C, 0x00,
0xE5, 0x8A, 0x40, 0x68, 0x53, 0x41, 0xA7, 0x67, 0x0D, 0x25, 0xB3, 0x31,
0x04, 0x9C, 0x24, 0xB6, 0x08, 0xD8, 0x35, 0x50, 0x70, 0x92, 0xAB, 0x01,
0x24, 0x69, 0x93, 0x20, 0xCC, 0x30, 0xE2, 0x20, 0x14, 0xA1, 0x59, 0x26,
0x26, 0x40, 0x24, 0xC2, 0x00, 0x14, 0xE2, 0x35, 0x60, 0x25, 0x84, 0x10,
0x62, 0x60, 0x80, 0x75, 0x21, 0x86, 0x04, 0x14, 0x0B, 0x89, 0x61, 0x88,
0x12, 0x99, 0x44, 0x96, 0xCE, 0xCC, 0x6C, 0x09, 0x0D, 0x02, 0x4C, 0x80,
0x90, 0x61, 0x37, 0xA5, 0xD4, 0x66, 0xFF, 0xA4, 0x36, 0xA4, 0x05, 0xED,
0x04, 0x02, 0x2A, 0x82, 0x48, 0x91, 0xA9, 0x3A, 0xC2, 0x62, 0x81, 0x24,
0xC8, 0x22, 0xA8, 0x30, 0x30, 0xB4, 0x40, 0x92, 0x12, 0x4E, 0xB6, 0x51,
0x86, 0x30, 0xC8, 0x20, 0x49, 0x24, 0x9D, 0x89, 0x48, 0x00, 0x89, 0x00,
0xEC, 0x30, 0x86, 0x00, 0x49, 0x69, 0x25, 0x03, 0x41, 0x84, 0x61, 0x80,
0x08, 0xB3, 0x29, 0x96, 0xC1, 0x78, 0x5D, 0x51, 0x27, 0xAE, 0x79, 0xC8,
0xB2, 0xF5, 0xC2, 0x90, 0xA0, 0xC5, 0xC7, 0xD6, 0xD2, 0x1A, 0xE9, 0x46,
0x18, 0xD3, 0x1B, 0x13, 0x25, 0xB5, 0x5B, 0xCC, 0x04, 0xF4, 0x43, 0x69,
0x88, 0x84, 0x22, 0x21, 0x78, 0x55, 0x22, 0x5F, 0xE4, 0x65, 0xB2, 0x51,
0x03, 0x13, 0x80, 0x78, 0xF9, 0xBA, 0x59, 0xCC, 0x0C, 0x62, 0x74, 0x92,
0x1C, 0x0F, 0x30, 0x28, 0x51, 0x15, 0x38, 0x31, 0x8F, 0xCA, 0x06, 0x86,
0xC9, 0x44, 0xB2, 0x56, 0x32, 0xB0, 0x86, 0x2B, 0x7E, 0x5F, 0x58, 0xBD,
0x42, 0x41, 0x00, 0x2F, 0xD6, 0x2F, 0x50, 0x90, 0x40, 0x0B, 0x88, 0x23,
0x89, 0xB8, 0x04, 0xA0, 0xC8, 0x4C, 0xCB, 0x6A, 0x28, 0xC2, 0x43, 0x4B,
0x01, 0x69, 0xBE, 0x4C, 0xCA, 0xBB, 0x86, 0xF4, 0xC6, 0x36, 0x44, 0x72,
0x01, 0x48, 0x5E, 0x07, 0x01, 0xBA, 0xE8, 0xBA, 0x5B, 0xA6, 0x31, 0x75,
0x8D, 0x6D, 0x7B, 0x9E, 0x2E, 0x83, 0x03, 0x22, 0x79, 0xB0, 0x86, 0xF7,
0x04, 0xC8, 0x9B, 0x12, 0x1A, 0x43, 0x08, 0x1B, 0x03, 0x50, 0xD1, 0xB5,
0x27, 0x41, 0x42, 0x75, 0x37, 0x35, 0x85, 0x8C, 0x9D, 0x32, 0xE2, 0x04,
0xC0, 0x83, 0x0C, 0x10, 0xC1, 0x30, 0x58, 0x49, 0xD0, 0x20, 0x41, 0x64,
0x99, 0x22, 0x66, 0x1A, 0x60, 0x36, 0x02, 0x83, 0xA6, 0xCC, 0x03, 0x72,
0x81, 0x71, 0x87, 0x56, 0x95, 0x60, 0x64, 0xB4, 0xC4, 0x6E, 0xAC, 0x42,
0x55, 0x85, 0xDB, 0x13, 0xA2, 0x24, 0x24, 0x58, 0x31, 0x7A, 0xAA, 0x6B,
0x66, 0x6F, 0xE1, 0x9D, 0x28, 0xDD, 0x13, 0xD4, 0xB2, 0x04, 0x08, 0x68,
0x1A, 0x11, 0x01, 0x8D, 0x83, 0xA3, 0xA8, 0x2D, 0x57, 0x4D, 0x04, 0xA9,
0xB9, 0x86, 0xC6, 0xC7, 0xC0, 0xC5, 0x1A, 0x15, 0x32, 0xC1, 0x01, 0x80,
0x17, 0x84, 0x21, 0x69, 0x44, 0x89, 0x14, 0xA5, 0x71, 0xC5, 0x8B, 0x80,
0xA8, 0x8A, 0x52, 0x29, 0x69, 0xA6, 0xD3, 0x44, 0x8B, 0x2D, 0x61, 0x09,
0x21, 0x8D, 0x3C, 0x32, 0x70, 0xBF, 0xC2, 0x81, 0x81, 0xBA, 0x65, 0x9B,
0x03, 0x7B, 0xAA, 0xAC, 0x51, 0xC9, 0x63, 0x49, 0x46, 0xA6, 0x48, 0xD3,
0x26, 0xB2, 0x35, 0xFD, 0x8C, 0xA4, 0x4A, 0x19, 0x39, 0xAC, 0x44, 0x17,
0x4B, 0x37, 0xFB, 0xFE, 0xF1, 0x35, 0x10, 0xBA, 0x85, 0x40, 0x93, 0xBC,
0x4D, 0x44, 0x2E, 0xA1, 0x50, 0x24, 0x82, 0x91, 0x42, 0x12, 0x90, 0x82,
0x44, 0x88, 0x93, 0x31, 0x17, 0xC4, 0x9D, 0x00, 0x49, 0xD8, 0xD6, 0xE7,
0x72, 0x18, 0x26, 0x23, 0xAD, 0xAA, 0xD6, 0xC3, 0x59, 0x00, 0x91, 0x3B,
0x3B, 0x69, 0xD5, 0x93, 0x79, 0x13, 0x12, 0x00, 0x12, 0x66, 0x44, 0xB4,
0x68, 0x4C, 0x55, 0x06, 0x00, 0x30, 0x43, 0x09, 0x2D, 0x10, 0xA1, 0x64,
0xA9, 0x37, 0x92, 0x09, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, 0x08,
0x5D, 0x04, 0x73, 0x01, 0x00, 0x00, 0x73, 0x01, 0x01, 0x02, 0x00, 0x00,
0x00, 0x00, 0x08, 0xCF, 0x05, 0x00, 0x00, 0x55, 0x07, 0x00, 0x00, 0x15,
0xF9, 0x45, 0xBD, 0xCB, 0x04, 0x4B, 0x59, 0xAD, 0x82, 0x40, 0xD1, 0x00,
0x19, 0x37, 0x00, 0x35, 0x51, 0x56, 0x61, 0x95, 0x01, 0x98, 0x21, 0x8D,
0xB8, 0x9D, 0x83, 0x0A, 0x08, 0x0C, 0x12, 0x27, 0x7B, 0x3C, 0x8C, 0xC8,
0x3D, 0x17, 0x85, 0x40, 0xE8, 0x57, 0x09, 0x12, 0x31, 0x71, 0x32, 0x91,
0x70, 0x63, 0x21, 0x3C, 0x88, 0x87, 0x84, 0x31, 0xBF, 0xB3, 0x82, 0x2A,
0x2A, 0xCF, 0xC9, 0x88, 0x7F, 0x38, 0xC8, 0x62, 0x6B, 0x2C, 0x91, 0x2B,
0xFD, 0x60, 0x84, 0x24, 0x31, 0x38, 0x46, 0x4C, 0x19, 0x69, 0x10, 0x24,
0x18, 0x32, 0x02, 0xC0, 0x9A, 0x84, 0x44, 0xC8, 0xD4, 0x21, 0x10, 0x4B,
0x40, 0x2C, 0x99, 0x06, 0x41, 0xA9, 0x00, 0x95, 0xCF, 0x30, 0xE6, 0xC6,
0x85, 0x02, 0xC6, 0x45, 0x8E, 0x09, 0xE5, 0x66, 0xFF, 0x65, 0x4B, 0xE6,
0x20, 0xC0, 0xAB, 0x16, 0x00, 0x0D, 0x8E, 0x81, 0x80, 0x0E, 0x81, 0x04,
0xE4, 0x1A, 0x49, 0x2D, 0x27, 0x41, 0x50, 0xD6, 0xD9, 0x7B, 0xA9, 0xC4,
0x19, 0x30, 0x67, 0x2C, 0x42, 0x58, 0x14, 0x37, 0xFA, 0xC7, 0xD6, 0xF2,
0xF8, 0xCC, 0xDE, 0x4B, 0x0C, 0x18, 0x99, 0x3B, 0x04, 0xB2, 0x93, 0x54,
0x6F, 0x60, 0x8C, 0x30, 0x4B, 0x19, 0x13, 0x13, 0x12, 0x4C, 0x81, 0x04,
0x77, 0x24, 0xBC, 0x0F, 0x22, 0xE9, 0xAE, 0x2E, 0x8B, 0x03, 0x12, 0x69,
0x34, 0x86, 0x90, 0xC6, 0xC6, 0x3B, 0x3D, 0x9F, 0x8E, 0x38, 0x89, 0x2A,
0x4F, 0x1C, 0x71, 0x12, 0x54, 0x84, 0x06, 0xC1, 0x56, 0x1B, 0x00, 0x19,
0x61, 0x32, 0x86, 0x90, 0xC1, 0x20, 0x80, 0xA1, 0x80, 0x4A, 0x8D, 0x22,
0x24, 0x12, 0x64, 0xB0, 0xE1, 0xB5, 0xA0, 0xC0, 0x20, 0xBD, 0x17, 0x4B,
0xBC, 0xE2, 0x4D, 0xA6, 0x50, 0xC6, 0x38, 0xEA, 0x14, 0x31, 0x5E, 0x1F,
0x07, 0xB8, 0xB9, 0x64, 0x44, 0xA8, 0x81, 0xAF, 0x71, 0x72, 0xC8, 0x89,
0x51, 0x03, 0x4E, 0xA1, 0x45, 0x0B, 0x54, 0x22, 0x92, 0xEC, 0x9A, 0x16,
0x29, 0x7D, 0x55, 0x00, 0x16, 0x3F, 0x32, 0x85, 0x81, 0xA4, 0x84, 0xA0,
0x82, 0x84, 0xCC, 0x88, 0x5C, 0x75, 0x30, 0xD0, 0x43, 0xAA, 0x4A, 0x72,
0xD0, 0x4C, 0xC4, 0x59, 0x63, 0x24, 0x5F, 0x76, 0xD2, 0xAC, 0xC4, 0x13,
0x57, 0x45, 0xA0, 0x16, 0x46, 0xC8, 0x21, 0x51, 0x28, 0x26, 0x22, 0x1A,
0x18, 0x66, 0x25, 0xB7, 0xC4, 0x94, 0x82, 0x05, 0xD2, 0x19, 0x2A, 0xAA,
0x74, 0x95, 0x4C, 0x08, 0x4C, 0xCB, 0x04, 0xB7, 0x07, 0x92, 0x58, 0x61,
0x30, 0x25, 0x63, 0x05, 0x92, 0xD6, 0xB2, 0x35, 0x00, 0x93, 0x00, 0x82,
0x40, 0x97, 0x59, 0x61, 0x92, 0x20, 0xFF, 0xF5, 0x22, 0x41, 0x32, 0x50,
0x21, 0x40, 0x6A, 0x13, 0x1B, 0x75, 0x23, 0x0D, 0x8D, 0x81, 0x12, 0x00,
0x2C, 0x32, 0x41, 0x40, 0xC8, 0x22, 0x42, 0x37, 0x04, 0x13, 0x20, 0x94,
0x80, 0x30, 0xE1, 0x92, 0x88, 0x4C, 0x48, 0x8A, 0x82, 0x65, 0xB1, 0x51,
0x9B, 0xFF, 0x04, 0x4B, 0x49, 0x40, 0x89, 0x01, 0x04, 0xC6, 0x16, 0x8C,
0x88, 0x12, 0xC3, 0x12, 0x24, 0x96, 0x17, 0x58, 0x20, 0x16, 0xA5, 0x29,
0x02, 0x04, 0x40, 0x06, 0x41, 0x40, 0x31, 0x20, 0xC6, 0x89, 0x89, 0x80,
0x00, 0x01, 0xA0, 0x99, 0x90, 0x14, 0xD8, 0x12, 0x6A, 0xE8, 0x13, 0xB5,
0x08, 0x1B, 0xB2, 0x24, 0x09, 0x00, 0x2E, 0x92, 0x7F, 0xE0, 0xEE, 0x27,
0x73, 0x26, 0x08, 0x33, 0x10, 0xC1, 0x57, 0x65, 0x8A, 0x90, 0x08, 0x98,
0x30, 0xD9, 0x52, 0x55, 0x31, 0x17, 0x3D, 0x06, 0x22, 0x44, 0x7A, 0x61,
0x58, 0xB1, 0x67, 0xA5, 0x03, 0xCB, 0xEA, 0x5C, 0x4F, 0xB1, 0x46, 0x14,
0xE9, 0x4F, 0x59, 0x4A, 0xC0, 0xDB, 0x64, 0x35, 0x41, 0x58, 0x61, 0x57,
0xD1, 0xD5, 0x0C, 0x30, 0x89, 0x67, 0x30, 0xC0, 0x43, 0x28, 0x6D, 0xEA,
0x27, 0x29, 0x3C, 0x24, 0xF0, 0xC4, 0xC6, 0xCB, 0x88, 0x42, 0x43, 0x59,
0x13, 0x69, 0x97, 0x9A, 0x38, 0x04, 0x28, 0x0B, 0x3C, 0xB1, 0xC0, 0x98,
0xB2, 0xD0, 0xC4, 0x36, 0x5A, 0xB4, 0xB2, 0x43, 0x1B, 0x63, 0x1C, 0x0E,
0xCF, 0x87, 0xDE, 0x92, 0xEE, 0x54, 0x48, 0x88, 0x25, 0x4B, 0xF7, 0xA4,
0xBB, 0x95, 0x12, 0x22, 0x09, 0x52, 0xE4, 0xA1, 0xFD, 0x2F, 0x96, 0xD3,
0x40, 0x34, 0x8A, 0x52, 0x00, 0xA0, 0x25, 0x28, 0x85, 0x85, 0x0D, 0x30,
0x11, 0x50, 0x20, 0x20, 0xC0, 0x2B, 0x38, 0xD4, 0x23, 0x44, 0x86, 0x88,
0x62, 0x18, 0xC3, 0x96, 0x20, 0x34, 0xC6, 0x88, 0x52, 0x58, 0x48, 0x11,
0xB3, 0x20, 0x9D, 0x4B, 0x09, 0x89, 0xD8, 0x1D, 0xDC, 0x21, 0x8E, 0x63,
0x52, 0x01, 0x62, 0xE6, 0x10, 0xD4, 0xC9, 0xB9, 0xA9, 0x24, 0x10, 0xC3,
0x3D, 0x37, 0x42, 0x40, 0x88, 0x07, 0xB3, 0x20, 0x81, 0x01, 0x13, 0x2A,
0x99, 0x99, 0x30, 0xA0, 0x32, 0xC5, 0x19, 0x56, 0x13, 0x50, 0x91, 0xD1,
0x32, 0x99, 0x23, 0x0B, 0xB0, 0x02, 0x92, 0x12, 0x0C, 0x95, 0xC1, 0x3A,
0x99, 0x37, 0x21, 0x09, 0x20, 0xEE, 0x74, 0x08, 0x44, 0x50, 0xC9, 0x80,
0x1D, 0x72, 0x44, 0x43, 0x20, 0x08, 0x0E, 0x50, 0x5B, 0xD9, 0x0D, 0x8B,
0xA5, 0x22, 0x6C, 0x32, 0x25, 0x32, 0x64, 0x86, 0x1F, 0xFA, 0x27, 0x65,
0x40, 0x44, 0xC1, 0x41, 0x64, 0x95, 0xE0, 0x6C, 0x6C, 0x13, 0x05, 0x85,
0xA2, 0x20, 0x31, 0xB2, 0x01, 0x60, 0x88, 0xBE, 0x44, 0x15, 0x26, 0x4C,
0x36, 0x3A, 0x96, 0x76, 0xC2, 0xD6, 0xA0, 0x13, 0x24, 0x54, 0x64, 0x86,
0xB0, 0xE1, 0x02, 0x14, 0x99, 0x3A, 0x20, 0x41, 0x86, 0xC0, 0x07, 0x59,
0x6B, 0xD8, 0x75, 0xA8, 0x9B, 0x84, 0x5D, 0x70, 0x60, 0xD8, 0x32, 0x18,
0x34, 0xA7, 0x4F, 0x64, 0x68, 0x1E, 0x3D, 0x31, 0x45, 0xE7, 0x0D, 0xE6,
0xB8, 0xA2, 0x69, 0xA6, 0x51, 0x92, 0x8E, 0x31, 0x88, 0x92, 0x06, 0xD0,
0xD3, 0x68, 0xA3, 0x22, 0x43, 0x1F, 0x1B, 0x13, 0x81, 0x24, 0x25, 0x94,
0x9A, 0x19, 0x19, 0x15, 0x79, 0x49, 0x26, 0xCB, 0xB1, 0x24, 0xB0, 0xC4,
0x92, 0x10, 0x86, 0x98, 0x89, 0x15, 0x4D, 0x31, 0x8D, 0x3F, 0xC9, 0xAD,
0x31, 0x62, 0x38, 0xC8, 0x64, 0xE1, 0x88, 0x96, 0x14, 0x25, 0x10, 0x48,
0x9D, 0x34, 0x24, 0x2C, 0x32, 0x50, 0x84, 0xB8, 0x9B, 0xC8, 0xF2, 0x28,
0x55, 0x9F, 0x17, 0xCA, 0xAE, 0xE4, 0x92, 0xA2, 0x48, 0x09, 0x2F, 0xE5,
0x57, 0x72, 0x49, 0x51, 0x24, 0x04, 0x97, 0xA2, 0xF9, 0x26, 0xA2, 0x28,
0x5A, 0x2B, 0x49, 0xA2, 0x95, 0xB3, 0x43, 0xE0, 0x68, 0x0F, 0x88, 0x4D,
0x52, 0x94, 0xC8, 0x28, 0x31, 0x31, 0x01, 0x28, 0x68, 0x28, 0x3A, 0x42,
0x04, 0x08, 0x24, 0x96, 0xB4, 0x01, 0x06, 0x58, 0x4C, 0x0A, 0x09, 0x08,
0xAB, 0xB3, 0x24, 0x94, 0xCC, 0xDF, 0xD8, 0x90, 0x41, 0x25, 0x59, 0x9B,
0xA0, 0x08, 0x2D, 0x04, 0x09, 0x64, 0xCB, 0x66, 0xFB, 0x11, 0xD3, 0x03,
0x04, 0x12, 0xC2, 0x92, 0x9D, 0x10, 0x6A, 0x1E, 0x94, 0x06, 0x27, 0x4C,
0x98, 0x40, 0x04, 0x0A, 0xBD, 0x49, 0x37, 0xB4, 0xB0, 0x9B, 0xC9, 0x8D,
0x6C, 0xCE, 0x13, 0x14, 0x28, 0x69, 0x18, 0x73, 0xA3, 0xD0, 0x1A, 0xCB,
0xA5, 0x34, 0x91, 0x01, 0x14, 0x49, 0x69, 0x82, 0xD0, 0x49, 0x2C, 0x1A,
0x99, 0x61, 0x64, 0x22, 0x42, 0x08, 0x41, 0xD3, 0x15, 0xD1, 0x64, 0x00,
0x5B, 0x97, 0x82, 0x08, 0x22, 0x46, 0xCC, 0x98, 0x69, 0x04, 0x86, 0x4B,
0x60, 0x40, 0xAB, 0x97, 0x45, 0x48, 0x32, 0x18, 0xD0, 0x49, 0x53, 0x2F,
0x06, 0x6A, 0x63, 0x24, 0x4B, 0xAD, 0xBB, 0x35, 0x2F, 0x89, 0x54, 0x58,
0x90, 0x26, 0x44, 0x15, 0x41, 0xE6, 0x55, 0x30, 0x2A, 0xEC, 0x12, 0xDD,
0x30, 0x03, 0x20, 0xC6, 0x80, 0xE8, 0x99, 0x69, 0xB4, 0xD1, 0x88, 0xD0,
0x75, 0x48, 0x1A, 0x26, 0x24, 0x36, 0x47, 0x46, 0x20, 0xB3, 0x6C, 0xD9,
0x54, 0x41, 0x20, 0x4C, 0x89, 0x9B, 0x80, 0x17, 0xB4, 0x6C, 0x92, 0xF1,
0x21, 0x67, 0x27, 0x9D, 0xEB, 0x28, 0xEB, 0x54, 0x01, 0x75, 0xA4, 0xD2,
0xE9, 0x41, 0x46, 0x34, 0xDB, 0x3E, 0x96, 0x1A, 0x58, 0x29, 0x4D, 0x3C,
0xB2, 0x5D, 0x4C, 0x44, 0xB7, 0x84, 0x87, 0x8C, 0x21, 0x64, 0x50, 0xA2,
0xC3, 0x1B, 0x43, 0x6A, 0x17, 0x81, 0x89, 0x89, 0x08, 0x4F, 0x09, 0x24,
0x2C, 0xE5, 0xE4, 0x97, 0x9C, 0x31, 0x88, 0x7F, 0xA1, 0x28, 0x73, 0x34,
0x49, 0x0D, 0x32, 0x49, 0x4D, 0x13, 0x0A, 0x8E, 0x2C, 0x0D, 0x94, 0x22,
0x13, 0xE0, 0xC8, 0x53, 0x1B, 0x43, 0x56, 0x7C, 0x5F, 0x34, 0xBB, 0x91,
0x70, 0x48, 0x22, 0x4B, 0xF9, 0xA5, 0xDC, 0x8B, 0x82, 0x41, 0x12, 0x5C,
0x15, 0x8A, 0x56, 0xD2, 0x9A, 0x4B, 0xE4, 0xFE, 0xF8, 0xE9, 0x49, 0x42,
0xD8, 0x4C, 0x93, 0x42, 0x0D, 0x08, 0x35, 0x02, 0x36, 0x59, 0x54, 0xAC,
0x52, 0x00, 0xBA, 0xA1, 0x84, 0xD2, 0xA1, 0x08, 0x2C, 0x1B, 0x18, 0x4C,
0x96, 0x33, 0x61, 0x0C, 0x80, 0x3A, 0x5F, 0x30, 0x76, 0x03, 0x42, 0x89,
0x17, 0xA6, 0x13, 0x04, 0x9E, 0xB4, 0x41, 0x54, 0x2B, 0x1B, 0xB4, 0x07,
0x0C, 0x03, 0xA2, 0x21, 0x4E, 0x52, 0xC8, 0x40, 0x02, 0x20, 0x91, 0x55,
0x10, 0x44, 0x4E, 0xD5, 0x75, 0x6C, 0x10, 0xC2, 0xBC, 0x36, 0x4C, 0x61,
0xC0, 0x2A, 0x89, 0x81, 0x04, 0xB4, 0xB0, 0x93, 0x1B, 0x93, 0x29, 0x9C,
0x34, 0x20, 0x9D, 0x22, 0x0E, 0x98, 0x74, 0x01, 0x00, 0x02, 0x0E, 0xA0,
0x19, 0x29, 0x4E, 0x90, 0x91, 0x50, 0x34, 0x04, 0x88, 0x21, 0x2C, 0x2A,
0x12, 0x44, 0xB4, 0xEA, 0x30, 0xC3, 0xAA, 0x77, 0x54, 0x6A, 0xFD, 0x96,
0xAB, 0x10, 0x24, 0x09, 0x13, 0x1B, 0xBE, 0x15, 0x9A, 0x91, 0xB5, 0x43,
0x02, 0x80, 0xC5, 0xFB, 0x56, 0x61, 0x58, 0x11, 0x20, 0x12, 0xA4, 0x42,
0x92, 0x83, 0xA6, 0x26, 0x7F, 0xC0, 0x9F, 0xF8, 0x24, 0x89, 0x31, 0x2C,
0xA8, 0xD1, 0x71, 0xC4, 0x42, 0x8D, 0x63, 0x76, 0x5A, 0x06, 0x63, 0x1A,
0x5D, 0x1B, 0x48, 0xB9, 0x8C, 0x64, 0x4A, 0xA0, 0x36, 0x24, 0x1B, 0xA2,
0xEB, 0x98, 0xBC, 0x08, 0x10, 0xD6, 0x31, 0xEC, 0x22, 0x80, 0xB3, 0x87,
0xF5, 0x0F, 0x11, 0x22, 0x94, 0x87, 0x36, 0x87, 0xCC, 0x37, 0x91, 0xB4,
0x92, 0x18, 0x96, 0x15, 0x4D, 0xA0, 0xA6, 0x1B, 0x68, 0x24, 0x79, 0x11,
0x09, 0x0D, 0xB6, 0x24, 0x21, 0xBC, 0x24, 0xD2, 0x17, 0xC8, 0x5F, 0x32,
0xD0, 0x31, 0x09, 0x1F, 0x6C, 0x92, 0xC8, 0x78, 0x64, 0x53, 0xFD, 0x7E,
0x28, 0x09, 0xCA, 0x6A, 0xB6, 0x86, 0x31, 0x10, 0x24, 0xB0, 0x92, 0xE7,
0x18, 0xBA, 0x21, 0xF1, 0xC1, 0xAC, 0x7F, 0x89, 0xD5, 0x67, 0xC7, 0xEF,
0x55, 0x2F, 0x49, 0x12, 0x44, 0x11, 0x25, 0xFB, 0xD5, 0x4B, 0xD2, 0x44,
0x91, 0x04, 0x49, 0x64, 0xA1, 0xF2, 0x70, 0xCA, 0x4A, 0xDA, 0x00, 0x00,
0x00, 0x00, 0x82, 0x00, 0x00, 0x08, 0x5D, 0x04, 0xE6, 0x02, 0x00, 0x00,
0x73, 0x01, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x08, 0xCF, 0x05, 0x00,
0x00, 0x29, 0x08, 0x00, 0x00, 0x26, 0xEE, 0x67, 0x1F, 0x1A, 0x69, 0x09,
0x45, 0x2F, 0x83, 0x09, 0xA0, 0x34, 0x24, 0xA6, 0x50, 0x12, 0x41, 0x75,
0x89, 0x01, 0x9A, 0x69, 0x04, 0xA7, 0x49, 0x52, 0xA9, 0x31, 0xB1, 0x03,
0x61, 0xA0, 0x03, 0xB1, 0xA2, 0xB8, 0x06, 0x41, 0xF8, 0x41, 0x89, 0x69,
0x90, 0xAC, 0x6F, 0x60, 0x2B, 0xD4, 0xCE, 0xC0, 0xBB, 0x64, 0x80, 0x90,
0x42, 0x9A, 0x85, 0x26, 0x53, 0x12, 0x0C, 0x03, 0x2D, 0x62, 0xF8, 0x5F,
0x22, 0x55, 0x88, 0xCB, 0x06, 0x6C, 0xB6, 0x6E, 0x6C, 0x80, 0x18, 0xA0,
0x5C, 0x22, 0x2A, 0xA4, 0x06, 0x01, 0x04, 0xA0, 0x8E, 0xB6, 0xA1, 0x31,
0x0C, 0x60, 0x61, 0x54, 0xC1, 0x86, 0x05, 0x72, 0xF3, 0x32, 0x27, 0x70,
0x20, 0x9D, 0xE9, 0x85, 0x41, 0x64, 0x44, 0x83, 0xAD, 0x55, 0x12, 0xC2,
0x90, 0x0B, 0x18, 0x0F, 0x50, 0xDB, 0xC2, 0xB8, 0x7A, 0x2D, 0x90, 0x63,
0xB0, 0x06, 0xB7, 0x98, 0xC8, 0x27, 0x50, 0xD3, 0x17, 0x43, 0x0B, 0x4B,
0x41, 0x88, 0xD9, 0x10, 0x5B, 0xB9, 0x57, 0x52, 0xAB, 0x3B, 0x6B, 0x09,
0xC7, 0x8B, 0x1A, 0x84, 0x9E, 0xC6, 0xC7, 0xC6, 0x31, 0x4D, 0x35, 0x8A,
0x18, 0x91, 0x78, 0x8D, 0xC7, 0x22, 0xAC, 0xE2, 0xB9, 0xEC, 0xC4, 0x5D,
0x7A, 0x65, 0x2B, 0x4F, 0xAF, 0xAD, 0x0B, 0xB1, 0x13, 0x42, 0xC0, 0xBA,
0xB8, 0x25, 0x94, 0xC6, 0x3C, 0xBC, 0x21, 0x56, 0x2A, 0x86, 0x86, 0x24,
0xD4, 0x2B, 0x02, 0x69, 0xE1, 0xE3, 0x0F, 0x38, 0xAD, 0x8B, 0x19, 0xC2,
0x42, 0x59, 0xC9, 0x03, 0x15, 0x69, 0xA7, 0x30, 0xB6, 0x60, 0x20, 0x4B,
0x15, 0x88, 0x96, 0x24, 0xC4, 0x98, 0xCE, 0xFA, 0xCB, 0x09, 0xBE, 0x3C,
0xC7, 0xFC, 0x64, 0x2A, 0x8D, 0x2C, 0x0F, 0x87, 0xEC, 0x4B, 0x97, 0x2C,
0x24, 0x24, 0x89, 0x7F, 0x62, 0x5C, 0xB9, 0x61, 0x21, 0x24, 0x4B, 0x28,
0x3C, 0x4F, 0x88, 0xE3, 0x09, 0x34, 0xAD, 0xD2, 0xF8, 0x23, 0xF4, 0x5F,
0xF1, 0x52, 0xF9, 0x15, 0x24, 0xBA, 0x03, 0xFA, 0x8E, 0xA4, 0xA5, 0xFC,
0x94, 0x4C, 0xCE, 0x18, 0x84, 0x82, 0x10, 0x00, 0x33, 0x0D, 0x80, 0x53,
0x28, 0x90, 0xC8, 0x99, 0x80, 0x84, 0x21, 0x82, 0x02, 0x95, 0x35, 0x12,
0xC1, 0x24, 0xA1, 0x24, 0x98, 0x24, 0x92, 0x16, 0x71, 0x89, 0x0A, 0x85,
0x4F, 0xF8, 0x2A, 0xD8, 0x61, 0xDC, 0x18, 0x92, 0x4C, 0x94, 0x02, 0x90,
0x0A, 0x0D, 0x45, 0x22, 0x49, 0x29, 0x2C, 0x58, 0x04, 0xD2, 0x13, 0x04,
0x10, 0x60, 0xCD, 0xDA, 0x83, 0x33, 0x52, 0x64, 0x8A, 0xA4, 0x18, 0x88,
0x2D, 0xD8, 0x94, 0xC9, 0x55, 0x15, 0x48, 0x25, 0x91, 0x7C, 0xA4, 0xC2,
0x62, 0x95, 0x81, 0x80, 0x64, 0x90, 0x60, 0xA1, 0x80, 0x54, 0x60, 0xC6,
0x24, 0x89, 0x52, 0x26, 0x05, 0xC2, 0x59, 0xB5, 0x23, 0x4C, 0x89, 0x4A,
0x26, 0x6A, 0x9D, 0xF6, 0xD6, 0x83, 0x0C, 0x00, 0x4B, 0x45, 0x46, 0x35,
0x8A, 0x08, 0x74, 0x64, 0x03, 0x25, 0x58, 0x68, 0xD1, 0x99, 0x62, 0xEB,
0xAF, 0x00, 0x86, 0x34, 0xB4, 0xCB, 0x3B, 0x3B, 0x60, 0x24, 0x35, 0xA3,
0x64, 0x30, 0x40, 0x10, 0xC6, 0x4C, 0x4C, 0xFC, 0x61, 0x86, 0x06, 0xCD,
0x5D, 0x09, 0x69, 0x02, 0x0B, 0x59, 0x8B, 0xB6, 0x36, 0x4B, 0x06, 0xE1,
0xA2, 0xE1, 0x19, 0xBD, 0xB6, 0x44, 0xE2, 0xB8, 0x98, 0xE6, 0x18, 0x55,
0xE5, 0x7F, 0x6F, 0x4A, 0x48, 0xB2, 0xF4, 0xBB, 0x17, 0x31, 0x0D, 0xFD,
0x3E, 0x4F, 0x42, 0xC8, 0x89, 0xA5, 0x96, 0x87, 0xD1, 0x50, 0x30, 0x26,
0x27, 0xDE, 0x21, 0x0A, 0x06, 0x26, 0xB3, 0x5B, 0x6D, 0x65, 0x34, 0x26,
0x45, 0x6C, 0x43, 0x50, 0xE6, 0x96, 0x45, 0x0A, 0x6E, 0x38, 0xB8, 0xF1,
0x06, 0x56, 0x4B, 0xAC, 0xE0, 0x65, 0xC8, 0xFF, 0xF1, 0x46, 0x10, 0x98,
0xDB, 0x6C, 0x41, 0x62, 0x6F, 0x98, 0x68, 0x45, 0x9C, 0x99, 0x71, 0xCD,
0xB3, 0xE3, 0xFB, 0x2A, 0x6A, 0x4D, 0x21, 0x09, 0x57, 0x24, 0x97, 0xF6,
0x54, 0xD4, 0x9A, 0x42, 0x12, 0xAE, 0x49, 0x2C, 0x2D, 0xF9, 0xB7, 0xDE,
0x14, 0xF8, 0x5B, 0xB8, 0x90, 0xFD, 0x6D, 0x6A, 0x95, 0xAB, 0x7A, 0xD9,
0x58, 0xE1, 0x5B, 0xDD, 0x01, 0x6A, 0x89, 0x45, 0x08, 0x9A, 0x70, 0x8D,
0x12, 0x56, 0x70, 0x33, 0x34, 0xC2, 0x67, 0x44, 0x44, 0x92, 0x6E, 0x26,
0x24, 0xB2, 0x68, 0xA0, 0x20, 0xA2, 0x74, 0x5D, 0x61, 0x12, 0x89, 0x2C,
0x32, 0x22, 0x01, 0x43, 0x4C, 0x96, 0x84, 0x24, 0x61, 0xCC, 0x89, 0xBD,
0x91, 0xA8, 0xED, 0x84, 0x6E, 0x61, 0x11, 0x24, 0xD4, 0x4A, 0x20, 0xAE,
0x01, 0xA0, 0x20, 0x26, 0x0A, 0x84, 0x6A, 0xA9, 0x8F, 0xFB, 0x66, 0x49,
0x20, 0x4C, 0x43, 0x48, 0xD4, 0x81, 0x04, 0x10, 0x03, 0x58, 0xE6, 0xD2,
0xEA, 0xAB, 0x4A, 0x0C, 0x55, 0x09, 0x44, 0xC3, 0x20, 0x95, 0x24, 0x61,
0x1A, 0xA0, 0xC0, 0x86, 0x93, 0x17, 0x19, 0x86, 0xEA, 0x20, 0x89, 0x6A,
0x83, 0x46, 0xE3, 0xD0, 0x0A, 0x5D, 0xB0, 0xD5, 0x58, 0xD8, 0x82, 0x24,
0x14, 0x30, 0x44, 0x02, 0xE6, 0x23, 0x11, 0xD0, 0x93, 0x0C, 0x95, 0x37,
0xC2, 0x20, 0x83, 0x37, 0x81, 0x26, 0xC4, 0x1B, 0xC5, 0xFA, 0x13, 0xD5,
0xC4, 0x09, 0x02, 0xEE, 0x4A, 0x8D, 0xEE, 0x3A, 0x2C, 0xB8, 0xE1, 0x74,
0x08, 0xB1, 0xAB, 0x82, 0x9A, 0xDD, 0xC4, 0x18, 0x30, 0x61, 0xBB, 0x0B,
0xDB, 0x8A, 0x2C, 0x46, 0x26, 0xC7, 0x64, 0xF4, 0x63, 0x41, 0xAC, 0x6B,
0xC5, 0x3A, 0x6F, 0x91, 0x0F, 0xE4, 0x4E, 0x29, 0xE8, 0x3D, 0x88, 0x86,
0xF1, 0x96, 0xD2, 0x6D, 0xE0, 0x81, 0x05, 0x2B, 0x4D, 0x21, 0x50, 0x1A,
0x44, 0xA6, 0x36, 0xB2, 0x31, 0x09, 0x41, 0x58, 0x9E, 0x50, 0xD6, 0x70,
0x34, 0xB0, 0x06, 0xC5, 0xF6, 0x12, 0x62, 0x4D, 0x3A, 0x90, 0x21, 0xA2,
0x13, 0xEB, 0x25, 0xB6, 0x9A, 0x20, 0xB5, 0x49, 0x74, 0x4D, 0x0E, 0x56,
0x11, 0x76, 0x7C, 0xBF, 0xA2, 0x49, 0x2E, 0xE5, 0xAA, 0xEA, 0x55, 0xCB,
0x91, 0xAF, 0xD1, 0x24, 0x97, 0x72, 0xD5, 0x75, 0x2A, 0xE5, 0xC8, 0xD6,
0x0D, 0xE9, 0xFB, 0xA0, 0x3E, 0x4A, 0x48, 0xFD, 0xA4, 0xA6, 0x29, 0xFC,
0xA8, 0xA0, 0x94, 0xCB, 0xB1, 0x6E, 0x81, 0x0C, 0x14, 0x86, 0x61, 0x84,
0xAD, 0x91, 0x24, 0x49, 0x49, 0xA8, 0xD4, 0x90, 0x2A, 0xA4, 0xC8, 0x11,
0x33, 0x04, 0xC4, 0x90, 0x88, 0x25, 0x22, 0x50, 0x1A, 0xCA, 0x86, 0xAC,
0xA0, 0x08, 0x30, 0x75, 0x12, 0x2B, 0x30, 0x83, 0x84, 0x0C, 0xF5, 0x70,
0xDA, 0xAC, 0xD2, 0x82, 0x18, 0x0A, 0x61, 0xA3, 0x1D, 0xC0, 0x88, 0x61,
0x09, 0x22, 0x66, 0x09, 0x89, 0xAE, 0x64, 0x90, 0x24, 0xA4, 0x94, 0x94,
0x00, 0x65, 0xA2, 0x09, 0x67, 0x41, 0xD4, 0x48, 0xD9, 0x2D, 0x30, 0x89,
0x43, 0x24, 0x1A, 0x8C, 0x04, 0x12, 0xD3, 0x05, 0x81, 0x46, 0x37, 0x63,
0x46, 0x64, 0x34, 0x98, 0x67, 0x63, 0x71, 0x72, 0xBA, 0x23, 0x6C, 0x89,
0xD8, 0x88, 0x61, 0x10, 0x54, 0x88, 0x52, 0x54, 0x6C, 0x06, 0xD4, 0x57,
0xDF, 0x19, 0x06, 0xEB, 0xCB, 0x42, 0xAA, 0xC8, 0x89, 0x73, 0x8D, 0x35,
0xC7, 0x2C, 0x02, 0x1A, 0xC6, 0x6C, 0xE8, 0x39, 0xAF, 0x88, 0x25, 0x5E,
0xD8, 0xA4, 0xA8, 0xC6, 0x93, 0x92, 0x38, 0xD4, 0x87, 0x39, 0x82, 0x22,
0x1B, 0x63, 0xDD, 0xC1, 0xE9, 0x55, 0xE4, 0x7F, 0x0A, 0x4F, 0xE3, 0xE8,
0x9B, 0x64, 0xE5, 0xB6, 0xD3, 0x65, 0x23, 0x15, 0x69, 0xBF, 0xDE, 0x1C,
0x2A, 0x37, 0xEA, 0xA9, 0xAB, 0x03, 0x64, 0x60, 0x28, 0xC2, 0x9F, 0xCD,
0x43, 0x6F, 0xA9, 0x93, 0x56, 0x47, 0x86, 0x09, 0x65, 0x92, 0xC2, 0x81,
0x56, 0xF0, 0xBB, 0x0A, 0x69, 0xFC, 0xB5, 0xBD, 0x5E, 0x32, 0x17, 0xD7,
0x67, 0xCF, 0xF9, 0x93, 0x72, 0xE5, 0xD4, 0xB9, 0x2A, 0xEB, 0x57, 0x22,
0x5F, 0xE6, 0x4D, 0xCB, 0x97, 0x52, 0xE4, 0xAB, 0xAD, 0x5C, 0x89, 0x7F,
0x89, 0xED, 0xD8, 0x49, 0x34, 0x97, 0x60, 0x8A, 0x01, 0x60, 0xAA, 0x80,
0x45, 0x3F, 0xAA, 0x66, 0x42, 0x5F, 0xAD, 0x80, 0xD6, 0x90, 0x2F, 0x4A,
0x41, 0x04, 0x10, 0x25, 0x06, 0x0A, 0x0C, 0x34, 0x04, 0x81, 0x84, 0x52,
0x01, 0x22, 0x84, 0x26, 0x93, 0x42, 0x01, 0x24, 0x0D, 0x96, 0x01, 0xB3,
0x10, 0x03, 0x40, 0x0C, 0xD0, 0x02, 0x75, 0x76, 0x86, 0xAC, 0xB5, 0xA4,
0xC4, 0xCC, 0x93, 0x00, 0x04, 0x3E, 0x42, 0x52, 0x27, 0xB9, 0x68, 0x8D,
0xDE, 0xBC, 0x90, 0x15, 0x98, 0xEC, 0x9A, 0x24, 0x04, 0x21, 0x13, 0x02,
0x37, 0x1A, 0x51, 0xAA, 0xC6, 0x99, 0x6A, 0x2C, 0x28, 0xD5, 0x1A, 0x59,
0x10, 0xCE, 0x83, 0x9D, 0x96, 0x59, 0x51, 0xA6, 0x57, 0x63, 0xE1, 0xB1,
0x32, 0xBA, 0x1B, 0x16, 0x57, 0xED, 0x76, 0xE3, 0x9C, 0x8B, 0xEF, 0xB8,
0x9B, 0x47, 0x2E, 0x1B, 0x58, 0xF8, 0xAD, 0xE0, 0xDC, 0xEE, 0xE6, 0x39,
0xA8, 0xDF, 0xB7, 0xE4, 0xD9, 0xE4, 0x6E, 0x85, 0x87, 0x38, 0xC4, 0xF6,
0xD5, 0xA0, 0xE4, 0xE2, 0x44, 0xE8, 0xD0, 0x91, 0x41, 0x42, 0x83, 0x03,
0x20, 0xB4, 0x98, 0x7A, 0x39, 0x41, 0x8B, 0x0F, 0x5E, 0xC0, 0x25, 0x55,
0x9F, 0x3F, 0xDB, 0x24, 0xAB, 0xBD, 0x15, 0x52, 0xAD, 0xC6, 0xA4, 0x8D,
0x7D, 0xB2, 0x4A, 0xBB, 0xD1, 0x55, 0x2A, 0xDC, 0x6A, 0x48, 0xD5, 0xB3,
0x0B, 0x75, 0x28, 0x3C, 0x4B, 0x17, 0x61, 0x26, 0x82, 0xB5, 0xFA, 0x4A,
0x0E, 0xD2, 0x9A, 0x12, 0x54, 0x19, 0x4F, 0x12, 0x72, 0xE4, 0x49, 0x8D,
0xA3, 0x40, 0x00, 0x47, 0x42, 0xC0, 0xDD, 0x49, 0x89, 0x12, 0x25, 0x12,
0x19, 0x10, 0x84, 0x10, 0x90, 0x44, 0x14, 0x44, 0x94, 0x90, 0x48, 0x82,
0x50, 0x52, 0x12, 0x6A, 0x21, 0x35, 0x28, 0x15, 0x69, 0x20, 0xA4, 0x98,
0x43, 0x21, 0xA4, 0x14, 0xB0, 0x09, 0x6C, 0xB0, 0x24, 0x50, 0x90, 0x12,
0xFD, 0x24, 0xA5, 0x26, 0x03, 0x03, 0x4E, 0xCB, 0x1B, 0x04, 0xB2, 0x24,
0x06, 0xC9, 0x26, 0x20, 0x08, 0x05, 0x2B, 0x1A, 0xA0, 0xA4, 0x84, 0x21,
0x03, 0x4C, 0x90, 0xD9, 0x9D, 0x86, 0x45, 0x95, 0x9A, 0x36, 0x64, 0xC9,
0x70, 0x5A, 0xC4, 0xAB, 0x71, 0xD0, 0x6F, 0x35, 0xEA, 0x6F, 0x56, 0x39,
0xF9, 0x35, 0x8F, 0x4B, 0xBD, 0xE5, 0xC6, 0x5F, 0xDC, 0xDF, 0xD3, 0x6B,
0xFF, 0x77, 0x7E, 0x3E, 0x1B, 0xE2, 0xF9, 0x50, 0xF8, 0x71, 0x15, 0xFF,
0xAA, 0x2F, 0x77, 0x07, 0xB6, 0xAB, 0xBC, 0x0B, 0x06, 0xFA, 0x50, 0x1C,
0x9E, 0xB4, 0x39, 0x50, 0xE8, 0x85, 0x0A, 0xDF, 0xF8, 0x32, 0x20, 0xEC,
0xF9, 0x7E, 0xD5, 0x22, 0xEE, 0xE2, 0xB6, 0x49, 0xAD, 0x5C, 0x8D, 0x7D,
0xAA, 0x45, 0xDD, 0xC5, 0x6C, 0x93, 0x5A, 0xB9, 0x1A, 0x9F, 0xDF, 0xE8,
0xAD, 0x07, 0x6E, 0x85, 0x83, 0xE0, 0xB1, 0xE3, 0xA2, 0x92, 0x4A, 0x11,
0x4A, 0x60, 0x1A, 0x88, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, 0x08,
0x5D, 0x04, 0x5A, 0x04, 0x00, 0x00, 0x73, 0x01, 0x01, 0x04, 0x00, 0x00,
0x00, 0x00, 0x08, 0xCF, 0x05, 0x00, 0x00, 0x40, 0x09, 0x00, 0x00, 0x37,
0xAA, 0x60, 0xD0, 0x24, 0x9A, 0x3F, 0x49, 0x2D, 0xA5, 0x8A, 0xA4, 0xC8,
0x0D, 0x24, 0x32, 0xAD, 0xC1, 0xB1, 0x05, 0x90, 0x21, 0x27, 0x6A, 0xCA,
0xA5, 0xB7, 0x48, 0x09, 0x01, 0x02, 0x55, 0x00, 0x11, 0x32, 0x84, 0x0A,
0x88, 0xA8, 0xB6, 0x0A, 0x29, 0x08, 0x21, 0x3B, 0x64, 0xC1, 0x88, 0x54,
0xE1, 0x1D, 0xC0, 0x41, 0x00, 0x26, 0xA8, 0x7C, 0x9A, 0x8F, 0xAA, 0xD3,
0x4D, 0x52, 0x00, 0x0A, 0x88, 0x63, 0x45, 0x40, 0x46, 0x1C, 0x80, 0x90,
0x0A, 0x49, 0x12, 0x84, 0x41, 0x31, 0x48, 0x48, 0xA9, 0x21, 0x04, 0xC9,
0x6B, 0x22, 0x24, 0xB3, 0x41, 0x73, 0x8F, 0x0E, 0xF5, 0x17, 0xC7, 0x22,
0xC9, 0xF7, 0x69, 0x67, 0x8E, 0x6F, 0xFA, 0xBD, 0xA5, 0xB7, 0xCC, 0x44,
0xCB, 0x0E, 0x67, 0x57, 0xAF, 0xAE, 0xB8, 0x3D, 0xE6, 0x4D, 0x9E, 0x78,
0xFC, 0x9E, 0xCD, 0x3A, 0xC9, 0xB2, 0xC2, 0xAE, 0x6E, 0x4B, 0x94, 0xF6,
0xAE, 0xE3, 0xB0, 0xF6, 0xD5, 0xF0, 0xA2, 0x27, 0x34, 0x8F, 0xE9, 0x47,
0x3A, 0x92, 0xE8, 0x84, 0xC4, 0x3C, 0x89, 0x64, 0x4C, 0x4C, 0x50, 0x8F,
0x0E, 0xBA, 0x26, 0x6B, 0xF8, 0xE0, 0x5A, 0xB8, 0xC6, 0x1E, 0xE9, 0x9B,
0x0B, 0x6F, 0xE6, 0xAC, 0x0F, 0x8F, 0xED, 0x52, 0x4B, 0xBB, 0x29, 0x79,
0x26, 0xAE, 0x24, 0xBF, 0xB5, 0x49, 0x2E, 0xEC, 0xA5, 0xE4, 0x9A, 0xB8,
0x92, 0xE7, 0x8B, 0x29, 0x2F, 0xA8, 0x5A, 0xE2, 0x49, 0xA5, 0xF1, 0x3C,
0x4F, 0xDF, 0x71, 0x84, 0x23, 0x0E, 0x16, 0x90, 0x90, 0x1D, 0x74, 0x52,
0x87, 0xEB, 0x49, 0x42, 0x42, 0x80, 0x99, 0x94, 0xA0, 0x48, 0x90, 0xDC,
0x33, 0x74, 0xC2, 0x93, 0x7B, 0x32, 0xFB, 0x80, 0x26, 0x48, 0x4C, 0x00,
0x28, 0x64, 0x54, 0x30, 0x18, 0x5B, 0x41, 0x43, 0x12, 0x84, 0x8D, 0xA1,
0x84, 0x1D, 0xB2, 0x30, 0x82, 0xCE, 0x86, 0xC5, 0xC5, 0x55, 0x4C, 0xBE,
0x5B, 0x41, 0x42, 0x6A, 0x3F, 0xA1, 0x20, 0xC4, 0x82, 0x08, 0x3B, 0xFF,
0x11, 0x71, 0x41, 0x75, 0x25, 0x10, 0x06, 0x10, 0x48, 0x20, 0xC1, 0x09,
0xD1, 0x05, 0xAA, 0xB5, 0x80, 0x6D, 0x4D, 0x4D, 0x89, 0xB8, 0x6B, 0x13,
0x20, 0xED, 0x43, 0xCD, 0x90, 0x67, 0xB0, 0x63, 0x63, 0x5B, 0x50, 0x01,
0x66, 0x59, 0x0C, 0x5F, 0x24, 0xC0, 0x9B, 0xC1, 0x6D, 0xC4, 0x33, 0x6D,
0x80, 0x19, 0xDC, 0xAF, 0x06, 0xF9, 0x69, 0xD3, 0x79, 0x89, 0x64, 0x86,
0x77, 0xB1, 0x0D, 0x68, 0xDA, 0xBD, 0x2F, 0x9B, 0xC7, 0x73, 0xB6, 0x32,
0x44, 0xAE, 0x33, 0x0C, 0x3F, 0x57, 0xB0, 0xAF, 0x6C, 0x99, 0xAF, 0x5A,
0xCE, 0x6E, 0xA2, 0x6E, 0x72, 0xB8, 0xD8, 0xF0, 0xDB, 0x78, 0x39, 0x39,
0x7A, 0x6F, 0x1A, 0x6E, 0x26, 0x93, 0xEF, 0x7A, 0x28, 0x8D, 0xA4, 0x32,
0x1C, 0x3F, 0x11, 0x03, 0x50, 0x16, 0x14, 0x09, 0xA1, 0x32, 0x06, 0xC6,
0x87, 0x94, 0xC5, 0x82, 0x7E, 0xCA, 0x1A, 0x28, 0xE0, 0xC6, 0xBC, 0xC5,
0x29, 0x21, 0x36, 0x04, 0x42, 0x41, 0x44, 0xD3, 0x4D, 0x3B, 0x3E, 0x3F,
0xB2, 0x49, 0x24, 0x92, 0xB2, 0x4A, 0x9A, 0xD4, 0x89, 0x7F, 0x64, 0x92,
0x49, 0x25, 0x64, 0x95, 0x35, 0xA9, 0x12, 0xC9, 0x7F, 0x42, 0x3F, 0x55,
0x4B, 0xE4, 0x71, 0x71, 0x2C, 0x69, 0x5B, 0xA6, 0x94, 0x54, 0xDA, 0x41,
0x8A, 0xA6, 0x82, 0x50, 0x0A, 0x4A, 0x4D, 0x25, 0x01, 0x08, 0x58, 0xC1,
0x80, 0x0C, 0x94, 0xE8, 0x92, 0xD0, 0x34, 0x00, 0x96, 0x98, 0x44, 0x4D,
0x49, 0x0C, 0x88, 0x2A, 0x84, 0x41, 0x80, 0x2F, 0x18, 0x66, 0x5B, 0x12,
0xD8, 0x08, 0x14, 0x50, 0x69, 0xA4, 0xA6, 0x92, 0x80, 0xC8, 0x10, 0x81,
0x33, 0xB1, 0x70, 0x02, 0x59, 0xB3, 0x24, 0x34, 0x48, 0x42, 0x2A, 0x04,
0xBF, 0x4A, 0xC5, 0x34, 0x2D, 0x03, 0x15, 0x42, 0x19, 0x26, 0x48, 0x44,
0xB4, 0x89, 0x82, 0x90, 0x64, 0x4A, 0x5B, 0x08, 0x9C, 0x34, 0xE9, 0x01,
0x58, 0x0E, 0xB2, 0xC8, 0xEE, 0x34, 0x1C, 0x71, 0xA6, 0x03, 0xDB, 0x3A,
0x21, 0x72, 0x9A, 0x1F, 0xF1, 0x93, 0x2B, 0xD4, 0x6B, 0x14, 0x6B, 0x95,
0xCA, 0x09, 0x86, 0x2E, 0xDE, 0xD5, 0x99, 0x5E, 0xC9, 0x85, 0x3B, 0xEE,
0x63, 0xB2, 0x6E, 0xDC, 0xDC, 0x2F, 0xDF, 0xA1, 0x5B, 0x5B, 0xF9, 0xB6,
0x3C, 0xAB, 0xC8, 0x56, 0xF6, 0x2B, 0x11, 0xD6, 0x74, 0x19, 0xA9, 0x6B,
0x64, 0xEE, 0xBF, 0x36, 0x9F, 0x05, 0x87, 0x83, 0x98, 0x97, 0x1C, 0x4D,
0x2E, 0xF2, 0x20, 0x5B, 0xCC, 0x0A, 0x28, 0xB8, 0x84, 0xDE, 0x18, 0xD2,
0x80, 0x97, 0xF3, 0xA4, 0xD0, 0xD3, 0xC4, 0x10, 0x97, 0x6F, 0xDD, 0x79,
0x89, 0x65, 0x0D, 0xA7, 0xE9, 0xDD, 0x4F, 0x47, 0x00, 0xA6, 0x17, 0x67,
0xC7, 0xF2, 0x91, 0x57, 0x72, 0x39, 0x92, 0xA6, 0xAE, 0xE4, 0x4F, 0x94,
0x8A, 0xBB, 0x91, 0xCC, 0x95, 0x35, 0x77, 0x22, 0x4F, 0x13, 0xF3, 0xFA,
0xA4, 0xBB, 0x34, 0xAD, 0x35, 0xD6, 0x04, 0xC0, 0x82, 0x2A, 0x36, 0xA9,
0x04, 0x97, 0x65, 0xAE, 0xB6, 0x22, 0x84, 0x11, 0x15, 0x23, 0x61, 0xB5,
0x4C, 0x96, 0x86, 0xCC, 0x98, 0x10, 0xBD, 0x84, 0x76, 0xD0, 0x95, 0x15,
0x21, 0x50, 0x20, 0x04, 0xB4, 0x50, 0x53, 0x34, 0xA5, 0xF1, 0x2D, 0x28,
0x80, 0x24, 0x68, 0xB7, 0x72, 0x60, 0xEE, 0x36, 0x60, 0x20, 0x55, 0x40,
0xA8, 0x09, 0x09, 0x4D, 0x4A, 0x53, 0x54, 0xA6, 0x88, 0x05, 0x90, 0x25,
0xAE, 0xB9, 0x4A, 0x25, 0x32, 0xC2, 0x01, 0xAC, 0xAA, 0x22, 0x42, 0x2A,
0x03, 0x4D, 0x67, 0x08, 0x4C, 0xA5, 0x90, 0x0B, 0x21, 0x53, 0x12, 0xD5,
0x14, 0x89, 0x53, 0xBF, 0x71, 0x70, 0x53, 0xB8, 0x8D, 0xB5, 0x91, 0xB1,
0xC2, 0x0C, 0x74, 0xDB, 0x32, 0xD1, 0x22, 0x4F, 0x70, 0xA4, 0x2A, 0xAE,
0x3D, 0x1B, 0xF4, 0xA3, 0x73, 0x5D, 0xD1, 0xF4, 0x5E, 0xE7, 0xBA, 0xD7,
0xB5, 0x2E, 0x0A, 0x2F, 0xC6, 0xA5, 0x7B, 0xAA, 0xEA, 0xEE, 0x9B, 0xDC,
0x4C, 0x89, 0x32, 0xEB, 0x24, 0xEF, 0x4E, 0xEE, 0x41, 0x8C, 0x78, 0xCF,
0x81, 0xE9, 0x27, 0xD5, 0x17, 0x91, 0x22, 0x36, 0xDB, 0x48, 0x7C, 0xEB,
0x43, 0x21, 0x61, 0xFF, 0x35, 0x47, 0x70, 0xCD, 0xAC, 0xBD, 0x1C, 0x2B,
0xC8, 0xB1, 0x59, 0xF1, 0xFC, 0xAD, 0x2A, 0xD7, 0x2B, 0x69, 0x4B, 0xE3,
0x52, 0x2F, 0xE5, 0x69, 0x56, 0xB9, 0x5B, 0x4A, 0x5F, 0x1A, 0x91, 0x64,
0x3F, 0x7C, 0xED, 0x9F, 0xD0, 0xFD, 0x05, 0x09, 0xA0, 0xA2, 0x1F, 0x02,
0x9A, 0x56, 0x25, 0xA9, 0xA1, 0x92, 0x44, 0x51, 0x04, 0xC8, 0xA5, 0x04,
0xD2, 0x0D, 0x44, 0x03, 0x29, 0x28, 0x3B, 0x51, 0x2E, 0xA0, 0x4C, 0xB3,
0x64, 0x06, 0x43, 0x0B, 0x48, 0x12, 0x26, 0x09, 0xDB, 0x27, 0x55, 0x98,
0x31, 0xD6, 0x12, 0x58, 0x9A, 0x16, 0x34, 0x84, 0x52, 0xFA, 0x80, 0x10,
0x4A, 0x84, 0x96, 0x74, 0x1A, 0x54, 0x4E, 0x5A, 0xEA, 0x0E, 0x1B, 0xF0,
0x42, 0xC0, 0x52, 0x83, 0x14, 0x34, 0xD3, 0x0C, 0x31, 0x01, 0x07, 0x68,
0x9A, 0xA9, 0x88, 0x12, 0x04, 0x20, 0x95, 0x89, 0x00, 0x82, 0x9A, 0x50,
0x03, 0xE0, 0x69, 0xAA, 0x98, 0x38, 0x66, 0xA5, 0x4C, 0x30, 0x48, 0x9C,
0x38, 0x11, 0x7E, 0xC6, 0xA1, 0xB8, 0x8E, 0xE0, 0x2E, 0x56, 0xB5, 0xC9,
0x62, 0x9A, 0xD8, 0xCC, 0x2B, 0xAB, 0x6D, 0xC3, 0x85, 0x79, 0xED, 0x4A,
0xE8, 0xAE, 0xDE, 0x9C, 0x31, 0xBB, 0x55, 0xF8, 0x94, 0x6D, 0x7B, 0x9E,
0x2B, 0xBB, 0x5E, 0x6F, 0x06, 0xD7, 0xA5, 0x65, 0x86, 0x42, 0xAB, 0xE0,
0x9B, 0xC4, 0x35, 0x7E, 0x29, 0xD5, 0x6B, 0x0F, 0x07, 0x34, 0x16, 0x37,
0xD0, 0xB5, 0xA6, 0x16, 0x0E, 0x20, 0xFB, 0xD5, 0x17, 0xA5, 0x0D, 0x65,
0x32, 0x09, 0x4F, 0x00, 0x58, 0x42, 0x02, 0xDE, 0x5C, 0xAC, 0xB8, 0x38,
0x1D, 0x56, 0x7C, 0xBF, 0x6B, 0x84, 0x4B, 0x32, 0xA5, 0x2F, 0x5A, 0xB9,
0x2F, 0xED, 0x70, 0x89, 0x66, 0x54, 0xA5, 0xEB, 0x57, 0x25, 0xD6, 0x54,
0xA2, 0xDC, 0xFC, 0x2D, 0x50, 0x94, 0x24, 0x0A, 0x63, 0x2F, 0x56, 0x20,
0x8A, 0x02, 0x34, 0x84, 0x95, 0x50, 0x53, 0x54, 0x24, 0x81, 0x28, 0x22,
0xA1, 0x49, 0x2C, 0x04, 0x02, 0x67, 0x66, 0xCC, 0x80, 0xC6, 0xA8, 0x4E,
0xE5, 0x09, 0x6D, 0xF2, 0x22, 0x2B, 0x22, 0xC9, 0x8C, 0x21, 0x20, 0x9A,
0x40, 0xA4, 0x2C, 0x01, 0xA0, 0x04, 0xA0, 0x92, 0x26, 0x04, 0x41, 0x6B,
0x21, 0xB0, 0x66, 0x58, 0x44, 0x94, 0x84, 0x95, 0x81, 0xA8, 0x80, 0x97,
0xCB, 0x1A, 0x52, 0x84, 0xE1, 0x18, 0x6A, 0x09, 0x32, 0x40, 0x04, 0x49,
0x6C, 0x61, 0x41, 0xC3, 0x2D, 0x10, 0x6A, 0x26, 0x42, 0x69, 0x02, 0xB2,
0x82, 0x10, 0x9A, 0xA2, 0x94, 0x81, 0x84, 0xEA, 0xAA, 0x4D, 0x58, 0xD2,
0xB7, 0x5E, 0xAE, 0xEE, 0x69, 0x13, 0xF3, 0x5F, 0x83, 0xC9, 0x17, 0xCD,
0x95, 0xF5, 0xE5, 0x26, 0x78, 0x21, 0xC2, 0xE1, 0x71, 0xD7, 0xEB, 0x87,
0xC3, 0xF8, 0x05, 0xDF, 0xE9, 0x21, 0x81, 0xAB, 0x97, 0xE3, 0x83, 0xDC,
0xE2, 0x87, 0xB6, 0xA9, 0x94, 0x38, 0x8A, 0x79, 0xD2, 0x9C, 0xA5, 0x8C,
0x74, 0x7D, 0x18, 0x82, 0x5C, 0x56, 0x87, 0x1D, 0x6C, 0xA8, 0x9E, 0x80,
0x3B, 0x3E, 0x4F, 0x98, 0xA8, 0xB8, 0x8C, 0x24, 0xBD, 0x5C, 0x8B, 0xF9,
0x8A, 0x8B, 0x88, 0xC2, 0x4B, 0xD5, 0xC8, 0xB2, 0xEC, 0xD0, 0x4D, 0xBD,
0x0F, 0xDF, 0x94, 0x14, 0xA0, 0x0E, 0x29, 0x7F, 0x29, 0x23, 0x68, 0xA2,
0x84, 0x04, 0x0C, 0x3D, 0x26, 0x60, 0x4A, 0x42, 0xD1, 0x41, 0x28, 0x25,
0x54, 0x89, 0x8D, 0x92, 0x64, 0x92, 0x49, 0x4A, 0x52, 0x94, 0x90, 0xC4,
0x21, 0xA9, 0xDE, 0x89, 0x37, 0xE4, 0x0A, 0x31, 0x29, 0x26, 0xAD, 0xF2,
0x8A, 0x22, 0xAB, 0xE2, 0x84, 0x24, 0x82, 0x02, 0x65, 0xB2, 0xDC, 0x50,
0xC6, 0x96, 0x4E, 0x12, 0x24, 0xC5, 0x5A, 0xCA, 0x85, 0x86, 0xEA, 0x14,
0xD5, 0x41, 0xC3, 0x46, 0x3D, 0x16, 0xC8, 0x9A, 0xA5, 0x32, 0x04, 0xA6,
0xAB, 0x42, 0x64, 0x81, 0xB0, 0x62, 0x90, 0x60, 0xCB, 0x0B, 0x50, 0xA4,
0x37, 0x44, 0x57, 0xFA, 0x90, 0x46, 0x64, 0x5C, 0x07, 0xBF, 0x2D, 0x8D,
0xAB, 0x9A, 0xEE, 0x65, 0xFE, 0x67, 0x4E, 0x09, 0x96, 0x2C, 0xDB, 0x57,
0x32, 0x45, 0xD3, 0xAA, 0xF3, 0x31, 0xB7, 0x38, 0xB7, 0xD9, 0xAB, 0xF9,
0x39, 0xB3, 0x4B, 0xF7, 0x0C, 0x86, 0x6C, 0x16, 0x8B, 0x15, 0xFE, 0xEB,
0xCF, 0x0F, 0x4D, 0x3E, 0x45, 0xE2, 0x8A, 0xA2, 0x75, 0x24, 0x7F, 0x17,
0x5E, 0x49, 0x8F, 0x56, 0xFA, 0xFD, 0x06, 0x17, 0x8B, 0xD7, 0xE5, 0x59,
0xF3, 0x7C, 0xAE, 0x88, 0x2A, 0xA5, 0x49, 0xC6, 0xAE, 0x44, 0xF9, 0x5D,
0x10, 0x55, 0x4A, 0x93, 0x8D, 0x5C, 0x89, 0x91, 0xA9, 0x43, 0xEE, 0x34,
0xD0, 0x82, 0x4C, 0x82, 0x1F, 0x89, 0x61, 0x9C, 0x24, 0x02, 0x00, 0x00,
0x00, 0x00, 0x82, 0x00, 0x00, 0x08, 0x5D, 0x04, 0xCD, 0x05, 0x00, 0x00,
0x73, 0x01, 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x08, 0xCF, 0x05, 0x00,
0x00, 0x85, 0x0A, 0x00, 0x00, 0x47, 0x89, 0x23, 0x64, 0xA6, 0x93, 0x40,
0xD1, 0x6D, 0x24, 0x19, 0x00, 0x04, 0x31, 0x5C, 0x22, 0x2C, 0x26, 0xE2,
0x08, 0xAA, 0x83, 0x04, 0x12, 0x8A, 0xA0, 0x18, 0x96, 0x02, 0x63, 0x45,
0x61, 0x44, 0xC0, 0x08, 0x34, 0xA6, 0x52, 0x52, 0x52, 0x04, 0xC1, 0x1A,
0x12, 0x00, 0x0D, 0x4B, 0x54, 0x69, 0x92, 0x49, 0x02, 0x8A, 0xB5, 0x00,
0x09, 0x4D, 0x2B, 0x74, 0x71, 0x4A, 0x56, 0x20, 0x20, 0xB0, 0x90, 0x70,
0xA4, 0x09, 0x93, 0x08, 0x95, 0x0C, 0xC1, 0x25, 0x80, 0x49, 0xA0, 0x04,
0x82, 0x6A, 0xD4, 0x41, 0x24, 0x16, 0x4B, 0x0E, 0xE2, 0xCD, 0xCC, 0xC7,
0x99, 0xE8, 0x0E, 0x79, 0xB7, 0xAC, 0xA3, 0x95, 0x6D, 0xDD, 0x7F, 0xC6,
0x71, 0x37, 0x6D, 0x2A, 0x2E, 0xE9, 0x4C, 0x5E, 0x9B, 0x69, 0x72, 0xCC,
0xBF, 0x92, 0xAB, 0xB9, 0x30, 0x6F, 0x9F, 0x3D, 0xB6, 0x1C, 0x26, 0xF7,
0x83, 0x97, 0x43, 0x9B, 0x28, 0x6D, 0x36, 0x84, 0xEA, 0x1C, 0xC9, 0x4D,
0xB0, 0x3E, 0x5F, 0xB4, 0xB5, 0x49, 0x71, 0x58, 0xDC, 0xBE, 0x35, 0x72,
0x54, 0xFB, 0x4B, 0x54, 0x97, 0x15, 0x8D, 0xCB, 0xE3, 0x57, 0x25, 0x4A,
0xCD, 0xF2, 0x4F, 0xEC, 0xB0, 0x25, 0x29, 0x42, 0x07, 0x1B, 0x03, 0x60,
0x08, 0xA4, 0x10, 0x98, 0xA8, 0x97, 0xD4, 0x8D, 0xC8, 0x48, 0x29, 0x1A,
0x48, 0x2D, 0x44, 0x88, 0xB0, 0xA1, 0x60, 0x91, 0x2A, 0xE1, 0xD5, 0x21,
0x86, 0x24, 0x49, 0x89, 0x0D, 0x68, 0x09, 0x60, 0x48, 0x09, 0x68, 0x21,
0x0F, 0xD0, 0xD6, 0x11, 0x20, 0xCE, 0xC3, 0x77, 0x42, 0x40, 0x20, 0xB4,
0x83, 0xB9, 0xA2, 0x9A, 0x08, 0x97, 0xC5, 0x14, 0xF1, 0x71, 0xAD, 0x52,
0xF9, 0x09, 0x58, 0x1A, 0x56, 0xA4, 0x14, 0x12, 0x1A, 0x27, 0x60, 0x82,
0x26, 0x20, 0xC1, 0x20, 0x90, 0x94, 0x1D, 0x8D, 0x82, 0xD0, 0x5A, 0x2E,
0xB1, 0x1B, 0x90, 0x7B, 0xC6, 0xA3, 0x86, 0xCA, 0xF8, 0x22, 0xC5, 0x9F,
0x29, 0x9C, 0x4B, 0xD5, 0x67, 0x59, 0x91, 0x26, 0x6E, 0xAE, 0x87, 0x25,
0xF3, 0x76, 0x49, 0x7D, 0xAC, 0x1D, 0x68, 0xFB, 0xD6, 0xAB, 0x11, 0xF7,
0x17, 0xE1, 0x5F, 0x3C, 0xE5, 0x58, 0x20, 0xC1, 0x54, 0x6E, 0xC5, 0xCA,
0xBA, 0x64, 0x3C, 0x15, 0x88, 0x2E, 0x85, 0x8F, 0x83, 0x62, 0x0A, 0xFE,
0x0A, 0x0E, 0x3D, 0x68, 0xC1, 0x11, 0x22, 0xB3, 0xE4, 0xFB, 0x48, 0xB5,
0xC2, 0x73, 0x2A, 0xAF, 0x8B, 0xB9, 0x2A, 0xFE, 0xD2, 0x2D, 0x70, 0x9C,
0xCA, 0xAB, 0xE2, 0xEE, 0x4A, 0xBA, 0xC9, 0x6E, 0x91, 0x6F, 0x3C, 0x49,
0x6A, 0x68, 0xAA, 0x86, 0xD5, 0x38, 0x6B, 0x00, 0x08, 0x58, 0x49, 0x20,
0x00, 0x52, 0x40, 0x40, 0x12, 0xB0, 0xA1, 0x12, 0xC8, 0x26, 0x19, 0x26,
0xE8, 0xD9, 0x0D, 0x32, 0x13, 0x38, 0x6D, 0x26, 0x24, 0xA9, 0xB0, 0x57,
0x14, 0x02, 0xD0, 0x01, 0xCB, 0x20, 0xBF, 0x80, 0x28, 0x44, 0xC2, 0x28,
0x1A, 0x02, 0x44, 0x00, 0x53, 0xA9, 0x3A, 0x92, 0xD0, 0x4A, 0x5B, 0x0F,
0xCA, 0x70, 0xC5, 0x2B, 0x68, 0x14, 0x92, 0xB7, 0x94, 0xA7, 0x89, 0x06,
0x69, 0x4D, 0x41, 0x24, 0xC3, 0x49, 0x1B, 0x31, 0x32, 0x92, 0x01, 0x24,
0x90, 0x2A, 0x92, 0xC9, 0x50, 0x57, 0xF7, 0xCE, 0x54, 0xD2, 0x9E, 0x5D,
0xAA, 0x73, 0x18, 0x40, 0xC9, 0x9D, 0x08, 0x8D, 0x8C, 0x4A, 0x98, 0x61,
0x69, 0x53, 0x65, 0x9A, 0x30, 0xD8, 0xE9, 0xA0, 0xDA, 0x16, 0x30, 0x5E,
0x2F, 0xBD, 0x9D, 0x3B, 0x97, 0x5C, 0xA6, 0x8B, 0x19, 0xD6, 0xB4, 0x3B,
0xBA, 0xE5, 0x39, 0xEE, 0x43, 0x4B, 0x7E, 0x95, 0x57, 0x56, 0xCA, 0xF6,
0x5B, 0x92, 0xB3, 0xB2, 0x60, 0x75, 0x70, 0xED, 0xDE, 0x5E, 0x0A, 0x45,
0x1E, 0xD5, 0x73, 0x81, 0x41, 0x14, 0xB1, 0x8F, 0xEA, 0x8B, 0x43, 0x5A,
0x02, 0x01, 0xC6, 0x0E, 0x07, 0xAB, 0x3E, 0x3F, 0x95, 0xAE, 0xA4, 0x97,
0x5D, 0xCA, 0x5E, 0xB5, 0x25, 0xD5, 0xFC, 0xAD, 0x75, 0x24, 0xBA, 0xEE,
0x52, 0xF5, 0xA9, 0x2E, 0xAE, 0x16, 0xDF, 0x20, 0xE5, 0x21, 0xFB, 0xE0,
0x5A, 0x81, 0x43, 0x54, 0x98, 0xA8, 0x10, 0x93, 0x02, 0xA8, 0x20, 0xA4,
0xA2, 0x6A, 0x22, 0x84, 0xA4, 0xB6, 0x9D, 0xE1, 0x43, 0x27, 0x64, 0x03,
0x30, 0x4A, 0xA8, 0xBD, 0x31, 0x26, 0xE1, 0x30, 0x49, 0x0C, 0x00, 0x43,
0x4D, 0x48, 0x21, 0x00, 0x80, 0x80, 0x40, 0x25, 0xFA, 0x5D, 0x8A, 0x4A,
0x48, 0x09, 0x40, 0x01, 0x84, 0xA6, 0x25, 0x01, 0x1A, 0x32, 0x1A, 0x2A,
0x12, 0x05, 0x44, 0x8A, 0xA9, 0x49, 0x44, 0xD0, 0x8A, 0x28, 0x5B, 0x58,
0x21, 0x01, 0x6D, 0x1E, 0x06, 0x29, 0x42, 0xCE, 0x84, 0xBA, 0xE5, 0x12,
0x77, 0x08, 0x12, 0x09, 0x49, 0x83, 0x00, 0x55, 0x01, 0x10, 0x96, 0xA6,
0x44, 0x9D, 0x1B, 0xE0, 0x10, 0x45, 0xC4, 0xCC, 0xCA, 0xEB, 0xEF, 0xF8,
0x40, 0xDE, 0xEC, 0x6E, 0xFB, 0xFE, 0xC3, 0x94, 0xB5, 0x92, 0x2D, 0x64,
0x99, 0x61, 0xC6, 0xB8, 0xE3, 0x73, 0x62, 0x8D, 0x11, 0xED, 0xF5, 0xB1,
0x7C, 0x38, 0x73, 0x5B, 0x01, 0xC6, 0xB9, 0x7D, 0x75, 0x93, 0xEA, 0xFD,
0xE2, 0xBA, 0x33, 0x17, 0x75, 0xD8, 0x9B, 0xB7, 0x2A, 0x44, 0xA8, 0xBB,
0x9D, 0xC5, 0x9A, 0x78, 0x71, 0x74, 0x85, 0x15, 0xB6, 0x88, 0x68, 0xA2,
0x93, 0x21, 0x3A, 0xB3, 0x1B, 0xE3, 0x04, 0x43, 0x91, 0x3B, 0x3E, 0x4F,
0x7A, 0x97, 0x2A, 0x49, 0x2B, 0x99, 0x47, 0x1A, 0xB9, 0x1A, 0xF7, 0xA9,
0x72, 0xA4, 0x92, 0xB9, 0x94, 0x71, 0xAB, 0x91, 0xA8, 0x7D, 0xC6, 0x69,
0xB7, 0x81, 0x4A, 0x00, 0x45, 0x58, 0x49, 0x8C, 0x20, 0xD1, 0x56, 0x00,
0x0C, 0x68, 0xAA, 0x0C, 0x9A, 0x08, 0x28, 0x09, 0x20, 0xD5, 0xA8, 0x64,
0x55, 0x03, 0x50, 0x49, 0xFF, 0x4C, 0xB0, 0x5E, 0x0C, 0x2A, 0x4C, 0x02,
0x1A, 0x2A, 0x92, 0x2F, 0x07, 0x2E, 0x26, 0x28, 0x35, 0x2A, 0x94, 0xD0,
0x94, 0x80, 0x84, 0x80, 0x49, 0x06, 0x10, 0x0E, 0x19, 0x2E, 0xA0, 0x77,
0x0D, 0x12, 0x61, 0x20, 0x19, 0x42, 0x69, 0x81, 0x55, 0x6A, 0x7C, 0x09,
0xFA, 0x5D, 0x60, 0x1D, 0x90, 0xA5, 0x2A, 0xD0, 0xA5, 0x27, 0x00, 0x23,
0x2F, 0x4A, 0x0C, 0x21, 0xF1, 0x6A, 0x69, 0x28, 0x80, 0x84, 0x13, 0x72,
0x9D, 0x89, 0xE6, 0x71, 0xFC, 0xEE, 0xE5, 0x61, 0xDD, 0x5A, 0xA3, 0x4A,
0xAA, 0xAA, 0x8D, 0xAD, 0x1C, 0x3B, 0xB5, 0xB8, 0xF4, 0x5F, 0xDA, 0xAE,
0xF7, 0x08, 0xBD, 0x65, 0xB4, 0xBA, 0x73, 0x44, 0xEB, 0x1B, 0xA4, 0x52,
0x04, 0xC1, 0x54, 0x45, 0xF9, 0xAC, 0xD9, 0x73, 0x78, 0x29, 0xA6, 0xDE,
0x98, 0xD2, 0x4F, 0x8C, 0x4A, 0x24, 0xD6, 0xC9, 0x29, 0x08, 0x18, 0x4C,
0xC6, 0x44, 0x03, 0xB6, 0x7C, 0xBF, 0x35, 0xA9, 0x32, 0x5C, 0x56, 0xE5,
0x1A, 0xD6, 0xA4, 0x97, 0xF3, 0x5A, 0x93, 0x25, 0xC5, 0x6E, 0x51, 0xAD,
0x6A, 0x49, 0x75, 0x1F, 0xA1, 0x2B, 0x6F, 0xD0, 0x95, 0xA0, 0x10, 0x11,
0x07, 0x8E, 0x4B, 0x18, 0x15, 0xA8, 0xA1, 0x46, 0xD0, 0x63, 0x0D, 0x00,
0x21, 0x28, 0x10, 0x51, 0x12, 0x20, 0x30, 0x49, 0x89, 0x4B, 0x0C, 0x16,
0x18, 0x98, 0x64, 0x08, 0x03, 0x45, 0xAC, 0x29, 0x90, 0x80, 0x93, 0x22,
0x49, 0x58, 0xEE, 0x94, 0x90, 0x97, 0xE8, 0x35, 0x4D, 0x04, 0x42, 0x08,
0xA9, 0x37, 0x49, 0x0D, 0x0A, 0x28, 0x43, 0xAC, 0x19, 0xA9, 0x4B, 0x11,
0x4D, 0x15, 0x05, 0x2B, 0x42, 0x82, 0x5F, 0x42, 0x61, 0x32, 0x09, 0x04,
0x26, 0x20, 0x81, 0x11, 0x31, 0x3B, 0x21, 0xA0, 0x13, 0x50, 0x18, 0x41,
0x28, 0x02, 0x93, 0x42, 0x56, 0x35, 0x12, 0x69, 0x84, 0x94, 0x8A, 0xAC,
0x24, 0x09, 0x03, 0x5D, 0xC3, 0x55, 0x71, 0x5F, 0x38, 0x79, 0x2B, 0x63,
0x70, 0x06, 0xE7, 0x70, 0x71, 0x45, 0x8D, 0xE2, 0x22, 0xD6, 0xEB, 0x0A,
0x29, 0x9B, 0xCB, 0xC9, 0xB5, 0x7E, 0xDF, 0xD5, 0xF9, 0x25, 0x6E, 0xE9,
0x5F, 0x67, 0x6B, 0x5A, 0xCB, 0xB9, 0xC9, 0x5D, 0xC4, 0x75, 0xD3, 0x4B,
0x3D, 0x8E, 0xA6, 0x0B, 0xD9, 0xE1, 0x4F, 0x52, 0xE2, 0x12, 0x4C, 0x4A,
0xA1, 0x22, 0xE2, 0x84, 0xE2, 0x59, 0x84, 0x81, 0x49, 0x3D, 0x41, 0x7D,
0x9F, 0x1F, 0xBD, 0x5C, 0xBA, 0x4B, 0x9B, 0xA9, 0x51, 0x7A, 0xB9, 0x24,
0xF7, 0xAB, 0x97, 0x49, 0x73, 0x75, 0x2A, 0x2F, 0x57, 0x24, 0x89, 0xA8,
0xB6, 0xB5, 0x4D, 0x29, 0x47, 0x1D, 0x65, 0x21, 0xD9, 0x5B, 0x82, 0x09,
0x97, 0x58, 0x03, 0x2E, 0x2E, 0x99, 0x80, 0x68, 0x4B, 0xF8, 0x35, 0x0B,
0x61, 0xB4, 0xA4, 0xB1, 0x93, 0x84, 0x18, 0x48, 0x63, 0x12, 0x59, 0x3A,
0xDA, 0x89, 0x6B, 0x42, 0x26, 0x59, 0x4A, 0x29, 0x24, 0x86, 0x04, 0x82,
0x13, 0x41, 0x62, 0x41, 0x62, 0x5A, 0x20, 0x84, 0x83, 0x0C, 0x9C, 0x2E,
0x99, 0x20, 0x81, 0x97, 0x04, 0x00, 0x5F, 0x14, 0xC2, 0x42, 0x0B, 0xAD,
0x09, 0x42, 0xA5, 0x04, 0x34, 0x15, 0x09, 0x04, 0x2B, 0xAD, 0x15, 0x08,
0x90, 0xD4, 0x24, 0x1A, 0xB4, 0x10, 0x2A, 0xC9, 0x01, 0x89, 0x07, 0x08,
0xAE, 0x2A, 0x43, 0x41, 0x50, 0x87, 0x23, 0x9B, 0x03, 0x1B, 0x3E, 0x4F,
0x4D, 0x3A, 0xB3, 0xB8, 0xE8, 0xF7, 0xD2, 0xA3, 0x77, 0x5A, 0x00, 0xC6,
0x16, 0x12, 0x17, 0x4A, 0xBD, 0xB9, 0xB5, 0x49, 0x6C, 0x2E, 0xC7, 0xAE,
0x07, 0x32, 0x04, 0x95, 0x2F, 0x8D, 0xF9, 0x46, 0xF8, 0x58, 0xE3, 0x05,
0xFD, 0x7B, 0x72, 0xF6, 0x25, 0x8A, 0x0C, 0x9E, 0x3B, 0x94, 0xF8, 0xF0,
0x8A, 0x57, 0x7A, 0xC6, 0x52, 0x86, 0x84, 0xF2, 0xDA, 0xA7, 0xC1, 0x9A,
0xA4, 0x23, 0x33, 0xAF, 0x01, 0x98, 0xC2, 0xE6, 0xAE, 0xF7, 0xFE, 0x57,
0x2D, 0x12, 0x2A, 0x2E, 0x44, 0x49, 0x7F, 0x2B, 0x96, 0x89, 0x15, 0x17,
0x22, 0x24, 0xB2, 0x7F, 0x75, 0xC0, 0xED, 0xE9, 0x58, 0xF1, 0x07, 0xD3,
0x29, 0x5B, 0x23, 0x69, 0x08, 0x06, 0xAD, 0x29, 0x45, 0x47, 0xDF, 0xF0,
0x50, 0x4A, 0x53, 0x87, 0x45, 0x2D, 0x09, 0x06, 0xA2, 0x45, 0x5D, 0x26,
0x5B, 0x86, 0xA9, 0xAB, 0x08, 0x60, 0x09, 0xA8, 0x23, 0x65, 0x00, 0xDC,
0x2A, 0xBF, 0x4A, 0x0D, 0x00, 0x9B, 0x80, 0xA1, 0x01, 0xA0, 0x53, 0x06,
0xAB, 0x57, 0x98, 0x27, 0x15, 0x43, 0x05, 0xBA, 0x00, 0x12, 0x4A, 0x02,
0x02, 0x66, 0x12, 0x0D, 0x66, 0x82, 0x45, 0x49, 0xD4, 0x6E, 0x40, 0x49,
0xDA, 0x59, 0xA8, 0x64, 0x42, 0xB2, 0x40, 0x50, 0xB4, 0x35, 0xA0, 0xC1,
0xA0, 0xE1, 0x81, 0x5C, 0x80, 0x27, 0x50, 0x36, 0x01, 0x5F, 0x05, 0xAD,
0xED, 0x9B, 0x3A, 0x61, 0x29, 0x34, 0xBA, 0x28, 0x04, 0xCE, 0xB4, 0x5A,
0x04, 0x90, 0xCD, 0x13, 0xAD, 0x99, 0x24, 0x85, 0x40, 0x0A, 0xA9, 0x38,
0x42, 0x18, 0x12, 0x23, 0xA3, 0xB6, 0x86, 0xA6, 0x14, 0x62, 0xED, 0xB1,
0x43, 0x05, 0x71, 0xB8, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, 0x08,
0x5D, 0x04, 0x41, 0x07, 0x00, 0x00, 0x73, 0x01, 0x01, 0x06, 0x00, 0x00,
0x00, 0x00, 0x08, 0xCF, 0x05, 0x00, 0x00, 0xDC, 0x0B, 0x00, 0x00, 0x56,
0x50, 0x34, 0x46, 0xC1, 0x60, 0x88, 0xE6, 0xBB, 0x96, 0xEF, 0x54, 0x19,
0x99, 0xC2, 0x26, 0xA9, 0xAA, 0x24, 0xC9, 0xB3, 0xA3, 0xD1, 0x53, 0x19,
0x6B, 0x60, 0x77, 0xC0, 0x4A, 0xFE, 0xEC, 0x69, 0x84, 0xC5, 0x86, 0x58,
0x70, 0x99, 0xF7, 0x6A, 0xB6, 0x73, 0x1E, 0x7D, 0xEC, 0xF1, 0xBE, 0xBE,
0xF5, 0xF5, 0x09, 0x8A, 0x2B, 0x7C, 0x59, 0x43, 0xFB, 0x83, 0x10, 0xB3,
0xB1, 0x07, 0x5C, 0x03, 0x1F, 0xE0, 0x49, 0x0B, 0x6A, 0xD1, 0xD6, 0x62,
0xB5, 0x35, 0xB7, 0xC4, 0xF8, 0xC6, 0x65, 0x78, 0x43, 0xB2, 0xFD, 0x6F,
0x73, 0x8B, 0x2E, 0xCA, 0x93, 0x5D, 0xCE, 0x2C, 0xBB, 0x2A, 0x4D, 0x3E,
0x49, 0x1C, 0x42, 0x82, 0x69, 0xAA, 0x99, 0x4C, 0x0A, 0x82, 0x1D, 0x44,
0xA6, 0x2A, 0x24, 0xCB, 0x52, 0x40, 0x30, 0xC4, 0x6A, 0x63, 0x45, 0x1B,
0x61, 0x81, 0x0D, 0x12, 0x58, 0x50, 0xA9, 0x24, 0x94, 0x80, 0x4A, 0x6A,
0x80, 0x01, 0x69, 0x05, 0x56, 0x32, 0x4B, 0x00, 0x98, 0x00, 0x94, 0x94,
0x96, 0xCF, 0x62, 0x24, 0x40, 0x1B, 0x98, 0x30, 0xD2, 0x41, 0xD3, 0x4C,
0x97, 0xA2, 0x69, 0xE5, 0x34, 0xDE, 0x44, 0x5C, 0xA2, 0xBC, 0xAB, 0xFD,
0x82, 0x4B, 0x74, 0x4D, 0x20, 0x41, 0xA4, 0xCC, 0x42, 0x00, 0x40, 0x92,
0x52, 0x09, 0xA2, 0x8C, 0x2A, 0xA4, 0xD4, 0x40, 0x00, 0x06, 0x92, 0x49,
0x32, 0x49, 0x53, 0x69, 0x4A, 0x52, 0x4A, 0x49, 0x33, 0x65, 0x8F, 0x14,
0x24, 0x5E, 0xDF, 0x63, 0xCD, 0xF1, 0x52, 0x2A, 0xEF, 0x9B, 0xE2, 0xA4,
0x55, 0xDB, 0x1F, 0x23, 0x57, 0x1D, 0xA6, 0x62, 0x0B, 0x24, 0x18, 0x69,
0x42, 0xA4, 0xCC, 0x3A, 0x92, 0x34, 0x70, 0xC9, 0x63, 0x4C, 0xA0, 0x91,
0x04, 0x41, 0x61, 0x95, 0x08, 0x79, 0xC4, 0x19, 0x75, 0x67, 0xC1, 0xF5,
0x8B, 0xD5, 0xC2, 0x8A, 0x24, 0x91, 0x2E, 0xFD, 0x62, 0xF5, 0x70, 0xA2,
0x89, 0x24, 0x4B, 0xB1, 0x42, 0x28, 0x7D, 0x94, 0x1A, 0x50, 0xB7, 0x41,
0x6C, 0xA0, 0x10, 0x66, 0x12, 0x22, 0x48, 0x82, 0x88, 0x2C, 0x02, 0x22,
0xA2, 0x49, 0x32, 0xD1, 0x54, 0xC1, 0x27, 0x64, 0x24, 0xA0, 0x1A, 0x60,
0xA4, 0xEF, 0x09, 0x06, 0xA5, 0x0E, 0xA2, 0x42, 0x10, 0x4C, 0x29, 0x54,
0x90, 0xB1, 0x30, 0x02, 0x2F, 0xC0, 0x26, 0x01, 0x01, 0x06, 0x40, 0x61,
0x30, 0x24, 0x89, 0x3B, 0x25, 0x02, 0x49, 0x30, 0x0C, 0x55, 0x61, 0x60,
0x75, 0x49, 0x53, 0x70, 0x6A, 0x2C, 0x48, 0x04, 0xC4, 0x4C, 0x2B, 0x16,
0x05, 0x52, 0x11, 0x12, 0x01, 0xDA, 0x81, 0xD4, 0xD0, 0x01, 0x32, 0x19,
0xA0, 0x58, 0x4E, 0xF7, 0xA8, 0x83, 0xA2, 0xAB, 0x62, 0x57, 0xCA, 0x85,
0x7C, 0xC0, 0xDA, 0xB0, 0x57, 0xB7, 0x5C, 0xDE, 0xA0, 0x77, 0xA9, 0x77,
0x90, 0x52, 0x50, 0x01, 0x8E, 0xCF, 0x9B, 0xF4, 0x97, 0xAB, 0x84, 0xA5,
0x42, 0x48, 0x97, 0x35, 0xFA, 0x4B, 0xD5, 0xC2, 0x52, 0xA1, 0x24, 0x4B,
0x9A, 0x22, 0x38, 0xD6, 0xF8, 0x96, 0xE8, 0xAB, 0x4A, 0x1F, 0xE5, 0x34,
0x14, 0x10, 0x28, 0x89, 0x6B, 0x41, 0x92, 0x64, 0xFF, 0x98, 0x14, 0x32,
0x48, 0xC3, 0x10, 0x18, 0x98, 0x12, 0x48, 0x4C, 0x20, 0xA8, 0x53, 0x23,
0xBA, 0x8C, 0x84, 0x82, 0x0B, 0x55, 0x08, 0x32, 0xD2, 0xB0, 0x82, 0x80,
0x6A, 0x19, 0x86, 0x13, 0x35, 0x48, 0x05, 0x20, 0x41, 0x0C, 0x06, 0x6A,
0x10, 0x60, 0x41, 0x1B, 0x0C, 0x86, 0x02, 0x4A, 0xC5, 0x59, 0x23, 0x0A,
0x04, 0x16, 0xA4, 0x90, 0x46, 0xC9, 0x6A, 0x8B, 0x12, 0x14, 0x4A, 0x24,
0xED, 0x98, 0x40, 0x81, 0x90, 0x54, 0xD1, 0x60, 0x26, 0x49, 0x49, 0x24,
0x6C, 0x6D, 0xA0, 0xE1, 0x83, 0x51, 0x18, 0x6D, 0x2C, 0x15, 0x2A, 0x54,
0x80, 0x20, 0x21, 0x08, 0x01, 0xA0, 0xCE, 0xA4, 0x06, 0x01, 0x2A, 0xCB,
0x00, 0x9D, 0xC3, 0x18, 0x10, 0x03, 0x4A, 0x49, 0x81, 0x0A, 0xED, 0x85,
0x33, 0x10, 0xC5, 0x4C, 0xCB, 0x49, 0x60, 0x80, 0x03, 0x22, 0x09, 0x9A,
0xA4, 0x98, 0x55, 0x24, 0x9D, 0x05, 0x20, 0xC3, 0x5A, 0x4C, 0xA8, 0x00,
0x0D, 0x24, 0xB2, 0x1B, 0x2B, 0xE6, 0x46, 0x9A, 0xA0, 0xBC, 0x92, 0xA1,
0x95, 0x3B, 0x37, 0x4C, 0x93, 0x01, 0x8A, 0x8B, 0xDA, 0x22, 0x15, 0x80,
0xC8, 0x2C, 0x62, 0xF6, 0x77, 0xCE, 0x72, 0xC2, 0x5C, 0xDC, 0xEE, 0x1D,
0xCD, 0x92, 0x57, 0xE2, 0x93, 0x26, 0xFD, 0xE3, 0x81, 0x0D, 0xC5, 0x0F,
0x55, 0xDE, 0x8F, 0x8C, 0x6C, 0x4D, 0x0C, 0x85, 0x25, 0x67, 0xD3, 0xFB,
0x5E, 0xA6, 0xA0, 0xA1, 0x2A, 0x54, 0xB5, 0xCD, 0x7E, 0xD7, 0xA9, 0xA8,
0x28, 0x4A, 0x95, 0x2D, 0x73, 0x42, 0xAB, 0xA0, 0x8E, 0x25, 0xB4, 0x2D,
0xA6, 0x92, 0x97, 0xC7, 0x0A, 0x04, 0xC1, 0x82, 0x42, 0xA0, 0x28, 0x04,
0x96, 0x98, 0x0A, 0x03, 0x28, 0x04, 0xCB, 0x60, 0x16, 0x01, 0x24, 0x19,
0x84, 0x1C, 0x20, 0x76, 0x60, 0x98, 0x6C, 0x02, 0x76, 0x5A, 0x01, 0x86,
0x02, 0x58, 0x0B, 0x08, 0x6C, 0xA0, 0x24, 0x01, 0x10, 0x4A, 0x60, 0xB5,
0xA2, 0x4B, 0x01, 0x89, 0x30, 0x04, 0x90, 0x60, 0x2A, 0xC6, 0x89, 0x17,
0xC0, 0xAA, 0x92, 0x4A, 0xCF, 0x21, 0x13, 0xAA, 0xA8, 0x42, 0x12, 0x18,
0x01, 0x00, 0x89, 0x81, 0xA1, 0xAC, 0x20, 0xDA, 0x82, 0xA8, 0x11, 0x21,
0xA0, 0x13, 0x09, 0x89, 0x40, 0xDB, 0x50, 0x42, 0x4D, 0x65, 0x26, 0x66,
0x92, 0x80, 0x49, 0x2C, 0x64, 0x45, 0x48, 0x20, 0x14, 0x55, 0x89, 0x0C,
0x04, 0xEA, 0x44, 0xA9, 0xA4, 0x90, 0x67, 0x98, 0xD0, 0x10, 0x40, 0x33,
0x3A, 0x98, 0x04, 0x26, 0xC4, 0x96, 0x90, 0x70, 0x99, 0x20, 0x6A, 0x34,
0x76, 0xD8, 0x61, 0x61, 0xBC, 0xB4, 0x02, 0x1A, 0x89, 0x02, 0x50, 0x77,
0xBE, 0x5B, 0x1D, 0x34, 0x1D, 0xED, 0x49, 0xEE, 0x3A, 0xB8, 0x4A, 0xE1,
0xA6, 0x18, 0x54, 0xB4, 0x04, 0x81, 0x60, 0x40, 0xB2, 0xA1, 0x1C, 0x89,
0x8D, 0xF7, 0xDC, 0x42, 0xFC, 0x6B, 0xA5, 0x40, 0x40, 0x54, 0x4D, 0xF8,
0xDB, 0x0A, 0xA8, 0x7B, 0xC6, 0x26, 0x2E, 0x5C, 0x54, 0x97, 0xA1, 0x1B,
0xC0, 0x86, 0x32, 0x7A, 0xDB, 0x83, 0x32, 0xE5, 0xEF, 0x0C, 0x72, 0x1E,
0x93, 0xD0, 0x9E, 0xEF, 0x8B, 0xE0, 0x7B, 0xAA, 0xB3, 0xE6, 0xFC, 0xD5,
0xDE, 0xA2, 0xEA, 0x29, 0x2A, 0x2E, 0x49, 0x77, 0xF9, 0xAB, 0xBD, 0x45,
0xD4, 0x52, 0x54, 0x5C, 0x92, 0xEC, 0xA6, 0x41, 0xCA, 0x00, 0x59, 0x94,
0xB6, 0xFF, 0xF2, 0x7D, 0x41, 0x42, 0x4D, 0x08, 0x8D, 0x11, 0x54, 0x19,
0x4C, 0x02, 0x4C, 0x34, 0x0D, 0xC9, 0x6B, 0x12, 0x44, 0xB5, 0x06, 0x62,
0x03, 0x13, 0x11, 0xB8, 0x21, 0x0A, 0xA4, 0x19, 0x27, 0x43, 0x60, 0xD5,
0x90, 0xC8, 0x43, 0x09, 0x04, 0x10, 0x44, 0x41, 0xD9, 0x04, 0x40, 0x01,
0x2D, 0x09, 0x81, 0x62, 0x0C, 0xB0, 0xA2, 0xA3, 0x24, 0x9A, 0x84, 0x09,
0xD8, 0x31, 0x55, 0x82, 0x24, 0x11, 0x00, 0xA7, 0x2E, 0x82, 0x21, 0x20,
0x84, 0x8D, 0x40, 0x3A, 0x2D, 0x02, 0x0E, 0xD9, 0xB6, 0x69, 0x28, 0x3B,
0xA1, 0x20, 0xC8, 0x84, 0x82, 0x59, 0x1A, 0x69, 0x90, 0x76, 0x26, 0x41,
0x42, 0x50, 0x41, 0x44, 0x10, 0x95, 0x49, 0x06, 0x45, 0xD7, 0xB0, 0xF7,
0x55, 0x8A, 0x01, 0x64, 0x91, 0x07, 0xA3, 0x10, 0x3A, 0x62, 0x41, 0x29,
0x38, 0x40, 0x6E, 0x53, 0x0D, 0x11, 0x07, 0x66, 0x40, 0x20, 0x6D, 0x90,
0x49, 0x31, 0x10, 0x01, 0x92, 0x58, 0xBA, 0x49, 0x86, 0x80, 0x20, 0x9D,
0x15, 0x2F, 0xDC, 0x42, 0xCA, 0x20, 0xAE, 0x17, 0xCD, 0xC5, 0x9D, 0x58,
0x26, 0x0B, 0x42, 0xB0, 0xC8, 0x6C, 0xC7, 0x6D, 0xDC, 0x45, 0xE0, 0xC1,
0x77, 0x84, 0xB3, 0xED, 0x83, 0x17, 0x38, 0x18, 0x46, 0x4E, 0xC6, 0xFB,
0x16, 0x21, 0xEA, 0xA2, 0x8D, 0x65, 0xF0, 0x59, 0x78, 0xF0, 0x17, 0x9B,
0x4D, 0x0D, 0x7E, 0x63, 0x78, 0xFD, 0x82, 0x4F, 0xFC, 0xFE, 0x41, 0xD1,
0x16, 0x47, 0x79, 0x25, 0x38, 0x53, 0x14, 0xD4, 0xDF, 0xCA, 0x36, 0xBC,
0x5B, 0xF3, 0x7E, 0x6A, 0xF5, 0x76, 0x8A, 0x2A, 0x25, 0x4B, 0x97, 0x77,
0xF9, 0xAB, 0xD5, 0xDA, 0x28, 0xA8, 0x95, 0x2E, 0x5D, 0xDA, 0x4D, 0x4A,
0x7F, 0x7F, 0xB7, 0xC8, 0xC1, 0x53, 0xB6, 0x43, 0xEA, 0x50, 0x09, 0x41,
0x13, 0x21, 0x28, 0x89, 0xD3, 0x58, 0x90, 0x20, 0x85, 0x00, 0x60, 0x84,
0x19, 0x0C, 0x68, 0x89, 0x0D, 0x81, 0x06, 0x49, 0x04, 0xC4, 0x65, 0x8C,
0x82, 0x48, 0x62, 0xB1, 0x34, 0xA1, 0x00, 0x90, 0x49, 0x89, 0x02, 0xA9,
0x43, 0x0C, 0x90, 0x0D, 0x42, 0x80, 0x41, 0x03, 0x0E, 0xE0, 0x4C, 0x02,
0x60, 0x24, 0x48, 0x4E, 0x8C, 0x87, 0x59, 0x06, 0x5A, 0x22, 0x65, 0x08,
0x24, 0xA1, 0x02, 0x40, 0x48, 0x02, 0x4A, 0x60, 0x4A, 0xCE, 0x63, 0x2A,
0xA5, 0x80, 0xA5, 0x97, 0x96, 0xEA, 0x16, 0x2C, 0xEC, 0xD4, 0x0D, 0x02,
0x00, 0x24, 0x0A, 0xC8, 0x12, 0x51, 0x44, 0x49, 0x00, 0xA0, 0x52, 0x94,
0x2D, 0x21, 0x26, 0x62, 0x82, 0x99, 0xD1, 0x48, 0x31, 0x26, 0x24, 0x6C,
0x28, 0x59, 0x54, 0x44, 0xFF, 0xD4, 0x69, 0x1B, 0x03, 0x44, 0xA6, 0x26,
0x58, 0x83, 0x84, 0xCD, 0x40, 0x21, 0x30, 0x43, 0x44, 0x83, 0x37, 0x25,
0xA0, 0xC9, 0x20, 0x19, 0x13, 0x0A, 0x24, 0x16, 0x81, 0x20, 0xC2, 0x50,
0x12, 0x58, 0x4A, 0x24, 0x36, 0x5A, 0xCD, 0x30, 0xAA, 0x0B, 0xBB, 0x61,
0x86, 0xE8, 0x1B, 0x2B, 0xD5, 0x99, 0x83, 0xBE, 0xAF, 0xF4, 0x1E, 0x9C,
0xC6, 0xF3, 0x88, 0xE5, 0xB2, 0xD9, 0x0C, 0x8D, 0xF3, 0x1C, 0xC1, 0x67,
0xBE, 0x88, 0x20, 0x39, 0x5E, 0xC3, 0xB7, 0x90, 0xC6, 0xFB, 0x10, 0x2D,
0xEA, 0xC9, 0x4F, 0x2B, 0x43, 0x3A, 0xC0, 0xF7, 0xA0, 0x31, 0x32, 0xA3,
0x17, 0xA3, 0x80, 0x53, 0x84, 0x68, 0x11, 0xD9, 0x17, 0xFC, 0x5F, 0xCC,
0x9A, 0xE1, 0x50, 0x94, 0xBA, 0x89, 0x72, 0xE6, 0xBF, 0x32, 0x6B, 0x85,
0x42, 0x52, 0xEA, 0x25, 0xCB, 0x9A, 0x14, 0xFE, 0xD2, 0x78, 0xC5, 0xBE,
0x25, 0x04, 0xC8, 0x6C, 0x19, 0x24, 0x4D, 0x48, 0x41, 0x20, 0x82, 0x99,
0x94, 0x1C, 0x29, 0x82, 0xD9, 0x23, 0x08, 0x55, 0x48, 0x15, 0x70, 0x8C,
0x91, 0x22, 0xA9, 0x2C, 0x02, 0x36, 0x61, 0x62, 0xA4, 0x90, 0x04, 0x19,
0xA4, 0x00, 0x09, 0x20, 0x02, 0x63, 0x47, 0x68, 0x20, 0x92, 0x08, 0x24,
0xD5, 0x94, 0x00, 0x4A, 0x56, 0x10, 0x6A, 0x83, 0x22, 0x62, 0x24, 0xA4,
0x20, 0x6F, 0x40, 0x9D, 0x02, 0xAE, 0x84, 0x4E, 0x88, 0x11, 0x86, 0x3B,
0x52, 0xA0, 0x16, 0x18, 0x4D, 0xED, 0xD3, 0x20, 0x1B, 0xBA, 0xBB, 0x97,
0xAB, 0x5E, 0x79, 0x15, 0xF6, 0x39, 0x3C, 0x25, 0xD7, 0xA7, 0xD6, 0x98,
0xB0, 0xB4, 0x6A, 0xC6, 0x4C, 0x8C, 0x89, 0x5F, 0xEE, 0x05, 0x00, 0x00,
0x00, 0x00, 0x82, 0x00, 0x00, 0x08, 0x5D, 0x04, 0xB4, 0x08, 0x00, 0x00,
0x73, 0x01, 0x01, 0x07, 0x00, 0x00, 0x00, 0x00, 0x08, 0xCF, 0x05, 0x00,
0x00, 0xF2, 0x0C, 0x00, 0x00, 0x66, 0x91, 0xE7, 0x8D, 0x2C, 0x86, 0x14,
0x80, 0x5A, 0x88, 0x09, 0xBC, 0x99, 0xDC, 0xA6, 0x93, 0x14, 0x50, 0x2A,
0xA6, 0x92, 0x94, 0xA4, 0x21, 0x6A, 0x84, 0x55, 0x7E, 0xFE, 0x9A, 0x4C,
0x21, 0xA9, 0x4E, 0xC9, 0x26, 0xA2, 0x00, 0xAA, 0x92, 0xC0, 0x0A, 0x52,
0xF3, 0x4D, 0x83, 0x97, 0x7B, 0xBF, 0x5E, 0x52, 0x64, 0x9A, 0xD7, 0xAF,
0x29, 0x32, 0x4D, 0x68, 0x86, 0xBA, 0x9A, 0x43, 0x48, 0x01, 0x90, 0x82,
0x3B, 0x34, 0x2C, 0x10, 0x62, 0xA1, 0x08, 0x22, 0xA8, 0x83, 0x24, 0x14,
0xD5, 0x43, 0x60, 0x29, 0xB0, 0xA7, 0x6C, 0x97, 0x95, 0x9F, 0x0F, 0xE6,
0xFC, 0xCA, 0x54, 0x91, 0x77, 0x7F, 0x37, 0xE6, 0x52, 0xA4, 0x8B, 0xBB,
0xA5, 0xFF, 0x12, 0x77, 0x7C, 0xC6, 0x83, 0x43, 0x25, 0x3A, 0x02, 0x4E,
0x90, 0x05, 0x42, 0x62, 0x0B, 0x20, 0xCC, 0x4A, 0xB2, 0x6A, 0x4B, 0x52,
0x1B, 0x2C, 0x0C, 0x94, 0x34, 0x10, 0x41, 0x04, 0x44, 0xCC, 0x06, 0xC8,
0x6C, 0xC5, 0xA1, 0x6F, 0xE1, 0x51, 0xE6, 0x25, 0x1A, 0xE0, 0xF9, 0x7F,
0x2B, 0xBD, 0x41, 0x50, 0xAA, 0x95, 0x7A, 0xBB, 0xBD, 0x7E, 0x57, 0x7A,
0x82, 0xA1, 0x55, 0x2A, 0xF5, 0x77, 0x7A, 0xF5, 0x52, 0x69, 0xA0, 0xD0,
0x9A, 0x29, 0xE2, 0x7C, 0xF9, 0xF5, 0x00, 0x12, 0x40, 0x50, 0x10, 0x08,
0x68, 0x83, 0x04, 0x80, 0xCD, 0x16, 0x61, 0xB6, 0x48, 0xDA, 0x1A, 0x90,
0xA8, 0x24, 0xA5, 0xA8, 0xAB, 0x30, 0x40, 0x24, 0x10, 0x41, 0xAB, 0x3B,
0xD6, 0xD9, 0x35, 0x11, 0x52, 0x41, 0x48, 0xD4, 0x08, 0xC3, 0x20, 0x16,
0x96, 0x86, 0x13, 0x02, 0x0D, 0x56, 0x02, 0x99, 0x4D, 0x42, 0x98, 0x01,
0x08, 0x02, 0x60, 0xF3, 0x92, 0x01, 0x80, 0x6A, 0x3B, 0x29, 0x09, 0x28,
0xD1, 0x28, 0x62, 0x4A, 0x08, 0x20, 0x55, 0xA8, 0xC6, 0xA5, 0x00, 0xA0,
0x89, 0x44, 0x83, 0x2D, 0xD5, 0x22, 0x41, 0x68, 0x82, 0x51, 0x24, 0x14,
0x48, 0x28, 0x09, 0x98, 0xC3, 0x30, 0x70, 0x02, 0xD5, 0x29, 0x41, 0x12,
0x82, 0x8A, 0x12, 0x42, 0x60, 0x8A, 0x00, 0x95, 0x64, 0x82, 0xD0, 0x1A,
0x01, 0x82, 0x82, 0x6A, 0x86, 0x15, 0x44, 0x7C, 0x84, 0xB3, 0x57, 0x16,
0x6D, 0x90, 0xA2, 0x8A, 0xA8, 0x19, 0xC8, 0xE0, 0x6A, 0xAE, 0x9C, 0xE2,
0xA7, 0xD5, 0x0B, 0x43, 0xB8, 0x66, 0x15, 0x41, 0xBF, 0x24, 0xBE, 0xB8,
0xBB, 0x48, 0x6C, 0x16, 0x5D, 0x5B, 0x8F, 0x30, 0xF0, 0xB3, 0xA6, 0x8A,
0x5F, 0x53, 0x83, 0x22, 0x20, 0x72, 0xBB, 0x3D, 0xFF, 0xB4, 0xBD, 0x69,
0x29, 0x0A, 0xA4, 0xAD, 0x5E, 0xAE, 0xEF, 0xED, 0x2F, 0x5A, 0x4A, 0x42,
0xA9, 0x2B, 0x57, 0xAB, 0xBB, 0xC2, 0xFD, 0xF1, 0x0E, 0x35, 0xA4, 0xA6,
0xDD, 0xF9, 0xAD, 0x2D, 0x5B, 0xCD, 0x00, 0xA5, 0x01, 0x28, 0x91, 0xB4,
0x19, 0x09, 0x03, 0x61, 0x22, 0x41, 0x42, 0x48, 0x13, 0x28, 0x30, 0x94,
0x24, 0x18, 0x69, 0x08, 0xA6, 0x19, 0x54, 0x06, 0xC6, 0x47, 0x40, 0x94,
0xA1, 0x04, 0xB0, 0x91, 0x56, 0x82, 0xC6, 0xCA, 0x09, 0x05, 0x09, 0xD2,
0x95, 0x44, 0x16, 0x16, 0x24, 0x00, 0x48, 0x92, 0x36, 0x2A, 0x82, 0x36,
0x8C, 0x31, 0x45, 0x21, 0x22, 0xA5, 0x30, 0x82, 0x7C, 0x0A, 0x9A, 0x5F,
0x03, 0x0C, 0x24, 0x32, 0xAA, 0x24, 0x12, 0x10, 0x92, 0x32, 0xE8, 0x04,
0x94, 0x45, 0x34, 0x04, 0x86, 0x82, 0x15, 0x85, 0x8D, 0x04, 0x81, 0x23,
0xFE, 0x89, 0xBC, 0x48, 0x09, 0x03, 0x75, 0x13, 0x06, 0x2A, 0xA2, 0x60,
0xC4, 0x11, 0xD8, 0x21, 0x4E, 0x3F, 0xD7, 0x1A, 0x35, 0x28, 0x75, 0x41,
0x93, 0x61, 0x21, 0x44, 0xD0, 0x4C, 0x29, 0x86, 0x84, 0x80, 0x7B, 0x0B,
0xE3, 0xA3, 0x2A, 0xEF, 0x44, 0x32, 0x62, 0x54, 0x30, 0x42, 0x84, 0x11,
0x32, 0x25, 0x86, 0xF0, 0x64, 0x37, 0x98, 0x04, 0x2A, 0x31, 0xAF, 0x07,
0x53, 0x78, 0x06, 0x54, 0xBC, 0x03, 0x88, 0xB0, 0xDD, 0x3D, 0x2F, 0x61,
0x0C, 0x38, 0xE0, 0xE7, 0x4C, 0xCE, 0xBB, 0x59, 0x71, 0x65, 0x43, 0xCB,
0x81, 0xBD, 0x93, 0xF9, 0xA6, 0x24, 0x28, 0xB1, 0x18, 0xD3, 0x41, 0xB8,
0x29, 0xC0, 0xC5, 0x94, 0x19, 0xA7, 0xB0, 0xD4, 0x18, 0x41, 0x20, 0x22,
0xFE, 0x58, 0x0C, 0xBD, 0x9E, 0x9F, 0xAE, 0xB8, 0xE2, 0x30, 0xB4, 0xAC,
0xBC, 0xC9, 0xC7, 0x1A, 0x8F, 0x5D, 0x71, 0xC4, 0x61, 0x69, 0x59, 0x79,
0x93, 0x8E, 0x35, 0x14, 0xA0, 0xC3, 0xA2, 0x30, 0x12, 0x24, 0xA0, 0xB0,
0xB0, 0x80, 0x50, 0x91, 0x84, 0x95, 0x40, 0x20, 0x18, 0x91, 0x28, 0x4B,
0xF6, 0x34, 0xC5, 0x20, 0x82, 0x25, 0x60, 0xFD, 0xFB, 0xF2, 0x02, 0x60,
0x91, 0x21, 0x09, 0x06, 0x49, 0xA4, 0x4A, 0x92, 0x82, 0x24, 0x11, 0x52,
0x80, 0xBC, 0x31, 0x22, 0x40, 0xAA, 0x62, 0xA1, 0xBA, 0x42, 0x46, 0x1D,
0x26, 0x08, 0x06, 0x0C, 0x34, 0x13, 0x56, 0xA0, 0xA4, 0x22, 0x05, 0x50,
0x06, 0xA6, 0xA2, 0x37, 0x09, 0x84, 0x91, 0x22, 0xAA, 0x10, 0x4A, 0x0A,
0x44, 0xB0, 0x82, 0x8D, 0xC9, 0x3B, 0x6C, 0x82, 0x01, 0x84, 0x90, 0x10,
0x0C, 0x98, 0x20, 0xB5, 0x84, 0x22, 0x80, 0x36, 0xC0, 0x94, 0x14, 0x84,
0x12, 0x1F, 0x50, 0x34, 0x64, 0x11, 0x56, 0x02, 0x50, 0x10, 0x52, 0x98,
0xA9, 0x15, 0x68, 0x05, 0x61, 0x20, 0x02, 0x99, 0x00, 0x11, 0x22, 0x60,
0xEE, 0x7E, 0x62, 0xE8, 0xD8, 0x03, 0xA2, 0xCC, 0xCC, 0x46, 0xB5, 0xFA,
0x41, 0xF9, 0x64, 0x2F, 0x27, 0x7E, 0x02, 0x01, 0x2B, 0x23, 0x3C, 0x6B,
0xC9, 0xA1, 0xA1, 0xA1, 0x92, 0x26, 0x01, 0x58, 0x69, 0xCD, 0x0A, 0xB6,
0xB1, 0x0C, 0x2B, 0xA8, 0x2D, 0xE8, 0x8A, 0xD3, 0xC1, 0xA0, 0x92, 0x45,
0x4C, 0x4D, 0xB7, 0x06, 0x7F, 0xCB, 0x6D, 0xB6, 0xBF, 0x0A, 0xF3, 0x11,
0x34, 0xB8, 0x9B, 0x0A, 0x09, 0x89, 0x32, 0x81, 0xF3, 0x4A, 0x24, 0x44,
0x9E, 0x10, 0x99, 0x2C, 0x4A, 0x16, 0x52, 0xFE, 0x84, 0xBB, 0x6C, 0xA5,
0xA6, 0xC7, 0x15, 0x44, 0x9E, 0x70, 0x63, 0x6D, 0x05, 0x9D, 0x88, 0xDF,
0x17, 0x4F, 0xE4, 0xF3, 0x49, 0x3C, 0x3E, 0x38, 0x91, 0x5C, 0x48, 0xA1,
0x67, 0x0D, 0xF5, 0xA4, 0x6F, 0x14, 0xC5, 0x12, 0x49, 0xA8, 0xB1, 0x0A,
0x62, 0x28, 0xB1, 0x74, 0xB9, 0x14, 0xCE, 0xCC, 0xEF, 0x4D, 0xC4, 0x7A,
0x5D, 0x9E, 0x45, 0xEC, 0x82, 0x9E, 0xC5, 0x89, 0xA5, 0x3D, 0xEE, 0x97,
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0x30, 0x24, 0x92, 0x18, 0x49, 0x09, 0x6C, 0x05, 0x15, 0x20, 0xA0, 0x8A,
0xAC, 0x58, 0xD2, 0x94, 0x90, 0x84, 0x4C, 0x42, 0x49, 0x4E, 0x1D, 0x29,
0x08, 0x40, 0x6B, 0xB3, 0x55, 0x08, 0xA4, 0xA4, 0xBE, 0x7C, 0x0A, 0x4D,
0x08, 0x42, 0x11, 0x09, 0x42, 0x44, 0x84, 0x10, 0x52, 0x92, 0x02, 0xA6,
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0xA2, 0x5F, 0x20, 0xC3, 0x05, 0x56, 0x36, 0x51, 0x84, 0x62, 0xAC, 0x55,
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0x99, 0x93, 0x25, 0xB0, 0xBF, 0x35, 0x8A, 0x05, 0xE4, 0x79, 0xC0, 0xE0,
0x5A, 0x02, 0x1A, 0x30, 0x5C, 0x65, 0x6E, 0x97, 0x7C, 0xEA, 0xE7, 0x17,
0x99, 0xE5, 0x7B, 0x40, 0x29, 0x78, 0x2A, 0x29, 0xEB, 0x62, 0xE2, 0x58,
0x55, 0x32, 0x85, 0xD6, 0xD9, 0x58, 0x98, 0xB9, 0xCE, 0x29, 0xA9, 0xE5,
0x88, 0x7D, 0xEB, 0x24, 0x84, 0x34, 0xDA, 0x65, 0x3D, 0xCA, 0x5C, 0x1B,
0x4D, 0xBE, 0xA5, 0xC4, 0xFB, 0xD1, 0x2E, 0x73, 0x2E, 0x29, 0x4A, 0xEB,
0xE1, 0x47, 0x1C, 0x58, 0xBD, 0xE2, 0x20, 0x79, 0xE0, 0x50, 0xA5, 0x77,
0x08, 0x6C, 0x6D, 0x89, 0x88, 0x4B, 0x82, 0xE4, 0x41, 0x14, 0xB1, 0x34,
0x96, 0x39, 0xC8, 0x82, 0xE0, 0xDF, 0x44, 0x9F, 0x7A, 0x7F, 0x13, 0x89,
0xA5, 0xDE, 0xA4, 0xFA, 0x9E, 0x9B, 0xE7, 0x34, 0xD4, 0xF7, 0xBA, 0x6E,
0xAA, 0xCA, 0x50, 0xFE, 0x5C, 0x4B, 0x23, 0x0A, 0x77, 0x83, 0xE2, 0xE4,
0x41, 0x75, 0x28, 0x89, 0x08, 0x5D, 0x89, 0xD1, 0x3C, 0xEC, 0xD1, 0xDA,
0x6B, 0xCB, 0x06, 0x9D, 0xBE, 0x8E, 0x7D, 0x54, 0xDD, 0xF7, 0x75, 0x77,
0x5B, 0xAB, 0xC9, 0x7D, 0x5D, 0xC6, 0x7D, 0x54, 0xDD, 0xF7, 0x75, 0x77,
0x5B, 0xAB, 0xC9, 0x7D, 0x5D, 0xC2, 0x49, 0x31, 0xB3, 0x60, 0xB4, 0x48,
0x99, 0x93, 0xC9, 0xF9, 0x90, 0x24, 0x63, 0x94, 0xA1, 0x6A, 0x10, 0x72,
0xD2, 0xA3, 0x4A, 0xC5, 0xF8, 0x37, 0x58, 0x61, 0x76, 0x49, 0x20, 0x0E,
0x7B, 0x0F, 0xD2, 0x4A, 0x86, 0x58, 0x2A, 0x18, 0x80, 0x62, 0xA9, 0xC3,
0x75, 0x26, 0xA4, 0x21, 0x04, 0xBE, 0x01, 0x01, 0x84, 0x21, 0x24, 0x24,
0x21, 0x95, 0x9A, 0x51, 0x04, 0x30, 0xCB, 0x74, 0xC2, 0x4C, 0x35, 0xAE,
0xBA, 0xBA, 0x24, 0x96, 0x32, 0x62, 0x49, 0x08, 0x32, 0x21, 0xD9, 0x32,
0x90, 0x01, 0xA4, 0x99, 0x22, 0x65, 0x0B, 0x00, 0x44, 0x2A, 0xD3, 0xA8,
0x33, 0x42, 0x21, 0x42, 0xD2, 0xCD, 0xA0, 0xBF, 0x24, 0x9E, 0x51, 0xB8,
0x73, 0xBB, 0xC0, 0x40, 0x24, 0x0E, 0x36, 0x18, 0xD5, 0x18, 0x4C, 0xDD,
0x0C, 0x38, 0xBC, 0xE6, 0xA8, 0xF9, 0xAB, 0x94, 0xCA, 0xF5, 0xFE, 0x56,
0x86, 0x5B, 0x11, 0x7B, 0xCD, 0x72, 0xE8, 0x34, 0xFF, 0xA5, 0xD1, 0x4E,
0xF6, 0x28, 0xA7, 0x7A, 0x39, 0xCE, 0xB4, 0x37, 0x96, 0x84, 0x9C, 0x44,
0xB9, 0xC0, 0xB7, 0x8B, 0xA2, 0x1A, 0x6D, 0x37, 0x40, 0x43, 0x5D, 0x29,
0x89, 0x11, 0x09, 0x54, 0x92, 0x42, 0x43, 0x7D, 0x12, 0x1B, 0x7C, 0x6D,
0x54, 0x85, 0xDE, 0xB1, 0x21, 0x85, 0x58, 0x73, 0x7D, 0xE7, 0x0A, 0x5B,
0xE3, 0x97, 0xBD, 0x36, 0x35, 0xC5, 0xA7, 0xA7, 0xA6, 0x2C, 0x21, 0xAE,
0x21, 0x24, 0x8A, 0x59, 0x29, 0xF5, 0xA5, 0xA2, 0x48, 0x2E, 0x08, 0xA3,
0x9C, 0x1F, 0x1B, 0x28, 0x49, 0xA4, 0x7F, 0x01, 0xEC, 0xF4, 0xDE, 0xE7,
0x10, 0xE0, 0x57, 0xFA, 0x1A, 0xF3, 0x26, 0x5D, 0x66, 0x68, 0xDC, 0x94,
0x9C, 0x6A, 0x5C, 0xAF, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, 0x08,
0x5D, 0x04, 0x28, 0x0A, 0x00, 0x00, 0x73, 0x01, 0x01, 0x08, 0x00, 0x00,
0x00, 0x00, 0x08, 0xCF, 0x05, 0x00, 0x00, 0x0C, 0x0E, 0x00, 0x00, 0x76,
0xFB, 0x06, 0x4C, 0xBA, 0xCC, 0xD1, 0xB9, 0x29, 0x38, 0xD4, 0xB8, 0xFC,
0x49, 0x2D, 0x76, 0x88, 0x17, 0x12, 0x80, 0x55, 0x8A, 0x6A, 0x01, 0xD1,
0xA7, 0x14, 0xB3, 0xFE, 0x96, 0x08, 0x40, 0x4D, 0x4A, 0x48, 0x25, 0x08,
0x00, 0x12, 0x82, 0x00, 0xC3, 0x30, 0x48, 0x12, 0x90, 0x98, 0x75, 0x90,
0x6A, 0x92, 0xA1, 0x9F, 0x52, 0x64, 0x98, 0x32, 0x9A, 0x00, 0x36, 0xD5,
0x56, 0x6E, 0x93, 0x0C, 0x0D, 0xC4, 0xC9, 0x77, 0xAB, 0x77, 0x7F, 0x73,
0x5D, 0x09, 0x9B, 0xE1, 0xC4, 0xA9, 0x50, 0x57, 0xAE, 0x9D, 0x28, 0xF0,
0x0C, 0xCD, 0xD4, 0xF9, 0xA4, 0x76, 0x50, 0xF1, 0xD5, 0x9E, 0x31, 0x8C,
0x4E, 0x1A, 0x68, 0x4D, 0x31, 0x94, 0x32, 0x72, 0x9A, 0x15, 0x7C, 0x79,
0xE3, 0xCC, 0x4E, 0x8E, 0x80, 0xC4, 0xA7, 0xB1, 0x2F, 0xF3, 0x04, 0x28,
0x52, 0x56, 0x32, 0x55, 0x8A, 0x42, 0x60, 0xA6, 0x21, 0x62, 0x41, 0x4A,
0x42, 0x42, 0x0C, 0x72, 0x6A, 0x8E, 0x16, 0x9B, 0x57, 0x8A, 0xAF, 0xF4,
0x85, 0x6D, 0x6C, 0x2D, 0x22, 0xB2, 0x01, 0xB6, 0x05, 0x0F, 0xA8, 0xA1,
0x08, 0x40, 0x4A, 0x53, 0x2C, 0x88, 0x74, 0x38, 0x2B, 0x7C, 0x74, 0xA2,
0x80, 0xD4, 0xAC, 0x10, 0x4B, 0xD3, 0x6F, 0xF4, 0xFB, 0x9F, 0x1B, 0xDC,
0xEA, 0xDA, 0xDC, 0xF8, 0xDE, 0xE7, 0x56, 0xD0, 0x08, 0xE3, 0x29, 0x6E,
0xD5, 0xED, 0xF2, 0x6A, 0xA1, 0x34, 0x10, 0x50, 0x96, 0xCE, 0xA6, 0xA3,
0x2C, 0xFB, 0x9B, 0x8C, 0x41, 0x8D, 0xBD, 0x32, 0x1B, 0x3D, 0x7E, 0x4F,
0x6F, 0x7D, 0xF1, 0xE7, 0x8A, 0xD6, 0x4F, 0x6F, 0x7D, 0xF1, 0xE7, 0x8A,
0xD1, 0x15, 0x69, 0x0C, 0x50, 0xAE, 0x25, 0x6B, 0x89, 0x14, 0x9A, 0x10,
0x52, 0x74, 0xBC, 0xC1, 0x2B, 0xCA, 0xF7, 0x76, 0x8E, 0xD0, 0x5E, 0x9B,
0x78, 0x7C, 0x5B, 0xDF, 0x77, 0xC6, 0xAE, 0xB5, 0x19, 0xDF, 0x2D, 0x5F,
0x1A, 0xB2, 0xF7, 0xBE, 0xEF, 0x8D, 0x5D, 0x6A, 0x33, 0xBE, 0x5A, 0xBE,
0x35, 0x65, 0xD5, 0x54, 0x21, 0xF9, 0x56, 0x80, 0xFC, 0x97, 0x5D, 0xBF,
0xCD, 0x84, 0x65, 0xA8, 0x64, 0x34, 0x31, 0x53, 0xD4, 0xEA, 0x2A, 0x2B,
0x42, 0x0D, 0x9B, 0x80, 0x2B, 0xB7, 0x24, 0x96, 0xCF, 0x5A, 0x1D, 0xEE,
0x64, 0x9B, 0x80, 0x3A, 0x98, 0x18, 0x72, 0x52, 0x96, 0x20, 0x51, 0x45,
0x00, 0x13, 0x56, 0xA2, 0x10, 0x10, 0xED, 0xB8, 0x8F, 0x1B, 0xF5, 0x8F,
0x17, 0x17, 0x1A, 0xD8, 0xE2, 0xA1, 0x6E, 0x8A, 0x5F, 0xD0, 0xB7, 0x4B,
0xFA, 0x02, 0x28, 0x4D, 0x0B, 0x54, 0x25, 0xFA, 0x5F, 0xD5, 0xE3, 0xA5,
0xD8, 0x0F, 0x85, 0x2B, 0x54, 0x04, 0x91, 0x4D, 0x0B, 0x10, 0x10, 0x4A,
0xC5, 0x04, 0x90, 0x00, 0x25, 0x10, 0x5A, 0x0F, 0x5A, 0x64, 0xA3, 0x0D,
0xA2, 0x87, 0xE0, 0x88, 0x06, 0xC1, 0x98, 0x3D, 0x63, 0xE5, 0x12, 0xB3,
0x7D, 0xC3, 0x0D, 0xE0, 0xE3, 0x9A, 0xE8, 0x29, 0x5E, 0xC2, 0x69, 0x8B,
0xD4, 0x85, 0x92, 0x34, 0xB3, 0x08, 0xE1, 0xBB, 0xCF, 0x3A, 0x00, 0x55,
0x09, 0x12, 0x2A, 0x10, 0x4C, 0xEA, 0x1A, 0x32, 0xD2, 0xC0, 0xC6, 0xB2,
0x2E, 0x61, 0x18, 0xC4, 0x35, 0xA0, 0x89, 0x89, 0x04, 0x2A, 0x44, 0x2B,
0x0D, 0x12, 0x55, 0x1A, 0x6B, 0xDE, 0x54, 0x8E, 0x18, 0x53, 0xF0, 0x02,
0xD6, 0x60, 0x26, 0xF5, 0x22, 0xC9, 0xFE, 0xC9, 0x11, 0x62, 0x97, 0x67,
0xBB, 0x9C, 0xD5, 0xEA, 0xDB, 0xBB, 0xBD, 0xF7, 0x97, 0x7A, 0xE2, 0xE2,
0x5E, 0x73, 0x57, 0xAB, 0x6E, 0xEE, 0xF7, 0xDE, 0x5D, 0xEB, 0x8B, 0x89,
0x70, 0x62, 0x28, 0x5B, 0xA1, 0x21, 0x02, 0x84, 0x02, 0x43, 0x29, 0xA2,
0x94, 0x26, 0x84, 0xC2, 0x44, 0x89, 0x82, 0x18, 0x48, 0x90, 0x54, 0x8B,
0x14, 0x15, 0x68, 0x4D, 0x29, 0x27, 0x1D, 0x2A, 0x7B, 0x55, 0x10, 0xBF,
0xAB, 0x98, 0x72, 0xC5, 0x79, 0x41, 0x8A, 0xA8, 0x90, 0x12, 0xB0, 0xA4,
0xD3, 0x56, 0x8A, 0x4D, 0x1C, 0x6F, 0x92, 0x08, 0x9A, 0x29, 0x7C, 0xB6,
0xB5, 0x4B, 0xEA, 0x42, 0x29, 0xA1, 0x28, 0x4D, 0x0F, 0xC2, 0x29, 0xA1,
0x33, 0x42, 0xDD, 0x01, 0x20, 0x13, 0x42, 0x43, 0x24, 0x30, 0x9C, 0x31,
0x20, 0x82, 0x0B, 0x41, 0x61, 0x0A, 0x82, 0x0C, 0x12, 0x02, 0xBF, 0x09,
0x91, 0x25, 0x06, 0xE5, 0x1A, 0x64, 0x96, 0xE8, 0xC1, 0x37, 0x44, 0x69,
0x87, 0xDF, 0xCE, 0x42, 0xCF, 0x33, 0xB8, 0x6D, 0xA0, 0x0B, 0xA2, 0xE4,
0xC2, 0xF9, 0x32, 0x5D, 0xE4, 0x0F, 0x90, 0xC5, 0x4C, 0x59, 0x6B, 0x61,
0xAA, 0x05, 0x03, 0x09, 0xE7, 0x5B, 0x49, 0xE1, 0x5D, 0x5A, 0xF1, 0xB4,
0x10, 0xCD, 0x8E, 0xC1, 0xBC, 0x10, 0xA8, 0x96, 0x82, 0xA1, 0xE9, 0xEF,
0x4C, 0xBE, 0x29, 0x30, 0xDA, 0x0F, 0x62, 0x7D, 0x5C, 0xE2, 0xA8, 0xBE,
0xF7, 0xB8, 0x86, 0x72, 0x9A, 0x98, 0x4A, 0xAC, 0x43, 0x5C, 0x44, 0x8D,
0xD3, 0xEA, 0xE2, 0x8D, 0xB7, 0xA6, 0xAC, 0xF6, 0xBC, 0x4D, 0x5D, 0xB2,
0xA2, 0xDC, 0xA4, 0xBB, 0x49, 0xA9, 0xE2, 0x6A, 0xED, 0x95, 0x16, 0xE5,
0x25, 0xDA, 0x4D, 0x42, 0x49, 0x8B, 0x78, 0x4C, 0x0E, 0x37, 0xF5, 0x62,
0x1A, 0x2A, 0x00, 0xC1, 0x24, 0x9D, 0x46, 0x11, 0x40, 0x92, 0x76, 0x4C,
0xC4, 0x00, 0x0D, 0x30, 0xD2, 0x42, 0x2B, 0x20, 0x00, 0x50, 0xD2, 0x4C,
0x02, 0x9A, 0x48, 0x40, 0x93, 0x90, 0x86, 0x9C, 0x21, 0x26, 0x1A, 0x72,
0xDB, 0x66, 0x64, 0x49, 0x2B, 0x8C, 0x26, 0x87, 0xEB, 0x49, 0x5B, 0x58,
0x00, 0x6C, 0x82, 0x08, 0x14, 0xD3, 0x4A, 0x41, 0x8E, 0xE5, 0x14, 0xA1,
0x12, 0x59, 0x8E, 0x0A, 0x11, 0x30, 0xA4, 0x8C, 0x84, 0x80, 0x36, 0x08,
0x24, 0x10, 0x44, 0x4E, 0x31, 0x1A, 0x49, 0x6E, 0x29, 0x84, 0xA0, 0xD3,
0x50, 0x06, 0x9D, 0xE8, 0x1A, 0x01, 0x49, 0x27, 0x12, 0x88, 0x72, 0xBD,
0x82, 0x3A, 0xF4, 0x40, 0x30, 0x02, 0x80, 0x6A, 0x0B, 0x48, 0x08, 0x64,
0x31, 0x43, 0x04, 0x98, 0x10, 0xA0, 0x68, 0xC2, 0xAB, 0x4A, 0x52, 0x49,
0x64, 0x4C, 0x86, 0x09, 0xB3, 0x22, 0x41, 0x2C, 0x10, 0x00, 0x0A, 0x80,
0x62, 0x4C, 0x6C, 0x98, 0x15, 0x40, 0x30, 0x12, 0x49, 0x5C, 0x5A, 0xDE,
0xBA, 0x2A, 0x49, 0x8D, 0x95, 0x0C, 0x3A, 0x87, 0xD1, 0x3B, 0x80, 0x31,
0xA9, 0x27, 0xD5, 0xAE, 0x63, 0x32, 0x21, 0xDE, 0xF3, 0xCA, 0xB4, 0x59,
0x9D, 0x53, 0xE5, 0xBA, 0x2F, 0x85, 0xB8, 0x93, 0xD1, 0xED, 0x1E, 0x3E,
0x38, 0x9A, 0x67, 0xF2, 0x22, 0x42, 0x2E, 0x9A, 0x7C, 0xEF, 0x47, 0xC1,
0x97, 0x25, 0xC4, 0x7D, 0xEB, 0x2C, 0xA0, 0x65, 0x05, 0x3D, 0xC2, 0x81,
0x12, 0xBA, 0xE2, 0x44, 0xE2, 0xE2, 0x4C, 0x6F, 0xBC, 0x80, 0x2B, 0xD6,
0xDB, 0x79, 0x42, 0x13, 0x30, 0x15, 0x9E, 0xD7, 0x84, 0xD5, 0xDE, 0x16,
0x9B, 0x17, 0x75, 0x2E, 0xF5, 0xE1, 0x35, 0x77, 0x85, 0xA6, 0xC5, 0xDD,
0x4B, 0xBD, 0x49, 0x68, 0xCA, 0x28, 0x06, 0x6D, 0xDC, 0x6F, 0xC8, 0xA8,
0x94, 0xA5, 0x32, 0x0A, 0x4C, 0xCD, 0x44, 0x04, 0x58, 0x83, 0x02, 0xF5,
0x88, 0xD9, 0xA4, 0x12, 0x60, 0x82, 0xCA, 0x24, 0x6D, 0x29, 0x41, 0x0D,
0x06, 0x08, 0x2D, 0x50, 0x2E, 0x29, 0x48, 0xE5, 0x3B, 0x99, 0xE6, 0x53,
0xB4, 0xB5, 0x45, 0x08, 0x6B, 0xE4, 0xA5, 0x6E, 0x88, 0xE4, 0x66, 0xA5,
0x22, 0x83, 0x68, 0x0A, 0xC4, 0x0B, 0xBB, 0x82, 0xEC, 0xA2, 0xA8, 0xD6,
0xAE, 0x92, 0x12, 0x6A, 0xB9, 0x34, 0x1D, 0x72, 0x22, 0x7B, 0x68, 0x82,
0x02, 0x0D, 0x57, 0xC4, 0x85, 0x01, 0x82, 0x50, 0x68, 0x25, 0x28, 0x2B,
0xCC, 0x68, 0x82, 0x33, 0x00, 0x60, 0xB4, 0x01, 0xAE, 0x50, 0x11, 0x44,
0x1A, 0xB1, 0x88, 0xA1, 0x0C, 0x13, 0x3D, 0x0C, 0x21, 0x43, 0x50, 0x98,
0x36, 0x0D, 0x14, 0x09, 0x28, 0x48, 0x91, 0x60, 0x20, 0xEE, 0x2F, 0x0C,
0x84, 0x05, 0x47, 0xC0, 0x08, 0x15, 0x40, 0x37, 0x68, 0x01, 0x24, 0x11,
0x2A, 0x41, 0x04, 0x0D, 0x33, 0x98, 0x83, 0x33, 0x07, 0x77, 0xC8, 0x2C,
0x20, 0x1B, 0x27, 0xA8, 0x62, 0xA0, 0x93, 0x5F, 0x5F, 0xF6, 0xDA, 0x67,
0xB6, 0xF7, 0x7A, 0xA0, 0xF3, 0xEC, 0x48, 0x7A, 0x50, 0xA0, 0x97, 0x7A,
0xE8, 0x76, 0x54, 0xDC, 0xD2, 0xEF, 0x73, 0xF0, 0xCB, 0x4E, 0x60, 0xC6,
0x34, 0x6F, 0xC5, 0x10, 0x87, 0x4C, 0xA7, 0x93, 0xD8, 0x88, 0x45, 0xAA,
0x8B, 0xDE, 0xF1, 0xEA, 0x18, 0x5B, 0xDE, 0xE9, 0x75, 0x6E, 0x28, 0x8B,
0x15, 0x3D, 0x3E, 0x0F, 0x28, 0x4F, 0x2D, 0x67, 0x9C, 0x68, 0x4C, 0x4C,
0x1C, 0x6A, 0xCF, 0x7F, 0x9F, 0x17, 0x7A, 0xB4, 0xAD, 0x46, 0x51, 0x34,
0x92, 0xEF, 0x9F, 0x17, 0x7A, 0xB4, 0xAD, 0x46, 0x51, 0x34, 0x92, 0xEC,
0xD5, 0x57, 0x28, 0xA0, 0x48, 0x3C, 0x5E, 0x6F, 0xF3, 0x7E, 0x93, 0x50,
0xD2, 0x10, 0x84, 0x10, 0x6A, 0x20, 0x41, 0x84, 0xA6, 0xF8, 0x24, 0xC8,
0x04, 0xD4, 0x80, 0x69, 0x11, 0x12, 0xC6, 0x54, 0x4C, 0x90, 0x87, 0xD1,
0x0D, 0x5C, 0x5C, 0x18, 0x48, 0x1B, 0x3B, 0xE9, 0xBB, 0x54, 0x04, 0x30,
0x2C, 0x25, 0xA7, 0xA8, 0x22, 0x97, 0xCE, 0xC0, 0x0F, 0x90, 0x59, 0x18,
0x66, 0x2A, 0x1A, 0xA4, 0x25, 0x30, 0x2E, 0x00, 0x82, 0x12, 0x30, 0x91,
0x36, 0x64, 0xB4, 0x8D, 0x58, 0x30, 0x0E, 0x00, 0x44, 0x9D, 0x12, 0x6E,
0xD7, 0x24, 0xB6, 0x49, 0x4C, 0x58, 0x20, 0xC5, 0x44, 0x01, 0x42, 0x03,
0x9C, 0x2A, 0xC5, 0x3E, 0x37, 0x1A, 0x80, 0x4A, 0xF1, 0xD9, 0x69, 0x6E,
0xDA, 0x30, 0x99, 0x31, 0x31, 0x13, 0xA0, 0x40, 0x20, 0x13, 0x02, 0x41,
0x68, 0x30, 0x53, 0x29, 0xA8, 0x0C, 0x1D, 0x89, 0x00, 0x21, 0x88, 0x25,
0x98, 0xCA, 0x64, 0x98, 0x04, 0xC1, 0x09, 0xE8, 0x32, 0xFB, 0xDA, 0xA9,
0x88, 0x06, 0x45, 0xC4, 0xC9, 0xD8, 0x00, 0x0D, 0xD9, 0x91, 0x06, 0x2F,
0x24, 0x99, 0xC2, 0x85, 0x37, 0x60, 0xCA, 0xF0, 0xC0, 0xAB, 0x9C, 0x93,
0x5D, 0xFA, 0xBE, 0x2E, 0x4E, 0x05, 0xCF, 0x03, 0x74, 0xA7, 0x8B, 0x03,
0x2B, 0xF9, 0xCC, 0x6B, 0x8B, 0xE3, 0xC1, 0xE6, 0xBE, 0x0B, 0x89, 0xC0,
0x92, 0xC8, 0x51, 0x32, 0x8E, 0x0C, 0x44, 0xF6, 0x2B, 0x42, 0x4D, 0x35,
0xD8, 0xA5, 0x09, 0x64, 0x49, 0x0D, 0x10, 0x51, 0x11, 0xF6, 0x9A, 0x7C,
0xEB, 0x65, 0x2F, 0x89, 0x33, 0x69, 0xAD, 0x2E, 0xF7, 0x88, 0x2C, 0x88,
0x52, 0xEB, 0x4F, 0x88, 0x62, 0x28, 0x88, 0x98, 0xA8, 0x62, 0x89, 0x13,
0x8B, 0x57, 0x38, 0x95, 0x9F, 0x1E, 0xFD, 0x46, 0xB5, 0x2A, 0x55, 0x37,
0xAB, 0x38, 0x92, 0xE5, 0xEF, 0xD4, 0x6B, 0x52, 0xA5, 0x53, 0x7A, 0xB3,
0x89, 0x2E, 0x5B, 0x54, 0x4D, 0x22, 0xE5, 0xBE, 0x2B, 0x72, 0x00, 0x75,
0xA2, 0xDD, 0x21, 0x01, 0xB1, 0x71, 0xD9, 0x50, 0x92, 0xEA, 0x00, 0x00,
0x00, 0x00, 0x82, 0x00, 0x00, 0x08, 0x5D, 0x04, 0x9B, 0x0B, 0x00, 0x00,
0x73, 0x01, 0x01, 0x09, 0x00, 0x00, 0x00, 0x00, 0x08, 0xCF, 0x05, 0x00,
0x00, 0x0E, 0x0F, 0x00, 0x00, 0x87, 0x89, 0xD0, 0x4C, 0x0D, 0x11, 0x07,
0x00, 0xE1, 0xB5, 0x49, 0x02, 0x01, 0x15, 0x56, 0x00, 0x98, 0x9A, 0x82,
0xAA, 0x4E, 0x81, 0x4A, 0x52, 0x4B, 0x49, 0x2D, 0x6A, 0x52, 0x90, 0x84,
0x20, 0x43, 0x21, 0x08, 0x84, 0x21, 0xF2, 0x22, 0x87, 0xD4, 0x20, 0x01,
0x5C, 0xCC, 0x95, 0xF6, 0x4D, 0x7C, 0xC9, 0xB3, 0x25, 0xB5, 0x20, 0x1C,
0xDA, 0x82, 0x66, 0x49, 0xDB, 0x03, 0x60, 0xB8, 0x45, 0x7D, 0x23, 0xDC,
0x02, 0xC3, 0xC1, 0x0E, 0x13, 0x5F, 0x33, 0xC0, 0x02, 0x47, 0xDE, 0x88,
0x6B, 0x79, 0x91, 0xD6, 0x7F, 0x20, 0xFF, 0x52, 0xEE, 0x9B, 0x1C, 0x8B,
0x59, 0xCC, 0xE9, 0xC2, 0x6D, 0xA2, 0xD2, 0xE1, 0x6C, 0x5C, 0x6A, 0x54,
0x63, 0x24, 0xB3, 0x9E, 0x2C, 0x93, 0xD2, 0xE4, 0xF4, 0x40, 0xDF, 0xF2,
0x6C, 0xDD, 0x51, 0xD6, 0xEA, 0x86, 0x8E, 0x22, 0x2E, 0x8F, 0x50, 0x98,
0x58, 0x34, 0x56, 0xD4, 0xF1, 0xEA, 0x82, 0x2C, 0xF5, 0xF7, 0x9D, 0x3B,
0x15, 0x81, 0xF4, 0x6F, 0xBD, 0xE7, 0x1A, 0xBB, 0xA6, 0x72, 0xB8, 0xD6,
0xAE, 0xEE, 0xB5, 0xBE, 0xF7, 0x9C, 0x6A, 0xEE, 0x99, 0xCA, 0xE3, 0x5A,
0xBB, 0xBA, 0xD1, 0x37, 0x84, 0xDB, 0xA6, 0xFA, 0x1F, 0x85, 0xAA, 0x03,
0x0D, 0x0B, 0x6B, 0x48, 0x7E, 0xFD, 0x26, 0x00, 0x98, 0x01, 0x81, 0x70,
0x02, 0x62, 0x5B, 0x27, 0x4D, 0x99, 0x4A, 0x8D, 0x86, 0x4E, 0xA0, 0x43,
0x64, 0xB4, 0x13, 0xA2, 0x4D, 0x25, 0x28, 0x4A, 0x0A, 0x28, 0x40, 0xA0,
0x05, 0x80, 0x0B, 0x19, 0x5B, 0x28, 0x42, 0x56, 0x25, 0xF6, 0x8A, 0x44,
0x22, 0xDF, 0x45, 0x07, 0x23, 0x4E, 0x12, 0x0A, 0x52, 0x4C, 0x69, 0x00,
0x00, 0x4A, 0x5A, 0x49, 0x2C, 0x10, 0x03, 0x49, 0x2D, 0x24, 0x98, 0x00,
0xC4, 0xC2, 0x82, 0x1F, 0x21, 0xA4, 0xA4, 0xD5, 0x7E, 0xFE, 0x9A, 0x4C,
0x01, 0x02, 0x84, 0x00, 0x52, 0x5A, 0xD9, 0x00, 0x08, 0x10, 0x33, 0x41,
0x8D, 0x49, 0x25, 0x7B, 0x35, 0x27, 0x38, 0x73, 0xE8, 0xAE, 0xB8, 0x39,
0x4B, 0x9E, 0x83, 0x31, 0x06, 0x59, 0xF5, 0xC4, 0x4C, 0xB3, 0xB2, 0x6F,
0x0E, 0x3D, 0xA8, 0x71, 0xEC, 0xAA, 0xB9, 0xCF, 0xEC, 0x74, 0xE9, 0x9C,
0xAA, 0x7A, 0x90, 0x07, 0x42, 0x4E, 0xA4, 0xB2, 0xE6, 0x95, 0x25, 0x97,
0x85, 0x1E, 0xD1, 0x82, 0x00, 0x48, 0x04, 0xD4, 0xE4, 0x2F, 0x65, 0xFB,
0xD4, 0x99, 0xC8, 0xF8, 0xEA, 0x9A, 0x9C, 0x61, 0x8D, 0xB9, 0xA2, 0xC2,
0x4A, 0x33, 0xB3, 0xE7, 0xAF, 0x7A, 0xCB, 0xD5, 0xDA, 0xB1, 0x14, 0xBD,
0x6A, 0xEE, 0x5D, 0x7B, 0xD6, 0x5E, 0xAE, 0xD5, 0x88, 0xA5, 0xEB, 0x57,
0x72, 0xDC, 0x47, 0x0F, 0xD3, 0x61, 0x69, 0xF4, 0x95, 0x5D, 0xB5, 0xBD,
0x6A, 0x94, 0x10, 0xA2, 0x50, 0x9E, 0x72, 0x7B, 0x04, 0x02, 0xA0, 0x00,
0x10, 0x0E, 0x88, 0x20, 0xC5, 0xF2, 0x1D, 0x94, 0xAA, 0xC4, 0xC3, 0x45,
0x54, 0x04, 0xD0, 0x98, 0xD1, 0x10, 0x40, 0xA5, 0x09, 0x12, 0x82, 0xD8,
0x31, 0x06, 0x64, 0x04, 0xA0, 0x83, 0x05, 0xA4, 0x30, 0xA1, 0x20, 0xC8,
0xD8, 0x20, 0xA1, 0x28, 0xE4, 0x50, 0x6F, 0x42, 0x40, 0xA5, 0x00, 0xC6,
0x1A, 0x0A, 0x50, 0x4E, 0xE2, 0x94, 0x55, 0x44, 0xB1, 0x26, 0x8A, 0x42,
0x13, 0x09, 0x90, 0x8A, 0x50, 0x62, 0x41, 0x0C, 0x3E, 0xB9, 0x20, 0x28,
0x48, 0x42, 0x17, 0xE8, 0x2E, 0xFA, 0x05, 0x7B, 0xD5, 0xA3, 0xDE, 0x0C,
0xCD, 0x8E, 0x5C, 0x01, 0xA2, 0x2C, 0xEE, 0x0C, 0xEF, 0x99, 0x5F, 0x6D,
0xDB, 0xD1, 0xC9, 0xFC, 0xC1, 0x73, 0x5E, 0xFE, 0xBE, 0x3E, 0xAD, 0x45,
0xC4, 0x18, 0xC4, 0xF0, 0x37, 0x14, 0xA7, 0xA4, 0x86, 0x99, 0xEA, 0x72,
0x69, 0xC6, 0x24, 0x43, 0x2B, 0x2D, 0x84, 0x69, 0x9D, 0xC3, 0xC2, 0x7C,
0x79, 0x18, 0x91, 0x22, 0xF2, 0x03, 0xB0, 0x25, 0x67, 0xC5, 0xBE, 0xEA,
0x4D, 0x2E, 0x62, 0x26, 0x1A, 0xD4, 0xB9, 0x7B, 0xEE, 0xA4, 0xD2, 0xE6,
0x22, 0x61, 0xAD, 0x4B, 0x97, 0x84, 0xAE, 0x0A, 0x4F, 0xCA, 0x54, 0x6D,
0x0B, 0x4F, 0x92, 0x42, 0x86, 0x9A, 0x56, 0x08, 0x0B, 0xCA, 0x48, 0xAE,
0x74, 0x9F, 0xA5, 0x84, 0x25, 0x2C, 0x16, 0x60, 0x09, 0x00, 0x82, 0x83,
0xA1, 0x20, 0x4C, 0x04, 0xD2, 0x42, 0x10, 0x2E, 0x75, 0xCA, 0xE5, 0xEA,
0x10, 0x80, 0x65, 0x7B, 0x0E, 0x18, 0x09, 0x4C, 0xB3, 0x4D, 0x69, 0x6A,
0xA4, 0xCD, 0x95, 0x60, 0x49, 0x08, 0x7D, 0x45, 0x08, 0x44, 0x90, 0x10,
0x97, 0xEF, 0xE9, 0x4C, 0x82, 0x76, 0x4B, 0x00, 0xFF, 0x01, 0x06, 0xF8,
0x28, 0x34, 0x26, 0x20, 0x26, 0x95, 0x8A, 0x1F, 0xA0, 0x89, 0x21, 0x59,
0x54, 0xBA, 0x86, 0xC9, 0x3B, 0x9E, 0x66, 0x31, 0x0B, 0x19, 0xD3, 0x99,
0xE0, 0x62, 0x06, 0x2D, 0xF0, 0x32, 0x15, 0x3D, 0x10, 0x5A, 0xD0, 0x0C,
0x43, 0xBF, 0x1A, 0xCD, 0x29, 0x7A, 0xB7, 0x0B, 0x41, 0xCE, 0xC3, 0x87,
0x2B, 0xBB, 0x33, 0xEC, 0x14, 0x01, 0xB8, 0x85, 0x92, 0x7B, 0x2E, 0x4C,
0x0F, 0x18, 0x8B, 0xD3, 0x6F, 0x44, 0xA2, 0x96, 0xD9, 0x74, 0x21, 0x0D,
0x3E, 0xB0, 0x3C, 0x1A, 0x64, 0x58, 0x45, 0x4C, 0x45, 0x3D, 0x6E, 0xB4,
0xD1, 0x02, 0xC7, 0x11, 0xD8, 0xAB, 0xD6, 0x26, 0xE9, 0x8C, 0xA0, 0x7C,
0x71, 0x7B, 0x8A, 0xC3, 0xB5, 0x9F, 0x16, 0x7A, 0xCD, 0x4E, 0x2E, 0x46,
0x2A, 0x55, 0x4D, 0x5D, 0xC9, 0x79, 0xEB, 0x35, 0x38, 0xB9, 0x18, 0xA9,
0x55, 0x35, 0x77, 0x25, 0x98, 0x5E, 0xE2, 0x0D, 0x6A, 0xC2, 0x3C, 0xDF,
0xE9, 0x01, 0x7D, 0x0F, 0xD6, 0x93, 0x8C, 0x43, 0xB5, 0x49, 0x20, 0x39,
0x24, 0xA2, 0x58, 0x91, 0x75, 0xC6, 0x57, 0x1E, 0xE1, 0x81, 0x34, 0x24,
0x6E, 0x55, 0x22, 0x36, 0x09, 0x45, 0x22, 0x44, 0x89, 0x84, 0x93, 0x41,
0x0D, 0x1B, 0xA8, 0x09, 0x30, 0x43, 0x6A, 0x09, 0x32, 0x90, 0x24, 0x12,
0x4E, 0xAA, 0x8D, 0xA4, 0xB0, 0x25, 0x0D, 0x4C, 0x48, 0x43, 0xF5, 0x80,
0x92, 0xB0, 0x42, 0x50, 0x8A, 0x4B, 0xE3, 0x56, 0x10, 0x08, 0x58, 0xBE,
0x20, 0x90, 0x87, 0xC4, 0x50, 0x92, 0x8E, 0xB6, 0x36, 0x1A, 0x1B, 0xDA,
0xA0, 0x82, 0xCD, 0xD4, 0x31, 0x0A, 0x42, 0x09, 0x60, 0x55, 0x96, 0x8A,
0x38, 0x47, 0x47, 0xCA, 0x90, 0x20, 0x92, 0xBC, 0x18, 0x07, 0x4A, 0xC9,
0x5F, 0xC8, 0x54, 0x6D, 0x45, 0x31, 0xE9, 0x9E, 0x86, 0x95, 0xDE, 0x8D,
0x6E, 0xC6, 0xA5, 0x8C, 0x95, 0x1C, 0x0C, 0x52, 0x49, 0x06, 0x17, 0x8C,
0xC8, 0xFE, 0x31, 0x63, 0x0F, 0xC2, 0x31, 0x48, 0x21, 0xA1, 0x80, 0x90,
0x41, 0x90, 0x40, 0xAA, 0x0B, 0x46, 0xA6, 0x08, 0xC4, 0x1A, 0xF1, 0xB7,
0xE8, 0xCE, 0xD7, 0x04, 0xCF, 0x53, 0x3D, 0x47, 0x46, 0xA9, 0x36, 0x9B,
0x5D, 0x58, 0xC0, 0xD8, 0x93, 0x68, 0x42, 0xD6, 0xF2, 0xDF, 0x5E, 0x54,
0xD4, 0x43, 0x3A, 0x0A, 0x14, 0x0F, 0xF4, 0x9E, 0x06, 0x86, 0xDA, 0x1C,
0x2D, 0x43, 0x1D, 0x61, 0x4D, 0x23, 0x03, 0x11, 0x48, 0x82, 0x4E, 0x05,
0x81, 0x64, 0x5E, 0x75, 0x71, 0x75, 0xF1, 0x22, 0x96, 0xFB, 0x67, 0xBD,
0x9E, 0x2B, 0x8B, 0xD5, 0x35, 0x75, 0x5B, 0xA4, 0x97, 0x72, 0xEF, 0x59,
0xE2, 0xB8, 0xBD, 0x53, 0x57, 0x55, 0xBA, 0x49, 0x77, 0x2E, 0xF4, 0x91,
0x31, 0x3E, 0x02, 0x0E, 0x01, 0x09, 0xBD, 0x4B, 0x7E, 0x51, 0xAB, 0x66,
0xED, 0xC1, 0xC5, 0x9B, 0x2F, 0xD1, 0x36, 0xA9, 0xA4, 0x3F, 0xA8, 0xE1,
0x00, 0xC9, 0xC6, 0x49, 0x9A, 0x02, 0xE0, 0x7B, 0x9A, 0x24, 0xF2, 0x08,
0x80, 0x80, 0xB7, 0x0C, 0x0C, 0xDD, 0x20, 0x92, 0xD8, 0x02, 0x52, 0x82,
0x20, 0x20, 0xBB, 0x24, 0xBE, 0x49, 0xDB, 0x04, 0x8D, 0xC0, 0xAB, 0x08,
0xA5, 0x1C, 0xDF, 0x53, 0x41, 0x30, 0xC0, 0x44, 0x4A, 0x4C, 0xD5, 0x28,
0x42, 0x50, 0x54, 0x6F, 0x54, 0x02, 0xE4, 0x22, 0x65, 0xA5, 0x80, 0x4A,
0x48, 0x20, 0x22, 0x24, 0xBA, 0xE6, 0x9A, 0x52, 0x94, 0xC8, 0x88, 0x65,
0xD3, 0xD4, 0x04, 0xC2, 0xB8, 0xA1, 0x9F, 0x6E, 0x64, 0x89, 0x96, 0x92,
0x59, 0x10, 0x25, 0xA5, 0x51, 0x0D, 0x4D, 0x22, 0x82, 0x9D, 0xB7, 0xB6,
0xBE, 0xBC, 0xC9, 0x9D, 0x41, 0x80, 0xE5, 0xB3, 0x17, 0x8F, 0x83, 0x33,
0x51, 0x36, 0x31, 0x16, 0x28, 0xBF, 0x5A, 0x77, 0x89, 0x57, 0x50, 0xD5,
0xF3, 0x88, 0x72, 0x57, 0x5B, 0x3E, 0x20, 0xAF, 0xB4, 0x42, 0x9B, 0xE4,
0x1C, 0x0F, 0x4A, 0x11, 0x30, 0xFF, 0xE2, 0x2B, 0x20, 0x66, 0xA1, 0x49,
0xAE, 0x32, 0xEB, 0x7A, 0x86, 0x9F, 0x22, 0xF5, 0x7E, 0x7D, 0x8D, 0x88,
0x65, 0x6C, 0x8F, 0x94, 0x7E, 0x09, 0xB1, 0x6E, 0x48, 0x51, 0x44, 0xDF,
0xCD, 0x31, 0x75, 0x14, 0x71, 0x0E, 0x08, 0x42, 0x4E, 0x73, 0xBD, 0x1E,
0xD6, 0xE8, 0x5B, 0xDE, 0x3E, 0xE4, 0x48, 0xDA, 0x5C, 0x89, 0x11, 0x28,
0x1F, 0x1F, 0x46, 0xD3, 0x28, 0xE0, 0xDD, 0x9E, 0xFD, 0x7B, 0xD7, 0x1A,
0x97, 0x57, 0x75, 0x59, 0x25, 0x55, 0xEA, 0xF5, 0x72, 0xBD, 0xEB, 0x8D,
0x4B, 0xAB, 0xBA, 0xAC, 0x92, 0xAA, 0xF5, 0x7A, 0xB9, 0xD9, 0xA9, 0xC5,
0x58, 0xDF, 0xB1, 0xDA, 0x5F, 0xA3, 0xF2, 0xB7, 0xA0, 0x87, 0x46, 0x82,
0x02, 0x80, 0x94, 0x74, 0x0A, 0x2A, 0x76, 0x03, 0x14, 0x7D, 0x44, 0x4A,
0xB1, 0x22, 0x75, 0x24, 0x35, 0x48, 0x97, 0x5D, 0x30, 0x43, 0x3F, 0xD7,
0xA0, 0x21, 0x33, 0xF2, 0x12, 0xEB, 0x0A, 0x37, 0x2C, 0x53, 0x40, 0x41,
0x92, 0x0B, 0x54, 0x97, 0x61, 0x20, 0x9D, 0x65, 0x8E, 0xD1, 0x5E, 0x4A,
0x67, 0x6D, 0x5D, 0x42, 0x53, 0x01, 0x84, 0x15, 0xE8, 0x5F, 0x3C, 0xF5,
0x69, 0x28, 0x24, 0xC9, 0x98, 0x82, 0x24, 0x48, 0x94, 0xCC, 0x83, 0x07,
0xE6, 0x0C, 0x49, 0xF6, 0xD0, 0xCC, 0xD2, 0xA0, 0xDC, 0x6A, 0x31, 0x08,
0x1F, 0x40, 0x23, 0x0C, 0xCC, 0x63, 0x21, 0xB8, 0x43, 0x91, 0x6B, 0x80,
0x5D, 0x8A, 0x25, 0x96, 0xBD, 0xE6, 0x1B, 0xDC, 0x2C, 0xAD, 0x47, 0x30,
0xA9, 0x73, 0x95, 0x9C, 0xF1, 0x9E, 0xEF, 0x1B, 0x6E, 0xA3, 0xBE, 0x74,
0xC1, 0xDA, 0xD0, 0xAE, 0x1C, 0xBE, 0x8C, 0x6B, 0x50, 0x5B, 0xC8, 0x88,
0x63, 0x54, 0xDF, 0x3A, 0xFA, 0x9A, 0xD6, 0x27, 0x82, 0x69, 0x72, 0x2B,
0x1E, 0x1E, 0x6B, 0x71, 0x16, 0x9E, 0x96, 0x94, 0x4C, 0xC4, 0x6A, 0x32,
0xEF, 0x17, 0x04, 0xDF, 0x3A, 0x88, 0x25, 0xBE, 0x2C, 0xA8, 0x1D, 0x5D,
0x47, 0xEF, 0x8A, 0x6F, 0xC4, 0xD3, 0x4C, 0x4A, 0x02, 0x8E, 0xBD, 0x2D,
0x3E, 0xE9, 0xA6, 0x8A, 0x18, 0xAC, 0xF7, 0x3B, 0xDC, 0xD6, 0xB5, 0x95,
0xC4, 0xA6, 0x4A, 0x2F, 0x53, 0x57, 0x7D, 0xEE, 0x6B, 0x5A, 0xCA, 0xE2,
0x53, 0x25, 0x17, 0xA9, 0xAB, 0xB2, 0x93, 0x00, 0xF1, 0xD3, 0x94, 0x25,
0x09, 0x45, 0x4A, 0x16, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, 0x08,
0x5D, 0x04, 0x0F, 0x0D, 0x00, 0x00, 0x73, 0x01, 0x01, 0x0A, 0x00, 0x00,
0x00, 0x00, 0x08, 0xCF, 0x05, 0x00, 0x00, 0x53, 0x10, 0x00, 0x00, 0x96,
0xB1, 0x93, 0xB3, 0x45, 0x28, 0x48, 0x02, 0x5D, 0x48, 0x92, 0x0A, 0xC0,
0x83, 0xF4, 0x4B, 0xB7, 0x03, 0xDF, 0x8E, 0xA4, 0xE6, 0x42, 0x93, 0xCC,
0xD2, 0x46, 0x24, 0x1D, 0x04, 0x20, 0xC1, 0xE6, 0xD7, 0xC9, 0x96, 0xDF,
0x02, 0x4A, 0x52, 0x95, 0xB4, 0x4A, 0x40, 0x73, 0x7D, 0xCD, 0x72, 0x09,
0xC1, 0x94, 0xBF, 0x58, 0x70, 0x21, 0x1C, 0x54, 0x98, 0x5E, 0x54, 0x82,
0x33, 0x49, 0x36, 0x8C, 0x81, 0x43, 0xF8, 0x98, 0x69, 0xB8, 0x41, 0x40,
0xCD, 0x26, 0x38, 0x05, 0x42, 0x5D, 0xE0, 0x17, 0x28, 0x24, 0x88, 0x9E,
0x62, 0xA4, 0xC4, 0x39, 0xC8, 0x9B, 0x2A, 0xB2, 0x63, 0xA1, 0x71, 0x41,
0x31, 0xC2, 0x94, 0x75, 0xDB, 0x08, 0xAF, 0x64, 0xFD, 0x3C, 0x15, 0xFC,
0x95, 0x79, 0xD2, 0x17, 0x8D, 0xBF, 0x03, 0xFE, 0x20, 0x47, 0x7F, 0x79,
0x48, 0x6E, 0x01, 0x9C, 0x45, 0x7B, 0x90, 0x73, 0x8B, 0x3D, 0x7C, 0x18,
0x9C, 0x6C, 0x73, 0x4B, 0xB1, 0xC5, 0x2F, 0xCA, 0xDF, 0x4A, 0x4D, 0xE4,
0xE0, 0xFC, 0x39, 0x73, 0x4B, 0x92, 0x0D, 0x70, 0x6D, 0x31, 0x7C, 0xF2,
0x9E, 0x1A, 0x70, 0xC2, 0xC7, 0x84, 0x51, 0x01, 0x0F, 0x8E, 0x7A, 0x0F,
0x56, 0x94, 0xF5, 0xBC, 0x0E, 0x01, 0x85, 0xA1, 0x67, 0x1A, 0x76, 0x07,
0xBB, 0xE3, 0x9B, 0xBB, 0xBD, 0x55, 0xDB, 0x39, 0xD4, 0xA5, 0xDD, 0xEA,
0xE7, 0x8E, 0x6E, 0xEE, 0xF5, 0x57, 0x6C, 0xE7, 0x52, 0x97, 0x77, 0xAB,
0x84, 0x92, 0x4F, 0x85, 0xE7, 0xB5, 0xB9, 0x69, 0x02, 0x42, 0x2D, 0xF6,
0xF7, 0xEB, 0x6F, 0xCB, 0xB0, 0x92, 0x8A, 0x16, 0x90, 0x0D, 0x40, 0x9A,
0x5F, 0xA5, 0xF9, 0x12, 0x60, 0x20, 0x13, 0x00, 0x51, 0x42, 0x42, 0x40,
0x69, 0x20, 0x5E, 0x93, 0x6F, 0x11, 0x00, 0xC9, 0xD0, 0xC2, 0x10, 0x5A,
0xC3, 0x90, 0x48, 0x32, 0x8B, 0x06, 0x24, 0x68, 0xCD, 0xB3, 0xE9, 0x02,
0x22, 0x1B, 0xE2, 0xD5, 0xB0, 0xF9, 0x22, 0x68, 0xA5, 0xD4, 0xC8, 0x26,
0x1A, 0x41, 0x06, 0xC9, 0xBB, 0x47, 0xB4, 0x04, 0xB4, 0x13, 0x09, 0x41,
0xDA, 0x53, 0x24, 0x69, 0x50, 0x93, 0x55, 0x20, 0x90, 0x48, 0x54, 0x42,
0x84, 0xCC, 0x2A, 0x17, 0xC5, 0xE2, 0x40, 0x4A, 0x2A, 0x22, 0xAA, 0x01,
0x0B, 0xC2, 0x40, 0x68, 0x5C, 0xA6, 0x10, 0xCF, 0x2B, 0x23, 0x16, 0x6B,
0x50, 0x80, 0x91, 0x66, 0xE4, 0xAC, 0x50, 0x48, 0xC5, 0xBB, 0x37, 0x1C,
0x34, 0xB6, 0x66, 0x17, 0x90, 0x0C, 0x6D, 0x64, 0xBB, 0x77, 0x49, 0xB9,
0x8D, 0x04, 0xCC, 0x70, 0xAE, 0xC6, 0x1C, 0xC2, 0x9D, 0xEA, 0xBF, 0xDB,
0x44, 0xD6, 0x0B, 0xF1, 0x57, 0x1B, 0x13, 0xC6, 0x29, 0x08, 0x40, 0x6D,
0xC5, 0x88, 0xD5, 0x0C, 0x4D, 0x34, 0xCD, 0xD0, 0xD8, 0xC9, 0x8C, 0xBB,
0x15, 0x8C, 0xA0, 0x53, 0xE7, 0x4C, 0xFE, 0x0D, 0x75, 0x31, 0xA4, 0x99,
0xF6, 0x2E, 0x8E, 0x07, 0xFB, 0x69, 0x90, 0xD3, 0xE3, 0xAF, 0x9C, 0x65,
0x0C, 0x2A, 0x9A, 0x71, 0x06, 0x36, 0x50, 0x9D, 0x4F, 0x9D, 0x89, 0xA6,
0xBA, 0x32, 0x8D, 0x2C, 0x34, 0x31, 0xF1, 0xF1, 0xA3, 0xEC, 0x4D, 0x0C,
0x24, 0xEF, 0x1E, 0x11, 0x40, 0x76, 0x8A, 0x8A, 0x22, 0xCF, 0x02, 0xC8,
0xA0, 0xF5, 0xE9, 0x36, 0xBA, 0x8A, 0x52, 0x29, 0x53, 0xD3, 0x79, 0xAD,
0x35, 0xCC, 0x59, 0xF0, 0xF3, 0xDE, 0x4D, 0x5C, 0x5C, 0x92, 0x96, 0x5E,
0xAE, 0x66, 0xB9, 0xEF, 0x26, 0xAE, 0x2E, 0x49, 0x4B, 0x2F, 0x57, 0x33,
0x42, 0x2A, 0x90, 0x29, 0xB7, 0x2D, 0xE0, 0x34, 0xAB, 0x45, 0xBF, 0x88,
0x60, 0x3E, 0x34, 0xEF, 0x23, 0xD0, 0xB4, 0x80, 0xC3, 0x59, 0x84, 0x00,
0x41, 0x42, 0x41, 0x28, 0x44, 0xC1, 0x20, 0x1A, 0x88, 0x45, 0x5A, 0x40,
0x08, 0x06, 0x94, 0xA5, 0x24, 0x65, 0xCC, 0xA7, 0x64, 0xA4, 0x92, 0x5A,
0x00, 0x00, 0x09, 0x2C, 0x01, 0xA6, 0x00, 0x82, 0xD8, 0xD6, 0xE0, 0x37,
0x08, 0xC2, 0x57, 0xE8, 0x9A, 0x10, 0x49, 0x92, 0x99, 0x80, 0x2F, 0x92,
0xA9, 0x24, 0xC0, 0x4A, 0x69, 0xC2, 0x45, 0x08, 0x10, 0x14, 0xD8, 0x80,
0x20, 0x2E, 0x12, 0x90, 0x20, 0x09, 0x25, 0xB3, 0x86, 0x52, 0x84, 0x28,
0x03, 0x57, 0x03, 0x61, 0x90, 0x20, 0x0D, 0xCE, 0xE7, 0x74, 0x18, 0xE7,
0xA3, 0xD0, 0x50, 0x63, 0x72, 0xC4, 0x06, 0xB7, 0x91, 0x52, 0x91, 0x30,
0x2D, 0x47, 0x29, 0x53, 0x86, 0x44, 0x8F, 0x1F, 0x1A, 0x9E, 0x3D, 0x90,
0x60, 0xB7, 0x6D, 0x70, 0x2B, 0xEA, 0xFC, 0xEB, 0x5A, 0x99, 0xB8, 0x19,
0x2C, 0x08, 0x0A, 0xEA, 0x00, 0x60, 0xD0, 0x0B, 0x23, 0xDE, 0x51, 0x24,
0xA1, 0x39, 0x3D, 0x54, 0x30, 0xA6, 0x1B, 0xCD, 0x3D, 0x2E, 0xC5, 0x8C,
0xB2, 0x48, 0xA7, 0x11, 0xA8, 0xB0, 0x90, 0xDC, 0x03, 0x7D, 0x88, 0xC1,
0xF3, 0xAB, 0xB1, 0x18, 0xB3, 0x03, 0xF9, 0x31, 0x6E, 0x6A, 0x04, 0x5D,
0x64, 0xDE, 0x37, 0xF2, 0xC8, 0x44, 0xA4, 0x28, 0xAB, 0x03, 0x76, 0x7C,
0x9C, 0xF3, 0xB6, 0xAE, 0xEA, 0xE3, 0x2A, 0x93, 0x8D, 0x71, 0xAA, 0xCD,
0x73, 0xCE, 0xDA, 0xBB, 0xAB, 0x8C, 0xAA, 0x4E, 0x35, 0xC6, 0xAB, 0x34,
0x99, 0x06, 0x02, 0x05, 0xBD, 0xF1, 0x60, 0x40, 0x5B, 0xA7, 0x89, 0x6E,
0x82, 0xCA, 0xA9, 0xA0, 0x71, 0xA6, 0x97, 0xF4, 0xC6, 0x11, 0x05, 0x80,
0xC1, 0x06, 0xE1, 0x07, 0x45, 0xDB, 0x10, 0x60, 0xC8, 0x90, 0x41, 0x98,
0x04, 0x10, 0xA4, 0x69, 0x23, 0x60, 0x8A, 0xA0, 0xC1, 0x0C, 0x4C, 0x15,
0x02, 0x48, 0x9A, 0x86, 0x09, 0x01, 0x24, 0x01, 0x55, 0x30, 0x52, 0x9A,
0x8F, 0x81, 0x80, 0x09, 0x20, 0x00, 0xD2, 0x99, 0x4A, 0x60, 0x4A, 0x70,
0xE0, 0x21, 0x12, 0x87, 0xCF, 0xD6, 0xD0, 0x87, 0x61, 0x06, 0x97, 0x60,
0xAD, 0xF1, 0xBF, 0x49, 0x29, 0x14, 0x50, 0x81, 0x00, 0x40, 0xBD, 0x29,
0x22, 0x49, 0x82, 0x92, 0x20, 0x54, 0x40, 0x64, 0xD5, 0xA8, 0x12, 0x9A,
0x93, 0x29, 0x81, 0xF1, 0x59, 0x96, 0x48, 0xD1, 0x1E, 0x1A, 0x42, 0xA2,
0xEC, 0x0C, 0xE2, 0xB4, 0x3E, 0x02, 0x01, 0x2B, 0x0D, 0x64, 0xB3, 0x3A,
0xEF, 0x1B, 0x8A, 0x03, 0xB2, 0x4D, 0x74, 0xA5, 0xAE, 0x9B, 0x78, 0x90,
0xDA, 0xAA, 0x2A, 0x14, 0x95, 0x33, 0x27, 0x4F, 0x03, 0x62, 0x67, 0xC1,
0x98, 0x80, 0xD9, 0xF1, 0x77, 0x4D, 0xCD, 0x5E, 0xA2, 0xB7, 0xB5, 0x4E,
0x38, 0xE3, 0x8D, 0xD6, 0xBB, 0xA6, 0xE6, 0xAF, 0x51, 0x5B, 0xDA, 0xA7,
0x1C, 0x71, 0xC6, 0xEB, 0x5B, 0x29, 0x2F, 0xA9, 0x41, 0x00, 0x94, 0x25,
0x09, 0x0D, 0x25, 0x35, 0x12, 0x68, 0x85, 0x8A, 0xD3, 0xE2, 0x9A, 0x29,
0x08, 0x04, 0x44, 0xDE, 0x2E, 0x66, 0xC1, 0x46, 0xE7, 0xA5, 0x3B, 0xEB,
0x50, 0x63, 0xBF, 0xF8, 0x66, 0x10, 0x0A, 0xB6, 0x4E, 0x1D, 0x51, 0x86,
0x20, 0xD3, 0x50, 0x50, 0xEC, 0xA1, 0x01, 0x34, 0x3F, 0x58, 0x53, 0x20,
0xA1, 0x30, 0x5A, 0x01, 0x10, 0x2A, 0xA2, 0x6A, 0xA5, 0x09, 0x24, 0xB5,
0xFD, 0x09, 0x41, 0x48, 0xA1, 0x89, 0xE2, 0x45, 0x34, 0xA1, 0x3C, 0x48,
0x5B, 0x4A, 0x30, 0x96, 0xC0, 0x9A, 0xA8, 0x12, 0x2A, 0x04, 0xA2, 0x30,
0xD1, 0x32, 0x45, 0x50, 0x41, 0xAA, 0x24, 0x1A, 0xC9, 0x23, 0x0B, 0x50,
0x2A, 0xC4, 0x4B, 0x1B, 0x0A, 0x8F, 0x01, 0x00, 0xA2, 0x8F, 0x54, 0xD8,
0x2E, 0xA2, 0x46, 0xEA, 0x4B, 0x3C, 0x67, 0x0A, 0xA2, 0x55, 0x6A, 0xA0,
0x1E, 0x88, 0x27, 0x71, 0x7B, 0xC0, 0xD8, 0xF4, 0x70, 0x0A, 0x20, 0xC0,
0xEE, 0xF5, 0x39, 0xD5, 0x65, 0xEA, 0xD7, 0x4E, 0x69, 0x57, 0xC7, 0x1D,
0x5E, 0xE4, 0xE7, 0x55, 0x97, 0xAB, 0x5D, 0x39, 0xA5, 0x5F, 0x1C, 0x75,
0x7B, 0x90, 0x61, 0xBE, 0x5B, 0x42, 0x4C, 0x21, 0x2D, 0x58, 0x52, 0x82,
0x83, 0x52, 0x9A, 0x29, 0xA1, 0xFB, 0xE4, 0xA2, 0x95, 0xAA, 0x4B, 0xE7,
0xE0, 0x10, 0x12, 0x08, 0x4A, 0x08, 0x23, 0x60, 0xA0, 0x8E, 0xAA, 0x49,
0xD2, 0x50, 0x01, 0x41, 0x1A, 0x90, 0x6A, 0x80, 0xD6, 0x41, 0x06, 0x22,
0x08, 0x83, 0x1A, 0x3A, 0xC3, 0x42, 0x50, 0x9A, 0x29, 0xA1, 0x34, 0x52,
0x8A, 0x50, 0x51, 0x3B, 0x0D, 0xA1, 0x6E, 0x82, 0x94, 0x4D, 0x44, 0xA0,
0x82, 0x82, 0xAA, 0x08, 0x82, 0x14, 0x28, 0x28, 0x4A, 0x12, 0x1B, 0x52,
0x9A, 0x13, 0x43, 0xF5, 0xA7, 0xEF, 0x9F, 0xBE, 0x7F, 0x41, 0x14, 0xD0,
0xB1, 0xA1, 0x62, 0x84, 0x2D, 0xD0, 0x4D, 0x44, 0x80, 0x76, 0x83, 0x28,
0x21, 0xA0, 0x25, 0x04, 0x25, 0x09, 0x04, 0x18, 0x48, 0x28, 0xA6, 0x8A,
0x68, 0xA6, 0x87, 0xF4, 0x25, 0x09, 0x42, 0x50, 0x64, 0x1A, 0x89, 0x84,
0xC1, 0x1A, 0x2A, 0x1D, 0x83, 0xF1, 0xDD, 0x18, 0xB1, 0x1F, 0x1B, 0xC0,
0x40, 0x25, 0x1F, 0xC0, 0x40, 0x23, 0xB4, 0x48, 0x32, 0x2A, 0xA0, 0xEC,
0x19, 0x0C, 0x21, 0xA0, 0xAC, 0x86, 0xE7, 0x2D, 0xBB, 0x88, 0xEC, 0x11,
0x65, 0xE3, 0x13, 0x2C, 0x41, 0x31, 0xB5, 0xE8, 0xC7, 0x91, 0xEA, 0x87,
0x8E, 0xFF, 0x16, 0xF3, 0xA4, 0x38, 0xD5, 0x8A, 0x79, 0xD2, 0x1C, 0x6A,
0xC5, 0x65, 0x2D, 0x3B, 0x6C, 0xC1, 0x28, 0x42, 0xD4, 0x81, 0x08, 0x99,
0x91, 0x32, 0x02, 0x08, 0x89, 0x9A, 0xA2, 0x10, 0x28, 0x68, 0x20, 0xD4,
0x8D, 0x15, 0x62, 0x14, 0x91, 0xEC, 0xA3, 0x26, 0x4C, 0x62, 0x55, 0xC5,
0x3C, 0x68, 0xD2, 0xE2, 0x6D, 0x11, 0xDA, 0x86, 0x22, 0x8E, 0xB1, 0xA1,
0xB6, 0xB3, 0x8C, 0x90, 0xC4, 0x25, 0x8B, 0xFC, 0x17, 0x1B, 0x62, 0xA2,
0x2A, 0x54, 0x26, 0x12, 0x87, 0xD5, 0x48, 0x9A, 0x89, 0x48, 0xAA, 0x94,
0xA4, 0x44, 0xDA, 0xDC, 0x4A, 0xF5, 0x62, 0xE1, 0x0F, 0x4C, 0x48, 0x6C,
0x42, 0x7A, 0x71, 0x7A, 0xE2, 0xBE, 0x05, 0xAD, 0x37, 0xC7, 0x7F, 0x88,
0x2D, 0x18, 0x44, 0x2D, 0x61, 0x08, 0x14, 0x22, 0x94, 0x94, 0x16, 0xA5,
0x60, 0x1F, 0x04, 0x84, 0xC1, 0x3C, 0xE2, 0xF5, 0x5A, 0x40, 0x53, 0x2D,
0x42, 0x00, 0x00, 0x6C, 0xBD, 0x1F, 0x88, 0x4A, 0x81, 0xC7, 0x15, 0x8B,
0xA9, 0xD5, 0x7F, 0x91, 0x7C, 0x4A, 0x3D, 0xB2, 0x5B, 0xE2, 0x51, 0xED,
0x92, 0xD6, 0x9F, 0x20, 0x42, 0xC1, 0x26, 0x64, 0xD3, 0x20, 0xC4, 0x10,
0x04, 0x25, 0xFA, 0x53, 0x29, 0x3D, 0x92, 0x4D, 0x80, 0xD8, 0xB5, 0x59,
0xC1, 0x67, 0x5C, 0x34, 0x1A, 0xF1, 0x7E, 0x8C, 0xBB, 0x5C, 0xE5, 0xDE,
0x65, 0xD6, 0xAB, 0x35, 0xA9, 0x91, 0xD6, 0xAB, 0x35, 0xA9, 0x91, 0xF9,
0x21, 0xAB, 0x10, 0x66, 0x44, 0x98, 0x82, 0x40, 0x94, 0x90, 0xEA, 0x69,
0x2D, 0x54, 0xB6, 0xF0, 0x1B, 0x67, 0x0C, 0xB0, 0xC6, 0xCB, 0x93, 0xC5,
0xE3, 0x8F, 0x3D, 0xEA, 0xC5, 0x9E, 0x86, 0xB8, 0x92, 0xF7, 0x96, 0x92,
0x8A, 0xE2, 0x4B, 0xDE, 0x5A, 0x4A, 0x1F, 0x8D, 0xCB, 0xA2, 0x00, 0x00,
0x00, 0x00, 0x82, 0x00, 0x00, 0x08, 0x5D, 0x04, 0x82, 0x0E, 0x00, 0x00,
0x73, 0x01, 0x01, 0x0B, 0x00, 0x00, 0x00, 0x00, 0x08, 0xCF, 0x05, 0x00,
0x00, 0x7B, 0x11, 0x00, 0x00, 0xA6, 0x3C, 0xA1, 0x81, 0x81, 0x9B, 0xD1,
0x4B, 0x0C, 0x97, 0xE7, 0x52, 0x26, 0x56, 0x8C, 0x69, 0x32, 0x42, 0x09,
0xA7, 0x70, 0x36, 0x24, 0x89, 0x08, 0x14, 0x22, 0x49, 0x48, 0xDB, 0x49,
0x29, 0x29, 0x15, 0x00, 0x00, 0x6A, 0x7E, 0x90, 0x00, 0x46, 0x85, 0x64,
0x34, 0x03, 0xA2, 0x24, 0xA4, 0xAB, 0x00, 0x54, 0x12, 0xA2, 0x00, 0x2F,
0x1D, 0x42, 0x6B, 0x81, 0x89, 0xC5, 0x24, 0x8B, 0x83, 0xD6, 0xDF, 0x1A,
0x86, 0x62, 0xD9, 0x54, 0x05, 0x35, 0xBE, 0x35, 0x0C, 0xC5, 0xB2, 0xA8,
0x0A, 0x68, 0x52, 0x44, 0xEE, 0x4B, 0x04, 0x9E, 0xA2, 0x0B, 0x1A, 0x98,
0x0D, 0x60, 0x03, 0x4D, 0xD3, 0x50, 0x4A, 0x1B, 0x51, 0x00, 0x08, 0x20,
0xA2, 0xA9, 0xA9, 0x24, 0x92, 0x5A, 0xDB, 0x9A, 0x52, 0xD2, 0x64, 0xCB,
0x7B, 0x04, 0x12, 0xA0, 0x04, 0x42, 0x24, 0x08, 0x29, 0x20, 0x20, 0x41,
0x2C, 0x88, 0xD2, 0x40, 0x4B, 0xB3, 0x4C, 0xCC, 0xC9, 0x82, 0x44, 0x81,
0x32, 0x49, 0x84, 0x32, 0x67, 0x73, 0x06, 0x1A, 0x8A, 0xB5, 0x20, 0xD0,
0x81, 0x49, 0x7D, 0x42, 0x05, 0x32, 0xFA, 0x81, 0x86, 0x9A, 0x52, 0x4D,
0x51, 0x85, 0x55, 0xAD, 0x01, 0x22, 0x41, 0x92, 0x48, 0x02, 0xA4, 0x80,
0x1B, 0x02, 0x94, 0x02, 0x02, 0x20, 0xD4, 0x87, 0xEE, 0xA0, 0xD0, 0x4B,
0x08, 0x4E, 0x12, 0x12, 0x4A, 0x00, 0x4D, 0x22, 0x85, 0xB4, 0x1A, 0x50,
0xF8, 0x9C, 0x3A, 0x52, 0xB6, 0x95, 0xA5, 0xA4, 0x21, 0x06, 0x50, 0x5B,
0x55, 0x29, 0x41, 0x34, 0x94, 0xE8, 0x22, 0x95, 0x81, 0x84, 0x30, 0x3E,
0x08, 0x09, 0x28, 0x05, 0x02, 0x68, 0x40, 0x45, 0x65, 0x2F, 0xD2, 0x98,
0xDD, 0x40, 0x52, 0x42, 0x4C, 0x21, 0x20, 0xD2, 0x26, 0x94, 0x94, 0xD0,
0x82, 0x82, 0xB1, 0xA4, 0xAC, 0x10, 0x68, 0x58, 0xA6, 0xAA, 0x40, 0x4A,
0x69, 0x22, 0x01, 0x42, 0x18, 0x09, 0x24, 0xE1, 0xD2, 0xFD, 0x24, 0x80,
0x60, 0x8A, 0xB4, 0x8A, 0xB2, 0x50, 0x26, 0x1D, 0x60, 0x46, 0x12, 0x00,
0x49, 0x29, 0x26, 0x03, 0x48, 0x42, 0x0C, 0x61, 0x50, 0x84, 0x6C, 0x54,
0x7C, 0x92, 0x8A, 0xA9, 0x40, 0xA8, 0x10, 0x8C, 0x34, 0xA0, 0x81, 0x2C,
0x26, 0x51, 0x40, 0x20, 0x14, 0x0A, 0x94, 0x50, 0x29, 0x58, 0x51, 0x23,
0x09, 0xFA, 0x64, 0x0A, 0x28, 0x14, 0x25, 0x08, 0x42, 0xD4, 0x05, 0xBA,
0x49, 0xA8, 0x1F, 0xA4, 0x04, 0x09, 0xA9, 0x08, 0xE2, 0xA0, 0x55, 0xA0,
0x00, 0xFC, 0x96, 0x49, 0x4C, 0xA5, 0x22, 0x85, 0xAA, 0x2F, 0x2E, 0xA5,
0x8A, 0x69, 0x7E, 0xFD, 0x6C, 0xA4, 0xB6, 0xAD, 0x35, 0x5F, 0x9A, 0xA1,
0x14, 0x20, 0x80, 0xF9, 0x15, 0x10, 0x00, 0x41, 0x42, 0x10, 0x1A, 0x2A,
0x95, 0x80, 0x21, 0x08, 0xBC, 0x52, 0x09, 0x82, 0x41, 0x84, 0x96, 0xC2,
0x00, 0x00, 0x03, 0x10, 0x18, 0x80, 0x87, 0x8C, 0x36, 0xF7, 0x66, 0x63,
0xFA, 0x38, 0xF1, 0x97, 0x85, 0xB8, 0x6E, 0xA6, 0x9D, 0x33, 0x55, 0x0A,
0x27, 0x0C, 0x4C, 0x42, 0x49, 0x56, 0x9B, 0xE7, 0x52, 0x48, 0x4B, 0x0D,
0x61, 0xC1, 0x18, 0x41, 0x16, 0xDB, 0x6D, 0xDB, 0xEB, 0x6F, 0xAB, 0xBC,
0x8F, 0x13, 0x59, 0x95, 0x29, 0x72, 0x99, 0x35, 0xBE, 0xAE, 0xF2, 0x3C,
0x4D, 0x66, 0x54, 0xA5, 0xCA, 0x64, 0xD0, 0xA2, 0x94, 0x9E, 0x52, 0x06,
0xA4, 0x45, 0x84, 0x80, 0xB9, 0x48, 0x2D, 0x18, 0x30, 0x85, 0xA0, 0x94,
0x92, 0x7B, 0x94, 0x25, 0x02, 0x93, 0xEE, 0x84, 0x12, 0x57, 0x2B, 0x0C,
0x03, 0x11, 0x18, 0x49, 0xE3, 0x7E, 0x49, 0x69, 0x83, 0x20, 0x91, 0x42,
0xC6, 0x9A, 0x4A, 0x49, 0x48, 0xA4, 0x43, 0xAC, 0x07, 0xE4, 0x51, 0x42,
0x10, 0x01, 0x22, 0x45, 0x40, 0x48, 0xAA, 0x92, 0x9A, 0xAC, 0x89, 0x31,
0x50, 0x21, 0x04, 0x52, 0x12, 0x06, 0x1B, 0xEA, 0x42, 0x38, 0xD6, 0xF8,
0x9F, 0x26, 0x97, 0xE6, 0x95, 0xF4, 0x28, 0x94, 0x34, 0xC8, 0x22, 0x32,
0xE8, 0x29, 0x49, 0x00, 0x05, 0x48, 0x32, 0x17, 0x14, 0x24, 0x10, 0x54,
0x48, 0x21, 0xA1, 0xA8, 0x4B, 0x08, 0x91, 0x2D, 0x42, 0x50, 0x50, 0x9A,
0x89, 0x01, 0x22, 0x41, 0x48, 0x4E, 0x88, 0x09, 0x41, 0x04, 0x42, 0xE2,
0x01, 0x28, 0x48, 0x94, 0x24, 0x8C, 0x38, 0x09, 0x10, 0x90, 0x6A, 0xD0,
0x90, 0x58, 0x70, 0x8A, 0x46, 0x13, 0xFA, 0x12, 0x34, 0x94, 0x55, 0xA2,
0x94, 0x24, 0x7A, 0xE8, 0x20, 0x94, 0x14, 0x52, 0x86, 0xA0, 0x90, 0xC2,
0xA9, 0x42, 0x50, 0x94, 0x14, 0x24, 0x52, 0x18, 0x70, 0xA9, 0x42, 0x50,
0x74, 0x94, 0x06, 0x82, 0x84, 0xE1, 0x94, 0x36, 0x0D, 0x09, 0x06, 0x09,
0x05, 0x08, 0x48, 0xA8, 0x95, 0x9C, 0x92, 0xC0, 0x98, 0x09, 0x41, 0x01,
0x28, 0x82, 0x90, 0xC2, 0x0A, 0x25, 0x7D, 0x44, 0xA1, 0x84, 0x94, 0x24,
0x19, 0x7C, 0xFE, 0x89, 0x21, 0x20, 0x82, 0x81, 0x4B, 0xEA, 0x50, 0x60,
0x80, 0x43, 0x51, 0x4B, 0xEA, 0x68, 0x4D, 0x47, 0xF4, 0x52, 0x84, 0xBE,
0x5B, 0x7C, 0x95, 0x83, 0xF7, 0xD4, 0x89, 0x84, 0xD0, 0xB6, 0xB5, 0x4C,
0x14, 0x12, 0x83, 0x04, 0x26, 0x30, 0x92, 0x14, 0xC3, 0x45, 0x34, 0x3F,
0xA0, 0x89, 0x84, 0xA2, 0x9A, 0x24, 0x84, 0xD1, 0x4A, 0x0B, 0x44, 0xA0,
0xC5, 0x54, 0x26, 0x0A, 0x12, 0x82, 0x50, 0x50, 0x91, 0x3D, 0x25, 0x04,
0xA2, 0x91, 0xB0, 0x51, 0x4A, 0x09, 0x04, 0x6C, 0x6E, 0x08, 0x4A, 0x1A,
0x87, 0x8C, 0x09, 0x21, 0x52, 0x69, 0x71, 0x75, 0xB7, 0xBD, 0x36, 0xB8,
0x8E, 0x5E, 0x58, 0x16, 0xF1, 0x4A, 0x5E, 0xAE, 0x71, 0x25, 0x8A, 0xD7,
0x0A, 0x7B, 0x84, 0x86, 0x53, 0xC6, 0x84, 0xDA, 0x65, 0x09, 0x11, 0x9E,
0x36, 0x14, 0x6F, 0x2C, 0x9F, 0xDA, 0xE2, 0x4B, 0x89, 0xF6, 0x2F, 0x5C,
0x52, 0x9E, 0x74, 0x96, 0xD6, 0x94, 0x48, 0xB3, 0xDE, 0xE1, 0x53, 0x64,
0xBC, 0xB6, 0xFE, 0x4D, 0xE1, 0x24, 0x92, 0x49, 0x5D, 0xEA, 0x6B, 0xA9,
0x79, 0x33, 0x76, 0xA7, 0x32, 0xA4, 0xE3, 0x59, 0x2E, 0xEB, 0xA9, 0x79,
0x33, 0x76, 0xA7, 0x32, 0xA4, 0xE3, 0x59, 0x2E, 0xD2, 0x8E, 0xC3, 0x7A,
0x0B, 0xAA, 0x74, 0x68, 0x4D, 0x17, 0x61, 0x25, 0x72, 0xC3, 0xB6, 0x89,
0x90, 0xB1, 0x0F, 0xE9, 0x6B, 0xAE, 0x80, 0xFC, 0xAE, 0xA1, 0x79, 0x48,
0x27, 0xFC, 0xB6, 0x94, 0x41, 0x4A, 0x41, 0xA9, 0x71, 0x04, 0x0D, 0x18,
0x14, 0x97, 0x1C, 0x69, 0x42, 0xD2, 0xDC, 0x45, 0xB3, 0x93, 0x81, 0xD1,
0x26, 0xED, 0x05, 0x12, 0x89, 0x04, 0x10, 0x42, 0x62, 0x41, 0xD1, 0x2D,
0x68, 0x6E, 0x9B, 0x30, 0xDC, 0x22, 0xD6, 0x34, 0x73, 0x1C, 0xDA, 0xBF,
0x96, 0x63, 0x9B, 0xD2, 0x3A, 0x9A, 0x63, 0xAB, 0x25, 0xB8, 0x8B, 0x3A,
0xC7, 0x14, 0xFE, 0xAA, 0xDF, 0x34, 0xFA, 0x8D, 0xA4, 0x3A, 0xCA, 0x52,
0x12, 0x4D, 0x05, 0xBA, 0x7C, 0xE3, 0x51, 0x5B, 0xD2, 0xEF, 0x14, 0x01,
0x22, 0xA0, 0x37, 0xC8, 0xA6, 0xFA, 0x38, 0x4E, 0xFF, 0x50, 0x12, 0xFD,
0xFB, 0xFA, 0x69, 0x29, 0x2D, 0x66, 0x8C, 0x00, 0x8D, 0x04, 0x92, 0x48,
0x00, 0xA4, 0x44, 0x27, 0x65, 0xD6, 0x34, 0x8C, 0xB2, 0xB8, 0x07, 0xDC,
0xEF, 0xA0, 0x94, 0xA4, 0xB4, 0x93, 0x50, 0x03, 0x30, 0x3A, 0x0D, 0x24,
0xB1, 0xBB, 0xA8, 0x74, 0x71, 0x31, 0x02, 0x4F, 0x71, 0xD3, 0xD2, 0x70,
0x04, 0xB1, 0xF8, 0xB0, 0xD9, 0x28, 0x95, 0x40, 0xE8, 0xD4, 0x18, 0xCB,
0xE4, 0x75, 0x7F, 0xB3, 0xEF, 0x5A, 0x49, 0x72, 0xEF, 0xBD, 0x69, 0x25,
0xCB, 0xB4, 0xD2, 0x84, 0x21, 0x02, 0x64, 0xB1, 0x00, 0x61, 0x4A, 0xA6,
0x4C, 0x09, 0x49, 0x3D, 0x74, 0xA2, 0x20, 0x9D, 0x6A, 0x7E, 0x5A, 0x92,
0xF4, 0xE1, 0x10, 0x0D, 0x56, 0xAC, 0xF6, 0xBD, 0xEB, 0x43, 0x89, 0x7A,
0xEF, 0x5A, 0x1C, 0x4B, 0xD0, 0x48, 0x4A, 0x0C, 0x9B, 0xCA, 0x21, 0xB3,
0xBC, 0x34, 0x02, 0x5A, 0x3B, 0xE5, 0xFF, 0x55, 0x4D, 0x92, 0x5E, 0x93,
0xB3, 0xE8, 0xF5, 0x94, 0xA9, 0x71, 0x53, 0x51, 0xBB, 0xBD, 0x48, 0x97,
0xEB, 0x29, 0x52, 0xE2, 0xA6, 0xA3, 0x77, 0x7A, 0x91, 0x2E, 0x62, 0xF5,
0xB4, 0x11, 0x97, 0x7F, 0x4D, 0x09, 0x0A, 0x9A, 0x89, 0x12, 0x0A, 0xC4,
0x8A, 0x16, 0xD0, 0x12, 0x10, 0x12, 0x41, 0xD0, 0x17, 0x40, 0x0C, 0x64,
0x0C, 0xB0, 0x10, 0x02, 0x88, 0x01, 0x19, 0x72, 0x69, 0xA8, 0xD4, 0x4C,
0x25, 0xA8, 0x48, 0x32, 0x48, 0x8B, 0xFA, 0x6E, 0x35, 0xC6, 0x05, 0x91,
0xB0, 0x48, 0x6D, 0xEC, 0x31, 0xB9, 0x68, 0x00, 0x49, 0x0C, 0x00, 0x49,
0xA8, 0x40, 0x84, 0x50, 0x13, 0x0B, 0x75, 0x64, 0x4D, 0x42, 0x45, 0x3B,
0x2D, 0x06, 0xE9, 0x6C, 0xDE, 0xBA, 0xE5, 0x60, 0x83, 0x2A, 0x56, 0x0E,
0xCA, 0xEE, 0x0F, 0xC0, 0xA4, 0xFB, 0x86, 0x7D, 0x04, 0x11, 0x20, 0x49,
0x10, 0xAA, 0xA0, 0xC2, 0x99, 0x5D, 0xEE, 0xCD, 0xCA, 0xF0, 0xBC, 0xDE,
0xA6, 0xAE, 0x65, 0xC5, 0x42, 0xA4, 0x47, 0x52, 0xBB, 0x16, 0xEE, 0x2D,
0xB8, 0xA8, 0xAF, 0x88, 0x14, 0xC4, 0x6C, 0x3C, 0x0C, 0x88, 0x04, 0x21,
0xA4, 0xE8, 0x92, 0x33, 0x5B, 0x6E, 0xCF, 0x9B, 0xBD, 0xCA, 0xAA, 0xD1,
0x35, 0xAA, 0xAE, 0x6E, 0xF8, 0xD5, 0x2E, 0xFB, 0xDC, 0xAA, 0xAD, 0x13,
0x5A, 0xAA, 0xE6, 0xEF, 0x8D, 0x52, 0xEC, 0x2E, 0x0F, 0xDD, 0x3C, 0x58,
0x9F, 0x16, 0x00, 0xA3, 0xB3, 0x48, 0x3A, 0x25, 0x6B, 0x8D, 0x05, 0x8A,
0x9B, 0x06, 0xE5, 0x82, 0x06, 0x9A, 0x42, 0x89, 0x58, 0x25, 0x7A, 0x13,
0x8B, 0x11, 0x2B, 0xB9, 0x1E, 0xDA, 0xA8, 0x2A, 0x92, 0x66, 0xC3, 0x2F,
0x5E, 0x0C, 0x42, 0x89, 0x36, 0x09, 0x06, 0x08, 0x5B, 0x7C, 0x08, 0x09,
0x12, 0xFA, 0x9A, 0x8C, 0x2E, 0xB4, 0x49, 0x69, 0x13, 0x97, 0x06, 0x0B,
0x55, 0x88, 0x0A, 0x9D, 0x2A, 0x57, 0x2E, 0x59, 0xAE, 0xF8, 0x30, 0x6E,
0x8E, 0x4C, 0x39, 0xC2, 0x1C, 0x5E, 0x28, 0x86, 0x18, 0x05, 0x8D, 0xD0,
0x02, 0xF1, 0x2C, 0x6D, 0xA2, 0x92, 0xDE, 0xD4, 0x33, 0x7C, 0xCE, 0x55,
0x69, 0xE9, 0x09, 0xD1, 0x86, 0x9E, 0x11, 0x84, 0xCC, 0x22, 0x9E, 0x14,
0xE1, 0x1A, 0x0F, 0x06, 0x83, 0x92, 0x1D, 0x9F, 0x1E, 0xFD, 0x5E, 0x5C,
0xB4, 0xE2, 0xEF, 0xC5, 0xEE, 0xB5, 0xC6, 0xAA, 0xB8, 0x9B, 0xF5, 0x79,
0x72, 0xD3, 0x8B, 0xBF, 0x17, 0xBA, 0xD7, 0x1A, 0xAA, 0xE2, 0x15, 0xCB,
0x4F, 0xFC, 0x04, 0x16, 0x04, 0x0A, 0x14, 0xF0, 0xBA, 0x2E, 0x97, 0xCF,
0xCA, 0xE0, 0x7B, 0x14, 0x0D, 0x10, 0xB1, 0xB8, 0x26, 0xA1, 0x55, 0x08,
0xA4, 0x72, 0x5F, 0x88, 0xD8, 0x10, 0xEF, 0xAB, 0xAC, 0xC0, 0x1F, 0xA4,
0x9E, 0x4B, 0x88, 0xAF, 0xEF, 0x4A, 0xB1, 0x29, 0xA8, 0x58, 0x69, 0x14,
0x26, 0x9A, 0xAC, 0x62, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, 0x08,
0x5D, 0x04, 0xF6, 0x0F, 0x00, 0x00, 0x73, 0x01, 0x01, 0x0C, 0x00, 0x00,
0x00, 0x00, 0x08, 0xCF, 0x05, 0x00, 0x00, 0x80, 0x12, 0x00, 0x00, 0xBA,
0x58, 0x66, 0x1D, 0x18, 0x44, 0xA8, 0x12, 0x1F, 0x04, 0xC9, 0xA4, 0xBE,
0x76, 0x40, 0x02, 0x0D, 0x20, 0x24, 0xA4, 0x92, 0x80, 0x60, 0x76, 0x76,
0xA3, 0x6F, 0xED, 0x42, 0xE2, 0x34, 0x07, 0x73, 0x1D, 0xD3, 0xEC, 0xDE,
0x5D, 0x86, 0xB7, 0xD8, 0x89, 0x72, 0xC3, 0xA8, 0x08, 0x2D, 0xCE, 0x52,
0x41, 0x00, 0x01, 0x62, 0x40, 0x90, 0x7D, 0xE0, 0xAA, 0xF0, 0x75, 0xC9,
0xF4, 0x3E, 0xC1, 0x9E, 0x9E, 0x0E, 0x2F, 0x04, 0x6C, 0xC3, 0x18, 0x1E,
0x70, 0x8D, 0x32, 0xD8, 0x10, 0x98, 0x72, 0xE8, 0xCA, 0x9B, 0x71, 0x04,
0x76, 0x84, 0x23, 0x86, 0x36, 0xEC, 0x0F, 0x93, 0x7E, 0xA5, 0x5D, 0xCE,
0x2B, 0x52, 0x77, 0x33, 0x2F, 0x8E, 0x29, 0xA9, 0xBF, 0x52, 0xAE, 0xE7,
0x15, 0xA9, 0x3B, 0x99, 0x97, 0xC7, 0x14, 0xD4, 0x39, 0x57, 0x96, 0xD7,
0xFE, 0x96, 0xA1, 0x54, 0x7E, 0xC5, 0x87, 0xE5, 0x74, 0xFA, 0xF4, 0x0D,
0x43, 0x4B, 0xB4, 0xAD, 0x40, 0xC5, 0x64, 0xD7, 0x8A, 0xFA, 0xD4, 0x12,
0x10, 0x81, 0x18, 0xB7, 0x05, 0xAE, 0xE6, 0x06, 0x34, 0x4A, 0x89, 0x42,
0x61, 0x24, 0xCA, 0x12, 0x8A, 0x4A, 0x18, 0xC0, 0x60, 0x08, 0x48, 0x2B,
0x03, 0x28, 0x4D, 0x09, 0x15, 0x41, 0x90, 0x44, 0x55, 0xEE, 0xA1, 0x4F,
0xAF, 0x0A, 0x7F, 0x1D, 0xC4, 0xA6, 0x4E, 0x03, 0x83, 0x27, 0x79, 0xB4,
0x26, 0x01, 0x9B, 0x68, 0xF7, 0x00, 0xC8, 0x3F, 0x60, 0xA6, 0x04, 0xCE,
0x31, 0x20, 0x16, 0x46, 0x69, 0xDF, 0xAA, 0x6B, 0xDA, 0x38, 0x0C, 0x57,
0x68, 0x2C, 0x32, 0xA0, 0xCF, 0x17, 0x0E, 0x1C, 0x56, 0xCE, 0x52, 0x9C,
0x8A, 0xFA, 0x04, 0xCA, 0x22, 0xB0, 0x79, 0xCD, 0x23, 0xA4, 0xD8, 0x90,
0x10, 0xF2, 0x52, 0x76, 0xD2, 0xCC, 0x85, 0xBB, 0x3E, 0x6C, 0xF7, 0xAB,
0xBB, 0x97, 0x9C, 0x27, 0x8B, 0x55, 0xF1, 0xAA, 0x93, 0x59, 0xEF, 0x57,
0x77, 0x2F, 0x38, 0x4F, 0x16, 0xAB, 0xE3, 0x55, 0x26, 0xAB, 0x97, 0xEC,
0x92, 0xAD, 0x1C, 0x65, 0xF2, 0x04, 0xC2, 0x68, 0x49, 0x74, 0x49, 0x62,
0xA0, 0xC0, 0x64, 0x14, 0x24, 0x84, 0x00, 0x06, 0x63, 0xB2, 0x32, 0x64,
0xBB, 0xD0, 0x05, 0x78, 0x0F, 0x78, 0x7E, 0xFD, 0xF9, 0x39, 0xE6, 0x80,
0x81, 0xC3, 0x05, 0xAA, 0xDF, 0xB3, 0x54, 0x21, 0x06, 0x41, 0x4C, 0xEE,
0x60, 0xD3, 0x42, 0x4B, 0xFA, 0x49, 0x06, 0x6A, 0x86, 0x90, 0x41, 0x35,
0x00, 0x2D, 0x35, 0x59, 0x2E, 0xB0, 0x4A, 0x4C, 0xFC, 0xDB, 0x8D, 0xE0,
0x20, 0x11, 0xF1, 0x21, 0xB0, 0x38, 0x76, 0x4B, 0xB9, 0xA7, 0xE4, 0xF4,
0x3E, 0xA9, 0x2E, 0x70, 0x42, 0xF3, 0x6B, 0x5E, 0x39, 0x3A, 0xD3, 0xD1,
0xF8, 0xA9, 0xED, 0xAF, 0x06, 0x1C, 0x52, 0x74, 0x41, 0x7A, 0x62, 0xE2,
0x34, 0x65, 0x08, 0xF0, 0x67, 0x23, 0x4B, 0x87, 0x5A, 0x7C, 0xE7, 0x67,
0xB1, 0x7A, 0x69, 0x15, 0x21, 0xCE, 0x78, 0x8C, 0xD2, 0xCF, 0xA3, 0x3D,
0xF2, 0xF5, 0x72, 0x4B, 0x3C, 0x69, 0x93, 0x8E, 0x2A, 0xE7, 0x19, 0xEF,
0x97, 0xAB, 0x92, 0x59, 0xE3, 0x4C, 0x9C, 0x71, 0x57, 0x38, 0xC1, 0xCF,
0xE8, 0x7C, 0x2E, 0x34, 0x3F, 0xB7, 0x51, 0x84, 0x80, 0xDD, 0x09, 0x20,
0x03, 0x22, 0x76, 0x48, 0x86, 0x09, 0x60, 0x90, 0x48, 0x0D, 0x30, 0x26,
0x68, 0xC9, 0xC7, 0xE3, 0x97, 0x70, 0x1E, 0x28, 0x8F, 0xCA, 0xAB, 0xBD,
0x24, 0x38, 0x02, 0x31, 0x33, 0x52, 0x1B, 0xB2, 0x24, 0x90, 0x85, 0x56,
0x72, 0x12, 0x09, 0xD0, 0x2C, 0x06, 0x65, 0x29, 0x02, 0x26, 0x15, 0xD1,
0xA8, 0x84, 0x11, 0x38, 0xD7, 0x32, 0x6D, 0x67, 0xC0, 0x40, 0x24, 0xCC,
0x94, 0x33, 0x27, 0x9E, 0x48, 0x0C, 0x39, 0xAA, 0xB9, 0xEC, 0x99, 0x07,
0xC9, 0x58, 0x37, 0x7B, 0xA6, 0xBF, 0x14, 0xAF, 0x97, 0xB4, 0x70, 0x10,
0xB0, 0x72, 0x52, 0x7D, 0x47, 0xC2, 0xE4, 0xF0, 0xDF, 0x47, 0x2F, 0x4D,
0x51, 0x9C, 0xA7, 0x17, 0x87, 0x91, 0x27, 0x91, 0x72, 0x56, 0xFA, 0xF4,
0xBA, 0x6C, 0x7A, 0x71, 0x19, 0xD2, 0x5E, 0x0E, 0xCF, 0xAF, 0x3D, 0xF2,
0x52, 0xDA, 0xD5, 0xCE, 0xE2, 0xA6, 0xBA, 0x91, 0xAC, 0xF7, 0xC9, 0x4B,
0x6B, 0x57, 0x3B, 0x8A, 0x9A, 0xEA, 0x46, 0x8F, 0x37, 0x41, 0x18, 0xCB,
0xFA, 0x24, 0x11, 0xB2, 0x9A, 0x51, 0x41, 0x28, 0x92, 0x49, 0x34, 0xBF,
0x21, 0xBA, 0x6A, 0x50, 0x09, 0x30, 0x10, 0x10, 0x09, 0x0C, 0x0C, 0x80,
0x0F, 0x0E, 0x48, 0x18, 0xCF, 0xAA, 0xFD, 0x25, 0x04, 0xFB, 0x04, 0x11,
0x5E, 0xAF, 0x40, 0x00, 0x01, 0x29, 0x30, 0x4A, 0xF1, 0xB5, 0x66, 0x58,
0x98, 0x12, 0x36, 0x41, 0x4C, 0xC4, 0x00, 0x52, 0x68, 0x30, 0x6C, 0x48,
0x66, 0x98, 0x25, 0xBA, 0x13, 0x0E, 0x3F, 0x80, 0x80, 0x49, 0x3D, 0xC7,
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0x8F, 0x79, 0x1E, 0x72, 0x4F, 0x49, 0x9E, 0x27, 0x24, 0x9C, 0xE4, 0x9B,
0x19, 0xC2, 0x0B, 0x78, 0x8F, 0x22, 0x75, 0x23, 0xB7, 0x93, 0x81, 0xD9,
0xF4, 0xD7, 0x8A, 0x56, 0xE2, 0xF8, 0xB9, 0xCD, 0xD5, 0x5D, 0xF4, 0xB5,
0xD7, 0x8A, 0x56, 0xE2, 0xF8, 0xB9, 0xCD, 0xD5, 0x5D, 0xF4, 0xB5, 0xAE,
0xC2, 0x45, 0x28, 0xD9, 0x49, 0xA8, 0x48, 0x63, 0x4D, 0x43, 0x21, 0x28,
0x89, 0x0F, 0x93, 0x51, 0xFA, 0x16, 0xEA, 0x02, 0xB6, 0x97, 0x64, 0x21,
0x01, 0x88, 0x20, 0x3F, 0x29, 0x82, 0x93, 0x55, 0x28, 0x10, 0x96, 0x30,
0xC3, 0x7B, 0x8C, 0x7F, 0x72, 0x65, 0x2E, 0x23, 0x01, 0x8C, 0xFB, 0x35,
0xE4, 0x1D, 0xEF, 0x41, 0x19, 0x6A, 0xA9, 0xAA, 0x4A, 0x1A, 0x90, 0x48,
0x68, 0x01, 0x62, 0x09, 0x12, 0x92, 0x96, 0xA0, 0x31, 0x00, 0x03, 0x54,
0x00, 0x49, 0xDA, 0x09, 0x88, 0x29, 0x84, 0xA2, 0x6C, 0xDC, 0xA1, 0xB2,
0xC4, 0x83, 0x15, 0x87, 0x87, 0xAA, 0x63, 0x84, 0xE4, 0xBE, 0x7D, 0x85,
0xD0, 0x54, 0x96, 0x87, 0x77, 0xAB, 0xC5, 0x7E, 0xB4, 0xEF, 0xC0, 0x2F,
0x48, 0x74, 0x33, 0xD6, 0x67, 0x9A, 0x68, 0xF6, 0x2A, 0x9C, 0x6E, 0x71,
0x9E, 0x3E, 0xB5, 0x39, 0xA6, 0x99, 0xD2, 0x7C, 0xED, 0x14, 0xE7, 0x52,
0xB3, 0xE8, 0xEC, 0x57, 0x25, 0xEB, 0x4C, 0x63, 0x5A, 0xE2, 0xAE, 0x6B,
0xB1, 0x5C, 0x97, 0xAD, 0x31, 0x8D, 0x6B, 0x8A, 0xB9, 0xAE, 0x90, 0x12,
0x37, 0x50, 0xB2, 0x18, 0x65, 0x92, 0x2E, 0x24, 0x14, 0x10, 0x50, 0x61,
0xFA, 0x26, 0x97, 0x55, 0x09, 0x10, 0x66, 0x12, 0xCA, 0x89, 0xA8, 0x91,
0x48, 0x48, 0x04, 0x99, 0xC4, 0x6B, 0xAA, 0xC4, 0x57, 0x9F, 0x92, 0xEF,
0x28, 0xAF, 0x15, 0x66, 0x24, 0x88, 0x09, 0x14, 0x00, 0x45, 0x28, 0x93,
0xA4, 0x80, 0x36, 0x09, 0x48, 0xD8, 0xB9, 0x04, 0x82, 0x19, 0x04, 0x10,
0x6D, 0x12, 0x77, 0xEC, 0xE9, 0x9A, 0xD7, 0x8F, 0xD5, 0x35, 0xC2, 0x0C,
0x07, 0x08, 0x24, 0xB8, 0x0C, 0x0E, 0x0D, 0xFA, 0x23, 0xC0, 0x40, 0x25,
0xFD, 0x8F, 0x48, 0x75, 0x92, 0x36, 0xAD, 0xE3, 0x3D, 0xE2, 0x93, 0xA3,
0x66, 0xC6, 0x92, 0x3C, 0x6C, 0xE1, 0x45, 0xE6, 0x4F, 0x67, 0x52, 0xB3,
0xDF, 0xEE, 0x26, 0x64, 0x8D, 0x5B, 0x72, 0xAA, 0x71, 0xA4, 0xBB, 0xEE,
0x26, 0x64, 0x8D, 0x5B, 0x72, 0xAA, 0x71, 0xA4, 0xBB, 0x69, 0x87, 0xF4,
0xE5, 0xDF, 0xD5, 0x00, 0xC9, 0x1A, 0x4E, 0xE1, 0x3F, 0xE4, 0x82, 0x82,
0x68, 0x48, 0x20, 0x52, 0xFA, 0x96, 0x11, 0x09, 0x41, 0x90, 0x60, 0x90,
0x41, 0x56, 0x87, 0xE8, 0x82, 0x42, 0x55, 0x05, 0x50, 0xBF, 0xBE, 0xEF,
0xFC, 0x64, 0x7B, 0x36, 0x97, 0xE0, 0xF8, 0x4F, 0x06, 0x4B, 0x48, 0x9D,
0x86, 0x99, 0x04, 0x1A, 0x94, 0xD0, 0x91, 0xA3, 0x09, 0x09, 0x24, 0x5E,
0x2F, 0x06, 0x5F, 0xD0, 0xD0, 0x48, 0x22, 0x0A, 0xF4, 0x17, 0x7D, 0x5A,
0x01, 0xAF, 0xF9, 0x32, 0x6E, 0x98, 0xEF, 0xF0, 0xF9, 0x0D, 0x7C, 0x82,
0xEE, 0x90, 0xEF, 0x08, 0x70, 0x54, 0x29, 0x0E, 0xF8, 0x70, 0x88, 0x27,
0xDA, 0x48, 0x9C, 0xD6, 0x03, 0x93, 0xF2, 0x38, 0xFF, 0x8A, 0x3D, 0x3F,
0x8A, 0x39, 0x74, 0xE9, 0xEA, 0xD3, 0x49, 0x87, 0x81, 0xC6, 0x78, 0xD2,
0x36, 0x38, 0xA8, 0xD4, 0xA5, 0x70, 0xCE, 0x8E, 0x84, 0xDC, 0xF5, 0xB6,
0x77, 0xA4, 0x0F, 0x3B, 0xD3, 0xA1, 0xB4, 0x7B, 0xC1, 0xD9, 0xF0, 0xF3,
0xBB, 0x95, 0x24, 0x32, 0xF2, 0x2A, 0x6B, 0xAA, 0x96, 0xE7, 0x77, 0x2A,
0x48, 0x65, 0xE4, 0x54, 0xD7, 0x55, 0x2D, 0x7A, 0x2A, 0x96, 0x25, 0xF0,
0x26, 0x00, 0xD0, 0x04, 0x49, 0x00, 0x6C, 0xA5, 0x29, 0x24, 0x06, 0x93,
0x00, 0x00, 0x10, 0x1A, 0xBC, 0x93, 0x2B, 0xCA, 0x61, 0x55, 0x20, 0x28,
0xC0, 0x24, 0xA5, 0x29, 0x4A, 0x52, 0x4C, 0x01, 0xA0, 0x34, 0x39, 0xB6,
0xBE, 0xB0, 0x41, 0x61, 0xC6, 0x65, 0xB5, 0x0A, 0x89, 0xF8, 0x80, 0x36,
0x49, 0x4A, 0x49, 0x50, 0x0C, 0xB0, 0x19, 0xA8, 0xA1, 0x20, 0x8E, 0x02,
0x50, 0x42, 0xB6, 0x03, 0x01, 0x05, 0x66, 0xFC, 0x04, 0x02, 0x4C, 0xB7,
0xEE, 0x72, 0x42, 0xFC, 0xD3, 0xA2, 0x1D, 0xA0, 0x16, 0x88, 0x72, 0xEE,
0xD4, 0xC3, 0x1B, 0x68, 0x14, 0xF7, 0x74, 0x8A, 0x3D, 0xE5, 0xBC, 0x4D,
0x1B, 0x34, 0xF1, 0xA6, 0x72, 0xE4, 0x90, 0x99, 0xCA, 0x68, 0x3F, 0x72,
0x79, 0xC8, 0xA9, 0xA0, 0x32, 0x9D, 0x31, 0x75, 0x30, 0x7C, 0xD2, 0x89,
0x11, 0xB4, 0xCA, 0x86, 0xCE, 0x4A, 0x10, 0xDD, 0x9F, 0x47, 0x3E, 0xAE,
0x17, 0x72, 0xB0, 0xD6, 0xD7, 0xC7, 0x05, 0xB9, 0xF5, 0x70, 0xBB, 0x95,
0x86, 0xB6, 0xBE, 0x38, 0x2D, 0xD8, 0x2B, 0x54, 0x0D, 0x1A, 0x29, 0xA5,
0x24, 0xB0, 0xD4, 0x43, 0x20, 0x83, 0x4A, 0x6A, 0xD5, 0x84, 0x94, 0x22,
0x08, 0x90, 0x09, 0x26, 0x54, 0x02, 0x03, 0x24, 0xAE, 0x8B, 0x9A, 0xA4,
0x88, 0x56, 0x26, 0x51, 0x08, 0x48, 0xA8, 0x89, 0xAC, 0xC8, 0x40, 0xAA,
0x52, 0xA9, 0xD6, 0x4C, 0xD0, 0x6C, 0x18, 0x5C, 0x7A, 0xB3, 0xBB, 0x9D,
0x45, 0x02, 0xB3, 0x21, 0x14, 0x9A, 0xA9, 0x49, 0x15, 0x65, 0x80, 0x26,
0x00, 0x19, 0x1E, 0xA1, 0x3F, 0xE9, 0x8F, 0xFA, 0x43, 0x49, 0x2C, 0x02,
0xA0, 0x42, 0x20, 0x1A, 0xBF, 0xE0, 0x4E, 0x80, 0x1E, 0x02, 0x01, 0x27,
0x45, 0xDD, 0xE9, 0x19, 0x23, 0x5E, 0x39, 0x31, 0x92, 0xC9, 0x26, 0xEB,
0xF1, 0x8C, 0x95, 0x69, 0xDD, 0x6A, 0x78, 0x30, 0xCF, 0x47, 0x01, 0x0A,
0xA1, 0x84, 0xD5, 0xE5, 0xC5, 0x12, 0x65, 0x63, 0x13, 0xDC, 0x92, 0x4B,
0x85, 0x2A, 0x76, 0x5D, 0x2C, 0xF9, 0x77, 0xE3, 0x13, 0x57, 0x72, 0xB9,
0xD2, 0xF2, 0xA7, 0x1C, 0x17, 0x37, 0xE3, 0x13, 0x57, 0x72, 0xB9, 0xD2,
0xF2, 0xA7, 0x1C, 0x17, 0x0E, 0xC4, 0x94, 0x3F, 0xCA, 0x4E, 0x00, 0x00,
0x00, 0x00, 0x82, 0x00, 0x00, 0x08, 0x5D, 0x04, 0x69, 0x11, 0x00, 0x00,
0x73, 0x01, 0x01, 0x0D, 0x00, 0x00, 0x00, 0x00, 0x08, 0xCF, 0x05, 0x00,
0x00, 0x51, 0x14, 0x00, 0x00, 0xC6, 0x9E, 0x08, 0x68, 0xE3, 0xE3, 0x37,
0x25, 0x68, 0xD2, 0x5A, 0x87, 0xEB, 0x4F, 0xCD, 0x13, 0x2D, 0x06, 0x26,
0x5A, 0x2A, 0x89, 0x20, 0x82, 0xD8, 0x26, 0x44, 0x7F, 0xC1, 0x0A, 0x35,
0x84, 0x48, 0x94, 0x82, 0x36, 0x24, 0xCA, 0x25, 0x0F, 0xEA, 0xAD, 0x24,
0x26, 0x24, 0x48, 0x68, 0x04, 0x58, 0xF0, 0x7A, 0x36, 0xE4, 0x5B, 0xAB,
0xD4, 0xBF, 0x9B, 0x76, 0x05, 0x09, 0x90, 0x69, 0x5A, 0x48, 0x22, 0x0B,
0x43, 0xB6, 0x28, 0x28, 0x30, 0x90, 0x65, 0x54, 0x1A, 0xC8, 0x88, 0x04,
0x76, 0x01, 0x01, 0x28, 0x82, 0x70, 0xA9, 0xA3, 0x4D, 0x2D, 0x44, 0x10,
0xD0, 0x42, 0xFE, 0xD9, 0xE0, 0x20, 0x12, 0x37, 0x93, 0xE0, 0x54, 0x8D,
0x5F, 0x60, 0x8D, 0xF5, 0x64, 0x85, 0x1B, 0xAE, 0xC8, 0x83, 0xCA, 0xFA,
0xF1, 0x20, 0xE4, 0x52, 0x9E, 0xCA, 0x58, 0x8A, 0xF1, 0xD9, 0xAD, 0xDE,
0x31, 0x00, 0xD0, 0xB2, 0x23, 0x43, 0x46, 0x98, 0x33, 0x2A, 0x02, 0xD2,
0xD2, 0x8A, 0xBA, 0x86, 0x1D, 0x33, 0x98, 0x69, 0xCD, 0x33, 0xF7, 0x1F,
0x30, 0xD0, 0x09, 0xC2, 0x66, 0xCC, 0x44, 0x87, 0x77, 0x60, 0x7C, 0x1C,
0xF2, 0x6B, 0x85, 0xD2, 0xA6, 0xEF, 0x2A, 0x5D, 0xC9, 0x73, 0x9E, 0x4D,
0x70, 0xBA, 0x54, 0xDD, 0xE5, 0x4B, 0xB9, 0x2E, 0x4C, 0x35, 0x34, 0xF1,
0x95, 0xA3, 0x97, 0xA5, 0x2F, 0x89, 0x28, 0x21, 0xAB, 0x05, 0xBA, 0x13,
0xB8, 0x24, 0x10, 0x73, 0x02, 0x60, 0x83, 0x8F, 0x69, 0x49, 0x1E, 0xE4,
0x88, 0x3B, 0x50, 0x8C, 0x31, 0x04, 0x48, 0xC3, 0x41, 0xAE, 0x62, 0xBC,
0x69, 0x46, 0x6A, 0x52, 0x94, 0xA0, 0x4B, 0x87, 0x81, 0x49, 0x05, 0x04,
0x16, 0x6E, 0x97, 0xF4, 0x93, 0x43, 0xE2, 0x4E, 0x24, 0x00, 0x2A, 0x50,
0x41, 0x18, 0xE5, 0x29, 0x9A, 0x96, 0x61, 0x90, 0x20, 0x26, 0x47, 0x3D,
0x18, 0x33, 0x26, 0x49, 0x80, 0x2F, 0x82, 0x77, 0x74, 0xB0, 0x01, 0x27,
0xB8, 0x03, 0x67, 0x4B, 0xE4, 0xE8, 0x28, 0x15, 0x84, 0x21, 0xA4, 0xC4,
0x98, 0x6C, 0xAB, 0xA6, 0xCB, 0x24, 0xD7, 0x29, 0x6E, 0x89, 0xD3, 0x2E,
0x11, 0x3A, 0x64, 0xCE, 0xA5, 0x80, 0x6E, 0x00, 0xC6, 0xA0, 0x52, 0x02,
0xA0, 0x41, 0xB5, 0xDC, 0xA8, 0xC1, 0xDC, 0x12, 0xC9, 0x93, 0x1B, 0x33,
0x1A, 0x81, 0xB6, 0x09, 0x89, 0x12, 0xAA, 0xF3, 0xAB, 0xD8, 0xB9, 0x93,
0x23, 0xB1, 0x10, 0xA8, 0x85, 0xCA, 0x4B, 0x58, 0x17, 0x95, 0xEB, 0x83,
0x59, 0x66, 0x1C, 0xA4, 0xD8, 0x10, 0xF6, 0x8E, 0x02, 0x24, 0xC7, 0x23,
0x8A, 0x84, 0xC0, 0xDF, 0x4A, 0x19, 0x80, 0xC0, 0xB9, 0xCE, 0x73, 0xAE,
0x79, 0x3D, 0x6F, 0x8B, 0xF1, 0x41, 0xA4, 0xE2, 0x8F, 0x78, 0x8A, 0x78,
0x52, 0xCE, 0x9B, 0x42, 0x66, 0x83, 0x3A, 0x7D, 0x69, 0x1B, 0x30, 0xCE,
0x1B, 0x47, 0xC2, 0x30, 0x52, 0xED, 0xDE, 0xD7, 0x72, 0x5E, 0xB5, 0xBD,
0xDC, 0x37, 0x4C, 0x97, 0x09, 0x7D, 0xC9, 0x7A, 0xD6, 0xF7, 0x70, 0xDD,
0x32, 0x5C, 0x25, 0xCB, 0x00, 0x5B, 0x5B, 0x93, 0xB2, 0x15, 0x41, 0x10,
0x36, 0x08, 0x30, 0xD3, 0xB0, 0x7A, 0xD0, 0x09, 0x16, 0x8E, 0xAA, 0x1F,
0xA5, 0x9C, 0x24, 0xCA, 0xA1, 0x8A, 0x40, 0x22, 0x66, 0x64, 0xF6, 0x81,
0x4A, 0xEE, 0xDD, 0x56, 0xE4, 0xD0, 0x41, 0x31, 0x0B, 0xCB, 0xFA, 0x86,
0x3E, 0x6F, 0x1E, 0x38, 0x53, 0x14, 0x97, 0xFC, 0x44, 0x24, 0x13, 0x55,
0x40, 0x11, 0x43, 0xE7, 0xD4, 0xFE, 0xE8, 0xA6, 0x48, 0x2A, 0x31, 0x94,
0x55, 0x04, 0x49, 0x58, 0xB4, 0x0A, 0xA1, 0x22, 0x85, 0xAA, 0x42, 0x64,
0xC4, 0x90, 0x02, 0xA0, 0x19, 0xA5, 0x20, 0x02, 0x48, 0xA9, 0x54, 0xA6,
0x61, 0x29, 0x24, 0x9B, 0xC9, 0x92, 0xD2, 0x92, 0x87, 0x55, 0x04, 0x12,
0x5A, 0x64, 0xC9, 0x86, 0x80, 0x5D, 0x49, 0x40, 0x42, 0x12, 0x53, 0x45,
0x04, 0x92, 0x6A, 0x00, 0x40, 0x48, 0x00, 0xCA, 0x0A, 0x15, 0x91, 0x10,
0x10, 0x49, 0x33, 0x79, 0x22, 0x52, 0x92, 0x49, 0x32, 0x04, 0xA4, 0x20,
0x35, 0x89, 0x29, 0xAC, 0xD2, 0x30, 0xD2, 0x49, 0x04, 0x99, 0x8A, 0xA5,
0x10, 0x04, 0x42, 0x01, 0x1B, 0x75, 0xB0, 0x4D, 0x52, 0x0C, 0x12, 0x26,
0x4C, 0x96, 0x98, 0x0A, 0xE5, 0x89, 0x90, 0x24, 0x40, 0x84, 0x9D, 0xC4,
0x83, 0x55, 0x29, 0x2C, 0x15, 0x28, 0x61, 0xC2, 0x33, 0x01, 0x09, 0x21,
0x00, 0xA2, 0x24, 0x92, 0x02, 0x41, 0x21, 0x00, 0x06, 0x94, 0x3E, 0x6C,
0x06, 0x08, 0x58, 0x51, 0x24, 0x82, 0x96, 0xC0, 0x25, 0x29, 0x34, 0xD2,
0x9A, 0x81, 0x88, 0x46, 0x98, 0x22, 0xF0, 0x89, 0x24, 0x01, 0x55, 0x21,
0x32, 0x5A, 0x4B, 0x14, 0x80, 0xC8, 0x50, 0x28, 0xA1, 0x32, 0xD2, 0x94,
0x95, 0x64, 0x8E, 0x81, 0x24, 0x90, 0xF1, 0xF9, 0x47, 0xB1, 0x50, 0x7F,
0x8C, 0xE9, 0x33, 0x84, 0x52, 0x99, 0xA4, 0x45, 0x15, 0x36, 0xF7, 0xBE,
0xCF, 0x1E, 0x0A, 0xDA, 0x9C, 0x36, 0x23, 0x7B, 0xBC, 0x42, 0xC3, 0x34,
0x6B, 0x60, 0x55, 0xFE, 0xA7, 0x77, 0xA6, 0xB7, 0x95, 0x24, 0x4B, 0xDD,
0xE9, 0xAD, 0xE5, 0x49, 0x12, 0xD6, 0x2B, 0x64, 0xF5, 0x10, 0x16, 0x7C,
0xB3, 0x69, 0x25, 0x7A, 0x41, 0xAB, 0x02, 0x06, 0xE1, 0xA9, 0x02, 0x78,
0xDF, 0x02, 0x1F, 0x12, 0x93, 0x55, 0x90, 0x20, 0xC6, 0x10, 0x7C, 0xFA,
0x84, 0xBB, 0x32, 0x90, 0x64, 0xD3, 0x84, 0x98, 0xA1, 0x09, 0x94, 0x18,
0x01, 0x60, 0x62, 0x0A, 0x1D, 0x13, 0x52, 0x91, 0x00, 0x12, 0x42, 0x16,
0x07, 0x0F, 0x09, 0x14, 0x14, 0x14, 0x04, 0x14, 0xA4, 0xC0, 0x0C, 0x88,
0xD0, 0x09, 0x64, 0x87, 0xA7, 0x5A, 0x84, 0x93, 0x76, 0x92, 0x1C, 0x45,
0x09, 0x77, 0xA5, 0x7F, 0xA8, 0xA2, 0x83, 0x40, 0x54, 0xCC, 0x32, 0x40,
0x07, 0x62, 0x32, 0x38, 0x94, 0x8D, 0x01, 0x2E, 0xA8, 0x00, 0x55, 0x25,
0x8B, 0xDA, 0xC2, 0xE8, 0xD5, 0x0D, 0x0D, 0x01, 0xEA, 0x46, 0xE8, 0x2A,
0x28, 0x3B, 0x7F, 0xB1, 0xEF, 0x8E, 0xB1, 0x9A, 0x97, 0x3B, 0xE3, 0xAC,
0x66, 0xA5, 0xCA, 0x43, 0xE1, 0x45, 0xCA, 0x00, 0x02, 0x24, 0x28, 0x0D,
0x4A, 0x16, 0x11, 0x40, 0xBE, 0x6A, 0x41, 0x12, 0x82, 0x43, 0x64, 0x11,
0xFE, 0x3A, 0x30, 0xA8, 0xD8, 0x96, 0x4B, 0xD3, 0x84, 0x0A, 0x15, 0x7F,
0xB7, 0xF7, 0xF3, 0xE7, 0x26, 0x5D, 0xDD, 0xFB, 0xF9, 0xF3, 0x93, 0x2E,
0xEE, 0xDD, 0xBD, 0x29, 0x40, 0x00, 0x44, 0x6F, 0xFC, 0x66, 0x4A, 0x6B,
0x32, 0x04, 0x08, 0x00, 0x9D, 0x55, 0x8A, 0x84, 0x90, 0x74, 0x75, 0x7F,
0x3F, 0x90, 0xF4, 0xE3, 0x0A, 0x8E, 0xEF, 0x6F, 0xEB, 0x5E, 0xD9, 0x2B,
0x57, 0x77, 0xEB, 0x5E, 0xD9, 0x2B, 0x57, 0x76, 0x8A, 0x1D, 0x87, 0xE7,
0x91, 0x35, 0x6A, 0x85, 0x16, 0x71, 0x24, 0x08, 0x23, 0x62, 0xF9, 0x1D,
0x77, 0x0A, 0xB7, 0xB7, 0x28, 0x7A, 0x4C, 0x6B, 0xEB, 0x3D, 0xF4, 0x2D,
0x8A, 0x8F, 0x8A, 0xD7, 0x12, 0x50, 0x81, 0x2D, 0xBA, 0x09, 0xAB, 0x29,
0xA0, 0xDB, 0xE6, 0x10, 0x21, 0x26, 0x4C, 0xAC, 0xE1, 0x45, 0xB9, 0x15,
0x2A, 0x0A, 0x24, 0x94, 0x92, 0x9A, 0x89, 0x09, 0x28, 0x2D, 0x05, 0xCF,
0xCB, 0x2D, 0x71, 0x56, 0xDF, 0xEB, 0xC1, 0x72, 0xA0, 0xAD, 0xAE, 0xEC,
0xFA, 0x7D, 0x65, 0x4A, 0xAB, 0xBB, 0x56, 0xE5, 0xE4, 0xBE, 0x2E, 0x5C,
0xBF, 0x59, 0x52, 0xAA, 0xEE, 0xD5, 0xB9, 0x79, 0x2F, 0x8B, 0x97, 0x2C,
0x95, 0xEE, 0xCA, 0x2C, 0x3B, 0x00, 0x8E, 0xAA, 0x52, 0x84, 0x83, 0x7A,
0x56, 0xE8, 0x41, 0xD9, 0x24, 0xA6, 0xC9, 0x22, 0x7A, 0x89, 0x1D, 0x00,
0x57, 0x36, 0x0C, 0xAA, 0x48, 0xDB, 0x49, 0x8A, 0xA8, 0x21, 0x44, 0x55,
0x34, 0x24, 0x0A, 0x88, 0x45, 0x01, 0x25, 0x00, 0x44, 0x09, 0x21, 0x91,
0x0D, 0x6B, 0x24, 0xB2, 0x5B, 0x25, 0x82, 0x66, 0x5D, 0x48, 0x91, 0x20,
0x88, 0x45, 0x55, 0x81, 0x28, 0x34, 0x42, 0x24, 0x21, 0x80, 0x44, 0xD4,
0x94, 0x00, 0x25, 0x25, 0x02, 0x00, 0x41, 0x29, 0x48, 0x44, 0x81, 0x09,
0xAA, 0x40, 0x25, 0xB3, 0x20, 0x12, 0x25, 0xB2, 0x01, 0x62, 0x74, 0x71,
0x28, 0xE7, 0x95, 0xBA, 0xDB, 0x3E, 0x08, 0xD7, 0x56, 0xBC, 0xFC, 0x03,
0xC2, 0xED, 0x7F, 0x2B, 0x8B, 0x52, 0xB1, 0x63, 0x1D, 0x97, 0xBC, 0xBB,
0x9C, 0xE5, 0x9F, 0x35, 0x67, 0xCB, 0xDE, 0x0D, 0xDD, 0xDA, 0xB6, 0x95,
0x35, 0xC6, 0xA4, 0x97, 0xDE, 0x0D, 0xDD, 0xDA, 0xB6, 0x95, 0x35, 0xC6,
0xA4, 0x96, 0x65, 0xAC, 0x0F, 0xA9, 0x0A, 0x94, 0xA5, 0x01, 0x22, 0xF4,
0xAC, 0x12, 0x22, 0x02, 0x2A, 0xC2, 0x70, 0xC9, 0x76, 0xCF, 0xA9, 0x2B,
0x49, 0xA0, 0x04, 0x49, 0x42, 0xE9, 0x82, 0x03, 0x4C, 0x9D, 0x01, 0x20,
0x18, 0x33, 0xB8, 0x80, 0x64, 0x02, 0x44, 0x82, 0x0B, 0x09, 0x04, 0xB1,
0x2C, 0xC2, 0x2D, 0x5A, 0xA6, 0x6A, 0xBF, 0x7C, 0x03, 0xB3, 0x26, 0x24,
0x54, 0xD1, 0x6C, 0xD2, 0x82, 0x08, 0x31, 0x87, 0x0C, 0x98, 0x01, 0x33,
0x28, 0x29, 0x29, 0x40, 0x4A, 0x30, 0xE8, 0x00, 0x52, 0x02, 0x68, 0x42,
0x1F, 0xCD, 0x44, 0xD6, 0x70, 0x88, 0x84, 0x14, 0x55, 0x48, 0x6A, 0x6B,
0x3A, 0x10, 0x88, 0x28, 0xC2, 0x76, 0x52, 0x41, 0x09, 0x6C, 0x41, 0x11,
0x08, 0x48, 0xDD, 0x58, 0x28, 0x48, 0xDC, 0xD8, 0xAD, 0xB3, 0x6D, 0x86,
0x83, 0xE1, 0xF6, 0x1D, 0xCE, 0x84, 0x4B, 0x3E, 0x99, 0x74, 0xC7, 0x31,
0xE5, 0x9F, 0xC4, 0x1E, 0xCA, 0x9C, 0xDC, 0x0F, 0x1B, 0x58, 0x9D, 0x94,
0xB4, 0x23, 0x40, 0xBC, 0xE8, 0x6A, 0x23, 0xC9, 0xAE, 0x29, 0x29, 0x0E,
0x50, 0x33, 0x14, 0xC5, 0x67, 0xC9, 0xD8, 0x6E, 0xAF, 0x52, 0xB6, 0x95,
0x35, 0xAE, 0x89, 0xAE, 0xC3, 0x75, 0x7A, 0x95, 0xB4, 0xA9, 0xAD, 0x74,
0x4D, 0x0F, 0xF5, 0x12, 0x1B, 0x50, 0x52, 0x82, 0x85, 0x4D, 0x51, 0xAD,
0x82, 0x62, 0x19, 0x33, 0x14, 0xBB, 0x6A, 0x89, 0x5A, 0x48, 0x7C, 0xFE,
0xF0, 0x08, 0x68, 0xBF, 0x6D, 0xD6, 0x35, 0xC6, 0x5A, 0x62, 0x08, 0x04,
0xB4, 0x10, 0x24, 0x4D, 0x56, 0x90, 0x56, 0x0B, 0x68, 0xA8, 0x28, 0x2B,
0x04, 0xA5, 0x2C, 0xC2, 0x86, 0xE1, 0xB5, 0xD5, 0xB9, 0x30, 0x43, 0x0B,
0x13, 0x25, 0x04, 0x94, 0x26, 0x82, 0x5F, 0x09, 0x76, 0x50, 0x97, 0xE2,
0xA0, 0x42, 0x5F, 0x49, 0x32, 0x13, 0xEB, 0x10, 0xA9, 0x14, 0x82, 0x2A,
0x30, 0x89, 0x21, 0x77, 0x4A, 0xA4, 0x18, 0x82, 0x20, 0x0A, 0xA5, 0xA6,
0x7A, 0x8F, 0x01, 0x00, 0x95, 0x5B, 0xFB, 0xCD, 0xAF, 0x60, 0x47, 0x92,
0xCB, 0x81, 0xF5, 0x62, 0xC1, 0x57, 0x4D, 0x2A, 0x32, 0xEE, 0x56, 0x3C,
0xF3, 0x36, 0x45, 0x88, 0xD9, 0x2C, 0x80, 0xDE, 0x07, 0xB4, 0x69, 0x21,
0xA2, 0x91, 0xC0, 0xA5, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, 0x08,
0x5D, 0x04, 0xDD, 0x12, 0x00, 0x00, 0x73, 0x01, 0x01, 0x0E, 0x00, 0x00,
0x00, 0x00, 0x08, 0xCF, 0x05, 0x00, 0x00, 0x67, 0x15, 0x00, 0x00, 0xD7,
0x1E, 0x00, 0x81, 0xB4, 0xC8, 0x10, 0xC4, 0x86, 0x21, 0x8C, 0x82, 0xE2,
0x6F, 0x2B, 0x2F, 0x08, 0xA5, 0x8D, 0xF4, 0x42, 0x4C, 0x6D, 0x08, 0x6F,
0x2F, 0x04, 0x8B, 0x2C, 0x43, 0x69, 0x13, 0x60, 0x7C, 0x9D, 0xDD, 0x5E,
0x73, 0x5A, 0xB9, 0x5B, 0x1A, 0x9C, 0x71, 0x13, 0x5D, 0xDD, 0x5E, 0x73,
0x5A, 0xB9, 0x5B, 0x1A, 0x9C, 0x71, 0x13, 0x52, 0x62, 0x84, 0x1D, 0x82,
0xC4, 0x48, 0x75, 0x16, 0x31, 0xA0, 0x2B, 0x11, 0x52, 0x41, 0xAA, 0x02,
0xC1, 0xD0, 0x0B, 0xF5, 0x81, 0x09, 0x12, 0xC3, 0x06, 0x43, 0x1A, 0x14,
0x8B, 0xCB, 0x23, 0x73, 0x11, 0x06, 0x5A, 0x22, 0x01, 0x99, 0x85, 0x53,
0x20, 0xBB, 0x15, 0x2A, 0x3B, 0x29, 0x4C, 0xA5, 0x14, 0x44, 0x12, 0x4C,
0xA1, 0x90, 0x96, 0xB2, 0x1D, 0x7F, 0xE3, 0xB4, 0x82, 0xC4, 0x24, 0x61,
0xD2, 0x09, 0xA8, 0xF8, 0xD4, 0xAB, 0x49, 0x09, 0x01, 0x01, 0x28, 0xC3,
0x82, 0xC9, 0x0D, 0x82, 0xC0, 0x42, 0x84, 0xEE, 0x15, 0x2C, 0x60, 0x56,
0x61, 0x8D, 0x0D, 0x75, 0xDC, 0x17, 0xB6, 0xE9, 0x72, 0xEF, 0xC0, 0x40,
0x24, 0x3A, 0xB0, 0x4C, 0xAD, 0x7E, 0xC7, 0xA7, 0x13, 0x46, 0xEF, 0xED,
0xC4, 0x68, 0x56, 0x2D, 0x41, 0x0F, 0x07, 0x44, 0xE4, 0xF9, 0x52, 0x20,
0x75, 0x96, 0x9A, 0xB1, 0xF3, 0x10, 0xD3, 0x43, 0xC0, 0x86, 0xAA, 0xEA,
0x5F, 0x3C, 0x21, 0xA1, 0xC0, 0x3C, 0x11, 0x67, 0xC1, 0xDD, 0xD1, 0x99,
0xAB, 0x99, 0xBB, 0x54, 0xD7, 0x1C, 0x5C, 0xAB, 0xEE, 0xE8, 0xCC, 0xD5,
0xCC, 0xDD, 0xAA, 0x6B, 0x8E, 0x2E, 0x55, 0x90, 0xD7, 0xC8, 0xCB, 0xE5,
0xD4, 0x42, 0x46, 0xFD, 0x41, 0x55, 0xD6, 0x90, 0x61, 0x00, 0x0C, 0x8F,
0x4E, 0x47, 0xA7, 0x8E, 0x82, 0x09, 0x1A, 0x09, 0x06, 0x4A, 0x80, 0x85,
0xF0, 0x40, 0x40, 0xDA, 0x5B, 0x02, 0xFD, 0xC1, 0x05, 0x00, 0xB2, 0x92,
0x0D, 0x50, 0x12, 0x02, 0xD0, 0xA5, 0xF1, 0xA1, 0x34, 0x80, 0x69, 0xA5,
0x15, 0x6A, 0x0A, 0xA8, 0x12, 0x24, 0x9D, 0x00, 0x77, 0x12, 0x44, 0xC2,
0x0C, 0x15, 0x8C, 0x12, 0x68, 0x24, 0x22, 0x84, 0x94, 0x2C, 0x5F, 0xD4,
0x4B, 0xFA, 0xCA, 0x97, 0x61, 0x08, 0xA4, 0x20, 0xD5, 0x41, 0x49, 0x28,
0x4D, 0x40, 0x12, 0x01, 0x94, 0x14, 0x92, 0x84, 0xD4, 0x01, 0x20, 0x35,
0x05, 0x24, 0x84, 0xC0, 0x06, 0x06, 0x5C, 0x90, 0x12, 0x76, 0x00, 0xAA,
0x00, 0x98, 0x25, 0x89, 0x26, 0x0E, 0x75, 0x91, 0x08, 0xA7, 0x6A, 0xF0,
0xDD, 0x9E, 0xB2, 0x95, 0x66, 0x78, 0xC5, 0x71, 0x56, 0xEE, 0x3F, 0x2E,
0x1E, 0xED, 0xBA, 0x8A, 0x89, 0x51, 0xED, 0x1C, 0x02, 0xB0, 0xD5, 0x9A,
0xFF, 0x8E, 0x2A, 0x9C, 0xDD, 0xE9, 0x5D, 0xDC, 0xA9, 0x7D, 0x6A, 0xF5,
0x56, 0x44, 0xD2, 0xB6, 0x86, 0xC3, 0x69, 0x80, 0x03, 0xE2, 0xA4, 0x21,
0x01, 0x28, 0x82, 0x9A, 0x02, 0x2A, 0x81, 0x55, 0xD8, 0xA1, 0x15, 0x4F,
0x11, 0xA2, 0xAB, 0xB0, 0x64, 0x21, 0x32, 0x01, 0x56, 0x76, 0x20, 0x90,
0x64, 0x88, 0x63, 0x61, 0x40, 0x45, 0x40, 0x40, 0x44, 0x8A, 0x93, 0x02,
0xAC, 0x61, 0xC1, 0x58, 0x84, 0x14, 0xD2, 0x68, 0x45, 0x28, 0xE3, 0x45,
0x00, 0xCA, 0x02, 0x42, 0x68, 0x9A, 0xA8, 0x24, 0x91, 0x25, 0xD6, 0x5D,
0x6A, 0x8D, 0xC2, 0x98, 0x00, 0xB1, 0xF1, 0x62, 0x10, 0x98, 0x42, 0xD3,
0xF0, 0x28, 0x7C, 0x12, 0x11, 0x45, 0x14, 0x80, 0x84, 0x26, 0x10, 0x26,
0x80, 0x2A, 0xD0, 0x01, 0x28, 0x02, 0x42, 0x0C, 0x8A, 0x0C, 0x84, 0x49,
0xA8, 0x29, 0x94, 0x21, 0x32, 0x11, 0x56, 0xB2, 0x14, 0xCA, 0x01, 0x48,
0x89, 0x64, 0x91, 0x13, 0xA5, 0x3C, 0x95, 0xA0, 0x37, 0xDE, 0xC1, 0x2C,
0x17, 0x39, 0xCD, 0x61, 0xD5, 0x3E, 0x78, 0x08, 0x04, 0xAB, 0x1B, 0x97,
0x0D, 0x16, 0xDD, 0x81, 0xB8, 0x1E, 0xB5, 0xBF, 0x16, 0xDA, 0x6A, 0xED,
0x9C, 0xDD, 0xD3, 0x5C, 0x6A, 0xE2, 0xF0, 0x91, 0xFA, 0xAA, 0x94, 0xBF,
0x24, 0x9A, 0x12, 0x4A, 0x52, 0x52, 0x50, 0xF8, 0xC1, 0x45, 0x01, 0x0B,
0x54, 0x3E, 0x41, 0x7E, 0x0D, 0x29, 0xE2, 0x47, 0xE2, 0x67, 0xE8, 0x22,
0x90, 0x08, 0x41, 0x75, 0xA2, 0x42, 0x12, 0x0B, 0x34, 0x5A, 0x04, 0x55,
0x13, 0x10, 0xD9, 0x30, 0x51, 0xA2, 0xA4, 0xB4, 0xA0, 0xA0, 0x48, 0x30,
0x16, 0x04, 0x9A, 0xAD, 0xF0, 0xA8, 0x47, 0x13, 0xF4, 0x71, 0xBE, 0x7F,
0x01, 0x28, 0x24, 0x84, 0x88, 0x20, 0xC8, 0x21, 0x7A, 0x87, 0x63, 0x46,
0x25, 0x0C, 0x09, 0x13, 0x12, 0x89, 0x6D, 0x42, 0x5F, 0x2C, 0x40, 0x7E,
0xEC, 0x24, 0xD0, 0x84, 0xA0, 0x26, 0xA1, 0x21, 0x81, 0x20, 0x12, 0x82,
0xC4, 0xA0, 0xCA, 0x12, 0x21, 0x28, 0x20, 0xD0, 0x91, 0x09, 0x41, 0x94,
0x24, 0x42, 0x50, 0x9C, 0x24, 0xA0, 0xC8, 0x4E, 0xD0, 0x64, 0x27, 0x68,
0x54, 0xB6, 0x15, 0x6B, 0x22, 0x4C, 0x98, 0x81, 0x2D, 0x51, 0x5F, 0x27,
0x5A, 0xB3, 0xBD, 0x03, 0x0A, 0x8C, 0xC9, 0x1D, 0x56, 0xBC, 0xAA, 0x33,
0x2F, 0x6D, 0xCA, 0x9C, 0x4E, 0x27, 0x80, 0x18, 0xA0, 0x00, 0x2F, 0x3C,
0xC9, 0xF5, 0x77, 0x0B, 0xDE, 0xA1, 0xC9, 0xD6, 0xBB, 0xAE, 0xAE, 0x5D,
0x96, 0x94, 0x05, 0xB1, 0x85, 0x4C, 0x24, 0x22, 0x00, 0x68, 0xE8, 0x91,
0x56, 0x81, 0x6E, 0x7F, 0x03, 0x46, 0xE2, 0xA1, 0x10, 0x41, 0xD8, 0x8D,
0x09, 0x26, 0x1A, 0x49, 0x24, 0xE8, 0x0C, 0x57, 0x6A, 0x03, 0x5A, 0xD6,
0x9E, 0xCB, 0x7D, 0xF5, 0x75, 0xE3, 0xA6, 0x92, 0x1E, 0xF4, 0xC0, 0x58,
0x92, 0x03, 0x4F, 0x4B, 0xDA, 0x95, 0x08, 0x09, 0x0E, 0xA9, 0xA4, 0xD4,
0xDB, 0x50, 0x0C, 0xC1, 0x24, 0x01, 0x02, 0x64, 0x00, 0x25, 0x20, 0x6B,
0x65, 0xA5, 0xEF, 0x4C, 0x1A, 0xA6, 0x67, 0x7B, 0xB0, 0xC4, 0x4E, 0x80,
0x28, 0x00, 0x71, 0xFE, 0xDF, 0xA4, 0x84, 0x52, 0x84, 0x5B, 0xC5, 0x0E,
0x80, 0x29, 0xA5, 0x19, 0x1E, 0xA0, 0x43, 0xFA, 0x42, 0x12, 0x94, 0xA4,
0xA4, 0x21, 0xF2, 0x28, 0x21, 0x9A, 0x65, 0xC1, 0xEF, 0x4C, 0xCE, 0xB8,
0xDB, 0x17, 0x38, 0x4D, 0x59, 0x5D, 0x96, 0x3D, 0x9A, 0xB2, 0xA1, 0x9A,
0x59, 0xC6, 0x2A, 0x4C, 0xB5, 0x3B, 0xD1, 0x91, 0x70, 0x64, 0x84, 0x82,
0x92, 0x40, 0x92, 0x2A, 0x24, 0x1D, 0xBD, 0x69, 0x97, 0xC5, 0xE3, 0x2A,
0x5E, 0x91, 0x41, 0x8C, 0x42, 0x09, 0x17, 0x44, 0x90, 0xD1, 0x09, 0x25,
0x09, 0x28, 0x25, 0x32, 0x84, 0x92, 0xC5, 0x9C, 0x44, 0xC2, 0x00, 0x20,
0x06, 0x01, 0x02, 0x4B, 0xF2, 0x90, 0x13, 0xB2, 0xF1, 0xA6, 0x08, 0xA6,
0x82, 0xAC, 0x36, 0x64, 0x35, 0xB2, 0x92, 0x00, 0x6B, 0xE5, 0xA1, 0xA6,
0xAC, 0x09, 0x69, 0x45, 0x08, 0x7C, 0x04, 0x94, 0xA2, 0x1A, 0x84, 0xA3,
0x0D, 0x29, 0x7E, 0xF9, 0x0E, 0xCB, 0xFA, 0x68, 0x43, 0xE0, 0x0B, 0xFA,
0x30, 0xDF, 0xDB, 0x91, 0xC6, 0xB6, 0xFE, 0x94, 0xAD, 0x2D, 0x50, 0x12,
0x1F, 0x24, 0xD4, 0x45, 0x05, 0xF8, 0x4D, 0x54, 0xBF, 0x4C, 0x3F, 0x34,
0x93, 0x56, 0x84, 0x3F, 0x4D, 0x4A, 0x00, 0x5B, 0x34, 0x3E, 0x7D, 0x08,
0x4A, 0x1F, 0xAC, 0x11, 0x49, 0x08, 0x1C, 0x4B, 0x50, 0xFD, 0x60, 0x66,
0x84, 0xD0, 0x94, 0x20, 0xA1, 0xB5, 0x10, 0x4D, 0x29, 0xA5, 0x33, 0x4B,
0xAA, 0xA2, 0x03, 0xC7, 0xA7, 0x9A, 0xD4, 0xCB, 0x85, 0x32, 0x2B, 0x32,
0xA2, 0xAE, 0xF3, 0x5A, 0x99, 0x70, 0xA6, 0x45, 0x66, 0x54, 0x55, 0xDD,
0x29, 0x4A, 0x13, 0x12, 0xC8, 0x69, 0x9D, 0x35, 0xA6, 0x4B, 0x09, 0x40,
0x00, 0xAA, 0x4E, 0x89, 0x60, 0xD4, 0x28, 0x58, 0x0E, 0xA5, 0x86, 0x36,
0x44, 0x19, 0x06, 0x44, 0x6D, 0xA5, 0x8A, 0x8C, 0x68, 0xE4, 0x99, 0x9A,
0x92, 0x9A, 0x93, 0xB8, 0x11, 0x24, 0xB4, 0x93, 0x1A, 0x1D, 0x48, 0x02,
0xE9, 0x02, 0x48, 0x30, 0x49, 0x98, 0x64, 0x13, 0x51, 0x02, 0x49, 0x38,
0x62, 0xA9, 0x40, 0x41, 0x15, 0x09, 0xAA, 0x01, 0x75, 0x12, 0x12, 0x55,
0x4D, 0x44, 0x55, 0x6D, 0x01, 0x08, 0x14, 0x14, 0x50, 0x13, 0x08, 0x44,
0x36, 0x87, 0xEB, 0x02, 0xB6, 0x94, 0x9A, 0x2A, 0x82, 0x5F, 0x97, 0xC4,
0xD4, 0x75, 0x54, 0x29, 0x28, 0x34, 0x25, 0x3C, 0x46, 0x94, 0xBF, 0x00,
0x21, 0xF8, 0x49, 0xA5, 0x60, 0x6A, 0x3E, 0x08, 0x22, 0x97, 0x64, 0x2D,
0x3E, 0x15, 0x98, 0x41, 0x43, 0xFA, 0x50, 0xB5, 0x45, 0x08, 0x42, 0xC4,
0xA0, 0x24, 0x97, 0x6C, 0x50, 0x92, 0xEB, 0x14, 0x51, 0x51, 0x6A, 0x87,
0xEF, 0xDF, 0xBF, 0xA4, 0x87, 0x61, 0xF2, 0x09, 0x14, 0x21, 0x30, 0x28,
0x49, 0x49, 0x49, 0x0B, 0x39, 0x60, 0x90, 0x87, 0xC5, 0xA5, 0x30, 0x09,
0x22, 0x8A, 0x92, 0x92, 0x16, 0xA8, 0xA6, 0x97, 0xF5, 0x69, 0xA5, 0x20,
0x90, 0xEB, 0x9A, 0x8D, 0xAB, 0x41, 0xA4, 0x22, 0x25, 0x05, 0xFA, 0x42,
0x02, 0x49, 0x34, 0x18, 0x08, 0x14, 0x26, 0x95, 0x80, 0xAA, 0x99, 0x34,
0x80, 0x84, 0x20, 0x25, 0x30, 0x0A, 0xDB, 0xE4, 0x1A, 0xA0, 0x19, 0x65,
0x38, 0x44, 0x45, 0x18, 0x70, 0x94, 0x94, 0x92, 0xD2, 0xFC, 0x52, 0x52,
0x45, 0x25, 0xA0, 0x61, 0xC1, 0x4A, 0xC0, 0x94, 0x95, 0x88, 0x0D, 0x48,
0x9E, 0x27, 0xC9, 0xA6, 0x29, 0x28, 0x42, 0x0B, 0xF2, 0x2A, 0xD5, 0x4D,
0x09, 0x4D, 0x51, 0x35, 0x13, 0x48, 0x58, 0x3E, 0x5A, 0x9A, 0x02, 0x56,
0x34, 0x82, 0xFD, 0xD8, 0xA1, 0xF4, 0x84, 0x2D, 0xD3, 0x43, 0xEA, 0x13,
0x4A, 0x28, 0x11, 0x05, 0x00, 0xC5, 0x29, 0xA4, 0x80, 0xB3, 0xA8, 0x41,
0x19, 0x62, 0x05, 0x08, 0x63, 0x49, 0xA8, 0x0D, 0x3E, 0x7E, 0x12, 0x68,
0x14, 0x52, 0x98, 0x29, 0x18, 0x65, 0x26, 0x96, 0x20, 0x55, 0x35, 0x30,
0xCC, 0xD5, 0x11, 0xA2, 0x60, 0x99, 0x26, 0x6A, 0x96, 0x96, 0x54, 0x08,
0x0F, 0x04, 0xDE, 0xCD, 0x56, 0xBA, 0x92, 0xA5, 0x54, 0xA9, 0x4A, 0xCA,
0xC0, 0x97, 0x44, 0xA4, 0xEA, 0x64, 0xED, 0x8D, 0x90, 0xAB, 0x24, 0x82,
0x0A, 0x90, 0xD2, 0x71, 0xDE, 0x0B, 0x08, 0x99, 0xDB, 0x6C, 0xC9, 0xD8,
0x04, 0x90, 0x37, 0xB6, 0x95, 0x76, 0x4D, 0x90, 0xD6, 0xEC, 0x90, 0x00,
0xDC, 0x32, 0x77, 0xA2, 0x64, 0x92, 0x65, 0xBA, 0xD0, 0x6C, 0xEC, 0x1D,
0x34, 0xB4, 0xCC, 0x00, 0x84, 0x09, 0x24, 0x12, 0x49, 0x95, 0x10, 0x80,
0x22, 0xA1, 0xE9, 0x61, 0x86, 0x49, 0x49, 0x80, 0x16, 0xAA, 0x7F, 0xD3,
0x56, 0x10, 0x93, 0x51, 0x60, 0xF8, 0x21, 0x09, 0xA1, 0x34, 0xA4, 0xA6,
0x9A, 0x8F, 0xAA, 0x19, 0x28, 0x08, 0x82, 0x4A, 0x45, 0xB2, 0x03, 0x48,
0x45, 0x64, 0x28, 0x48, 0x14, 0x04, 0xAC, 0x52, 0x91, 0x4A, 0x1D, 0x88,
0x09, 0x34, 0x02, 0xB1, 0x49, 0x34, 0x50, 0x42, 0x69, 0x14, 0x00, 0x00,
0x00, 0x00, 0x82, 0x00, 0x00, 0x08, 0x5D, 0x04, 0x50, 0x14, 0x00, 0x00,
0x73, 0x01, 0x01, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x08, 0xCF, 0x05, 0x00,
0x00, 0xAD, 0x16, 0x00, 0x00, 0xE7, 0xC0, 0x2A, 0x85, 0x69, 0x2B, 0x10,
0x1D, 0x90, 0x12, 0x00, 0x40, 0x24, 0x2C, 0x52, 0x00, 0x04, 0x12, 0x8C,
0x2A, 0xA7, 0x0D, 0x08, 0xA0, 0x52, 0x4B, 0x69, 0x32, 0x1F, 0x1A, 0xA4,
0x53, 0x54, 0x80, 0xEC, 0xA6, 0xA3, 0xE4, 0x08, 0x49, 0x28, 0x90, 0x02,
0x5F, 0xBF, 0xA8, 0x09, 0x14, 0xD4, 0x05, 0x08, 0x4A, 0x6A, 0x26, 0xA1,
0x45, 0x28, 0x4D, 0x41, 0x41, 0x14, 0x1A, 0x94, 0x30, 0xA2, 0x13, 0x4D,
0x25, 0xD9, 0x7D, 0x06, 0x90, 0x4D, 0x54, 0x24, 0x19, 0x0B, 0x00, 0x88,
0xA0, 0x55, 0x12, 0x1A, 0x16, 0x09, 0x42, 0x04, 0x61, 0xEC, 0x02, 0x21,
0x0C, 0x28, 0x25, 0x09, 0x05, 0x28, 0xA0, 0x04, 0x03, 0x55, 0x24, 0x07,
0xE4, 0x83, 0x25, 0x22, 0xAD, 0x31, 0x08, 0xA0, 0x21, 0x60, 0x80, 0x80,
0x97, 0xC9, 0x58, 0x52, 0x11, 0x44, 0x1A, 0x12, 0x85, 0xB4, 0xA1, 0xF2,
0x69, 0xA0, 0xBF, 0x41, 0x48, 0x15, 0x68, 0x40, 0xA4, 0xA5, 0x2F, 0xCA,
0x69, 0x21, 0x60, 0x9C, 0x3C, 0x30, 0x93, 0x52, 0x60, 0x84, 0x13, 0x09,
0x4D, 0x44, 0xA4, 0x02, 0xB1, 0xA0, 0x54, 0x80, 0x10, 0x29, 0xA8, 0x08,
0x29, 0x35, 0x0A, 0x69, 0x4C, 0x13, 0x41, 0x08, 0x8A, 0x82, 0x83, 0x0C,
0x43, 0xA9, 0x38, 0x65, 0x0C, 0xD9, 0x50, 0x92, 0x24, 0x1A, 0xA8, 0x84,
0x19, 0x40, 0x44, 0x10, 0x91, 0xA3, 0x05, 0xE0, 0x35, 0x7E, 0x7A, 0xD4,
0xB5, 0x14, 0xAA, 0xAC, 0xAC, 0x42, 0x6A, 0x95, 0xB7, 0xF0, 0x0C, 0x49,
0x6C, 0x2A, 0xDD, 0x16, 0xC6, 0xAC, 0x35, 0xA1, 0x7C, 0x43, 0x2E, 0x0D,
0xFF, 0xE3, 0x95, 0x76, 0x76, 0x76, 0x55, 0x54, 0x11, 0x56, 0x18, 0xC9,
0x61, 0x80, 0x64, 0x4E, 0xB4, 0xD8, 0x82, 0xC1, 0x30, 0x21, 0x37, 0xC1,
0x54, 0x48, 0x04, 0xB0, 0xA5, 0x04, 0xCA, 0x06, 0x8B, 0xA9, 0x34, 0x10,
0x95, 0x82, 0x69, 0x43, 0x52, 0x41, 0x24, 0xB0, 0x49, 0x06, 0x40, 0x24,
0x00, 0x00, 0x24, 0x40, 0x10, 0x84, 0xD2, 0x56, 0xCA, 0x12, 0x56, 0x05,
0x00, 0x84, 0x10, 0x82, 0xFC, 0xAC, 0x16, 0xA9, 0x32, 0x9A, 0x49, 0x3C,
0x56, 0xF2, 0x11, 0x42, 0xC2, 0x94, 0xA3, 0x08, 0xD2, 0x8A, 0x0D, 0x22,
0x84, 0xA2, 0x13, 0x08, 0x7E, 0x09, 0x4C, 0xD0, 0x50, 0x16, 0x7D, 0x24,
0x13, 0x55, 0x09, 0x82, 0x4B, 0x24, 0x15, 0x82, 0xD9, 0x58, 0x3B, 0x29,
0x90, 0xEC, 0xA5, 0x8F, 0x8B, 0xF0, 0xB0, 0x14, 0xA0, 0x22, 0xA2, 0x42,
0xD5, 0x28, 0x44, 0x54, 0x41, 0x01, 0xF0, 0xA5, 0x08, 0xAC, 0xC9, 0x41,
0x08, 0x82, 0x97, 0x66, 0x87, 0xEF, 0x85, 0x21, 0x11, 0x4C, 0x52, 0x28,
0x5B, 0x06, 0x94, 0x03, 0x47, 0x18, 0x7E, 0x5F, 0x14, 0x3F, 0x7C, 0x0B,
0x02, 0xC5, 0xF5, 0x14, 0x85, 0x85, 0x4A, 0x1B, 0x51, 0x0B, 0x10, 0x84,
0x84, 0xA1, 0xA4, 0x8A, 0x09, 0x22, 0x21, 0xFF, 0x1C, 0x44, 0x52, 0x92,
0x50, 0x93, 0x84, 0x04, 0x50, 0x49, 0x33, 0x50, 0x94, 0x9A, 0x2A, 0x3B,
0x30, 0x13, 0x57, 0x49, 0x42, 0x6A, 0xD3, 0x28, 0x40, 0x08, 0x4E, 0x46,
0xA0, 0x2D, 0x19, 0x29, 0x41, 0x7C, 0x80, 0x02, 0xC2, 0x11, 0x28, 0x45,
0x2F, 0x8D, 0x08, 0x38, 0x66, 0x11, 0x48, 0x41, 0x0B, 0x66, 0xA2, 0x08,
0xA9, 0x24, 0x26, 0x01, 0xA5, 0x09, 0x41, 0x4A, 0x08, 0x95, 0x8D, 0x05,
0x18, 0x46, 0xB2, 0xA6, 0xA8, 0x8D, 0x14, 0xAC, 0x0C, 0x55, 0x06, 0x5A,
0x4A, 0x36, 0x0C, 0x6F, 0x6F, 0x92, 0x04, 0xB4, 0x55, 0x30, 0x93, 0x0C,
0x45, 0x2C, 0xDA, 0x5D, 0x9A, 0x95, 0x10, 0xFE, 0x6A, 0x55, 0x40, 0xD9,
0x17, 0x20, 0x55, 0x46, 0xEE, 0x04, 0x30, 0xA4, 0x12, 0xD5, 0xE6, 0x5E,
0x35, 0x5E, 0x7C, 0xEA, 0xE2, 0x85, 0x2A, 0xB3, 0x2A, 0x09, 0x65, 0xFA,
0xDA, 0x07, 0xFC, 0x72, 0x63, 0x35, 0x72, 0x96, 0x43, 0x0B, 0x15, 0x05,
0xAC, 0x2C, 0x95, 0x0E, 0xF4, 0x58, 0xC9, 0x17, 0x10, 0xCD, 0x25, 0x4C,
0x84, 0x85, 0x57, 0x18, 0x31, 0x0A, 0xA0, 0x86, 0x83, 0x24, 0x41, 0x04,
0x2A, 0x08, 0x68, 0x2D, 0x07, 0x08, 0xCD, 0x43, 0x12, 0x00, 0x8B, 0xAA,
0x44, 0xBF, 0x80, 0x1D, 0x74, 0x24, 0x14, 0x4C, 0xC1, 0x42, 0x0D, 0x00,
0x3F, 0x44, 0xB6, 0x51, 0x4A, 0x50, 0x90, 0xC8, 0xD9, 0xA4, 0x8D, 0x02,
0x94, 0x12, 0x8A, 0x41, 0x5A, 0x09, 0x5A, 0x7C, 0xB0, 0x7F, 0x36, 0xEA,
0x1F, 0xBE, 0xE3, 0x14, 0xBE, 0x41, 0x41, 0x42, 0xDA, 0x12, 0x2D, 0x90,
0x0A, 0x12, 0x54, 0x09, 0x08, 0xA5, 0x2D, 0xA2, 0x2A, 0x94, 0x6C, 0x1C,
0x32, 0xB1, 0x34, 0x2C, 0x68, 0x28, 0x48, 0xAA, 0xC0, 0x56, 0x25, 0x12,
0xFA, 0x9D, 0x20, 0x4A, 0x29, 0x42, 0x4A, 0x02, 0x52, 0x12, 0x69, 0x41,
0xC8, 0xCF, 0xC1, 0x76, 0xD4, 0xD5, 0x0F, 0xCA, 0x27, 0x08, 0x55, 0xA0,
0x90, 0x91, 0x34, 0x00, 0x53, 0x14, 0x86, 0x84, 0x27, 0x6D, 0x24, 0x24,
0x13, 0x41, 0x28, 0x35, 0x51, 0x4D, 0x06, 0xA2, 0x54, 0x00, 0x12, 0x0A,
0x2A, 0x2C, 0x50, 0xC9, 0xA2, 0x95, 0x9E, 0xB0, 0x41, 0x28, 0x9A, 0x29,
0x08, 0x4A, 0x6A, 0x0A, 0x4A, 0x28, 0x28, 0x14, 0xA4, 0x37, 0x42, 0x90,
0x97, 0xF4, 0x20, 0x40, 0x84, 0x92, 0x50, 0x6A, 0x26, 0x87, 0xEF, 0xA9,
0x09, 0x44, 0x51, 0x4D, 0x54, 0xA2, 0xB3, 0xA1, 0x28, 0xA4, 0x20, 0x30,
0xA0, 0x25, 0x00, 0xC1, 0x97, 0xC9, 0x44, 0x94, 0x03, 0x09, 0x46, 0xDF,
0x3F, 0xA8, 0x41, 0x46, 0xA9, 0x0D, 0xCB, 0x17, 0x55, 0x21, 0x28, 0x24,
0x55, 0x31, 0x20, 0xA1, 0x21, 0x20, 0x25, 0x50, 0x4A, 0x13, 0x50, 0xC2,
0x42, 0x68, 0x32, 0x43, 0x2A, 0x89, 0x41, 0x91, 0x87, 0x42, 0x40, 0x25,
0x10, 0x29, 0x35, 0x21, 0x32, 0x21, 0x35, 0x12, 0x0A, 0x12, 0x82, 0x20,
0xBA, 0x93, 0x20, 0x26, 0x42, 0xA8, 0x21, 0x83, 0x09, 0x20, 0x83, 0x02,
0x4B, 0x36, 0x95, 0x83, 0x41, 0x01, 0x35, 0x21, 0xE3, 0x51, 0xCF, 0x6D,
0x15, 0x69, 0x4C, 0x37, 0x95, 0xA9, 0x52, 0x5D, 0x00, 0xD0, 0xAA, 0x24,
0x62, 0x3D, 0x8B, 0xC6, 0x9B, 0x0A, 0x01, 0x00, 0x1B, 0xB7, 0xD4, 0x29,
0x65, 0x5D, 0x16, 0x5F, 0x1B, 0x96, 0x86, 0x1B, 0xB4, 0x58, 0x62, 0x0B,
0x08, 0xDC, 0x10, 0xAA, 0xE3, 0xA6, 0x88, 0x52, 0x36, 0xC0, 0x44, 0xAA,
0x24, 0x36, 0x0C, 0x16, 0x89, 0xD5, 0x20, 0x6C, 0x10, 0x48, 0x12, 0x0D,
0x44, 0xA2, 0x20, 0x11, 0x24, 0x20, 0xC6, 0x12, 0x51, 0x48, 0x98, 0x0C,
0x15, 0x50, 0x13, 0x47, 0x1D, 0x64, 0x90, 0x97, 0xC9, 0x2F, 0x93, 0x34,
0x3F, 0x7C, 0xB6, 0xF9, 0x2E, 0xB0, 0x64, 0x4D, 0x08, 0x5B, 0xC2, 0x49,
0x7C, 0x92, 0x42, 0x24, 0xB1, 0x22, 0x2A, 0x88, 0x4D, 0x14, 0xA0, 0xA0,
0x89, 0x30, 0x64, 0x11, 0x1A, 0x4C, 0x24, 0x02, 0x0A, 0xF1, 0x21, 0x84,
0x31, 0x30, 0x60, 0xDF, 0x09, 0xA2, 0x91, 0x28, 0x4A, 0x13, 0x45, 0x28,
0x21, 0x22, 0x0C, 0x0A, 0xA8, 0xCB, 0x18, 0x8F, 0xFA, 0x0C, 0x84, 0xA0,
0xC1, 0x83, 0x20, 0x9D, 0x04, 0x83, 0x3A, 0x2D, 0x6C, 0x25, 0x05, 0x89,
0x41, 0x41, 0x42, 0x51, 0x04, 0x10, 0x9A, 0x12, 0x19, 0x4B, 0xE4, 0x80,
0x90, 0x54, 0x30, 0x4B, 0xAA, 0x94, 0x36, 0x08, 0x4C, 0x55, 0x44, 0xB6,
0x29, 0x44, 0x12, 0x24, 0x41, 0x64, 0x26, 0x0B, 0x4E, 0x5D, 0x05, 0x09,
0x01, 0x21, 0x22, 0x94, 0x41, 0x9A, 0x85, 0xA0, 0xC1, 0x82, 0x34, 0x71,
0x73, 0x07, 0x44, 0x1B, 0x04, 0x18, 0x36, 0x58, 0x42, 0x50, 0x43, 0x44,
0x18, 0x32, 0x26, 0x58, 0x54, 0xDA, 0x08, 0x68, 0x31, 0x32, 0x08, 0x22,
0xA8, 0x95, 0x26, 0x41, 0x55, 0x14, 0xA0, 0x82, 0x34, 0x58, 0x44, 0xE8,
0x89, 0x06, 0x08, 0x20, 0x81, 0x4B, 0xC7, 0x9B, 0xBF, 0x6E, 0x2E, 0x54,
0x44, 0x55, 0x66, 0x35, 0x71, 0x26, 0xFD, 0xB8, 0xB9, 0x51, 0x11, 0x55,
0x98, 0xD5, 0xC4, 0x9F, 0xAC, 0xF6, 0x5B, 0x4D, 0x53, 0x25, 0x98, 0xA3,
0x41, 0x46, 0x10, 0x44, 0xB0, 0x10, 0x60, 0xAA, 0x08, 0x10, 0xC6, 0x18,
0x99, 0x6D, 0xD0, 0xA8, 0x88, 0xE8, 0x46, 0x94, 0xB8, 0xAE, 0xDB, 0x55,
0x07, 0xE7, 0xB3, 0x41, 0xD8, 0x64, 0x8D, 0xC8, 0x61, 0x0C, 0x20, 0x83,
0x20, 0xC1, 0x42, 0x50, 0x90, 0x41, 0x6E, 0xC2, 0x84, 0x32, 0x5A, 0x8A,
0x68, 0xA6, 0x84, 0xA1, 0x22, 0x68, 0xA5, 0x12, 0x0A, 0x0D, 0x4A, 0x50,
0x41, 0x07, 0x52, 0x25, 0x06, 0xA2, 0x50, 0x94, 0x55, 0x42, 0x42, 0x50,
0x94, 0x25, 0x09, 0x04, 0x16, 0x83, 0x04, 0x07, 0xFC, 0x4F, 0xC4, 0x83,
0x28, 0xA6, 0x84, 0xC4, 0x83, 0x30, 0x54, 0x04, 0x48, 0x4A, 0x12, 0x0A,
0x08, 0x61, 0xC6, 0xD7, 0x1D, 0x71, 0x04, 0x24, 0x16, 0xDD, 0x1D, 0x30,
0xC7, 0x23, 0xA7, 0x52, 0x41, 0xD8, 0xD6, 0x8F, 0x47, 0x60, 0xE8, 0x8B,
0xC2, 0x44, 0x82, 0x20, 0x8D, 0x85, 0x45, 0xC4, 0x19, 0x0A, 0x89, 0x05,
0xA0, 0xB0, 0x83, 0x2D, 0x5E, 0x24, 0x24, 0x19, 0x04, 0x28, 0x41, 0x6C,
0x48, 0x3A, 0x28, 0x3B, 0x06, 0x0A, 0x85, 0xC7, 0x72, 0x2D, 0x04, 0x2F,
0x6B, 0x42, 0xBA, 0x73, 0x5D, 0xBC, 0x55, 0xE2, 0xD0, 0x41, 0xCC, 0x20,
0x83, 0x7E, 0xAC, 0x10, 0x41, 0x50, 0xBC, 0x13, 0x6B, 0x3C, 0xCE, 0xFE,
0x3A, 0xD4, 0x10, 0x88, 0x48, 0x15, 0xDF, 0xC7, 0x5A, 0x82, 0x11, 0x09,
0x02, 0xBF, 0x9F, 0xF0, 0x87, 0x9B, 0x09, 0x43, 0x45, 0xDB, 0x16, 0x4B,
0x6F, 0x37, 0x61, 0xA2, 0x48, 0x96, 0x84, 0x95, 0x20, 0xC6, 0xA0, 0x83,
0x86, 0xEA, 0x88, 0x00, 0xF5, 0xA6, 0x40, 0x56, 0x55, 0x98, 0x51, 0x51,
0x3A, 0xCB, 0xB5, 0x7A, 0xBE, 0xEA, 0xEF, 0x78, 0x94, 0xD9, 0xE4, 0xA7,
0x5D, 0x9D, 0x62, 0x33, 0x0B, 0x97, 0xFD, 0x1A, 0xD2, 0x31, 0xAF, 0x82,
0xC3, 0x0C, 0x21, 0x50, 0x18, 0x1D, 0xAF, 0xF3, 0x37, 0x4E, 0x3F, 0xB8,
0xAE, 0xA2, 0xDA, 0x3F, 0x9B, 0x5A, 0x75, 0xE7, 0xAE, 0x3C, 0x13, 0x75,
0x67, 0x93, 0xBF, 0xAE, 0x2E, 0x90, 0x49, 0x52, 0x24, 0x0A, 0xDF, 0xD7,
0x17, 0x48, 0x24, 0xA9, 0x12, 0x05, 0x67, 0xB0, 0x7F, 0x44, 0x35, 0x33,
0x17, 0x80, 0xC8, 0x00, 0x5E, 0xD4, 0x24, 0xDF, 0x28, 0x58, 0xB4, 0xB0,
0x21, 0x53, 0xDC, 0xC0, 0x44, 0x48, 0x61, 0x90, 0x52, 0xBC, 0x9A, 0x8C,
0x66, 0x58, 0x1D, 0xAA, 0x2E, 0xDD, 0xD1, 0xDC, 0xEC, 0x10, 0xA1, 0xDC,
0x96, 0xC1, 0x96, 0x30, 0x82, 0x0C, 0xB4, 0x2B, 0x16, 0x0E, 0xA1, 0x58,
0x96, 0x8C, 0x6C, 0xEF, 0x4E, 0x76, 0x7F, 0x1C, 0xA9, 0x66, 0xC8, 0x1B,
0x5D, 0x8F, 0x1A, 0xCA, 0xBA, 0x6B, 0x56, 0xF3, 0x7B, 0xAF, 0x72, 0xBB,
0xEA, 0xCD, 0x78, 0x08, 0x04, 0xB1, 0x56, 0xB7, 0xB4, 0x70, 0x0A, 0x12,
0xD9, 0x11, 0x67, 0x8D, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, 0x08,
0x5D, 0x04, 0xC4, 0x15, 0x00, 0x00, 0x73, 0x01, 0x01, 0x10, 0x00, 0x00,
0x00, 0x00, 0x08, 0xCF, 0x05, 0x00, 0x00, 0xF2, 0x17, 0x00, 0x00, 0xF7,
0x91, 0xCB, 0xEA, 0x5D, 0x2C, 0x44, 0x8C, 0x97, 0x05, 0x57, 0xD4, 0xBA,
0x58, 0x89, 0x19, 0x2E, 0x0A, 0x1C, 0x48, 0x08, 0x9A, 0xB2, 0x89, 0x48,
0x82, 0x2A, 0x52, 0x62, 0xA1, 0x15, 0x63, 0x42, 0x94, 0x8D, 0x10, 0x6A,
0x52, 0xD2, 0x76, 0x6C, 0xE8, 0x55, 0x04, 0x61, 0x30, 0xEF, 0x08, 0x5F,
0x32, 0x08, 0x66, 0xCB, 0x48, 0x44, 0xC0, 0x91, 0x3B, 0x21, 0x96, 0x2E,
0x2D, 0xFA, 0xD3, 0xAB, 0x04, 0x59, 0x50, 0xAF, 0xDA, 0xAB, 0x98, 0xCB,
0x1B, 0x86, 0x93, 0x12, 0xC6, 0x98, 0x44, 0x89, 0xA9, 0x31, 0xA9, 0x02,
0x5B, 0x12, 0x44, 0x84, 0x12, 0x07, 0x44, 0xAE, 0x5C, 0x37, 0x06, 0x7F,
0x15, 0xBD, 0x65, 0x51, 0x73, 0xB5, 0xF3, 0x73, 0x79, 0x2F, 0xC8, 0x87,
0xF5, 0x77, 0xA7, 0xF4, 0xDF, 0xFF, 0x20, 0x0F, 0xAF, 0x1D, 0x2A, 0xC8,
0x50, 0x29, 0xBD, 0xCB, 0x64, 0x0D, 0xF3, 0x88, 0x92, 0x84, 0xC5, 0x82,
0x96, 0x26, 0x21, 0x88, 0x7F, 0xB1, 0x2C, 0x91, 0x30, 0x48, 0x78, 0x25,
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0x86, 0xF4, 0x9B, 0x4D, 0x73, 0x91, 0x62, 0x0B, 0x8B, 0x89, 0x0D, 0x09,
0x0F, 0xAF, 0xA9, 0xB7, 0xDB, 0x3C, 0x4E, 0x3A, 0xB4, 0xDE, 0x35, 0x52,
0xB2, 0x31, 0xAE, 0xAE, 0x2B, 0x8E, 0xAD, 0x37, 0x8D, 0x54, 0xAC, 0x8C,
0x6B, 0xAB, 0x8A, 0x4E, 0x6A, 0x12, 0x00, 0x30, 0x4A, 0x8C, 0x3A, 0x00,
0x05, 0x4F, 0x40, 0xA5, 0x2C, 0x29, 0xA5, 0x25, 0x48, 0x92, 0x53, 0x4D,
0x29, 0x20, 0x0B, 0x0C, 0x01, 0x08, 0x44, 0xEB, 0x72, 0x58, 0x04, 0x42,
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0x4A, 0x4A, 0x52, 0x92, 0x11, 0x43, 0xEA, 0x10, 0x15, 0x64, 0x3B, 0xF6,
0x61, 0x00, 0x68, 0x21, 0x08, 0x01, 0xAA, 0xA4, 0x81, 0x3A, 0x00, 0x21,
0x02, 0xA9, 0x14, 0x22, 0x6A, 0x22, 0x8A, 0x28, 0xA2, 0x8A, 0x28, 0x44,
0x92, 0x97, 0xEF, 0xD3, 0x87, 0x4D, 0x29, 0x4D, 0x34, 0xBF, 0x49, 0x00,
0x00, 0x8A, 0x04, 0x22, 0x87, 0xD4, 0x50, 0xFA, 0x8A, 0x10, 0x2A, 0xD3,
0x4A, 0x49, 0x89, 0x24, 0x92, 0x93, 0x01, 0x08, 0x40, 0x29, 0x49, 0x8B,
0x3B, 0x24, 0xEC, 0x96, 0x9F, 0x60, 0x00, 0x6A, 0xAB, 0xC9, 0x5E, 0xE2,
0x50, 0x7A, 0xBD, 0xC0, 0x79, 0xE0, 0x3C, 0xCC, 0x2E, 0x71, 0x20, 0x36,
0xDB, 0xEF, 0x5B, 0x64, 0x7F, 0x96, 0xD8, 0x84, 0x61, 0x4A, 0xC5, 0x4F,
0x03, 0x10, 0xDF, 0xE2, 0x43, 0x61, 0x95, 0x21, 0xBB, 0x3C, 0xBF, 0x6D,
0x65, 0xF3, 0x7D, 0xC9, 0x2A, 0xF7, 0x53, 0x1C, 0x71, 0x35, 0x75, 0xED,
0xAC, 0xBE, 0x6F, 0xB9, 0x25, 0x5E, 0xEA, 0x63, 0x8E, 0x26, 0xAE, 0x93,
0x9F, 0x49, 0x2D, 0xC1, 0x84, 0xAE, 0x5C, 0x4A, 0x5F, 0x14, 0x20, 0x6D,
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0x96, 0x44, 0x1A, 0x88, 0x32, 0x11, 0x4B, 0xFA, 0x52, 0x9D, 0xB1, 0xBA,
0x72, 0x25, 0x21, 0x15, 0x04, 0x49, 0x88, 0x68, 0x69, 0x18, 0xAA, 0x45,
0x38, 0x4C, 0x4B, 0x6A, 0x04, 0x1A, 0xB2, 0xB4, 0xB1, 0x5B, 0x4A, 0x0D,
0x08, 0x2F, 0x90, 0x92, 0x94, 0x91, 0x59, 0xA4, 0x22, 0xAC, 0xD4, 0x48,
0xA0, 0x44, 0x22, 0x8A, 0x03, 0xF3, 0x51, 0x89, 0x41, 0xA4, 0x82, 0xC2,
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0xD9, 0x49, 0xBE, 0x00, 0x9E, 0xAC, 0x68, 0x5C, 0x04, 0x34, 0x97, 0x7B,
0x82, 0xDB, 0x2F, 0x8F, 0xB9, 0x54, 0xF8, 0xF5, 0xE7, 0x99, 0x83, 0xD3,
0x94, 0x9A, 0x42, 0xA7, 0x8E, 0xB1, 0xB6, 0xE9, 0xA4, 0x98, 0xFA, 0xDB,
0x39, 0x74, 0x45, 0x92, 0x8C, 0x92, 0x2A, 0xE7, 0x38, 0xB2, 0xD8, 0x67,
0xDE, 0xBD, 0x9B, 0x17, 0x22, 0x44, 0x43, 0x6D, 0xBC, 0x22, 0x5B, 0x6D,
0xC5, 0x8B, 0x17, 0xAE, 0x12, 0x12, 0xA9, 0x55, 0xFB, 0x6C, 0x4B, 0x88,
0x6F, 0xBD, 0x6C, 0x84, 0xAC, 0xF4, 0x3E, 0x35, 0xBB, 0xF1, 0xC7, 0x8E,
0x39, 0x5C, 0xCC, 0x99, 0x35, 0xD5, 0x6A, 0xE7, 0xC6, 0xB7, 0x7E, 0x38,
0xF1, 0xC7, 0x2B, 0x99, 0x93, 0x26, 0xBA, 0xAD, 0x5C, 0x2E, 0xE2, 0x2B,
0xC6, 0x84, 0x0C, 0xC0, 0x50, 0xB1, 0x81, 0xD2, 0xA2, 0x42, 0xC6, 0x8A,
0x10, 0x38, 0x50, 0x52, 0x98, 0x72, 0x28, 0x24, 0x4A, 0x4C, 0x07, 0x22,
0xC9, 0xDD, 0x94, 0x10, 0x0A, 0x6A, 0x00, 0xD0, 0xA2, 0x5F, 0x24, 0xA2,
0x94, 0xD4, 0x05, 0x27, 0x26, 0x71, 0x11, 0x31, 0x2C, 0x0E, 0x55, 0x48,
0x9A, 0x69, 0x4A, 0xF4, 0x26, 0x12, 0x40, 0x4A, 0x50, 0xB4, 0xB4, 0xFB,
0x0D, 0x44, 0xA1, 0x24, 0x02, 0x61, 0x2F, 0xDF, 0xD2, 0xC1, 0x05, 0xB0,
0x60, 0x18, 0xA1, 0x00, 0x4B, 0x41, 0x82, 0xC2, 0x76, 0x4B, 0x39, 0x2F,
0x74, 0xC0, 0xC8, 0x89, 0x4D, 0x34, 0xEB, 0x22, 0xB2, 0x67, 0xE5, 0x8A,
0xB2, 0x7D, 0x2E, 0x90, 0x90, 0x18, 0xE6, 0xC1, 0x35, 0xFA, 0xC1, 0x92,
0xE1, 0xF2, 0x3D, 0xA0, 0x4E, 0x31, 0x2D, 0xE8, 0x6B, 0xA5, 0x08, 0xE0,
0x62, 0x48, 0xA9, 0x89, 0xB6, 0x68, 0x3A, 0x0B, 0x16, 0xA1, 0x14, 0x94,
0x69, 0x44, 0x43, 0xA9, 0xBD, 0x2D, 0x3E, 0x3E, 0x94, 0x14, 0xC5, 0xEB,
0x16, 0xA2, 0x7B, 0xDE, 0xB1, 0x08, 0x3B, 0x75, 0xA4, 0xCA, 0x22, 0x69,
0x70, 0x65, 0x84, 0x9B, 0x49, 0xC5, 0xE9, 0x47, 0x0F, 0xB4, 0x16, 0xE9,
0x77, 0xAB, 0x91, 0x62, 0xCB, 0xD6, 0x92, 0x0B, 0x47, 0xD5, 0xD8, 0x9D,
0x0A, 0xF1, 0x90, 0x34, 0x49, 0x1A, 0x7A, 0x4F, 0xA9, 0x37, 0xC7, 0x34,
0x4A, 0x2C, 0x40, 0xB5, 0x26, 0x43, 0x4D, 0x59, 0xEA, 0x7D, 0x5F, 0x7C,
0x77, 0x7D, 0xEB, 0x72, 0x37, 0x2B, 0x73, 0x8E, 0x92, 0xEF, 0xEA, 0xFB,
0xE3, 0xBB, 0xEF, 0x5B, 0x91, 0xB9, 0x5B, 0x9C, 0x74, 0x97, 0x67, 0x24,
0x72, 0x55, 0x6B, 0xE8, 0xA6, 0x04, 0xFB, 0x20, 0xD2, 0x9E, 0x14, 0x25,
0x01, 0x34, 0xA4, 0xF0, 0x11, 0x55, 0x24, 0x97, 0x30, 0x40, 0x49, 0x32,
0xE4, 0x68, 0x35, 0x18, 0x80, 0x52, 0x60, 0xA8, 0x45, 0x28, 0x90, 0xD7,
0x30, 0x91, 0x20, 0x55, 0x3F, 0x12, 0x0B, 0x61, 0x41, 0x64, 0x12, 0x30,
0x82, 0x69, 0x4E, 0xC9, 0x11, 0x06, 0x0C, 0x24, 0xA1, 0x15, 0x52, 0x92,
0x4E, 0x88, 0x20, 0x18, 0x90, 0x81, 0x24, 0x96, 0x41, 0x05, 0x49, 0x81,
0x33, 0x3A, 0x3A, 0xF1, 0x09, 0xAF, 0x70, 0x1B, 0x83, 0x7C, 0xA6, 0xBC,
0x49, 0x99, 0x8F, 0xB0, 0xD3, 0x79, 0xB2, 0x61, 0xBB, 0x82, 0x49, 0x89,
0x6A, 0x40, 0x08, 0x32, 0xDA, 0xC3, 0xB3, 0x69, 0xE5, 0xB9, 0x79, 0x19,
0x0B, 0x07, 0x67, 0x33, 0xFA, 0xAC, 0xDB, 0xDB, 0x7A, 0x54, 0x49, 0x1D,
0x3E, 0x3E, 0xB6, 0x6A, 0x9A, 0x29, 0x63, 0x2A, 0x79, 0x67, 0xA8, 0xA4,
0x48, 0xA9, 0x34, 0x52, 0xD7, 0x22, 0x2F, 0x9E, 0x58, 0x89, 0x6C, 0xD1,
0x94, 0x0C, 0x49, 0x24, 0x5C, 0x4D, 0x32, 0x81, 0x89, 0x24, 0xAB, 0x5D,
0x89, 0x15, 0x0F, 0x9C, 0xEC, 0xF6, 0x2F, 0x27, 0x9A, 0x51, 0x38, 0x3C,
0x39, 0xE4, 0x83, 0x37, 0x9B, 0x89, 0xDD, 0x38, 0x91, 0x22, 0xCF, 0x5D,
0x9E, 0xBF, 0xD5, 0xF3, 0x7E, 0xB5, 0xDF, 0x19, 0xAD, 0xCA, 0xE7, 0x5C,
0xEB, 0x8E, 0x2A, 0xE6, 0xBE, 0xAF, 0x9B, 0xF5, 0xAE, 0xF8, 0xCD, 0x6E,
0x57, 0x3A, 0xE7, 0x5C, 0x71, 0x57, 0x34, 0x7C, 0x84, 0xE4, 0xE8, 0x29,
0xAF, 0x26, 0x89, 0x70, 0x82, 0x29, 0xF4, 0x52, 0x92, 0xE0, 0x22, 0xAA,
0x4F, 0x01, 0x04, 0x20, 0xA4, 0xE2, 0x90, 0x41, 0x58, 0x2D, 0xBA, 0x02,
0xD2, 0x00, 0x73, 0xAD, 0x88, 0xAB, 0x03, 0xD8, 0x8A, 0xA7, 0x85, 0x09,
0x42, 0x4B, 0xE4, 0x26, 0x94, 0x9D, 0xA8, 0x41, 0x75, 0x82, 0x50, 0x84,
0x0C, 0xD0, 0x40, 0x49, 0xFA, 0x08, 0xD1, 0x89, 0x25, 0xC4, 0x69, 0xEB,
0xDD, 0xAA, 0x2A, 0xA7, 0x6D, 0x9D, 0x9D, 0xB0, 0xC1, 0x6C, 0x37, 0x6D,
0x1A, 0x30, 0x4C, 0xB3, 0xA5, 0xC5, 0xAA, 0x40, 0xAF, 0xEA, 0xBF, 0x93,
0xDD, 0x7E, 0x1A, 0x7E, 0xED, 0xB7, 0x43, 0x73, 0x7E, 0x62, 0x00, 0x00,
0x00, 0x00, 0x82, 0x00, 0x00, 0x08, 0x5D, 0x04, 0x37, 0x17, 0x00, 0x00,
0x73, 0x01, 0x01, 0x11, 0x00, 0x00, 0x00, 0x00, 0x08, 0xCF, 0x05, 0x00,
0x00, 0x37, 0x19, 0x00, 0x00, 0x09, 0x31, 0x6A, 0xFB, 0xB1, 0xE0, 0x48,
0x25, 0xF8, 0xB9, 0x31, 0x23, 0xD4, 0xDC, 0xE3, 0x4D, 0x9C, 0x34, 0xD3,
0xEF, 0x5E, 0xB4, 0xD3, 0xE3, 0x8B, 0x3C, 0xD2, 0x19, 0x8D, 0xD7, 0xC4,
0x74, 0xC5, 0xD6, 0xA2, 0x71, 0x7C, 0xD2, 0xEA, 0xCE, 0x94, 0xF6, 0x79,
0x3C, 0x9E, 0xCF, 0x62, 0xC5, 0xEB, 0x75, 0xA6, 0xAC, 0x0F, 0x63, 0xEF,
0x3D, 0x71, 0xBE, 0x65, 0x5E, 0xB9, 0x99, 0x93, 0x77, 0xC7, 0x59, 0x77,
0x3E, 0xF3, 0xD7, 0x1B, 0xE6, 0x55, 0xEB, 0x99, 0x99, 0x37, 0x7C, 0x75,
0x97, 0x70, 0xD6, 0x97, 0xCA, 0x29, 0x35, 0xE4, 0xA2, 0x98, 0x0E, 0xE4,
0xA0, 0xA5, 0x25, 0xC0, 0x40, 0xA6, 0x93, 0x5F, 0x12, 0xE0, 0x20, 0x89,
0x2E, 0x47, 0x52, 0x68, 0x14, 0xD2, 0x73, 0x0A, 0xB0, 0x1C, 0x06, 0x09,
0x39, 0xA0, 0x82, 0x45, 0x53, 0xF3, 0x2D, 0x4A, 0x01, 0x01, 0xFA, 0xDB,
0xF3, 0x16, 0xA2, 0x40, 0x29, 0x4F, 0xD0, 0x43, 0x26, 0x24, 0xB8, 0x35,
0xE0, 0x20, 0x12, 0x30, 0x09, 0x69, 0x3D, 0x1B, 0x12, 0xD2, 0x49, 0xE0,
0x91, 0x24, 0x9D, 0x11, 0xCA, 0x76, 0x4C, 0xF6, 0xE6, 0xAC, 0xB8, 0x9F,
0x99, 0xD3, 0x15, 0x89, 0x29, 0x26, 0xBC, 0xDF, 0x25, 0x6C, 0xD7, 0xB4,
0x70, 0x10, 0x92, 0x52, 0x69, 0xF5, 0x9E, 0x34, 0xFA, 0xCF, 0x1E, 0x7C,
0x04, 0x91, 0x5C, 0x4E, 0xF3, 0xBC, 0x51, 0x74, 0xD9, 0xDE, 0x1B, 0x51,
0x12, 0x39, 0x45, 0x2D, 0x22, 0xA6, 0xBA, 0x97, 0x7B, 0xCD, 0x2E, 0x0D,
0xCD, 0xD2, 0xD3, 0x5A, 0x51, 0x5C, 0x4D, 0x33, 0x3B, 0x9E, 0xF5, 0xB1,
0x07, 0xFC, 0x5D, 0x38, 0xAC, 0xAD, 0xBC, 0x0F, 0xAC, 0x56, 0x7A, 0xDF,
0x87, 0x7A, 0x78, 0xD7, 0x89, 0xAD, 0xEB, 0x74, 0xCA, 0xBF, 0x32, 0xE5,
0xFE, 0x1D, 0xE9, 0xE3, 0x5E, 0x26, 0xB7, 0xAD, 0xD3, 0x2A, 0xFC, 0xCB,
0x96, 0x56, 0x44, 0x64, 0xEA, 0x52, 0x9F, 0x22, 0x78, 0x91, 0xE9, 0x7C,
0x8F, 0x20, 0x7E, 0x7D, 0x00, 0x0C, 0xD5, 0x68, 0x29, 0xF7, 0x15, 0x41,
0x42, 0xDA, 0x49, 0x77, 0x25, 0xF3, 0x32, 0x49, 0x32, 0xEE, 0x74, 0x1A,
0x1F, 0x04, 0x57, 0xE9, 0x7C, 0x02, 0x00, 0xE1, 0x97, 0xDB, 0x77, 0x0A,
0x53, 0x24, 0xBB, 0xDD, 0xAD, 0xE7, 0x8F, 0x46, 0x48, 0x89, 0x70, 0xA8,
0x72, 0x44, 0x11, 0x33, 0xC2, 0x0E, 0xE7, 0x27, 0x1E, 0x8F, 0x4B, 0x7D,
0x23, 0x24, 0xEA, 0x2E, 0x11, 0xA3, 0xA1, 0x9A, 0x1A, 0x2B, 0xC6, 0x43,
0xC0, 0x00, 0x66, 0x82, 0x38, 0x08, 0x42, 0x92, 0x8B, 0xD6, 0xE8, 0xBC,
0x16, 0x9F, 0x59, 0xEA, 0x5A, 0x7D, 0x6E, 0x75, 0x28, 0xBD, 0x67, 0x81,
0x54, 0x83, 0xF9, 0xC5, 0xEC, 0xBB, 0x2E, 0x69, 0x71, 0x0F, 0x6B, 0xC4,
0x07, 0xA6, 0x75, 0x11, 0x89, 0x23, 0x53, 0xF9, 0xC3, 0x7E, 0x2C, 0x5E,
0xB7, 0x49, 0xA1, 0xA5, 0xD3, 0x7F, 0x4B, 0x9C, 0x5A, 0x38, 0x05, 0x69,
0x92, 0xEC, 0xF6, 0x7E, 0xF3, 0xC7, 0x55, 0xEB, 0x5D, 0xF1, 0xB5, 0xE2,
0xB6, 0xD7, 0x57, 0x26, 0xBE, 0xF3, 0xC7, 0x55, 0xEB, 0x5D, 0xF1, 0xB5,
0xE2, 0xB6, 0xD7, 0x57, 0x26, 0x8D, 0x71, 0xFC, 0xF7, 0xF3, 0xDC, 0x7A,
0x28, 0xF4, 0x2C, 0x16, 0x49, 0xC9, 0xA0, 0xD0, 0xB2, 0x2C, 0x06, 0x48,
0xA2, 0x7D, 0x08, 0xC9, 0x09, 0xE2, 0xA2, 0xBF, 0x06, 0x90, 0x1C, 0x04,
0x56, 0x66, 0xBE, 0x0C, 0xA5, 0xC7, 0xF0, 0x49, 0xF0, 0x63, 0x5B, 0xB8,
0xEB, 0x24, 0xE4, 0xB2, 0x58, 0x1E, 0x74, 0xE3, 0x38, 0xE1, 0x03, 0x24,
0xC5, 0x94, 0xBD, 0xE8, 0x80, 0x45, 0xE0, 0x3F, 0x01, 0xF8, 0x37, 0x46,
0x15, 0x93, 0xE7, 0x78, 0xA8, 0x9A, 0x8A, 0xE7, 0x53, 0xE0, 0xCF, 0x4A,
0x27, 0xBA, 0x5A, 0x51, 0x7B, 0x3B, 0x13, 0x4F, 0x48, 0xDE, 0xE1, 0xC3,
0x43, 0xEE, 0x94, 0x43, 0x8E, 0xC4, 0x8B, 0xC8, 0xAD, 0x68, 0xE0, 0x15,
0xC4, 0xC2, 0x57, 0x67, 0xB1, 0xF7, 0x9E, 0xBA, 0xAF, 0x1D, 0x73, 0x75,
0x53, 0x29, 0xCC, 0xBE, 0xB4, 0x9A, 0xFB, 0xCF, 0x5D, 0x57, 0x8E, 0xB9,
0xBA, 0xA9, 0x94, 0xE6, 0x5F, 0x5A, 0x4D, 0x15, 0x91, 0x15, 0xA5, 0x48,
0xF4, 0x52, 0x7D, 0x0F, 0xCF, 0xA5, 0x68, 0x56, 0x94, 0x7F, 0x29, 0x1C,
0xF1, 0xF4, 0xE4, 0x41, 0xAC, 0xA3, 0xD1, 0x43, 0xF4, 0xFA, 0x6D, 0xE8,
0x3E, 0x45, 0xA8, 0xAC, 0x49, 0x71, 0x8A, 0xCB, 0xE8, 0x03, 0xF9, 0x03,
0x58, 0xA6, 0x8F, 0x40, 0xCA, 0x80, 0x8F, 0x29, 0xF4, 0x21, 0x04, 0x79,
0x52, 0x91, 0x93, 0x80, 0x6B, 0x16, 0xF4, 0xFB, 0x82, 0x62, 0x9B, 0x20,
0x6A, 0x8D, 0x20, 0x44, 0x5A, 0x37, 0xA6, 0xBC, 0x7B, 0x15, 0x6D, 0x20,
0xA2, 0x71, 0x76, 0x9F, 0xCE, 0x9D, 0x50, 0x62, 0xC5, 0x37, 0xA2, 0x99,
0xE6, 0x96, 0x91, 0xBF, 0x10, 0x93, 0x67, 0x9E, 0xF1, 0xE8, 0xE0, 0x14,
0x44, 0x0C, 0x10, 0xFC, 0xD1, 0x70, 0x76, 0x7A, 0xDF, 0x89, 0xE3, 0x87,
0x8D, 0x78, 0xEB, 0x95, 0xD6, 0x36, 0xD7, 0x52, 0x35, 0xF8, 0x9E, 0x38,
0x78, 0xD7, 0x8E, 0xB9, 0x5D, 0x63, 0x6D, 0x75, 0x23, 0x45, 0x65, 0x3E,
0x94, 0x81, 0xE8, 0xA0, 0xF9, 0x53, 0x48, 0xF2, 0xA4, 0x82, 0xE2, 0x03,
0x22, 0x0B, 0xD2, 0x60, 0xE4, 0x82, 0x29, 0x19, 0x20, 0x83, 0x92, 0xA2,
0x85, 0xAB, 0x7B, 0xEC, 0x92, 0x28, 0x24, 0x57, 0x90, 0x89, 0x19, 0x26,
0x8C, 0x93, 0x72, 0xA2, 0x3D, 0x31, 0xE9, 0xAE, 0x8D, 0x7C, 0xE0, 0x46,
0xBE, 0x76, 0x16, 0x5F, 0x04, 0x8A, 0xDF, 0xDA, 0x00, 0x22, 0x47, 0x0C,
0x06, 0x83, 0xC3, 0x30, 0xD0, 0x6B, 0xCF, 0x07, 0x00, 0x40, 0x27, 0xA0,
0x14, 0x08, 0x4E, 0x89, 0x44, 0xEA, 0x0F, 0xD1, 0x3A, 0x20, 0xB4, 0x52,
0x48, 0x72, 0x5C, 0x66, 0xFE, 0x9E, 0x97, 0x4F, 0x34, 0xA2, 0x1B, 0xC6,
0xFE, 0x90, 0xCE, 0x22, 0x44, 0x9E, 0x1B, 0xF1, 0x30, 0x75, 0xCE, 0x44,
0xD3, 0x49, 0xE8, 0xE0, 0x13, 0xC8, 0x36, 0x20, 0xD9, 0xCB, 0x05, 0x35,
0x44, 0xBA, 0x8F, 0x59, 0x22, 0x76, 0x7A, 0xBF, 0x89, 0xE3, 0xAA, 0xF5,
0xD7, 0x29, 0x4C, 0xBC, 0xDB, 0x5D, 0x59, 0x7F, 0x89, 0xE3, 0xAA, 0xF5,
0xD7, 0x29, 0x4C, 0xBC, 0xDB, 0x5D, 0x59, 0x65, 0x64, 0x19, 0xE3, 0xD6,
0x40, 0x7D, 0x05, 0x3E, 0x9A, 0x11, 0xE9, 0x48, 0xF4, 0x3E, 0xAD, 0x23,
0xF1, 0x58, 0x83, 0x5A, 0x53, 0xE8, 0xB7, 0x10, 0x72, 0x4E, 0xC8, 0xF2,
0xAC, 0x3D, 0x00, 0xFA, 0x48, 0x76, 0xB8, 0x71, 0xDC, 0x6C, 0xA8, 0x07,
0x6B, 0x80, 0x7C, 0x8E, 0x3B, 0x8C, 0x5C, 0x67, 0x1C, 0x43, 0x86, 0x4A,
0x0F, 0x91, 0x09, 0x59, 0x5E, 0xF4, 0x41, 0x9A, 0x6C, 0x87, 0x63, 0xB8,
0x12, 0x8C, 0xE4, 0x9F, 0x8C, 0x5E, 0x78, 0x45, 0x5E, 0xB7, 0xCF, 0x00,
0x79, 0x20, 0xF4, 0x99, 0xC6, 0x65, 0xDF, 0xAB, 0x47, 0x04, 0x02, 0xC5,
0xEB, 0x4F, 0xBC, 0xD1, 0xC0, 0x29, 0x4F, 0xCE, 0x40, 0x16, 0xAC, 0xF4,
0xBF, 0x13, 0xBE, 0x27, 0xAD, 0x72, 0xBD, 0xDE, 0x4A, 0xE6, 0x5F, 0x51,
0x35, 0xF8, 0x9D, 0xF1, 0x3D, 0x6B, 0x95, 0xEE, 0xF2, 0x57, 0x32, 0xFA,
0x89, 0xA2, 0xE3, 0xFA, 0x12, 0x9C, 0x11, 0xDF, 0x9E, 0xC9, 0xFE, 0x52,
0x4D, 0x62, 0x0E, 0x4C, 0xA7, 0x0E, 0xBC, 0x0D, 0x2E, 0x93, 0x4D, 0x28,
0x97, 0x70, 0xAA, 0x2B, 0xC8, 0x0E, 0xDC, 0x20, 0xB8, 0x4C, 0x51, 0xC7,
0x43, 0x85, 0x34, 0xA4, 0xD0, 0x90, 0x5D, 0xE4, 0xA0, 0x17, 0x00, 0x68,
0x21, 0x65, 0x77, 0x6D, 0x19, 0x26, 0x8C, 0x94, 0x90, 0x7D, 0x21, 0xC2,
0x55, 0x1E, 0xAF, 0x7A, 0x13, 0x16, 0x8A, 0x32, 0x73, 0x2E, 0x22, 0x78,
0x14, 0x2E, 0xE9, 0x61, 0xC9, 0xB0, 0xC3, 0x9A, 0x49, 0x82, 0x92, 0x82,
0x43, 0x80, 0x12, 0x83, 0x98, 0x04, 0xC6, 0x9E, 0x00, 0x83, 0x34, 0x13,
0xD3, 0x39, 0x26, 0xA5, 0xD0, 0x72, 0x42, 0x6B, 0xCB, 0xE8, 0xAA, 0x77,
0xB1, 0x5C, 0x9F, 0x7A, 0xE2, 0x76, 0x8F, 0xB1, 0x22, 0x99, 0xEE, 0x99,
0xBF, 0x2E, 0xD1, 0x58, 0x1B, 0x17, 0x34, 0x8D, 0xE9, 0xE4, 0x5D, 0x3D,
0x26, 0x6B, 0xDD, 0x3D, 0x35, 0xC3, 0xFA, 0x8E, 0x7B, 0xA7, 0xD3, 0xF7,
0x75, 0xE8, 0xE0, 0x13, 0xDC, 0x86, 0x54, 0xB2, 0x27, 0xC6, 0x68, 0x86,
0x21, 0xA0, 0x37, 0x0F, 0x86, 0x72, 0x04, 0x90, 0xCA, 0x06, 0xD3, 0x12,
0xB3, 0xCE, 0xFC, 0x4E, 0xF4, 0xF1, 0x7B, 0xBD, 0x64, 0xCA, 0x6E, 0x6B,
0x89, 0x53, 0x5F, 0x89, 0xDE, 0x9E, 0x2F, 0x77, 0xAC, 0x99, 0x4D, 0xCD,
0x71, 0x2A, 0x68, 0xD6, 0x96, 0xB1, 0x34, 0x83, 0xF8, 0xE9, 0x7D, 0x48,
0xAF, 0x3B, 0x28, 0x35, 0xE2, 0xFD, 0x14, 0x87, 0x75, 0x59, 0x70, 0xC2,
0xC4, 0xD3, 0x41, 0x33, 0xCA, 0xAD, 0x20, 0x53, 0x4A, 0x29, 0x42, 0x7D,
0xB7, 0xA3, 0x98, 0x09, 0x29, 0x66, 0xFE, 0x04, 0x92, 0xFC, 0x52, 0x87,
0x2A, 0xAE, 0xDA, 0x84, 0x97, 0x65, 0x69, 0xFA, 0x1C, 0xAA, 0xAC, 0x24,
0x1D, 0x73, 0x82, 0x90, 0x2A, 0x02, 0x83, 0x3F, 0x26, 0x20, 0x43, 0x5D,
0xD5, 0xE0, 0xD2, 0x0B, 0x18, 0xBB, 0x9F, 0x0D, 0x6B, 0x0D, 0x18, 0xCC,
0x0D, 0x16, 0xFB, 0x5C, 0x5C, 0xF9, 0x8B, 0x00, 0x16, 0x0E, 0xEE, 0xDC,
0x4A, 0xF7, 0x20, 0x78, 0x0A, 0x9E, 0x53, 0x17, 0x5D, 0xA2, 0xAC, 0x5D,
0x22, 0xE2, 0x12, 0xC2, 0x40, 0xDC, 0x40, 0x01, 0x84, 0x1D, 0x12, 0x03,
0x48, 0x10, 0x00, 0xD8, 0xB0, 0xB8, 0x09, 0x05, 0xE0, 0x48, 0x24, 0x00,
0xBC, 0x58, 0xD1, 0xB1, 0xF4, 0x72, 0x62, 0x9C, 0x29, 0xE8, 0xE2, 0x45,
0xF8, 0xBF, 0x42, 0xC7, 0x15, 0x85, 0xA3, 0x34, 0x20, 0x2C, 0xEA, 0x60,
0x62, 0x7D, 0xCF, 0x08, 0x73, 0x5A, 0xE7, 0x7B, 0xCE, 0x77, 0x4A, 0x2F,
0x10, 0xC5, 0xF2, 0x7D, 0x9E, 0x1B, 0xD3, 0xD0, 0x7B, 0xDD, 0x33, 0x7E,
0x24, 0x83, 0xD2, 0x13, 0x03, 0xEF, 0x74, 0xFA, 0xFA, 0x98, 0xD3, 0xDF,
0xD7, 0x40, 0x8B, 0x11, 0x89, 0xE8, 0xE0, 0x13, 0xD8, 0xDA, 0x53, 0x83,
0x16, 0xE6, 0x9A, 0x75, 0x00, 0x0E, 0x52, 0x74, 0xAB, 0x4C, 0x69, 0x27,
0x85, 0x91, 0x8A, 0xCF, 0x3B, 0xF5, 0x73, 0xAA, 0xC9, 0xDD, 0xEB, 0x7A,
0xDE, 0xE6, 0x57, 0x5C, 0x43, 0x5F, 0xAB, 0x9D, 0x56, 0x4E, 0xEF, 0x5B,
0xD6, 0xF7, 0x32, 0xBA, 0xE2, 0x1A, 0x3E, 0x92, 0x1D, 0x26, 0x84, 0x1C,
0x95, 0x14, 0xFB, 0xDD, 0x41, 0x19, 0x20, 0x9A, 0xFC, 0x9F, 0x4B, 0x20,
0xF0, 0x13, 0x4B, 0xFA, 0x08, 0xC9, 0x11, 0x92, 0xA2, 0x72, 0x41, 0xFB,
0xA4, 0x91, 0x43, 0xF4, 0x1E, 0x16, 0x00, 0xFC, 0x79, 0x13, 0xBA, 0xFF,
0xA4, 0xFA, 0x00, 0x3E, 0xD1, 0x00, 0x3B, 0xA3, 0x7E, 0x98, 0xF4, 0x85,
0x90, 0xB8, 0x18, 0x01, 0xAF, 0x30, 0x8C, 0x94, 0xFA, 0x7D, 0x26, 0xA1,
0x77, 0xAB, 0x15, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, 0x08,
0x5D, 0x04, 0xAB, 0x18, 0x00, 0x00, 0x74, 0x01, 0x01, 0x12, 0x00, 0x00,
0x00, 0x00, 0x08, 0xCF, 0x05, 0x00, 0x00, 0xD9, 0x1A, 0x00, 0x00, 0x12,
0x3A, 0x12, 0x0B, 0xBC, 0x02, 0x37, 0x9B, 0x03, 0xDB, 0xA9, 0x05, 0xE3,
0x65, 0xC0, 0x97, 0xE0, 0x01, 0x74, 0x6D, 0x78, 0xA7, 0x3A, 0x16, 0xC4,
0x4E, 0x8D, 0xA9, 0x74, 0xD3, 0x11, 0xC3, 0x7D, 0x37, 0xF4, 0x9A, 0x27,
0x74, 0x5D, 0x29, 0x7B, 0x7C, 0xEA, 0x39, 0x60, 0xF7, 0x4E, 0x79, 0xDE,
0x33, 0xB9, 0x7B, 0x9E, 0xF1, 0x33, 0xDD, 0x1C, 0x02, 0xAB, 0x07, 0x60,
0x79, 0x1F, 0xAB, 0x9D, 0x39, 0x9B, 0xD6, 0xB2, 0x66, 0x4E, 0x65, 0xEB,
0x8A, 0x5F, 0xEA, 0xE7, 0x4E, 0x66, 0xF5, 0xAC, 0x99, 0x93, 0x99, 0x7A,
0xE2, 0x97, 0x16, 0xBE, 0xB8, 0x0E, 0xF9, 0x58, 0x12, 0xE0, 0xC2, 0x5B,
0x40, 0x0E, 0x6D, 0x75, 0x55, 0x77, 0x08, 0x5B, 0xA2, 0x1B, 0xEF, 0x05,
0xDE, 0x0A, 0x10, 0x94, 0xB3, 0xAD, 0xE8, 0x3B, 0x16, 0xF2, 0x10, 0x3C,
0x50, 0xF9, 0x68, 0x32, 0xC6, 0x5B, 0x18, 0xE3, 0x80, 0x2C, 0x06, 0xC9,
0x06, 0xDC, 0xFE, 0x98, 0xB5, 0xD2, 0xC3, 0xF6, 0x80, 0x2B, 0xCF, 0xF8,
0x89, 0x3C, 0xDD, 0x1D, 0x12, 0x5D, 0xE0, 0x13, 0xE9, 0x03, 0xF1, 0xC3,
0x8D, 0x58, 0xB8, 0xC9, 0x87, 0x1C, 0x38, 0x75, 0x35, 0x83, 0x02, 0x7D,
0xF5, 0x39, 0x29, 0xAF, 0x11, 0x48, 0x02, 0x5C, 0x99, 0x59, 0xA3, 0x95,
0xDB, 0x09, 0x40, 0x6F, 0xBC, 0x89, 0x78, 0x01, 0xE0, 0x01, 0xE4, 0x92,
0x66, 0x73, 0xE0, 0x26, 0x48, 0xA0, 0xA4, 0x51, 0x99, 0xBA, 0x90, 0x73,
0xC5, 0x0C, 0x85, 0x76, 0x8F, 0x4A, 0x7B, 0xCC, 0x1D, 0x19, 0xF3, 0xA5,
0x11, 0xE5, 0xC0, 0xB2, 0xC6, 0x92, 0x37, 0xA4, 0x03, 0x13, 0x48, 0x43,
0x26, 0x3F, 0x17, 0x1C, 0xBB, 0xC8, 0x28, 0x9D, 0xC9, 0x7C, 0x20, 0xA8,
0xDC, 0x82, 0x9E, 0xF5, 0x21, 0x7F, 0x83, 0xEE, 0x26, 0x96, 0x9B, 0x20,
0xE9, 0xC5, 0x48, 0xD0, 0x69, 0xF5, 0x44, 0x6C, 0x8D, 0x1C, 0x02, 0x8E,
0x0A, 0xC6, 0x82, 0x91, 0x55, 0x9D, 0xCF, 0xEE, 0xA4, 0x52, 0x42, 0xB2,
0xF9, 0xBB, 0xBB, 0x2B, 0xF7, 0x52, 0x29, 0x21, 0x59, 0x7C, 0xDD, 0xDD,
0x95, 0xE4, 0xF2, 0x48, 0x90, 0x60, 0xF0, 0x24, 0x04, 0xA2, 0x41, 0xD1,
0x12, 0x08, 0x90, 0x60, 0x8F, 0x85, 0xA0, 0xC2, 0x40, 0x48, 0x91, 0x6D,
0x98, 0x44, 0xA1, 0x35, 0x12, 0x01, 0x16, 0x0B, 0x41, 0xA9, 0x48, 0x45,
0x28, 0xAA, 0x0B, 0x41, 0xC6, 0x24, 0x30, 0xF0, 0x89, 0x12, 0x14, 0xC6,
0x25, 0x05, 0x28, 0x35, 0x08, 0x62, 0x50, 0x4A, 0x12, 0x26, 0x8A, 0x56,
0x0F, 0xC2, 0x29, 0x00, 0xAF, 0x0C, 0x48, 0x0F, 0xE8, 0x58, 0xBE, 0x25,
0x07, 0x45, 0xB7, 0x89, 0x41, 0x28, 0x30, 0x46, 0xC1, 0x82, 0x24, 0x12,
0x0C, 0x18, 0xB5, 0x6B, 0x7C, 0xB0, 0x5B, 0xEC, 0xC6, 0x7A, 0xA5, 0xD7,
0xC3, 0x0B, 0x42, 0x9B, 0x0C, 0x22, 0x43, 0x3F, 0x15, 0x82, 0xD7, 0x4D,
0x89, 0x41, 0x28, 0x30, 0x43, 0x08, 0x90, 0x5A, 0x24, 0x18, 0x2B, 0xC3,
0x0C, 0x11, 0x22, 0x43, 0x1E, 0x0C, 0x67, 0x03, 0x4C, 0x4E, 0xA2, 0x51,
0x2B, 0x0F, 0x5C, 0x2B, 0x0C, 0x4C, 0x00, 0x4A, 0x81, 0xE5, 0x61, 0xA1,
0xA1, 0xA3, 0x94, 0x53, 0xC6, 0xF8, 0xC4, 0xD1, 0x2A, 0x3A, 0x62, 0x68,
0x95, 0x86, 0xB0, 0xC4, 0xC4, 0xC4, 0xC4, 0xF5, 0x32, 0x8E, 0x94, 0x45,
0x5C, 0x8B, 0xC1, 0xA6, 0x99, 0x47, 0x78, 0xDC, 0x4D, 0x38, 0x8A, 0x7B,
0x3C, 0x7A, 0x66, 0xF7, 0x7B, 0x11, 0xC3, 0x08, 0xBA, 0x16, 0x69, 0xAD,
0x29, 0xEA, 0x89, 0xA6, 0x97, 0x51, 0x28, 0x69, 0x94, 0x74, 0xA2, 0x2A,
0xE4, 0x5E, 0x2E, 0xA1, 0xE1, 0x89, 0xA1, 0xF1, 0x94, 0x45, 0x0B, 0x22,
0xAE, 0x45, 0x43, 0x4D, 0x62, 0x33, 0x4B, 0xA8, 0x6A, 0x09, 0xA2, 0xEA,
0x5D, 0xE0, 0xD3, 0xA8, 0x95, 0xA3, 0x80, 0x50, 0xF3, 0xCD, 0x27, 0x94,
0x34, 0x35, 0x62, 0x12, 0x53, 0x45, 0x04, 0x92, 0x6A, 0x00, 0x40, 0x48,
0x00, 0xCA, 0x0A, 0x15, 0x91, 0x10, 0x10, 0x49, 0x33, 0x79, 0x22, 0x52,
0x92, 0x49, 0x32, 0x04, 0xA4, 0x20, 0x35, 0x89, 0x29, 0xAC, 0xD2, 0x30,
0xD2, 0x49, 0x04, 0x99, 0x8A, 0xA5, 0x10, 0x04, 0x42, 0x01, 0x1B, 0x75,
0xB0, 0x4D, 0x52, 0x0C, 0x12, 0x26, 0x4C, 0x96, 0x98, 0x0A, 0xE5, 0x89,
0x90, 0x24, 0x40, 0x84, 0x9D, 0xC4, 0x83, 0x55, 0x29, 0x2C, 0x15, 0x28,
0x61, 0xC2, 0x33, 0x01, 0x09, 0x21, 0x00, 0xA2, 0x24, 0x92, 0x02, 0x41,
0x21, 0x00, 0x06, 0x94, 0x3E, 0x6C, 0x06, 0x08, 0x58, 0x51, 0x24, 0x82,
0x96, 0xC0, 0x25, 0x29, 0x34, 0xD2, 0x9A, 0x81, 0x88, 0x46, 0x98, 0x22,
0xF0, 0x89, 0x24, 0x01, 0x55, 0x21, 0x32, 0x5A, 0x4B, 0x14, 0x80, 0xC8,
0x50, 0x28, 0xA1, 0x32, 0xD2, 0x94, 0x95, 0x64, 0x8E, 0x81, 0x24, 0x90,
0xF1, 0xF9, 0x47, 0xB1, 0x50, 0x7F, 0x8C, 0xE9, 0x33, 0x84, 0x52, 0x99,
0xA4, 0x45, 0x15, 0x36, 0xF7, 0xBE, 0xCF, 0x1E, 0x0A, 0xDA, 0x9C, 0x36,
0x23, 0x7B, 0xBC, 0x42, 0xC3, 0x34, 0x6B, 0x60, 0x55, 0xFE, 0xA7, 0x77,
0xA6, 0xB7, 0x95, 0x24, 0x4B, 0xDD, 0xE9, 0xAD, 0xE5, 0x49, 0x12, 0xD6,
0x2B, 0x64, 0xF5, 0x10, 0x16, 0x7C, 0xB3, 0x69, 0x25, 0x7A, 0x41, 0xAB,
0x02, 0x06, 0xE1, 0xA9, 0x02, 0x78, 0xDF, 0x02, 0x1F, 0x12, 0x93, 0x55,
0x90, 0x20, 0xC6, 0x10, 0x7C, 0xFA, 0x84, 0xBB, 0x32, 0x90, 0x64, 0xD3,
0x84, 0x98, 0xA1, 0x09, 0x94, 0x18, 0x01, 0x60, 0x62, 0x0A, 0x1D, 0x13,
0x52, 0x91, 0x00, 0x12, 0x42, 0x16, 0x07, 0x0F, 0x09, 0x14, 0x14, 0x14,
0x04, 0x14, 0xA4, 0xC0, 0x0C, 0x88, 0xD0, 0x09, 0x64, 0x87, 0xA7, 0x5A,
0x84, 0x93, 0x76, 0x92, 0x1C, 0x45, 0x09, 0x77, 0xA5, 0x7F, 0xA8, 0xA2,
0x83, 0x40, 0x54, 0xCC, 0x32, 0x40, 0x07, 0x62, 0x32, 0x38, 0x94, 0x8D,
0x01, 0x2E, 0xA8, 0x00, 0x55, 0x25, 0x8B, 0xDA, 0xC2, 0xE8, 0xD5, 0x0D,
0x0D, 0x01, 0xEA, 0x46, 0xE8, 0x2A, 0x28, 0x3B, 0x7F, 0xB1, 0xEF, 0x8E,
0xB1, 0x9A, 0x97, 0x3B, 0xE3, 0xAC, 0x66, 0xA5, 0xCA, 0x43, 0xE1, 0x45,
0xCA, 0x00, 0x02, 0x24, 0x28, 0x0D, 0x4A, 0x16, 0x11, 0x40, 0xBE, 0x6A,
0x41, 0x12, 0x82, 0x43, 0x64, 0x11, 0xFE, 0x3A, 0x30, 0xA8, 0xD8, 0x96,
0x4B, 0xD3, 0x84, 0x0A, 0x15, 0x7F, 0xB7, 0xF7, 0xF3, 0xE7, 0x26, 0x5D,
0xDD, 0xFB, 0xF9, 0xF3, 0x93, 0x2E, 0xEE, 0xDD, 0xBD, 0x29, 0x40, 0x00,
0x44, 0x6F, 0xFC, 0x66, 0x4A, 0x6B, 0x32, 0x04, 0x08, 0x00, 0x9D, 0x55,
0x8A, 0x84, 0x90, 0x74, 0x75, 0x7F, 0x3F, 0x90, 0xF4, 0xE3, 0x0A, 0x8E,
0xEF, 0x6F, 0xEB, 0x5E, 0xD9, 0x2B, 0x57, 0x77, 0xEB, 0x5E, 0xD9, 0x2B,
0x57, 0x76, 0x8A, 0x1D, 0x87, 0xE7, 0x91, 0x35, 0x6A, 0x85, 0x16, 0x71,
0x24, 0x08, 0x23, 0x62, 0xF9, 0x1D, 0x77, 0x0A, 0xB7, 0xB7, 0x28, 0x7A,
0x4C, 0x6B, 0xEB, 0x3D, 0xF4, 0x2D, 0x8A, 0x8F, 0x8A, 0xD7, 0x12, 0x50,
0x81, 0x2D, 0xBA, 0x09, 0xAB, 0x29, 0xA0, 0xDB, 0xE6, 0x10, 0x21, 0x26,
0x4C, 0xAC, 0xE1, 0x45, 0xB9, 0x15, 0x2A, 0x0A, 0x24, 0x94, 0x92, 0x9A,
0x89, 0x09, 0x28, 0x2D, 0x05, 0xCF, 0xCB, 0x2D, 0x71, 0x56, 0xDF, 0xEB,
0xC1, 0x72, 0xA0, 0xAD, 0xAE, 0xEC, 0xFA, 0x7D, 0x65, 0x4A, 0xAB, 0xBB,
0x56, 0xE5, 0xE4, 0xBE, 0x2E, 0x5C, 0xBF, 0x59, 0x52, 0xAA, 0xEE, 0xD5,
0xB9, 0x79, 0x2F, 0x8B, 0x97, 0x2C, 0x95, 0xEE, 0xCA, 0x2C, 0x3B, 0x00,
0x8E, 0xAA, 0x52, 0x84, 0x83, 0x7A, 0x56, 0xE8, 0x41, 0xD9, 0x24, 0xA6,
0xC9, 0x22, 0x7A, 0x89, 0x1D, 0x00, 0x57, 0x36, 0x0C, 0xAA, 0x48, 0xDB,
0x49, 0x8A, 0xA8, 0x21, 0x44, 0x55, 0x34, 0x24, 0x0A, 0x88, 0x45, 0x01,
0x25, 0x00, 0x44, 0x09, 0x21, 0x91, 0x0D, 0x6B, 0x24, 0xB2, 0x5B, 0x25,
0x82, 0x66, 0x5D, 0x48, 0x91, 0x20, 0x88, 0x45, 0x55, 0x81, 0x28, 0x34,
0x42, 0x24, 0x21, 0x80, 0x44, 0xD4, 0x94, 0x00, 0x25, 0x25, 0x02, 0x00,
0x41, 0x29, 0x48, 0x44, 0x81, 0x09, 0xAA, 0x40, 0x25, 0xB3, 0x20, 0x12,
0x25, 0xB2, 0x01, 0x62, 0x74, 0x71, 0x28, 0xE7, 0x95, 0xBA, 0xDB, 0x3E,
0x08, 0xD7, 0x56, 0xBC, 0xFC, 0x03, 0xC2, 0xED, 0x7F, 0x2B, 0x8B, 0x52,
0xB1, 0x63, 0x1D, 0x97, 0xBC, 0xBB, 0x9C, 0xE5, 0x9F, 0x35, 0x67, 0xCB,
0xDE, 0x0D, 0xDD, 0xDA, 0xB6, 0x95, 0x35, 0xC6, 0xA4, 0x97, 0xDE, 0x0D,
0xDD, 0xDA, 0xB6, 0x95, 0x35, 0xC6, 0xA4, 0x96, 0x65, 0xAC, 0x0F, 0xA9,
0x0A, 0x94, 0xA5, 0x01, 0x22, 0xF4, 0xAC, 0x12, 0x22, 0x02, 0x2A, 0xC2,
0x70, 0xC9, 0x76, 0xCF, 0xA9, 0x2B, 0x49, 0xA0, 0x04, 0x49, 0x42, 0xE9,
0x82, 0x03, 0x4C, 0x9D, 0x01, 0x20, 0x18, 0x33, 0xB8, 0x80, 0x64, 0x02,
0x44, 0x82, 0x0B, 0x09, 0x04, 0xB1, 0x2C, 0xC2, 0x2D, 0x5A, 0xA6, 0x6A,
0xBF, 0x7C, 0x03, 0xB3, 0x26, 0x24, 0x54, 0xD1, 0x6C, 0xD2, 0x82, 0x08,
0x31, 0x87, 0x0C, 0x98, 0x01, 0x33, 0x28, 0x29, 0x29, 0x40, 0x4A, 0x30,
0xE8, 0x00, 0x52, 0x02, 0x68, 0x42, 0x1F, 0xCD, 0x44, 0xD6, 0x70, 0x88,
0x84, 0x14, 0x55, 0x48, 0x6A, 0x6B, 0x3A, 0x10, 0x88, 0x28, 0xC2, 0x76,
0x52, 0x41, 0x09, 0x6C, 0x41, 0x11, 0x08, 0x48, 0xDD, 0x58, 0x28, 0x48,
0xDC, 0xD8, 0xAD, 0xB3, 0x6D, 0x86, 0x83, 0xE1, 0xF6, 0x1D, 0xCE, 0x84,
0x4B, 0x3E, 0x99, 0x74, 0xC7, 0x31, 0xE5, 0x9F, 0xC4, 0x1E, 0xCA, 0x9C,
0xDC, 0x0F, 0x1B, 0x58, 0x9D, 0x94, 0xB4, 0x23, 0x40, 0xBC, 0xE8, 0x6A,
0x23, 0xC9, 0xAE, 0x29, 0x29, 0x0E, 0x50, 0x33, 0x14, 0xC5, 0x67, 0xC9,
0xD8, 0x6E, 0xAF, 0x52, 0xB6, 0x95, 0x35, 0xAE, 0x89, 0xAE, 0xC3, 0x75,
0x7A, 0x95, 0xB4, 0xA9, 0xAD, 0x74, 0x4D, 0x0F, 0xF5, 0x12, 0x1B, 0x50,
0x52, 0x82, 0x85, 0x4D, 0x51, 0xAD, 0x82, 0x62, 0x19, 0x33, 0x14, 0xBB,
0x6A, 0x89, 0x5A, 0x48, 0x7C, 0xFE, 0xF0, 0x08, 0x68, 0xBF, 0x6D, 0xD6,
0x35, 0xC6, 0x5A, 0x62, 0x08, 0x04, 0xB4, 0x10, 0x24, 0x4D, 0x56, 0x90,
0x56, 0x0B, 0x68, 0xA8, 0x28, 0x2B, 0x04, 0xA5, 0x2C, 0xC2, 0x86, 0xE1,
0xB5, 0xD5, 0xB9, 0x30, 0x43, 0x0B, 0x13, 0x25, 0x04, 0x94, 0x26, 0x82,
0x5F, 0x09, 0x76, 0x50, 0x97, 0xE2, 0xA0, 0x42, 0x5F, 0x49, 0x32, 0x13,
0xEB, 0x10, 0xA9, 0x14, 0x82, 0x2A, 0x30, 0x89, 0x21, 0x77, 0x4A, 0xA4,
0x18, 0x82, 0x20, 0x0A, 0xA5, 0xA6, 0x7A, 0x8F, 0x01, 0x00, 0x95, 0x5B,
0xFB, 0xCD, 0xAF, 0x60, 0x47, 0x92, 0xCB, 0x81, 0xF5, 0x62, 0xC1, 0x57,
0x4D, 0x2A, 0x32, 0xEE, 0x56, 0x3C, 0xF3, 0x36, 0x45, 0x88, 0xD9, 0x2C,
0x80, 0xDE, 0x07, 0xB4, 0x69, 0x21, 0xA2, 0x91, 0xC0, 0xA5, 0x00, 0x00,
0x00, 0x00
};


wma_dec.ZIP > parser.c

#include " codeccontext.h "
#include " wmadeci.h "
//#include " mpegvideo.h "
//#include " mpegaudio.h "
#include & lt; string.h & gt; //jacky 2006/10/18

AVCodecParser *av_first_parser = NULL;



AVCodecParserContext *av_parser_init(int codec_id)
{
AVCodecParserContext *s;
AVCodecParser *parser;
int ret;

for(parser = av_first_parser; parser != NULL; parser = parser- & gt; next) {
if (parser- & gt; codec_ids[0] == codec_id ||
parser- & gt; codec_ids[1] == codec_id ||
parser- & gt; codec_ids[2] == codec_id)
goto found;
}
return NULL;
found:
s = av_mallocz(sizeof(AVCodecParserContext));
if (!s)
return NULL;
s- & gt; parser = parser;
s- & gt; priv_data = av_mallocz(parser- & gt; priv_data_size);
if (!s- & gt; priv_data) {
av_free(s);
return NULL;
}
if (parser- & gt; parser_init) {
ret = parser- & gt; parser_init(s);
if (ret != 0) {
av_free(s- & gt; priv_data);
av_free(s);
return NULL;
}
}
return s;
}


/* NOTE: buf_size == 0 is used to signal EOF so that the last frame
can be returned if necessary */
int av_parser_parse(AVCodecParserContext *s,
CodecContext *avctx,
unsigned char **poutbuf, int *poutbuf_size,
const unsigned char *buf, int buf_size,
long long pts, long long dts)
{
int index, i, k;
unsigned char dummy_buf[FF_INPUT_BUFFER_PADDING_SIZE];

if (buf_size == 0) {
/* padding is always necessary even if EOF, so we add it here */
memset(dummy_buf, 0, sizeof(dummy_buf));
buf = dummy_buf;
} else {
/* add a new packet descriptor */
k = (s- & gt; cur_frame_start_index + 1) & (AV_PARSER_PTS_NB - 1);
s- & gt; cur_frame_start_index = k;
s- & gt; cur_frame_offset[k] = s- & gt; cur_offset;
s- & gt; cur_frame_pts[k] = pts;
s- & gt; cur_frame_dts[k] = dts;

/* fill first PTS/DTS */
if (s- & gt; cur_offset == 0) {
s- & gt; last_pts = pts;
s- & gt; last_dts = dts;
}
}

/* WARNING: the returned index can be negative */
index = s- & gt; parser- & gt; parser_parse(s, avctx, poutbuf, poutbuf_size, buf, buf_size);
/* update the file pointer */
if (*poutbuf_size) {
/* fill the data for the current frame */
s- & gt; frame_offset = s- & gt; last_frame_offset;
s- & gt; pts = s- & gt; last_pts;
s- & gt; dts = s- & gt; last_dts;

/* offset of the next frame */
s- & gt; last_frame_offset = s- & gt; cur_offset + index;
/* find the packet in which the new frame starts. It
is tricky because of MPEG video start codes
which can begin in one packet and finish in
another packet. In the worst case, an MPEG
video start code could be in 4 different
packets. */
k = s- & gt; cur_frame_start_index;
for(i = 0; i & lt; AV_PARSER_PTS_NB; i++) {
if (s- & gt; last_frame_offset & gt; = s- & gt; cur_frame_offset[k])
break;
k = (k - 1) & (AV_PARSER_PTS_NB - 1);
}
s- & gt; last_pts = s- & gt; cur_frame_pts[k];
s- & gt; last_dts = s- & gt; cur_frame_dts[k];
}
if (index & lt; 0)
index = 0;
s- & gt; cur_offset += index;
return index;
}


wma_dec.ZIP > i2c.h

#ifndef I2C_H
#define I2C_H

/* I2C peripheral configuration defines (control interface of the audio codec) */
#define CODEC_I2C I2C1
#define CODEC_ADDRESS 0x94 /* b00100111 */



void config_I2C(I2C_TypeDef *I2Cx);

#endif


wma_dec.ZIP > wmadeci.h

#include " includes.h "
#ifndef WMADECI_H
#define WMADECI_H


void av_free(void *ptr);
void avcodec_register_all(void);
void __av_freepy(void **ptr);
void decode_last_superframe(CodecContext *avctx, void *data, int *data_size);
void init_WMADecodeContext_struct(CodecContext *avctx);

#endif


wma_dec.ZIP > includes.h

#ifndef INCLUDES_H
#define INCLUDES_H

#include & lt; stdlib.h & gt;
#include & lt; string.h & gt;
#include & lt; cross_studio_io.h & gt;
//#include & lt; stdio.h & gt;
//#include & lt; math.h & gt;

#include " stm32f4xx.h "
#include " stm32f4xx_conf.h "
#include " i2c.h "
#include " spi3_i2s.h "


#include " defines.h "
#include " codeccontext.h "
#include " wmadec_tab.h "
#include " avformat.h "
#include " asf.h "
#include " avio.h "
#include " IO_init.h "
#include " wmadeci.h "



//#include " global_variables.h "


#endif


wma_dec.ZIP > utils.c

#include " includes.h "



/* encoder management */
AVCodec *first_avcodec;

void register_avcodec(AVCodec *format)
{
AVCodec **p;
p = & first_avcodec;
while (*p != NULL) p = & (*p)- & gt; next;
*p = format;
format- & gt; next = NULL;
}

void avcodec_get_context_defaults(CodecContext *s){
s- & gt; bit_rate= 800*1000;
// s- & gt; bit_rate_tolerance= s- & gt; bit_rate*10; //unused while decoding
//s- & gt; qmin= 2; //unused while decoding
//s- & gt; qmax= 31; //unused while decoding
//s- & gt; mb_qmin= 2; //unused while decoding
//s- & gt; mb_qmax= 31; //unused while decoding
//s- & gt; rc_eq= " tex^qComp " ; //unused while decoding
//s- & gt; qcompress= 0.5; //unused while decoding
//s- & gt; max_qdiff= 3; //unused while decoding
//s- & gt; b_quant_factor=1.25; //unused while decoding
//s- & gt; b_quant_offset=1.25; //unused while decoding
//s- & gt; i_quant_factor=-0.8; //unused while decoding
//s- & gt; i_quant_offset=0.0; //unused while decoding
// s- & gt; error_concealment= 3; //unused while decoding
// s- & gt; error_resilience= 1;
//s- & gt; workaround_bugs= FF_BUG_AUTODETECT;
//s- & gt; frame_rate_base= 1;
//s- & gt; frame_rate = 25;
//s- & gt; gop_size= 50; //unused while decoding
//s- & gt; me_method= ME_EPZS; //unused while decoding
//s- & gt; get_buffer= avcodec_default_get_buffer;
//s- & gt; release_buffer= avcodec_default_release_buffer;
//s- & gt; get_format= avcodec_default_get_format;
//s- & gt; me_subpel_quality=8; //unused while decoding
//s- & gt; lmin= FF_QP2LAMBDA * s- & gt; qmin; //unused while decoding
//s- & gt; lmax= FF_QP2LAMBDA * s- & gt; qmax; //unused while decoding
//s- & gt; sample_aspect_ratio= (AVRational){0,1};
//s- & gt; ildct_cmp= FF_CMP_VSAD; //unused while decoding

//s- & gt; intra_quant_bias= FF_DEFAULT_QUANT_BIAS; //unused while decoding
//s- & gt; inter_quant_bias= FF_DEFAULT_QUANT_BIAS; //unused while decoding
//s- & gt; palctrl = NULL; //unused while decoding
//s- & gt; reget_buffer= avcodec_default_reget_buffer;
}


void *av_mallocz(unsigned int size)
{
void *ptr;

ptr = av_malloc(size);
if (!ptr)
return NULL;
memset(ptr, 0, size);
return ptr;
}

/**
* realloc which does nothing if the block is large enough
*/
void *av_fast_realloc(void *ptr, unsigned int *size, unsigned int min_size)
{
if(min_size & lt; *size)
return ptr;

*size= min_size + 10*1024;

return av_realloc(ptr, *size);
}



/**
* Copy the string str to buf. If str length is bigger than buf_size -
* 1 then it is clamped to buf_size - 1.
* NOTE: this function does what strncpy should have done to be
* useful. NEVER use strncpy.
*
* @param buf destination buffer
* @param buf_size size of destination buffer
* @param str source string
*/
void pstrcpy(char *buf, int buf_size, const char *str)
{
int c;
char *q = buf;

if (buf_size & lt; = 0)
return;

for(;;) {
c = *str++;
if (c == 0 || q & gt; = buf + buf_size - 1)
break;
*q++ = c;
}
*q = '\0';
}


AVCodec *avcodec_find_decoder(enum CodecID id)
{
AVCodec *p;
p = first_avcodec;
while (p) {
if (p- & gt; decode != NULL & & p- & gt; id == id)
return p;
p = p- & gt; next;
}
return NULL;
}



int avcodec_open(CodecContext *avctx, AVCodec *codec)
{
int ret;

if(avctx- & gt; codec)
return -1;

avctx- & gt; codec = codec;
avctx- & gt; codec_id = codec- & gt; id;
avctx- & gt; frame_number = 0;
if (codec- & gt; priv_data_size & gt; 0) {
avctx- & gt; priv_data = av_mallocz(codec- & gt; priv_data_size);
if (!avctx- & gt; priv_data)
return -1; //jacky 2006/10/18
//return -ENOMEM;
} else {
avctx- & gt; priv_data = NULL;
}
ret = avctx- & gt; codec- & gt; init(avctx);
if (ret & lt; 0) {
av_freep( & avctx- & gt; priv_data);
return ret;
}
return 0;
}


/* decode an audio frame. return -1 if error, otherwise return the
*number of bytes used. If no frame could be decompressed,
*frame_size_ptr is zero. Otherwise, it is the decompressed frame
*size in BYTES. */
int avcodec_decode_audio(CodecContext *avctx, short *samples,
int *frame_size_ptr,
unsigned char *buf, int buf_size)
{
int ret;
ret = avctx- & gt; codec- & gt; decode(avctx, samples, frame_size_ptr,
buf, buf_size);
avctx- & gt; frame_number++;
return ret;
}


wma_dec.ZIP > spi3_i2s.c

#include " includes.h "


/* @brief Initializes the Audio Codec audio interface (I2S)
* @note This function assumes that the I2S input clock (through PLL_R in
* Devices RevA/Z and through dedicated PLLI2S_R in Devices RevB/Y)
* is already configured and ready to be used.
* @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
* in SPI mode or 2 or 3 in I2S mode.
* @param CurrAudioInterface = AUDIO_INTERFACE_I2S lub AUDIO_INTERFACE_DAC
* @param AudioFreq: Audio frequency to be configured for the I2S peripheral.
* @retval None
*/
void config_I2S(SPI_TypeDef *SPIx, uint32_t CurrAudioInterface, unsigned int AudioFreq) //inicjalizacja SPI3 jako interfejsu I2S
{
unsigned char opoznienie = 0;
I2S_InitTypeDef I2S_InitStructure;
uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
uint32_t tmp = 0, i2sclk = 0;
uint32_t pllm = 0, plln = 0, pllr = 0;

if (SPIx == SPI1)
{
RCC- & gt; APB2RSTR = RCC- & gt; APB2RSTR | RCC_APB2RSTR_SPI1RST; //reset interfejsu SPI1
for(opoznienie = 0; opoznienie & lt; 10; opoznienie++);
RCC- & gt; APB2RSTR = 0; //koniec resetu SPI1
}
if (SPIx == SPI2)
{
RCC- & gt; APB1RSTR = RCC- & gt; APB1RSTR | RCC_APB1RSTR_SPI2RST; //reset interfejsu SPI2
for(opoznienie = 0; opoznienie & lt; 10; opoznienie++);
RCC- & gt; APB1RSTR = 0; //koniec resetu SPI2
}
if (SPIx == SPI3)
{
RCC- & gt; APB1RSTR = RCC- & gt; APB1RSTR | RCC_APB1RSTR_SPI3RST; //reset interfejsu SPI3
for(opoznienie = 0; opoznienie & lt; 10; opoznienie++);
RCC- & gt; APB1RSTR = 0; //koniec resetu SPI3
}
I2S_InitStructure.I2S_AudioFreq = AudioFreq;
I2S_InitStructure.I2S_Standard = I2S_STANDARD;
I2S_InitStructure.I2S_DataFormat = I2S_DataFormat_16b;
I2S_InitStructure.I2S_CPOL = I2S_CPOL_Low;
if (CurrAudioInterface == AUDIO_INTERFACE_DAC)
{
I2S_InitStructure.I2S_Mode = I2S_Mode_MasterRx;
}
else
{
I2S_InitStructure.I2S_Mode = I2S_Mode_MasterTx;
}
I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Enable;
/* Initialize the I2S peripheral with the structure above */
/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
SPIx- & gt; I2SCFGR = SPIx- & gt; I2SCFGR & 0xF040; /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
SPIx- & gt; I2SPR = 0x0002; //clear SPI prescaler register
tmpreg = SPIx- & gt; I2SCFGR; /* Get the I2SCFGR register value */
if(I2S_InitStructure.I2S_AudioFreq == I2S_AudioFreq_Default) // If the default value has to be written, reinitialize i2sdiv and i2sodd
{
i2sodd = (uint16_t)0;
i2sdiv = (uint16_t)2;
}
else // If the requested audio frequency is not the default, compute the prescaler */
{
if(I2S_InitStructure.I2S_DataFormat == I2S_DataFormat_16b) // Check the frame length (For the Prescaler computing)
{
packetlength = 1; //Packet length is 16 bits
}
else
{
packetlength = 2; // Packet length is 32 bits
}
/* Get I2S source Clock frequency ****************************************/
/* If an external I2S clock has to be used, this define should be set
in the project configuration or in the stm32f4xx_conf.h file */
#ifdef I2S_EXTERNAL_CLOCK_VAL
if ((RCC- & gt; CFGR & RCC_CFGR_I2SSRC) == 0) // Set external clock as I2S clock source
{
RCC- & gt; CFGR |= (uint32_t)RCC_CFGR_I2SSRC;
}
i2sclk = I2S_EXTERNAL_CLOCK_VAL; // Set the I2S clock to the external clock value
#else /* There is no define for External I2S clock source */
if ((RCC- & gt; CFGR & RCC_CFGR_I2SSRC) != 0) // Set PLLI2S as I2S clock source
{
RCC- & gt; CFGR = RCC- & gt; CFGR & (~(RCC_CFGR_I2SSRC));
}
plln = (uint32_t)(((RCC- & gt; PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) & gt; & gt; 6) & (RCC_PLLI2SCFGR_PLLI2SN & gt; & gt; 6)); // Get the PLLI2SN value
pllr = (uint32_t)(((RCC- & gt; PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) & gt; & gt; 28) & (RCC_PLLI2SCFGR_PLLI2SR & gt; & gt; 28));//Get the PLLI2SR value
pllm = (uint32_t)(RCC- & gt; PLLCFGR & RCC_PLLCFGR_PLLM); // Get the PLLM value
i2sclk = (uint32_t)(((HSE_VALUE / pllm) * plln) / pllr); //Get the I2S source clock value
#endif /* I2S_EXTERNAL_CLOCK_VAL */
/* Compute the Real divider depending on the MCLK output state, with a floating point */
if(I2S_InitStructure.I2S_MCLKOutput == I2S_MCLKOutput_Enable)// MCLK output is enabled
{
tmp = (uint16_t)(((((i2sclk / 256) * 10) / I2S_InitStructure.I2S_AudioFreq)) + 5);
}
else // MCLK output is disabled */
{
tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / I2S_InitStructure.I2S_AudioFreq)) + 5);
}
tmp = tmp / 10; //Remove the floating point
i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); // Check the parity of the divider
i2sdiv = (uint16_t)((tmp - i2sodd) / 2); // Compute the i2sdiv prescaler
i2sodd = (uint16_t) (i2sodd & lt; & lt; 8); // Get the Mask for the Odd bit (SPI_I2SPR[8]) register
}
if ((i2sdiv & lt; 2) || (i2sdiv & gt; 0xFF)) // Test if the divider is 1 or 0 or greater than 0xFF
{
i2sdiv = 2; //Set the default values
i2sodd = 0;
}
SPIx- & gt; I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStructure.I2S_MCLKOutput)); // Write to SPIx I2SPR register the computed value
/* Configure the I2S with the SPI_InitStruct values */
tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStructure.I2S_Mode | \
(uint16_t)(I2S_InitStructure.I2S_Standard | (uint16_t)(I2S_InitStructure.I2S_DataFormat | \
(uint16_t)I2S_InitStructure.I2S_CPOL))));
SPIx- & gt; I2SCFGR = tmpreg; // Write to SPIx I2SCFGR
if ((CODEC_I2S- & gt; I2SCFGR & I2S_ENABLE_MASK) == 0) // If the I2S peripheral is still not enabled, enable it
{
I2S_Cmd(CODEC_I2S, ENABLE);
}
}



/**
* @brief Enables or disables the specified SPI peripheral (in I2S mode).
* @param SPIx: where x can be 2 or 3 to select the SPI peripheral (or I2Sxext
* for full duplex mode).
* @param NewState: new state of the SPIx peripheral.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
{
if (NewState != DISABLE)
{
SPIx- & gt; I2SCFGR |= SPI_I2SCFGR_I2SE; // Enable the selected SPI peripheral (in I2S mode)
}
else
{
SPIx- & gt; I2SCFGR & = (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE); // Disable the selected SPI peripheral in I2S mode
}
}


/**
* @brief Enables or disables the SPIx/I2Sx DMA interface.
* @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
* in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
* @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
* @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
* @param NewState: new state of the selected SPI DMA transfer request.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
{
if (NewState != DISABLE)
{
SPIx- & gt; CR2 |= SPI_I2S_DMAReq; // Enable the selected SPI DMA requests
}
else
{
SPIx- & gt; CR2 & = (uint16_t)~SPI_I2S_DMAReq;// Disable the selected SPI DMA requests
}
}


wma_dec.ZIP > codeccontext.h

/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( & lt; _ & gt; ) \___| & lt; | \_\ ( & lt; _ & gt; & gt; & lt; & lt;
* Firmware |____|_ /\____/ \___ & gt; __|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id: $
*
* Copyright (C) 2005 Dave Chapman
*
* All files in this archive are subject to the GNU General Public License.
* See the file COPYING in the source tree root for full license agreement.
*
* This software is distributed on an " AS IS " basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/

#ifndef CODECCTX_H
#define CODECCTX_H

/**
* external api header. 01/04/06 Marsdaddy & lt; pajojo@gmail.com & gt;
*/


#ifdef __cplusplus
extern " C "
#endif

struct AVCodec;

enum CodecID {
CODEC_ID_NONE,
CODEC_ID_MPEG1VIDEO,
CODEC_ID_MPEG2VIDEO, /* prefered ID for MPEG Video 1 or 2 decoding */
CODEC_ID_MPEG2VIDEO_XVMC,
CODEC_ID_H263,
CODEC_ID_RV10,
CODEC_ID_RV20,
CODEC_ID_MP2,
CODEC_ID_MP3, /* prefered ID for MPEG Audio layer 1, 2 or3 decoding */
CODEC_ID_VORBIS,
CODEC_ID_AC3,
CODEC_ID_MJPEG,
CODEC_ID_MJPEGB,
CODEC_ID_LJPEG,
CODEC_ID_SP5X,
CODEC_ID_MPEG4,
CODEC_ID_RAWVIDEO,
CODEC_ID_MSMPEG4V1,
CODEC_ID_MSMPEG4V2,
CODEC_ID_MSMPEG4V3,
CODEC_ID_WMV1,
CODEC_ID_WMV2,
CODEC_ID_H263P,
CODEC_ID_H263I,
CODEC_ID_FLV1,
CODEC_ID_SVQ1,
CODEC_ID_SVQ3,
CODEC_ID_DVVIDEO,
CODEC_ID_DVAUDIO,
CODEC_ID_WMAV1,
CODEC_ID_WMAV2,
CODEC_ID_MACE3,
CODEC_ID_MACE6,
CODEC_ID_HUFFYUV,
CODEC_ID_CYUV,
CODEC_ID_H264,
CODEC_ID_INDEO3,
CODEC_ID_VP3,
CODEC_ID_THEORA,
CODEC_ID_AAC,
CODEC_ID_MPEG4AAC,
CODEC_ID_ASV1,
CODEC_ID_ASV2,
CODEC_ID_FFV1,
CODEC_ID_4XM,
CODEC_ID_VCR1,
CODEC_ID_CLJR,
CODEC_ID_MDEC,
CODEC_ID_ROQ,
CODEC_ID_INTERPLAY_VIDEO,
CODEC_ID_XAN_WC3,
CODEC_ID_XAN_WC4,
CODEC_ID_RPZA,
CODEC_ID_CINEPAK,
CODEC_ID_WS_VQA,
CODEC_ID_MSRLE,
CODEC_ID_MSVIDEO1,
CODEC_ID_IDCIN,
CODEC_ID_8BPS,
CODEC_ID_SMC,
CODEC_ID_FLIC,
CODEC_ID_TRUEMOTION1,
CODEC_ID_VMDVIDEO,
CODEC_ID_VMDAUDIO,
CODEC_ID_MSZH,
CODEC_ID_ZLIB,
CODEC_ID_QTRLE,

/* various pcm " codecs " */
CODEC_ID_PCM_S16LE,
CODEC_ID_PCM_S16BE,
CODEC_ID_PCM_U16LE,
CODEC_ID_PCM_U16BE,
CODEC_ID_PCM_S8,
CODEC_ID_PCM_U8,
CODEC_ID_PCM_MULAW,
CODEC_ID_PCM_ALAW,

/* various adpcm codecs */
CODEC_ID_ADPCM_IMA_QT,
CODEC_ID_ADPCM_IMA_WAV,
CODEC_ID_ADPCM_IMA_DK3,
CODEC_ID_ADPCM_IMA_DK4,
CODEC_ID_ADPCM_IMA_WS,
CODEC_ID_ADPCM_IMA_SMJPEG,
CODEC_ID_ADPCM_MS,
CODEC_ID_ADPCM_4XM,
CODEC_ID_ADPCM_XA,
CODEC_ID_ADPCM_ADX,
CODEC_ID_ADPCM_EA,

/* AMR */
CODEC_ID_AMR_NB,
CODEC_ID_AMR_WB,

/* RealAudio codecs*/
CODEC_ID_RA_144,
CODEC_ID_RA_288,

/* various DPCM codecs */
CODEC_ID_ROQ_DPCM,
CODEC_ID_INTERPLAY_DPCM,
CODEC_ID_XAN_DPCM,

CODEC_ID_MPEG2TS, /* _FAKE_ codec to indicate a raw MPEG2 transport
stream (only used by libavformat) */
};


enum CodecType {
CODEC_TYPE_UNKNOWN = -1,
CODEC_TYPE_VIDEO,
CODEC_TYPE_AUDIO,
CODEC_TYPE_DATA,
};



#define FF_I_TYPE 1 // Intra
#define FF_P_TYPE 2 // Predicted
#define FF_B_TYPE 3 // Bi-dir predicted


/**
* Required number of additionally allocated bytes at the end of the input bitstream for decoding.
* this is mainly needed because some optimized bitstream readers read
* 32 or 64 bit at once and could read over the end & lt; br & gt;
* Note, if the first 23 bits of the additional bytes are not 0 then damaged
* MPEG bitstreams could cause overread and segfault
*/
#define FF_INPUT_BUFFER_PADDING_SIZE 8



/**
* main external api structure.
*/
typedef struct CodecContext {
/**
* the average bitrate.
* - encoding: set by user. unused for constant quantizer encoding
* - decoding: set by lavc. 0 or some bitrate if this info is available in the stream
*/
int bit_rate;

/* audio only */
unsigned short sample_rate; /// & lt; samples per sec
char bits_per_sample;
unsigned char channels;

/**
* number of bits the bitstream is allowed to diverge from the reference.
* the reference can be CBR (for CBR pass1) or VBR (for pass2)
* - encoding: set by user. unused for constant quantizer encoding
* - decoding: unused
*/
// int bit_rate_tolerance;

/**
* CODEC_FLAG_*.
* - encoding: set by user.
* - decoding: set by user.
*/
// int flags;

/**
* some codecs needs additionnal format info. It is stored here
* - encoding: set by user.
* - decoding: set by lavc. (FIXME is this ok?)
*/
// int sub_id;

/**
* motion estimation algorithm used for video coding.
* - encoding: MUST be set by user.
* - decoding: unused
*/
// int me_method;

/**
* some codecs need / can use extra-data like huffman tables.
* mjpeg: huffman tables
* rv10: additional flags
* mpeg4: global headers (they can be in the bitstream or here)
* - encoding: set/allocated/freed by lavc.
* - decoding: set/allocated/freed by user.
*/
unsigned char/*void*/ *extradata;
unsigned char/*int*/ extradata_size;

/* video only */
/**
* frames per sec multiplied by frame_rate_base.
* for variable fps this is the precission, so if the timestamps
* can be specified in msec precssion then this is 1000*frame_rate_base
* - encoding: MUST be set by user
* - decoding: set by lavc. 0 or the frame_rate if available
*/
// int frame_rate;

/**
* width / height.
* - encoding: MUST be set by user.
* - decoding: set by user if known, codec should override / dynamically change if needed
*/
// int width, height;

//#define FF_ASPECT_SQUARE 1
//#define FF_ASPECT_4_3_625 2
//#define FF_ASPECT_4_3_525 3
//#define FF_ASPECT_16_9_625 4
//#define FF_ASPECT_16_9_525 5
//#define FF_ASPECT_EXTENDED 15

/**
* the number of pictures in a group of pitures, or 0 for intra_only.
* - encoding: set by user.
* - decoding: unused
*/
// int gop_size;

/**
* Frame rate emulation. If not zero lower layer (i.e. format handler)
* has to read frames at native frame rate.
* - encoding: set by user.
* - decoding: unused.
*/
// int rate_emu;

// int sample_fmt; /// & lt; sample format, currenly unused

/* the following data should not be initialized */
int frame_size; /// & lt; in samples, initialized when calling 'init'
int frame_number; /// & lt; audio or video frame number
// int real_pict_num; /// & lt; returns the real picture number of previous encoded frame

struct AVCodec *codec;

void *priv_data; // PJJ

/* statistics, used for 2-pass encoding */
// int mv_bits;
// int header_bits;
// int i_tex_bits;
// int p_tex_bits;
// int i_count;
// int p_count;
// int skip_count;
// int misc_bits;

/**
* number of bits used for the previously encoded frame.
* - encoding: set by lavc
* - decoding: unused
*/
// int frame_bits;

/**
* private data of the user, can be used to carry app specific stuff.
* - encoding: set by user
* - decoding: set by user
*/
// void *opaque;

char codec_name[10/*32*/];
enum CodecType codec_type; /* see CODEC_TYPE_xxx */
enum CodecID codec_id; /* see CODEC_ID_xxx */

/**
* fourcc (LSB first, so " ABCD " - & gt; ('D' & lt; & lt; 24) + ('C' & lt; & lt; 16) + ('B' & lt; & lt; 8) + 'A').
* this is used to workaround some encoder bugs
* - encoding: set by user, if not then the default based on codec_id will be used
* - decoding: set by user, will be converted to upper case by lavc during init
*/
// unsigned int codec_tag;

/**
* workaround bugs in encoders which sometimes cannot be detected automatically.
* - encoding: unused
* - decoding: set by user
*/
// int workaround_bugs;
/*#define FF_BUG_AUTODETECT 1 /// autodetection
#define FF_BUG_OLD_MSMPEG4 2
#define FF_BUG_XVID_ILACE 4
#define FF_BUG_UMP4 8
#define FF_BUG_NO_PADDING 16
#define FF_BUG_AC_VLC 0 /// will be removed, libavcodec can now handle these non compliant files by default
#define FF_BUG_QPEL_CHROMA 64
#define FF_BUG_STD_QPEL 128
#define FF_BUG_QPEL_CHROMA2 256
#define FF_BUG_DIRECT_BLOCKSIZE 512
#define FF_BUG_EDGE 1024 */

int block_align; /// & lt; used by some WAV based audio codecs
short *outBuf_start_address; //pocz?tek bufora z danymi do DAC
short *outBuf_pointer; //adres, od którego b?dzie wype?niany bufor z danymi do DAC
int size_outBuf; //wielkośae bufora outBuf w bajtach
//
// int size_outBuf;

/* int parse_only; /* - decoding only: if true, only parsing is done
(function avcodec_parse_frame()). The frame
data is returned. Only MPEG codecs support this now. */

/**
* 0- & gt; h263 quant 1- & gt; mpeg quant.
* - encoding: set by user.
* - decoding: unused
*/
// int mpeg_quant;

/**
* pass1 encoding statistics output buffer.
* - encoding: set by lavc
* - decoding: unused
*/
// char *stats_out;

/**
* pass2 encoding statistics input buffer.
* concatenated stuff from stats_out of pass1 should be placed here
* - encoding: allocated/set/freed by user
* - decoding: unused
*/
// char *stats_in;

// int rc_override_count;

/**
* rate control equation.
* - encoding: set by user
* - decoding: unused
*/
// char *rc_eq;

// uint64_t error[4];

/**
* minimum MB quantizer.
* - encoding: set by user.
* - decoding: unused
*/
// int mb_qmin;

/**
* maximum MB quantizer.
* - encoding: set by user.
* - decoding: unused
*/
// int mb_qmax;

/**
* motion estimation compare function.
* - encoding: set by user.
* - decoding: unused
*/
// int me_cmp;
/**
* subpixel motion estimation compare function.
* - encoding: set by user.
* - decoding: unused
*/
// int me_sub_cmp;
/**
* macroblock compare function (not supported yet).
* - encoding: set by user.
* - decoding: unused
*/
// int mb_cmp;
/**
* interlaced dct compare function
* - encoding: set by user.
* - decoding: unused
*/
// int ildct_cmp;
/*#define FF_CMP_SAD 0
#define FF_CMP_SSE 1
#define FF_CMP_SATD 2
#define FF_CMP_DCT 3
#define FF_CMP_PSNR 4
#define FF_CMP_BIT 5
#define FF_CMP_RD 6
#define FF_CMP_ZERO 7
#define FF_CMP_VSAD 8
#define FF_CMP_VSSE 9
#define FF_CMP_CHROMA 256

/**
* ME diamond size & shape.
* - encoding: set by user.
* - decoding: unused
*/
// int dia_size;

/**
* amount of previous MV predictors (2a+1 x 2a+1 square).
* - encoding: set by user.
* - decoding: unused
*/
// int last_predictor_count;

/**
* pre pass for motion estimation.
* - encoding: set by user.
* - decoding: unused
*/
// int pre_me;

/**
* motion estimation pre pass compare function.
* - encoding: set by user.
* - decoding: unused
*/
// int me_pre_cmp;

/**
* ME pre pass diamond size & shape.
* - encoding: set by user.
* - decoding: unused
*/
// int pre_dia_size;

/**
* subpel ME quality.
* - encoding: set by user.
* - decoding: unused
*/
// int me_subpel_quality;

/**
* Maximum motion estimation search range in subpel units.
* if 0 then no limit
*
* - encoding: set by user.
* - decoding: unused.
*/
// int me_range;

/**
* frame_rate_base.
* for variable fps this is 1
* - encoding: set by user.
* - decoding: set by lavc.
* @todo move this after frame_rate
*/

// int frame_rate_base;
/**
* intra quantizer bias.
* - encoding: set by user.
* - decoding: unused
*/
// int intra_quant_bias;
//#define FF_DEFAULT_QUANT_BIAS 999999

/**
* inter quantizer bias.
* - encoding: set by user.
* - decoding: unused
*/
// int inter_quant_bias;

/**
* color table ID.
* - encoding: unused.
* - decoding: which clrtable should be used for 8bit RGB images
* table have to be stored somewhere FIXME
*/
// int color_table_id;

/**
* internal_buffer count.
* Dont touch, used by lavc default_get_buffer()
*/
// int internal_buffer_count;

/**
* internal_buffers.
* Dont touch, used by lavc default_get_buffer()
*/
// void *internal_buffer;

/**
* global quality for codecs which cannot change it per frame.
* this should be proportional to MPEG1/2/4 qscale.
* - encoding: set by user.
* - decoding: unused
*/
// int global_quality;

//#define FF_CODER_TYPE_VLC 0
//#define FF_CODER_TYPE_AC 1
/**
* coder type
* - encoding: set by user.
* - decoding: unused
*/
// int coder_type;

/**
* context model
* - encoding: set by user.
* - decoding: unused
*/
// int context_model;

/**
* slice flags
* - encoding: unused
* - decoding: set by user.
*/
// int slice_flags;
/*#define SLICE_FLAG_CODED_ORDER 0x0001 /// & lt; draw_horiz_band() is called in coded order instead of display
#define SLICE_FLAG_ALLOW_FIELD 0x0002 /// & lt; allow draw_horiz_band() with field slices (MPEG2 field pics)
#define SLICE_FLAG_ALLOW_PLANE 0x0004 /// & lt; allow draw_horiz_band() with 1 component at a time (SVQ1)

/**
* XVideo Motion Acceleration
* - encoding: forbidden
* - decoding: set by decoder
*/
// int xvmc_acceleration;

/**
* macroblock decision mode
* - encoding: set by user.
* - decoding: unused
*/
// int mb_decision;
/*#define FF_MB_DECISION_SIMPLE 0 /// & lt; uses mb_cmp
#define FF_MB_DECISION_BITS 1 /// & lt; chooses the one which needs the fewest bits
#define FF_MB_DECISION_RD 2 /// & lt; rate distoration

/**
* custom intra quantization matrix
* - encoding: set by user, can be NULL
* - decoding: set by lavc
*/
// uint16_t *intra_matrix;

/**
* custom inter quantization matrix
* - encoding: set by user, can be NULL
* - decoding: set by lavc
*/
// uint16_t *inter_matrix;

/**
* fourcc from the AVI stream header (LSB first, so " ABCD " - & gt; ('D' & lt; & lt; 24) + ('C' & lt; & lt; 16) + ('B' & lt; & lt; 8) + 'A').
* this is used to workaround some encoder bugs
* - encoding: unused
* - decoding: set by user, will be converted to upper case by lavc during init
*/
// unsigned int stream_codec_tag;

/**
* scene change detection threshold.
* 0 is default, larger means fewer detected scene changes
* - encoding: set by user.
* - decoding: unused
*/
// int scenechange_threshold;

/**
* minimum lagrange multipler
* - encoding: set by user.
* - decoding: unused
*/
// int lmin;

/**
* maximum lagrange multipler
* - encoding: set by user.
* - decoding: unused
*/
// int lmax;

/**
* noise reduction strength
* - encoding: set by user.
* - decoding: unused
*/
// int noise_reduction;

/**
* simulates errors in the bitstream to test error concealment.
* - encoding: set by user.
* - decoding: unused.
*/
// int error_rate;

/**
* MP3 antialias algorithm, see FF_AA_* below.
* - encoding: unused
* - decoding: set by user
*/
// int antialias_algo;
/*#define FF_AA_AUTO 0
#define FF_AA_FASTINT 1 //not implemented yet
#define FF_AA_INT 2
#define FF_AA_FLOAT 3
/**
* Quantizer noise shaping.
* - encoding: set by user
* - decoding: unused
*/
// int quantizer_noise_shaping;
} CodecContext;


/**
* AVOption.
*/
//typedef struct AVOption {
/** options' name */
// const char *name; /* if name is NULL, it indicates a link to next */
/** short English text help or const struct AVOption* subpointer */
// const char *help; // const struct AVOption* sub;
/** offset to context structure where the parsed value should be stored */
// int offset;
/** options' type */
// int type;
//#define FF_OPT_TYPE_BOOL 1 /// & lt; boolean - true,1,on (or simply presence)
//#define FF_OPT_TYPE_DOUBLE 2 /// & lt; double
//#define FF_OPT_TYPE_INT 3 /// & lt; integer
//#define FF_OPT_TYPE_STRING 4 /// & lt; string (finished with \0)
//#define FF_OPT_TYPE_MASK 0x1f /// & lt; mask for types - upper bits are various flags
//#define FF_OPT_TYPE_EXPERT 0x20 // flag for expert option
//#define FF_OPT_TYPE_FLAG (FF_OPT_TYPE_BOOL | 0x40)
//#define FF_OPT_TYPE_RCOVERRIDE (FF_OPT_TYPE_STRING | 0x80)
/** min value (min == max - & gt; no limits) */
// double min;
/** maximum value for double/int */
// double max;
/** default boo [0,1]l/double/int value */
// double defval;
/**
* default string value (with optional semicolon delimited extra option-list
* i.e. option1;option2;option3
* defval might select other then first argument as default
*/
// const char *defstr;
//#define FF_OPT_MAX_DEPTH 10
//} AVOption;

/**
* AVCodec.
*/
typedef struct AVCodec {
const char *name;
enum CodecType type;
int id;
int priv_data_size;
int (*init)(CodecContext *);
// int (*encode)(CodecContext *, unsigned char *buf, int buf_size, void *data);
int (*close)(CodecContext *);
int (*decode)(CodecContext *, void *outdata, int *outdata_size,
unsigned char *buf, int buf_size);
// int capabilities;
// const AVOption *options;
struct AVCodec *next;
// void (*flush)(CodecContext *);
} AVCodec;


/* frame parsing */
typedef struct AVCodecParserContext {
void *priv_data;
struct AVCodecParser *parser;
int/*long long*/ frame_offset; /* offset of the current frame */
int/*long long*/ cur_offset; /* current offset
(incremented by each av_parser_parse()) */
int/*long long*/ last_frame_offset; /* offset of the last frame */
/* video info */
// int pict_type; /* XXX: put it back in AVCodecContext */
// int repeat_pict; /* XXX: put it back in AVCodecContext */
int/*long long*/ pts; /* pts of the current frame */
int/*long long*/ dts; /* dts of the current frame */

/* private data */
int/*long long*/ last_pts;
int/*long long*/ last_dts;

#define AV_PARSER_PTS_NB 4
int cur_frame_start_index;
int/*long long*/ cur_frame_offset[AV_PARSER_PTS_NB];
int/*long long*/ cur_frame_pts[AV_PARSER_PTS_NB];
int/*long long*/ cur_frame_dts[AV_PARSER_PTS_NB];
} AVCodecParserContext;

typedef struct AVCodecParser {
int codec_ids[3]; /* several codec IDs are permitted */
int priv_data_size;
int (*parser_init)(AVCodecParserContext *s);
int (*parser_parse)(AVCodecParserContext *s,
CodecContext *avctx,
unsigned char **poutbuf, int *poutbuf_size,
const unsigned char *buf, int buf_size);
void (*parser_close)(AVCodecParserContext *s);
struct AVCodecParser *next;
} AVCodecParser;

extern AVCodecParser *av_first_parser;

AVCodecParserContext *av_parser_init(int codec_id);
int av_parser_parse(AVCodecParserContext *s,
CodecContext *avctx,
unsigned char **poutbuf, int *poutbuf_size,
const unsigned char *buf, int buf_size,
long long pts, long long dts);

/* external high level API */
void avcodec_get_context_defaults(CodecContext *s);
void register_avcodec(AVCodec *format);
AVCodec *avcodec_find_decoder(enum CodecID id);

/**
* opens / inits the AVCodecContext.
* not thread save!
*/
int avcodec_open(CodecContext *avctx, AVCodec *codec);
int avcodec_decode_audio(CodecContext *avctx, short *samples,
int *frame_size_ptr,
unsigned char *buf, int buf_size);

/* memory */
void *av_malloc(unsigned int size);
void *av_mallocz(unsigned int size);
void *av_realloc(void *ptr, unsigned int size);
void *av_fast_realloc(void *ptr, unsigned int *size, unsigned int min_size);
#define av_freep(p) __av_freepy((void **)(p))


#endif /* CODECCTX_H */


wma_dec.ZIP > main.c

#include " includes.h "
#include " demo.h "



typedef struct
{
unsigned char *Flash_dataPtr;
int Flash_dataOffset; //offset potrzebnych danych (od pocz?tku pliku)
unsigned int data_size;
}file_data;

file_data fdata;

int read_data(file_data *data_stream, unsigned char *buffer_Ptr, int bytes_to_copy)
{//ta funkcja ma kopiowaae do buffer_Ptr z data_stream_Ptr ilośae bajtów określon? zmienn? bytes_to_copy.
unsigned int bytes_copied = bytes_to_copy;
unsigned char *src;
src = data_stream- & gt; Flash_dataPtr + data_stream- & gt; Flash_dataOffset;
memcpy(buffer_Ptr, src, bytes_to_copy);
//data_stream- & gt; Flash_dataOffset = data_stream- & gt; Flash_dataOffset + bytes_copied;
return bytes_copied;
}


int seek_data(file_data *data_stream, offset_t offset, int whence)
{ /*ta funkcja teraz odpowiednio ustawia wskaźnik data_streamOffset zale?nie od wartości offset
W przypadku pobierania danych z karty SD, funkcja ta b?dzie musieae dogrywaae odpowiednie dane z bloków karty i
wpisywaae te dane do data_stream_Ptr */
data_stream- & gt; Flash_dataOffset = offset;
}


int f_read(void *read_func, unsigned char *buf_Ptr, int bytes_to_copy)
{
unsigned short bytes_copied;
bytes_copied = read_data( & fdata, buf_Ptr, bytes_to_copy);
fdata.Flash_dataOffset = fdata.Flash_dataOffset + bytes_copied;
return bytes_copied;
}



int f_seek(void *seek_func, offset_t offset, int whence)
{
seek_data( & fdata, offset, whence);
}




int main(void)
{
AVFormatContext *ic = NULL;
CodecContext *wma;
AVCodec *codec;
AVInputFormat *fmt;
AVPacket pkt;
ByteIOContext bioc;
AVProbeData pd;
unsigned char *file_buffer;
unsigned char filename[15] = " nazwa_pliku_wma " ;
unsigned int size, size_outBuf;
unsigned char i;
int len;
static void *data;
unsigned int communication_OK;

config_clk();//konfig zegarów systemowych
config_PLLI2S(0);
config_IO_port(); //konfig linii IO
config_I2C(I2C1); //konfig interfejsu I2C(1) do komunikacji z kodekiem
reset_codec(); //reset kodeka CS43L22

communication_OK = config_codec(AUDIO_INTERFACE_I2S, OUTPUT_DEVICE_AUTO, 200 /*volume*/); //konfig kodeka CS43L22
while(1)
{
fdata.Flash_dataPtr = rawData;
fdata.Flash_dataOffset = 0; //odczyt od pocz?tku pliku
fdata.data_size = sizeof(rawData);
file_buffer = malloc(1024 * sizeof(unsigned char)); //w tym buforze jest fragment pliku WMA (np.odczytany z karty SD)
av_register_all();
read_data( & fdata, file_buffer, 1024); //tu wype?nienie file_buffer fragmentem pliku WMA
pd.buf = file_buffer; //dekodowanie WMA z bufora RAM przechowuj?cego fragment danych pliku WMA (np. odczytanych z karty SD)
pd.buf_size = 1024;
pd.filename = filename;
fmt = av_probe_input_format( & pd, 1);
init_put_byte( & bioc, file_buffer, 1024, 0, 0, f_read, 0, f_seek);
if(av_open_input_stream( & ic, & bioc, filename, fmt/*, NULL*/) & lt; 0)
{
debug_printf( " Error: %s\n " , filename);
return 1;//exit(1);
}
for(i = 0; i & lt; ic- & gt; nb_streams; i++)
{
wma = & ic- & gt; streams[i]- & gt; codec;
if(wma- & gt; codec_type == CODEC_TYPE_AUDIO)
break;
}

config_I2S(SPI3, AUDIO_INTERFACE_I2S, ((wma- & gt; sample_rate / 2) * wma- & gt; channels));//konfig SPI3 jako interfejsu I2S
Media_Audio_Init(AUDIO_INTERFACE_I2S);//Initializes and prepares the Media to perform audio data transfer from Media to the I2S peripheral.
codec = avcodec_find_decoder(wma- & gt; codec_id);
if (!codec) {
debug_printf( " Error: codec not found\n " );
return 1;
}
/* open it */
if (avcodec_open(wma, codec) & lt; 0) {
debug_printf( " Error: could not open codec\n " );
return 1;
}
data = wma- & gt; outBuf_start_address;
size_outBuf = wma- & gt; size_outBuf;
for(;;)
{
if (av_read_frame(ic, & pkt) & lt; 0)
break;
size = pkt.size;
while (size & gt; 0)
{
len = avcodec_decode_audio(wma, data, & size_outBuf, pkt.data, size);
if (len & lt; 0)
{
break;
}
if (size_outBuf & lt; = 0)
{
continue;
}
if (size_outBuf & gt; 0)
{

// debug_printf( " The audio frame size is %d\n " , size_outBuf);
/*if(fwrite(outbuf, 1, out_size, outfile) & lt; = 0) //nie robi? pliku WAV
{
fprintf(ble, " Error: not data write in output file\n " );
goto end;
} */

}
size -= len;
data = wma- & gt; outBuf_pointer;
}
av_free_packet( & pkt); //dopisa?em - zwolnienie pami?ci po zdekodowaniu pakietu
}
decode_last_superframe(wma, data, & size_outBuf);
GPIOD- & gt; BSRRH = (GPIO_BSRR_BR_12) & gt; & gt; 16; //zgaszenie zapalonej zielonej LED (BSRRH jest starsz?, 16-bit po?ow? rejestru BSRR, dlatego GPIO_BSRR_BR_12 (32-bit liczba) trzeba przesun?ae w prawo o 16 bitów
wma- & gt; codec- & gt; close(wma);
av_free(ic- & gt; streams[0]- & gt; priv_data);
av_free(ic- & gt; streams[0]);
av_free(ic- & gt; priv_data);
av_free(ic);
free(file_buffer);
}
}


wma_dec.ZIP > avio.h

#ifndef AVIO_H
#define AVIO_H

#include " codeccontext.h "

typedef struct CodecTag {
int id;
unsigned int tag;
// unsigned int invalid_asf : 1;
} CodecTag;



typedef struct {
unsigned char *buffer;
int buffer_size;
unsigned char *buf_ptr, *buf_end;
void *opaque;
int (*read_packet)(void *opaque, unsigned char *buf, int buf_size);
// void (*write_packet)(void *opaque, unsigned char *buf, int buf_size);
int (*seek)(void *opaque, long long offset, int whence);
int pos; /* position in the file of the current buffer */
// int must_flush; /* true if the next seek should flush */
int eof_reached; /* true if eof reached */
int write_flag; /* true if open for writing */
//int is_streamed;
// int max_packet_size;
} ByteIOContext;



/* unbuffered I/O */

struct URLContext {
struct URLProtocol *prot;
// int flags;
// int is_streamed; /* true if streamed (no seek possible), default = false */
// int max_packet_size; /* if non zero, the stream is packetized with this max packet size */
// void *priv_data;
// char filename[1]; /* specified filename */
};

typedef struct URLContext URLContext;


typedef struct URLProtocol {
const char *name;
int (*url_open)(URLContext *h, const char *filename, int flags);
int (*url_read)(URLContext *h, unsigned char *buf, int size);
// int (*url_write)(URLContext *h, unsigned char *buf, int size);
long long (*url_seek)(URLContext *h, long long pos, int whence);
int (*url_close)(URLContext *h);
struct URLProtocol *next;
} URLProtocol;

extern URLProtocol *first_protocol;


int init_put_byte(ByteIOContext *s,
unsigned char *buffer,
int buffer_size,
int write_flag,
void *opaque,
int (*read_packet)(void *opaque, unsigned char *buf, int buf_size), //wskaźnik do funkcji wype?niaj?cej buf danymi z opaque
void (*write_packet)(void *opaque, unsigned char *buf, int buf_size),
int (*seek)(void *opaque, long long offset, int whence)); //wskaźnik do funkcji ustawiaj?cej wskaźnik opaque zale?nie od wartości offset


long long url_fseek(ByteIOContext *s, long long offset, int whence);
long long url_filesize(URLContext *h);
long long url_seek(URLContext *h, long long pos, int whence);

int get_buffer(ByteIOContext *s, unsigned char *buf, int size);
int get_byte(ByteIOContext *s);
unsigned int get_le32(ByteIOContext *s);
unsigned long long get_le64(ByteIOContext *s);
unsigned int get_le16(ByteIOContext *s);

void url_fskip(ByteIOContext *s, long long offset);
long long url_ftell(ByteIOContext *s);
int url_feof(ByteIOContext *s);
URLContext *url_fileno(ByteIOContext *s);


int wav_codec_get_id(unsigned int tag, int bps);
void get_wav_header(ByteIOContext *pb, CodecContext *codec, int size);


enum CodecID codec_get_id(const CodecTag *tags, unsigned int tag);
#endif


wma_dec.ZIP > stm32f4xx_spi.h

/**
******************************************************************************
* @file stm32f4xx_spi.h
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the SPI
* firmware library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* & lt; h2 & gt; & lt; center & gt; & copy; COPYRIGHT 2011 STMicroelectronics & lt; /center & gt; & lt; /h2 & gt;
******************************************************************************
*/

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_SPI_H
#define __STM32F4xx_SPI_H

#ifdef __cplusplus
extern " C " {
#endif

/* Includes ------------------------------------------------------------------*/
#include " stm32f4xx.h "

/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/

/** @addtogroup SPI
* @{
*/

/* Exported types ------------------------------------------------------------*/

/**
* @brief SPI Init structure definition
*/

typedef struct
{
uint16_t SPI_Direction; /*! & lt; Specifies the SPI unidirectional or bidirectional data mode.
This parameter can be a value of @ref SPI_data_direction */

uint16_t SPI_Mode; /*! & lt; Specifies the SPI operating mode.
This parameter can be a value of @ref SPI_mode */

uint16_t SPI_DataSize; /*! & lt; Specifies the SPI data size.
This parameter can be a value of @ref SPI_data_size */

uint16_t SPI_CPOL; /*! & lt; Specifies the serial clock steady state.
This parameter can be a value of @ref SPI_Clock_Polarity */

uint16_t SPI_CPHA; /*! & lt; Specifies the clock active edge for the bit capture.
This parameter can be a value of @ref SPI_Clock_Phase */

uint16_t SPI_NSS; /*! & lt; Specifies whether the NSS signal is managed by
hardware (NSS pin) or by software using the SSI bit.
This parameter can be a value of @ref SPI_Slave_Select_management */

uint16_t SPI_BaudRatePrescaler; /*! & lt; Specifies the Baud Rate prescaler value which will be
used to configure the transmit and receive SCK clock.
This parameter can be a value of @ref SPI_BaudRate_Prescaler
@note The communication clock is derived from the master
clock. The slave clock does not need to be set. */

uint16_t SPI_FirstBit; /*! & lt; Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref SPI_MSB_LSB_transmission */

uint16_t SPI_CRCPolynomial; /*! & lt; Specifies the polynomial used for the CRC calculation. */
}SPI_InitTypeDef;

/**
* @brief I2S Init structure definition
*/

typedef struct
{

uint16_t I2S_Mode; /*! & lt; Specifies the I2S operating mode.
This parameter can be a value of @ref I2S_Mode */

uint16_t I2S_Standard; /*! & lt; Specifies the standard used for the I2S communication.
This parameter can be a value of @ref I2S_Standard */

uint16_t I2S_DataFormat; /*! & lt; Specifies the data format for the I2S communication.
This parameter can be a value of @ref I2S_Data_Format */

uint16_t I2S_MCLKOutput; /*! & lt; Specifies whether the I2S MCLK output is enabled or not.
This parameter can be a value of @ref I2S_MCLK_Output */

uint32_t I2S_AudioFreq; /*! & lt; Specifies the frequency selected for the I2S communication.
This parameter can be a value of @ref I2S_Audio_Frequency */

uint16_t I2S_CPOL; /*! & lt; Specifies the idle state of the I2S clock.
This parameter can be a value of @ref I2S_Clock_Polarity */
}I2S_InitTypeDef;

/* Exported constants --------------------------------------------------------*/

/** @defgroup SPI_Exported_Constants
* @{
*/

#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
((PERIPH) == SPI2) || \
((PERIPH) == SPI3))

#define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \
((PERIPH) == SPI2) || \
((PERIPH) == SPI3) || \
((PERIPH) == I2S2ext) || \
((PERIPH) == I2S3ext))

#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
((PERIPH) == SPI3))

#define IS_SPI_23_PERIPH_EXT(PERIPH) (((PERIPH) == SPI2) || \
((PERIPH) == SPI3) || \
((PERIPH) == I2S2ext) || \
((PERIPH) == I2S3ext))

#define IS_I2S_EXT_PERIPH(PERIPH) (((PERIPH) == I2S2ext) || \
((PERIPH) == I2S3ext))


/** @defgroup SPI_data_direction
* @{
*/

#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
((MODE) == SPI_Direction_2Lines_RxOnly) || \
((MODE) == SPI_Direction_1Line_Rx) || \
((MODE) == SPI_Direction_1Line_Tx))
/**
* @}
*/

/** @defgroup SPI_mode
* @{
*/

#define SPI_Mode_Master ((uint16_t)0x0104)
#define SPI_Mode_Slave ((uint16_t)0x0000)
#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
((MODE) == SPI_Mode_Slave))
/**
* @}
*/

/** @defgroup SPI_data_size
* @{
*/

#define SPI_DataSize_16b ((uint16_t)0x0800)
#define SPI_DataSize_8b ((uint16_t)0x0000)
#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
((DATASIZE) == SPI_DataSize_8b))
/**
* @}
*/

/** @defgroup SPI_Clock_Polarity
* @{
*/

#define SPI_CPOL_Low ((uint16_t)0x0000)
#define SPI_CPOL_High ((uint16_t)0x0002)
#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
((CPOL) == SPI_CPOL_High))
/**
* @}
*/

/** @defgroup SPI_Clock_Phase
* @{
*/

#define SPI_CPHA_1Edge ((uint16_t)0x0000)
#define SPI_CPHA_2Edge ((uint16_t)0x0001)
#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
((CPHA) == SPI_CPHA_2Edge))
/**
* @}
*/

/** @defgroup SPI_Slave_Select_management
* @{
*/

#define SPI_NSS_Soft ((uint16_t)0x0200)
#define SPI_NSS_Hard ((uint16_t)0x0000)
#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
((NSS) == SPI_NSS_Hard))
/**
* @}
*/

/** @defgroup SPI_BaudRate_Prescaler
* @{
*/

#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
((PRESCALER) == SPI_BaudRatePrescaler_4) || \
((PRESCALER) == SPI_BaudRatePrescaler_8) || \
((PRESCALER) == SPI_BaudRatePrescaler_16) || \
((PRESCALER) == SPI_BaudRatePrescaler_32) || \
((PRESCALER) == SPI_BaudRatePrescaler_64) || \
((PRESCALER) == SPI_BaudRatePrescaler_128) || \
((PRESCALER) == SPI_BaudRatePrescaler_256))
/**
* @}
*/

/** @defgroup SPI_MSB_LSB_transmission
* @{
*/

#define SPI_FirstBit_MSB ((uint16_t)0x0000)
#define SPI_FirstBit_LSB ((uint16_t)0x0080)
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
((BIT) == SPI_FirstBit_LSB))
/**
* @}
*/

/** @defgroup SPI_I2S_Mode
* @{
*/

#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
#define I2S_Mode_MasterTx ((uint16_t)0x0200)
#define I2S_Mode_MasterRx ((uint16_t)0x0300)
#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
((MODE) == I2S_Mode_SlaveRx) || \
((MODE) == I2S_Mode_MasterTx)|| \
((MODE) == I2S_Mode_MasterRx))
/**
* @}
*/


/** @defgroup SPI_I2S_Standard
* @{
*/

#define I2S_Standard_Phillips ((uint16_t)0x0000)
#define I2S_Standard_MSB ((uint16_t)0x0010)
#define I2S_Standard_LSB ((uint16_t)0x0020)
#define I2S_Standard_PCMShort ((uint16_t)0x0030)
#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
((STANDARD) == I2S_Standard_MSB) || \
((STANDARD) == I2S_Standard_LSB) || \
((STANDARD) == I2S_Standard_PCMShort) || \
((STANDARD) == I2S_Standard_PCMLong))
/**
* @}
*/

/** @defgroup SPI_I2S_Data_Format
* @{
*/

#define I2S_DataFormat_16b ((uint16_t)0x0000)
#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
#define I2S_DataFormat_24b ((uint16_t)0x0003)
#define I2S_DataFormat_32b ((uint16_t)0x0005)
#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
((FORMAT) == I2S_DataFormat_16bextended) || \
((FORMAT) == I2S_DataFormat_24b) || \
((FORMAT) == I2S_DataFormat_32b))
/**
* @}
*/

/** @defgroup SPI_I2S_MCLK_Output
* @{
*/

#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
((OUTPUT) == I2S_MCLKOutput_Disable))
/**
* @}
*/

/** @defgroup SPI_I2S_Audio_Frequency
* @{
*/

#define I2S_AudioFreq_192k ((uint32_t)192000)
#define I2S_AudioFreq_96k ((uint32_t)96000)
#define I2S_AudioFreq_48k ((uint32_t)48000)
#define I2S_AudioFreq_44k ((uint32_t)44100)
#define I2S_AudioFreq_32k ((uint32_t)32000)
#define I2S_AudioFreq_22k ((uint32_t)22050)
#define I2S_AudioFreq_16k ((uint32_t)16000)
#define I2S_AudioFreq_11k ((uint32_t)11025)
#define I2S_AudioFreq_8k ((uint32_t)8000)
#define I2S_AudioFreq_Default ((uint32_t)2)

#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) & gt; = I2S_AudioFreq_8k) & & \
((FREQ) & lt; = I2S_AudioFreq_192k)) || \
((FREQ) == I2S_AudioFreq_Default))
/**
* @}
*/

/** @defgroup SPI_I2S_Clock_Polarity
* @{
*/

#define I2S_CPOL_Low ((uint16_t)0x0000)
#define I2S_CPOL_High ((uint16_t)0x0008)
#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
((CPOL) == I2S_CPOL_High))
/**
* @}
*/

/** @defgroup SPI_I2S_DMA_transfer_requests
* @{
*/

#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) & & ((DMAREQ) != 0x00))
/**
* @}
*/

/** @defgroup SPI_NSS_internal_software_management
* @{
*/

#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
((INTERNAL) == SPI_NSSInternalSoft_Reset))
/**
* @}
*/

/** @defgroup SPI_CRC_Transmit_Receive
* @{
*/

#define SPI_CRC_Tx ((uint8_t)0x00)
#define SPI_CRC_Rx ((uint8_t)0x01)
#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
/**
* @}
*/

/** @defgroup SPI_direction_transmit_receive
* @{
*/

#define SPI_Direction_Rx ((uint16_t)0xBFFF)
#define SPI_Direction_Tx ((uint16_t)0x4000)
#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
((DIRECTION) == SPI_Direction_Tx))
/**
* @}
*/

/** @defgroup SPI_I2S_interrupts_definition
* @{
*/

#define SPI_I2S_IT_TXE ((uint8_t)0x71)
#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
#define SPI_I2S_IT_ERR ((uint8_t)0x50)
#define I2S_IT_UDR ((uint8_t)0x53)
#define SPI_I2S_IT_TIFRFE ((uint8_t)0x58)

#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
((IT) == SPI_I2S_IT_RXNE) || \
((IT) == SPI_I2S_IT_ERR))

#define SPI_I2S_IT_OVR ((uint8_t)0x56)
#define SPI_IT_MODF ((uint8_t)0x55)
#define SPI_IT_CRCERR ((uint8_t)0x54)

#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))

#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE)|| ((IT) == SPI_I2S_IT_TXE) || \
((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \
((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\
((IT) == SPI_I2S_IT_TIFRFE))
/**
* @}
*/

/** @defgroup SPI_I2S_flags_definition
* @{
*/

#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
#define I2S_FLAG_UDR ((uint16_t)0x0008)
#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
#define SPI_FLAG_MODF ((uint16_t)0x0020)
#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
#define SPI_I2S_FLAG_TIFRFE ((uint16_t)0x0100)

#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
((FLAG) == SPI_I2S_FLAG_TIFRFE))
/**
* @}
*/

/** @defgroup SPI_CRC_polynomial
* @{
*/

#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) & gt; = 0x1)
/**
* @}
*/

/** @defgroup SPI_I2S_Legacy
* @{
*/

#define SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx
#define SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx
#define SPI_IT_TXE SPI_I2S_IT_TXE
#define SPI_IT_RXNE SPI_I2S_IT_RXNE
#define SPI_IT_ERR SPI_I2S_IT_ERR
#define SPI_IT_OVR SPI_I2S_IT_OVR
#define SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE
#define SPI_FLAG_TXE SPI_I2S_FLAG_TXE
#define SPI_FLAG_OVR SPI_I2S_FLAG_OVR
#define SPI_FLAG_BSY SPI_I2S_FLAG_BSY
#define SPI_DeInit SPI_I2S_DeInit
#define SPI_ITConfig SPI_I2S_ITConfig
#define SPI_DMACmd SPI_I2S_DMACmd
#define SPI_SendData SPI_I2S_SendData
#define SPI_ReceiveData SPI_I2S_ReceiveData
#define SPI_GetFlagStatus SPI_I2S_GetFlagStatus
#define SPI_ClearFlag SPI_I2S_ClearFlag
#define SPI_GetITStatus SPI_I2S_GetITStatus
#define SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit
/**
* @}
*/

/**
* @}
*/

/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/

/* Function used to set the SPI configuration to the default reset state *****/
void SPI_I2S_DeInit(SPI_TypeDef* SPIx);

/* Initialization and Configuration functions *********************************/
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);

void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct);

/* Data transfers functions ***************************************************/
void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);

/* Hardware CRC Calculation functions *****************************************/
void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
void SPI_TransmitCRC(SPI_TypeDef* SPIx);
uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);

/* DMA transfers management functions *****************************************/
void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);

/* Interrupts and flags management functions **********************************/
void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);

#ifdef __cplusplus
}
#endif

#endif /*__STM32F4xx_SPI_H */

/**
* @}
*/

/**
* @}
*/

/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


wma_dec.ZIP > wmadec_tab.c

/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( & lt; _ & gt; ) \___| & lt; | \_\ ( & lt; _ & gt; & gt; & lt; & lt;
* Firmware |____|_ /\____/ \___ & gt; __|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id: $
*
* Copyright (C) 2005 Dave Chapman
*
* All files in this archive are subject to the GNU General Public License.
* See the file COPYING in the source tree root for full license agreement.
*
* This software is distributed on an " AS IS " basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/

#include " includes.h "
/**
* Various WMA tables. 01/04/06 Marsdaddy & lt; pajojo@gmail.com & gt;
*/

const uint16_t wma_critical_freqs[25] = {
100, 200, 300, 400, 510, 630, 770, 920,
1080, 1270, 1480, 1720, 2000, 2320, 2700, 3150,
3700, 4400, 5300, 6400, 7700, 9500, 12000, 15500,
24500,
};

/* first value is number of bands */
const uint8_t exponent_band_22050[3][25] = {
{ 10, 4, 8, 4, 8, 8, 12, 20, 24, 24, 16, },
{ 14, 4, 8, 8, 4, 12, 12, 16, 24, 16, 20, 24, 32, 40, 36, },
{ 23, 4, 4, 4, 8, 4, 4, 8, 8, 8, 8, 8, 12, 12, 16, 16, 24, 24, 32, 44, 48, 60, 84, 72, },
};

const uint8_t exponent_band_32000[3][25] = {
{ 11, 4, 4, 8, 4, 4, 12, 16, 24, 20, 28, 4, },
{ 15, 4, 8, 4, 4, 8, 8, 16, 20, 12, 20, 20, 28, 40, 56, 8, },
{ 16, 8, 4, 8, 8, 12, 16, 20, 24, 40, 32, 32, 44, 56, 80, 112, 16, },
};

const uint8_t exponent_band_44100[3][25] = {
{ 12, 4, 4, 4, 4, 4, 8, 8, 8, 12, 16, 20, 36, },
{ 15, 4, 8, 4, 8, 8, 4, 8, 8, 12, 12, 12, 24, 28, 40, 76, },
{ 17, 4, 8, 8, 4, 12, 12, 8, 8, 24, 16, 20, 24, 32, 40, 60, 80, 152, },
};

const uint16_t hgain_huffcodes[37] = {
0x00003, 0x002e7, 0x00001, 0x005cd, 0x0005d, 0x005c9, 0x0005e, 0x00003,
0x00016, 0x0000b, 0x00001, 0x00006, 0x00001, 0x00006, 0x00004, 0x00005,
0x00004, 0x00007, 0x00003, 0x00007, 0x00004, 0x0000a, 0x0000a, 0x00002,
0x00003, 0x00000, 0x00005, 0x00002, 0x0005f, 0x00004, 0x00003, 0x00002,
0x005c8, 0x000b8, 0x005ca, 0x005cb, 0x005cc,
};

const uint8_t hgain_huffbits[37] = {
10, 12, 10, 13, 9, 13, 9, 8,
7, 5, 5, 4, 4, 3, 3, 3,
4, 3, 4, 4, 5, 5, 6, 8,
7, 10, 8, 10, 9, 8, 9, 9,
13, 10, 13, 13, 13,
};

const fixed32 lsp_codebook[NB_LSP_COEFS][16] = {
{0x1fcc2,0x1fabd,0x1f8c7,0x1f66d,0x1f34c,0x1eef1,0x1e83e,0x1dca6,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0},
{0x1f8fc,0x1f5f9,0x1f328,0x1f025,0x1ecd8,0x1e8fc,0x1e46f,0x1df1b,0x1d87c,0x1d047,0x1c6b5,0x1bb8f,0x1add8,0x19c0e,0x18220,0x154ca},
{0x1e6ae,0x1dd65,0x1d58e,0x1cd3b,0x1c439,0x1ba69,0x1af5e,0x1a32c,0x195c4,0x18498,0x16fd2,0x156ea,0x13de4,0x11f63,0xf7ae,0xbd90},
{0x1c4fa,0x1ada0,0x19976,0x1891d,0x17986,0x1697f,0x15858,0x145fd,0x1316b,0x11900,0xfcfa,0xdf55,0xbe63,0x9902,0x6e83,0x2e05},
{0x16f2d,0x15205,0x135f3,0x11b14,0x10170,0xe743,0xcdec,0xb504,0x9ab2,0x7f86,0x6296,0x4565,0x24e2,0x90,0xffffd52f,0xffffa172},
{0xffbc,0xd786,0xb521,0x943e,0x7876,0x5ea3,0x44ad,0x2bf0,0x1274,0xfffff829,0xfffe9981,0xffffbfab,0xffffa0bb,0xffff7d3f,0xffff59e3,0xffff3269},
{0x43e1,0x102a,0xffffe94a,0xffffc9fa,0xffffb076,0xffff9a6b,0xffff871c,0xffff7555,0xffff62b4,0xffff4f81,0xffff3bf4,0xffff25f7,0xffff0c0f,0xfffeef53,0xfffecb7e,0xfffe9fb3},
{0xffff75ea,0xffff4325,0xffff1da2,0xfffefd23,0xfffeddb9,0xfffebb51,0xfffe945f,0xfffe6131,0xfffee5fe,0xfffed5ba,0xfffec442,0xfffeb224,0xfffe9f95,0xfffe880e,0xfffe6c7a,0xfffe54c1},
{0xffff9d2e,0xffff709e,0xffff5489,0xffff3d5e,0xffff295b,0xffff1761,0xffff06a2,0xfffef68a,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0},
{0xfffe7045,0xfffe572f,0xfffe45ea,0xfffe38af,0xfffe2d8f,0xfffe2347,0xfffe18df,0xfffe0d42,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}
};

const uint32_t scale_huffcodes[121] = {
0x3ffe8, 0x3ffe6, 0x3ffe7, 0x3ffe5, 0x7fff5, 0x7fff1, 0x7ffed, 0x7fff6,
0x7ffee, 0x7ffef, 0x7fff0, 0x7fffc, 0x7fffd, 0x7ffff, 0x7fffe, 0x7fff7,
0x7fff8, 0x7fffb, 0x7fff9, 0x3ffe4, 0x7fffa, 0x3ffe3, 0x1ffef, 0x1fff0,
0x0fff5, 0x1ffee, 0x0fff2, 0x0fff3, 0x0fff4, 0x0fff1, 0x07ff6, 0x07ff7,
0x03ff9, 0x03ff5, 0x03ff7, 0x03ff3, 0x03ff6, 0x03ff2, 0x01ff7, 0x01ff5,
0x00ff9, 0x00ff7, 0x00ff6, 0x007f9, 0x00ff4, 0x007f8, 0x003f9, 0x003f7,
0x003f5, 0x001f8, 0x001f7, 0x000fa, 0x000f8, 0x000f6, 0x00079, 0x0003a,
0x00038, 0x0001a, 0x0000b, 0x00004, 0x00000, 0x0000a, 0x0000c, 0x0001b,
0x00039, 0x0003b, 0x00078, 0x0007a, 0x000f7, 0x000f9, 0x001f6, 0x001f9,
0x003f4, 0x003f6, 0x003f8, 0x007f5, 0x007f4, 0x007f6, 0x007f7, 0x00ff5,
0x00ff8, 0x01ff4, 0x01ff6, 0x01ff8, 0x03ff8, 0x03ff4, 0x0fff0, 0x07ff4,
0x0fff6, 0x07ff5, 0x3ffe2, 0x7ffd9, 0x7ffda, 0x7ffdb, 0x7ffdc, 0x7ffdd,
0x7ffde, 0x7ffd8, 0x7ffd2, 0x7ffd3, 0x7ffd4, 0x7ffd5, 0x7ffd6, 0x7fff2,
0x7ffdf, 0x7ffe7, 0x7ffe8, 0x7ffe9, 0x7ffea, 0x7ffeb, 0x7ffe6, 0x7ffe0,
0x7ffe1, 0x7ffe2, 0x7ffe3, 0x7ffe4, 0x7ffe5, 0x7ffd7, 0x7ffec, 0x7fff4,
0x7fff3,
};

const uint8_t scale_huffbits[121] = {
18, 18, 18, 18, 19, 19, 19, 19,
19, 19, 19, 19, 19, 19, 19, 19,
19, 19, 19, 18, 19, 18, 17, 17,
16, 17, 16, 16, 16, 16, 15, 15,
14, 14, 14, 14, 14, 14, 13, 13,
12, 12, 12, 11, 12, 11, 10, 10,
10, 9, 9, 8, 8, 8, 7, 6,
6, 5, 4, 3, 1, 4, 4, 5,
6, 6, 7, 7, 8, 8, 9, 9,
10, 10, 10, 11, 11, 11, 11, 12,
12, 13, 13, 13, 14, 14, 16, 15,
16, 15, 18, 19, 19, 19, 19, 19,
19, 19, 19, 19, 19, 19, 19, 19,
19, 19, 19, 19, 19, 19, 19, 19,
19, 19, 19, 19, 19, 19, 19, 19,
19,
};

const uint32_t coef0_huffcodes[666] = {
0x00258, 0x0003d, 0x00000, 0x00005, 0x00008, 0x00008, 0x0000c, 0x0001b,
0x0001f, 0x00015, 0x00024, 0x00032, 0x0003a, 0x00026, 0x0002c, 0x0002f,
0x0004a, 0x0004d, 0x00061, 0x00070, 0x00073, 0x00048, 0x00052, 0x0005a,
0x0005d, 0x0006e, 0x00099, 0x0009e, 0x000c1, 0x000ce, 0x000e4, 0x000f0,
0x00093, 0x0009e, 0x000a2, 0x000a1, 0x000b8, 0x000d2, 0x000d3, 0x0012e,
0x00130, 0x000de, 0x0012d, 0x0019b, 0x001e4, 0x00139, 0x0013a, 0x0013f,
0x0014f, 0x0016d, 0x001a2, 0x0027c, 0x0027e, 0x00332, 0x0033c, 0x0033f,
0x0038b, 0x00396, 0x003c5, 0x00270, 0x0027c, 0x0025a, 0x00395, 0x00248,
0x004bd, 0x004fb, 0x00662, 0x00661, 0x0071b, 0x004e6, 0x004ff, 0x00666,
0x0071c, 0x0071a, 0x0071f, 0x00794, 0x00536, 0x004e2, 0x0078e, 0x004ee,
0x00518, 0x00535, 0x004fb, 0x0078d, 0x00530, 0x00680, 0x0068f, 0x005cb,
0x00965, 0x006a6, 0x00967, 0x0097f, 0x00682, 0x006ae, 0x00cd0, 0x00e28,
0x00f13, 0x00f1f, 0x009f5, 0x00cd3, 0x00f11, 0x00926, 0x00964, 0x00f32,
0x00f12, 0x00f30, 0x00966, 0x00d0b, 0x00a68, 0x00b91, 0x009c7, 0x00b73,
0x012fa, 0x0131d, 0x013f9, 0x01ca0, 0x0199c, 0x01c7a, 0x0198c, 0x01248,
0x01c74, 0x01c64, 0x0139e, 0x012fd, 0x00a77, 0x012fc, 0x01c7b, 0x012ca,
0x014cc, 0x014d2, 0x014e3, 0x014dc, 0x012dc, 0x03344, 0x02598, 0x0263c,
0x0333b, 0x025e6, 0x01a1c, 0x01e3c, 0x014e2, 0x033d4, 0x01a11, 0x03349,
0x03cce, 0x014e1, 0x01a34, 0x0273e, 0x02627, 0x0273f, 0x038ee, 0x03971,
0x03c67, 0x03c61, 0x0333d, 0x038c2, 0x0263f, 0x038cd, 0x02638, 0x02e41,
0x0351f, 0x03348, 0x03c66, 0x03562, 0x02989, 0x027d5, 0x0333c, 0x02e4f,
0x0343b, 0x02ddf, 0x04bc8, 0x029c0, 0x02e57, 0x04c72, 0x025b7, 0x03547,
0x03540, 0x029d3, 0x04c45, 0x025bb, 0x06600, 0x04c73, 0x04bce, 0x0357b,
0x029a6, 0x029d2, 0x0263e, 0x0298a, 0x07183, 0x06602, 0x07958, 0x04b66,
0x0537d, 0x05375, 0x04fe9, 0x04b67, 0x0799f, 0x04bc9, 0x051fe, 0x06a3b,
0x05bb6, 0x04fa8, 0x0728f, 0x05376, 0x0492c, 0x0537e, 0x0795a, 0x06a3c,
0x0e515, 0x07887, 0x0683a, 0x051f9, 0x051fd, 0x0cc6a, 0x06a8a, 0x0cc6d,
0x05bb3, 0x0683b, 0x051fc, 0x05378, 0x0728e, 0x07886, 0x05bb7, 0x0f2a4,
0x0795b, 0x0683c, 0x09fc1, 0x0683d, 0x0b752, 0x09678, 0x0a3e8, 0x06ac7,
0x051f0, 0x0b759, 0x06af3, 0x04b6b, 0x0f2a0, 0x0f2ad, 0x096c3, 0x0e518,
0x0b75c, 0x0d458, 0x0cc6b, 0x0537c, 0x067aa, 0x04fea, 0x0343a, 0x0cc71,
0x0967f, 0x09fc4, 0x096c2, 0x0e516, 0x0f2a1, 0x0d45c, 0x0d45d, 0x0d45e,
0x12fb9, 0x0967e, 0x1982f, 0x09883, 0x096c4, 0x0b753, 0x12fb8, 0x0f2a8,
0x1ca21, 0x096c5, 0x0e51a, 0x1ca27, 0x12f3c, 0x0d471, 0x0f2aa, 0x0b75b,
0x12fbb, 0x0f2a9, 0x0f2ac, 0x0d45a, 0x0b74f, 0x096c8, 0x16e91, 0x096ca,
0x12fbf, 0x0d0a7, 0x13103, 0x0d516, 0x16e99, 0x12cbd, 0x0a3ea, 0x19829,
0x0b755, 0x29ba7, 0x1ca28, 0x29ba5, 0x16e93, 0x1982c, 0x19828, 0x25994,
0x0a3eb, 0x1ca29, 0x16e90, 0x1ca25, 0x1982d, 0x1ca26, 0x16e9b, 0x0b756,
0x0967c, 0x25997, 0x0b75f, 0x198d3, 0x0b757, 0x19a2a, 0x0d45b, 0x0e517,
0x1ca24, 0x1ca23, 0x1ca22, 0x0b758, 0x16e97, 0x0cd14, 0x13100, 0x00007,
0x0003b, 0x0006b, 0x00097, 0x00138, 0x00125, 0x00173, 0x00258, 0x00335,
0x0028e, 0x004c6, 0x00715, 0x00729, 0x004ef, 0x00519, 0x004ed, 0x00532,
0x0068c, 0x00686, 0x00978, 0x00e5d, 0x00e31, 0x009f4, 0x00b92, 0x012f8,
0x00d06, 0x00a67, 0x00d44, 0x00a76, 0x00d59, 0x012cd, 0x01c78, 0x01c75,
0x0199f, 0x0198f, 0x01c67, 0x014c6, 0x01c79, 0x01c76, 0x00b94, 0x00d1b,
0x01e32, 0x01e31, 0x01ab0, 0x01a05, 0x01aa1, 0x0333a, 0x025e5, 0x02626,
0x03541, 0x03544, 0x03421, 0x03546, 0x02e55, 0x02e56, 0x0492d, 0x02dde,
0x0299b, 0x02ddc, 0x0357a, 0x0249c, 0x0668b, 0x1c77f, 0x1ca20, 0x0d45f,
0x09886, 0x16e9a, 0x0f2a7, 0x0b751, 0x0a3ee, 0x0cf59, 0x0cf57, 0x0b754,
0x0d0a6, 0x16e98, 0x0b760, 0x06ac6, 0x0a3f0, 0x12fbe, 0x13104, 0x0f2a5,
0x0a3ef, 0x0d472, 0x12cba, 0x1982e, 0x16e9c, 0x1c77e, 0x198d0, 0x13105,
0x16e92, 0x0b75d, 0x0d459, 0x0001a, 0x000c0, 0x0016c, 0x003cd, 0x00350,
0x0067b, 0x0051e, 0x006a9, 0x009f4, 0x00b72, 0x00d09, 0x01249, 0x01e3d,
0x01ca1, 0x01a1f, 0x01721, 0x01a8a, 0x016e8, 0x03347, 0x01a35, 0x0249d,
0x0299a, 0x02596, 0x02e4e, 0x0298b, 0x07182, 0x04c46, 0x025ba, 0x02e40,
0x027d6, 0x04fe8, 0x06607, 0x05310, 0x09884, 0x072e1, 0x06a3d, 0x04b6a,
0x04c7a, 0x06603, 0x04c7b, 0x03428, 0x06605, 0x09664, 0x09fc0, 0x071de,
0x06601, 0x05bb2, 0x09885, 0x0a3e2, 0x1c61f, 0x12cbb, 0x0b750, 0x0cf58,
0x0967d, 0x25995, 0x668ad, 0x0b75a, 0x09fc2, 0x0537f, 0x0b75e, 0x13fae,
0x12fbc, 0x00031, 0x001c4, 0x004c5, 0x005b8, 0x00cf4, 0x0096f, 0x00d46,
0x01e57, 0x01a04, 0x02625, 0x03346, 0x028f9, 0x04c47, 0x072e0, 0x04b69,
0x03420, 0x07957, 0x06639, 0x0799e, 0x07959, 0x07881, 0x04b68, 0x09fc3,
0x09fd6, 0x0cc70, 0x0a3f1, 0x12cbe, 0x0e30e, 0x0e51b, 0x06af2, 0x12cbc,
0x1c77d, 0x0f2ab, 0x12fbd, 0x1aa2f, 0x0a3ec, 0x0d473, 0x05377, 0x0a3e9,
0x1982b, 0x0e300, 0x12f3f, 0x0cf5f, 0x096c0, 0x38c3c, 0x16e94, 0x16e95,
0x12f3d, 0x29ba4, 0x29ba6, 0x1c77c, 0x6a8ba, 0x3545c, 0x33457, 0x668ac,
0x6a8bb, 0x16e9d, 0x0e519, 0x25996, 0x12f3e, 0x00036, 0x0033e, 0x006ad,
0x00d03, 0x012c8, 0x0124a, 0x03c42, 0x03ccd, 0x06606, 0x07880, 0x06852,
0x06a3a, 0x05bb4, 0x0f2a2, 0x09fc7, 0x12cb9, 0x0cc6c, 0x0a6e8, 0x096c1,
0x0004a, 0x00355, 0x012f9, 0x014e8, 0x01abe, 0x025b6, 0x0492e, 0x09fc6,
0x051ff, 0x0cc6f, 0x096cb, 0x0d071, 0x198d1, 0x12cb8, 0x38c3d, 0x13faf,
0x096c9, 0x0009d, 0x00539, 0x012ce, 0x0341f, 0x029c1, 0x04b33, 0x0a3e3,
0x0d070, 0x16e96, 0x0b763, 0x000a0, 0x009ce, 0x038cc, 0x0343d, 0x051fa,
0x09888, 0x12fba, 0x000df, 0x00a75, 0x029a7, 0x09fc5, 0x0e301, 0x0967b,
0x001e7, 0x012c9, 0x051fb, 0x09889, 0x0f2a6, 0x0016f, 0x01cb9, 0x0cf5a,
0x12cbf, 0x09679, 0x00272, 0x01a15, 0x0967a, 0x003cb, 0x025f6, 0x0b762,
0x0028d, 0x03c60, 0x0cf5e, 0x00352, 0x03ccc, 0x0072f, 0x07186, 0x004ec,
0x05379, 0x0068e, 0x09887, 0x006a7, 0x06af1, 0x00e29, 0x0cf5b, 0x00f31,
0x0d470, 0x009c6, 0x013fb, 0x13102, 0x019a5, 0x13101, 0x01983, 0x01c65,
0x0124f, 0x014c7, 0x01726, 0x01abf, 0x03304, 0x02624, 0x03c41, 0x027d7,
0x02ddd, 0x02e54, 0x0343c, 0x06604, 0x07181, 0x0663a, 0x04fa9, 0x0663b,
0x05311, 0x0537a, 0x06839, 0x05bb5, 0x0492f, 0x06af0, 0x096c7, 0x0cc6e,
0x0537b, 0x0cf5c, 0x0cf56, 0x198d2, 0x0cf5d, 0x0a3ed, 0x0f2a3, 0x1982a,
0x0b761, 0x096c6,
};

const uint8_t coef0_huffbits[666] = {
11, 6, 2, 3, 4, 5, 5, 5,
5, 6, 6, 6, 6, 7, 7, 7,
7, 7, 7, 7, 7, 8, 8, 8,
8, 8, 8, 8, 8, 8, 8, 8,
9, 9, 9, 9, 9, 9, 9, 9,
9, 9, 9, 9, 9, 10, 10, 10,
10, 10, 10, 10, 10, 10, 10, 10,
10, 10, 10, 11, 11, 11, 10, 11,
11, 11, 11, 11, 11, 11, 11, 11,
11, 11, 11, 11, 12, 12, 11, 12,
12, 12, 12, 11, 12, 12, 12, 12,
12, 12, 12, 12, 12, 12, 12, 12,
12, 12, 12, 12, 12, 13, 13, 12,
12, 12, 13, 13, 13, 13, 13, 13,
13, 13, 13, 13, 13, 13, 13, 14,
13, 13, 13, 13, 13, 13, 13, 14,
14, 14, 14, 14, 14, 14, 14, 14,
14, 14, 14, 13, 14, 14, 14, 14,
14, 14, 14, 14, 14, 14, 14, 14,
14, 14, 14, 14, 14, 14, 14, 15,
15, 14, 14, 15, 15, 15, 14, 15,
15, 15, 15, 15, 15, 15, 15, 15,
15, 15, 15, 15, 15, 15, 15, 15,
15, 15, 14, 15, 15, 15, 15, 16,
16, 16, 15, 16, 15, 15, 16, 16,
16, 16, 15, 16, 16, 16, 15, 16,
16, 15, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 15, 15, 16, 16,
15, 16, 16, 16, 17, 17, 17, 16,
16, 17, 16, 16, 16, 16, 17, 16,
17, 17, 16, 16, 15, 15, 15, 16,
17, 16, 17, 16, 16, 17, 17, 17,
17, 17, 17, 16, 17, 17, 17, 16,
17, 17, 16, 17, 17, 17, 16, 17,
17, 16, 16, 17, 17, 17, 18, 17,
17, 17, 17, 17, 18, 18, 17, 17,
17, 19, 17, 19, 18, 17, 17, 18,
17, 17, 18, 17, 17, 17, 18, 17,
17, 18, 17, 17, 17, 17, 17, 16,
17, 17, 17, 17, 18, 16, 17, 4,
6, 8, 9, 9, 10, 10, 10, 10,
11, 11, 11, 11, 12, 12, 12, 12,
12, 12, 12, 12, 12, 13, 13, 13,
13, 13, 13, 13, 13, 13, 13, 13,
13, 13, 13, 14, 13, 13, 13, 13,
13, 13, 14, 14, 14, 14, 14, 14,
15, 15, 15, 15, 15, 15, 16, 15,
15, 15, 15, 15, 15, 17, 17, 17,
16, 18, 16, 17, 17, 16, 16, 17,
17, 18, 17, 16, 17, 17, 17, 16,
17, 17, 18, 17, 18, 17, 17, 17,
18, 17, 17, 5, 8, 10, 10, 11,
11, 12, 12, 12, 13, 13, 14, 13,
13, 14, 14, 14, 14, 14, 14, 15,
15, 15, 15, 15, 15, 15, 15, 15,
15, 15, 15, 16, 16, 15, 16, 16,
15, 15, 15, 15, 15, 16, 16, 15,
15, 16, 16, 17, 17, 18, 17, 16,
17, 18, 19, 17, 16, 16, 17, 17,
17, 6, 9, 11, 12, 12, 13, 13,
13, 14, 14, 14, 15, 15, 15, 16,
15, 15, 15, 15, 15, 15, 16, 16,
16, 16, 17, 18, 16, 16, 16, 18,
17, 16, 17, 18, 17, 17, 16, 17,
17, 16, 17, 16, 17, 18, 18, 18,
17, 19, 19, 17, 20, 19, 18, 19,
20, 18, 16, 18, 17, 7, 10, 12,
13, 13, 14, 14, 14, 15, 15, 16,
16, 16, 16, 16, 18, 16, 17, 17,
8, 11, 13, 14, 14, 15, 16, 16,
16, 16, 17, 17, 17, 18, 18, 17,
17, 8, 12, 14, 15, 15, 15, 17,
17, 18, 17, 9, 12, 14, 15, 16,
16, 17, 9, 13, 15, 16, 16, 17,
9, 13, 16, 16, 16, 10, 13, 16,
18, 17, 10, 14, 17, 10, 14, 17,
11, 14, 16, 11, 14, 11, 15, 12,
16, 12, 16, 12, 16, 12, 16, 12,
17, 13, 13, 17, 13, 17, 13, 13,
14, 14, 14, 14, 14, 14, 14, 15,
15, 15, 15, 15, 15, 15, 16, 15,
16, 16, 16, 16, 16, 16, 17, 16,
16, 16, 16, 17, 16, 17, 16, 17,
17, 17,
};

const uint32_t coef1_huffcodes[555] = {
0x00115, 0x00002, 0x00001, 0x00000, 0x0000d, 0x00007, 0x00013, 0x0001d,
0x00008, 0x0000c, 0x00023, 0x0002b, 0x0003f, 0x00017, 0x0001b, 0x00043,
0x00049, 0x00050, 0x00055, 0x00054, 0x00067, 0x00064, 0x0007b, 0x0002d,
0x00028, 0x0002a, 0x00085, 0x00089, 0x0002b, 0x00035, 0x00090, 0x00091,
0x00094, 0x00088, 0x000c1, 0x000c6, 0x000f2, 0x000e3, 0x000c5, 0x000e2,
0x00036, 0x000f0, 0x000a7, 0x000cd, 0x000fb, 0x00059, 0x00116, 0x00103,
0x00108, 0x0012b, 0x0012d, 0x00188, 0x0012e, 0x0014c, 0x001c3, 0x00187,
0x001e7, 0x0006f, 0x00094, 0x00069, 0x001e6, 0x001ca, 0x00147, 0x00195,
0x000a7, 0x00213, 0x00209, 0x00303, 0x00295, 0x00289, 0x0028c, 0x0028d,
0x00312, 0x00330, 0x0029b, 0x00308, 0x00328, 0x0029a, 0x0025e, 0x003c5,
0x00384, 0x0039f, 0x00397, 0x00296, 0x0032e, 0x00332, 0x003c6, 0x003e6,
0x0012d, 0x000d1, 0x00402, 0x000dd, 0x00161, 0x0012b, 0x00127, 0x0045d,
0x00601, 0x004ab, 0x0045f, 0x00410, 0x004bf, 0x00528, 0x0045c, 0x00424,
0x00400, 0x00511, 0x00618, 0x0073d, 0x0063a, 0x00614, 0x0073c, 0x007c0,
0x007cf, 0x00802, 0x00966, 0x00964, 0x00951, 0x008a0, 0x00346, 0x00803,
0x00a52, 0x0024a, 0x007c1, 0x0063f, 0x00126, 0x00406, 0x00789, 0x008a2,
0x00960, 0x00967, 0x00c05, 0x00c70, 0x00c79, 0x00a5d, 0x00c26, 0x00c4d,
0x00372, 0x008a5, 0x00c08, 0x002c5, 0x00f11, 0x00cc4, 0x00f8e, 0x00e16,
0x00496, 0x00e77, 0x00f9c, 0x00c25, 0x00f1e, 0x00c27, 0x00f1f, 0x00e17,
0x00ccd, 0x00355, 0x00c09, 0x00c78, 0x00f90, 0x00521, 0x00357, 0x00356,
0x0068e, 0x00f9d, 0x00c04, 0x00e58, 0x00a20, 0x00a2c, 0x00c4c, 0x0052f,
0x00f8d, 0x01178, 0x01053, 0x01097, 0x0180f, 0x0180d, 0x012fb, 0x012aa,
0x0202a, 0x00a40, 0x018ed, 0x01ceb, 0x01455, 0x018e3, 0x012a1, 0x00354,
0x00353, 0x00f1c, 0x00c7b, 0x00c37, 0x0101d, 0x012cb, 0x01142, 0x0197d,
0x01095, 0x01e3b, 0x0186b, 0x00588, 0x01c2a, 0x014b8, 0x01e3a, 0x018ec,
0x01f46, 0x012fa, 0x00a53, 0x01ce8, 0x00a55, 0x01c29, 0x0117b, 0x01052,
0x012a0, 0x00589, 0x00950, 0x01c2b, 0x00a50, 0x0208b, 0x0180e, 0x02027,
0x02556, 0x01e20, 0x006e7, 0x01c28, 0x0197a, 0x00684, 0x020a2, 0x01f22,
0x03018, 0x039cf, 0x03e25, 0x02557, 0x0294c, 0x028a6, 0x00d11, 0x028a9,
0x02979, 0x00d46, 0x00a56, 0x039ce, 0x030cc, 0x0329a, 0x0149d, 0x0510f,
0x0451c, 0x02028, 0x03299, 0x01ced, 0x014b9, 0x00f85, 0x00c7a, 0x01800,
0x00341, 0x012ca, 0x039c8, 0x0329d, 0x00d0d, 0x03e20, 0x05144, 0x00d45,
0x030d0, 0x0186d, 0x030d5, 0x00d0f, 0x00d40, 0x04114, 0x020a1, 0x0297f,
0x03e24, 0x032f1, 0x04047, 0x030d4, 0x028a8, 0x00d0e, 0x0451d, 0x04044,
0x0297e, 0x04042, 0x030d2, 0x030cf, 0x03e21, 0x03e26, 0x028a5, 0x0451a,
0x00d48, 0x01a16, 0x00d44, 0x04518, 0x0149b, 0x039ca, 0x01498, 0x0403d,
0x0451b, 0x0149c, 0x032f3, 0x030cb, 0x08073, 0x03e22, 0x0529a, 0x020aa,
0x039cc, 0x0738a, 0x06530, 0x07389, 0x06193, 0x08071, 0x04043, 0x030ce,
0x05147, 0x07388, 0x05145, 0x08072, 0x04521, 0x00d47, 0x0297c, 0x030cd,
0x030ca, 0x0000b, 0x0000c, 0x00083, 0x000e4, 0x00048, 0x00102, 0x001cc,
0x001f5, 0x00097, 0x0020b, 0x00124, 0x00453, 0x00627, 0x00639, 0x00605,
0x00517, 0x001b8, 0x00663, 0x00667, 0x007c3, 0x00823, 0x00961, 0x00963,
0x00e5a, 0x00e59, 0x00a2b, 0x00cbf, 0x00292, 0x00a2d, 0x007d0, 0x00953,
0x00cc5, 0x00f84, 0x004ab, 0x014a7, 0x0068a, 0x0117a, 0x0052e, 0x01442,
0x0052c, 0x00c77, 0x00f8f, 0x004aa, 0x01094, 0x01801, 0x012c4, 0x0297b,
0x00952, 0x01f19, 0x006a5, 0x01149, 0x012c5, 0x01803, 0x022f2, 0x0329b,
0x04520, 0x0149e, 0x00d13, 0x01f16, 0x01ce9, 0x0101c, 0x006e6, 0x039c9,
0x06191, 0x07c8e, 0x06192, 0x0ca63, 0x039cd, 0x06190, 0x06884, 0x06885,
0x07382, 0x00d49, 0x00d41, 0x0450c, 0x0149a, 0x030d1, 0x08077, 0x03e23,
0x01a15, 0x0e701, 0x0e702, 0x08079, 0x0822a, 0x0a218, 0x07887, 0x0403f,
0x0520b, 0x0529b, 0x0e700, 0x04519, 0x00007, 0x000e0, 0x000d0, 0x0039b,
0x003e5, 0x00163, 0x0063e, 0x007c9, 0x00806, 0x00954, 0x01044, 0x01f44,
0x0197c, 0x01f45, 0x00a51, 0x01f47, 0x00951, 0x0052d, 0x02291, 0x0092f,
0x00a54, 0x00d12, 0x0297d, 0x00d0c, 0x01499, 0x0329e, 0x032f0, 0x02025,
0x039c6, 0x00a57, 0x03e46, 0x00d42, 0x0738b, 0x05146, 0x04046, 0x08078,
0x0510e, 0x07886, 0x02904, 0x04156, 0x04157, 0x06032, 0x030d3, 0x08bce,
0x04040, 0x0403e, 0x0a414, 0x10457, 0x08075, 0x06887, 0x07c8f, 0x039c7,
0x07387, 0x08070, 0x08bcf, 0x1482a, 0x10456, 0x1482b, 0x01a17, 0x06886,
0x0450d, 0x00013, 0x0006b, 0x00615, 0x0080b, 0x0082b, 0x00952, 0x00e5b,
0x018e2, 0x0186c, 0x01f18, 0x0329f, 0x00d43, 0x03e29, 0x05140, 0x05141,
0x0ca62, 0x06033, 0x03c42, 0x03e28, 0x0450f, 0x0a21a, 0x07384, 0x0a219,
0x0e703, 0x0a21b, 0x01a14, 0x07383, 0x045e6, 0x0007a, 0x0012c, 0x00ccc,
0x0068f, 0x01802, 0x00a52, 0x00953, 0x04045, 0x01a20, 0x0451f, 0x000a4,
0x00735, 0x01cec, 0x02029, 0x020a3, 0x0451e, 0x00069, 0x00c24, 0x02024,
0x032f2, 0x05142, 0x00196, 0x00523, 0x000a6, 0x0197b, 0x0030b, 0x0092e,
0x003e9, 0x03e27, 0x00160, 0x05143, 0x00652, 0x04041, 0x00734, 0x028a7,
0x0080f, 0x01483, 0x0097c, 0x00340, 0x0068b, 0x00522, 0x01054, 0x01096,
0x01f17, 0x0202b, 0x01cea, 0x020a0, 0x02978, 0x02026, 0x0297a, 0x039cb,
0x03e2b, 0x0149f, 0x0329c, 0x07385, 0x08074, 0x0450e, 0x03e2a, 0x05149,
0x08076, 0x07386, 0x05148,
};

const uint8_t coef1_huffbits[555] = {
9, 5, 2, 4, 4, 5, 5, 5,
6, 6, 6, 6, 6, 7, 7, 7,
7, 7, 7, 7, 7, 7, 7, 8,
8, 8, 8, 8, 8, 8, 8, 8,
8, 8, 8, 8, 8, 8, 8, 8,
9, 8, 8, 8, 8, 9, 9, 9,
9, 9, 9, 9, 9, 9, 9, 9,
9, 10, 10, 10, 9, 9, 9, 9,
10, 10, 10, 10, 10, 10, 10, 10,
10, 10, 10, 10, 10, 10, 10, 10,
10, 10, 10, 10, 10, 10, 10, 10,
11, 11, 11, 11, 11, 11, 11, 11,
11, 11, 11, 11, 11, 11, 11, 11,
11, 11, 11, 11, 11, 11, 11, 11,
11, 12, 12, 12, 12, 12, 12, 12,
12, 12, 11, 11, 11, 11, 11, 12,
12, 12, 12, 12, 12, 12, 12, 12,
13, 12, 12, 12, 12, 12, 12, 12,
13, 12, 12, 12, 12, 12, 12, 12,
12, 13, 12, 12, 12, 13, 13, 13,
13, 12, 12, 12, 12, 12, 12, 13,
12, 13, 13, 13, 13, 13, 13, 13,
14, 14, 13, 13, 13, 13, 13, 13,
13, 12, 12, 12, 13, 13, 13, 13,
13, 13, 13, 13, 13, 13, 13, 13,
13, 13, 14, 13, 14, 13, 13, 13,
13, 13, 14, 13, 14, 14, 13, 14,
14, 13, 14, 13, 13, 14, 14, 13,
14, 14, 14, 14, 14, 14, 14, 14,
14, 15, 14, 14, 14, 14, 15, 15,
15, 14, 14, 13, 13, 12, 12, 13,
13, 13, 14, 14, 15, 14, 15, 15,
14, 13, 14, 15, 15, 15, 14, 14,
14, 14, 15, 14, 14, 15, 15, 15,
14, 15, 14, 14, 14, 14, 14, 15,
15, 16, 15, 15, 15, 14, 15, 15,
15, 15, 14, 14, 16, 14, 15, 14,
14, 15, 15, 15, 15, 16, 15, 14,
15, 15, 15, 16, 15, 15, 14, 14,
14, 4, 7, 8, 8, 9, 9, 9,
9, 10, 10, 11, 11, 11, 11, 11,
11, 12, 11, 11, 11, 12, 12, 12,
12, 12, 12, 12, 12, 12, 11, 12,
12, 12, 13, 13, 13, 13, 13, 13,
13, 12, 12, 13, 13, 13, 13, 14,
14, 13, 14, 13, 13, 13, 14, 14,
15, 15, 14, 13, 13, 13, 14, 14,
15, 15, 15, 16, 14, 15, 17, 17,
15, 15, 15, 15, 15, 14, 16, 14,
16, 16, 16, 16, 16, 16, 15, 15,
17, 15, 16, 15, 6, 8, 10, 10,
10, 11, 11, 11, 12, 12, 13, 13,
13, 13, 14, 13, 14, 13, 14, 14,
14, 14, 14, 15, 15, 14, 14, 14,
14, 14, 14, 15, 15, 15, 15, 16,
15, 15, 16, 15, 15, 15, 14, 16,
15, 15, 18, 17, 16, 17, 15, 14,
15, 16, 16, 19, 17, 19, 16, 17,
15, 7, 10, 11, 12, 12, 12, 12,
13, 13, 13, 14, 15, 14, 15, 15,
16, 15, 14, 14, 15, 16, 15, 16,
16, 16, 16, 15, 15, 7, 11, 12,
13, 13, 14, 14, 15, 15, 15, 8,
11, 13, 14, 14, 15, 9, 12, 14,
14, 15, 9, 13, 10, 13, 10, 14,
10, 14, 11, 15, 11, 15, 11, 14,
12, 15, 12, 13, 13, 13, 13, 13,
13, 14, 13, 14, 14, 14, 14, 14,
14, 15, 14, 15, 16, 15, 14, 15,
16, 15, 15,
};

const uint32_t coef2_huffcodes[1336] = {
0x003e6, 0x000f6, 0x00000, 0x00002, 0x00006, 0x0000f, 0x0001b, 0x00028,
0x00039, 0x0003f, 0x0006b, 0x00076, 0x000b7, 0x000e8, 0x000ef, 0x00169,
0x001a7, 0x001d4, 0x001dc, 0x002c4, 0x00349, 0x00355, 0x00391, 0x003dc,
0x00581, 0x005b2, 0x00698, 0x0070c, 0x00755, 0x0073a, 0x00774, 0x007cf,
0x00b0a, 0x00b66, 0x00d2e, 0x00d5e, 0x00e1b, 0x00eac, 0x00e5a, 0x00f7e,
0x00fa1, 0x0163e, 0x01a37, 0x01a52, 0x01c39, 0x01ab3, 0x01d5f, 0x01cb6,
0x01f52, 0x01dd9, 0x02c04, 0x02c2e, 0x02c2d, 0x02c23, 0x03467, 0x034a3,
0x0351b, 0x03501, 0x03a5d, 0x0351c, 0x03875, 0x03dea, 0x0397b, 0x039db,
0x03df1, 0x039d8, 0x03bb4, 0x0580a, 0x0584d, 0x05842, 0x05b13, 0x058ea,
0x0697d, 0x06a06, 0x068cc, 0x06ac7, 0x06a96, 0x072f4, 0x07543, 0x072b4,
0x07d20, 0x0b003, 0x073b5, 0x07be6, 0x0d180, 0x07bd1, 0x07cb8, 0x07d06,
0x07d25, 0x0d2f2, 0x0d19a, 0x0d334, 0x0e1dc, 0x0d529, 0x0d584, 0x0e1d2,
0x0e5e3, 0x0eec4, 0x0e564, 0x0fa49, 0x16001, 0x0eedc, 0x0f7fa, 0x1a32c,
0x16131, 0x16003, 0x0f9c8, 0x1ef80, 0x1d2a0, 0x1aa4b, 0x0f7ce, 0x1abfe,
0x1aa50, 0x1a458, 0x1a816, 0x1cae4, 0x1d2fe, 0x1d52e, 0x1aa4c, 0x2c245,
0x1d2a1, 0x1a35d, 0x1ca1b, 0x1d5d8, 0x1f531, 0x1ca1c, 0x1f389, 0x1f4af,
0x3a5e7, 0x351fb, 0x2c24b, 0x34bce, 0x2c24d, 0x2c249, 0x2c24a, 0x72dfc,
0x357ef, 0x35002, 0x3a5e6, 0x39431, 0x5843b, 0x34a77, 0x58431, 0x3a5f3,
0x3a5dd, 0x3e5e5, 0x356bd, 0x3976e, 0x6a3d2, 0x3500d, 0x694c4, 0x580bd,
0x3e5e8, 0x74b95, 0x34a6e, 0x3977c, 0x39432, 0x5b0d2, 0x6a3d8, 0x580b8,
0x5b0cb, 0x5b0d7, 0x72dee, 0x72ded, 0x72dec, 0x74b9c, 0x3977f, 0x72dea,
0x74b9e, 0x7be7d, 0x580bf, 0x5b0d5, 0x7cba8, 0x74b91, 0x3e5dd, 0xb6171,
0xd46b3, 0xd46b9, 0x7cba1, 0x74b9f, 0x72de1, 0xe59f5, 0x3e5eb, 0x00004,
0x00015, 0x00038, 0x00075, 0x000e8, 0x001d3, 0x00347, 0x0039c, 0x00690,
0x0074a, 0x00b60, 0x00e93, 0x00f74, 0x0163d, 0x01a5a, 0x01d24, 0x01cbe,
0x01f4b, 0x03468, 0x03562, 0x03947, 0x03e82, 0x05804, 0x05b12, 0x05803,
0x0696d, 0x06a9e, 0x0697c, 0x06978, 0x06afb, 0x074b2, 0x072f5, 0x073c0,
0x07541, 0x06944, 0x074b7, 0x070d3, 0x07ba9, 0x0b0b1, 0x0d1af, 0x0e1dd,
0x0e5e2, 0x0e1a3, 0x0eec3, 0x1612f, 0x0e961, 0x0eeda, 0x0e78e, 0x0fa48,
0x1612c, 0x0e511, 0x0e565, 0x0e953, 0x1aa4a, 0x0e59d, 0x1d52c, 0x1a811,
0x1cae7, 0x1abfc, 0x1d52d, 0x1cacf, 0x1cf05, 0x2c254, 0x34a72, 0x1f4ac,
0x3976b, 0x34a71, 0x2c6d9, 0x2d873, 0x34a6a, 0x357e7, 0x3464c, 0x3e5f5,
0x58433, 0x1f53a, 0x3500a, 0x357ea, 0x34a73, 0x3942f, 0x357e5, 0x39775,
0x694cd, 0x39772, 0x7cba5, 0x6a3ef, 0x35483, 0x74b98, 0x5b0c1, 0x39770,
0x3a5d7, 0x39433, 0x39434, 0x694ce, 0x580be, 0x3e5ff, 0x6a3ec, 0xb616f,
0xd46b1, 0x6a3d1, 0x72de5, 0x74b6e, 0x72de9, 0x3e700, 0xd46b6, 0x6a3e9,
0x74b69, 0xe5675, 0xd46b8, 0x7cbaa, 0x3a5d1, 0x0000c, 0x0003c, 0x000eb,
0x001f1, 0x003a4, 0x006a8, 0x007d5, 0x00d43, 0x00e77, 0x016c5, 0x01cb1,
0x02c5d, 0x03a55, 0x03a56, 0x03e51, 0x03bb5, 0x05b0a, 0x06a9f, 0x074b8,
0x07d28, 0x0d187, 0x0d40e, 0x0d52e, 0x0d425, 0x0eae3, 0x0e1d3, 0x1612e,
0x0e59e, 0x0eec2, 0x0e578, 0x0e51a, 0x0e579, 0x0e515, 0x0e960, 0x0d183,
0x0d220, 0x0d2cb, 0x0e512, 0x16c3e, 0x16002, 0x16c42, 0x1cae9, 0x3461a,
0x1d2fa, 0x1a308, 0x1a849, 0x1cf07, 0x1f38f, 0x34b65, 0x2c253, 0x1ef9e,
0x1cbc3, 0x1cbc1, 0x2c255, 0x1f384, 0x58435, 0x2c5cd, 0x3a5f7, 0x2c252,
0x3959c, 0x2c6d8, 0x3a5d3, 0x6ad78, 0x6a3f2, 0x7cba9, 0xb6176, 0x72deb,
0x39764, 0x3e5f6, 0x3a5d8, 0x74a8c, 0x6a3e6, 0x694d1, 0x6ad79, 0x1a4592,
0xe59fb, 0x7cbb3, 0x5b0cd, 0x00017, 0x000b5, 0x002c3, 0x005b7, 0x00b1c,
0x00e5c, 0x0163f, 0x01ab2, 0x01efa, 0x0348a, 0x0396e, 0x058da, 0x06963,
0x06a30, 0x072cd, 0x073cf, 0x07ce7, 0x0d2ca, 0x0d2d8, 0x0e764, 0x0e794,
0x16008, 0x16167, 0x1617e, 0x1aa49, 0x1a30b, 0x1a813, 0x2c6da, 0x1a580,
0x1cbc2, 0x0f9ca, 0x1617f, 0x1d2fe, 0x0f7fc, 0x16c40, 0x0e513, 0x0eec5,
0x0f7c3, 0x1d508, 0x1a81e, 0x1d2fd, 0x39430, 0x35486, 0x3e5fd, 0x2c24c,
0x2c75a, 0x34a74, 0x3a5f4, 0x3464d, 0x694ca, 0x3a5f1, 0x1d509, 0x1d5c0,
0x34648, 0x3464e, 0x6a3d5, 0x6a3e8, 0x6a3e7, 0x5b0c3, 0x2c248, 0x1f38a,
0x3a5f2, 0x6a3e5, 0x00029, 0x00168, 0x0058c, 0x00b67, 0x00f9d, 0x01c3d,
0x01cbf, 0x02c20, 0x0351d, 0x03df6, 0x06af9, 0x072b5, 0x0b1d7, 0x0b0b2,
0x0d40a, 0x0d52b, 0x0e952, 0x0e797, 0x163c3, 0x1c3a0, 0x1f386, 0x1ca21,
0x34655, 0x2c247, 0x1f53b, 0x2c250, 0x2c24f, 0x1f385, 0x1ef5d, 0x1cf15,
0x1caea, 0x1ab0a, 0x1cf19, 0x1f53d, 0x1d5c2, 0x1d2fb, 0x1ef58, 0x34a78,
0x357ec, 0x1f533, 0x3a5e1, 0x694d2, 0x58482, 0x3a5ee, 0x2c6dc, 0x357eb,
0x5b0c4, 0x39778, 0x6a3e1, 0x7cbb4, 0x3a5e1, 0x74b68, 0x3a5ef, 0x3a5d2,
0x39424, 0x72de2, 0xe59f6, 0xe59f7, 0x3e702, 0x3e5ec, 0x1f38b, 0x0003b,
0x001f0, 0x00777, 0x00fa8, 0x01cb2, 0x02d84, 0x03a57, 0x03dd6, 0x06917,
0x06a11, 0x07d07, 0x0eae2, 0x0e796, 0x0f9c9, 0x0f7fb, 0x16166, 0x16160,
0x1ab1b, 0x1abfa, 0x2d87b, 0x1d2f7, 0x39768, 0x1f38c, 0x34653, 0x34651,
0x6a3d9, 0x35001, 0x3abbd, 0x38742, 0x39426, 0x34a76, 0x3a5ec, 0x34a75,
0x35000, 0x35488, 0x1cf10, 0x2c6db, 0x357ed, 0x357e8, 0x357e9, 0x3a5f0,
0x694c2, 0xb6178, 0x72df5, 0x39425, 0x3942b, 0x74b6d, 0x74b6f, 0xb6177,
0xb6179, 0x74b6a, 0xb6172, 0x58487, 0x3e5ee, 0x3e5ed, 0x72df2, 0x72df4,
0x7cbae, 0x6a3ca, 0x70e86, 0x34bcf, 0x6a3c8, 0x00059, 0x00384, 0x00d5b,
0x01c38, 0x03560, 0x0395b, 0x0584e, 0x06964, 0x073cd, 0x0b1e7, 0x0e798,
0x0e78d, 0x0fa43, 0x1a848, 0x1a32f, 0x1aa4e, 0x3464a, 0x1f4ab, 0x1f38d,
0x3a5eb, 0x3a5d4, 0x3548a, 0x6a3c7, 0x5b0d0, 0x6a3c5, 0x7cbb0, 0x694cb,
0x3a5e5, 0x3e5e2, 0x3942c, 0x2d872, 0x1f4ae, 0x3a5d5, 0x694d3, 0x58481,
0x35009, 0x39774, 0x58432, 0xb616c, 0x5b0db, 0x3548b, 0xb6174, 0x1d5d95,
0xb004c, 0x7cbb2, 0x3a5e5, 0x74a8f, 0xe59f9, 0x72df6, 0xe59fd, 0x7cbad,
0xd427d, 0x72cff, 0x3977a, 0x5b0d9, 0xb616d, 0xb616b, 0x1a4593, 0x7cbaf,
0x5b0da, 0x00071, 0x003eb, 0x01603, 0x02c6c, 0x03961, 0x068c8, 0x06a31,
0x072bd, 0x0d2c2, 0x0e51b, 0x0e5e6, 0x1abfb, 0x1d2ff, 0x1cae5, 0x1ef5c,
0x1ef5e, 0x1cf13, 0x34a6d, 0x3976d, 0xb616a, 0x3e5f2, 0x6a3c4, 0xb6169,
0x3e5dc, 0x580b9, 0x74b99, 0x75764, 0x58434, 0x3a5d9, 0x6945a, 0x69459,
0x3548c, 0x3a5e9, 0x69457, 0x72df1, 0x6945e, 0x6a35e, 0x3e701, 0xb6168,
0x5b0dd, 0x3a5de, 0x6a3c2, 0xd4278, 0x6a3cc, 0x72dfd, 0xb6165, 0x16009a,
0x7cbb1, 0xd427c, 0xb6162, 0xe765e, 0x1cecbe, 0x7cbb6, 0x69454, 0xb6160,
0xd427a, 0x1d5d96, 0xb1d6d, 0xe59f4, 0x72de8, 0x3a5db, 0x0007a, 0x006ae,
0x01c3c, 0x03aba, 0x058e9, 0x072cc, 0x0d2dd, 0x0d22d, 0x0eec1, 0x0eedb,
0x1d2a2, 0x1ef5b, 0x357e2, 0x3abbf, 0x1d2f9, 0x35004, 0x3a5dc, 0x351fc,
0x3976c, 0x6a3c6, 0x6a3cb, 0x3e5ea, 0xe59f3, 0x6a3ce, 0x69452, 0xe59f0,
0x74b90, 0xd4279, 0xd427b, 0x7cbb5, 0x5b0c5, 0x3a5e3, 0x3a5e2, 0x000d0,
0x00775, 0x01efe, 0x03dd5, 0x0728c, 0x07cb9, 0x0e1a2, 0x0ea85, 0x0eed8,
0x1a30a, 0x1aa4f, 0x3a5df, 0x35008, 0x3a5e0, 0x3e5f4, 0x3e5f7, 0xb1d6c,
0x5843e, 0x34a70, 0x72df8, 0x74b6b, 0xd427f, 0x72df0, 0x5b0bf, 0x5b0c0,
0xd46b0, 0x72def, 0xe59f8, 0x162e64, 0xb1d6f, 0x3a5e0, 0x39427, 0x69166,
0x6a3e2, 0x6a3e3, 0x74a8d, 0xd427e, 0x1d5d97, 0xd46b4, 0x5b0d8, 0x6a3d3,
0x000e0, 0x00b63, 0x034cc, 0x06a33, 0x073c9, 0x0e1a0, 0x0f7fd, 0x0f9cc,
0x1617d, 0x1caeb, 0x1f4a9, 0x3abb3, 0x69450, 0x39420, 0x39777, 0x3e5e0,
0x6a3d4, 0x6a3ed, 0xb6166, 0xe59f1, 0xb1d6e, 0xe5676, 0x6a3ea, 0xe5674,
0xb6163, 0xd46b7, 0x7cba6, 0xd46ba, 0x1d5d94, 0xb6164, 0x6a3f1, 0x7cba2,
0x69451, 0x72dfa, 0xd46bb, 0x72df7, 0x74b94, 0x1cecbf, 0xe59fa, 0x16009b,
0x6a3e4, 0x000e6, 0x00e94, 0x03876, 0x070ef, 0x0d52a, 0x16015, 0x16014,
0x1abf9, 0x1cf17, 0x34a79, 0x34650, 0x3e705, 0x6a3d0, 0x58430, 0x74b9d,
0x7be7e, 0x5b0be, 0x39773, 0x6a3de, 0x000fb, 0x00f7b, 0x03dd7, 0x07bd0,
0x0e59c, 0x0f9cd, 0x1cf18, 0x1d2ff, 0x34a7a, 0x39429, 0x3500c, 0x72de0,
0x69456, 0x7be7c, 0xd46b5, 0xd46b2, 0x6a3dd, 0x001a2, 0x0163b, 0x06913,
0x0b016, 0x0fa42, 0x1a32d, 0x1cf06, 0x34a7c, 0x34a7d, 0xb6161, 0x35481,
0x3e5fa, 0x7cba0, 0x7be7f, 0x7cba3, 0x7cba7, 0x5b0d3, 0x72de6, 0x6a3dc,
0x001a9, 0x01ab4, 0x06a34, 0x0d46a, 0x16130, 0x1ef5f, 0x1f532, 0x1f536,
0x3942e, 0x58436, 0x6a3db, 0x6945b, 0x001c9, 0x01ca0, 0x0728b, 0x0eed9,
0x1f539, 0x1ca1d, 0x39765, 0x39766, 0x58439, 0x6945d, 0x39767, 0x001d3,
0x01f2c, 0x07bfc, 0x16161, 0x34652, 0x3a5ed, 0x3548d, 0x58438, 0x6a3da,
0x002c1, 0x02c5e, 0x0d335, 0x1ab1a, 0x2d874, 0x35006, 0x35484, 0x5b0cc,
0x74b9a, 0x72df3, 0x6a3d6, 0x002da, 0x034b3, 0x0d5ae, 0x1caee, 0x2d871,
0x357e3, 0x74b97, 0x72df9, 0x580ba, 0x5b0d4, 0x0034d, 0x0354e, 0x0f750,
0x1cbc0, 0x3a5e7, 0x3a5e4, 0x00385, 0x03a58, 0x16c41, 0x2c5cf, 0x3e5e1,
0x74b6c, 0xe5677, 0x6a3df, 0x00390, 0x03e50, 0x163c2, 0x2d876, 0x35482,
0x5b0d6, 0x5843a, 0x0039f, 0x0585e, 0x1a583, 0x3500f, 0x74b93, 0x39771,
0x003e4, 0x06912, 0x16c43, 0x357e1, 0x0058a, 0x0696f, 0x1f538, 0x5b0c9,
0x6a3cf, 0x005b6, 0x06af8, 0x1f534, 0x58483, 0x6a3e0, 0x00695, 0x07d02,
0x1cae8, 0x58485, 0x006a2, 0x0754a, 0x357ee, 0x3977b, 0x00748, 0x074b2,
0x34a7b, 0x00729, 0x0b1e0, 0x34649, 0x3e5e3, 0x0073d, 0x0d2c4, 0x3e5e6,
0x007bb, 0x0b099, 0x39762, 0x5b0ce, 0x6945f, 0x007d1, 0x0d5ab, 0x39779,
0x007d3, 0x0d52f, 0x39763, 0x6945c, 0x00b1a, 0x0d2c5, 0x35489, 0x00d23,
0x0eaed, 0x3e5f8, 0x00d32, 0x16016, 0x3e5fb, 0x00d41, 0x0e768, 0x3a5ed,
0x00e1f, 0x16017, 0x58027, 0x00ead, 0x0fa07, 0x69455, 0x00e54, 0x1612b,
0x00e55, 0x1a581, 0x00f78, 0x1a32b, 0x580bc, 0x6a3ee, 0x00f79, 0x1abfd,
0x00f95, 0x1ab18, 0x6a3f0, 0x01637, 0x1aa4d, 0x0162d, 0x1f53c, 0x6a3f3,
0x01a31, 0x1a810, 0x39769, 0x01a50, 0x1caef, 0x01a36, 0x1a32e, 0x01a67,
0x1f38e, 0x01a85, 0x1ef59, 0x01aa6, 0x1ef83, 0x01d51, 0x2c012, 0x01d53,
0x2d879, 0x01d5e, 0x35005, 0x01cba, 0x1cf04, 0x69453, 0x01d2d, 0x351ff,
0x01f2d, 0x2d86f, 0x01f29, 0x35007, 0x02c22, 0x351fa, 0x02c03, 0x3a5ec,
0x02c5f, 0x3a5eb, 0x02c58, 0x34a6b, 0x03469, 0x356be, 0x02c59, 0x34a6c,
0x0346a, 0x3a5ea, 0x034bd, 0x034bf, 0x356bf, 0x0386a, 0x03ab9, 0x5843f,
0x0386b, 0x3a5f5, 0x03a4b, 0x39421, 0x03aa4, 0x3a5e9, 0x03a5a, 0x03960,
0x3977e, 0x03de9, 0x03958, 0x03df7, 0x039e1, 0x3e5e4, 0x0395f, 0x69458,
0x03e91, 0x03df2, 0x39428, 0x058f2, 0x03e80, 0x6a3c3, 0x03e93, 0x694c0,
0x058b8, 0x5b0ca, 0x0584f, 0x694c1, 0x058f1, 0x068d6, 0x06a10, 0x06ac3,
0x06a32, 0x070d2, 0x06911, 0x074b1, 0x07494, 0x06ad4, 0x06ad6, 0x072b8,
0x06afa, 0x074b3, 0x07540, 0x073ce, 0x0b005, 0x074b3, 0x07495, 0x074b9,
0x0d336, 0x07bff, 0x07763, 0x073c8, 0x07d29, 0x0b622, 0x0d221, 0x0d181,
0x0b1d1, 0x074b8, 0x0b1d0, 0x0d19b, 0x0d2c3, 0x0b172, 0x0d2dc, 0x0b623,
0x0d5aa, 0x0d426, 0x0d182, 0x0e795, 0x0e1d1, 0x0d337, 0x0e96c, 0x0e5e4,
0x0e514, 0x0eaee, 0x16000, 0x0e767, 0x0e1a1, 0x0e78f, 0x16004, 0x0f7c2,
0x0e799, 0x0e5e7, 0x0e566, 0x0e769, 0x0f751, 0x0eede, 0x0fa06, 0x16005,
0x0fa9f, 0x1a5e6, 0x0e766, 0x1636f, 0x0eedd, 0x0eec0, 0x1a309, 0x1ceca,
0x163cd, 0x0f9cb, 0x0eedf, 0x1a582, 0x1612d, 0x0e5e5, 0x1abf8, 0x1a30c,
0x1ca1f, 0x163cc, 0x1a35c, 0x1ca1e, 0x1aa51, 0x163ac, 0x1a84e, 0x1a53f,
0x1cf16, 0x1d2fc, 0x1a5b3, 0x1ab19, 0x1a81f, 0x1d5c3, 0x16c3f, 0x1d5c1,
0x1d2fc, 0x1f4aa, 0x1a812, 0x1f535, 0x1cf12, 0x1a817, 0x1617c, 0x1ab0b,
0x1d2f8, 0x1ef82, 0x2d87a, 0x1d52f, 0x1f530, 0x1aa48, 0x35487, 0x1d2fd,
0x1f4ad, 0x1cf11, 0x3461b, 0x35485, 0x1ca20, 0x1caed, 0x1cae6, 0x1abff,
0x3464f, 0x34a6f, 0x1ef81, 0x3464b, 0x39d96, 0x1f383, 0x1f537, 0x1cf14,
0x2c5ce, 0x3500e, 0x2c251, 0x1caec, 0x1f387, 0x34654, 0x357e4, 0x2d878,
0x3500b, 0x35480, 0x3a5e8, 0x3548e, 0x34b64, 0x1f4a8, 0x35003, 0x3e5df,
0x2d870, 0x357e6, 0x3e5f0, 0x1ef5a, 0x3a5ea, 0x1f388, 0x3e703, 0x2c24e,
0x3a5e2, 0x351fd, 0x2c6dd, 0x3e704, 0x351fe, 0x2d875, 0x5b0c7, 0x3976a,
0x3a5e6, 0x39423, 0x58480, 0x2c246, 0x3a5e3, 0x2d877, 0x3e5f1, 0x3abbe,
0x58489, 0x3e5f9, 0x357e0, 0x3abbc, 0x5b0c6, 0x69167, 0x69165, 0x3e5e9,
0x39422, 0x3976f, 0x3977d, 0x3e5de, 0x6a3c9, 0x58b98, 0x3a5f6, 0x3a5d0,
0x58486, 0x6a3c1, 0x3e5fc, 0x5b0dc, 0x3548f, 0x3942d, 0x694c9, 0x58484,
0x3a5e8, 0x74b9b, 0x74b96, 0x694d0, 0x58488, 0x3a5e4, 0x3942a, 0x72ec2,
0x39776, 0x5b0d1, 0x5b0cf, 0x3a5d6, 0xe59fc, 0x5b0c8, 0x3e5e7, 0x7cbb7,
0x70e87, 0x7cbab, 0x5b0c2, 0x694c3, 0x74a8e, 0x3e5f3, 0x6a3cd, 0x72dfe,
0x73b2e, 0x72ec0, 0x694c5, 0x58437, 0x694c8, 0x72dff, 0x39435, 0x5843d,
0x6a3d7, 0x72ec1, 0xd22c8, 0x694cf, 0xb6173, 0x3e5fe, 0x580bb, 0xe59f2,
0xb616e, 0xb6175, 0x3a5da, 0x5b0bd, 0x694cc, 0x5843c, 0x694c7, 0x74b92,
0x72ec3, 0x694c6, 0xb6170, 0x7cbac, 0xb1733, 0x7cba4, 0xb6167, 0x72de7,
0x72de4, 0x6a3c0, 0x3e5ef, 0x162e65, 0x72de3, 0x72dfb, 0x6a35f, 0x6a3eb,
};

const uint8_t coef2_huffbits[1336] = {
11, 9, 2, 3, 4, 4, 5, 6,
6, 7, 7, 8, 8, 8, 9, 9,
9, 9, 10, 10, 10, 10, 11, 11,
11, 11, 11, 11, 11, 12, 12, 12,
12, 12, 12, 12, 12, 12, 13, 13,
13, 13, 13, 13, 13, 13, 13, 14,
14, 14, 14, 14, 14, 14, 14, 14,
14, 14, 14, 14, 14, 15, 15, 15,
15, 15, 15, 15, 15, 15, 15, 15,
15, 15, 15, 15, 15, 16, 15, 16,
16, 16, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 16, 16, 16, 16,
17, 17, 17, 17, 17, 17, 17, 17,
17, 17, 17, 18, 17, 17, 17, 17,
17, 17, 17, 18, 18, 17, 17, 18,
17, 17, 18, 17, 18, 18, 18, 18,
19, 18, 18, 18, 18, 18, 18, 20,
18, 18, 18, 19, 19, 18, 19, 18,
19, 19, 18, 19, 19, 18, 19, 19,
19, 19, 18, 19, 19, 19, 19, 19,
19, 19, 20, 20, 20, 19, 19, 20,
19, 20, 19, 19, 20, 19, 19, 20,
20, 20, 20, 19, 20, 21, 19, 3,
5, 7, 8, 9, 9, 10, 11, 11,
12, 12, 12, 13, 13, 13, 13, 14,
14, 14, 14, 15, 15, 15, 15, 15,
15, 15, 15, 15, 15, 15, 16, 16,
15, 15, 15, 15, 16, 16, 16, 16,
17, 16, 17, 17, 16, 17, 17, 17,
17, 17, 17, 16, 17, 17, 17, 17,
18, 17, 17, 18, 18, 18, 18, 18,
19, 18, 18, 18, 18, 18, 18, 19,
19, 18, 18, 18, 18, 19, 18, 19,
19, 19, 20, 19, 18, 19, 19, 19,
19, 19, 19, 19, 19, 19, 19, 20,
20, 19, 20, 19, 20, 19, 20, 19,
19, 21, 20, 20, 19, 4, 7, 8,
10, 11, 11, 12, 12, 13, 13, 14,
14, 14, 14, 15, 15, 15, 15, 15,
16, 16, 16, 16, 16, 16, 16, 17,
17, 17, 17, 17, 17, 17, 16, 16,
16, 16, 17, 17, 17, 17, 18, 18,
18, 17, 17, 18, 18, 18, 18, 18,
18, 18, 18, 18, 19, 18, 18, 18,
19, 18, 19, 19, 19, 20, 20, 20,
19, 19, 19, 19, 19, 19, 19, 21,
21, 20, 19, 5, 8, 10, 11, 12,
13, 13, 13, 14, 14, 15, 15, 15,
15, 16, 16, 16, 16, 16, 17, 17,
17, 17, 17, 17, 17, 17, 18, 17,
18, 17, 17, 17, 17, 17, 17, 17,
17, 17, 17, 17, 19, 18, 19, 18,
18, 18, 18, 18, 19, 18, 17, 17,
18, 18, 19, 19, 19, 19, 18, 18,
18, 19, 6, 9, 11, 12, 13, 13,
14, 14, 14, 15, 15, 16, 16, 16,
16, 16, 16, 17, 17, 17, 18, 18,
18, 18, 18, 18, 18, 18, 18, 18,
18, 17, 18, 18, 17, 18, 18, 18,
18, 18, 18, 19, 19, 18, 18, 18,
19, 19, 19, 20, 19, 19, 18, 19,
19, 20, 21, 21, 19, 19, 18, 6,
10, 12, 13, 14, 14, 14, 15, 15,
15, 16, 16, 17, 17, 17, 17, 17,
17, 17, 18, 18, 19, 18, 18, 18,
19, 18, 18, 18, 19, 18, 18, 18,
18, 18, 18, 18, 18, 18, 18, 18,
19, 20, 20, 19, 19, 19, 19, 20,
20, 19, 20, 19, 19, 19, 20, 20,
20, 19, 19, 18, 19, 7, 10, 12,
13, 14, 15, 15, 15, 16, 16, 17,
17, 17, 17, 17, 17, 18, 18, 18,
18, 19, 18, 19, 19, 19, 20, 19,
18, 19, 19, 18, 18, 19, 19, 19,
18, 19, 19, 20, 19, 18, 20, 21,
20, 20, 19, 19, 21, 20, 21, 20,
20, 20, 19, 19, 20, 20, 21, 20,
19, 7, 11, 13, 14, 15, 15, 15,
16, 16, 17, 17, 17, 17, 18, 18,
18, 18, 18, 19, 20, 19, 19, 20,
19, 19, 19, 19, 19, 19, 19, 19,
18, 18, 19, 20, 19, 19, 19, 20,
19, 19, 19, 20, 19, 20, 20, 21,
20, 20, 20, 21, 22, 20, 19, 20,
20, 21, 20, 21, 20, 19, 8, 11,
13, 14, 15, 16, 16, 16, 17, 17,
17, 18, 18, 18, 18, 18, 19, 18,
19, 19, 19, 19, 21, 19, 19, 21,
19, 20, 20, 20, 19, 18, 18, 8,
12, 14, 15, 16, 16, 16, 16, 17,
17, 17, 19, 18, 18, 19, 19, 20,
19, 18, 20, 19, 20, 20, 19, 19,
20, 20, 21, 21, 20, 19, 19, 19,
19, 19, 19, 20, 21, 20, 19, 19,
8, 12, 14, 15, 16, 16, 17, 17,
17, 18, 18, 18, 19, 19, 19, 19,
19, 19, 20, 21, 20, 21, 19, 21,
20, 20, 20, 20, 21, 20, 19, 20,
19, 20, 20, 20, 19, 22, 21, 21,
19, 9, 12, 14, 15, 16, 17, 17,
17, 18, 18, 18, 19, 19, 19, 19,
20, 19, 19, 19, 9, 13, 15, 16,
17, 17, 18, 18, 18, 19, 18, 20,
19, 20, 20, 20, 19, 9, 13, 15,
16, 17, 17, 18, 18, 18, 20, 18,
19, 20, 20, 20, 20, 19, 20, 19,
9, 13, 15, 16, 17, 18, 18, 18,
19, 19, 19, 19, 10, 14, 16, 17,
18, 18, 19, 19, 19, 19, 19, 10,
14, 16, 17, 18, 18, 18, 19, 19,
10, 14, 16, 17, 18, 18, 18, 19,
19, 20, 19, 10, 14, 16, 18, 18,
18, 19, 20, 19, 19, 10, 14, 17,
18, 18, 18, 10, 15, 17, 18, 19,
19, 21, 19, 11, 15, 17, 18, 18,
19, 19, 11, 15, 17, 18, 19, 19,
11, 15, 17, 18, 11, 15, 18, 19,
19, 11, 15, 18, 19, 19, 11, 16,
18, 19, 11, 15, 18, 19, 11, 16,
18, 12, 16, 18, 19, 12, 16, 19,
12, 16, 19, 19, 19, 12, 16, 19,
12, 16, 19, 19, 12, 16, 18, 12,
16, 19, 12, 17, 19, 12, 17, 19,
12, 17, 19, 12, 17, 19, 13, 17,
13, 17, 13, 17, 19, 19, 13, 17,
13, 17, 19, 13, 17, 13, 18, 19,
13, 17, 19, 13, 18, 13, 17, 13,
18, 13, 18, 13, 18, 13, 18, 13,
18, 13, 18, 14, 18, 19, 14, 18,
14, 18, 14, 18, 14, 18, 14, 19,
14, 19, 14, 18, 14, 18, 14, 18,
14, 19, 14, 14, 18, 14, 14, 19,
14, 18, 14, 19, 14, 19, 14, 15,
19, 15, 15, 15, 15, 19, 15, 19,
15, 15, 19, 15, 15, 19, 15, 19,
15, 19, 15, 19, 15, 15, 15, 15,
15, 15, 15, 15, 15, 15, 15, 16,
15, 15, 15, 16, 16, 16, 15, 16,
16, 16, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 16, 16, 16, 16,
16, 16, 16, 17, 16, 16, 16, 17,
17, 16, 17, 17, 16, 17, 17, 17,
17, 17, 17, 17, 17, 17, 17, 17,
17, 17, 17, 17, 17, 17, 17, 18,
17, 17, 17, 17, 17, 17, 17, 17,
18, 17, 17, 18, 17, 17, 17, 17,
18, 18, 17, 17, 17, 17, 17, 17,
17, 18, 17, 18, 18, 17, 17, 17,
18, 18, 18, 17, 18, 17, 18, 18,
18, 18, 18, 18, 18, 18, 18, 17,
18, 18, 18, 18, 19, 18, 18, 18,
18, 18, 18, 18, 18, 18, 18, 18,
18, 18, 18, 18, 18, 18, 18, 19,
18, 18, 19, 18, 18, 18, 19, 18,
19, 18, 18, 19, 18, 18, 19, 19,
19, 19, 19, 18, 19, 18, 19, 18,
19, 19, 18, 18, 19, 19, 19, 19,
19, 19, 19, 19, 19, 19, 18, 19,
19, 19, 19, 19, 18, 19, 19, 19,
19, 19, 19, 19, 19, 19, 19, 20,
19, 19, 19, 19, 21, 19, 19, 20,
19, 20, 19, 19, 19, 19, 19, 20,
20, 20, 19, 19, 19, 20, 19, 19,
19, 20, 20, 19, 20, 19, 19, 21,
20, 20, 19, 19, 19, 19, 19, 19,
20, 19, 20, 20, 20, 20, 20, 20,
20, 19, 19, 21, 20, 20, 19, 19,
};

const uint32_t coef3_huffcodes[1072] = {
0x001b2, 0x00069, 0x00000, 0x00004, 0x00006, 0x0000e, 0x00014, 0x00019,
0x00016, 0x0002b, 0x00030, 0x0003d, 0x0003c, 0x0005a, 0x0005f, 0x0006d,
0x0007e, 0x0005f, 0x0007f, 0x000b6, 0x000bc, 0x000d8, 0x000f2, 0x000fe,
0x000bc, 0x000fc, 0x00161, 0x0016e, 0x00174, 0x00176, 0x001a2, 0x001e3,
0x001f3, 0x00174, 0x0017a, 0x001ea, 0x002a8, 0x002c4, 0x002e6, 0x00314,
0x00346, 0x00367, 0x003e9, 0x002e5, 0x002ee, 0x003d6, 0x00555, 0x00554,
0x00557, 0x005c3, 0x005d6, 0x006e0, 0x0062f, 0x006e2, 0x00799, 0x00789,
0x007fa, 0x005ce, 0x007fe, 0x005ec, 0x007cc, 0x007af, 0x00aa7, 0x00b19,
0x00b94, 0x00b85, 0x00b9f, 0x00c48, 0x00c45, 0x00dd8, 0x00c4c, 0x00c4b,
0x00d99, 0x00d1f, 0x00dc2, 0x00f95, 0x00fa2, 0x00bb5, 0x00b9f, 0x00f5d,
0x00bbf, 0x00f47, 0x0154a, 0x00fd5, 0x00f45, 0x00f7f, 0x0160d, 0x01889,
0x01757, 0x01722, 0x018b3, 0x0172d, 0x01a39, 0x01a18, 0x01bb3, 0x01b30,
0x01e63, 0x0173c, 0x01b35, 0x01723, 0x01e80, 0x01fee, 0x01761, 0x01ffc,
0x01f7f, 0x02c7c, 0x01fa1, 0x0177b, 0x01755, 0x0175a, 0x01fa6, 0x02eab,
0x0310a, 0x02c69, 0x03669, 0x03127, 0x03103, 0x02e43, 0x03662, 0x03165,
0x03124, 0x0313b, 0x03111, 0x03668, 0x0343b, 0x03c52, 0x03efc, 0x02e6c,
0x03fda, 0x03ef8, 0x02e7b, 0x03ee2, 0x03cc5, 0x03d72, 0x058c0, 0x03df8,
0x02ea9, 0x03e7e, 0x0556d, 0x05c82, 0x03d71, 0x03e7b, 0x03c42, 0x058d7,
0x03f4e, 0x06200, 0x03d70, 0x05cb2, 0x05c96, 0x05cb0, 0x03f45, 0x05cb1,
0x02e6d, 0x03110, 0x02f68, 0x05c90, 0x07ca6, 0x07c88, 0x06204, 0x062c8,
0x078a6, 0x07986, 0x079d5, 0x0b1ad, 0x07989, 0x0b079, 0x05cdd, 0x0aad4,
0x05de8, 0x07dcd, 0x07987, 0x05d67, 0x05d99, 0x0b91d, 0x07cf1, 0x05d9b,
0x079d7, 0x0b07b, 0x05c85, 0x05d9a, 0x07dcc, 0x07ebf, 0x07dce, 0x07dfb,
0x07ec0, 0x07d1a, 0x07a07, 0x05c84, 0x0c471, 0x07cf2, 0x0baef, 0x0b9d2,
0x05deb, 0x07bd6, 0x0b845, 0x05d98, 0x0b91a, 0x0bae8, 0x0c4e0, 0x0dc31,
0x0f93d, 0x0bbce, 0x0d1d2, 0x0f7a9, 0x0d9b9, 0x0bbcb, 0x0b900, 0x0aad7,
0x0babd, 0x0c4e1, 0x0f46f, 0x0c588, 0x0c58b, 0x160e6, 0x0bbcf, 0x0bac3,
0x0f945, 0x0f7a3, 0x0d1c1, 0x0fb8e, 0x0f7a4, 0x0fb8c, 0x0f40c, 0x0c473,
0x0fd72, 0x0bbcd, 0x0fffa, 0x0f940, 0x0bbc9, 0x0f7a8, 0x1a1ed, 0x0bbc5,
0x1f26f, 0x163fd, 0x160c7, 0x1a1f5, 0x0f947, 0x163fc, 0x154b3, 0x0fff6,
0x163f6, 0x160e9, 0x1a1f0, 0x0bab9, 0x0baba, 0x17086, 0x0b903, 0x0fd75,
0x0f308, 0x176f3, 0x163ff, 0x0fd7d, 0x1bb78, 0x163fb, 0x188db, 0x1a1f7,
0x154b2, 0x172fd, 0x163f4, 0x1bb73, 0x172ff, 0x0babc, 0x0f97d, 0x1a1f3,
0x1bb6d, 0x1ffd5, 0x1a1f4, 0x1f272, 0x17380, 0x17382, 0x1ffe7, 0x0bac8,
0x0bbc4, 0x188d3, 0x160e0, 0x0fd7b, 0x1725f, 0x172f5, 0x1bb79, 0x1fad9,
0x1f269, 0x188d0, 0x0bac4, 0x0bac5, 0x31185, 0x188d2, 0x188cc, 0x31187,
0x3e7fe, 0x188d1, 0x1bb6c, 0x1f268, 0x1fad2, 0x1ffd9, 0x1a1ea, 0x1bb68,
0x1facb, 0x3fdb2, 0x1e81a, 0x188ce, 0x172fb, 0x1a1ef, 0x1face, 0x1bb70,
0x0bac1, 0x1bb6b, 0x172f8, 0x1bb66, 0x1ffdf, 0x1bb6a, 0x1ffd7, 0x1f266,
0x176f8, 0x37653, 0x1fa7e, 0x31182, 0x1fac8, 0x2c7e3, 0x370ee, 0x176ec,
0x176e9, 0x2e4bc, 0x160c5, 0x3765a, 0x3ce9c, 0x17373, 0x176e8, 0x188d4,
0x176f1, 0x176ef, 0x37659, 0x1bb7c, 0x1ffde, 0x176f2, 0x3118b, 0x2c7d4,
0x37651, 0x5ce9f, 0x37650, 0x31191, 0x3f4f6, 0x3f4f5, 0x7a06c, 0x1fac1,
0x5c97b, 0x2c7e0, 0x79d3a, 0x3e7fd, 0x2c7df, 0x3f4f0, 0x7a06d, 0x376c1,
0x79d3b, 0x00004, 0x00014, 0x00059, 0x000ab, 0x000b8, 0x00177, 0x001f5,
0x001f2, 0x00315, 0x003fc, 0x005bd, 0x0062d, 0x006e8, 0x007dd, 0x00b04,
0x007cd, 0x00b1e, 0x00d1e, 0x00f15, 0x00f3b, 0x00f41, 0x01548, 0x018b0,
0x0173b, 0x01884, 0x01a1c, 0x01bb4, 0x01f25, 0x017b5, 0x0176d, 0x01ef8,
0x02e73, 0x03107, 0x03125, 0x03105, 0x02e49, 0x03ce8, 0x03ef9, 0x03e5e,
0x02e72, 0x03471, 0x03fd9, 0x0623f, 0x078a0, 0x06867, 0x05cb3, 0x06272,
0x068ec, 0x06e9a, 0x079d4, 0x06e98, 0x0b1aa, 0x06e1a, 0x07985, 0x068ee,
0x06e9b, 0x05c88, 0x0b1ac, 0x07dfa, 0x05d65, 0x07cf0, 0x07cbf, 0x0c475,
0x160eb, 0x1bb7e, 0x0f7a6, 0x1fedd, 0x160e3, 0x0fffb, 0x0fb8d, 0x0fff9,
0x0d1c0, 0x0c58c, 0x1a1e9, 0x0bab8, 0x0f5cf, 0x0fff5, 0x376c5, 0x1a1ec,
0x160ed, 0x1fede, 0x1fac9, 0x1a1eb, 0x1f224, 0x176ee, 0x0fd79, 0x17080,
0x17387, 0x1bb7a, 0x1ffe9, 0x176f7, 0x17385, 0x17781, 0x2c7d5, 0x17785,
0x1ffe3, 0x163f5, 0x1fac2, 0x3e7f9, 0x3118d, 0x3fdb1, 0x1ffe2, 0x1f226,
0x3118a, 0x2c7d9, 0x31190, 0x3118c, 0x3f4f3, 0x1bb7f, 0x1bb72, 0x31184,
0xb92f4, 0x3e7fb, 0x6e1d9, 0x1faca, 0x62300, 0x3fdb8, 0x3d037, 0x3e7fc,
0x62301, 0x3f4f2, 0x1f26a, 0x0000e, 0x00063, 0x000f8, 0x001ee, 0x00377,
0x003f7, 0x006e3, 0x005cc, 0x00b05, 0x00dd2, 0x00fd4, 0x0172e, 0x0172a,
0x01e23, 0x01f2d, 0x01763, 0x01769, 0x0176c, 0x02e75, 0x03104, 0x02ec1,
0x03e58, 0x0583f, 0x03f62, 0x03f44, 0x058c5, 0x0623c, 0x05cf4, 0x07bd7,
0x05d9d, 0x0aad2, 0x05d66, 0x0b1a9, 0x0b078, 0x07cfe, 0x0b918, 0x0c46f,
0x0b919, 0x0b847, 0x06e1b, 0x0b84b, 0x0aad8, 0x0fd74, 0x172f4, 0x17081,
0x0f97c, 0x1f273, 0x0f7a0, 0x0fd7c, 0x172f7, 0x0fd7a, 0x1bb77, 0x172fe,
0x1f270, 0x0fd73, 0x1bb7b, 0x1a1bc, 0x1bb7d, 0x0bbc3, 0x172f6, 0x0baeb,
0x0fb8f, 0x3f4f4, 0x3fdb4, 0x376c8, 0x3e7fa, 0x1ffd0, 0x62303, 0xb92f5,
0x1f261, 0x31189, 0x3fdb5, 0x2c7db, 0x376c9, 0x1fad6, 0x1fad1, 0x00015,
0x000f0, 0x002e0, 0x0058e, 0x005d7, 0x00c4d, 0x00fa1, 0x00bdb, 0x01756,
0x01f70, 0x02c19, 0x0313c, 0x0370f, 0x03cc0, 0x02ea8, 0x058c6, 0x058c7,
0x02eb7, 0x058d0, 0x07d18, 0x0aa58, 0x0b848, 0x05d9e, 0x05d6c, 0x0b84c,
0x0c589, 0x0b901, 0x163f8, 0x0bac9, 0x0b9c5, 0x0f93c, 0x188d8, 0x0bbc7,
0x160ec, 0x0fd6f, 0x188d9, 0x160ea, 0x0f7a7, 0x0f944, 0x0baab, 0x0dc3a,
0x188cf, 0x176fb, 0x2c7d8, 0x2c7d7, 0x1bb75, 0x5ce9e, 0x62302, 0x370ed,
0x176f4, 0x1ffd1, 0x370ef, 0x3f4f8, 0x376c7, 0x1ffe1, 0x376c6, 0x176ff,
0x6e1d8, 0x176f6, 0x17087, 0x0f5cd, 0x00035, 0x001a0, 0x0058b, 0x00aac,
0x00b9a, 0x0175f, 0x01e22, 0x01e8c, 0x01fb2, 0x0310b, 0x058d1, 0x0552e,
0x05c27, 0x0686e, 0x07ca7, 0x0c474, 0x0dc33, 0x07bf2, 0x05de9, 0x07a35,
0x0baaa, 0x0b9eb, 0x0fb95, 0x0b9b8, 0x17381, 0x1f262, 0x188cd, 0x17088,
0x172fa, 0x0f7a2, 0x1fad3, 0x0bac0, 0x3765c, 0x1fedf, 0x1f225, 0x1fad4,
0x2c7da, 0x5ce9d, 0x3e7f8, 0x1e203, 0x188d7, 0x00054, 0x002c0, 0x007a1,
0x00f78, 0x01b36, 0x01fa3, 0x0313a, 0x03436, 0x0343a, 0x07d1d, 0x07bd8,
0x05cdf, 0x0b846, 0x0b189, 0x0d9b8, 0x0fff8, 0x0d9be, 0x0c58a, 0x05dea,
0x0d1d3, 0x160e4, 0x1f26b, 0x188da, 0x1e202, 0x2c7d2, 0x163fe, 0x31193,
0x17782, 0x376c2, 0x2c7d1, 0x3fdb0, 0x3765d, 0x2c7d0, 0x1fad0, 0x1e201,
0x188dd, 0x2c7e2, 0x37657, 0x37655, 0x376c4, 0x376c0, 0x176ea, 0x0006f,
0x003cf, 0x00dd5, 0x01f23, 0x02c61, 0x02ed0, 0x05d54, 0x0552d, 0x07883,
0x0b1a8, 0x0b91c, 0x0babf, 0x0b902, 0x0f7aa, 0x0f7a5, 0x1a1e8, 0x1ffd6,
0x0babe, 0x1a1bf, 0x163f3, 0x1ffd8, 0x1fad7, 0x1f275, 0x1ffdc, 0x0007d,
0x005bc, 0x01549, 0x02a99, 0x03def, 0x06273, 0x079d6, 0x07d1b, 0x0aad3,
0x0d0fc, 0x2c7dd, 0x188d6, 0x0bac2, 0x2c7e1, 0x1bb76, 0x1a1bd, 0x31186,
0x0fd78, 0x1a1be, 0x31183, 0x3fdb6, 0x3f4f1, 0x37652, 0x1fad5, 0x3f4f9,
0x3e7ff, 0x5ce9c, 0x3765b, 0x31188, 0x17372, 0x000bd, 0x0078b, 0x01f21,
0x03c43, 0x03ded, 0x0aad6, 0x07ec1, 0x0f942, 0x05c86, 0x17089, 0x0babb,
0x1ffe8, 0x2c7de, 0x1f26e, 0x1fac4, 0x3f4f7, 0x37656, 0x1fa7d, 0x376c3,
0x3fdb3, 0x3118f, 0x1fac6, 0x000f8, 0x007ed, 0x01efd, 0x03e7a, 0x05c91,
0x0aad9, 0x0baec, 0x0dc32, 0x0f46e, 0x1e200, 0x176fa, 0x3765e, 0x3fdb7,
0x2c7d6, 0x3fdb9, 0x37654, 0x37658, 0x3118e, 0x1ffdb, 0x000f6, 0x00c43,
0x03106, 0x068ef, 0x0b84d, 0x0b188, 0x0bbcc, 0x1f264, 0x1bb69, 0x17386,
0x1fac0, 0x00171, 0x00f39, 0x03e41, 0x068ed, 0x0d9bc, 0x0f7a1, 0x1bb67,
0x1ffdd, 0x176f9, 0x001b9, 0x00f7d, 0x03f63, 0x0d0fd, 0x0b9ea, 0x188dc,
0x1fac3, 0x1a1f2, 0x31192, 0x1ffe4, 0x001f6, 0x01754, 0x06865, 0x0f309,
0x160e5, 0x176f5, 0x3765f, 0x1facc, 0x001e9, 0x01a1a, 0x06201, 0x0f105,
0x176f0, 0x002df, 0x01756, 0x05d6d, 0x163fa, 0x176ed, 0x00342, 0x02e40,
0x0d0ff, 0x17082, 0x003cd, 0x02a98, 0x0fffc, 0x2c7dc, 0x1fa7f, 0x003fe,
0x03764, 0x0fffd, 0x176fc, 0x1fac5, 0x002f7, 0x02ed1, 0x0fb97, 0x0058a,
0x02edc, 0x0bbc8, 0x005d4, 0x0623d, 0x160e8, 0x0062e, 0x05830, 0x163f9,
0x006eb, 0x06205, 0x1f274, 0x007de, 0x062c9, 0x1f265, 0x005c9, 0x05cde,
0x1ffd3, 0x005d4, 0x07988, 0x007ce, 0x0b849, 0x00b1b, 0x05c89, 0x1fac7,
0x00b93, 0x05c83, 0x00b9e, 0x0f14f, 0x00c4a, 0x0b9c7, 0x00dd4, 0x0c470,
0x1f271, 0x00f38, 0x0fb96, 0x176eb, 0x00fa0, 0x163f7, 0x00bb2, 0x0b91b,
0x00bbe, 0x0f102, 0x00f44, 0x0f946, 0x1facd, 0x00f79, 0x0d9bd, 0x0154d,
0x0bbc6, 0x00fd2, 0x160e7, 0x0172b, 0x188cb, 0x0175e, 0x0fd76, 0x0175c,
0x1bb71, 0x0189f, 0x1a1ee, 0x01f24, 0x1a1f6, 0x01ba7, 0x0bbca, 0x01f7d,
0x0ffff, 0x01f2e, 0x1bb65, 0x01bb5, 0x172f9, 0x01fef, 0x1f26c, 0x01f3e,
0x0fd77, 0x01762, 0x1bb6e, 0x01ef9, 0x172fc, 0x01fa0, 0x02ab7, 0x02e4a,
0x1f267, 0x01fb3, 0x1ffda, 0x02e42, 0x03101, 0x17780, 0x0313d, 0x03475,
0x17784, 0x03126, 0x1facf, 0x03c51, 0x17783, 0x03e40, 0x1ffe5, 0x03663,
0x1ffe0, 0x03e8f, 0x1f26d, 0x0343c, 0x03cc1, 0x176fd, 0x03e45, 0x02ec0,
0x03f61, 0x03dee, 0x03fd8, 0x0583e, 0x02e45, 0x03e59, 0x03d02, 0x05ce8,
0x05568, 0x176fe, 0x02f69, 0x1fad8, 0x058c1, 0x05c83, 0x1ffe6, 0x06271,
0x06e1c, 0x062c7, 0x068e1, 0x0552f, 0x06864, 0x06866, 0x06e99, 0x05cbc,
0x07ca5, 0x078a1, 0x05c82, 0x07dcf, 0x0623b, 0x0623e, 0x068e8, 0x07a36,
0x05d9c, 0x0b077, 0x07cf3, 0x07a34, 0x07ca4, 0x07d19, 0x079d2, 0x07d1c,
0x07bd9, 0x0b84a, 0x0fb94, 0x0aad5, 0x0dc30, 0x07bf3, 0x0baee, 0x0b07a,
0x0c472, 0x0b91e, 0x0d9ba, 0x05d9f, 0x0d0fe, 0x0b9c6, 0x05c87, 0x0f14e,
0x0baed, 0x0b92e, 0x0f103, 0x0b9c4, 0x0fb91, 0x0d9bb, 0x0b1ab, 0x0c58d,
0x0fffe, 0x0f93b, 0x0f941, 0x0baea, 0x0b91f, 0x0f5cc, 0x0d9bf, 0x0f943,
0x0f104, 0x1f260, 0x0fb92, 0x0f93f, 0x0f3a6, 0x0bac7, 0x0f7ab, 0x0bac6,
0x17383, 0x0fd6d, 0x0bae9, 0x0fd6e, 0x1e74f, 0x188ca, 0x1f227, 0x0fb93,
0x0fb90, 0x0fff7, 0x17085, 0x17083, 0x160e1, 0x17084, 0x0f93e, 0x160e2,
0x160c6, 0x1a1f1, 0x1bb6f, 0x17384, 0x0fd70, 0x1f263, 0x188d5, 0x173a6,
0x0f5ce, 0x163f2, 0x0fd71, 0x1ffd2, 0x160c4, 0x1ffd4, 0x2c7d3, 0x1bb74,
};

const uint8_t coef3_huffbits[1072] = {
9, 7, 2, 3, 4, 4, 5, 5,
6, 6, 6, 6, 7, 7, 7, 7,
7, 8, 8, 8, 8, 8, 8, 8,
9, 9, 9, 9, 9, 9, 9, 9,
9, 10, 10, 10, 10, 10, 10, 10,
10, 10, 10, 11, 11, 11, 11, 11,
11, 11, 11, 11, 11, 11, 11, 11,
11, 12, 11, 12, 12, 12, 12, 12,
12, 12, 12, 12, 12, 12, 12, 12,
12, 12, 12, 12, 12, 13, 13, 13,
13, 13, 13, 13, 13, 13, 13, 13,
13, 13, 13, 13, 13, 13, 13, 13,
13, 14, 13, 14, 14, 13, 14, 13,
13, 14, 14, 14, 14, 14, 14, 14,
14, 14, 14, 14, 14, 14, 14, 14,
14, 14, 14, 14, 14, 14, 14, 15,
14, 14, 15, 14, 14, 15, 15, 15,
15, 15, 15, 15, 15, 15, 14, 15,
15, 15, 15, 15, 15, 15, 15, 15,
15, 14, 15, 15, 15, 15, 15, 15,
15, 15, 15, 16, 15, 16, 16, 16,
16, 15, 15, 16, 16, 16, 16, 16,
15, 16, 16, 16, 15, 16, 15, 15,
16, 15, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 16, 16, 16, 16,
16, 17, 16, 17, 16, 17, 17, 16,
17, 16, 17, 16, 16, 17, 17, 17,
16, 17, 16, 16, 17, 16, 17, 16,
17, 17, 16, 16, 17, 17, 17, 17,
17, 17, 17, 17, 16, 17, 17, 16,
17, 17, 17, 17, 17, 17, 17, 17,
16, 18, 17, 17, 17, 17, 17, 17,
17, 17, 17, 17, 17, 17, 16, 17,
17, 17, 17, 17, 17, 17, 17, 17,
17, 17, 17, 17, 17, 17, 17, 18,
17, 17, 17, 17, 18, 17, 17, 18,
19, 17, 17, 17, 18, 17, 17, 17,
18, 18, 18, 17, 17, 17, 18, 17,
17, 17, 17, 17, 17, 17, 17, 17,
18, 18, 18, 18, 18, 18, 18, 18,
18, 18, 17, 18, 18, 18, 18, 17,
18, 18, 18, 17, 17, 18, 18, 18,
18, 19, 18, 18, 19, 19, 20, 18,
19, 18, 19, 19, 18, 19, 20, 18,
19, 4, 6, 7, 8, 9, 9, 9,
10, 10, 10, 11, 11, 11, 11, 12,
12, 12, 12, 12, 12, 13, 13, 13,
13, 13, 13, 13, 13, 14, 14, 14,
14, 14, 14, 14, 14, 14, 14, 14,
14, 14, 14, 15, 15, 15, 15, 15,
15, 15, 15, 15, 16, 15, 15, 15,
15, 16, 16, 15, 16, 16, 15, 16,
17, 17, 17, 17, 17, 16, 16, 16,
16, 16, 17, 17, 17, 16, 18, 17,
17, 17, 18, 17, 17, 18, 17, 17,
17, 17, 17, 18, 17, 18, 18, 18,
17, 17, 18, 19, 18, 18, 17, 17,
18, 18, 18, 18, 19, 17, 17, 18,
20, 19, 19, 18, 19, 18, 19, 19,
19, 19, 17, 5, 7, 9, 10, 10,
11, 11, 12, 12, 12, 13, 13, 13,
13, 13, 14, 14, 14, 14, 14, 15,
14, 15, 15, 15, 15, 15, 16, 16,
16, 16, 16, 16, 16, 16, 16, 16,
16, 16, 15, 16, 16, 17, 17, 17,
16, 17, 17, 17, 17, 17, 17, 17,
17, 17, 17, 17, 17, 17, 17, 16,
16, 19, 18, 18, 19, 17, 19, 20,
17, 18, 18, 18, 18, 18, 18, 6,
8, 10, 11, 12, 12, 12, 13, 13,
13, 14, 14, 14, 14, 15, 15, 15,
15, 15, 15, 16, 16, 16, 16, 16,
16, 17, 17, 17, 16, 16, 17, 17,
17, 17, 17, 17, 17, 16, 16, 16,
17, 18, 18, 18, 17, 19, 19, 18,
18, 17, 18, 19, 18, 17, 18, 18,
19, 18, 17, 17, 6, 9, 11, 12,
13, 13, 13, 14, 14, 14, 15, 15,
15, 15, 15, 16, 16, 16, 16, 16,
16, 17, 16, 17, 17, 17, 17, 17,
17, 17, 18, 17, 18, 17, 17, 18,
18, 19, 19, 17, 17, 7, 10, 12,
13, 13, 14, 14, 14, 14, 15, 16,
16, 16, 16, 16, 16, 16, 16, 16,
16, 17, 17, 17, 17, 18, 17, 18,
18, 18, 18, 18, 18, 18, 18, 17,
17, 18, 18, 18, 18, 18, 18, 7,
10, 12, 13, 14, 15, 15, 15, 15,
16, 16, 17, 17, 17, 17, 17, 17,
17, 17, 17, 17, 18, 17, 17, 8,
11, 13, 14, 15, 15, 15, 15, 16,
16, 18, 17, 17, 18, 17, 17, 18,
17, 17, 18, 18, 19, 18, 18, 19,
19, 19, 18, 18, 18, 8, 11, 13,
14, 15, 16, 16, 16, 16, 17, 17,
17, 18, 17, 18, 19, 18, 18, 18,
18, 18, 18, 8, 12, 14, 15, 15,
16, 16, 16, 17, 17, 18, 18, 18,
18, 18, 18, 18, 18, 17, 9, 12,
14, 15, 16, 16, 17, 17, 17, 17,
18, 9, 12, 14, 15, 16, 17, 17,
17, 18, 9, 13, 15, 16, 17, 17,
18, 17, 18, 17, 9, 13, 15, 16,
17, 18, 18, 18, 10, 13, 15, 16,
18, 10, 14, 16, 17, 18, 10, 14,
16, 17, 10, 14, 16, 18, 18, 10,
14, 16, 18, 18, 11, 15, 16, 11,
15, 17, 11, 15, 17, 11, 15, 17,
11, 15, 17, 11, 15, 17, 12, 16,
17, 12, 15, 12, 16, 12, 16, 18,
12, 16, 12, 16, 12, 16, 12, 16,
17, 12, 16, 18, 12, 17, 13, 16,
13, 16, 13, 16, 18, 13, 16, 13,
17, 13, 17, 13, 17, 13, 17, 13,
17, 13, 17, 13, 17, 13, 17, 13,
16, 13, 17, 13, 17, 13, 17, 14,
17, 14, 17, 14, 17, 14, 14, 14,
17, 14, 17, 14, 14, 18, 14, 14,
18, 14, 18, 14, 18, 14, 17, 14,
17, 14, 17, 14, 14, 18, 14, 15,
15, 15, 14, 15, 15, 14, 15, 15,
15, 18, 15, 18, 15, 15, 17, 15,
15, 15, 15, 15, 15, 15, 15, 15,
15, 15, 16, 15, 15, 15, 15, 16,
16, 16, 16, 16, 15, 15, 15, 15,
16, 16, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 16, 17, 16, 16,
16, 17, 16, 16, 16, 17, 17, 17,
17, 17, 16, 17, 17, 17, 17, 16,
16, 16, 17, 17, 17, 17, 16, 17,
17, 17, 17, 17, 17, 17, 17, 17,
17, 17, 17, 17, 17, 17, 18, 17,
};

const uint32_t coef4_huffcodes[476] = {
0x00f01, 0x0001e, 0x00000, 0x00004, 0x00006, 0x0000d, 0x0000a, 0x00017,
0x0001d, 0x00017, 0x0002c, 0x00031, 0x00039, 0x0003e, 0x00039, 0x0005a,
0x00066, 0x00070, 0x0007b, 0x00070, 0x00077, 0x000af, 0x000c9, 0x000f2,
0x000f4, 0x000b2, 0x000e3, 0x0015b, 0x0015d, 0x00181, 0x0019d, 0x001e3,
0x001c5, 0x002b5, 0x002db, 0x00338, 0x003c3, 0x003cc, 0x003f0, 0x002cd,
0x003fa, 0x003a1, 0x005b4, 0x00657, 0x007ab, 0x0074d, 0x0074c, 0x00ac1,
0x00ac5, 0x0076b, 0x00ca8, 0x00f04, 0x00f00, 0x00fe3, 0x00f3c, 0x00f10,
0x00f39, 0x00fe6, 0x00e26, 0x00e90, 0x016c5, 0x01827, 0x01954, 0x015c5,
0x01958, 0x01f8a, 0x01c4a, 0x02b0f, 0x02b41, 0x02b0e, 0x033c6, 0x03050,
0x01c4f, 0x02d88, 0x0305c, 0x03c18, 0x02b4f, 0x02cc2, 0x03a47, 0x05680,
0x0569d, 0x06442, 0x06443, 0x06446, 0x0656e, 0x06444, 0x07120, 0x0748a,
0x0c1ba, 0x07e22, 0x07aa6, 0x07f25, 0x07aa7, 0x07e20, 0x0c11b, 0x0c118,
0x07aa5, 0x0ad0a, 0x0f389, 0x19ebb, 0x0caad, 0x0fe42, 0x0fe40, 0x16c34,
0x2b4e5, 0x33d65, 0x16c30, 0x1e7ae, 0x1e25c, 0x18370, 0x1e703, 0x19eba,
0x16c37, 0x0e234, 0x16c6e, 0x00004, 0x0002a, 0x00061, 0x00075, 0x000cb,
0x000ff, 0x00190, 0x001eb, 0x001d1, 0x002b9, 0x00307, 0x00339, 0x0033f,
0x003fb, 0x003b4, 0x0060c, 0x00679, 0x00645, 0x0067d, 0x0078a, 0x007e3,
0x00749, 0x00ac4, 0x00ad2, 0x00ae3, 0x00c10, 0x00c16, 0x00ad1, 0x00cf4,
0x00fe2, 0x01586, 0x00e9d, 0x019f1, 0x01664, 0x01e26, 0x01d38, 0x02b4d,
0x033c5, 0x01fc2, 0x01fc3, 0x01d28, 0x03c1d, 0x0598e, 0x0f094, 0x07aa4,
0x0ad38, 0x0ac0c, 0x0c11a, 0x079ea, 0x0c881, 0x0fe44, 0x0b635, 0x0ac0d,
0x0b61e, 0x05987, 0x07121, 0x0f382, 0x0f387, 0x0e237, 0x0fe47, 0x0f383,
0x0f091, 0x0f385, 0x0e233, 0x182ee, 0x19eb8, 0x1663e, 0x0f093, 0x00014,
0x00058, 0x00159, 0x00167, 0x00300, 0x003d4, 0x005b5, 0x0079d, 0x0076a,
0x00b67, 0x00b60, 0x00f05, 0x00cf0, 0x00f17, 0x00e95, 0x01822, 0x01913,
0x016c2, 0x0182f, 0x01959, 0x01fcb, 0x01e27, 0x01c40, 0x033c7, 0x01e7b,
0x01c49, 0x02d89, 0x01e23, 0x01660, 0x03f12, 0x02cc6, 0x033e1, 0x05b34,
0x0609a, 0x06569, 0x07488, 0x07e21, 0x0cf5f, 0x0712c, 0x0389d, 0x067cf,
0x07f28, 0x1663f, 0x33d67, 0x1663d, 0x1e25d, 0x3c1ab, 0x15c44, 0x16c36,
0x0001f, 0x000ec, 0x00323, 0x005b2, 0x0079f, 0x00ac2, 0x00f16, 0x00e9e,
0x01956, 0x01e0f, 0x019ea, 0x01666, 0x02b89, 0x02b02, 0x02d8c, 0x03c1b,
0x03c19, 0x032b5, 0x03f9c, 0x02ccf, 0x03897, 0x05b35, 0x0ad02, 0x07f29,
0x06441, 0x03884, 0x07888, 0x0784e, 0x06568, 0x0c1bb, 0x05986, 0x067cc,
0x0fe49, 0x0fe48, 0x0c1bc, 0x0fe41, 0x18371, 0x1663c, 0x0e231, 0x0711e,
0x0ad09, 0x0f092, 0x0002d, 0x001db, 0x00781, 0x00c1a, 0x00f55, 0x01580,
0x01ea8, 0x02d9b, 0x032af, 0x03f16, 0x03c1c, 0x07834, 0x03c45, 0x0389c,
0x067ce, 0x06445, 0x0c1b9, 0x07889, 0x07f3a, 0x0784f, 0x07f2b, 0x0ad0b,
0x0f090, 0x0c11d, 0x0e94e, 0x0711f, 0x0e9f1, 0x0f38e, 0x079e9, 0x0ad03,
0x0f09b, 0x0caae, 0x0fe46, 0x2b4e6, 0x0e9f0, 0x19eb6, 0x67ac1, 0x67ac0,
0x33d66, 0x0f388, 0x00071, 0x003a0, 0x00ca9, 0x01829, 0x01d39, 0x02b43,
0x02cc4, 0x06554, 0x0f09a, 0x0b61f, 0x067cd, 0x0711c, 0x0b636, 0x07f2a,
0x0b634, 0x0c11f, 0x0cf5e, 0x0b61d, 0x0f06b, 0x0caab, 0x0c1be, 0x0e94c,
0x0f099, 0x182ed, 0x0e94f, 0x0c119, 0x0e232, 0x2b4e4, 0x0f38a, 0x19eb4,
0x1e25f, 0x0e94d, 0x000b7, 0x00785, 0x016cc, 0x03051, 0x033c4, 0x0656f,
0x03891, 0x0711d, 0x0caaf, 0x0f097, 0x07489, 0x0f098, 0x0c880, 0x0caaa,
0x0f386, 0x19eb7, 0x16c6f, 0x0f384, 0x182e8, 0x182e9, 0x0e230, 0x1e700,
0x33d62, 0x33d63, 0x33d64, 0x16c33, 0x0e216, 0x000fd, 0x00c15, 0x01665,
0x03c4a, 0x07f3b, 0x07896, 0x0c11c, 0x0e215, 0x16c32, 0x0f38b, 0x0f38d,
0x182ea, 0x1e701, 0x712df, 0x15c46, 0x00194, 0x00fe0, 0x03f13, 0x0748b,
0x0f096, 0x0cf80, 0x1e25e, 0xe25bd, 0x33d61, 0x16c31, 0x001f9, 0x01912,
0x05710, 0x0f3d0, 0x0c1bf, 0x00301, 0x01e24, 0x0ad08, 0x003cd, 0x01c41,
0x0c1bd, 0x00563, 0x03a52, 0x0f3d1, 0x00570, 0x02cce, 0x0e217, 0x0067b,
0x0655d, 0x0074b, 0x06447, 0x00c12, 0x074fb, 0x00f08, 0x0b61c, 0x00e22,
0x0fe43, 0x016c7, 0x01836, 0x019f2, 0x01c43, 0x01d3f, 0x01fcf, 0x02b4c,
0x0304c, 0x032b6, 0x03a46, 0x05607, 0x03f17, 0x02cc5, 0x0609b, 0x0655c,
0x07e23, 0x067c1, 0x07f26, 0x07f27, 0x0f095, 0x0e9f3, 0x0cf81, 0x0c11e,
0x0caac, 0x0f38f, 0x0e9f2, 0x074fa, 0x0e236, 0x0fe45, 0x1c428, 0x0e235,
0x182ef, 0x19eb5, 0x0f3d6, 0x182ec, 0x16c35, 0x0f38c, 0x2b4e7, 0x15c47,
0xe25bc, 0x1e702, 0x1c4b6, 0x0e25a, 0x3c1aa, 0x15c45, 0x1c429, 0x19eb9,
0x1e7af, 0x182eb, 0x1e0d4, 0x3896e,
};

const uint8_t coef4_huffbits[476] = {
12, 6, 2, 3, 4, 4, 5, 5,
5, 6, 6, 6, 6, 6, 7, 7,
7, 7, 7, 8, 8, 8, 8, 8,
8, 9, 9, 9, 9, 9, 9, 9,
10, 10, 10, 10, 10, 10, 10, 11,
10, 11, 11, 11, 11, 12, 12, 12,
12, 12, 12, 12, 12, 12, 12, 12,
12, 12, 13, 13, 13, 13, 13, 13,
13, 13, 14, 14, 14, 14, 14, 14,
14, 14, 14, 14, 14, 15, 15, 15,
15, 15, 15, 15, 15, 15, 16, 16,
16, 15, 15, 15, 15, 15, 16, 16,
15, 16, 16, 17, 16, 16, 16, 17,
18, 18, 17, 17, 17, 17, 17, 17,
17, 17, 17, 4, 6, 7, 8, 8,
8, 9, 9, 10, 10, 10, 10, 10,
10, 11, 11, 11, 11, 11, 11, 11,
12, 12, 12, 12, 12, 12, 12, 12,
12, 13, 13, 13, 14, 13, 14, 14,
14, 13, 13, 14, 14, 16, 16, 15,
16, 16, 16, 15, 16, 16, 16, 16,
16, 16, 16, 16, 16, 17, 16, 16,
16, 16, 17, 17, 17, 18, 16, 5,
8, 9, 10, 10, 10, 11, 11, 12,
12, 12, 12, 12, 12, 13, 13, 13,
13, 13, 13, 13, 13, 14, 14, 13,
14, 14, 13, 14, 14, 15, 14, 15,
15, 15, 16, 15, 16, 16, 15, 15,
15, 18, 18, 18, 17, 18, 17, 17,
6, 9, 10, 11, 11, 12, 12, 13,
13, 13, 13, 14, 14, 14, 14, 14,
14, 14, 14, 15, 15, 15, 16, 15,
15, 15, 15, 15, 15, 16, 16, 15,
16, 16, 16, 16, 17, 18, 17, 16,
16, 16, 7, 10, 11, 12, 12, 13,
13, 14, 14, 14, 14, 15, 14, 15,
15, 15, 16, 15, 15, 15, 15, 16,
16, 16, 17, 16, 17, 16, 15, 16,
16, 16, 16, 18, 17, 17, 19, 19,
18, 16, 7, 11, 12, 13, 14, 14,
15, 15, 16, 16, 15, 16, 16, 15,
16, 16, 16, 16, 16, 16, 16, 17,
16, 17, 17, 16, 17, 18, 16, 17,
17, 17, 8, 11, 13, 14, 14, 15,
15, 16, 16, 16, 16, 16, 16, 16,
16, 17, 17, 16, 17, 17, 17, 17,
18, 18, 18, 17, 17, 8, 12, 14,
14, 15, 15, 16, 17, 17, 16, 16,
17, 17, 20, 17, 9, 12, 14, 16,
16, 16, 17, 21, 18, 17, 9, 13,
15, 16, 16, 10, 13, 16, 10, 14,
16, 11, 15, 16, 11, 15, 17, 11,
15, 12, 15, 12, 16, 12, 16, 13,
16, 13, 13, 13, 14, 14, 13, 14,
14, 14, 15, 15, 14, 15, 15, 15,
15, 15, 15, 15, 16, 17, 16, 16,
16, 16, 17, 16, 17, 16, 18, 17,
17, 17, 16, 17, 17, 16, 18, 17,
21, 17, 18, 17, 18, 17, 18, 17,
17, 17, 17, 19,
};

const uint32_t coef5_huffcodes[435] = {
0x00347, 0x0000b, 0x00001, 0x00001, 0x0000c, 0x00004, 0x00010, 0x00015,
0x0001f, 0x0000b, 0x00023, 0x00026, 0x00029, 0x00035, 0x00037, 0x00001,
0x00015, 0x0001a, 0x0001d, 0x0001c, 0x0001e, 0x0004e, 0x00049, 0x00051,
0x00078, 0x00004, 0x00000, 0x00008, 0x0000d, 0x0007b, 0x00005, 0x00032,
0x00095, 0x00091, 0x00096, 0x000a1, 0x000d9, 0x00003, 0x00019, 0x00061,
0x00066, 0x00060, 0x00017, 0x0000e, 0x00063, 0x001a0, 0x001b7, 0x001e6,
0x001e7, 0x001b6, 0x00018, 0x001e8, 0x00038, 0x00031, 0x00005, 0x0003d,
0x00027, 0x001ea, 0x0001a, 0x000c5, 0x000f9, 0x000ff, 0x000db, 0x00250,
0x000fc, 0x0025c, 0x00008, 0x00075, 0x003d7, 0x003d3, 0x001b0, 0x0007c,
0x003ca, 0x00036, 0x00189, 0x004a6, 0x004a2, 0x004fb, 0x000c0, 0x0007f,
0x0009a, 0x00311, 0x0006e, 0x0009b, 0x0068c, 0x006c0, 0x00484, 0x00012,
0x000c3, 0x0094f, 0x00979, 0x009f9, 0x00d09, 0x00da6, 0x00da8, 0x00901,
0x000c1, 0x00373, 0x00d08, 0x009fa, 0x00d8b, 0x00d85, 0x00d86, 0x000df,
0x006e2, 0x000ce, 0x00f24, 0x009fe, 0x001f7, 0x007c1, 0x000cf, 0x009fc,
0x009ff, 0x00d89, 0x00da9, 0x009fd, 0x001f8, 0x01a36, 0x0128c, 0x0129d,
0x01a37, 0x00196, 0x003ea, 0x00f8b, 0x00d93, 0x01e45, 0x01e58, 0x01e4b,
0x01e59, 0x013f1, 0x00309, 0x00265, 0x00308, 0x0243a, 0x027e1, 0x00f89,
0x00324, 0x03cbc, 0x03c86, 0x03695, 0x0243c, 0x0243b, 0x0243e, 0x01e4a,
0x003a5, 0x03468, 0x03428, 0x03c84, 0x027e0, 0x025e2, 0x01880, 0x00197,
0x00325, 0x03cb7, 0x0791e, 0x007ec, 0x06c75, 0x004c8, 0x04bc7, 0x004c6,
0x00983, 0x0481e, 0x01b53, 0x0251b, 0x01b58, 0x00984, 0x04fa8, 0x03cbb,
0x00f8a, 0x00322, 0x0346a, 0x0243d, 0x00326, 0x03469, 0x0481f, 0x0481d,
0x00746, 0x09032, 0x01b50, 0x01d13, 0x0d8e4, 0x0481b, 0x06c74, 0x0796b,
0x07969, 0x00985, 0x0d8e3, 0x00986, 0x00fa2, 0x01301, 0x06c7c, 0x00987,
0x03cb8, 0x0f4af, 0x00e88, 0x1b1c0, 0x00fce, 0x033eb, 0x03f6a, 0x03f69,
0x00fcf, 0x0791f, 0x004c9, 0x04871, 0x00fcd, 0x00982, 0x00fcc, 0x00fa3,
0x01d12, 0x0796c, 0x01b47, 0x00321, 0x0796a, 0x0d8e2, 0x04872, 0x04873,
0x0000e, 0x00014, 0x0000a, 0x000a0, 0x00012, 0x0007d, 0x001a2, 0x0003b,
0x0025f, 0x000dd, 0x0027c, 0x00343, 0x00368, 0x0036b, 0x0003e, 0x001fa,
0x00485, 0x001b3, 0x0007f, 0x001b1, 0x0019e, 0x004ba, 0x007ad, 0x00339,
0x00066, 0x007a4, 0x00793, 0x006c6, 0x0007e, 0x000f1, 0x00372, 0x009fb,
0x00d83, 0x00d8a, 0x00947, 0x009f4, 0x001d0, 0x01b09, 0x01b4b, 0x007ec,
0x003e1, 0x000ca, 0x003ec, 0x02539, 0x04fa9, 0x01b57, 0x03429, 0x03d2a,
0x00d97, 0x003a7, 0x00dc0, 0x00d96, 0x00dc1, 0x007eb, 0x03cba, 0x00c43,
0x00c41, 0x01b52, 0x007ef, 0x00323, 0x03cb9, 0x03c83, 0x007d0, 0x007ed,
0x06c7f, 0x09033, 0x03f6c, 0x36383, 0x1e95d, 0x06c78, 0x00747, 0x01b51,
0x00022, 0x00016, 0x00039, 0x00252, 0x00079, 0x00486, 0x00338, 0x00369,
0x00d88, 0x00026, 0x00d87, 0x00f4b, 0x00d82, 0x00027, 0x001e1, 0x01a15,
0x007c7, 0x012f0, 0x001e0, 0x006d0, 0x01a16, 0x01e44, 0x01e5f, 0x03690,
0x00d90, 0x00c42, 0x00daf, 0x00d92, 0x00f80, 0x00cfb, 0x0342f, 0x0487f,
0x01b46, 0x07968, 0x00d95, 0x00d91, 0x01b55, 0x03f68, 0x04bc6, 0x03cbd,
0x00f81, 0x00320, 0x00069, 0x000fe, 0x006d5, 0x0033f, 0x000de, 0x007c6,
0x01e40, 0x00d94, 0x00f88, 0x03c8e, 0x03694, 0x00dae, 0x00dad, 0x00267,
0x003a6, 0x00327, 0x0487e, 0x007ee, 0x00749, 0x004c7, 0x03692, 0x01b56,
0x00fd1, 0x07a56, 0x06c77, 0x09031, 0x00748, 0x06c7a, 0x0796d, 0x033ea,
0x06c76, 0x00fd0, 0x36382, 0x1e417, 0x00745, 0x04faf, 0x0d8e1, 0x03f6b,
0x1e95c, 0x04fad, 0x0009e, 0x004bd, 0x0067c, 0x01b08, 0x003eb, 0x01b45,
0x03691, 0x0d8e5, 0x07904, 0x00981, 0x007ea, 0x019f4, 0x06c7d, 0x04fab,
0x04fac, 0x06c7e, 0x01300, 0x06c7b, 0x0006f, 0x003f7, 0x03c85, 0x004c4,
0x0001e, 0x006e1, 0x03693, 0x01b44, 0x00241, 0x01e46, 0x0019d, 0x00266,
0x004bb, 0x02538, 0x007ac, 0x01b54, 0x00902, 0x04870, 0x00da7, 0x00900,
0x00185, 0x06c79, 0x006e3, 0x003e9, 0x01e94, 0x003ed, 0x003f2, 0x0342e,
0x0346b, 0x0251a, 0x004c5, 0x01881, 0x0481c, 0x01b59, 0x03c87, 0x04fae,
0x007e9, 0x03f6d, 0x0f20a, 0x09030, 0x04faa, 0x0d8e6, 0x03f6f, 0x0481a,
0x03f6e, 0x1e416, 0x0d8e7,
};

const uint8_t coef5_huffbits[435] = {
10, 4, 2, 4, 4, 5, 5, 5,
5, 6, 6, 6, 6, 6, 6, 7,
7, 7, 7, 7, 7, 7, 7, 7,
7, 8, 8, 8, 8, 7, 8, 8,
8, 8, 8, 8, 8, 9, 9, 9,
9, 9, 9, 9, 9, 9, 9, 9,
9, 9, 10, 9, 10, 10, 10, 10,
10, 9, 10, 10, 10, 10, 10, 10,
10, 10, 11, 11, 10, 10, 11, 11,
10, 11, 11, 11, 11, 11, 12, 12,
12, 12, 12, 12, 11, 11, 11, 12,
12, 12, 12, 12, 12, 12, 12, 12,
12, 12, 12, 12, 12, 12, 12, 13,
13, 13, 12, 12, 13, 13, 13, 12,
12, 12, 12, 12, 13, 13, 13, 13,
13, 14, 14, 14, 14, 13, 13, 13,
13, 13, 14, 14, 14, 14, 14, 14,
15, 14, 14, 14, 14, 14, 14, 13,
14, 14, 14, 14, 14, 14, 15, 14,
15, 14, 15, 15, 15, 15, 15, 15,
16, 15, 15, 14, 15, 16, 15, 14,
14, 15, 14, 14, 15, 14, 15, 15,
15, 16, 15, 17, 16, 15, 15, 15,
15, 16, 16, 16, 16, 17, 15, 16,
14, 16, 16, 17, 16, 16, 16, 16,
16, 15, 15, 15, 16, 16, 16, 16,
17, 15, 15, 15, 15, 16, 15, 15,
4, 7, 8, 8, 9, 9, 9, 10,
10, 10, 10, 10, 10, 10, 11, 11,
11, 11, 11, 11, 11, 11, 11, 12,
12, 11, 11, 11, 12, 12, 12, 12,
12, 12, 12, 12, 13, 13, 13, 13,
12, 13, 14, 14, 15, 15, 14, 14,
14, 14, 14, 14, 14, 15, 14, 14,
14, 15, 15, 15, 14, 14, 15, 15,
15, 16, 16, 18, 17, 15, 15, 15,
6, 9, 10, 10, 11, 11, 12, 12,
12, 13, 12, 12, 12, 13, 13, 13,
13, 13, 13, 13, 13, 13, 13, 14,
14, 14, 14, 14, 14, 14, 14, 15,
15, 15, 14, 14, 15, 16, 15, 14,
14, 15, 7, 10, 11, 12, 13, 13,
13, 14, 14, 14, 14, 14, 14, 14,
14, 15, 15, 15, 15, 15, 14, 15,
16, 15, 15, 16, 15, 15, 15, 16,
15, 16, 18, 17, 15, 15, 16, 16,
17, 15, 8, 11, 13, 13, 14, 15,
14, 16, 15, 16, 15, 15, 15, 15,
15, 15, 17, 15, 9, 12, 14, 15,
10, 13, 14, 15, 10, 13, 11, 14,
11, 14, 11, 15, 12, 15, 12, 12,
13, 15, 13, 14, 13, 14, 14, 14,
14, 14, 15, 15, 15, 15, 14, 15,
15, 16, 16, 16, 15, 16, 16, 15,
16, 17, 16,
};

const uint16_t levels0[60] = {
317, 92, 62, 60, 19, 17, 10, 7,
6, 5, 5, 3, 3, 3, 2, 2,
2, 2, 2, 2, 2, 1, 2, 2,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1,
};

const uint16_t levels1[40] = {
311, 91, 61, 28, 10, 6, 5, 2,
2, 2, 2, 2, 2, 2, 2, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
};

const uint16_t levels2[340] = {
181,110, 78, 63, 61, 62, 60, 61,
33, 41, 41, 19, 17, 19, 12, 11,
9, 11, 10, 6, 8, 7, 6, 4,
5, 5, 4, 4, 3, 4, 3, 5,
3, 4, 3, 3, 3, 3, 3, 3,
2, 2, 4, 2, 3, 2, 3, 3,
2, 2, 2, 2, 2, 2, 2, 2,
3, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 1, 2, 1, 2, 2,
2, 2, 1, 2, 1, 1, 1, 2,
2, 1, 2, 1, 2, 2, 2, 2,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1,
};

const uint16_t levels3[180] = {
351,122, 76, 61, 41, 42, 24, 30,
22, 19, 11, 9, 10, 8, 5, 5,
4, 5, 5, 3, 3, 3, 3, 3,
3, 3, 2, 2, 3, 2, 2, 2,
3, 3, 2, 2, 2, 3, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 1, 1,
2, 2, 1, 2, 1, 2, 2, 2,
2, 2, 2, 1, 2, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 2,
2, 1, 2, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1,
};

const uint16_t levels4[70] = {
113, 68, 49, 42, 40, 32, 27, 15,
10, 5, 3, 3, 3, 3, 2, 2,
2, 2, 2, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1,
};

const uint16_t levels5[40] = {
214, 72, 42, 40, 18, 4, 4, 2,
2, 2, 2, 2, 1, 1, 2, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
};

/*typedef struct CoefVLCTable
{
int n; // total number of codes
const uint32_t *huffcodes; // VLC bit values
const uint8_t *huffbits; // VLC bit size
const uint16_t *levels; // table to build run/level tables
} CoefVLCTable;*/

const CoefVLCTable coef_vlcs[6] = {
{
sizeof(coef0_huffbits), coef0_huffcodes, coef0_huffbits, levels0,
},
{
sizeof(coef1_huffbits), coef1_huffcodes, coef1_huffbits, levels1,
},
{
sizeof(coef2_huffbits), coef2_huffcodes, coef2_huffbits, levels2,
},
{
sizeof(coef3_huffbits), coef3_huffcodes, coef3_huffbits, levels3,
},
{
sizeof(coef4_huffbits), coef4_huffcodes, coef4_huffbits, levels4,
},
{
sizeof(coef5_huffbits), coef5_huffcodes, coef5_huffbits, levels5,
},
};


const fixed64 pow_table[] =
{
0x10000LL,0x11f3dLL,0x14249LL,0x1699cLL,0x195bcLL,0x1c73dLL,0x1fec9LL,0x23d1dLL,0x2830bLL,0x2d182LL,
0x3298bLL,0x38c53LL,0x3fb28LL,0x47783LL,0x5030aLL,0x59f98LL,0x64f40LL,0x71457LL,0x7f17bLL,0x8e99aLL,
0xa0000LL,0xb385eLL,0xc96d9LL,0xe2019LL,0xfd954LL,0x11c865LL,0x13f3dfLL,0x166320LL,0x191e6eLL,0x1c2f10LL,
0x1f9f6eLL,0x237b39LL,0x27cf8bLL,0x2cab1aLL,0x321e65LL,0x383bf0LL,0x3f1882LL,0x46cb6aLL,0x4f6eceLL,0x592006LL,
0x640000LL,0x7033acLL,0x7de47eLL,0x8d40f6LL,0x9e7d44LL,0xb1d3f4LL,0xc786b7LL,0xdfdf43LL,0xfb304bLL,0x119d69aLL,
0x13c3a4eLL,0x162d03aLL,0x18e1b70LL,0x1beaf00LL,0x1f52feeLL,0x2325760LL,0x276f514LL,0x2c3f220LL,0x31a5408LL,
0x37b403cLL,0x3e80000LL,0x46204b8LL,0x4eaece8LL,0x58489a0LL,0x630e4a8LL,0x6f24788LL,0x7cb4328LL,0x8beb8a0LL,
0x9cfe2f0LL,0xb026200LL,0xc5a4710LL,0xddc2240LL,0xf8d1260LL,0x1172d600LL,0x1393df60LL,0x15f769c0LL,0x18a592c0LL,
0x1ba77540LL,0x1f074840LL,0x22d08280LL,0x27100000LL,0x2bd42f40LL,0x312d4100LL,0x372d6000LL,0x3de8ee80LL,
0x4576cb80LL,0x4df09f80LL,0x57733600LL,0x621edd80LL,0x6e17d480LL,0x7b86c700LL,0x8a995700LL,0x9b82b800LL,
0xae7c5c00LL,0xc3c6b900LL,0xdbaa2200LL,0xf677bc00LL,0x1148a9400LL,0x13648d200LL,0x15c251800LL,0x186a00000LL,
0x1b649d800LL,0x1ebc48a00LL,0x227c5c000LL,0x26b195000LL,0x2b6a3f000LL,0x30b663c00LL,0x36a801c00LL,0x3d534a400LL,
0x44cee4800LL,0x4d343c800LL,0x569fd6000LL,0x6131b2800LL,0x6d0db9800LL,0x7a5c33800LL,0x894a55000LL,0x9a0ad6000LL,
0xacd69d000LL,0xc1ed84000LL,0xd9972f000LL,0xf42400000LL,0x111ee28000LL,0x1335ad6000LL,0x158db98000LL,0x182efd4000LL,
0x1b22676000LL,0x1e71fe6000LL,0x2229014000LL,0x26540e8000LL,0x2b014f0000LL,0x3040a5c000LL,0x3623e60000LL,0x3cbf0fc000LL,
0x4428940000LL,0x4c79a08000LL,0x55ce758000LL,0x6046c58000LL,0x6c06220000LL,0x7934728000LL,0x87fe7d0000LL,0x9896800000LL,
0xab34d90000LL,0xc018c60000LL,0xd7893f0000LL,0xf1d5e40000LL,0x10f580a0000LL,0x13073f00000LL,0x1559a0c0000LL,0x17f48900000LL,
0x1ae0d160000LL,0x1e286780000LL,0x21d66fc0000LL,0x25f769c0000LL,0x2a995c80000LL,0x2fcc0440000LL,0x35a10940000LL,
0x3c2c3b80000LL,0x4383d500000LL,0x4bc0c780000LL,0x54ff0e80000LL,0x5f5e1000000LL,0x6b010780000LL,0x780f7c00000LL,
0x86b5c800000LL,0x9725ae00000LL,0xa9970600000LL,0xbe487500000LL,0xd5804700000LL,0xef8d5a00000LL,0x10cc82e00000LL,
0x12d940c00000LL,0x152605c00000LL,0x17baa2200000LL,0x1a9fd9c00000LL,0x1ddf82a00000LL,0x2184a5c00000LL,0x259ba5400000LL,
0x2a3265400000LL,0x2f587cc00000LL,0x351f69000000LL,0x3b9aca000000LL,0x42e0a4800000LL,0x4b09ad800000LL,
0x54319d000000LL,0x5e778d000000LL,0x69fe64000000LL,0x76ed49800000LL,0x85702c000000LL,0x95b858000000LL,
0xa7fd1c000000LL,0xbc7c87000000LL,0xd37c3a000000LL,0xed4a55000000LL,0x10a3e82000000LL,0x12abb1a000000LL,
0x14f2e7a000000LL,0x1781474000000LL,0x1a5f7f4000000LL,0x1d974de000000LL,0x2133a18000000LL
};

const fixed32 pow_10_to_yover16[]=
{
0x10000,0x127a0,0x15562,0x18a39,0x1c73d,0x20db4,0x25f12,0x2bd09,0x3298b,0x3a6d9,0x4378b,0x4dea3,
0x59f98,0x67e6b,0x77fbb,0x8a8de,0xa0000,0xb8c3e,0xd55d1,0xf6636,0x11c865,0x148906,0x17b6b8,0x1b625b,
0x1f9f6e,0x248475,0x2a2b6e,0x30b25f,0x383bf0,0x40f02c,0x4afd4b,0x5698b0,0x640000,0x737a6b,0x855a26,
0x99fe1f,0xb1d3f4,0xcd5a3e,0xed232b,0x111d78a,0x13c3a4e,0x16d2c94,0x1a5b24e,0x1e6f7b0,0x2325760,
0x28961b4,0x2ede4ec,0x361f6dc,0x3e80000,0x482c830,0x5358580,0x603ed30,0x6f24788,0x8058670,0x9435fb0,
0xab26b70,0xc5a4710,0xe43bdc0,0x1078f700,0x1305ace0,0x15f769c0,0x195dd100,0x1d4af120
};

/*const fixed32 pow_a_table[] =
{ //
0x1004,0x1008,0x100c,0x1010,0x1014,0x1018,0x101c,0x1021,0x1025,0x1029,0x102d,0x1031,0x1036,0x103a,
0x103e,0x1043,0x1047,0x104b,0x1050,0x1054,0x1059,0x105d,0x1062,0x1066,0x106b,0x106f,0x1074,0x1078,
0x107d,0x1082,0x1086,0x108b,0x1090,0x1095,0x1099,0x109e,0x10a3,0x10a8,0x10ad,0x10b2,0x10b7,0x10bc,
0x10c1,0x10c6,0x10cb,0x10d0,0x10d5,0x10da,0x10df,0x10e5,0x10ea,0x10ef,0x10f5,0x10fa,0x10ff,0x1105,
0x110a,0x1110,0x1115,0x111b,0x1120,0x1126,0x112c,0x1131,0x1137,0x113d,0x1143,0x1149,0x114f,0x1155,
0x115a,0x1161,0x1167,0x116d,0x1173,0x1179,0x117f,0x1186,0x118c,0x1192,0x1199,0x119f,0x11a6,0x11ac,
0x11b3,0x11b9,0x11c0,0x11c7,0x11ce,0x11d4,0x11db,0x11e2,0x11e9,0x11f0,0x11f8,0x11ff,0x1206,0x120d,
0x1215,0x121c,0x1223,0x122b,0x1233,0x123a,0x1242,0x124a,0x1251,0x1259,0x1261,0x1269,0x1271,0x127a,
0x1282,0x128a,0x1293,0x129b,0x12a4,0x12ac,0x12b5,0x12be,0x12c7,0x12d0,0x12d9,0x12e2,0x12eb,0x12f4,
0x12fe,0x1307
};*/
const fixed32 pow_a_table[] =
{
65600, 65665, 65729, 65795, 65860, 65926, 65992, 66058, 66125, 66192, 66260, 66327, 66395, 66464, 66533, 66602,
66672, 66741, 66812, 66882, 66953, 67025, 67097, 67169, 67241, 67314, 67388, 67462, 67536, 67610, 67685, 67761,
67837, 67913, 67990, 68067, 68144, 68222, 68301, 68380, 68459, 68539, 68619, 68700, 68781, 68863, 68945, 69028,
69111, 69195, 69279, 69364, 69449, 69535, 69621, 69708, 69795, 69883, 69972, 70061, 70151, 70241, 70332, 70423,
70515, 70608, 70701, 70795, 70889, 70984, 71080, 71176, 71273, 71371, 71469, 71568, 71668, 71769, 71870, 71972,
72074, 72178, 72282, 72387, 72492, 72599, 72706, 72814, 72922, 73032, 73142, 73254, 73366, 73479, 73592, 73707,
73823, 73939, 74057, 74175, 74295, 74415, 74536, 74658, 74782, 74906, 75031, 75158, 75285, 75414, 75544, 75674,
75806, 75940, 76074, 76209, 76346, 76484, 76623, 76764, 76905, 77048, 77193, 77339, 77486, 77634, 77784, 77936
};

/*const fixed64 lsp_pow_e_table[] =
{
0xf333f9deLL, 0xf0518db9LL, 0x0LL, 0x7e656b4fLL, 0x7999fcefLL, 0xf828c6dcLL, 0x0LL,
0x3f32b5a7LL, 0x3cccfe78LL, 0xfc14636eLL, 0x0LL, 0x9f995ad4LL, 0x9e667f3cLL, 0xfe0a31b7LL,
0x0LL, 0x4fccad6aLL, 0x4f333f9eLL, 0x7f0518dcLL, 0x0LL, 0x27e656b5LL, 0x27999fcfLL,
0xbf828c6eLL, 0x0LL, 0x13f32b5aLL, 0x13cccfe7LL, 0xdfc14637LL, 0x0LL, 0x89f995adLL,
0x9e667f4LL, 0x6fe0a31bLL, 0x0LL, 0x44fccad7LL, 0x4f333faLL, 0x37f0518eLL, 0x0LL,
0xa27e656bLL, 0x827999fdLL, 0x1bf828c7LL, 0x0LL, 0xd13f32b6LL, 0x413cccfeLL, 0xdfc1463LL,
0x0LL, 0xe89f995bLL, 0xa09e667fLL, 0x6fe0a32LL, 0x0LL, 0x744fccadLL, 0x504f3340LL,
0x837f0519LL, 0x0LL, 0xba27e657LL, 0xa82799a0LL, 0xc1bf828cLL, 0x0LL, 0x5d13f32bLL,
0xd413ccd0LL, 0x60dfc146LL, 0x0LL, 0xae89f996LL, 0x6a09e668LL, 0x306fe0a3LL, 0x0LL,
0xd744fccbLL, 0xb504f334LL, 0x9837f052LL, 0x80000000LL, 0x6ba27e65LL, 0x5a82799aLL,
0x4c1bf829LL, 0x40000000LL, 0x35d13f33LL, 0x2d413ccdLL, 0x260dfc14LL, 0x20000000LL,
0x1ae89f99LL, 0x16a09e66LL, 0x1306fe0aLL, 0x10000000LL, 0xd744fcdLL, 0xb504f33LL,
0x9837f05LL, 0x8000000LL, 0x6ba27e6LL, 0x5a8279aLL, 0x4c1bf83LL, 0x4000000LL,
0x35d13f3LL, 0x2d413cdLL, 0x260dfc1LL, 0x2000000LL, 0x1ae89faLL, 0x16a09e6LL,
0x1306fe1LL, 0x1000000LL, 0xd744fdLL, 0xb504f3LL, 0x9837f0LL, 0x800000LL,
0x6ba27eLL, 0x5a827aLL, 0x4c1bf8LL, 0x400000LL, 0x35d13fLL, 0x2d413dLL,
0x260dfcLL, 0x200000LL, 0x1ae8a0LL, 0x16a09eLL, 0x1306feLL, 0x100000LL,
0xd7450LL, 0xb504fLL, 0x9837fLL, 0x80000LL, 0x6ba28LL, 0x5a828LL, 0x4c1c0LL,
0x40000LL, 0x35d14LL, 0x2d414LL, 0x260e0LL, 0x20000LL, 0x1ae8aLL, 0x16a0aLL,
0x13070LL, 0x10000LL, 0xd745LL, 0xb505LL, 0x9838LL, 0x8000LL, 0x6ba2LL,
0x5a82LL, 0x4c1cLL, 0x4000LL, 0x35d1LL, 0x2d41LL, 0x260eLL, 0x2000LL,
0x1ae9LL, 0x16a1LL, 0x1307LL, 0x1000LL, 0xd74LL, 0xb50LL, 0x983LL, 0x800LL,
0x6baLL, 0x5a8LL, 0x4c2LL, 0x400LL, 0x35dLL, 0x2d4LL, 0x261LL, 0x200LL, 0x1afLL,
0x16aLL, 0x130LL, 0x100LL, 0xd7LL, 0xb5LL, 0x98LL, 0x80LL, 0x6cLL, 0x5bLL,
0x4cLL, 0x40LL, 0x36LL, 0x2dLL, 0x26LL, 0x20LL, 0x1bLL, 0x17LL, 0x13LL,
0x10LL, 0xdLL, 0xbLL, 0xaLL, 0x8LL, 0x7LL, 0x6LL, 0x5LL, 0x4LL, 0x3LL,
0x3LL, 0x2LL, 0x2LL, 0x2LL, 0x1LL, 0x1LL, 0x1LL, 0x1LL, 0x1LL, 0x1LL,
0x1LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL,
0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL,
0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL,
0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL,
0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL,
0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL, 0x0LL,
0x0LL, 0x0LL
};*/

const uint64_t lsp_pow_e_table[] =
{
1.99033E+14, 1.67366E+14, 1.40737E+14, 1.18346E+14,
9.95164E+13, 8.3683E+13, 7.03687E+13, 5.91728E+13,
4.97582E+13, 4.18415E+13, 3.51844E+13, 2.95864E+13,
2.48791E+13, 2.09208E+13, 1.75922E+13, 1.47932E+13,
1.24396E+13, 1.04604E+13, 8.79609E+12, 7.3966E+12,
6.21978E+12, 5.23019E+12, 4.39805E+12, 3.6983E+12,
3.10989E+12, 2.61509E+12, 2.19902E+12, 1.84915E+12,
1.55494E+12, 1.30755E+12, 1.09951E+12, 9.24575E+11,
7.77472E+11, 6.53774E+11, 5.49756E+11, 4.62288E+11,
3.88736E+11, 3.26887E+11, 2.74878E+11, 2.31144E+11,
1.94368E+11, 1.63443E+11, 1.37439E+11, 1.15572E+11,
97184015999, 81721690674, 68719476736, 57785961645,
48592008000, 40860845337, 34359738368, 28892980823,
24296004000, 20430422668, 17179869184, 14446490411,
12148002000, 10215211334, 8589934592, 7223245206,
6074001000, 5107605667, 4294967296, 3611622603,
3037000500, 2553802834, 2147483648, 1805811301,
1518500250, 1276901417, 1073741824, 902905651,
759250125, 638450708, 536870912, 451452825,
379625062, 319225354, 268435456, 225726413,
189812531, 159612677, 134217728, 112863206,
94906266, 79806339, 67108864, 56431603,
47453133, 39903169, 33554432, 28215802,
23726566, 19951585, 16777216, 14107901,
11863283, 9975792, 8388608, 7053950,
5931642, 4987896, 4194304, 3526975,
2965821, 2493948, 2097152, 1763488,
1482910, 1246974, 1048576, 881744,
741455, 623487, 524288, 440872,
370728, 311744, 262144, 220436,
185364, 155872, 131072, 110218,
92682, 77936, 65536, 55109,
46341, 38968, 32768, 27554,
23170, 19484, 16384, 13777,
11585, 9742, 8192, 6889,
5793, 4871, 4096, 3444,
2896, 2435, 2048, 1722,
1448, 1218, 1024, 861,
724, 609, 512, 431,
362, 304, 256, 215,
181, 152, 128, 108,
91, 76, 64, 54,
45, 38, 32, 27,
23, 19, 16, 13,
11, 10, 8, 7,
6, 5, 4, 3,
3, 2, 2, 2,
1, 1, 1, 1,
1, 1, 1, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0};


/* misc math functions */
const uint8_t ff_sqrt_tab[128]=
{
0, 1, 1, 1, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5, 5, 5,
5, 5, 5, 5, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
9, 9, 9, 9,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,11,11,11,11,11,11,11
};

const uint8_t ff_log2_tab[256]=
{
0,0,1,1,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7
};


const uint16_t tcos_0[] = {/*tablica s- & gt; mdct_ctx[0].tcos dla pliku 44,1kHz (dla pliku 22kHz nie jest wykorzystywana)*/
65535, 65535, 65535, 65534, 65534, 65533, 65532, 65531, 65530, 65529, 65527, 65525, 65524, 65522, 65520, 65517,
65515, 65512, 65510, 65507, 65504, 65501, 65497, 65494, 65490, 65486, 65482, 65478, 65474, 65470, 65465, 65460,
65455, 65450, 65445, 65440, 65434, 65429, 65423, 65417, 65411, 65405, 65398, 65392, 65385, 65378, 65371, 65364,
65357, 65349, 65341, 65334, 65326, 65318, 65309, 65301, 65292, 65284, 65275, 65266, 65256, 65247, 65238, 65228,
65218, 65208, 65198, 65188, 65177, 65167, 65156, 65145, 65134, 65123, 65112, 65100, 65089, 65077, 65065, 65053,
65041, 65028, 65016, 65003, 64990, 64977, 64964, 64951, 64937, 64923, 64910, 64896, 64882, 64867, 64853, 64839,
64824, 64809, 64794, 64779, 64764, 64748, 64732, 64717, 64701, 64685, 64669, 64652, 64636, 64619, 64602, 64585,
64568, 64551, 64533, 64516, 64498, 64480, 64462, 64444, 64426, 64407, 64388, 64370, 64351, 64332, 64312, 64293,
64273, 64254, 64234, 64214, 64194, 64173, 64153, 64132, 64111, 64091, 64069, 64048, 64027, 64005, 63984, 63962,
63940, 63918, 63895, 63873, 63851, 63828, 63805, 63782, 63759, 63735, 63712, 63688, 63665, 63641, 63617, 63592,
63568, 63543, 63519, 63494, 63469, 63444, 63419, 63393, 63368, 63342, 63316, 63290, 63264, 63238, 63211, 63184,
63158, 63131, 63104, 63077, 63049, 63022, 62994, 62966, 62938, 62910, 62882, 62854, 62825, 62796, 62768, 62739,
62709, 62680, 62651, 62621, 62591, 62562, 62532, 62501, 62471, 62441, 62410, 62379, 62348, 62317, 62286, 62255,
62223, 62192, 62160, 62128, 62096, 62064, 62031, 61999, 61966, 61933, 61901, 61867, 61834, 61801, 61767, 61734,
61700, 61666, 61632, 61598, 61563, 61529, 61494, 61459, 61424, 61389, 61354, 61318, 61283, 61247, 61211, 61175,
61139, 61103, 61066, 61030, 60993, 60956, 60919, 60882, 60845, 60808, 60770, 60732, 60694, 60656, 60618, 60580,
60542, 60503, 60464, 60426, 60387, 60347, 60308, 60269, 60229, 60189, 60150, 60110, 60070, 60029, 59989, 59948,
59908, 59867, 59826, 59785, 59743, 59702, 59661, 59619, 59577, 59535, 59493, 59451, 59408, 59366, 59323, 59280,
59238, 59194, 59151, 59108, 59064, 59021, 58977, 58933, 58889, 58845, 58801, 58756, 58712, 58667, 58622, 58577,
58532, 58487, 58441, 58396, 58350, 58304, 58258, 58212, 58166, 58119, 58073, 58026, 57979, 57932, 57885, 57838,
57791, 57743, 57696, 57648, 57600, 57552, 57504, 57456, 57407, 57359, 57310, 57261, 57212, 57163, 57114, 57064,
57015, 56965, 56916, 56866, 56816, 56765, 56715, 56665, 56614, 56563, 56513, 56462, 56411, 56359, 56308, 56256,
56205, 56153, 56101, 56049, 55997, 55945, 55892, 55840, 55787, 55734, 55681, 55628, 55575, 55522, 55468, 55414,
55361, 55307, 55253, 55199, 55145, 55090, 55036, 54981, 54926, 54871, 54816, 54761, 54706, 54650, 54595, 54539,
54483, 54427, 54371, 54315, 54259, 54202, 54146, 54089, 54032, 53975, 53918, 53861, 53804, 53746, 53689, 53631,
53573, 53515, 53457, 53399, 53341, 53282, 53224, 53165, 53106, 53047, 52988, 52929, 52869, 52810, 52750, 52691,
52631, 52571, 52511, 52450, 52390, 52330, 52269, 52208, 52148, 52087, 52026, 51964, 51903, 51842, 51780, 51718,
51657, 51595, 51533, 51470, 51408, 51346, 51283, 51221, 51158, 51095, 51032, 50969, 50905, 50842, 50779, 50715,
50651, 50587, 50523, 50459, 50395, 50331, 50266, 50202, 50137, 50072, 50007, 49942, 49877, 49812, 49747, 49681,
49615, 49550, 49484, 49418, 49352, 49286, 49219, 49153, 49086, 49020, 48953, 48886, 48819, 48752, 48685, 48617,
48550, 48482, 48415, 48347, 48279, 48211, 48143, 48074, 48006, 47937, 47869, 47800, 47731, 47662, 47593, 47524,
47455, 47385, 47316, 47246, 47177, 47107, 47037, 46967, 46897, 46826, 46756, 46685, 46615, 46544, 46473, 46402,
46331, 46260, 46189, 46118, 46046, 45975, 45903, 45831, 45759, 45687, 45615, 45543, 45470, 45398, 45325, 45253,
45180, 45107, 45034, 44961, 44888, 44815, 44741, 44668, 44594, 44520, 44446, 44373, 44298, 44224, 44150, 44076,
44001, 43927, 43852, 43777, 43702, 43628, 43552, 43477, 43402, 43327, 43251, 43176, 43100, 43024, 42948, 42872,
42796, 42720, 42644, 42567, 42491, 42414, 42338, 42261, 42184, 42107, 42030, 41953, 41875, 41798, 41720, 41643,
41565, 41487, 41410, 41332, 41254, 41175, 41097, 41019, 40940, 40862, 40783, 40704, 40626, 40547, 40468, 40389,
40309, 40230, 40151, 40071, 39991, 39912, 39832, 39752, 39672, 39592, 39512, 39432, 39351, 39271, 39190, 39110,
39029, 38948, 38867, 38786, 38705, 38624, 38543, 38462, 38380, 38299, 38217, 38135, 38053, 37972, 37890, 37807,
37725, 37643, 37561, 37478, 37396, 37313, 37231, 37148, 37065, 36982, 36899, 36816, 36733, 36649, 36566, 36482,
36399, 36315, 36231, 36148, 36064, 35980, 35896, 35812, 35727, 35643, 35559, 35474, 35390, 35305, 35220, 35135,
35050, 34965, 34880, 34795, 34710, 34625, 34539, 34454, 34368, 34283, 34197, 34111, 34025, 33939, 33853, 33767,
33681, 33595, 33508, 33422, 33335, 33249, 33162, 33075, 32989, 32902, 32815, 32728, 32640, 32553, 32466, 32379,
32291, 32204, 32116, 32028, 31941, 31853, 31765, 31677, 31589, 31501, 31413, 31324, 31236, 31148, 31059, 30971,
30882, 30793, 30704, 30616, 30527, 30438, 30349, 30259, 30170, 30081, 29992, 29902, 29813, 29723, 29634, 29544,
29454, 29364, 29274, 29184, 29094, 29004, 28914, 28824, 28733, 28643, 28553, 28462, 28371, 28281, 28190, 28099,
28008, 27918, 27827, 27736, 27644, 27553, 27462, 27371, 27279, 27188, 27096, 27005, 26913, 26821, 26730, 26638,
26546, 26454, 26362, 26270, 26178, 26086, 25993, 25901, 25809, 25716, 25624, 25531, 25439, 25346, 25253, 25160,
25068, 24975, 24882, 24789, 24696, 24602, 24509, 24416, 24323, 24229, 24136, 24042, 23949, 23855, 23761, 23668,
23574, 23480, 23386, 23292, 23198, 23104, 23010, 22916, 22822, 22728, 22633, 22539, 22444, 22350, 22255, 22161,
22066, 21972, 21877, 21782, 21687, 21592, 21497, 21402, 21307, 21212, 21117, 21022, 20927, 20831, 20736, 20641,
20545, 20450, 20354, 20259, 20163, 20067, 19972, 19876, 19780, 19684, 19588, 19492, 19396, 19300, 19204, 19108,
19012, 18916, 18819, 18723, 18627, 18530, 18434, 18337, 18241, 18144, 18048, 17951, 17854, 17757, 17661, 17564,
17467, 17370, 17273, 17176, 17079, 16982, 16885, 16788, 16690, 16593, 16496, 16399, 16301, 16204, 16106, 16009,
15912, 15814, 15716, 15619, 15521, 15423, 15326, 15228, 15130, 15032, 14934, 14837, 14739, 14641, 14543, 14445,
14347, 14248, 14150, 14052, 13954, 13856, 13757, 13659, 13561, 13462, 13364, 13266, 13167, 13069, 12970, 12872,
12773, 12674, 12576, 12477, 12378, 12280, 12181, 12082, 11983, 11884, 11785, 11687, 11588, 11489, 11390, 11291,
11192, 11093, 10993, 10894, 10795, 10696, 10597, 10498, 10398, 10299, 10200, 10100, 10001, 9902, 9802, 9703,
9604, 9504, 9405, 9305, 9206, 9106, 9006, 8907, 8807, 8708, 8608, 8508, 8409, 8309, 8209, 8109,
8010, 7910, 7810, 7710, 7610, 7511, 7411, 7311, 7211, 7111, 7011, 6911, 6811, 6711, 6611, 6511,
6411, 6311, 6211, 6111, 6011, 5911, 5811, 5710, 5610, 5510, 5410, 5310, 5209, 5109, 5009, 4909,
4809, 4708, 4608, 4508, 4407, 4307, 4207, 4106, 4006, 3906, 3805, 3705, 3605, 3504, 3404, 3304,
3203, 3103, 3002, 2902, 2801, 2701, 2601, 2500, 2400, 2299, 2199, 2098, 1998, 1897, 1797, 1696,
1596, 1495, 1395, 1294, 1194, 1093, 993, 892, 792, 691, 591, 490, 390, 289, 188, 88};

const uint16_t tsin_0[] = {/*tablica s- & gt; mdct_ctx[0].tsin dla pliku 44,1kHz (dla pliku 22kHz nie jest wykorzystywana)*/
13, 113, 214, 314, 415, 515, 616, 716, 817, 917, 1018, 1118, 1219, 1319, 1420, 1520,
1621, 1721, 1822, 1922, 2023, 2123, 2224, 2324, 2425, 2525, 2626, 2726, 2827, 2927, 3027, 3128,
3228, 3329, 3429, 3529, 3630, 3730, 3831, 3931, 4031, 4132, 4232, 4332, 4432, 4533, 4633, 4733,
4834, 4934, 5034, 5134, 5235, 5335, 5435, 5535, 5635, 5735, 5836, 5936, 6036, 6136, 6236, 6336,
6436, 6536, 6636, 6736, 6836, 6936, 7036, 7136, 7236, 7336, 7436, 7536, 7635, 7735, 7835, 7935,
8035, 8134, 8234, 8334, 8434, 8533, 8633, 8733, 8832, 8932, 9031, 9131, 9230, 9330, 9429, 9529,
9628, 9728, 9827, 9927, 10026, 10125, 10225, 10324, 10423, 10522, 10622, 10721, 10820, 10919, 11018, 11117,
11216, 11315, 11414, 11513, 11612, 11711, 11810, 11909, 12008, 12107, 12205, 12304, 12403, 12502, 12600, 12699,
12798, 12896, 12995, 13093, 13192, 13290, 13389, 13487, 13585, 13684, 13782, 13880, 13978, 14077, 14175, 14273,
14371, 14469, 14567, 14665, 14763, 14861, 14959, 15057, 15155, 15252, 15350, 15448, 15546, 15643, 15741, 15838,
15936, 16033, 16131, 16228, 16326, 16423, 16520, 16618, 16715, 16812, 16909, 17006, 17103, 17200, 17297, 17394,
17491, 17588, 17685, 17782, 17878, 17975, 18072, 18168, 18265, 18361, 18458, 18554, 18651, 18747, 18843, 18940,
19036, 19132, 19228, 19324, 19420, 19516, 19612, 19708, 19804, 19900, 19996, 20091, 20187, 20282, 20378, 20474,
20569, 20664, 20760, 20855, 20950, 21046, 21141, 21236, 21331, 21426, 21521, 21616, 21711, 21806, 21901, 21995,
22090, 22185, 22279, 22374, 22468, 22562, 22657, 22751, 22845, 22940, 23034, 23128, 23222, 23316, 23410, 23504,
23597, 23691, 23785, 23879, 23972, 24066, 24159, 24253, 24346, 24439, 24532, 24626, 24719, 24812, 24905, 24998,
25091, 25184, 25276, 25369, 25462, 25554, 25647, 25739, 25832, 25924, 26016, 26109, 26201, 26293, 26385, 26477,
26569, 26661, 26753, 26844, 26936, 27028, 27119, 27211, 27302, 27393, 27485, 27576, 27667, 27758, 27849, 27940,
28031, 28122, 28213, 28303, 28394, 28485, 28575, 28666, 28756, 28846, 28937, 29027, 29117, 29207, 29297, 29387,
29477, 29566, 29656, 29746, 29835, 29925, 30014, 30103, 30193, 30282, 30371, 30460, 30549, 30638, 30727, 30815,
30904, 30993, 31081, 31170, 31258, 31346, 31435, 31523, 31611, 31699, 31787, 31875, 31963, 32050, 32138, 32226,
32313, 32400, 32488, 32575, 32662, 32749, 32836, 32923, 33010, 33097, 33184, 33270, 33357, 33443, 33530, 33616,
33703, 33789, 33875, 33961, 34047, 34133, 34218, 34304, 34390, 34475, 34561, 34646, 34731, 34817, 34902, 34987,
35072, 35157, 35241, 35326, 35411, 35495, 35580, 35664, 35748, 35833, 35917, 36001, 36085, 36169, 36252, 36336,
36420, 36503, 36587, 36670, 36753, 36837, 36920, 37003, 37086, 37168, 37251, 37334, 37416, 37499, 37581, 37664,
37746, 37828, 37910, 37992, 38074, 38156, 38237, 38319, 38400, 38482, 38563, 38644, 38726, 38807, 38888, 38968,
39049, 39130, 39211, 39291, 39371, 39452, 39532, 39612, 39692, 39772, 39852, 39932, 40011, 40091, 40170, 40250,
40329, 40408, 40487, 40566, 40645, 40724, 40803, 40881, 40960, 41038, 41117, 41195, 41273, 41351, 41429, 41507,
41585, 41662, 41740, 41817, 41895, 41972, 42049, 42126, 42203, 42280, 42357, 42433, 42510, 42586, 42663, 42739,
42815, 42891, 42967, 43043, 43119, 43194, 43270, 43345, 43421, 43496, 43571, 43646, 43721, 43796, 43871, 43945,
44020, 44094, 44169, 44243, 44317, 44391, 44465, 44539, 44612, 44686, 44759, 44833, 44906, 44979, 45052, 45125,
45198, 45271, 45344, 45416, 45488, 45561, 45633, 45705, 45777, 45849, 45921, 45992, 46064, 46135, 46207, 46278,
46349, 46420, 46491, 46562, 46633, 46703, 46774, 46844, 46914, 46984, 47054, 47124, 47194, 47264, 47333, 47403,
47472, 47541, 47611, 47680, 47749, 47817, 47886, 47955, 48023, 48091, 48160, 48228, 48296, 48364, 48431, 48499,
48567, 48634, 48701, 48769, 48836, 48903, 48970, 49036, 49103, 49169, 49236, 49302, 49368, 49434, 49500, 49566,
49632, 49697, 49763, 49828, 49894, 49959, 50024, 50089, 50153, 50218, 50283, 50347, 50411, 50475, 50539, 50603,
50667, 50731, 50794, 50858, 50921, 50985, 51048, 51111, 51173, 51236, 51299, 51361, 51424, 51486, 51548, 51610,
51672, 51734, 51795, 51857, 51918, 51980, 52041, 52102, 52163, 52224, 52284, 52345, 52405, 52466, 52526, 52586,
52646, 52705, 52765, 52825, 52884, 52943, 53003, 53062, 53121, 53179, 53238, 53297, 53355, 53413, 53472, 53530,
53588, 53645, 53703, 53761, 53818, 53875, 53933, 53990, 54047, 54103, 54160, 54217, 54273, 54329, 54385, 54441,
54497, 54553, 54609, 54664, 54720, 54775, 54830, 54885, 54940, 54995, 55049, 55104, 55158, 55212, 55266, 55320,
55374, 55428, 55481, 55535, 55588, 55641, 55694, 55747, 55800, 55853, 55905, 55958, 56010, 56062, 56114, 56166,
56218, 56269, 56321, 56372, 56423, 56474, 56525, 56576, 56627, 56677, 56728, 56778, 56828, 56878, 56928, 56978,
57027, 57077, 57126, 57175, 57224, 57273, 57322, 57371, 57419, 57468, 57516, 57564, 57612, 57660, 57708, 57755,
57803, 57850, 57897, 57944, 57991, 58038, 58084, 58131, 58177, 58223, 58270, 58315, 58361, 58407, 58452, 58498,
58543, 58588, 58633, 58678, 58723, 58767, 58812, 58856, 58900, 58944, 58988, 59032, 59075, 59119, 59162, 59205,
59248, 59291, 59334, 59377, 59419, 59461, 59504, 59546, 59588, 59629, 59671, 59712, 59754, 59795, 59836, 59877,
59918, 59958, 59999, 60039, 60080, 60120, 60160, 60199, 60239, 60279, 60318, 60357, 60396, 60435, 60474, 60513,
60551, 60590, 60628, 60666, 60704, 60742, 60779, 60817, 60854, 60892, 60929, 60966, 61002, 61039, 61076, 61112,
61148, 61184, 61220, 61256, 61292, 61327, 61363, 61398, 61433, 61468, 61503, 61537, 61572, 61606, 61640, 61674,
61708, 61742, 61776, 61809, 61843, 61876, 61909, 61942, 61974, 62007, 62040, 62072, 62104, 62136, 62168, 62200,
62231, 62263, 62294, 62325, 62356, 62387, 62418, 62448, 62479, 62509, 62539, 62569, 62599, 62629, 62658, 62687,
62717, 62746, 62775, 62804, 62832, 62861, 62889, 62917, 62945, 62973, 63001, 63029, 63056, 63083, 63111, 63138,
63164, 63191, 63218, 63244, 63270, 63297, 63323, 63348, 63374, 63400, 63425, 63450, 63475, 63500, 63525, 63550,
63574, 63598, 63623, 63647, 63670, 63694, 63718, 63741, 63765, 63788, 63811, 63833, 63856, 63879, 63901, 63923,
63945, 63967, 63989, 64011, 64032, 64054, 64075, 64096, 64117, 64137, 64158, 64178, 64199, 64219, 64239, 64259,
64278, 64298, 64317, 64336, 64355, 64374, 64393, 64412, 64430, 64448, 64467, 64485, 64502, 64520, 64538, 64555,
64572, 64589, 64606, 64623, 64640, 64656, 64673, 64689, 64705, 64721, 64736, 64752, 64767, 64783, 64798, 64813,
64828, 64842, 64857, 64871, 64885, 64899, 64913, 64927, 64940, 64954, 64967, 64980, 64993, 65006, 65019, 65031,
65044, 65056, 65068, 65080, 65092, 65103, 65115, 65126, 65137, 65148, 65159, 65170, 65180, 65190, 65201, 65211,
65221, 65230, 65240, 65249, 65259, 65268, 65277, 65286, 65294, 65303, 65311, 65320, 65328, 65336, 65343, 65351,
65358, 65366, 65373, 65380, 65387, 65393, 65400, 65406, 65412, 65419, 65424, 65430, 65436, 65441, 65447, 65452,
65457, 65462, 65466, 65471, 65475, 65479, 65483, 65487, 65491, 65495, 65498, 65501, 65505, 65508, 65510, 65513,
65516, 65518, 65520, 65522, 65524, 65526, 65527, 65529, 65530, 65531, 65532, 65533, 65534, 65534, 65535, 65535};

const FFTComplex exptab_0[] = {/*tablica s- & gt; mdct_ctx[0].exptab dla pliku 44,1kHz (dla pliku 22kHz nie jest wykorzystywana)*/
/*re im re im re im re im */
65536, 0, 65535, 402, 65531, 804, 65525, 1206,
65516, 1608, 65505, 2010, 65492, 2412, 65476, 2814,
65457, 3216, 65436, 3617, 65413, 4019, 65387, 4420,
65358, 4821, 65328, 5222, 65294, 5623, 65259, 6023,
65220, 6424, 65180, 6824, 65137, 7224, 65091, 7623,
65043, 8022, 64993, 8421, 64940, 8820, 64884, 9218,
64827, 9616, 64766, 10014, 64704, 10411, 64639, 10808,
64571, 11204, 64501, 11600, 64429, 11996, 64354, 12391,
64277, 12785, 64197, 13180, 64115, 13573, 64031, 13966,
63944, 14359, 63854, 14751, 63763, 15143, 63668, 15534,
63572, 15924, 63473, 16314, 63372, 16703, 63268, 17091,
63162, 17479, 63054, 17867, 62943, 18253, 62830, 18639,
62714, 19024, 62596, 19409, 62476, 19792, 62353, 20175,
62228, 20557, 62101, 20939, 61971, 21320, 61839, 21699,
61705, 22078, 61568, 22457, 61429, 22834, 61288, 23210,
61145, 23586, 60999, 23961, 60851, 24335, 60700, 24708,
60547, 25080, 60392, 25451, 60235, 25821, 60075, 26190,
59914, 26558, 59750, 26925, 59583, 27291, 59415, 27656,
59244, 28020, 59071, 28383, 58896, 28745, 58718, 29106,
58538, 29466, 58356, 29824, 58172, 30182, 57986, 30538,
57798, 30893, 57607, 31248, 57414, 31600, 57219, 31952,
57022, 32303, 56823, 32652, 56621, 33000, 56418, 33347,
56212, 33692, 56004, 34037, 55794, 34380, 55582, 34721,
55368, 35062, 55152, 35401, 54934, 35738, 54714, 36075,
54491, 36410, 54267, 36744, 54040, 37076, 53812, 37407,
53581, 37736, 53349, 38064, 53114, 38391, 52878, 38716,
52639, 39040, 52398, 39362, 52156, 39683, 51911, 40002,
51665, 40320, 51417, 40636, 51166, 40951, 50914, 41264,
50660, 41576, 50404, 41886, 50146, 42194, 49886, 42501,
49624, 42806, 49361, 43110, 49095, 43412, 48828, 43713,
48559, 44011, 48288, 44308, 48015, 44604, 47741, 44898,
47464, 45190, 47186, 45480, 46906, 45769, 46624, 46056,
46341, 46341, 46056, 46624, 45769, 46906, 45480, 47186,
45190, 47464, 44898, 47741, 44604, 48015, 44308, 48288,
44011, 48559, 43713, 48828, 43412, 49095, 43110, 49361,
42806, 49624, 42501, 49886, 42194, 50146, 41886, 50404,
41576, 50660, 41264, 50914, 40951, 51166, 40636, 51417,
40320, 51665, 40002, 51911, 39683, 52156, 39362, 52398,
39040, 52639, 38716, 52878, 38391, 53114, 38064, 53349,
37736, 53581, 37407, 53812, 37076, 54040, 36744, 54267,
36410, 54491, 36075, 54714, 35738, 54934, 35401, 55152,
35062, 55368, 34721, 55582, 34380, 55794, 34037, 56004,
33692, 56212, 33347, 56418, 33000, 56621, 32652, 56823,
32303, 57022, 31952, 57219, 31600, 57414, 31248, 57607,
30893, 57798, 30538, 57986, 30182, 58172, 29824, 58356,
29466, 58538, 29106, 58718, 28745, 58896, 28383, 59071,
28020, 59244, 27656, 59415, 27291, 59583, 26925, 59750,
26558, 59914, 26190, 60075, 25821, 60235, 25451, 60392,
25080, 60547, 24708, 60700, 24335, 60851, 23961, 60999,
23586, 61145, 23210, 61288, 22834, 61429, 22457, 61568,
22078, 61705, 21699, 61839, 21320, 61971, 20939, 62101,
20557, 62228, 20175, 62353, 19792, 62476, 19409, 62596,
19024, 62714, 18639, 62830, 18253, 62943, 17867, 63054,
17479, 63162, 17091, 63268, 16703, 63372, 16314, 63473,
15924, 63572, 15534, 63668, 15143, 63763, 14751, 63854,
14359, 63944, 13966, 64031, 13573, 64115, 13180, 64197,
12785, 64277, 12391, 64354, 11996, 64429, 11600, 64501,
11204, 64571, 10808, 64639, 10411, 64704, 10014, 64766,
9616, 64827, 9218, 64884, 8820, 64940, 8421, 64993,
8022, 65043, 7623, 65091, 7224, 65137, 6824, 65180,
6424, 65220, 6023, 65259, 5623, 65294, 5222, 65328,
4821, 65358, 4420, 65387, 4019, 65413, 3617, 65436,
3216, 65457, 2814, 65476, 2412, 65492, 2010, 65505,
1608, 65516, 1206, 65525, 804, 65531, 402, 65535,
0, 65536, -402, 65535, -804, 65531, -1206, 65525,
-1608, 65516, -2010, 65505, -2412, 65492, -2814, 65476,
-3216, 65457, -3617, 65436, -4019, 65413, -4420, 65387,
-4821, 65358, -5222, 65328, -5623, 65294, -6023, 65259,
-6424, 65220, -6824, 65180, -7224, 65137, -7623, 65091,
-8022, 65043, -8421, 64993, -8820, 64940, -9218, 64884,
-9616, 64827, -10014, 64766, -10411, 64704, -10808, 64639,
-11204, 64571, -11600, 64501, -11996, 64429, -12391, 64354,
-12785, 64277, -13180, 64197, -13573, 64115, -13966, 64031,
-14359, 63944, -14751, 63854, -15143, 63763, -15534, 63668,
-15924, 63572, -16314, 63473, -16703, 63372, -17091, 63268,
-17479, 63162, -17867, 63054, -18253, 62943, -18639, 62830,
-19024, 62714, -19409, 62596, -19792, 62476, -20175, 62353,
-20557, 62228, -20939, 62101, -21320, 61971, -21699, 61839,
-22078, 61705, -22457, 61568, -22834, 61429, -23210, 61288,
-23586, 61145, -23961, 60999, -24335, 60851, -24708, 60700,
-25080, 60547, -25451, 60392, -25821, 60235, -26190, 60075,
-26558, 59914, -26925, 59750, -27291, 59583, -27656, 59415,
-28020, 59244, -28383, 59071, -28745, 58896, -29106, 58718,
-29466, 58538, -29824, 58356, -30182, 58172, -30538, 57986,
-30893, 57798, -31248, 57607, -31600, 57414, -31952, 57219,
-32303, 57022, -32652, 56823, -33000, 56621, -33347, 56418,
-33692, 56212, -34037, 56004, -34380, 55794, -34721, 55582,
-35062, 55368, -35401, 55152, -35738, 54934, -36075, 54714,
-36410, 54491, -36744, 54267, -37076, 54040, -37407, 53812,
-37736, 53581, -38064, 53349, -38391, 53114, -38716, 52878,
-39040, 52639, -39362, 52398, -39683, 52156, -40002, 51911,
-40320, 51665, -40636, 51417, -40951, 51166, -41264, 50914,
-41576, 50660, -41886, 50404, -42194, 50146, -42501, 49886,
-42806, 49624, -43110, 49361, -43412, 49095, -43713, 48828,
-44011, 48559, -44308, 48288, -44604, 48015, -44898, 47741,
-45190, 47464, -45480, 47186, -45769, 46906, -46056, 46624,
-46341, 46341, -46624, 46056, -46906, 45769, -47186, 45480,
-47464, 45190, -47741, 44898, -48015, 44604, -48288, 44308,
-48559, 44011, -48828, 43713, -49095, 43412, -49361, 43110,
-49624, 42806, -49886, 42501, -50146, 42194, -50404, 41886,
-50660, 41576, -50914, 41264, -51166, 40951, -51417, 40636,
-51665, 40320, -51911, 40002, -52156, 39683, -52398, 39362,
-52639, 39040, -52878, 38716, -53114, 38391, -53349, 38064,
-53581, 37736, -53812, 37407, -54040, 37076, -54267, 36744,
-54491, 36410, -54714, 36075, -54934, 35738, -55152, 35401,
-55368, 35062, -55582, 34721, -55794, 34380, -56004, 34037,
-56212, 33692, -56418, 33347, -56621, 33000, -56823, 32652,
-57022, 32303, -57219, 31952, -57414, 31600, -57607, 31248,
-57798, 30893, -57986, 30538, -58172, 30182, -58356, 29824,
-58538, 29466, -58718, 29106, -58896, 28745, -59071, 28383,
-59244, 28020, -59415, 27656, -59583, 27291, -59750, 26925,
-59914, 26558, -60075, 26190, -60235, 25821, -60392, 25451,
-60547, 25080, -60700, 24708, -60851, 24335, -60999, 23961,
-61145, 23586, -61288, 23210, -61429, 22834, -61568, 22457,
-61705, 22078, -61839, 21699, -61971, 21320, -62101, 20939,
-62228, 20557, -62353, 20175, -62476, 19792, -62596, 19409,
-62714, 19024, -62830, 18639, -62943, 18253, -63054, 17867,
-63162, 17479, -63268, 17091, -63372, 16703, -63473, 16314,
-63572, 15924, -63668, 15534, -63763, 15143, -63854, 14751,
-63944, 14359, -64031, 13966, -64115, 13573, -64197, 13180,
-64277, 12785, -64354, 12391, -64429, 11996, -64501, 11600,
-64571, 11204, -64639, 10808, -64704, 10411, -64766, 10014,
-64827, 9616, -64884, 9218, -64940, 8820, -64993, 8421,
-65043, 8022, -65091, 7623, -65137, 7224, -65180, 6824,
-65220, 6424, -65259, 6023, -65294, 5623, -65328, 5222,
-65358, 4821, -65387, 4420, -65413, 4019, -65436, 3617,
-65457, 3216, -65476, 2814, -65492, 2412, -65505, 2010,
-65516, 1608, -65525, 1206, -65531, 804, -65535, 402};



const uint16_t tcos_1[] = {/*tablica s- & gt; mdct_ctx[1].tcos dla pliku 44,1kHz lub s- & gt; mdct_ctx[0].tcos dla pliku 22kHz*/
65535, 65535, 65534, 65532, 65530, 65527, 65523, 65519, 65515, 65509, 65503, 65497, 65490, 65482, 65473, 65464,
65455, 65445, 65434, 65422, 65410, 65397, 65384, 65370, 65356, 65340, 65325, 65308, 65291, 65274, 65255, 65236,
65217, 65197, 65176, 65155, 65133, 65110, 65087, 65063, 65039, 65014, 64988, 64962, 64935, 64908, 64880, 64851,
64822, 64792, 64762, 64731, 64699, 64666, 64634, 64600, 64566, 64531, 64496, 64460, 64423, 64386, 64348, 64310,
64271, 64231, 64191, 64150, 64109, 64067, 64024, 63981, 63937, 63893, 63848, 63802, 63756, 63709, 63662, 63614,
63565, 63516, 63466, 63415, 63364, 63313, 63261, 63208, 63154, 63100, 63046, 62991, 62935, 62878, 62821, 62764,
62706, 62647, 62588, 62528, 62467, 62406, 62345, 62282, 62219, 62156, 62092, 62027, 61962, 61896, 61830, 61763,
61696, 61628, 61559, 61490, 61420, 61349, 61278, 61207, 61135, 61062, 60989, 60915, 60840, 60765, 60690, 60614,
60537, 60460, 60382, 60303, 60224, 60145, 60065, 59984, 59903, 59821, 59738, 59655, 59572, 59488, 59403, 59318,
59232, 59146, 59059, 58972, 58884, 58795, 58706, 58616, 58526, 58435, 58344, 58252, 58160, 58067, 57973, 57879,
57785, 57690, 57594, 57498, 57401, 57304, 57206, 57108, 57009, 56909, 56809, 56709, 56608, 56506, 56404, 56301,
56198, 56095, 55990, 55886, 55780, 55675, 55568, 55461, 55354, 55246, 55138, 55029, 54919, 54809, 54699, 54588,
54476, 54364, 54252, 54139, 54025, 53911, 53797, 53682, 53566, 53450, 53333, 53216, 53099, 52980, 52862, 52743,
52623, 52503, 52383, 52262, 52140, 52018, 51895, 51772, 51649, 51525, 51400, 51275, 51150, 51024, 50898, 50771,
50643, 50515, 50387, 50258, 50129, 49999, 49869, 49738, 49607, 49476, 49344, 49211, 49078, 48945, 48811, 48676,
48541, 48406, 48270, 48134, 47997, 47860, 47723, 47585, 47446, 47307, 47168, 47028, 46888, 46747, 46606, 46464,
46322, 46180, 46037, 45894, 45750, 45606, 45461, 45316, 45171, 45025, 44879, 44732, 44585, 44437, 44289, 44141,
43992, 43843, 43693, 43543, 43393, 43242, 43090, 42939, 42787, 42634, 42481, 42328, 42174, 42020, 41866, 41711,
41556, 41400, 41244, 41087, 40931, 40773, 40616, 40458, 40299, 40141, 39982, 39822, 39662, 39502, 39341, 39180,
39019, 38857, 38695, 38533, 38370, 38207, 38043, 37879, 37715, 37550, 37385, 37220, 37055, 36888, 36722, 36555,
36388, 36221, 36053, 35885, 35717, 35548, 35379, 35210, 35040, 34870, 34699, 34529, 34358, 34186, 34015, 33842,
33670, 33498, 33325, 33151, 32978, 32804, 32630, 32455, 32280, 32105, 31930, 31754, 31578, 31402, 31225, 31048,
30871, 30693, 30516, 30337, 30159, 29980, 29802, 29622, 29443, 29263, 29083, 28903, 28722, 28541, 28360, 28179,
27997, 27815, 27633, 27451, 27268, 27085, 26902, 26718, 26535, 26351, 26166, 25982, 25797, 25612, 25427, 25242,
25056, 24870, 24684, 24498, 24311, 24124, 23937, 23750, 23562, 23375, 23187, 22998, 22810, 22621, 22433, 22244,
22054, 21865, 21675, 21485, 21295, 21105, 20915, 20724, 20533, 20342, 20151, 19960, 19768, 19576, 19384, 19192,
19000, 18807, 18615, 18422, 18229, 18035, 17842, 17649, 17455, 17261, 17067, 16873, 16678, 16484, 16289, 16094,
15899, 15704, 15509, 15314, 15118, 14922, 14726, 14530, 14334, 14138, 13942, 13745, 13548, 13352, 13155, 12958,
12761, 12563, 12366, 12168, 11971, 11773, 11575, 11377, 11179, 10981, 10783, 10584, 10386, 10187, 9989, 9790,
9591, 9392, 9193, 8994, 8795, 8596, 8396, 8197, 7997, 7798, 7598, 7398, 7198, 6999, 6799, 6599,
6399, 6198, 5998, 5798, 5598, 5397, 5197, 4996, 4796, 4595, 4395, 4194, 3994, 3793, 3592, 3391,
3191, 2990, 2789, 2588, 2387, 2186, 1985, 1784, 1583, 1382, 1181, 980, 779, 578, 377, 176};

const uint16_t tsin_1[] = {/*tablica s- & gt; mdct_ctx[1].tsin dla pliku 44,1kHz lub s- & gt; mdct_ctx[0].tsin dla pliku 22kHz*/
25, 226, 427, 628, 829, 1030, 1231, 1432, 1633, 1834, 2035, 2236, 2437, 2638, 2839, 3040,
3241, 3442, 3642, 3843, 4044, 4244, 4445, 4646, 4846, 5047, 5247, 5447, 5648, 5848, 6048, 6248,
6449, 6649, 6849, 7049, 7248, 7448, 7648, 7848, 8047, 8247, 8446, 8645, 8845, 9044, 9243, 9442,
9641, 9840, 10038, 10237, 10436, 10634, 10832, 11031, 11229, 11427, 11625, 11823, 12020, 12218, 12415, 12613,
12810, 13007, 13204, 13401, 13598, 13794, 13991, 14187, 14383, 14579, 14775, 14971, 15167, 15362, 15558, 15753,
15948, 16143, 16338, 16532, 16727, 16921, 17115, 17309, 17503, 17697, 17890, 18084, 18277, 18470, 18663, 18855,
19048, 19240, 19432, 19624, 19816, 20007, 20199, 20390, 20581, 20772, 20962, 21153, 21343, 21533, 21723, 21912,
22102, 22291, 22480, 22669, 22857, 23045, 23234, 23421, 23609, 23797, 23984, 24171, 24358, 24544, 24730, 24917,
25102, 25288, 25473, 25658, 25843, 26028, 26212, 26397, 26580, 26764, 26948, 27131, 27314, 27496, 27679, 27861,
28043, 28224, 28405, 28587, 28767, 28948, 29128, 29308, 29488, 29667, 29846, 30025, 30204, 30382, 30560, 30738,
30915, 31092, 31269, 31446, 31622, 31798, 31974, 32149, 32324, 32499, 32673, 32847, 33021, 33195, 33368, 33541,
33713, 33886, 34057, 34229, 34400, 34571, 34742, 34912, 35082, 35252, 35421, 35590, 35759, 35927, 36095, 36263,
36430, 36597, 36764, 36930, 37096, 37262, 37427, 37592, 37756, 37920, 38084, 38248, 38411, 38573, 38736, 38898,
39059, 39221, 39381, 39542, 39702, 39862, 40021, 40180, 40339, 40497, 40655, 40813, 40970, 41127, 41283, 41439,
41594, 41750, 41904, 42059, 42213, 42366, 42520, 42672, 42825, 42977, 43128, 43279, 43430, 43581, 43731, 43880,
44029, 44178, 44326, 44474, 44622, 44769, 44915, 45061, 45207, 45353, 45498, 45642, 45786, 45930, 46073, 46216,
46358, 46500, 46641, 46782, 46923, 47063, 47203, 47342, 47481, 47619, 47757, 47895, 48032, 48168, 48304, 48440,
48575, 48710, 48844, 48978, 49111, 49244, 49377, 49509, 49640, 49771, 49902, 50032, 50161, 50291, 50419, 50547,
50675, 50802, 50929, 51056, 51181, 51307, 51431, 51556, 51680, 51803, 51926, 52048, 52170, 52292, 52413, 52533,
52653, 52773, 52892, 53010, 53128, 53245, 53362, 53479, 53595, 53710, 53825, 53940, 54054, 54167, 54280, 54392,
54504, 54616, 54727, 54837, 54947, 55056, 55165, 55273, 55381, 55488, 55595, 55701, 55807, 55912, 56017, 56121,
56224, 56327, 56430, 56532, 56633, 56734, 56834, 56934, 57034, 57132, 57231, 57328, 57425, 57522, 57618, 57714,
57809, 57903, 57997, 58090, 58183, 58275, 58367, 58458, 58549, 58639, 58728, 58817, 58906, 58993, 59081, 59168,
59254, 59339, 59424, 59509, 59593, 59676, 59759, 59841, 59923, 60004, 60085, 60165, 60244, 60323, 60401, 60479,
60556, 60633, 60709, 60784, 60859, 60933, 61007, 61080, 61153, 61225, 61296, 61367, 61437, 61507, 61576, 61645,
61713, 61780, 61847, 61913, 61979, 62044, 62108, 62172, 62235, 62298, 62360, 62422, 62482, 62543, 62603, 62662,
62720, 62778, 62836, 62893, 62949, 63004, 63059, 63114, 63168, 63221, 63274, 63326, 63377, 63428, 63478, 63528,
63577, 63626, 63673, 63721, 63767, 63814, 63859, 63904, 63948, 63992, 64035, 64077, 64119, 64160, 64201, 64241,
64281, 64320, 64358, 64395, 64432, 64469, 64505, 64540, 64574, 64608, 64642, 64675, 64707, 64738, 64769, 64800,
64829, 64858, 64887, 64915, 64942, 64969, 64995, 65020, 65045, 65069, 65093, 65116, 65138, 65160, 65181, 65202,
65222, 65241, 65260, 65278, 65295, 65312, 65329, 65344, 65359, 65374, 65387, 65401, 65413, 65425, 65436, 65447,
65457, 65467, 65476, 65484, 65492, 65499, 65505, 65511, 65516, 65520, 65524, 65528, 65530, 65532, 65534, 65535};

const FFTComplex exptab_1[] = {/*tablica s- & gt; mdct_ctx[1].exptab dla pliku 44,1kHz lub s- & gt; mdct_ctx[0].exptab dla pliku 22kHz*/
/*re im re im re im re im */
65536, 0, 65531, 804, 65516, 1608, 65492, 2412,
65457, 3216, 65413, 4019, 65358, 4821, 65294, 5623,
65220, 6424, 65137, 7224, 65043, 8022, 64940, 8820,
64827, 9616, 64704, 10411, 64571, 11204, 64429, 11996,
64277, 12785, 64115, 13573, 63944, 14359, 63763, 15143,
63572, 15924, 63372, 16703, 63162, 17479, 62943, 18253,
62714, 19024, 62476, 19792, 62228, 20557, 61971, 21320,
61705, 22078, 61429, 22834, 61145, 23586, 60851, 24335,
60547, 25080, 60235, 25821, 59914, 26558, 59583, 27291,
59244, 28020, 58896, 28745, 58538, 29466, 58172, 30182,
57798, 30893, 57414, 31600, 57022, 32303, 56621, 33000,
56212, 33692, 55794, 34380, 55368, 35062, 54934, 35738,
54491, 36410, 54040, 37076, 53581, 37736, 53114, 38391,
52639, 39040, 52156, 39683, 51665, 40320, 51166, 40951,
50660, 41576, 50146, 42194, 49624, 42806, 49095, 43412,
48559, 44011, 48015, 44604, 47464, 45190, 46906, 45769,
46341, 46341, 45769, 46906, 45190, 47464, 44604, 48015,
44011, 48559, 43412, 49095, 42806, 49624, 42194, 50146,
41576, 50660, 40951, 51166, 40320, 51665, 39683, 52156,
39040, 52639, 38391, 53114, 37736, 53581, 37076, 54040,
36410, 54491, 35738, 54934, 35062, 55368, 34380, 55794,
33692, 56212, 33000, 56621, 32303, 57022, 31600, 57414,
30893, 57798, 30182, 58172, 29466, 58538, 28745, 58896,
28020, 59244, 27291, 59583, 26558, 59914, 25821, 60235,
25080, 60547, 24335, 60851, 23586, 61145, 22834, 61429,
22078, 61705, 21320, 61971, 20557, 62228, 19792, 62476,
19024, 62714, 18253, 62943, 17479, 63162, 16703, 63372,
15924, 63572, 15143, 63763, 14359, 63944, 13573, 64115,
12785, 64277, 11996, 64429, 11204, 64571, 10411, 64704,
9616, 64827, 8820, 64940, 8022, 65043, 7224, 65137,
6424, 65220, 5623, 65294, 4821, 65358, 4019, 65413,
3216, 65457, 2412, 65492, 1608, 65516, 804, 65531,
0, 65536, -804, 65531, -1608, 65516, -2412, 65492,
-3216, 65457, -4019, 65413, -4821, 65358, -5623, 65294,
-6424, 65220, -7224, 65137, -8022, 65043, -8820, 64940,
-9616, 64827, -10411, 64704, -11204, 64571, -11996, 64429,
-12785, 64277, -13573, 64115, -14359, 63944, -15143, 63763,
-15924, 63572, -16703, 63372, -17479, 63162, -18253, 62943,
-19024, 62714, -19792, 62476, -20557, 62228, -21320, 61971,
-22078, 61705, -22834, 61429, -23586, 61145, -24335, 60851,
-25080, 60547, -25821, 60235, -26558, 59914, -27291, 59583,
-28020, 59244, -28745, 58896, -29466, 58538, -30182, 58172,
-30893, 57798, -31600, 57414, -32303, 57022, -33000, 56621,
-33692, 56212, -34380, 55794, -35062, 55368, -35738, 54934,
-36410, 54491, -37076, 54040, -37736, 53581, -38391, 53114,
-39040, 52639, -39683, 52156, -40320, 51665, -40951, 51166,
-41576, 50660, -42194, 50146, -42806, 49624, -43412, 49095,
-44011, 48559, -44604, 48015, -45190, 47464, -45769, 46906,
-46341, 46341, -46906, 45769, -47464, 45190, -48015, 44604,
-48559, 44011, -49095, 43412, -49624, 42806, -50146, 42194,
-50660, 41576, -51166, 40951, -51665, 40320, -52156, 39683,
-52639, 39040, -53114, 38391, -53581, 37736, -54040, 37076,
-54491, 36410, -54934, 35738, -55368, 35062, -55794, 34380,
-56212, 33692, -56621, 33000, -57022, 32303, -57414, 31600,
-57798, 30893, -58172, 30182, -58538, 29466, -58896, 28745,
-59244, 28020, -59583, 27291, -59914, 26558, -60235, 25821,
-60547, 25080, -60851, 24335, -61145, 23586, -61429, 22834,
-61705, 22078, -61971, 21320, -62228, 20557, -62476, 19792,
-62714, 19024, -62943, 18253, -63162, 17479, -63372, 16703,
-63572, 15924, -63763, 15143, -63944, 14359, -64115, 13573,
-64277, 12785, -64429, 11996, -64571, 11204, -64704, 10411,
-64827, 9616, -64940, 8820, -65043, 8022, -65137, 7224,
-65220, 6424, -65294, 5623, -65358, 4821, -65413, 4019,
-65457, 3216, -65492, 2412, -65516, 1608, -65531, 804};



const uint16_t tcos_2[] = {/*tablica s- & gt; mdct_ctx[2].tcos dla pliku 44,1kHz lub s- & gt; mdct_ctx[1].tcos dla pliku 22kHz*/
65535, 65533, 65529, 65523, 65514, 65503, 65489, 65472, 65454, 65432, 65409, 65382, 65354, 65323, 65289, 65253,
65214, 65174, 65130, 65084, 65036, 64985, 64932, 64876, 64818, 64758, 64695, 64629, 64562, 64491, 64419, 64343,
64266, 64186, 64104, 64019, 63932, 63842, 63750, 63656, 63559, 63460, 63358, 63254, 63148, 63039, 62928, 62814,
62698, 62580, 62460, 62337, 62212, 62084, 61954, 61822, 61687, 61550, 61411, 61269, 61126, 60979, 60831, 60680,
60527, 60372, 60214, 60054, 59892, 59728, 59561, 59393, 59221, 59048, 58873, 58695, 58515, 58333, 58148, 57962,
57773, 57582, 57389, 57194, 56996, 56797, 56595, 56391, 56185, 55977, 55767, 55555, 55341, 55124, 54906, 54685,
54462, 54238, 54011, 53782, 53551, 53319, 53084, 52847, 52608, 52367, 52125, 51880, 51633, 51385, 51134, 50882,
50627, 50371, 50113, 49853, 49591, 49327, 49061, 48794, 48524, 48253, 47980, 47705, 47429, 47150, 46870, 46588,
46305, 46019, 45732, 45443, 45153, 44860, 44566, 44271, 43973, 43674, 43374, 43071, 42768, 42462, 42155, 41846,
41536, 41224, 40911, 40596, 40280, 39962, 39642, 39321, 38999, 38675, 38350, 38023, 37694, 37365, 37034, 36701,
36367, 36032, 35696, 35358, 35019, 34678, 34336, 33993, 33649, 33303, 32956, 32608, 32258, 31908, 31556, 31203,
30849, 30493, 30137, 29779, 29420, 29061, 28700, 28337, 27974, 27610, 27245, 26879, 26512, 26143, 25774, 25404,
25033, 24661, 24288, 23914, 23539, 23163, 22786, 22409, 22031, 21652, 21272, 20891, 20509, 20127, 19744, 19360,
18976, 18590, 18205, 17818, 17431, 17043, 16654, 16265, 15875, 15485, 15093, 14702, 14310, 13917, 13524, 13130,
12736, 12341, 11946, 11550, 11154, 10758, 10361, 9964, 9566, 9168, 8770, 8371, 7972, 7573, 7173, 6774,
6374, 5973, 5573, 5172, 4771, 4370, 3968, 3567, 3165, 2764, 2362, 1960, 1558, 1156, 754, 352};

const uint16_t tsin_2[] = {/*tablica s- & gt; mdct_ctx[2].tsin dla pliku 44,1kHz lub s- & gt; mdct_ctx[1].tsin dla pliku 22kHz*/
50, 452, 854, 1257, 1659, 2061, 2462, 2864, 3266, 3667, 4069, 4470, 4871, 5272, 5673, 6073,
6474, 6874, 7273, 7673, 8072, 8471, 8870, 9268, 9666, 10063, 10460, 10857, 11254, 11649, 12045, 12440,
12835, 13229, 13622, 14015, 14408, 14800, 15191, 15582, 15972, 16362, 16751, 17140, 17527, 17915, 18301, 18687,
19072, 19456, 19840, 20223, 20605, 20986, 21367, 21746, 22125, 22503, 22881, 23257, 23633, 24007, 24381, 24754,
25126, 25497, 25866, 26235, 26603, 26970, 27336, 27701, 28065, 28428, 28790, 29151, 29510, 29869, 30226, 30582,
30937, 31291, 31644, 31995, 32346, 32695, 33043, 33389, 33735, 34079, 34422, 34763, 35104, 35442, 35780, 36116,
36451, 36785, 37117, 37447, 37777, 38105, 38431, 38756, 39080, 39402, 39722, 40041, 40359, 40675, 40989, 41302,
41614, 41924, 42232, 42539, 42844, 43147, 43449, 43749, 44048, 44345, 44640, 44934, 45225, 45516, 45804, 46091,
46376, 46659, 46941, 47220, 47498, 47774, 48049, 48321, 48592, 48861, 49128, 49393, 49656, 49918, 50178, 50435,
50691, 50945, 51197, 51447, 51695, 51941, 52186, 52428, 52668, 52906, 53143, 53377, 53609, 53840, 54068, 54294,
54518, 54740, 54960, 55178, 55394, 55608, 55820, 56030, 56237, 56442, 56646, 56847, 57046, 57243, 57437, 57630,
57820, 58009, 58195, 58378, 58560, 58739, 58917, 59092, 59264, 59435, 59603, 59769, 59933, 60095, 60254, 60411,
60566, 60718, 60868, 61016, 61162, 61305, 61446, 61585, 61721, 61855, 61987, 62116, 62243, 62368, 62490, 62610,
62728, 62843, 62956, 63066, 63174, 63280, 63384, 63485, 63583, 63679, 63773, 63865, 63954, 64040, 64124, 64206,
64286, 64362, 64437, 64509, 64579, 64646, 64711, 64773, 64833, 64891, 64946, 64998, 65048, 65096, 65141, 65184,
65224, 65262, 65298, 65331, 65361, 65389, 65415, 65438, 65459, 65477, 65492, 65506, 65516, 65525, 65531, 65534};

const FFTComplex exptab_2[] = {/*tablica s- & gt; mdct_ctx[2].exptab dla pliku 44,1kHz lub s- & gt; mdct_ctx[1].exptab dla pliku 22kHz*/
/*re im re im re im re im */
65536, 0, 65516, 1608, 65457, 3216, 65358, 4821,
65220, 6424, 65043, 8022, 64827, 9616, 64571, 11204,
64277, 12785, 63944, 14359, 63572, 15924, 63162, 17479,
62714, 19024, 62228, 20557, 61705, 22078, 61145, 23586,
60547, 25080, 59914, 26558, 59244, 28020, 58538, 29466,
57798, 30893, 57022, 32303, 56212, 33692, 55368, 35062,
54491, 36410, 53581, 37736, 52639, 39040, 51665, 40320,
50660, 41576, 49624, 42806, 48559, 44011, 47464, 45190,
46341, 46341, 45190, 47464, 44011, 48559, 42806, 49624,
41576, 50660, 40320, 51665, 39040, 52639, 37736, 53581,
36410, 54491, 35062, 55368, 33692, 56212, 32303, 57022,
30893, 57798, 29466, 58538, 28020, 59244, 26558, 59914,
25080, 60547, 23586, 61145, 22078, 61705, 20557, 62228,
19024, 62714, 17479, 63162, 15924, 63572, 14359, 63944,
12785, 64277, 11204, 64571, 9616, 64827, 8022, 65043,
6424, 65220, 4821, 65358, 3216, 65457, 1608, 65516,
0, 65536, -1608, 65516, -3216, 65457, -4821, 65358,
-6424, 65220, -8022, 65043, -9616, 64827, -11204, 64571,
-12785, 64277, -14359, 63944, -15924, 63572, -17479, 63162,
-19024, 62714, -20557, 62228, -22078, 61705, -23586, 61145,
-25080, 60547, -26558, 59914, -28020, 59244, -29466, 58538,
-30893, 57798, -32303, 57022, -33692, 56212, -35062, 55368,
-36410, 54491, -37736, 53581, -39040, 52639, -40320, 51665,
-41576, 50660, -42806, 49624, -44011, 48559, -45190, 47464,
-46341, 46341, -47464, 45190, -48559, 44011, -49624, 42806,
-50660, 41576, -51665, 40320, -52639, 39040, -53581, 37736,
-54491, 36410, -55368, 35062, -56212, 33692, -57022, 32303,
-57798, 30893, -58538, 29466, -59244, 28020, -59914, 26558,
-60547, 25080, -61145, 23586, -61705, 22078, -62228, 20557,
-62714, 19024, -63162, 17479, -63572, 15924, -63944, 14359,
-64277, 12785, -64571, 11204, -64827, 9616, -65043, 8022,
-65220, 6424, -65358, 4821, -65457, 3216, -65516, 1608};



const uint16_t tcos_3[] = {/*tablica s- & gt; mdct_ctx[3].tcos dla pliku 44,1kHz lub s- & gt; mdct_ctx[2].tcos dla pliku 22kHz*/
65535, 65529, 65513, 65487, 65451, 65405, 65350, 65285, 65210, 65125, 65030, 64925, 64811, 64687, 64553, 64409,
64256, 64093, 63921, 63738, 63546, 63345, 63134, 62914, 62684, 62444, 62196, 61938, 61670, 61393, 61107, 60812,
60508, 60194, 59872, 59540, 59200, 58850, 58492, 58125, 57749, 57365, 56972, 56570, 56159, 55741, 55314, 54878,
54434, 53983, 53522, 53054, 52578, 52094, 51602, 51103, 50595, 50080, 49558, 49028, 48491, 47946, 47394, 46835,
46269, 45696, 45116, 44529, 43936, 43336, 42730, 42117, 41497, 40872, 40240, 39602, 38958, 38309, 37653, 36992,
36326, 35654, 34976, 34293, 33605, 32912, 32215, 31512, 30804, 30092, 29375, 28654, 27929, 27199, 26466, 25728,
24986, 24241, 23492, 22739, 21983, 21224, 20462, 19696, 18928, 18156, 17382, 16605, 15826, 15045, 14261, 13475,
12687, 11897, 11105, 10312, 9517, 8720, 7922, 7123, 6324, 5523, 4721, 3918, 3115, 2312, 1508, 704};

const uint16_t tsin_3[] = {/*tablica s- & gt; mdct_ctx[3].tsin dla pliku 44,1kHz lub s- & gt; mdct_ctx[2].tsin dla pliku 22kHz*/
101, 905, 1709, 2513, 3316, 4119, 4921, 5723, 6524, 7323, 8122, 8919, 9715, 10510, 11303, 12094,
12884, 13671, 14457, 15240, 16021, 16800, 17576, 18349, 19120, 19888, 20653, 21414, 22173, 22928, 23679, 24428,
25172, 25913, 26649, 27382, 28111, 28835, 29555, 30271, 30982, 31688, 32390, 33086, 33778, 34465, 35146, 35822,
36493, 37158, 37818, 38472, 39120, 39762, 40398, 41029, 41653, 42270, 42882, 43487, 44085, 44677, 45262, 45840,
46411, 46976, 47533, 48083, 48626, 49161, 49689, 50210, 50723, 51228, 51726, 52216, 52698, 53172, 53638, 54096,
54546, 54988, 55421, 55846, 56263, 56671, 57071, 57462, 57844, 58218, 58583, 58939, 59286, 59624, 59953, 60274,
60585, 60887, 61180, 61463, 61738, 62003, 62259, 62505, 62742, 62970, 63188, 63396, 63595, 63785, 63965, 64135,
64295, 64446, 64587, 64719, 64840, 64952, 65054, 65147, 65229, 65302, 65365, 65418, 65461, 65494, 65518, 65531};

const FFTComplex exptab_3[] = {/*tablica s- & gt; mdct_ctx[3].exptab dla pliku 44,1kHz lub s- & gt; mdct_ctx[2].exptab dla pliku 22kHz*/
/*re im re im re im re im */
65536, 0, 65457, 3216, 65220, 6424, 64827, 9616,
64277, 12785, 63572, 15924, 62714, 19024, 61705, 22078,
60547, 25080, 59244, 28020, 57798, 30893, 56212, 33692,
54491, 36410, 52639, 39040, 50660, 41576, 48559, 44011,
46341, 46341, 44011, 48559, 41576, 50660, 39040, 52639,
36410, 54491, 33692, 56212, 30893, 57798, 28020, 59244,
25080, 60547, 22078, 61705, 19024, 62714, 15924, 63572,
12785, 64277, 9616, 64827, 6424, 65220, 3216, 65457,
0, 65536, -3216, 65457, -6424, 65220, -9616, 64827,
-12785, 64277, -15924, 63572, -19024, 62714, -22078, 61705,
-25080, 60547, -28020, 59244, -30893, 57798, -33692, 56212,
-36410, 54491, -39040, 52639, -41576, 50660, -44011, 48559,
-46341, 46341, -48559, 44011, -50660, 41576, -52639, 39040,
-54491, 36410, -56212, 33692, -57798, 30893, -59244, 28020,
-60547, 25080, -61705, 22078, -62714, 19024, -63572, 15924,
-64277, 12785, -64827, 9616, -65220, 6424, -65457, 3216};




const uint16_t tcos_4[] = {/*tablica s- & gt; mdct_ctx[4].tcos dla pliku 44,1kHz lub s- & gt; mdct_ctx[3].tcos dla pliku 22kHz*/
65535, 65510, 65446, 65342, 65199, 65017, 64796, 64535, 64236, 63898, 63522, 63107, 62654, 62164, 61636, 61071,
60469, 59831, 59157, 58447, 57702, 56922, 56108, 55260, 54378, 53464, 52518, 51540, 50531, 49492, 48423, 47325,
46198, 45043, 43861, 42653, 41419, 40161, 38877, 37571, 36242, 34891, 33519, 32127, 30716, 29286, 27838, 26374,
24893, 23398, 21889, 20366, 18831, 17285, 15729, 14163, 12588, 11006, 9417, 7823, 6223, 4621, 3015, 1407};

const uint16_t tsin_4[] = {/*tablica s- & gt; mdct_ctx[4].tsin dla pliku 44,1kHz lub s- & gt; mdct_ctx[3].tsin dla pliku 22kHz*/
201, 1809, 3416, 5022, 6624, 8222, 9815, 11402, 12982, 14555, 16119, 17673, 19216, 20748, 22267, 23773,
25265, 26741, 28201, 29645, 31070, 32477, 33864, 35231, 36576, 37900, 39200, 40478, 41730, 42958, 44159, 45334,
46482, 47602, 48693, 49755, 50787, 51788, 52758, 53696, 54602, 55475, 56314, 57120, 57891, 58628, 59329, 59994,
60623, 61216, 61772, 62290, 62771, 63214, 63620, 63986, 64315, 64604, 64855, 65066, 65239, 65372, 65466, 65520};

const FFTComplex exptab_4[] = {/*tablica s- & gt; mdct_ctx[4].exptab dla pliku 44,1kHz lub s- & gt; mdct_ctx[3].exptab dla pliku 22kHz*/
/*re im re im re im re im */
65536, 0, 65220, 6424, 64277, 12785, 62714, 19024,
60547, 25080, 57798, 30893, 54491, 36410, 50660, 41576,
46341, 46341, 41576, 50660, 36410, 54491, 30893, 57798,
25080, 60547, 19024, 62714, 12785, 64277, 6424, 65220,
0, 65536, -6424, 65220, -12785, 64277, -19024, 62714,
-25080, 60547, -30893, 57798, -36410, 54491, -41576, 50660,
-46341, 46341, -50660, 41576, -54491, 36410, -57798, 30893,
-60547, 25080, -62714, 19024, -64277, 12785, -65220, 6424};




const uint16_t window_0[] = { /*tablica s- & gt; window[0] dla pliku 44,1kHz (niewykorzystywana dla pliku 22kHz) */
65535, 65535, 65535, 65535, 65535, 65534, 65534, 65534, 65534, 65533, 65533, 65532, 65532, 65531, 65531, 65530,
65530, 65529, 65528, 65528, 65527, 65526, 65525, 65524, 65523, 65522, 65521, 65520, 65519, 65518, 65517, 65516,
65515, 65513, 65512, 65511, 65509, 65508, 65506, 65505, 65503, 65502, 65500, 65499, 65497, 65495, 65493, 65492,
65490, 65488, 65486, 65484, 65482, 65480, 65478, 65476, 65473, 65471, 65469, 65467, 65464, 65462, 65460, 65457,
65455, 65452, 65450, 65447, 65445, 65442, 65439, 65436, 65434, 65431, 65428, 65425, 65422, 65419, 65416, 65413,
65410, 65407, 65404, 65401, 65397, 65394, 65391, 65387, 65384, 65381, 65377, 65374, 65370, 65367, 65363, 65359,
65356, 65352, 65348, 65344, 65340, 65337, 65333, 65329, 65325, 65321, 65316, 65312, 65308, 65304, 65300, 65295,
65291, 65287, 65282, 65278, 65274, 65269, 65265, 65260, 65255, 65251, 65246, 65241, 65236, 65232, 65227, 65222,
65217, 65212, 65207, 65202, 65197, 65192, 65187, 65181, 65176, 65171, 65166, 65160, 65155, 65149, 65144, 65138,
65133, 65127, 65122, 65116, 65110, 65105, 65099, 65093, 65087, 65081, 65075, 65069, 65063, 65057, 65051, 65045,
65039, 65033, 65027, 65020, 65014, 65008, 65001, 64995, 64988, 64982, 64975, 64969, 64962, 64956, 64949, 64942,
64935, 64929, 64922, 64915, 64908, 64901, 64894, 64887, 64880, 64873, 64866, 64858, 64851, 64844, 64837, 64829,
64822, 64815, 64807, 64800, 64792, 64785, 64777, 64769, 64762, 64754, 64746, 64738, 64731, 64723, 64715, 64707,
64699, 64691, 64683, 64675, 64666, 64658, 64650, 64642, 64634, 64625, 64617, 64608, 64600, 64592, 64583, 64574,
64566, 64557, 64549, 64540, 64531, 64522, 64514, 64505, 64496, 64487, 64478, 64469, 64460, 64451, 64442, 64432,
64423, 64414, 64405, 64395, 64386, 64377, 64367, 64358, 64348, 64339, 64329, 64320, 64310, 64300, 64290, 64281,
64271, 64261, 64251, 64241, 64231, 64221, 64211, 64201, 64191, 64181, 64171, 64160, 64150, 64140, 64130, 64119,
64109, 64098, 64088, 64077, 64067, 64056, 64046, 64035, 64024, 64013, 64003, 63992, 63981, 63970, 63959, 63948,
63937, 63926, 63915, 63904, 63893, 63881, 63870, 63859, 63848, 63836, 63825, 63814, 63802, 63791, 63779, 63767,
63756, 63744, 63732, 63721, 63709, 63697, 63685, 63673, 63662, 63650, 63638, 63626, 63614, 63601, 63589, 63577,
63565, 63553, 63540, 63528, 63516, 63503, 63491, 63478, 63466, 63453, 63441, 63428, 63415, 63403, 63390, 63377,
63364, 63352, 63339, 63326, 63313, 63300, 63287, 63274, 63261, 63247, 63234, 63221, 63208, 63194, 63181, 63168,
63154, 63141, 63127, 63114, 63100, 63087, 63073, 63059, 63046, 63032, 63018, 63004, 62991, 62977, 62963, 62949,
62935, 62921, 62907, 62893, 62878, 62864, 62850, 62836, 62821, 62807, 62793, 62778, 62764, 62749, 62735, 62720,
62706, 62691, 62676, 62662, 62647, 62632, 62617, 62603, 62588, 62573, 62558, 62543, 62528, 62513, 62498, 62482,
62467, 62452, 62437, 62422, 62406, 62391, 62375, 62360, 62345, 62329, 62313, 62298, 62282, 62267, 62251, 62235,
62219, 62204, 62188, 62172, 62156, 62140, 62124, 62108, 62092, 62076, 62060, 62044, 62027, 62011, 61995, 61979,
61962, 61946, 61929, 61913, 61896, 61880, 61863, 61847, 61830, 61813, 61797, 61780, 61763, 61746, 61729, 61713,
61696, 61679, 61662, 61645, 61628, 61610, 61593, 61576, 61559, 61542, 61524, 61507, 61490, 61472, 61455, 61437,
61420, 61402, 61385, 61367, 61349, 61332, 61314, 61296, 61278, 61261, 61243, 61225, 61207, 61189, 61171, 61153,
61135, 61117, 61098, 61080, 61062, 61044, 61025, 61007, 60989, 60970, 60952, 60933, 60915, 60896, 60878, 60859,
60840, 60822, 60803, 60784, 60765, 60746, 60728, 60709, 60690, 60671, 60652, 60633, 60614, 60594, 60575, 60556,
60537, 60518, 60498, 60479, 60460, 60440, 60421, 60401, 60382, 60362, 60343, 60323, 60303, 60284, 60264, 60244,
60224, 60204, 60185, 60165, 60145, 60125, 60105, 60085, 60065, 60044, 60024, 60004, 59984, 59964, 59943, 59923,
59903, 59882, 59862, 59841, 59821, 59800, 59780, 59759, 59738, 59718, 59697, 59676, 59655, 59635, 59614, 59593,
59572, 59551, 59530, 59509, 59488, 59467, 59446, 59424, 59403, 59382, 59361, 59339, 59318, 59297, 59275, 59254,
59232, 59211, 59189, 59168, 59146, 59124, 59103, 59081, 59059, 59037, 59015, 58993, 58972, 58950, 58928, 58906,
58884, 58862, 58839, 58817, 58795, 58773, 58751, 58728, 58706, 58684, 58661, 58639, 58616, 58594, 58571, 58549,
58526, 58504, 58481, 58458, 58435, 58413, 58390, 58367, 58344, 58321, 58298, 58275, 58252, 58229, 58206, 58183,
58160, 58137, 58113, 58090, 58067, 58044, 58020, 57997, 57973, 57950, 57927, 57903, 57879, 57856, 57832, 57809,
57785, 57761, 57737, 57714, 57690, 57666, 57642, 57618, 57594, 57570, 57546, 57522, 57498, 57474, 57450, 57425,
57401, 57377, 57353, 57328, 57304, 57279, 57255, 57231, 57206, 57181, 57157, 57132, 57108, 57083, 57058, 57034,
57009, 56984, 56959, 56934, 56909, 56884, 56859, 56834, 56809, 56784, 56759, 56734, 56709, 56684, 56658, 56633,
56608, 56582, 56557, 56532, 56506, 56481, 56455, 56430, 56404, 56379, 56353, 56327, 56301, 56276, 56250, 56224,
56198, 56172, 56147, 56121, 56095, 56069, 56043, 56017, 55990, 55964, 55938, 55912, 55886, 55859, 55833, 55807,
55780, 55754, 55728, 55701, 55675, 55648, 55621, 55595, 55568, 55542, 55515, 55488, 55461, 55435, 55408, 55381,
55354, 55327, 55300, 55273, 55246, 55219, 55192, 55165, 55138, 55111, 55083, 55056, 55029, 55001, 54974, 54947,
54919, 54892, 54864, 54837, 54809, 54782, 54754, 54727, 54699, 54671, 54643, 54616, 54588, 54560, 54532, 54504,
54476, 54448, 54420, 54392, 54364, 54336, 54308, 54280, 54252, 54224, 54195, 54167, 54139, 54110, 54082, 54054,
54025, 53997, 53968, 53940, 53911, 53883, 53854, 53825, 53797, 53768, 53739, 53710, 53682, 53653, 53624, 53595,
53566, 53537, 53508, 53479, 53450, 53421, 53392, 53362, 53333, 53304, 53275, 53245, 53216, 53187, 53157, 53128,
53099, 53069, 53040, 53010, 52980, 52951, 52921, 52892, 52862, 52832, 52802, 52773, 52743, 52713, 52683, 52653,
52623, 52593, 52563, 52533, 52503, 52473, 52443, 52413, 52383, 52352, 52322, 52292, 52262, 52231, 52201, 52170,
52140, 52109, 52079, 52048, 52018, 51987, 51957, 51926, 51895, 51865, 51834, 51803, 51772, 51741, 51711, 51680,
51649, 51618, 51587, 51556, 51525, 51494, 51463, 51431, 51400, 51369, 51338, 51307, 51275, 51244, 51213, 51181,
51150, 51118, 51087, 51056, 51024, 50992, 50961, 50929, 50898, 50866, 50834, 50802, 50771, 50739, 50707, 50675,
50643, 50611, 50579, 50547, 50515, 50483, 50451, 50419, 50387, 50355, 50323, 50291, 50258, 50226, 50194, 50161,
50129, 50097, 50064, 50032, 49999, 49967, 49934, 49902, 49869, 49836, 49804, 49771, 49738, 49706, 49673, 49640,
49607, 49574, 49542, 49509, 49476, 49443, 49410, 49377, 49344, 49310, 49277, 49244, 49211, 49178, 49145, 49111,
49078, 49045, 49011, 48978, 48945, 48911, 48878, 48844, 48811, 48777, 48743, 48710, 48676, 48643, 48609, 48575,
48541, 48508, 48474, 48440, 48406, 48372, 48338, 48304, 48270, 48236, 48202, 48168, 48134, 48100, 48066, 48032,
47997, 47963, 47929, 47895, 47860, 47826, 47792, 47757, 47723, 47688, 47654, 47619, 47585, 47550, 47515, 47481,
47446, 47412, 47377, 47342, 47307, 47272, 47238, 47203, 47168, 47133, 47098, 47063, 47028, 46993, 46958, 46923,
46888, 46853, 46818, 46782, 46747, 46712, 46677, 46641, 46606, 46571, 46535, 46500, 46464, 46429, 46394, 46358,
46322, 46287, 46251, 46216, 46180, 46144, 46109, 46073, 46037, 46001, 45966, 45930, 45894, 45858, 45822, 45786,
45750, 45714, 45678, 45642, 45606, 45570, 45534, 45498, 45461, 45425, 45389, 45353, 45316, 45280, 45244, 45207,
45171, 45134, 45098, 45061, 45025, 44988, 44952, 44915, 44879, 44842, 44805, 44769, 44732, 44695, 44658, 44622,
44585, 44548, 44511, 44474, 44437, 44400, 44363, 44326, 44289, 44252, 44215, 44178, 44141, 44104, 44066, 44029,
43992, 43955, 43917, 43880, 43843, 43805, 43768, 43731, 43693, 43656, 43618, 43581, 43543, 43505, 43468, 43430,
43393, 43355, 43317, 43279, 43242, 43204, 43166, 43128, 43090, 43053, 43015, 42977, 42939, 42901, 42863, 42825,
42787, 42749, 42710, 42672, 42634, 42596, 42558, 42520, 42481, 42443, 42405, 42366, 42328, 42290, 42251, 42213,
42174, 42136, 42097, 42059, 42020, 41982, 41943, 41904, 41866, 41827, 41788, 41750, 41711, 41672, 41633, 41594,
41556, 41517, 41478, 41439, 41400, 41361, 41322, 41283, 41244, 41205, 41166, 41127, 41087, 41048, 41009, 40970,
40931, 40891, 40852, 40813, 40773, 40734, 40695, 40655, 40616, 40576, 40537, 40497, 40458, 40418, 40379, 40339,
40299, 40260, 40220, 40180, 40141, 40101, 40061, 40021, 39982, 39942, 39902, 39862, 39822, 39782, 39742, 39702,
39662, 39622, 39582, 39542, 39502, 39462, 39422, 39381, 39341, 39301, 39261, 39221, 39180, 39140, 39100, 39059,
39019, 38979, 38938, 38898, 38857, 38817, 38776, 38736, 38695, 38655, 38614, 38573, 38533, 38492, 38451, 38411,
38370, 38329, 38288, 38248, 38207, 38166, 38125, 38084, 38043, 38002, 37961, 37920, 37879, 37838, 37797, 37756,
37715, 37674, 37633, 37592, 37550, 37509, 37468, 37427, 37385, 37344, 37303, 37262, 37220, 37179, 37137, 37096,
37055, 37013, 36972, 36930, 36888, 36847, 36805, 36764, 36722, 36680, 36639, 36597, 36555, 36514, 36472, 36430,
36388, 36347, 36305, 36263, 36221, 36179, 36137, 36095, 36053, 36011, 35969, 35927, 35885, 35843, 35801, 35759,
35717, 35675, 35632, 35590, 35548, 35506, 35464, 35421, 35379, 35337, 35294, 35252, 35210, 35167, 35125, 35082,
35040, 34997, 34955, 34912, 34870, 34827, 34785, 34742, 34699, 34657, 34614, 34571, 34529, 34486, 34443, 34400,
34358, 34315, 34272, 34229, 34186, 34143, 34100, 34057, 34015, 33972, 33929, 33886, 33842, 33799, 33756, 33713,
33670, 33627, 33584, 33541, 33498, 33454, 33411, 33368, 33325, 33281, 33238, 33195, 33151, 33108, 33065, 33021,
32978, 32934, 32891, 32847, 32804, 32760, 32717, 32673, 32630, 32586, 32542, 32499, 32455, 32411, 32368, 32324,
32280, 32236, 32193, 32149, 32105, 32061, 32017, 31974, 31930, 31886, 31842, 31798, 31754, 31710, 31666, 31622,
31578, 31534, 31490, 31446, 31402, 31357, 31313, 31269, 31225, 31181, 31137, 31092, 31048, 31004, 30959, 30915,
30871, 30826, 30782, 30738, 30693, 30649, 30604, 30560, 30516, 30471, 30427, 30382, 30337, 30293, 30248, 30204,
30159, 30114, 30070, 30025, 29980, 29936, 29891, 29846, 29802, 29757, 29712, 29667, 29622, 29577, 29533, 29488,
29443, 29398, 29353, 29308, 29263, 29218, 29173, 29128, 29083, 29038, 28993, 28948, 28903, 28858, 28812, 28767,
28722, 28677, 28632, 28587, 28541, 28496, 28451, 28405, 28360, 28315, 28269, 28224, 28179, 28133, 28088, 28043,
27997, 27952, 27906, 27861, 27815, 27770, 27724, 27679, 27633, 27587, 27542, 27496, 27451, 27405, 27359, 27314,
27268, 27222, 27176, 27131, 27085, 27039, 26993, 26948, 26902, 26856, 26810, 26764, 26718, 26672, 26626, 26580,
26535, 26489, 26443, 26397, 26351, 26305, 26258, 26212, 26166, 26120, 26074, 26028, 25982, 25936, 25890, 25843,
25797, 25751, 25705, 25658, 25612, 25566, 25520, 25473, 25427, 25381, 25334, 25288, 25242, 25195, 25149, 25102,
25056, 25009, 24963, 24917, 24870, 24824, 24777, 24730, 24684, 24637, 24591, 24544, 24498, 24451, 24404, 24358,
24311, 24264, 24218, 24171, 24124, 24077, 24031, 23984, 23937, 23890, 23843, 23797, 23750, 23703, 23656, 23609,
23562, 23515, 23468, 23421, 23375, 23328, 23281, 23234, 23187, 23140, 23093, 23045, 22998, 22951, 22904, 22857,
22810, 22763, 22716, 22669, 22621, 22574, 22527, 22480, 22433, 22385, 22338, 22291, 22244, 22196, 22149, 22102,
22054, 22007, 21960, 21912, 21865, 21818, 21770, 21723, 21675, 21628, 21580, 21533, 21485, 21438, 21390, 21343,
21295, 21248, 21200, 21153, 21105, 21058, 21010, 20962, 20915, 20867, 20819, 20772, 20724, 20676, 20629, 20581,
20533, 20486, 20438, 20390, 20342, 20294, 20247, 20199, 20151, 20103, 20055, 20007, 19960, 19912, 19864, 19816,
19768, 19720, 19672, 19624, 19576, 19528, 19480, 19432, 19384, 19336, 19288, 19240, 19192, 19144, 19096, 19048,
19000, 18952, 18904, 18855, 18807, 18759, 18711, 18663, 18615, 18566, 18518, 18470, 18422, 18373, 18325, 18277,
18229, 18180, 18132, 18084, 18035, 17987, 17939, 17890, 17842, 17794, 17745, 17697, 17649, 17600, 17552, 17503,
17455, 17406, 17358, 17309, 17261, 17212, 17164, 17115, 17067, 17018, 16970, 16921, 16873, 16824, 16776, 16727,
16678, 16630, 16581, 16532, 16484, 16435, 16386, 16338, 16289, 16240, 16192, 16143, 16094, 16046, 15997, 15948,
15899, 15851, 15802, 15753, 15704, 15655, 15607, 15558, 15509, 15460, 15411, 15362, 15314, 15265, 15216, 15167,
15118, 15069, 15020, 14971, 14922, 14873, 14824, 14775, 14726, 14677, 14628, 14579, 14530, 14481, 14432, 14383,
14334, 14285, 14236, 14187, 14138, 14089, 14040, 13991, 13942, 13893, 13843, 13794, 13745, 13696, 13647, 13598,
13548, 13499, 13450, 13401, 13352, 13302, 13253, 13204, 13155, 13106, 13056, 13007, 12958, 12908, 12859, 12810,
12761, 12711, 12662, 12613, 12563, 12514, 12465, 12415, 12366, 12317, 12267, 12218, 12168, 12119, 12070, 12020,
11971, 11921, 11872, 11823, 11773, 11724, 11674, 11625, 11575, 11526, 11476, 11427, 11377, 11328, 11278, 11229,
11179, 11130, 11080, 11031, 10981, 10932, 10882, 10832, 10783, 10733, 10684, 10634, 10584, 10535, 10485, 10436,
10386, 10336, 10287, 10237, 10187, 10138, 10088, 10038, 9989, 9939, 9889, 9840, 9790, 9740, 9691, 9641,
9591, 9541, 9492, 9442, 9392, 9342, 9293, 9243, 9193, 9143, 9094, 9044, 8994, 8944, 8894, 8845,
8795, 8745, 8695, 8645, 8596, 8546, 8496, 8446, 8396, 8346, 8296, 8247, 8197, 8147, 8097, 8047,
7997, 7947, 7897, 7848, 7798, 7748, 7698, 7648, 7598, 7548, 7498, 7448, 7398, 7348, 7298, 7248,
7198, 7148, 7099, 7049, 6999, 6949, 6899, 6849, 6799, 6749, 6699, 6649, 6599, 6549, 6499, 6449,
6399, 6349, 6298, 6248, 6198, 6148, 6098, 6048, 5998, 5948, 5898, 5848, 5798, 5748, 5698, 5648,
5598, 5548, 5498, 5447, 5397, 5347, 5297, 5247, 5197, 5147, 5097, 5047, 4996, 4946, 4896, 4846,
4796, 4746, 4696, 4646, 4595, 4545, 4495, 4445, 4395, 4345, 4295, 4244, 4194, 4144, 4094, 4044,
3994, 3943, 3893, 3843, 3793, 3743, 3693, 3642, 3592, 3542, 3492, 3442, 3391, 3341, 3291, 3241,
3191, 3140, 3090, 3040, 2990, 2939, 2889, 2839, 2789, 2739, 2688, 2638, 2588, 2538, 2488, 2437,
2387, 2337, 2287, 2236, 2186, 2136, 2086, 2035, 1985, 1935, 1885, 1834, 1784, 1734, 1684, 1633,
1583, 1533, 1483, 1432, 1382, 1332, 1282, 1231, 1181, 1131, 1081, 1030, 980, 930, 880, 829,
779, 729, 679, 628, 578, 528, 478, 427, 377, 327, 276, 226, 176, 126, 75, 25};


const uint16_t window_1[] = { /*tablica s- & gt; window[1] dla pliku 44,1kHz lub s- & gt; window[0] dla pliku 22kHz */
65535, 65535, 65535, 65534, 65533, 65533, 65532, 65531, 65529, 65528, 65526, 65525, 65523, 65521, 65519, 65516,
65514, 65511, 65509, 65506, 65503, 65499, 65496, 65492, 65489, 65485, 65481, 65477, 65472, 65468, 65463, 65459,
65454, 65448, 65443, 65438, 65432, 65427, 65421, 65415, 65409, 65402, 65396, 65389, 65382, 65375, 65368, 65361,
65354, 65346, 65338, 65331, 65323, 65314, 65306, 65298, 65289, 65280, 65271, 65262, 65253, 65244, 65234, 65224,
65214, 65204, 65194, 65184, 65174, 65163, 65152, 65141, 65130, 65119, 65108, 65096, 65084, 65072, 65060, 65048,
65036, 65024, 65011, 64998, 64985, 64972, 64959, 64946, 64932, 64918, 64905, 64891, 64876, 64862, 64848, 64833,
64818, 64803, 64788, 64773, 64758, 64742, 64727, 64711, 64695, 64679, 64662, 64646, 64629, 64613, 64596, 64579,
64562, 64544, 64527, 64509, 64491, 64473, 64455, 64437, 64419, 64400, 64381, 64362, 64343, 64324, 64305, 64286,
64266, 64246, 64226, 64206, 64186, 64166, 64145, 64124, 64104, 64083, 64062, 64040, 64019, 63997, 63976, 63954,
63932, 63909, 63887, 63865, 63842, 63819, 63796, 63773, 63750, 63727, 63703, 63679, 63656, 63632, 63607, 63583,
63559, 63534, 63509, 63485, 63460, 63434, 63409, 63384, 63358, 63332, 63306, 63280, 63254, 63228, 63201, 63174,
63148, 63121, 63094, 63066, 63039, 63011, 62984, 62956, 62928, 62900, 62871, 62843, 62814, 62786, 62757, 62728,
62698, 62669, 62640, 62610, 62580, 62550, 62520, 62490, 62460, 62429, 62399, 62368, 62337, 62306, 62274, 62243,
62212, 62180, 62148, 62116, 62084, 62052, 62019, 61987, 61954, 61921, 61888, 61855, 61822, 61788, 61755, 61721,
61687, 61653, 61619, 61585, 61550, 61516, 61481, 61446, 61411, 61376, 61340, 61305, 61269, 61234, 61198, 61162,
61126, 61089, 61053, 61016, 60979, 60943, 60905, 60868, 60831, 60793, 60756, 60718, 60680, 60642, 60604, 60566,
60527, 60489, 60450, 60411, 60372, 60333, 60293, 60254, 60214, 60175, 60135, 60095, 60054, 60014, 59974, 59933,
59892, 59851, 59810, 59769, 59728, 59687, 59645, 59603, 59561, 59519, 59477, 59435, 59393, 59350, 59307, 59264,
59221, 59178, 59135, 59092, 59048, 59004, 58961, 58917, 58873, 58828, 58784, 58739, 58695, 58650, 58605, 58560,
58515, 58470, 58424, 58378, 58333, 58287, 58241, 58195, 58148, 58102, 58055, 58009, 57962, 57915, 57868, 57820,
57773, 57725, 57678, 57630, 57582, 57534, 57486, 57437, 57389, 57340, 57292, 57243, 57194, 57145, 57095, 57046,
56996, 56947, 56897, 56847, 56797, 56747, 56696, 56646, 56595, 56544, 56493, 56442, 56391, 56340, 56289, 56237,
56185, 56134, 56082, 56030, 55977, 55925, 55873, 55820, 55767, 55714, 55661, 55608, 55555, 55502, 55448, 55394,
55341, 55287, 55233, 55178, 55124, 55070, 55015, 54960, 54906, 54851, 54796, 54740, 54685, 54630, 54574, 54518,
54462, 54406, 54350, 54294, 54238, 54181, 54125, 54068, 54011, 53954, 53897, 53840, 53782, 53725, 53667, 53609,
53551, 53493, 53435, 53377, 53319, 53260, 53202, 53143, 53084, 53025, 52966, 52906, 52847, 52788, 52728, 52668,
52608, 52548, 52488, 52428, 52367, 52307, 52246, 52186, 52125, 52064, 52003, 51941, 51880, 51819, 51757, 51695,
51633, 51571, 51509, 51447, 51385, 51322, 51260, 51197, 51134, 51071, 51008, 50945, 50882, 50818, 50755, 50691,
50627, 50563, 50499, 50435, 50371, 50307, 50242, 50178, 50113, 50048, 49983, 49918, 49853, 49787, 49722, 49656,
49591, 49525, 49459, 49393, 49327, 49261, 49194, 49128, 49061, 48995, 48928, 48861, 48794, 48727, 48659, 48592,
48524, 48457, 48389, 48321, 48253, 48185, 48117, 48049, 47980, 47912, 47843, 47774, 47705, 47636, 47567, 47498,
47429, 47359, 47290, 47220, 47150, 47081, 47011, 46941, 46870, 46800, 46730, 46659, 46588, 46518, 46447, 46376,
46305, 46233, 46162, 46091, 46019, 45948, 45876, 45804, 45732, 45660, 45588, 45516, 45443, 45371, 45298, 45225,
45153, 45080, 45007, 44934, 44860, 44787, 44714, 44640, 44566, 44493, 44419, 44345, 44271, 44197, 44122, 44048,
43973, 43899, 43824, 43749, 43674, 43599, 43524, 43449, 43374, 43298, 43223, 43147, 43071, 42996, 42920, 42844,
42768, 42691, 42615, 42539, 42462, 42385, 42309, 42232, 42155, 42078, 42001, 41924, 41846, 41769, 41691, 41614,
41536, 41458, 41380, 41302, 41224, 41146, 41068, 40989, 40911, 40832, 40754, 40675, 40596, 40517, 40438, 40359,
40280, 40200, 40121, 40041, 39962, 39882, 39802, 39722, 39642, 39562, 39482, 39402, 39321, 39241, 39160, 39080,
38999, 38918, 38837, 38756, 38675, 38594, 38512, 38431, 38350, 38268, 38186, 38105, 38023, 37941, 37859, 37777,
37694, 37612, 37530, 37447, 37365, 37282, 37199, 37117, 37034, 36951, 36868, 36785, 36701, 36618, 36535, 36451,
36367, 36284, 36200, 36116, 36032, 35948, 35864, 35780, 35696, 35611, 35527, 35442, 35358, 35273, 35188, 35104,
35019, 34934, 34848, 34763, 34678, 34593, 34507, 34422, 34336, 34251, 34165, 34079, 33993, 33907, 33821, 33735,
33649, 33562, 33476, 33389, 33303, 33216, 33130, 33043, 32956, 32869, 32782, 32695, 32608, 32521, 32433, 32346,
32258, 32171, 32083, 31995, 31908, 31820, 31732, 31644, 31556, 31468, 31380, 31291, 31203, 31114, 31026, 30937,
30849, 30760, 30671, 30582, 30493, 30404, 30315, 30226, 30137, 30047, 29958, 29869, 29779, 29690, 29600, 29510,
29420, 29331, 29241, 29151, 29061, 28970, 28880, 28790, 28700, 28609, 28519, 28428, 28337, 28247, 28156, 28065,
27974, 27883, 27792, 27701, 27610, 27519, 27428, 27336, 27245, 27154, 27062, 26970, 26879, 26787, 26695, 26603,
26512, 26420, 26328, 26235, 26143, 26051, 25959, 25866, 25774, 25682, 25589, 25497, 25404, 25311, 25218, 25126,
25033, 24940, 24847, 24754, 24661, 24567, 24474, 24381, 24288, 24194, 24101, 24007, 23914, 23820, 23726, 23633,
23539, 23445, 23351, 23257, 23163, 23069, 22975, 22881, 22786, 22692, 22598, 22503, 22409, 22315, 22220, 22125,
22031, 21936, 21841, 21746, 21652, 21557, 21462, 21367, 21272, 21177, 21081, 20986, 20891, 20796, 20700, 20605,
20509, 20414, 20318, 20223, 20127, 20031, 19936, 19840, 19744, 19648, 19552, 19456, 19360, 19264, 19168, 19072,
18976, 18879, 18783, 18687, 18590, 18494, 18398, 18301, 18205, 18108, 18011, 17915, 17818, 17721, 17624, 17527,
17431, 17334, 17237, 17140, 17043, 16946, 16848, 16751, 16654, 16557, 16459, 16362, 16265, 16167, 16070, 15972,
15875, 15777, 15680, 15582, 15485, 15387, 15289, 15191, 15093, 14996, 14898, 14800, 14702, 14604, 14506, 14408,
14310, 14212, 14113, 14015, 13917, 13819, 13721, 13622, 13524, 13425, 13327, 13229, 13130, 13032, 12933, 12835,
12736, 12637, 12539, 12440, 12341, 12243, 12144, 12045, 11946, 11847, 11748, 11649, 11550, 11452, 11353, 11254,
11154, 11055, 10956, 10857, 10758, 10659, 10560, 10460, 10361, 10262, 10163, 10063, 9964, 9865, 9765, 9666,
9566, 9467, 9367, 9268, 9168, 9069, 8969, 8870, 8770, 8670, 8571, 8471, 8371, 8272, 8172, 8072,
7972, 7873, 7773, 7673, 7573, 7473, 7373, 7273, 7173, 7074, 6974, 6874, 6774, 6674, 6574, 6474,
6374, 6273, 6173, 6073, 5973, 5873, 5773, 5673, 5573, 5472, 5372, 5272, 5172, 5072, 4971, 4871,
4771, 4671, 4570, 4470, 4370, 4269, 4169, 4069, 3968, 3868, 3768, 3667, 3567, 3467, 3366, 3266,
3165, 3065, 2965, 2864, 2764, 2663, 2563, 2462, 2362, 2261, 2161, 2061, 1960, 1860, 1759, 1659,
1558, 1458, 1357, 1257, 1156, 1056, 955, 854, 754, 653, 553, 452, 352, 251, 151, 50};



const uint16_t window_2[] = { /*tablica s- & gt; window[2] dla pliku 44,1kHz lub s- & gt; window[1] dla pliku 22kHz */
65535, 65534, 65533, 65531, 65529, 65526, 65522, 65518, 65513, 65507, 65501, 65494, 65487, 65479, 65470, 65461,
65451, 65441, 65429, 65418, 65405, 65392, 65379, 65365, 65350, 65335, 65319, 65302, 65285, 65267, 65248, 65229,
65210, 65189, 65168, 65147, 65125, 65102, 65078, 65054, 65030, 65005, 64979, 64952, 64925, 64898, 64869, 64840,
64811, 64781, 64750, 64719, 64687, 64654, 64621, 64587, 64553, 64518, 64482, 64446, 64409, 64372, 64334, 64295,
64256, 64216, 64176, 64135, 64093, 64051, 64008, 63965, 63921, 63876, 63831, 63785, 63738, 63691, 63644, 63595,
63546, 63497, 63447, 63396, 63345, 63293, 63241, 63188, 63134, 63080, 63025, 62970, 62914, 62857, 62800, 62742,
62684, 62625, 62565, 62505, 62444, 62383, 62321, 62259, 62196, 62132, 62068, 62003, 61938, 61872, 61805, 61738,
61670, 61602, 61533, 61463, 61393, 61323, 61252, 61180, 61107, 61034, 60961, 60887, 60812, 60737, 60661, 60585,
60508, 60430, 60352, 60274, 60194, 60115, 60034, 59953, 59872, 59790, 59707, 59624, 59540, 59456, 59371, 59286,
59200, 59113, 59026, 58939, 58850, 58762, 58672, 58583, 58492, 58401, 58310, 58218, 58125, 58032, 57938, 57844,
57749, 57654, 57558, 57462, 57365, 57267, 57169, 57071, 56972, 56872, 56772, 56671, 56570, 56468, 56366, 56263,
56159, 56056, 55951, 55846, 55741, 55635, 55528, 55421, 55314, 55206, 55097, 54988, 54878, 54768, 54657, 54546,
54434, 54322, 54210, 54096, 53983, 53868, 53754, 53638, 53522, 53406, 53289, 53172, 53054, 52936, 52817, 52698,
52578, 52458, 52337, 52216, 52094, 51972, 51849, 51726, 51602, 51478, 51354, 51228, 51103, 50977, 50850, 50723,
50595, 50467, 50339, 50210, 50080, 49951, 49820, 49689, 49558, 49426, 49294, 49161, 49028, 48894, 48760, 48626,
48491, 48355, 48219, 48083, 47946, 47809, 47671, 47533, 47394, 47255, 47116, 46976, 46835, 46694, 46553, 46411,
46269, 46126, 45983, 45840, 45696, 45552, 45407, 45262, 45116, 44970, 44824, 44677, 44529, 44382, 44234, 44085,
43936, 43787, 43637, 43487, 43336, 43185, 43034, 42882, 42730, 42577, 42424, 42270, 42117, 41962, 41808, 41653,
41497, 41341, 41185, 41029, 40872, 40714, 40557, 40398, 40240, 40081, 39922, 39762, 39602, 39442, 39281, 39120,
38958, 38797, 38634, 38472, 38309, 38145, 37982, 37818, 37653, 37489, 37324, 37158, 36992, 36826, 36660, 36493,
36326, 36158, 35990, 35822, 35654, 35485, 35315, 35146, 34976, 34806, 34635, 34465, 34293, 34122, 33950, 33778,
33605, 33433, 33260, 33086, 32912, 32738, 32564, 32390, 32215, 32039, 31864, 31688, 31512, 31335, 31159, 30982,
30804, 30627, 30449, 30271, 30092, 29913, 29734, 29555, 29375, 29196, 29015, 28835, 28654, 28473, 28292, 28111,
27929, 27747, 27565, 27382, 27199, 27016, 26833, 26649, 26466, 26281, 26097, 25913, 25728, 25543, 25358, 25172,
24986, 24800, 24614, 24428, 24241, 24054, 23867, 23679, 23492, 23304, 23116, 22928, 22739, 22551, 22362, 22173,
21983, 21794, 21604, 21414, 21224, 21034, 20843, 20653, 20462, 20271, 20079, 19888, 19696, 19504, 19312, 19120,
18928, 18735, 18542, 18349, 18156, 17963, 17769, 17576, 17382, 17188, 16994, 16800, 16605, 16411, 16216, 16021,
15826, 15631, 15436, 15240, 15045, 14849, 14653, 14457, 14261, 14064, 13868, 13671, 13475, 13278, 13081, 12884,
12687, 12489, 12292, 12094, 11897, 11699, 11501, 11303, 11105, 10907, 10708, 10510, 10312, 10113, 9914, 9715,
9517, 9318, 9118, 8919, 8720, 8521, 8321, 8122, 7922, 7723, 7523, 7323, 7123, 6924, 6724, 6524,
6324, 6123, 5923, 5723, 5523, 5322, 5122, 4921, 4721, 4520, 4320, 4119, 3918, 3718, 3517, 3316,
3115, 2914, 2714, 2513, 2312, 2111, 1910, 1709, 1508, 1307, 1106, 905, 704, 503, 302, 101};



const uint16_t window_3[] = { /*tablica s- & gt; window[3] dla pliku 44,1kHz lub s- & gt; window[2] dla pliku 22kHz */
65535, 65532, 65527, 65520, 65510, 65498, 65483, 65466, 65446, 65424, 65399, 65372, 65342, 65310, 65276, 65239,
65199, 65158, 65113, 65066, 65017, 64966, 64911, 64855, 64796, 64734, 64671, 64604, 64535, 64464, 64391, 64315,
64236, 64155, 64072, 63986, 63898, 63808, 63715, 63620, 63522, 63422, 63319, 63214, 63107, 62998, 62886, 62771,
62654, 62535, 62414, 62290, 62164, 62035, 61905, 61772, 61636, 61498, 61358, 61216, 61071, 60924, 60775, 60623,
60469, 60313, 60155, 59994, 59831, 59666, 59498, 59329, 59157, 58983, 58806, 58628, 58447, 58264, 58079, 57891,
57702, 57510, 57316, 57120, 56922, 56721, 56519, 56314, 56108, 55899, 55688, 55475, 55260, 55042, 54823, 54602,
54378, 54153, 53925, 53696, 53464, 53231, 52995, 52758, 52518, 52277, 52033, 51788, 51540, 51291, 51040, 50787,
50531, 50274, 50016, 49755, 49492, 49228, 48961, 48693, 48423, 48151, 47877, 47602, 47325, 47046, 46765, 46482,
46198, 45912, 45624, 45334, 45043, 44750, 44456, 44159, 43861, 43562, 43261, 42958, 42653, 42347, 42039, 41730,
41419, 41107, 40793, 40478, 40161, 39842, 39522, 39200, 38877, 38553, 38227, 37900, 37571, 37241, 36909, 36576,
36242, 35906, 35569, 35231, 34891, 34550, 34208, 33864, 33519, 33173, 32826, 32477, 32127, 31776, 31424, 31070,
30716, 30360, 30003, 29645, 29286, 28925, 28564, 28201, 27838, 27473, 27108, 26741, 26374, 26005, 25635, 25265,
24893, 24521, 24147, 23773, 23398, 23022, 22645, 22267, 21889, 21509, 21129, 20748, 20366, 19984, 19600, 19216,
18831, 18446, 18060, 17673, 17285, 16897, 16508, 16119, 15729, 15338, 14947, 14555, 14163, 13770, 13376, 12982,
12588, 12193, 11798, 11402, 11006, 10609, 10212, 9815, 9417, 9019, 8620, 8222, 7823, 7423, 7024, 6624,
6223, 5823, 5422, 5022, 4621, 4219, 3818, 3416, 3015, 2613, 2211, 1809, 1407, 1005, 603, 201};



const uint16_t window_4[] = { /*tablica s- & gt; window[4] dla pliku 44,1kHz lub s- & gt; window[3] dla pliku 22kHz */
65534, 65524, 65504, 65475, 65435, 65386, 65327, 65258, 65179, 65090, 64992, 64883, 64765, 64638, 64500, 64353,
64196, 64030, 63853, 63668, 63472, 63267, 63053, 62829, 62595, 62352, 62100, 61838, 61567, 61287, 60998, 60699,
60391, 60075, 59749, 59414, 59070, 58717, 58356, 57985, 57606, 57218, 56822, 56417, 56003, 55582, 55151, 54713,
54266, 53811, 53348, 52877, 52398, 51911, 51416, 50913, 50403, 49885, 49360, 48827, 48287, 47740, 47185, 46624,
46055, 45479, 44897, 44308, 43712, 43109, 42500, 41885, 41263, 40635, 40001, 39361, 38715, 38064, 37406, 36743,
36074, 35400, 34721, 34036, 33346, 32651, 31952, 31247, 30538, 29824, 29106, 28383, 27656, 26925, 26189, 25450,
24707, 23960, 23210, 22456, 21699, 20939, 20175, 19408, 18639, 17866, 17091, 16313, 15533, 14751, 13966, 13179,
12391, 11600, 10808, 10014, 9218, 8421, 7623, 6824, 6023, 5222, 4420, 3617, 2814, 2010, 1206, 402};



const int32_t noise_table002[] = {/*tablica s- & gt; noise_table dla noise_mult == 0x51F (= s- & gt; noise_table(float) * 65536) */
0, 93, -195, -180, 1300, 90, 128, -364, 400, 459, -1822, -919, 1856, -59, -1379, 970,
-1330, 1310, -1739, -619, -2172, -542, -2049, -475, 438, 1258, 895, 1281, 24, 20, 1865, 902,
-1012, -94, -885, 1796, -2175, -542, 1766, -1930, -2039, -2148, 855, -1066, 51, 1134, -584, -1383,
-2265, 1227, 1703, 777, -1363, 327, -2146, 2039, -36, -1006, -1475, -1762, 419, -2154, 1395, -254,
-1498, -730, -1453, 1387, -115, 36, 2010, -2236, 2095, 2086, 1188, -1418, 1884, 612, 2027, -1431,
-1930, -617, -1935, 1879, -1083, -1176, 514, 1093, 2269, 2259, 233, 1624, -1613, -546, -2189, 718,
31, 102, 1861, -1763, -109, -800, 79, -1639, 672, 1456, -1601, 2212, -236, 289, 1133, 473,
1165, 2235, 190, -2206, 157, 1404, 608, 875, -239, -653, 696, 2004, -42, 2219, -588, -1076,
525, -223, -804, 1073, -668, -1136, -267, -491, -279, -2123, 786, 388, -278, 2081, 495, -568,
-570, -1924, -1784, 1787, -694, 902, 1897, 1029, -1531, 1256, -864, -977, 2080, -1024, 878, -1452,
1473, 209, -1147, 460, -303, 945, 192, 851, 732, -2195, -1512, 1836, -1294, -1178, -670, -368,
-1106, -2097, 443, -117, -2146, -766, -939, 1201, -115, 818, -688, 1406, 1705, 721, 1429, -764,
-174, -1225, 50, 582, -2064, -1723, 676, 2034, 655, -1385, -193, 1661, -1792, 1509, 1401, 720,
1048, -908, 1550, 808, 1832, -1685, 399, 1035, 958, -50, 443, -281, 320, 289, 284, 634,
1613, 1930, 2008, 1085, 80, 1857, 404, -1839, 979, 2224, -579, -491, -285, -1564, 1385, -2202,
-1700, -984, 758, -333, -892, 61, 592, 178, -1364, 567, 1750, -1852, -583, -405, 1203, -2155,
-757, -2032, -595, 1615, -1463, -22, -1405, -2040, -1346, 1464, 1090, -436, 179, 600, -1497, -405,
1221, -407, 1826, 644, 253, 1847, -1142, -1726, -1050, 45, -2089, 877, 485, 555, -1135, -403,
-1254, -2114, 543, 1817, -663, -904, -989, 1075, -290, -1747, -506, 1473, 1089, 835, 1056, 1214,
2220, -1804, -567, -1154, 2217, 1047, -1043, -491, -1150, 299, 1768, -1529, 474, 544, 1571, 994,
1613, -942, 101, 1336, -570, 1128, 870, -1928, 1097, -955, -1608, 340, -607, 1056, -820, -2240,
-1753, 1281, 1880, -1542, 1947, -422, 110, -1011, -174, -1297, -1082, -343, 872, 1476, -540, 1682,
253, -1139, 1837, -183, 306, -1093, -1149, 2215, -237, 1216, 1545, 351, 1124, -1361, 1178, -2041,
-129, 1684, -694, -875, 936, -646, 1536, 897, -1174, 1714, 2203, -461, -1369, 729, 832, 1305,
694, -792, 433, 1446, -1086, -1110, 1255, -469, 1740, 2141, -909, 1150, -1312, 39, 1729, 1458,
-497, 1320, 11, 492, 671, -2248, -2087, 341, 1881, 2167, 1761, -2237, -221, 216, 366, -491,
-112, 2016, -353, 1328, 1285, -1549, -1778, -1256, -564, -805, -669, -2156, -1883, -1908, 52, -1181,
-1369, 2104, -1326, 2205, -1897, 1226, 2084, 1505, 1400, 1977, 1353, -1487, 1267, 1853, 1823, 480,
-676, 120, -1301, -892, -173, -493, -1950, -501, -1119, -1166, 1485, -842, 901, -747, -94, -1230,
-1253, 1411, -944, -631, -737, -1928, -355, -506, -1126, -1482, 197, 1437, 43, -1524, -120, -678,
491, -25, 1350, -1029, 570, -569, -39, 1443, 1565, -1568, 231, 197, -552, 897, 513, 956,
1338, 1157, 375, 709, 1098, -716, -1101, -1507, 331, -1752, 2055, 1637, 2139, 1080, -1700, 222,
339, -1044, -2263, 564, 465, 141, -1368, -320, -103, -94, -671, 606, -211, 399, 1090, 481,
-1185, -1283, 1852, 1331, 559, 2239, -936, -1851, -1819, -1460, 1605, -1239, -38, -2041, 841, -1716,
358, -1021, 703, -1009, 1000, -990, -2175, -1604, -92, 631, -2000, 31, -1128, -325, 859, 1531,
1749, 547, -1834, 880, -864, -228, -641, -1894, -1545, 1311, -1934, 1533, -456, 110, 2182, 2234,
2038, 1959, 386, -1562, -874, -2046, 1299, 1776, -1453, -2019, 3, -1884, -1811, 640, -962, -789,
-1993, -518, 2157, -1000, -1682, -1663, -994, -1990, -1899, -605, -260, 518, -2167, 368, 1544, -1904,
-2213, 732, 545, -1450, 872, -1111, -807, 385, 1843, -1587, 18, -952, -771, 669, -612, 2248,
-1839, 1976, -576, -121, -405, -150, 1763, 2046, -1390, -752, 1306, -97, 860, 648, -1854, -863,
-1823, 1752, 401, -1028, -1353, -810, -193, -1591, 2207, -698, 1804, -2069, -1060, 1679, 1128, 1205,
-841, 866, -1732, -1380, -83, 1688, -2231, 779, 1471, -1755, 1983, -669, 1034, -1675, 289, 461,
157, -2145, -828, -651, -1517, 772, -2179, 33, 1128, -1978, 41, -1049, -1186, 1043, -1063, 268,
-2049, -1934, -2092, -590, 774, 1223, -135, -1605, -906, -1698, 990, -1551, -155, -145, -1890, 1715,
675, 37, 620, -673, 1868, 1011, 1535, 362, 95, 1029, -1511, 1754, 339, 677, 1116, -917,
569, 33, 2104, 1893, -886, 373, -1809, -922, 2048, 1334, 2088, 1443, -1218, -1928, -88, -1998,
1223, 1132, -577, -1449, 1211, 1821, 1087, -959, 599, 1159, 907, 1444, 466, -2043, -2196, 1835,
-581, -399, 995, 1175, 968, 1053, 1046, -2065, -1797, 176, -44, -1125, -665, -566, 372, -1951,
-1251, -1484, -658, 1207, -1997, 578, 239, 257, -411, 326, 1976, 2206, 684, -662, 1841, -912,
533, -1315, -1660, 1441, -1255, 637, -1431, -850, -1870, 1283, -1645, -526, -1545, 1314, -1290, 1502,
-717, -1356, -405, -2140, -1727, -802, -1791, -887, -1446, 447, 914, -853, -2058, 2195, -1173, -430,
861, -799, -2099, -2204, -1524, 1041, -939, -2170, -1223, 2031, 1043, -1657, 2170, 1087, -1313, -1076,
-224, -1108, -597, 1775, -1028, -404, -1242, -204, -1015, -1104, 1482, 991, -1729, -636, 1601, -1616,
1891, -1476, -1104, -1033, 1650, -359, 1741, -1842, 1635, -205, -1840, -332, -1650, 670, -477, -959,
1716, 1175, -2015, -1024, 1588, -854, 1104, 1951, -2169, 2129, -1642, -1696, -1380, 1840, 302, -283,
573, -1430, 545, 57, 676, -1649, 1289, -219, -888, 1030, -1994, -1445, 2105, 1977, 436, 1500,
2054, -1672, -899, -1809, -1469, -235, -72, 683, 1122, -1560, -156, -189, 478, -2083, -1309, -1328,
-1602, 1255, 2068, 713, 1584, -912, 1464, -2197, 1779, -1428, -199, -811, 1305, -2156, 646, 1405,
-2262, 1347, 1971, -936, 372, -1172, -1010, 178, 1268, -1174, 618, 617, 797, -1408, 527, -563,
1395, -589, -1856, 579, 1324, -775, 1487, 951, 2045, -1124, -1776, 1214, 1979, -734, -627, -1599,
-660, -1474, 1273, 1240, -481, -1751, 2048, 80, -243, 662, -99, 368, 1064, 1241, 491, 1656,
1974, -503, 1614, -699, 1386, 680, 576, -211, 1401, -683, 1576, -263, 1076, -921, 377, 1214,
-732, 862, 769, -175, 2003, -55, -757, 35, -1919, 1323, 1451, -1291, -1770, -1303, -2200, 434,
1624, -1114, -1924, 1065, -1281, 826, -2048, -1497, 1335, 1811, -5, -1058, 88, -802, -1662, 408,
-988, 1188, -322, -996, 233, 1291, -1125, -311, 2268, -1817, -51, -175, -1676, 1957, 757, -43,
1834, -505, 371, 975, -647, 1580, 1914, 1278, -1203, -807,