MAX5054-MAX5057.pdf

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19-3348; Rev 0; 8/04

4A, 20ns, Dual MOSFET Drivers

The MAX5054-MAX5057 dual, high-speed MOSFET
drivers source and sink up to 4A peak current. These
devices feature a fast 20ns propagation delay and 20ns
rise and fall times while driving a 5000pF capacitive
load. Propagation delay time is minimized and matched
between the inverting and noninverting inputs and
between channels. High sourcing/sinking peak currents, low propagation delay, and thermally enhanced
packages make the MAX5054-MAX5057 ideal for highfrequency and high-power circuits.
The MAX5054-MAX5057 operate from a 4V to 15V single
power supply and consume 40uA (typ) of supply current
when not switching. These devices have internal logic
circuitry that prevents shoot-through during output state
changes to minimize the operating current at high
switching frequency. The logic inputs are protected
against voltage spikes up to +18V, regardless of the VDD
voltage. The MAX5054A is the only version that has
CMOS input logic levels while the MAX5054B/MAX5055/
MAX5056/MAX5057 have TTL input logic levels.
The MAX5055-MAX5057 provide the combination of dual
inverting, dual noninverting, and inverting/noninverting
input drivers. The MAX5054 feature both inverting and
noninverting inputs per driver for greater flexibility. They
are available in 8-pin TDFN (3mm x 3mm), standard SO,
and thermally enhanced SO packages. These devices
operate over the automotive temperature range of -40C
to +125C.

Applications

Features
? 4V to 15V Single Power Supply
? 4A Peak Source/Sink Drive Current
? 20ns (typ) Propagation Delay
? Matching Delay Between Inverting and
Noninverting Inputs
? Matching Propagation Delay Between Two
Channels
? VDD / 2 CMOS Logic Inputs (MAX5054AATA)
? TTL Logic Inputs
(MAX5054B/MAX5055/MAX5056/MAX5057)
? 0.1 x VDD (CMOS) and 0.3V (TTL) Logic-Input
Hysteresis
? Up to +18V Logic Inputs (Regardless of VDD
Voltage)
? Low Input Capacitance: 2.5pF (typ)
? 40uA (typ) Quiescent Current
? -40C to +125C Operating Temperature Range
? 8-Pin TDFN and SO Packages

Ordering Information
PART

TEMP RANGE

PINPACKAGE

TOP
MARK

Power MOSFET Switching

Motor Control

MAX5054AATA

-40C to +125C

8 TDFN-EP*

AGS

Switch-Mode Power Supplies

Power-Supply Modules

MAX5054BATA

-40C to +125C

8 TDFN-EP*

AGR

MAX5055AASA

Typical Operating Circuit

-40C to +125C

8 SO-EP*

MAX5055BASA

-40C to +125C

8 SO

--

MAX5056AASA

DC-DC Converters

-40C to +125C

8 SO-EP*

--

--

MAX5056BASA

-40C to +125C

8 SO

--

MAX5057AASA

-40C to +125C

8 SO-EP*

--

MAX5057BASA

VOUT

VIN

-40C to +125C

8 SO

--

*EP = Exposed pad. Package code S8E-14.

MAX5054
VDD
INA+

Selector Guide and Pin Configurations appear at end of
data sheet.

OUTA
INA-

INB+
OUTB
PWM IN

INBGND

________________________________________________________________ Maxim Integrated Products

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.

1

MAX5054-MAX5057

General Description

MAX5054-MAX5057

4A, 20ns, Dual MOSFET Drivers
ABSOLUTE MAXIMUM RATINGS
8-Pin SO-EP (derate 19.2mW/C above +70C)... ........1538mW
Junction-to-Case Thermal Resistance (?JC) ......................6C/W
8-Pin SO (derate 5.9mW/C above +70C)... ..................471mW
Junction-to-Case Thermal Resistance (?JC) ....................40C/W
Operating Temperature Range..............................-40C to +125C
Storage Temperature Range .................................-65C to +150C
Junction Temperature ...........................................................+150C
Lead Temperature (soldering, 10s)......................................+300C

(Voltages referenced to GND.)
VDD...............................................................................-0.3V to +18V
INA+, INA-, INB+, INB- ...............................................-0.3V to +18V
OUTA, OUTB...................................................-0.3V to (VDD + 0.3V)
OUTA, OUTB Short-Circuit Duration ........................................10ms
Continuous Source/Sink Current at OUT_ (PD & lt; PDMAX) .....200mA
Continuous Power Dissipation (TA = +70C)
8-Pin TDFN-EP (derate 24.4mW/C above +70C)........1951mW
Junction-to-Case Thermal Resistance (?JC) ......................2C/W

Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
(VDD = 4V to 15V, TA = -40C to +125C, unless otherwise noted. Typical values are at VDD = 15V and TA = +25C.) (Note 1)
PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

15

V

3.50

3.85

V

POWER SUPPLY
VDD Operating Range
VDD Undervoltage Lockout

VDD
UVLO

4
VDD rising

3.00

VDD Undervoltage Lockout
Hysteresis

200

VDD Undervoltage Lockout to
Output Delay

12

VDD rising

IDD

INA- = INB- = VDD,
INA+ = INB+ = 0V
(not switching)

mV
us

VDD = 4V

28

55

VDD = 15V

40

75

2.4

4

uA

VDD Supply Current
IDD-SW

INA- = 0V, INB+ = VDD = 15V,
INA+ = INB- both channels switching at
250kHz, CL = 0

1

mA

DRIVER OUTPUT (SINK)
Driver Output Resistance Pulling
Down
Peak Output Current (Sinking)

RON-N

IPK-N

Output-Voltage Low
Latchup Protection

VDD = 15V,
IOUT_ = -100mA

TA = +25C

1.1

1.8

TA = +125C

1.5

2.4

VDD = 4.5V,
IOUT_ = -100mA

TA = +25C

2.2

3.3

TA = +125C

3.0

4.5

VDD = 15V, CL = 10,000pF
IOUT_ = -100mA

ILUP

4

A

VDD = 4.5V

0.45

VDD = 15V

0.24

Reverse current IOUT_ (Note 2)

Ohm

400

V
mA

DRIVER OUTPUT (SOURCE)
Driver Output Resistance Pulling
Up
Peak Output Current (Sourcing)

2

RON-P

IPK-P

VDD = 15V,
IOUT_ = 100mA

TA = +25C

1.5

2.1

VDD = 4.5V,
IOUT_ = 100mA

TA = +125C

1.9

2.75

TA = +25C

2.75

4

TA = +125C

3.75

5.5

VDD = 15V, CL = 10,000pF

4

_______________________________________________________________________________________

Ohm

A

4A, 20ns, Dual MOSFET Drivers

(VDD = 4V to 15V, TA = -40C to +125C, unless otherwise noted. Typical values are at VDD = 15V and TA = +25C.) (Note 1)
PARAMETER

SYMBOL

CONDITIONS

MIN

VDD = 4.5V
VDD = 15V

Output-Voltage High

TYP

MAX

UNITS

VDD 0.55
VDD 0.275

V

IOUT_ = 100mA

LOGIC INPUT (Note 3)
MAX5054A
Logic 1 Input Voltage

Logic 0 Input Voltage

VIH

VIL

MAX5054B/MAX5055/MAX5056/MAX5057
(Note 4)

0.7 x
VDD

V

2.1
0.3 x
VDD

MAX5054A
MAX5054B/MAX5055/MAX5056/MAX5057

Logic-Input Hysteresis

VHYS

0.1 x
VDD

MAX5054A
MAX5054B/MAX5055/MAX5056/MAX5057

Logic-Input-Current Leakage
Input Capacitance

INA+, INB+, INA-, INB- = 0V or VDD

V

0.8
V

0.3
-1

CIN

+0.1

+1

2.5

uA
pF

SWITCHING CHARACTERISTICS FOR VDD = 15V (Figure 1)
CL = 1000pF

tF

32
4

CL = 5000pF

15

CL = 10,000pF

OUT_ Fall Time

18

CL = 1000pF

tR

CL = 5000pF
CL = 10,000pF

OUT_ Rise Time

4

26

ns

ns

Turn-On Delay Time

tD-ON

CL = 10,000pF (Note 2)

10

20

34

ns

Turn-Off Delay Time

tD-OFF

CL = 10,000pF (Note 2)

10

20

34

ns

SWITCHING CHARACTERISTICS FOR VDD = 4.5V (Figure 1)
CL = 1000pF

tF

85
7

CL = 5000pF

30

CL = 10,000pF

OUT_ Fall Time

37

CL = 1000pF

tR

CL = 5000pF
CL = 10,000pF

OUT_ Rise Time

7

75

ns

ns

Turn-On Delay Time

tD-ON

CL = 10,000pF (Note 2)

18

35

70

ns

Turn-Off Delay Time

tD-OFF

CL = 10,000pF (Note 2)

18

35

70

ns

_______________________________________________________________________________________

3

MAX5054-MAX5057

ELECTRICAL CHARACTERISTICS (continued)

ELECTRICAL CHARACTERISTICS (continued)
(VDD = 4V to 15V, TA = -40C to +125C, unless otherwise noted. Typical values are at VDD = 15V and TA = +25C.) (Note 1)
PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

MATCHING CHARACTERISTICS
Mismatch Propagation Delays from
Inverting and Noninverting Inputs
to Output

?tON-OFF

Mismatch Propagation Delays
Between Channel A and Channel B

?tA-B

VDD = 15V, CL = 10,000pF

2

VDD = 4.5V, CL = 10,000pF

4

VDD = 15V, CL = 10,000pF

1

VDD = 4.5V, CL = 10,000pF

2

ns

ns

All devices are 100% tested at TA = +25C. Specifications over -40C to +125C are guaranteed by design.
Limits are guaranteed by design, not production tested.
The logic-input thresholds are tested at VDD = 4V and VDD = 15V.
TTL compatible with reduced noise immunity.

Note 1:
Note 2:
Note 3:
Note 4:

Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)

20

40
30

TA = +25C

20

10

10
0
10

12

14

6

8

10

12

14

16

4

IDD-SW SUPPLY CURRENT
vs. SUPPLY VOLTAGE

6

SUPPLY VOLTAGE (V)

TA = +25C

30
20

TA = -40C

10

4

500kHz

2
1

10

80

MAX5054 toc03

70
1MHz

60
50

500kHz

40
30
50kHz

100kHz

0

0
8

16

10

0
6

14

DUTY CYCLE = 50%
VDD = 15V, CL = 4700pF
1 CHANNEL SWITCHING

90

20

50kHz

100kHz

12

SUPPLY CURRENT vs. SUPPLY VOLTAGE

1MHz

3

10

100

SUPPLY CURRENT (mA)

40

DUTY CYCLE = 50%
VDD = 15V, CL = 0
1 CHANNEL SWITCHING

5

8

SUPPLY VOLTAGE (V)

MAX5054 toc05

TA = +125C

6
IDD-SW SUPPLY CURRENT (mA)

MAX5054 toc04

60

12

SUPPLY VOLTAGE (V)

4

TA = -40C

0
4

16

PROPAGATION DELAY TIME,
HIGH-TO-LOW vs. SUPPLY VOLTAGE
(CL = 5000pF)

4

20

MAX5054 toc06

8

SUPPLY VOLTAGE (V)

50

TA = +25C
30

TA = -40C

0
6

40

10

TA = -40C
4

TA = +125C

50
PROPAGATION DELAY (ns)

TA = +25C

30

50
TA = +125C

40

60

MAX5054 toc02

TA = +125C

FALL TIME (ns)

RISE TIME (ns)

50

60

MAX5054 toc01

60

PROPAGATION DELAY TIME,
LOW-TO-HIGH vs. SUPPLY VOLTAGE
(CL = 5000pF)

FALL TIME vs. SUPPLY VOLTAGE
(CL = 5000pF)

RISE TIME vs. SUPPLY VOLTAGE
(CL = 5000pF)

PROPAGATION DELAY (ns)

MAX5054-MAX5057

4A, 20ns, Dual MOSFET Drivers

14

16

4

6

8

10

12

SUPPLY VOLTAGE (V)

14

16

4

6

8

10

12

SUPPLY VOLTAGE (V)

_______________________________________________________________________________________

14

16

4A, 20ns, Dual MOSFET Drivers

2.5
2.0
1.5

MAX5054AATA
(CMOS INPUT)

9
8
7

VIN RISING

6
5
4
VIN FALLING

3
2

3.0
INPUT THRESHOLD VOLTAGE (V)

3.0

10

MAX5054 toc08

VDD = 15V,
f = 250kHz, CL = 0
DUTY CYCLE = 50%
BOTH CHANNELS SWITCHING

INPUT THRESHOLD VOLTAGE (V)

SUPPLY CURRENT (mA)

MAX5054 toc07

4.0
3.5

INPUT THRESHOLD VOLTAGE
vs. SUPPLY VOLTAGE

INPUT THRESHOLD VOLTAGE
vs. SUPPLY VOLTAGE

MAX5054 toc09

IDD-SW SUPPLY CURRENT
vs. TEMPERATURE

TTL INPUT VERSIONS

2.5
VIN RISING

2.0
1.5
1.0

VIN FALLING
0.5

1
1.0

0

0
-50

-25

0

25

50

75

100

125

4

6

8

10

12

6

4

16

14

8

10

12

14

TEMPERATURE (C)

SUPPLY VOLTAGE (V)

SUPPLY CURRENT vs. LOGIC-INPUT
VOLTAGE (INPUT LOW-TO-HIGH)

SUPPLY CURRENT vs. LOGIC-INPUT
VOLTAGE (INPUT HIGH-TO-LOW)

SUPPLY CURRENT vs. LOGIC-INPUT
VOLTAGE (INPUT LOW-TO-HIGH)

300

200

MAX5054AATA (CMOS INPUT)
VDD = 15V
4
SUPPLY CURRENT (mA)

400

300

200

100

100

2

4

6

8

10

12

14

0

16

3

2

1

0

0

MAX5054 toc12

TTL INPUT VERSIONS
VDD = 15V
SUPPLY CURRENT (uA)

400

5

MAX5054 toc11

TTL INPUT VERSIONS
VDD = 15V
SUPPLY CURRENT (uA)

500

MAX5054 toc10

500

0

16

SUPPLY VOLTAGE (V)

2

4

6

8

10

12

14

0

16

0

2

4

6

8

10

12

14

16

LOGIC-INPUT VOLTAGE (V)

LOGIC-INPUT VOLTAGE (V)

LOGIC-INPUT VOLTAGE (V)

SUPPLY CURRENT vs. LOGIC-INPUT
VOLTAGE (INPUT HIGH-TO-LOW)

DELAY MISMATCH BETWEEN IN_+
AND IN_- TO OUT_ vs. TEMPERATURE

DELAY MISMATCH BETWEEN IN_+
AND IN_- TO OUT_ vs. TEMPERATURE

3

2

1

2

-2
-4

0

OUTPUT RISING

0

2

4

6

8

10

12

LOGIC-INPUT VOLTAGE (V)

14

16

OUTPUT RISING

2
0
-2

OUTPUT FALLING

-4

MAX5054AATA (CMOS INPUT)
VDD = 4.5V, CL = 10,000pF

-6
0

4
DELAY MISMATCH (ns)

4

MAX5054 toc15

OUTPUT FALLING
DELAY MISMATCH (ns)

4

6

MAX5054 toc14

MAX5054AATA (CMOS INPUT)
VDD = +15V
SUPPLY CURRENT (mA)

6

MAX5054 toc13

5

MAX5054AATA (CMOS INPUT)
VDD = 15V, CL = 10,000pF

-6
-50

-25

0

25

50

75

TEMPERATURE (C)

100

125

-50

-25

0

25

50

75

100

125

TEMPERATURE (C)

_______________________________________________________________________________________

5

MAX5054-MAX5057

Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)

Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)

DELAY MISMATCH BETWEEN 2 CHANNELS
vs. TEMPERATURE

DELAY MISMATCH BETWEEN 2 CHANNELS
vs. TEMPERATURE
3

1
0
-1

VDD = 15V, CL = 10,000pF
3
DELAY MISMATCH (ns)

OUTPUT FALLING

OUTPUT RISING

MAX5054 toc17

VDD = 4.5V, CL = 10,000pF
2

4

MAX5054 toc16

4

DELAY MISMATCH (ns)

MAX5054-MAX5057

4A, 20ns, Dual MOSFET Drivers

OUTPUT RISING

2
1
0
-1

-2
-3

OUTPUT FALLING

-2
-3
-4

-4
-50

-25

0

25

50

75

100

-50

125

-25

0

25

50

75

100

125

TEMPERATURE (C)

TEMPERATURE (C)

LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE
(VDD = 4V, CL = 5000pF)
MAX5054 toc18

LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE
(VDD = 4V, CL = 10,000pF)
MAX5054 toc19

IN_2V/div

IN_2V/div

OUT_
2V/div

MAX5055 (TTL INPUT)

OUT_
2V/div

MAX5055 (TTL INPUT)

20ns/div

40ns/div

LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE
(VDD = 4V, CL = 5000pF)

LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE
(VDD = 4V, CL = 10,000pF)
MAX5054 toc21

MAX5054 toc20

IN_2V/div

IN_2V/div

OUT_
2V/div
OUT_
2V/div
MAX5055 (TTL INPUT)
20ns/div

6

MAX5055 (TTL INPUT)
40ns/div

_______________________________________________________________________________________

4A, 20ns, Dual MOSFET Drivers

LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE
(VDD = 15V, CL = 5000pF)
MAX5054 toc22

LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE
(VDD = 15V, CL = 10,000pF)
MAX5054 toc23

IN_2V/div

IN_2V/div

OUT_
5V/div

OUT_
5V/div

MAX5055

MAX5055

20ns/div

40ns/div

LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE
(VDD = 15V, CL = 5000pF)
MAX5054 toc24

LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE
(VDD = 15V, CL = 10,000pF)
MAX5054 toc25

IN_2V/div

IN_2V/div

OUT_
5V/div

OUT_
5V/div

MAX5055

MAX5055
20ns/div

40ns/div

VDD vs. OUTPUT VOLTAGE

VDD vs. OUTPUT VOLTAGE

MAX5054 toc26

MAX5054 toc27

VDD
5V/div
OUTA
5V/div

MAX5055
INA- = INB- = GND
CLA = CLB = 10,000pF

VDD
5V/div
OUTA
5V/div

OUTB
5V/div

MAX5055
INA- = INB- = GND
CLA = CLB = 10,000pF
2ms/div

OUTB
5V/div
2ms/div

_______________________________________________________________________________________

7

MAX5054-MAX5057

Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)

MAX5054-MAX5057

4A, 20ns, Dual MOSFET Drivers
Pin Descriptions
MAX5054
PIN

NAME

1

INA-

Inverting Logic-Input Terminal for Driver A. Connect to GND when not used.

2

INB-

Inverting Logic-Input Terminal for Driver B. Connect to GND when not used.

3

GND

Ground

4

OUTB

5

VDD

6

OUTA

Driver A Output. Sources or sinks current for channel A to turn the external MOSFET on or off.

7

INB+

Noninverting Logic-Input Terminal for Driver B. Connect to VDD when not used.

8

INA+

--

EP

FUNCTION

Driver B Output. Sources or sinks current for channel B to turn the external MOSFET on or off.
Power Supply. Bypass to GND with one or more 0.1uF ceramic capacitors.

Noninverting Logic-Input Terminal for Driver A. Connect to VDD when not used.
Exposed Pad. Internally connected to GND. Do not use the exposed pad as the only electrical
ground connection.

MAX5055/MAX5056/MAX5057
PIN

NAME

FUNCTION

MAX5055

MAX5056

MAX5057

1, 8

1, 8

1, 8

N.C.

No Connection. Not internally connected.

2

--

2

INA-

Inverting Logic-Input Terminal for Driver A. Connect to GND if not used.

3

3

3

GND

Ground

4

--

--

INB-

Inverting Logic-Input Terminal for Driver B. Connect to GND if not used.

5

5

5

OUTB

Driver B Output. Sources or sinks current for channel B to turn the external
MOSFET on or off.

6

6

6

VDD

Power Supply. Bypass to GND with one or more 0.1uF ceramic capacitors.

7

7

7

OUTA

Driver A Output. Sources or sinks current for channel A to turn the external
MOSFET on or off.

--

4

4

INB+

Noninverting Logic-Input Terminal for Driver B. Connect to VDD if not used.

--

2

--

INA+

--

8

--

--

EP

Noninverting Logic-Input Terminal for Driver A. Connect to VDD if not used.
Exposed Pad. Internally connected to GND. Do not use the exposed pad as
the only electrical ground connection.

_______________________________________________________________________________________

4A, 20ns, Dual MOSFET Drivers
MAX5054-MAX5057

IN_+

VIH
VIL

VDD

MAX5055
MAX5056
MAX5057

90%
OUT_
tD-OFF1

tD-ON1

IN_+

tF
IN_-

P
BREAKBEFOREMAKE
CONTROL

10%
tR

OUT_
N

VIH
VIL
tD-OFF2

tD-ON2

GND
RISING MISMATCH = tD-ON2 - tD-ON1
FALLING MISMATCH = tD-OFF2 - tD-OFF1

NONINVERTING INPUT DRIVER

Figure 1. Timing Diagram

VDD

MAX5055
MAX5056
MAX5057

VDD

MAX5054
IN_-

P
BREAKBEFOREMAKE
CONTROL

IN_+

P
BREAKBEFOREMAKE
CONTROL

IN_OUT_

OUT_
N

N
GND
GND
INVERTING INPUT DRIVER

Figure 2. MAX5054 Block Diagram (1 Driver)

Detailed Description
VDD Undervoltage Lockout (UVLO)
The MAX5054-MAX5057 have internal undervoltage
lockout for VDD. When VDD is below the UVLO threshold, OUT_ is low, independent of the state of the inputs.
The undervoltage lockout is typically 3.5V with 200mV
typical hysteresis to avoid chattering. When VDD rises
above the UVLO threshold, the outputs go high or low
depending upon the logic-input levels. Bypass VDD
using low-ESR ceramic capacitors for proper operation
(see the Applications Information section).

Figure 3. MAX5055/MAX5056/MAX5057 Functional Diagrams
(1 Driver)

Logic Inputs
The MAX5054B-MAX5057 have TTL-compatible logic
inputs, while the MAX5054A is a CMOS logic-input driver. The logic-input signals can be independent of the
VDD voltage. For example, the device can be powered
by a 5V supply while the logic inputs are provided from
CMOS logic. Also, the logic inputs are protected against
the voltage spikes up to 18V, regardless of the VDD voltage. The TTL and CMOS logic inputs have 300mV and
0.1 x VDD hysteresis, respectively, to avoid possible double pulsing during transition. The low 2.5pF input capacitance reduces loading and increases switching speed.

_______________________________________________________________________________________

9

MAX5054-MAX5057

4A, 20ns, Dual MOSFET Drivers
Table 1. MAX5054 Truth Table
INA+/INB+

INA-/INB-

OUTA/OUTB

Low

Low

Low

Low

High

Low

High

Low

High

High

High

VDD

Low

Table 2. MAX5055/MAX5056/MAX5057
Truth Table

MAX5054A
PWM
INPUT

INA+

OFF
ON

INA-

OUTA

GND

NONINVERTING
IN_+

OUT_

Low

Low

High

High
INVERTING

IN_-

OUT_

Low

High

High

Low

The logic inputs are high impedance and must not be left
floating. If the inputs are left open, OUT_ can go to an
undefined state as soon as VDD rises above the UVLO
threshold. Therefore, the PWM output from the controller
must assume proper state when powering up the device.
The MAX5054 has two logic inputs per driver providing
greater flexibility in controlling the MOSFET. Use IN_+ for
noninverting logic and IN_- for inverting logic operation.
Connect IN_+ to V DD and IN_- to GND if not used.
Alternatively, the unused input can be used as an
ON/OFF function. Use IN_+ for active-low shutdown logic
and IN_- for active-high shutdown logic (see Figure 4).
See Table 1 for all possible input combinations.

Driver Output
The MAX5054-MAX5057 have low RDS(ON) p-channel
and n-channel devices (totem pole) in the output stage
for the fast turn-on and turn-off high gate-charge switching MOSFETs. The peak source or sink current is typically
4A. The OUT_ voltage is approximately equal to VDD
when in high state and is ground when in low state. The
driver R DS(ON) is lower at higher V DD , thus higher
source-/sink-current capability and faster switching
speeds. The propagation delays from the noninverting
and inverting logic inputs to outputs are matched to 2ns.
The break-before-make logic avoids any cross-conduction between the internal p- and n-channel devices, and
eliminates shoot-through currents reducing the quiescent
supply current.

10

Figure 4. Unused Input as an ON/OFF Function (1/2 MAX5054A)

Applications Information
RLC Series Circuit
The driver's RDS(ON) (RON), internal bond and lead
inductance (LP), trace inductance (LS), gate inductance
(LG), and gate capacitance (CG) form a series RLC
circuit with a second-order characteristic equation. The
series RLC circuit has an undamped natural frequency
(?0) and a damping ratio (?) where:
?0 =

1
(LP + LS + LG ) CG
RON

?=
2

(LP + LS + LG )
CG

The damping ratio needs to be greater than 0.5 (ideally 1)
to avoid ringing. Add a small resistor (RGATE) in series
with the gate when driving a very low gate-charge
MOSFET, or when the driver is placed away from the
MOSFET. Use the following equation to calculate the
series resistor:

RGATE >=

(LP + LS + LG )
- RON
CG

LP can be approximated as 3nH and 2nH for SO and
TDFN packages, respectively. LS is on the order of
20nH/in. Verify LG with the MOSFET vendor.

______________________________________________________________________________________

4A, 20ns, Dual MOSFET Drivers

Power Dissipation
Power dissipation of the MAX5054-MAX5057 consists
of three components: caused by the quiescent current,
capacitive charge/discharge of internal nodes, and the
output current (either capacitive or resistive load).
Maintain the sum of these components below the maximum power dissipation limit.
The current required to charge and discharge the internal
nodes is frequency dependent (see the Supply Current
vs. Supply Voltage graph in the T ypical Operating
Characteristics). The power dissipation (PQ) due to the
quiescent switching supply current (IDD-SW) per driver
can be calculated as:
PQ = VDD x IDD-SW
For capacitive loads, use the following equation to estimate the power dissipation per driver:
PCLOAD = CLOAD x (VDD)2 x fSW
where CLOAD is the capacitive load, VDD is the supply
voltage, and fSW is the switching frequency.
Calculate the total power dissipation (PT) per driver as
follows:
PT = PQ + PCLOAD
Use the following equation to estimate the MAX5054-
MAX5057 total power dissipation per driver when driving
a ground-referenced resistive load:
PT = PQ + PRLOAD

where D (duty cycle) is the fraction of the period the
MAX5054-MAX5057's output pulls high duty cycle,
RON(MAX) is the maximum on-resistance of the device
with the output high, and ILOAD is the output load current
of the MAX5054-MAX5057.

Layout Information
The MAX5054-MAX5057 MOSFET drivers source and
sink large currents to create very fast rising and falling
edges at the gate of the switching MOSFET. The high
di/dt can cause unacceptable ringing if the trace
lengths and impedances are not well controlled. Use the
following PC board layout guidelines when designing
with the MAX5054-MAX5057:
o

o

o

Place one or more 0.1uF decoupling ceramic
capacitors from VDD to GND as close to the device
as possible. Connect VDD and GND to large copper
areas. Place one bulk capacitor of 10uF (min) on
the PC board with a low resistance path to the VDD
input and GND of the MAX5054-MAX5057.
Two AC current loops form between the device and
the gate of the driven MOSFET. The MOSFET looks
like a large capacitance from gate to source when the
gate pulls low. The active current loop is from the
MOSFET gate to OUT_ of the MAX5054-MAX5057, to
GND of the MAX5054-MAX5057, and to the source of
the MOSFET. When the gate of the MOSFET pulls
high, the active current is from the VDD terminal of the
decoupling capacitor, to V DD of the MAX5054-
MAX5057, to OUT_ of the MAX5054-MAX5057, to the
MOSFET gate, to the MOSFET source, and to the
negative terminal of the decoupling capacitor. Both
charging current and discharging current loops are
important. Minimize the physical distance and the
impedance in these AC current paths.
Keep the device as close to the MOSFET as possible.

o

In a multilayer PC board, the inner layers should
consist of a GND plane containing the discharging
and charging current loops.

o

Pay extra attention to the ground loop and use a
low-impedance source when using a TTL logicinput device. Fast fall time at OUT_ may corrupt the
input during transition.

PRLOAD = D x RON(MAX) x ILOAD2

______________________________________________________________________________________

11

MAX5054-MAX5057

Supply Bypassing and Grounding
Pay extra attention to bypassing and grounding the
MAX5054-MAX5057. Peak supply and output currents
may exceed 8A when both drivers drive large external
capacitive loads in phase. Supply voltage drops and
ground shifts create forms of negative feedback for
inverters and may degrade the delay and transition times.
Ground shifts due to insufficient device grounding may
also disturb other circuits sharing the same AC ground
return path. Any series inductance in the VDD, OUT_,
and/or GND paths can cause oscillations due to the very
high di/dt when switching the MAX5054-MAX5057 with
any capacitive load. Place one or more 0.1uF ceramic
capacitors in parallel as close to the device as possible to
bypass VDD to GND. Use a ground plane to minimize
ground return resistance and series inductance. Place
the external MOSFET as close as possible to the
MAX5054-MAX5057 to further minimize board inductance and AC path impedance.

MAX5054-MAX5057

4A, 20ns, Dual MOSFET Drivers
Exposed Pad
Both the SO-EP and TDFN-EP packages have an
exposed pad on the bottom of their package. These
pads are internally connected to GND. For the best
thermal conductivity, solder the exposed pad to the

ground plane to dissipate 1.5W and 1.9W in SO-EP and
TDFN-EP packages, respectively. Do not use the
ground-connected pads as the only electrical ground
connection or ground return. Use GND (pin 3) as the
primary electrical ground connection.

Additional Application Circuits

VOUT

VIN

MAX5054
VDD
INA+
OUTA
INA-

MAX5054

VDD
VDD

PWM IN

INA+

INB+
OUTA

INA-

PWM IN

OUTB
PWM IN

INBGND

INB+
OUTB
INBGND

Figure 5. Push-Pull Converter with Synchronous Rectification Drive Using MAX5054

12

______________________________________________________________________________________

2

R27
10Ohm

C6
0.1uF

C3
4.7uF

C4
4.7uF

PVIN

REG9

REG5

TP3

3

4

C19
1uF

C18
1000pF

C17
0.33uF

R11
360Ohm

R3
2.2kOhm

REG5

LXH

REG5

D8

R15
31.6kOhm
1%

1

C2
390pF

R16
10.5kOhm
1%

TP1

C1
100pF

C5
4700pF

R25
100kOhm

C24
1000pF

+VIN

R21
24.9kOhm
1%

RCFF

14

13

12

11

10

9

8

7

6

17

18

19

20

21

22

2

1

REG9

R12
100kOhm
1%

R19
475Ohm

R23
10Ohm

2

VOUT

OUT
FB

4
1

2 65

U3

R17
0.027Ohm
1%

D3

1

PVIN

3

4
IN
1
PGND
2
GND

C21
4.7uF
80V

2

2

C34
330pF

8

2

D2

VOUT

1

2

4

R24
10Ohm

3
2

1 87

5

6

N1 8 7

D7
2

10

2T

8

+VIN

T1

XFRMRH

R22
15kOhm

6

4T

1

5

8T

2

1

3

XFRMRH

R18
4.7Ohm

D5

R13
47Ohm

REG9

R5
38.3kOhm
1%

7
N2

R6
1MOhm
1%

+VIN

R7
0Ohm

R8
8.2Ohm

R2
2.55kOhm
1%

5

SENSE (+) SENSE (-)

TRIM

3

R9
8.2Ohm

1

+VIN

R14
270Ohm

C9
1uF

DRVB

XFRMRH

C8
4.7uF

+VIN

ON/OFF

D1

R4
1MOhm
1%
C7
0.22uF

C27
0.15uF

C20
220pF

R20
0Ohm

29

16
DRVL
15
CS

PGND

DRVDD

DRVB

XFRMRH

DRVH

BST

23

24

25

26

27

28

C36
C28
R1
0.22uF
0.047uF 11.5kOhm
1%
VOUT

U2

LXL

LXH

LXVDD

STT

PVIN

REG9

REG5

FB

COMP

AVIN

GND

UVLO

STARTUP

IC_PADDLE

SYNCOUT

FLTINT

MAX5051

RCOSC U1 SYNCIN

4
COM
5
CSS

3

2

1

D6
1

1

6
5

4

N3

1

7

4

6

INA-

INB+

OUTB

OUTA

14

EN

IN

RESET
L1
2.4uH

MAX5054

U4

4

3 GND

2

1

C11
0.47uF
100V

N4

56

C32
1uF

C22
2200pF
2kV

+5V

C23
1000pF

1 87
D4
R10 2 3
20Ohm
2

2

C35
1uF

C10
0.47uF
100V

3

5

2

C30
0.1uF

C13
270uF
4V

5V

C25
0.047uF
100V

+5V

5

C26
0.1uF

GND

VDD

INB-

8

HOLD

REG9

7

8

N.C. 6

WDI

OUT

INA+

U5

C12
1uF
100V

+VIN

2

N5

3

3

4

5

1

GND

OUT

VCC
U6

CA

AN

2

1

LXH

C33
1uF
10V

R29
1Ohm

XFRMRH

VOUT

-VIN

C15
270uF
4V

U1: MAX5051
U2: PS2913-1-M
U3: MAX8515
U4: MAX5054
U5: MAX5023M
U6: PS9715
N1, N2: SI4486
N3, N4: SI4864
N5: BSS123

C31 5V
0.1uF

C14
270uF
4V

C16
3.3uF

+VIN

R28
2kOhm

R26
560Ohm

SGND

VOUT

DRVB

MAX5054-MAX5057

REG5

4A, 20ns, Dual MOSFET Drivers

Figure 6. Schematic of a 48V Input, 3.3V at 15A Output Synchronously Rectified, Isolated Power Supply

______________________________________________________________________________________

13

4A, 20ns, Dual MOSFET Drivers
MAX5054-MAX5057

Pin Configurations
TOP VIEW
MAX5054

MAX5055

INA-

1

8

INA+

N.C.

1

8

N.C.

INB-

2

7

INB+

INA- 2

7

OUTA

GND

3

6

OUTA

GND

3

6

VDD

OUTB 4

5

VDD

INB- 4

5

OUTB

TDFN-EP

SO/SO-EP

MAX5056

MAX5057

N.C.

1

8

N.C.

N.C.

1

8

N.C.

INA+

2

7

OUTA

INA- 2

7

OUTA

GND

3

6

VDD

GND

3

6

VDD

INB+ 4

5

OUTB

INB+ 4

5

OUTB

SO/SO-EP

SO/SO-EP

Selector Guide
PART

PINPACKAGE

LOGIC INPUT

MAX5054AATA

8 TDFN-EP*
8 TDFN-EP*

TTL Dual Inverting and Dual
Noninverting Inputs

MAX5055AASA

8 SO-EP*

TTL Dual Inverting Inputs

MAX5055BASA

8 SO

TTL Dual Inverting Inputs

MAX5056AASA

8 SO-EP*

TTL Dual Noninverting Inputs

MAX5056BASA

8 SO

TTL Dual Noninverting Inputs

MAX5057AASA

8 SO-EP*

TTL Inverting and
Noninverting Inputs

MAX5057BASA

8 SO

TRANSISTOR COUNT: 258
PROCESS: CMOS

VDD / 2 CMOS Dual Inverting
and Dual Noninverting Inputs

MAX5054BATA

Chip Information

TTL Inverting and
Noninverting Inputs

*EP = Exposed pad.

14

______________________________________________________________________________________

4A, 20ns, Dual MOSFET Drivers

N

E

H

MILLIMETERS

MAX
MIN
0.069
0.053
0.010
0.004
0.014
0.019
0.007
0.010
0.050 BSC
0.150
0.157
0.228
0.244
0.016
0.050

SOICN .EPS

INCHES
DIM
A
A1
B
C
e
E
H
L

MAX
MIN
1.35
1.75
0.10
0.25
0.35
0.49
0.19
0.25
1.27 BSC
3.80
4.00
5.80
6.20
0.40

1.27

VARIATIONS:
1

INCHES

TOP VIEW

DIM
D
D
D

MIN
0.189
0.337
0.386

MAX
0.197
0.344
0.394

MILLIMETERS
MIN
4.80
8.55
9.80

MAX
5.00
8.75
10.00

N MS012
8
AA
14
AB
16
AC

D
A
B

e

C

0?-8?

A1
L

FRONT VIEW

SIDE VIEW

PROPRIETARY INFORMATION
TITLE:

PACKAGE OUTLINE, .150 " SOIC
APPROVAL

DOCUMENT CONTROL NO.

21-0041

REV.

B

1
1

______________________________________________________________________________________

15

MAX5054-MAX5057

Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)

Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
8L, SOIC EXP. PAD.EPS

MAX5054-MAX5057

4A, 20ns, Dual MOSFET Drivers

PACKAGE OUTLINE
8L SOIC, .150 " EXPOSED PAD

21-0111

16

______________________________________________________________________________________

B

1

1

4A, 20ns, Dual MOSFET Drivers

6, 8, & 10L, DFN THIN.EPS

D
N

PIN 1
INDEX
AREA

E

E2
DETAIL A

C
L

C
L

L
A

L
e

e

PACKAGE OUTLINE, 6, 8, 10 & 14L,
TDFN, EXPOSED PAD, 3x3x0.80 mm

21-0137

NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY

F

1

2

COMMON DIMENSIONS
SYMBOL
A

MIN.
0.70

0.80

D

2.90

3.10

E

2.90

3.10

0.00

0.05

A1
L
k

MAX.

0.40
0.20
0.25 MIN.

A2

0.20 REF.

PACKAGE VARIATIONS
PKG. CODE

N

D2

E2

e

JEDEC SPEC

b

[(N/2)-1] x e

T633-1

6

1.50?0.10

2.30?0.10

0.95 BSC

MO229 / WEEA

0.40?0.05

1.90 REF

T833-1

8

1.50?0.10

2.30?0.10

0.65 BSC

MO229 / WEEC

0.30?0.05

1.95 REF

T1033-1

10

1.50?0.10

2.30?0.10

0.50 BSC

MO229 / WEED-3

0.25?0.05

2.00 REF

T1433-1

14

1.70?0.10

2.30?0.10

0.40 BSC

----

0.20?0.03

2.40 REF

T1433-2

14

1.70?0.10

2.30?0.10

0.40 BSC

----

0.20?0.03

2.40 REF

PACKAGE OUTLINE, 6, 8, 10 & 14L,
TDFN, EXPOSED PAD, 3x3x0.80 mm

21-0137

F

2

2

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17
(C) 2004 Maxim Integrated Products

Printed USA

is a registered trademark of Maxim Integrated Products.

MAX5054-MAX5057

Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)


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