fn3676.pdf

regulator prędkości silników modelarskich na AT90s2313

ciagle kombinuje i szukam jak zrobic ten regulator! szukam po necie i znalazlem stronke : http://www.m.case.btinternet.co.uk/html/speed_controller.html jest tam uklad drivera na hip4081, w TME jest dostepny podobny uklad i mysle ze da sie go zamiennie zastosowac - nawet niedrogi i malo komponetow zewnetrznych zalaczam jeszcze dokumentacje hip4082


HIP4082

(R)

Data Sheet

July 2004

80V, 1.25A Peak Current H-Bridge FET
Driver

FN3676.3

Features

The HIP4082 is a medium frequency, medium voltage
H-Bridge N-Channel MOSFET driver IC, available in 16 lead
plastic SOIC (N) and DIP packages.
Specifically targeted for PWM motor control and UPS
applications, bridge based designs are made simple and
flexible with the HIP4082 H-bridge driver. With operation up
to 80V, the device is best suited to applications of moderate
power levels.

o Independently Drives 4 N-Channel FET in Half Bridge or
Full Bridge Configurations
o Bootstrap Supply Max Voltage to 95VDC
o Drives 1000pF Load in Free Air at 50°C with Rise and Fall
Times of Typically 15ns
o User-Programmable Dead Time (0.1 to 4.5us)
o DIS (Disable) Overrides Input Control and Refreshes
Bootstrap Capacitor when Pulled Low

Similar to the HIP4081, it has a flexible input protocol for
driving every possible switch combination except those
which would cause a shoot-through condition. The
HIP4082's reduced drive current allows smaller packaging
and it has a much wider range of programmable dead times
(0.1 to 4.5us) making it ideal for switching frequencies up to
200kHz. The HIP4082 does not contain an internal charge
pump, but does incorporate non-latching level-shift
translation control of the upper drive circuits.

o Input Logic Thresholds Compatible with 5V to 15V Logic
Levels

This set of features and specifications is optimized for
applications where size and cost are important. For
applications needing higher drive capability the HIP4080A
and HIP4081A are recommended.

o DC Motor Controls

Ordering Information

o Noise Cancellation Systems

PART
NUMBER

TEMP.
RANGE (°C)

PACKAGE

PKG.
DWG. #

o Shoot-Through Protection
o Undervoltage Protection
o Pb-free Available

Applications
o UPS Systems

o Full Bridge Power Supplies
o Switching Power Amplifiers

o Battery Powered Vehicles
o Peripherals

HIP4082IB

-55 to +125 16 Ld SOIC (N)

M16.15

o Medium/Large Voice Coil Motors

HIP4082IBZ
(Note)

-55 to +125 16 Ld SOIC (N) (Pb-free)

M16.15

HIP4082IP

-55 to +125 16 Ld PDIP

E16.3

o Related Literature
- TB363, Guidelines for Handling and Processing
Moisture Sensitive Surface Mount Devices (SMDs)

HIP4082IPZ
(Note)

-55 to +125 16 Ld PDIP (Pb-free)

E16.3

NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.

Pinout
HIP4082
(PDIP, SOIC)
TOP VIEW
BHB 1

16 BHO

BHI 2

15 BHS

BLI 3

14 BLO

ALI 4

13 ALO

DEL 5

12 VDD

VSS

11 AHS
10 AHO

DIS 8

1

6

AHI 7

9 AHB

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Harris Corporation 1995. Copyright Intersil Americas Inc. 2003, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

HIP4082
Application Block Diagram
80V

12V
BHO
BHS
BHI

LOAD

BLO

BLI
HIP4082
ALI

ALO
AHS

AHI

AHO

GND

GND

Functional Block Diagram

9
LEVEL
SHIFT

U/V
BHI

7

DIS

1
DRIVER
LEVEL
SHIFT

10 AHO BHO 16

2

AHI

AHB BHB

DRIVER

8

11 AHS

BHS 15

TURN-ON
DELAY

TURN-ON
DELAY

VDD
VDD

12

ALI

5

BLI

3

VSS

DRIVER
TURN-ON
DELAY

4

DEL

DETECTOR
UNDERVOLTAGE

6

2

DRIVER
13 ALO

BLO 14

TURN-ON
DELAY

U/V

HIP4082
Typical Application (PWM Mode Switching)
80V

1 BHB

VDD 12

6 VSS

AHS 11

7 AHI

FROM
OPTIONAL
OVERCURRENT
LATCH

ALO 13

5 DEL

DIS

BLO 14

4 ALI

DELAY RESISTOR

BHS 15

3 BLI
PWM
INPUT

BHO 16

2 BHI

12V

AHO 10

8 DIS

AHB 9

LOAD

12V

GND

RDIS

TO OPTIONAL
CURRENT CONTROLLER OR
OVERCURRENT LATCH

+

-

RSH

GND

3

HIP4082
Absolute Maximum Ratings

Thermal Information

Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V
Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V
Voltage on AHS, BHS . . . . . -6V (Transient) to 80V (25°C to 150°C)
Voltage on AHS, BHS . . . . . -6V (Transient) to 70V (-55°C to150°C)
Voltage on AHB, BHB . . . . . . . . VAHS, BHS -0.3V to VAHS, BHS +VDD
Voltage on ALO, BLO . . . . . . . . . . . . . . . . . VSS -0.3V to VDD +0.3V
Voltage on AHO, BHO . . . VAHS, BHS -0.3V to VAHB, BHB +0.3V Input
Current, DEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5mA to 0mA
Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns
NOTE: All voltages are relative VSS unless otherwise specified.

Thermal Resistance, Junction-Ambient

?JA (°C/W)

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
115
DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
Maximum Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . See Curve
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Max. Junction Temperature . . . . . . . . . . . . . . . . . +150°C
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300°C
(For SOIC - Lead Tips Only))

Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . +8.5V to +15V
Voltage on VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +1.0V
Voltage on AHB, BHB . . . . . . . VAHS, BHS +7.5V to VAHS, BHS +VDD
Input Current, DEL . . . . . . . . . . . . . . . . . . . . . . . . . -4mA to -100uA
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Electrical Specifications

VDD = VAHB = VBHB = 12V, VSS = VAHS = VBHS = 0V, RDEL = 100K
TJ = -55°C
TO +150°C

TJ = +25°C
TYP

MAX

MIN

All inputs = 0V, RDEL = 100K

1.2

2.3

3.5

0.85

4

mA

2.2

4.0

5.5

1.9

6.0

mA

f = 50kHz, no load

1.5

2.6

4.0

1.1

4.2

mA

50kHz, no load, RDEL = 10kOhm

SYMBOL

MIN

All inputs = 0V, RDEL = 10K

PARAMETER

2.5

4.0

6.4

2.1

6.6

mA

TEST CONDITIONS

MAX UNITS

SUPPLY CURRENTS & UNDER VOLTAGE PROTECTION
VDD Quiescent Current

IDD

VDD Operating Current

IDDO

AHB, BHB Off Quiescent Current

IAHBL, IBHBL

AHI = BHI = 0V

0.5

1.0

1.5

0.4

1.6

mA

AHB, BHB On Quiescent Current

IAHBH, IBHBH

AHI = BHI = VDD

65

145

240

40

250

uA

AHB, BHB Operating Current

IAHBO, IBHBO

f = 50kHz, CL = 1000pF

.65

1.1

1.8

.45

2.0

mA

AHS, BHS Leakage Current

IHLK

-

-

1.0

-

-

uA

VAHS = VBHS = 80V
VAHB = VBHB = 96

VDD Rising Undervoltage Threshold

VDDUV+

6.8

7.6

8.25

6.5

8.5

V

VDD Falling Undervoltage Threshold

VDDUV-

6.5

7.1

7.8

6.25

8.1

V

Undervoltage Hysteresis

UVHYS

0.17

0.4

0.75

0.15

0.90

V

AHB, BHB Undervoltage Threshold

VHBUV

Referenced to AHS & BHS

5

6.0

7

4.5

7.5

V

0.8

V

INPUT PINS: ALI, BLI, AHI, BHI, & DIS
Low Level Input Voltage

VIL

Full Operating Conditions

-

-

1.0

-

High Level Input Voltage

VIH

Full Operating Conditions

2.5

-

-

2.7

-

35

-

-

-

mV

Input Voltage Hysteresis

V

Low Level Input Current

IIL

VIN = 0V, Full Operating Conditions

-145

-100

-60

-150

-50

uA

High Level Input Current

IIH

VIN = 5V, Full Operating Conditions

-1

-

+1

-10

+10

uA

RDEL = 100K

2.5

4.5

8.0

2.0

8.5

uS

RDEL = 10K

0.27

0.5

0.75

0.2

0.85

uS

TURN-ON DELAY PIN DEL
Dead Time

TDEAD

GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, & BHO
Low Level Output Voltage

VOL

IOUT = 50mA

0.65

1.1

0.5

1.2

V

High Level Output Voltage

VDD-VOH

IOUT = -50mA

0.7

1.2

0.5

1.3

V

4

HIP4082
Electrical Specifications

VDD = VAHB = VBHB = 12V, VSS = VAHS = VBHS = 0V, RDEL = 100K (Continued)
TJ = -55°C
TO +150°C

TJ = +25°C
PARAMETER

SYMBOL

MIN

TEST CONDITIONS

TYP

MAX

MIN

MAX UNITS

Peak Pullup Current

IO +

VOUT = 0V

1.1

1.4

2.5

0.85

2.75

A

Peak Pulldown Current

IO -

VOUT = 12V

1.0

1.3

2.3

0.75

2.5

A

Switching Specifications

VDD = VAHB = VBHB = 12V, VSS = VAHS = VBHS = 0V, RDEL= 100K, CL = 1000pF.
TJ = -55°C TO
+150°C

TJ = +25°C
PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

MIN

MAX

UNITS

Lower Turn-off Propagation Delay
(ALI-ALO, BLI-BLO)

TLPHL

-

25

50

-

70

ns

Upper Turn-off Propagation Delay
(AHI-AHO, BHI-BHO)

THPHL

-

55

80

-

100

ns

Lower Turn-on Propagation Delay
(ALI-ALO, BLI-BLO)

TLPLH

-

40

85

-

100

ns

Upper Turn-on Propagation Delay
(AHI-AHO, BHI-BHO)

THPLH

-

75

110

-

150

ns

Rise Time

TR

-

9

20

-

25

ns

Fall Time

TF

-

9

20

-

25

ns

TPWIN-ON/OFF

50

-

-

50

-

ns

80

ns

Minimum Input Pulse Width
Output Pulse Response to 50 ns Input Pulse

63

TPWOUT

Disable Turn-off Propagation Delay
(DIS - Lower Outputs)

TDISLOW

-

50

80

-

90

ns

Disable Turn-off Propagation Delay
(DIS - Upper Outputs)

TDISHIGH

-

75

100

-

125

ns

Disable Turn-on Propagation Delay
(DIS - ALO & BLO)

TDLPLH

-

40

70

-

100

ns

Disable Turn-on Propagation Delay
(DIS- AHO & BHO)

TDHPLH

-

1.2

2

-

3

us

Refresh Pulse Width (ALO & BLO)

TREF-PW

375

580

900

350

950

ns

RDEL = 10K

TRUTH TABLE
INPUT

OUTPUT

ALI, BLI

AHI, BHI

VDDUV

VHBUV

DIS

ALO, BLO

AHO, BHO

X

X

X

X

1

0

0

X

X

1

X

X

0

0

0

X

0

1

0

0

0

1

X

0

X

0

1

0

0

1

0

0

0

0

1

0

0

0

0

0

0

0

NOTE:

X signifies that input can be either a "1" or "0".

5

HIP4082
Pin Descriptions
PIN
NUMBER

SYMBOL

DESCRIPTION

1

BHB

B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap
diode and positive side of bootstrap capacitor to this pin.

2

BHI

B High-side Input. Logic level input that controls BHO driver (Pin 16). BLI (Pin 3) high level input overrides BHI high
level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 8) high level input overrides BHI high level
input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD).

3

BLI

B Low-side Input. Logic level input that controls BLO driver (Pin 14). If BHI (Pin 2) is driven high or not connected
externally then BLI controls both BLO and BHO drivers, with dead time set by delay currents at DEL (Pin 5). DIS (Pin
8) high level input overrides BLI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than
VDD).

4

ALI

A Low-side Input. Logic level input that controls ALO driver (Pin 13). If AHI (Pin 7) is driven high or not connected
externally then ALI controls both ALO and AHO drivers, with dead time set by delay currents at DEL (Pin 5). DIS (Pin
8) high level input overrides ALI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than
VDD).

5

DEL

Turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the dead time between drivers.
All drivers turn-off with no adjustable delay, so the DEL resistor guarantees no shoot-through by delaying the turn-on
of all drivers. The voltage across the DEL resistor is approximately Vdd -2V.

6

VSS

Chip negative supply, generally will be ground.

7

AHI

A High-side Input. Logic level input that controls AHO driver (Pin 10). ALI (Pin 4) high level input overrides AHI high
level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 8) high level input overrides AHI high level
input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD).

8

DIS

DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs.
When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to
15V (no greater than VDD).

9

AHB

A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap
diode and positive side of bootstrap capacitor to this pin.

10

AHO

A High-side Output. Connect to gate of A High-side power MOSFET.

11

AHS

A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.

12

VDD

Positive supply to control logic and lower gate drivers. De-couple this pin to VSS (Pin 6).

13

ALO

A Low-side Output. Connect to gate of A Low-side power MOSFET.

14

BLO

B Low-side Output. Connect to gate of B Low-side power MOSFET.

15

BHS

B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.

16

BHO

B High-side Output. Connect to gate of B High-side power MOSFET.

6

HIP4082
Timing Diagrams
X = A OR B, A AND B HALVES OF BRIDGE CONTROLLER ARE INDEPENDENT
TLPHL

THPHL

DIS=0
and UV
XLI

XHI

XLO

XHO

THPLH

TLPLH

FIGURE 1. INDEPENDENT MODE

DIS=0
and UV
XLI

XHI = HI OR NOT CONNECTED

XLO

XHO

FIGURE 2. BISTATE MODE

TDLPLH

DIS or UV

TDIS
TREF-PW

XLI

XHI

XLO

XHO
TDHPLH

FIGURE 3. DISABLE FUNCTION

7

TR
(10% - 90%)

TF
(10% - 90%)

HIP4082
Performance Curves
16

3.5

200kHz

VDD = 16V

3

IDD SUPPLY CURRENT (mA)

IDD SUPPLY CURRENT (mA)

15
3.25

VDD = 15V

2.75
2.5

VDD = 12V

2.25

VDD = 10V

2
VDD = 8V

1.75
1.5
-60

14
13
12
11
10
8

-20

50kHz

7
6

10kHz

5
4

-40

100kHz

9

0
20
40
60
80 100
JUNCTION TEMPERATURE (°C)

120

140

FIGURE 4. IDD SUPPLY CURRENT vs TEMPERATURE AND
VDD SUPPLY VOLTAGE

-60

7
PEAK GATE CURRENT (A)

LOADED, NL BIAS CURRENTS (mA)

1.925

6
5
4

1000pF LOAD

3
NO LOAD

2

-20

100
FREQUENCY (kHz)

150

1.5
SOURCE

ISRC(BIAS)
1.25

SINK

ISNK(BIAS)
1
0.75

8
8

200

FIGURE 6. FLOATING (IXHB) BIAS CURRENT vs FREQUENCY
AND LOAD

140

2

0.815
0.5
50

120

1.75

1
0

0
20
40
60
80 100
JUNCTION TEMPERATURE (°C)

FIGURE 5. VDD SUPPLY CURRENT vs TEMPERATURE AND
SWITCHING FREQUENCY (1000pF LOAD)

8

0

-40

9

10

11

12
13
14
BIAS
BIAS SUPPLY VOLTAGE (V) AT 25°C

15
15

FIGURE 7. GATE SOURCE/SINK PEAK CURRENT vs BIAS
SUPPLY VOLTAGE AT 25°C

1.2

-40°C
1.1

-55°C

1.2
VDD-VOH (V)

NORMALIZED GATE
SINK/SOURCE CURRENT (A)

1.4

1

0°C
25°C

1
125°C

150°C

0.8
0.9
0.6
0.8
-75

-50

-25
0
25
50
75
100
JUNCTION TEMPERATURE (°C)

125

150

FIGURE 8. GATE CURRENT vs TEMPERATURE, NORMALIZED
TO 25°C

8

8

9

10
11
12
13
VDD SUPPLY VOLTAGE (V)

14

FIGURE 9. VDD-VOH vs BIAS VOLTAGE TEMPERATURE

15

HIP4082
Performance Curves

(Continued)
8
VDD, BIAS SUPPLY VOLTAGE (V)

1.4

VOL (V)

1.2
-40°C

-55°C

0°C

25°C

1

0.8

125°C
150°C

0.6
8

9

10
11
12
13
VDD SUPPLY VOLTAGE (V)

14

LOWER U/V SET
6.5

6
UPPER U/V SET/RESET
5.5

-40

DIS TO TURN-ON/OFF TIME (ns)

80

UPPER tON

70
60

UPPER tOFF
LOWER tON

50
40
30

LOWER tOFF

20
-60

120

140 160

-40

-20

0

20

40

60

80

100

120

DISHTON
1000

DISHTOFF

100

DISLTON
10

140 160

-60 -40

JUNCTION TEMPERATURE (°C)

FIGURE 12. UPPER LOWER TURN-ON / TURN-OFF PROPAGATION DELAY vs TEMPERATURE

-20

DISLOFF

0
20
40
60
80 100
JUNCTION TEMPERATURE (°C)

120 140 160

FIGURE 13. UPPER/LOWER DIS(ABLE) TO TURN-ON/OFF vs
TEMPERATURE (°C)

2

2.5
TOTAL POWER DISSIPATION (W)

LEVEL-SHIFT CURRENT (mA)

0
20
40
60
80 100
JUNCTION TEMPERATURE (°C)

104

90

1.5

1

0.5

-20

FIGURE 11. UNDERVOLTAGE TRIP VOLTAGES vs TEMPERATURE

100

PROPAGATION DELAYS (ns)

7

5
-60

15

FIGURE 10. VOL vs BIAS VOLTAGE AND TEMPERATURE

LOWER U/V RESET
7.5

0

20

40
60
80
SWITCHING FREQUENCY (kHz)

FIGURE 14. FULL BRIDGE LEVEL-SHIFT CURRENT vs
FREQUENCY (kHz)

9

100

2
16 PIN DIP
1.5
SOIC
1

0.5
QUIESCENT BIAS COMPONENT
0

-60

-30

0
30
60
90
AMBIENT TEMPERATURE (°C)

120

FIGURE 15. MAXIMUM POWER DISSIPATION vs AMBIENT
TEMPERATURE

150

HIP4082
Performance Curves

(Continued)

104

90
VDD = 15V

VDD = 12V

VXHS-VSS

DEAD TIME (ns)

85

VDD = 9V

1000

80

75

100

0

10

20

30
40
50
60
70
DEAD TIME RESISTANCE (kOhm)

80

90 100

FIGURE 16. DEAD-TIME vs DEL RESISTANCE AND BIAS
SUPPLY (VDD) VOLTAGE

10

70

100

50

0
50
TEMPERATURE (°C)

100

150

FIGURE 17. MAXIMUM OPERATING PEAK AHS/BHS VOLTAGE
vs TEMPERATURE

HIP4082
Dual-In-Line Plastic Packages (PDIP)
E16.3 (JEDEC MS-001-BB ISSUE D)

N

16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1

INDEX
AREA

12 3

INCHES

N/2

MILLIMETERS

SYMBOL
-A-

MIN

MAX

MIN

MAX

NOTES

A

-B-

-

0.210

-

5.33

4

-C-

A2

SEATING
PLANE

A

e

B1

D1

A1

eC

B

0.015

-

0.39

-

4

0.115

0.195

2.93

4.95

-

B

0.014

0.022

0.356

0.558

-

C
L

B1

0.045

0.070

1.15

1.77

8, 10

eA

L

D1

A1
A2

E

D
BASE
PLANE

C

0.008

0.014

C

D

0.735

0.775

0.204

0.355

18.66

19.68

5

C A BS

NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.

D1

0.005

-

0.13

-

5

E

0.010 (0.25) M

eB

0.300

0.325

7.62

8.25

6

E1

0.240

0.280

6.10

7.11

5

e

0.100 BSC

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

eA

0.300 BSC

3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of
Publication No. 95.

eB

-

4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3.

L

0.115

N

5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

11

2.54 BSC
7.62 BSC

0.430
0.150
16

2.93

6

10.92
3.81
16

7
4
9
Rev. 0 12/93

HIP4082
Small Outline Plastic Packages (SOIC)

M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

N

INCHES
INDEX
AREA

H

0.25(0.010) M

BM

SYMBOL

E

2

MIN

MAX

NOTES

A

0.053

0.069

1.35

1.75

-

0.004

0.010

0.10

0.25

-

B

SEATING PLANE
h x 45o

A

D

9

0.25

-

0.386

0.394

9.80

10.00

3

0.150

0.157

3.80

4.00

4

0.050 BSC

1.27 BSC

-

BS

0.228

0.244

5.80

6.20

-

h
C

0.10(0.004)
C AM

0.49

0.19

e

?
u
A1

B
0.25(0.010) M

0.35

0.010

H

-C-

e

0.019

0.007

E

L

0.014

C
D

3

-A-

MILLIMETERS

MAX

A1

-B1

MIN

0.010

0.020

0.25

0.50

5

L

0.016

0.050

0.40

1.27

6

8o

0o

N

?

16
0o

16

7
8o

Rev. 1 02/02

NOTES:
1. Symbols are defined in the "MO Series Symbol List" in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension "D" does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. "L" is the length of terminal for soldering to a substrate.
7. "N" is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width "B", as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com
12


Pobierz plik - link do postu