K9GAG08U0E.pdf

Samsung UE37D5700 - Tv włącza się i wyłącza, brak logo, podświetlenie ok

Jakiego programatora używacie to programowania tych ukladów? Ja posiadam RT809H ale nie radzi sobie z ta pamiecia. Takie było pytanie autora tego tematu odnośnie ... programowania NAND? Dostał odp. . I tylko tyle. :idea: To,że kol. z (kleczewa) handluje Twoim ? lub (błędnie zgranym wsadem) lub mającym kupione NAND z BB to już nie mój problem :cry: A wstawki o restauracji , dworcu i naleśnikach to "ni z gruchy ni z pietruchy" p.s jest filmik na YT , że NAND PROGRAMMER TL86 READ/VERIFY Samsung K9GAG08U0E Link Norma w tych NAND to 2-5 BB Programmer RT809H czyta i zapisuje wsady w tym NAND ( ale nie pomija BB) i po wlutowaniu nowej kości ... jest to samo! :D Link_ NAND:Bad_Blocks Ponadto ten NAND jest w 3-wer. K9GAG08U0E , K9GAG08U0E (AML-01) , K9GAG08U0E (HDT-01) - róznią się algorytmem programowania Chwalą się , że sprzedawany na znanym PL portalu (za 199pln) czyta ten NAND Jego nazwa : Czytnik pamięci NAND Lite! TSOP48 Ciekawie z tego forum Link


Rev. 0.9.1,Mar. 2010
K9GAG08U0E
K9LBG08U0E
K9HCG08U1E

Final

16Gb E-die NAND Flash
Multi-Level-Cell (2bit/cell)

datasheet
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SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
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(c) 2010 Samsung Electronics Co., Ltd. All rights reserved.

-1-

Final Rev. 0.9.1

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

FLASH MEMORY

Revision History
Revision No.

History

Draft Date

Remark

Editor

0.0

1. Initial issue

Jun. 12, 2009

Advance

0.1

1. Pin configuration is changed.
2. tREA is changed from 20ns to 25ns.
3. Memory cell array is amended.
4. Row address is modified.
5. Dummy busy time for Two-Plane Program(tDBSY) is deleted.

Oct. 21, 2009

Advance

0.2

1. Pin configuration is changed.

Oct. 21, 2009

Advance

0.3

1. tRC/tWC is changed from 30ns to 20ns.
2. The Parameter related tRC/tWC is changed

Nov. 6, 2009

Advance

0.4

1. 52LGA (11x14) QDP is added

Nov. 13, 2009

Advance

S.M.Lee

0.5

1. AC character's changed.

Jan. 20, 2010

Advance

S.M.Lee

0.9

1. Part ID K9LBG08U0E and K9HCG08U1E are added.

Mar. 09, 2010

Final

S.M.Lee

1. tR 300- & gt; 400 changed.
2. K9HCG08U5E is deleted.
3.Package Dimensions of 48-TSOP are amended.

Mar. 31, 2010

Final

S.M.Lee

0.9.1

-2-

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

datasheet

Final Rev. 0.9.1

FLASH MEMORY

Table Of Contents
1.0 INTRODUCTION ........................................................................................................................................................ 5
1.1 Product List.............................................................................................................................................................. 5
1.2 Features ...........................................................................................................................................................5
1.3 General Description................................................................................................................................................. 5
1.4 Pin Configuration (TSOP1) ...................................................................................................................................... 6
1.5 Package Dimensions ............................................................................................................................................... 6
1.6 PIN CONFIGURATION (48TSOP) .......................................................................................................................... 7
1.6.1PACKAGE DIMENSIONS .................................................................................................................................. 7
1.7 Pin Description ........................................................................................................................................................ 8
2.0 PRODUCT INTRODUCTION...................................................................................................................................... 10
2.1 Absolute Maximum Ratings ..................................................................................................................................... 11
2.2 Recommended Operating Conditions ..................................................................................................................... 11
2.3 Dc And Operating Characteristics(Recommended Operating Conditions Otherwise Noted.) ................................. 11
2.4 Valid Block............................................................................................................................................................... 12
2.5 Ac Test Condition .................................................................................................................................................... 12
2.6 Capacitance(Ta=25°c, Vcc=3.3v, F=1.0mhz).......................................................................................................... 12
2.7 Mode Selection........................................................................................................................................................ 12
2.8 Program / Erase Characteristics ........................................................................................................................13
2.9 AC Timing Characteristics for Command / Address / Data Input ............................................................................ 13
2.10 AC Characteristics for Operation........................................................................................................................... 14
3.0 NAND FLASH TECHNICAL NOTES .......................................................................................................................... 15
3.1 Initial Invalid Block(s) ............................................................................................................................................... 15
3.2 Initial Invalid Block(s) ............................................................................................................................................... 15
3.3 Error in write or read operation................................................................................................................................ 16
3.4 Addressing for program operation ........................................................................................................................... 18
3.5 Interleaving operation ............................................................................................................................................. 20
3.5.1Interleaving Page Program ................................................................................................................................ 21
3.5.2Interleaving Page Read...................................................................................................................................... 22
3.5.3 Interleaving Block Erase ................................................................................................................................... 23
3.5.4Interleaving Read to Page Program ................................................................................................................... 24
3.5.5 Interleaving Copy-Back Program ...................................................................................................................... 25
3.6 System Interface Using CE don't-care. ................................................................................................................... 26
4.0 TIMING DIAGRAMS ................................................................................................................................................... 27
4.1 Command Latch Cycle ............................................................................................................................................ 27
4.2 Address Latch Cycle................................................................................................................................................ 27
4.3 Input Data Latch Cycle ............................................................................................................................................ 28
4.4 * Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)...................................................................................... 28
4.5 Serial Access Cycle after Read(EDO Type, CLE=L, WE=H, ALE=L) ..................................................................... 29
4.6 Status Read Cycle................................................................................................................................................... 29
4.7 Read Operation ....................................................................................................................................................... 30
4.8 Read Operation(Intercepted by CE) ........................................................................................................................ 30
4.9 Random Data Output In a Page .............................................................................................................................. 31
4.10 Cache Read Operation(1/2) .................................................................................................................................. 32
4.11 Cache Read Operation(2/2) .................................................................................................................................. 33
4.12 Page Program Operation....................................................................................................................................... 34
4.13 Page Program Operation with Random Data Input ............................................................................................... 35
4.14 Copy-Back Program Operation with Random Data Input ...................................................................................... 36
4.15 Cache Program Operation(available only within a block) ...................................................................................... 37
4.16 Block Erase Operation........................................................................................................................................... 38
4.17 Read ID Operation................................................................................................................................................. 39
4.17.1ID Definition Table .....................................................................................................................................40
5.0 DEVICE OPERATION ................................................................................................................................................ 42
5.1 Page Read............................................................................................................................................................... 42
5.2 CACHE READ ......................................................................................................................................................... 43
5.3 Page Program ......................................................................................................................................................... 45
5.4 Copy-back Program................................................................................................................................................. 46
5.5 Cache Program ....................................................................................................................................................... 47
5.6 Block Erase ............................................................................................................................................................. 50
5.7 Read Status............................................................................................................................................................. 51

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K9GAG08U0E
K9LBG08U0E K9HCG08U1E

datasheet

Final Rev. 0.9.1

FLASH MEMORY

5.8 Read ID ................................................................................................................................................................... 52
5.9 RESET..................................................................................................................................................................... 52
5.10 Ready/Busy ........................................................................................................................................................... 53
6.0 DATA PROTECTION & POWER UP SEQUENCE..................................................................................................... 54
6.1 WP AC Timing guide ............................................................................................................................................... 55

-4-

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

Final Rev. 0.9.1

FLASH MEMORY

1.0 INTRODUCTION

1.1 Product List
Part Number

Density

K9GAG08U0E-S

16Gb

K9LBG08U0E-S

32Gb

K9HCG08U1E-S

Interface

Vcc Range

Organization

PKG Type

Conventional

2.7V ~ 3.6V

x8

48TSOP1

64Gb

1.2 Features
o Voltage Supply
- 3.3V Device : 2.7V ~ 3.6V
o Organization
- Memory Cell Array : (2,076M x 110.49K) x 8bit
- Data Register
: (8K + 436) x 8bit
o Automatic Program and Erase
- Page Program : (8K + 436)Byte
- Block Erase : (1M + 54.5K)Byte
o Page Read Operation
- Page Size : (8K + 436)Byte
- Random Read : 400?s(Max.)
- Serial Access : 30ns(Min.)
o Memory Cell : 2bit / Memory Cell
o Fast Write Cycle Time
- Program time : 1.2ms(Typ.)
- Block Erase Time : 1.5ms(Typ.)

o Command/Address/Data Multiplexed I/O Port
o Hardware Data Protection
- Program/Erase Lockout During Power Transitions
o Reliable CMOS Floating-Gate Technology
- ECC Requirement : 24bit/(1K +54.5)Byte
- Endurance & Data Retention : Pleae refer to the qualification report
o Command Register Operation
o Unique ID for Copyright Protection
o Package :
- K9GAG08U0E-SCB0/SIB0 : Pb-Halogen FREE PACKAGE
48 - Pin TSOP1 (12 x 20 / 0.5 mm pitch)
- K9LBG08U0E-SCB0/SIB0 : Pb-Halogen FREE PACKAGE
48 - Pin TSOP1 (12 x 20 / 0.5 mm pitch)
- K9HCG08U1E-SCB0/SIB0 : Pb-Halogen FREE PACKAGE
48 - Pin TSOP1 (12 x 20 / 0.5 mm pitch)

1.3 General Description
The device is offered in 3.3V Vcc. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program operation
can be performed in typical 1.2ms on the 8,628-byte page and an erase operation can be performed in typical 1.5ms on a (1M+54.5K)byte block. Data in
the data register can be read out at 30ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input.
The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining
of data. Even the write-intensive systems can take advantage of the K9GAG08U0E?s extended reliability of P/E cycles which are presented in the Qualification report by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9GAG08U0E is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.

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Final Rev. 0.9.1

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

FLASH MEMORY

1.4 Pin Configuration (48TSOP)
K9GAG08U0E-SCB0/SIB0
K9LBG08U0E-SCB0/SIB0
N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

48-pin TSOP1
Standard Type
12mm x 20mm

1.4.1 Package Dimensions
48-PIN LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
Unit :mm

48 - TSOP1 - 1220AF
1.20MAX
1.00.?0.05
(1.00)

#48

#24

(13°)

#25

(10

°)

( 13

°)

0.10
MAX
0.075

(18.80)

)

0.05 MIN

+0.075
0.125 -0.035

)
15
0.
(R

0.4375?0.05
0.4375?0.05

18.40.?0.10

.1 5

)
15

(0.25)

0
(R

0.
(R

0.50TYP
[0.50?0.06]

0.16 -0.01

+0.03

12.00.?0.10

#1

(1.00)

(1.00)

0.20 -0.03

+0.07

(1.00)

(19.00)

0 .2
5)

0 .2

5)



20.00.?0.20

(R
(R

0° ~

0.25TYP

(R
0.
15
)

(10°)

(0.50)
0.45 ~ 0.75

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Final Rev. 0.9.1

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

FLASH MEMORY

1.5 Pin Configuration (48TSOP)
K9HCG08U1E-SCB0/SIB0
N.C
N.C
N.C
N.C
N.C
R/B2
R/B1
RE
CE1
CE2
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

48-pin TSOP1
Standard Type
12mm x 20mm

N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C

1.5.1 package dimensions
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
Unit :mm

48 - TSOP1 - 1220BF
1.20MAX
1.05.?0.3
(1.00)

#48

#24

(13°)

#25

(10

°)

0
(R
(0.25)
°)

0.10
MAX
0.075

( 13

0.02 MIN

+0.075
0.125 -0.035

0.4625?0.05
0.4625?0.05

)
15
0.
(R

(18.80)

0.25TYP

(R
(R

0 .2

0.2
5

5)

0°~ 8

(R
0.
15
)

(10°)

(19.00)

)

)
15

18.40.?0.10

.1 5

0.
(R

0.50TYP
[0.50?0.06]

12.00.?0.10

0.16 -0.03

+0.07

#1

(1.00)

(1.00)

0.20 -0.03

+0.07

(1.00)

)

°

20.00.?0.20
(0.50)
0.45 ~ 0.75

-7-

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

datasheet

Final Rev. 0.9.1

FLASH MEMORY

1.6 Pin Description
Pin Name

Pin Function

I/O0 ~ I/O7

DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to
high-z when the chip is deselected or when the outputs are disabled.

CLE

COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high, commands are
latched into the command register through the I/O ports on the rising edge of the WE signal.

ALE

ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising
edge of WE with ALE high.

CE

CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does
not return to standby mode in program or erase operation.

RE

READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one.

WE

WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.

WP

WRITE PROTECT
The WP pin provides inadvertent program/erase protection during power transitions. The internal high voltage generator is
reset when the WP pin is active low.

R/B

READY/BUSY OUTPUT
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read
operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled.

Vcc

POWER
VCC is the power supply for device.

Vss

GROUND

N.C

NO CONNECTION
Lead is not internally connected.

NOTE :
Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.

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Final Rev. 0.9.1

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

FLASH MEMORY

VCC
VSS
A14 - A33

X-Buffers
Latches
& Decoders

(16,608M + 883.9M)Bits
NAND Flash
ARRAY

A0 - A13

Y-Buffers
Latches
& Decoders

(8,192 + 436)Byte x 265,728
Data Register & S/A
Y-Gating

Command
Command
Register

Control Logic
& High Voltage
Generator

CE
RE
WE

VCC
VSS

I/O Buffers & Latches

Global Buffers

Output
Driver

I/0 0

I/0 7
CLE ALE WP

Figure 1. K9GAG08U0E Functional Block Diagram

1 Block = 128 Pages
(1M + 54.5K)Bytes

1 Page = (8K + 436)Bytes
1 Block = (8K + 436)B x 128 Pages
= (1M + 54.5K) Bytes

265,728 Pages
(=2,076 Blocks)

= 17,491 Mbits
8 bit
8K Bytes

436 Bytes

I/O 0 ~ I/O 7

Page Register
8K Bytes

436 Bytes

Figure 2. K9GAG08U0E Array Organization

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

1st Cycle

A0

A1

A2

A3

A4

A5

A6

A7

2nd Cycle

A8

A9

A10

A11

A12

A13

*L

*L

3rd Cycle

A14

A15

A16

A17

A18

A19

A20

A21

4th Cycle

A22

A23

A24

A25

A26

A27

A28

A29

5th Cycle

A30

A31

A32

A33*

*L

*L

*L

*L

Column Address

Row Address;
Page Address : A14 ~ A20
Block Address : A21 ~ A32
*A33 : Chip address for
K9LBG08U0E, K9HCG08U1E

NOTE :
Column Address : Starting Address of the Register.
* L must be set to 'Low'.
* The device ignores any additional input of address cycles than required.
* Row Address consists of Page address (A14 ~ A20) & Block address(A21 ~ the last Address)

-9-

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

datasheet

Final Rev. 0.9.1

FLASH MEMORY

2.0 PRODUCT INTRODUCTION
NAND Flash Memory has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities
by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low.
Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address
respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc. require just one cycle
bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution..
Page Read and Page Program need the same five address cycles following the required command input. In Block Erase operation, however, only the
three row address cycles are used. Device operations are selected by writing specific commands into the command register. The table below defines the
specific commands.
[Table 1] Command Sets
1st Set

2nd Set

Read

Function

00h

30h

Read for Copy Back

00h

35h

Cache Read

31h

-

Read Start for Last Page Cache Read

3Fh

-

Page Program

80h

10h

Cache Program

80h

15h

Copy-Back Program

85h

10h

Block Erase
Random Data Input

60h
(1)

Random Data Output(1)

D0h

85h

-

05h

Acceptable Command during Busy

E0h

Read ID

90h

-

Read Status

70h

-

Chip Status1

F1h

-

Chip Status2

F2h

Reset

FFh

O
O
O

-

NOTE :
1) Random Data Input/Output can be executed in a page.

CAUTION : Any undefined command inputs are prohibited except for above command set of Table 1.

- 10 -

O

Final Rev. 0.9.1

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

FLASH MEMORY

2.1 Absolute Maximum Ratings
Parameter

Symbol

Rating

VCC

-0.6 to + 4.6

VIN

-0.6 to + 4.6

VI/O

-0.6 to Vcc+0.3 ( & lt; 4.6V)

TSTG

-65 to +100

°C

Ios

5

mA

Voltage on any pin relative to VSS

Storage Temperature

K9XXG08UXE-XCB0

Unit

V

K9XXG08UXE-XIB0
Short Circuit Current

NOTE :
1) Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods & lt; 30ns.
Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods & lt; 20ns.
2) Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2.2 Recommended Operating Conditions
(Voltage reference to GND, K9XXG08XXE-XCB0 :TA=0 to 70°C(1), K9XXG08XXE-XIB0:TA=-40 to 85°C(1))
Parameter

Symbol

Min

Typ.

Max

Unit

Supply Voltage

VCC

2.7

3.3

3.6

V

Supply Voltage

VSS

0

0

0

V

NOTE:
1) Data retention is not guaranteed on Operating condition temperature over/under.

2.3 Dc And Operating Characteristics(Recommended Operating Conditions Otherwise Noted.)
Parameter

Symbol
ICC1(4)

Program

Test Conditions

Min

Typ

Max

Unit

-

30

50

mA

CE=VCC-0.2, WP=0V/VCC

-

10

50

VIN=0 to Vcc(max)

-

-

?10

VOUT=0 to Vcc(max)

-

-

?10

-

0.8 xVcc

-

Vcc +0.3

-

-0.3

-

0.2 xVcc

2.4

-

-

tRC=30ns
CE=VIL, IOUT=0mA

ICC2(4)

Erase

Operating
Current

Page Read with Serial
Access

ICC3(4)

Stand-by Current(CMOS)

ISB(3)

Input Leakage Current

ILI

Output Leakage Current

ILO(5)

Input High Voltage

-

VIH(1)

(5)

Input Low Voltage, All inputs

VIL

Output High Voltage Level

VOH

(1)

K9GAG08U0E :IOH=-400?A

Output Low Voltage Level

VOL

K9GAG08U0E :IOL=2.1mA

-

-

IOL(R/B)

K9GAG08U0E :VOL=0.4V

8

10

-

V

0.4

Output Low Current(R/B)

?A

NOTE :
1) VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.
2) Typical value is measured at Vcc=3.3V, TA=25°C. Not 100% tested.
3) The Typical value of the K9LBG08U0E's ISB is 20?A and the maximum value is100?A
The Typical value of the K9HCG08U1E's ISB is 40?A and the maximum value is200?A
4) The Typical value of K9LBG08U0E, K9HCG08U1E's Icc1, Icc2 and Icc3 are 35mA and the maximum values are 55mA.
5) The maximum value of K9LBG08U0E's is ?20?A.
The maximum value of K9HCG08U1E's is ?40?A.

- 11 -

mA

Final Rev. 0.9.1

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

FLASH MEMORY

2.4 Valid Block
Parameter

Symbol

Min

K9GAG08U0E

Typ.

Max

2,018
NVB

K9LBG08U0E

2,076
-

4,036

K9HCG08U1E

Unit
Blocks

4,152

8,072

8,304

NOTE :
1) The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both
cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits which cause status failure during program and erase operation. Do
not erase or program factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.
2) The 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment

2.5 Ac Test Condition
(K9XXG08XXE-XCB0 :TA=0 to 70°C, K9XXG08XXE-XIB0:TA=-40 to 85°C, K9XXG08UXE: Vcc=2.7V ~ 3.3V,unless otherwise noted)
Parameter

K9XXG08UXE

Input Pulse Levels

0V to Vcc

Input Rise and Fall Times

5ns

Input and Output Timing Levels

Vcc/2

Output Load

1 TTL GATE and CL=50pF

2.6 Capacitance(Ta=25°c, Vcc=3.3v, F=1.0mhz)
K9GAG08U0E
Item

Symbol

K9LBG08U0E

K9HCG08U1E

Test Condition

Unit
Min

Min

Max

Min

Max

-

8

-

13

-

23

pF

-

5

-

10

-

20

pF

-

8

-

13

-

23

pF

-

CI/O

Max

5

-

10

-

20

pF

VIL=0V

Input/Output Capacitance
CI/O(W)*
CIN

VIN=0V

Input Capacitance
CIN(W)*
NOTE :
1) Capacitance is periodically sampled and not 100% tested.
2) CI/O(W) and CIN(W) are tested at wafer level.

2.7 Mode Selection
CLE

ALE

CE

RE

WP

H

L

L

WE

H

X

Mode

L

H

L

H

X

H

L

L

H

H

L

H

L

H

H

L

L

L

H

H

Data Input

Read Mode

Command Input
Address Input(5clock)

Write Mode

Command Input
Address Input(5clock)

L

L

L

H

X

Data Output

X

X

X

X

H

X

During Read(Busy)

X

X

X

X

X

H

During Program(Busy)

X

X

X

X

X

H

During Erase(Busy)

X

X(1)

X

X

X

L

Write Protect

X

X

H

X

X

0V/V

NOTE :
1) X can be VIL or VIH.
2) WP should be biased to CMOS high or CMOS low for standby.

- 12 -

CC(2)

Stand-by

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

Final Rev. 0.9.1

datasheet

FLASH MEMORY

2.8 Program / Erase Characteristics
Parameter

Symbol

Min

Typ

Max

Unit

Program Time

tPROG

-

1.2

5

ms

Dummy Busy Time for Cache Program

tCBSY(4)

-

-

5

ms

Number of Partial Program Cycles in the Same Page

Nop

-

-

1

cycle

Block Erase Time

tBERS

-

1.5

10

ms

NOTE:
1)Typical program time is measured at Vcc=3.3V, TA=25°C. Not 100% tested.
2) Typical Program time is defined as the time within which more than 50% of the whole pages are programed at 3.3V Vcc and 25°C temperature.
3) Within a same block, program time(tPROG) of page group A is faster than that of page group B. Typical tPROG is the average program time of the page group A and
B(Table 5).
Page Group A: Page 0, 1, 3, 5, 7, ... , 77,79,7B,7D
Page Group B: Page 2, 4, 6, 8, 0A, ... , 7A,7C,7E,7F
4) tCBSY depends on the timing between internal programming time and data in time.

2.9 AC Timing Characteristics for Command / Address / Data Input
Parameter
CLE Setup Time

Symbol

Min

tCLH

CE Setup Time

(1)

Unit

-

ns

5

tCLS

CLE Hold Time

Max

15

(1)

-

ns

25

-

ns

tCH

5

-

ns

WE Pulse Width

tWP

15

-

ns

ALE Setup Time

tALS(1)

15

-

ns

tCS

CE Hold Time

ALE Hold Time

tALH

5

-

ns

Data Setup Time

tDS(1)

15

-

ns

Data Hold Time

tDH

5

-

ns

Write Cycle Time

tWC

30

-

ns

WE High Hold Time

tWH

10

-

ns

Address to Data Loading Time

ADL(2)

300

-

ns

t

NOTES : 1. The transition of the corresponding control pins must occur only once while WE is held low
2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle

- 13 -

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

Final Rev. 0.9.1

datasheet

FLASH MEMORY

2.10 AC Characteristics for Operation
Parameter

Symbol

Min

Max

Unit

tR

-

400

?s

Data Transfer from Cell to Register
ALE to RE Delay

tAR

10

-

ns

CLE to RE Delay

tCLR

10

-

ns

Ready to RE Low

tRR

20

-

ns

RE Pulse Width

tRP

15

-

ns

100

WE High to Busy

tWB

-

WP High to WE Low

tWW

100

ns
ns

Read Cycle Time

tRC

30

-

ns

RE Access Time

tREA

-

25

ns

CE Access Time

tCEA

-

35

ns

RE High to Output Hi-Z

tRHZ

-

100

ns

CE High to Output Hi-Z

tCHZ

-

30

ns

CE High to ALE or CLE Don't Care

tCSD

0

-

ns

RE High to Output Hold

tRHOH

15

-

ns

RE Low to Output Hold

tRLOH

5

-

ns

RE High Hold Time

tREH

10

-

ns

Output Hi-Z to RE Low

tIR

0

-

ns

RE High to WE Low

tRHW

100

-

ns

WE High to RE Low

tWHR

60

-

ns

Device Resetting Time(Read/Program/Erase)

tRST

-

10/30/500(1)

?s

tDCBSYR

-

400

?s

Cache Busy in Read Cache (following 31h and 3Fh)

Note :
1) If reset command(FFh) is written at Ready state, the device goes into Busy for maxium 10us.

- 14 -

Final Rev. 0.9.1

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

FLASH MEMORY

3.0 NAND FLASH TECHNICAL NOTES
3.1 Initial Invalid Block(s)
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information
regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices
with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not affect the performance of valid block(s) because it
is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the initial invalid block(s) via
address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment.

3.2 Initial Invalid Block(s)
All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The initial invalid block(s)
status is defined by the 1st byte in the spare area. Samsung makes sure that the first or the last page of every initial invalid block has non-FFh data at the
column address of 0 or 8,192.The initial invalid block information is also erasable in most cases, and it is impossible to recover the information once it has
been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the initial invalid block information and create the initial
invalid block table via the following suggested flow chart. Any intentional erasure of the initial invalid block information is prohibited

Start

Block No = 1

Read FFh Check
Column 0 or 8192
of the First page
Block No. = Block No. + 1

Fail

Pass

Read FFh Check
Column 0 or 8192
of the last page
Pass

Fail

Entry Bad Block 1)

No
Last Block
Yes
End

Figure 3. Flow Chart to Create Initial Invalid Block Table

NOTE :
1) No Erase Operation is allowed to detected bad block

- 15 -

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

Final Rev. 0.9.1

FLASH MEMORY

3.3 Error in write or read operation
Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data. Block replacement
should be done upon erase or program error.

Failure Mode

Detection and Countermeasure sequence

Erase Failure

Status Read after Program -- & gt; Block Replacement

Up to 24 Bit Failure

Read

Status Read after Erase -- & gt; Block Replacement

Program Failure

Write

Verify ECC - & gt; ECC Correction

ECC

: Error Correcting Code -- & gt; RS Code or BCH Code etc.
Example) 24bit correction / 1K+54.5 byte

Program Flow Chart

Start

Write 80h

Write Address

Write Data

Write 10h

Read Status Register

I/O 6 = 1 ?
or R/B = 1 ?

*
Program Error

No

Yes
No

I/O 0 = 0 ?

Yes
Program Completed

*

: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.

- 16 -

Final Rev. 0.9.1

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

FLASH MEMORY

NAND Flash Technical Notes (Continued)

Erase Flow Chart

Read Flow Chart
Start

Start

Write 60h

Write 00h

Write Block Address

Write Address

Write D0h

Write 30h

Read Status Register

Read Data
ECC Generation
No

I/O 6 = 1 ?
or R/B = 1 ?

No

*
Erase Error

No

Verify ECC

Reclaim the Error

Yes

Yes

I/O 0 = 0 ?

Page Read Completed

Yes
Erase Completed

*

: If erase operation results in an error, map out
the failing block and replace it with another block.

Block Replacement
1st

~
(n-1)th
nth

{

Block A

1
an error occurs.

(page)

1st

~
(n-1)th
nth

Buffer memory of the controller.

{

Block B
2

(page)

* Step1
When an error happens in the nth page of the Block 'A' during erase or program operation.
* Step2
Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block 'B')
* Step3
Then, copy the nth page data of the Block 'A' in the buffer memory to the nth page of the Block 'B'.
* Step4
Do not erase or program Block 'A' by creating an 'invalid block' table or other appropriate scheme.

- 17 -

Final Rev. 0.9.1

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

FLASH MEMORY

3.4 Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most significant bit) pages of
the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB among the pages to be programmed.
Therefore, LSB doesn't need to be page 0.
Page 127

(128)

Page 31

Page 127

(128)

:

:

(32)

Page 31

(1)

:

Page 2
Page 1
Page 0

:

(3)
(2)
(1)

Page 2
Page 1
Page 0

Data register

Data register

From the LSB page to MSB page
DATA IN: Data (1)

(3)
(32)
(2)

Ex.) Random page program (Prohibition)

Data (128)

DATA IN: Data (1)

- 18 -

Data (128)

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

Final Rev. 0.9.1

FLASH MEMORY

Paired Page Address Information
Paired Page Address(1/2)

Paired Page Address(2/2)

Group A

Group B

Group A

Group B

00h

02h

3Fh

42h

01h

04h

41h

44h

03h

06h

43h

46h

05h

08h

45h

48h

07h

0Ah

47h

4Ah

09h

0Ch

49h

4Ch

0Bh

0Eh

4Bh

4Eh

0Dh

10h

4Dh

50h

0Fh

12h

4Fh

52h

11h

14h

51h

54h

13h

16h

53h

56h

15h

18h

55h

58h

17h

1Ah

57h

5Ah

19h

1Ch

59h

5Ch

1Bh

1Eh

5Bh

5Eh

1Dh

20h

5Dh

60h

1Fh

22h

5Fh

62h

21h

24h

61h

64h

23h

26h

63h

66h

25h

28h

65h

68h

27h

2Ah

67h

6Ah

29h

2Ch

69h

6Ch

2Bh

2Eh

6Bh

6Eh

2Dh

30h

6Dh

70h

2Fh

32h

6Fh

72h

31h

34h

71h

74h

33h

36h

73h

76h

35h

38h

75h

78h

37h

3Ah

77h

7Ah

39h

3Ch

79h

7Ch

3Bh

3Eh

7Bh

7Eh

3Dh

40h

7Dh

7Fh

NOTE :
When program operation is abnormally aborted (ex. power-down, reset), not only page data under program but also paired page data may be damaged.

- 19 -

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

Final Rev. 0.9.1

datasheet

FLASH MEMORY

3.5 Interleaving operation
K9LBG08U0E and K9HCG08U1E devices are composed of two chips sharing per CE pin. They provide interleaving operation between two chips
This interleaving operation improves the system throughput almost twice compared to non-interleaving operation.
At first, the host issues a operation command to one of the LSB chips, say (chip #1). Due to DDP device goes into busy state. During this time, MSB chip
(chip #2) is in ready state. So it can execute the operation command issued by the host.
After the execution of operation by LSB chip (chip #1), it can execute another operation regardless of MSB chip (chip #2). Before that the host needs to
check the status of LSB chip (chip #1) by issuing F1h command. Only when the status of LSB chip (chip #1) becomes ready status, host can issue
another operation command. If LSB chip (chip #1) is in busy state, the host has to wait for LSB chip (chip #1) to get into ready state.
Similarly, MSB chip (chip #2) can execute another operation after the completion of the previous operation. The host can monitor the status of MSB chip
(chip #2) by issuing F2h command. When MSB chip (chip #2) shows ready state, host can issue another operation command to MSB chip (chip #2).
This interleaving algorithm improves the system throughput almost twice. The host can issue page operation command to each chip individually. This
reduces the time lag for the completion of operation.
NOTES : During interleave operations, 70h command is prohibited.
[Table 2] F1h Read Status Register Definition
I/O No.

Page Program

Block Erase

Read

Definition

I/O 0

Chip1 Pass/Fail

Chip1 Pass/Fail

Not use

Pass : " 0 "

Fail : " 1 "

I/O 1

Plane Pass/Fail

Plane Pass/Fail

Not use

Pass : " 0 "

Fail : " 1 "

I/O 2

Not Use

Not Use

Not use

Don't -cared

I/O 3

Not Use

Not Use

Not Use

Don't -cared

I/O 4

Not Use

Not Use

Not Use

Don't -cared

I/O 5

Not Use

Not Use

Not Use

I/O 6

Ready/Busy

Ready/Busy

Ready/Busy

Busy : " 0 "

Don't -cared

I/O 7

Write Protect

Write Protect

Write Protect

Protected : " 0 "

Ready : " 1 "
Not Protected : " 1 "

NOTE : 1. I/Os defined 'Not use' are recommended to be masked out when Read Status is being executed.

[Table 3] F2h Read Status Register Definition
I/O No.

Page Program

Block Erase

Read

Definition

I/O 0

Chip2 Pass/Fail

Chip2 Pass/Fail

Not use

Pass : " 0 "

Fail : " 1 "

I/O 1

Plane Pass/Fail

Plane Pass/Fail

Not use

Pass : " 0 "

Fail : " 1 "

I/O 2

Not Use

Not Use

Not use

Don't -cared

I/O 3

Not Use

Not Use

Not Use

Don't -cared

I/O 4

Not Use

Not Use

Not Use

Don't -cared

I/O 5

Not Use

Not Use

Not Use

Don't -cared

I/O 6

Ready/Busy

Ready/Busy

Ready/Busy

Busy : " 0 "

I/O 7

Write Protect

Write Protect

Write Protect

Protected : " 0 "

NOTE : 1. I/Os defined 'Not use' are recommended to be masked out when Read Status is being executed.

- 20 -

Ready : " 1 "
Not Protected : " 1 "

Final Rev. 0.9.1

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

FLASH MEMORY

3.5.1 Interleaving Page Program

1
I/OX

80h

Add & Data

10h

Add & Data

80h

10h

Chip Address : High

Chip Address : Low

busy of Chip #1

?

R/B (#1)
internal only

busy of Chip #2

?

R/B (#2)
internal only

?

R/B

A

B

1
another page program on Chip #1
" 1 "

" 1 "

I/OX

F1h

I/O6

F2h

I/O6

Ready

busy of Chip #1

?

internal only

R/B (#2)

busy of Chip #2

?

internal only

Busy

Busy

R/B (#1)

Ready

" 0 "

" 0 "

?

R/B

C

B

D

State A : Chip #1 is executing page program operation and chip #2 is in ready state. So the host can issue page program command to chip #2.
State B : Both chip #1 and chip #2 are executing page program operation.
State C : Page program on chip #1 is terminated, but page program on chip #2 is still operating. And the system should issue F1h /F2hcommand to detect the status of chip
#1. If chip #1 is ready, status I/O6 is " 1 " and the system can issue another page program command to chip #1.
State D : Chip #1 and Chip #2 are ready.
According to the above process, the system can operate page program on chip #1 and chip #2 alternately.

- 21 -

Final Rev. 0.9.1

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

FLASH MEMORY

3.5.2 Interleaving Page Read

" 1 "

" 1 "

I/OX

00h

Add

30h

00h

Chip Address: Low

Add

30h

I/O6

F1h

Chip Address: High

Ready

Ready

" 0 "
Busy

" 0 "
Busy

R/B (#1)

I/O6

F2h

internal only

R/B (#2)
internal only

R/B
A

00h

I/OX

Add

05h

Chip Address: Low

B

Add

C

1

Data Out

E0h

00h

Add

Column Address

R/B (#1)
internal only

R/B (#2)
internal only

R/B
D

1

I/OX

Add

05h

Col.Add E0h

2

Data Out

R/B (#1)
internal only

R/B (#2)
internal only

R/B
E
2

State A : Chip #1 is executing page read operation, and chip #2 is in ready state. So the host can issue page read command to chip #2.
State B : Both chip #1 and chip #2 are executing page read operation.
State C : Page read on chip #1 is completed and chip #2 is still executing page read operation.
State D : Before the host read the data, the host should check the Ready/Busy status for both chips by F1h and F2h commands.
State E : Chip #1 and Chip #2 are ready.
Note : *F1h command is required to check the status of chip #1.
F2h command is required to check the status of chip #2.

- 22 -

Final Rev. 0.9.1

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

FLASH MEMORY

3.5.3 Interleaving Block Erase

I/OX

60h

Add

60h

D0h

Add

D0h

Chip Address : High

Chip Address : Low

busy of Chip #1

?

R/B (#1)
internal only

?

R/B (#2)
internal only

?

R/B

A

B
1

another block erase on Chip #1
" 1 "
F1h

I/OX

I/O6

" 1 "
Ready

F2h

I/O6

" 0 "
Busy

internal only

busy of Chip #2

?

R/B (#2)
internal only

Busy

?

R/B (#1)

Ready

" 0 "

?

R/B

B 1

C

D

State A : Chip #1 is executing block erase operation, and chip #2 is in ready state. So the host can issue block erase command to chip #2.
State B : Both chip #1 and chip #2 are executing block erase operation.
State C : Block erase on chip #1 is terminated, but block erase on chip #2 is still operating. And the system should issue F1h /F2hcommand to detect the status of chip #1. If
chip #1 is ready, status I/O6 is " 1 " and the system can issue another block erase command to chip #1.
State D : Chip #1 and Chip #2 are ready.
According to the above process, the system can operate block erase on chip #1 and chip #2 alternately.

- 23 -

Final Rev. 0.9.1

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

FLASH MEMORY

3.5.4 Interleaving Read to Page Program

" 1 "

I/OX

80h

00h

10h

Data in

Add
Chip Address : Low

Add

30h

F2h

I/O6

Chip Address : High

R/B (#1)

tPROG of

internal only

Ready

" 0 "
Busy

chip #1

R/B (#2)

tR of

internal only

chip #2

R/B

A

B

1
" 1 "

I/OX

00h

Add

Chip Address : High

05h

E0h

Add
Column Address

tPROG of

F1h

I/O6
" 0 "
Busy

R/B (#1)
internal only

Data out

chip #1

R/B (#2)
internal only

R/B
1

C

D

State A : Chip #1 is executing page program operation, and chip #2 is in ready state. So the host can issue read command to chip #2.
State B : Both chip #1 is executing page program operation and chip #2 is executing read operation.
State C : Read operation on chip #2 is completed and chip #2 is ready for the next operation. Chip #1 is still executing page program operation.
State D : Both chip #1 and chip #2 are ready.
Note :
*F1h command is required to check the status of chip #1 to issue the next command to chip #1.
F2h command is required to check the status of chip #2 to issue the next command to chip #2.
As the above process, the system can operate Interleave read to page porgram on chip #1 and chip #2 alternatively.

- 24 -

Ready

Final Rev. 0.9.1

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

FLASH MEMORY

3.5.5 Interleaving Copy-Back Program
" 1 "

I/OX

00h

F1h

35h

Add

I/O6

Chip Address : Low

Ready

00h

Chip Address : Low

" 0 "
Busy

R/B (#1)

tR of

internal only

05h

Add

E0h

Add
Column Address

chip #1

R/B (#2)
internal only

R/B
1
" 1 "

I/OX

85h

10h

Add & Data

00h

Chip Address : Low

F2h

35h

Add

I/O6

Chip Address : High

Ready

00h

" 0 "
Busy

R/B (#1)

tPROG of

internal only

R/B (#2)

tR of

chip #1

chip #2

internal only

R/B
A

1

I/OX

E0h

Add

05h

Add

Chip Address : High

B

85h

Data Out

Add & Data

2

C

10h

F1h

Chip Address : High

Column Address

R/B (#1)
internal only

R/B (#2)
internal only

R/B
2

3

D
" 1 "

I/OX

F1h

I/O6

" 1 "

F2h

Ready

" 0 "
Busy

I/O6

Ready

" 0 "
Busy

R/B (#1)
internal only

tPROG of

chip #2

R/B (#2)
internal only

R/B
3

E

F

State A : Chip #1 is executing copy-back program operation, and chip #2 is in ready state. So the host can issue read for copy-back command to chip #2.
State B : Chip #1 is executing copy-back program operation and chip #2 is executing read for copy-back operation.
State C : Read for copy-back operation on chip #2 is completed and chip #2 is ready for the next operation. Chip #1 is still executing copy-back program operation.
State D : Both chip #1 and chip #2 are executing copy-back program operation.
State E : Chip #2 is still executing a copy-back program operation, and chip #1 is in ready for the next operation.
State F : Both chip #1 and chip #2 are ready.
Note :
*F1h command is required to check the status of chip #1 to issue the next command to chip #1.
F2h command is required to check the status of chip #2 to issue the next command to chip #2.
As the above process, the system can operate Interleave copy-back program on chip #1 and chip #2 alternatively.

- 25 -

Final Rev. 0.9.1

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

FLASH MEMORY

3.6 System Interface Using CE don't-care.

?

?

CLE

?

For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 8,628byte data registers are
utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle
time on the order of ?-seconds, de-activating CE during the data-loading and serial access would provide significant savings in power consumption.

I/Ox

?

ALE

80h

Address(5Cycles)

tCS

?

??

WE

? ?

?

CE

? ?

CE don't-care

Data Input

tCH

Data Input

10h

tCEA
CE

CE

tREA
tWP

RE

WE
out

I/O0~7

?

CLE

?

Figure 4. Program Operation with CE don't-care.

CE don't-care

?

ALE

tR

?

R/B

??

? ? ?

RE

?

WE
I/Ox

? ?

CE

00h

Address(5Cycle)

Data Output(serial access)

30h

Figure 5. Read Operation with CE don't-care.

- 26 -

Final Rev. 0.9.1

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

FLASH MEMORY

4.0 TIMING DIAGRAMS
4.1 Command Latch Cycle
CLE
tCLS

tCLH

tCS

tCH

CE

tWP
WE

tALH

tALS
ALE

tDH

tDS
I/Ox

Command

4.2 Address Latch Cycle
tCLS
CLE
tCS
tWC

tWC

tWC

tWC

CE

tWP

tWP

tWP

tWP

WE
tWH
tALH

tALS

tWH
tALS

tALH

tALS

tWH
tALH

tALS

tWH
tALH

tALS

tALH

ALE
tDS
I/Ox

tDH

Col. Add1

tDS

tDH

Col. Add2

- 27 -

tDS

tDH

Row Add1

tDS

tDH

Row Add2

tDS

tDH

Row Add3

Final Rev. 0.9.1

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

FLASH MEMORY

4.3 Input Data Latch Cycle
tCLH

?

CLE

tCH

?

CE

tWC

?

ALE

tWP

?

tALS
tWP

tWP

WE
tWH
tDH

tDS

tDH

tDS

tDH

?

tDS
I/Ox

DIN final

DIN 1

?

DIN 0

4.4 * Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)
tRC

?

CE

tCHZ

tREH

?

tREA

tREA

tREA

RE
tRHZ

tRHZ

I/Ox

Dout

Dout

?

tRHOH

?

tRR
R/B

NOTES :
1)Transition is measured at ?200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
2) tRLOH is valid when frequency is higher than 20MHz.
tRHOH starts to be valid when frequency is lower than 20MHz.

- 28 -

Dout

Final Rev. 0.9.1

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

FLASH MEMORY

4.5 Serial Access Cycle after Read(EDO Type, CLE=L, WE=H, ALE=L)

?

CE
tRC

tCHZ
tREH

?

tRP
RE

tCEA
I/Ox

tRHZ

tREA
tRLOH

tRHOH

? ?

tREA

Dout

?

tRR

Dout

R/B
NOTES :
1) Transition is measured at ?200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
2) tRLOH is valid when frequency is higher than 20MHz.
tRHOH starts to be valid when frequency is lower than 20MHz.

4.6 Status Read Cycle
tCLR
CLE
tCLS

tCLH

tCS
CE
tCH
tWP
WE

tCEA

tCHZ

tWHR
RE
tDS
I/Ox

tDH

tIR

tREA

tRHZ
tRHOH

Status Output

70h/F1h/F2h

- 29 -

Final Rev. 0.9.1

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

FLASH MEMORY

4.7 Read Operation
tCLR
CLE

CE
tWC
WE
tWB
tAR
ALE
tR

tRHZ

tRC

?

RE

I/Ox

00h

Col. Add1

Col. Add2

Row Add1

Column Address

Row Add2 Row Add3

30h

Dout N

Dout N+1

? ?

tRR
Dout M

Row Address
Busy

R/B

4.8 Read Operation(Intercepted by CE)
tCLR
CLE

CE
tCSD
WE

tCHZ
tWB
tAR

ALE
tRC

tR
RE
tRR
I/Ox

00h

Col. Add1

Col. Add2

Column Address

Row Add1

Row Add2 Row Add3

30h

Dout N

Row Address

Busy

R/B

- 30 -

Dout N+1

Dout N+2

- 31 -

R/B

I/Ox

RE

ALE

WE

CE

CLE

00h
Col. Add2

Column Address

Col. Add1

Row Add2 Row Add3

Row Address

Row Add1

30h/35h

Busy

tRR

tR

tWB

tAR

Dout N

tRC

Dout N+1

tRHW

05h

Col. Add2

Column Address

Col. Add1

E0h

tREA

tWHR

tCLR

Dout M

Dout M+1

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

datasheet
Final Rev. 0.9.1

FLASH MEMORY

4.9 Random Data Output In a Page

- 32 -

R/B

I/Ox

RE

ALE

WE

CE

CLE

Col. Add1

Col. Add2

Row Add1

Row Add2

Row Add3

30h

tWB

NOTE : 1. The column address will be reset to 0 by the 31h command input.
2. Cache Read operation is available only within a block.

00h

tWC

tR

31h

tWB

tRR

tDCBSYR

Col. Add. 0

Page Address M

D0 D1

tRC

?
?
DOUT

1

31h

tWB

tRR

tDCBSYR

Col. Add. 0

Page Address M+1

D0

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

datasheet
Final Rev. 0.9.1

FLASH MEMORY

4.10 Cache Read Operation(1/2)

- 33 -

R/B

I/Ox

RE

ALE

WE

DOUT

tRR

Col. Add. 0

Page Address M+2

D0 D1

tRC

DOUT

31h

tWB
tRR

tDCBSYR

Col. Add. 0

Page Address M+3

D0 D1

tRC

DOUT

3Fh

tWB
tDH

tDCBSYR

Col. Add. 0

Page Address M+4

D0 D1

tRC

datasheet

NOTE : 1. The column address will be reset to 0 by the 31h and 3Fh command input.
2. Cache Read operation is available only within a block.

1

31h

tWB

tDCBSYR

?
?

CE

?
?

CLE

?
?

K9GAG08U0E
K9LBG08U0E K9HCG08U1E
Final Rev. 0.9.1

FLASH MEMORY

4.11 Cache Read Operation(2/2)

Final Rev. 0.9.1

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

FLASH MEMORY

4.12 Page Program Operation
CLE

CE
tWC

?

tWC

tWC

WE
tWB

tADL

tPROG

tWHR

ALE

I/Ox

80h

Co.l Add1 Col. Add2

SerialData
Column Address
Input Command

Row Add1

Row Add2 Row Add3

Row Address

? ?

RE
Din
Din
N
M
1 up to m Byte
Serial Input

Program
Command

NOTE :
tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.

- 34 -

I/O0

Read Status
Command

?

R/B

70h
/F!h

10h

I/O0=0 Successful Program
I/O0=1 Error in Program

- 35 -

R/B

I/Ox

RE

ALE

WE

Col. Add1

Col. Add2

Row Add2 Row Add3

Row Address

Row Add1

tWC

tADL

Din
M
85h
Col. Add1

Col. Add2

Serial Input Random Data Column Address
Input Command

Din
N

tWC

tADL

Din
K
Serial Input

Din
J

NOTE : 1. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.

Serial Data
Column Address
Input Command

80h

tWC

?
? ?

CE

?
? ?

CLE

Program
Command

10h

tWB

tPROG

?

I/O0

I/O0=0 Successful Program
I/O0=1 Error in Program

Read Status
Command

70h

tWHR

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

datasheet
Final Rev. 0.9.1

FLASH MEMORY

4.13 Page Program Operation with Random Data Input

- 36 -

R/B

I/Ox

RE

ALE

WE

CE

Column Address

Row Address

Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3

35h

tWB

tR

Busy

Data 1

tRC

? ?
Data N
Column Address

Row Address

Data 1

tADL

Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3

Copy-Back Data
Input Command

85h

NOTE : 1. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.

00h

tWC

?

CLE

Data N

10h

tWB

70h

I/Ox

tWHR

Read Status Command

tPROG

I/O0=0 Successful Program
I/O0=1 Error in Program

Busy

?

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

datasheet
Final Rev. 0.9.1

FLASH MEMORY

4.14 Copy-Back Program Operation with Random Data Input

? ?

R/B

I/Ox

RE

ALE

? ?
Din
M

Serial Input

Din
N

?

- 37 -

15h
Program
Command
(Dummy)

tCBSY

tCBSY : max. 4ms

80h

Last Page Input & Program

Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3

tADL

Din
N

I/Ox

Address &
15h
Data Input
Col. Add1,2 & Row Add1,2, 3
Data

80h

tCBSY

80h

Address &
Data Input

15h

tCBSY

80h

Address &
Data Input

15h

tCBSY

80h

Address &
Data Input

I/O

10h

70h
/

tPROG*2

70h

datasheet

R/B

Ex.) Cache Program

tWB tPROG*2

Din
10h
M
Program Confirm
Command
(True)

NOTE : 1. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
2. Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if
the previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only
after completion of the previous cycle, which can be expressed as the following formula.
tPROG = Program time for the last page + Program time for the ( last -1)th page
- (command input cycle time + address input cycle time + Last page data loading time)

Max. 127 times repeatable

Row Address

Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3

Serial Data Column Address
Input Command

80h

tADL

tWB

?

WE

tWC

?
? ?

CE

?

CLE

K9GAG08U0E
K9LBG08U0E K9HCG08U1E
Final Rev. 0.9.1

FLASH MEMORY

4.15 Cache Program Operation(available only within a block)

Final Rev. 0.9.1

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

FLASH MEMORY

4.16 Block Erase Operation
CLE

CE
tWC
WE
tWB

tBERS
tWHR

ALE

RE

I/Ox

60h

Row Add1

Row Add2 Row Add3

70h

D0h

I/O 0

Busy

R/B
Auto Block Erase
Setup Command

Erase Command

?

Row Address

Read Status
Command

- 38 -

I/O0=0 Successful Erase
I/O0=1 Error in Erase

Final Rev. 0.9.1

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

FLASH MEMORY

4.17 Read ID Operation
CLE

CE

WE
tAR
ALE

RE
tREA
I/Ox

00h

90h
Read ID Command

Address 1cycle

Device
Code

ECh

3rd cyc.

5th cyc.

6th cyc.

Maker Code Device Code

Device

Device Code (2nd Cycle)

3rd Cycle

K9GAG08U0E

D5h

84h

D7h

C5h

K9LBG08U0E

4th cyc.

4th Cycle

5th Cycle

6th Cycle

50h
72h

K9HCG08U1E

- 39 -

54h

42h

Final Rev. 0.9.1

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

FLASH MEMORY

4.17.1 ID Definition Table
Description
st

1 Byte
2nd Byte
3rd Byte
4th Byte
5th Byte
6th Byte

Maker Code
Device Code
Internal Chip Number, Cell Type, Number of Simultaneously Programmed Pages, Etc.
Page Size, Block Size,Redundant Area Size.
Plane Number, ECC Level, Organization.
Device Technology, EDO, Interface.

3rd ID Data
Description

I/O7

I/O6

I/O5 I/O4

I/O3 I/O2

I/O1 I/O0
0
0
1
1

Internal Chip Number

1
2
4
8

Cell Type

2 Level Cell
4 Level Cell
8 Level Cell
16 Level Cell

Number of
Simultaneously
Programmed Pages

1
2
4
8

Interleave Operation
Between multiple chips

Not Support
Support

Cache Operation

Not Support
Support

0
0
1
1
0
0
1
1

0
1
0
1

0
1
0
1

0
1
0
1

0
1
0
1

4th ID Data
Description
Page Size
(w/o redundant area )

Block Size
(w/o redundant area )

Redundant Area Size
( byte / Page Size)

I/O6

I/O5 I/O4

I/O3

I/O2

I/O1 I/O0
0
0
1
1

2KB
4KB
8KB
Reserved
128KB
256KB
512KB
1MB
Reserved
Reserved
Reserved
Reserved

I/O7

Reserved
128B
218B
400B
436B
Reserved
Reserved
Reserved

0
0
1
1
0
0
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

- 40 -

0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
1
0
1

Final Rev. 0.9.1

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

FLASH MEMORY

5th ID Data
Description

I/O7

I/O6

I/O5

I/O4

I/O3 I/O2

Plane Number

ECC Level

1bit / 512B
2bit / 512B
4bit / 512B
8bit / 512B
16bit / 512B
24bit / 1KB
Reserved
Reserved

0
0
0
0
1
1
1
1

Reserved

0
0
1
1
0
0
1
1

I/O1

I/O0

0

0
0
1
1

1
2
4
8

0

0
1
0
1

0
1
0
1
0
1
0
1

0

6th ID Data
Description

Device Version

EDO

SDR
DDR

I/O6

I/O5

I/O4

I/O3

0
1
0
1

Reserved

0

- 41 -

0

0

I/O2

I/O1

I/O0

0
0
0
0
1
1
1
1

Not Support
Support

Interface

I/O7

50nm
40nm
30nm
Reserved
Reserved
Reserved
Reserved
Reserved

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
0

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

datasheet

Final Rev. 0.9.1

FLASH MEMORY

5.0 DEVICE OPERATION
5.1 Page Read
Page read is initiated by writing 00h-30h to the command register along with five address cycles. The 8,628 bytes of data within the selected page are
transferred to the cache registers via data registers in less than 400?s(tR). The system controller can detect the completion of this data transfer(tR) by
analyzing the output of R/B pin. Once the data in a page is loaded into the cache registers, they may be read out in 30ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the data starting from the selected column address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random data output command. The column address
of next data, which is going to be out, may be changed to the address which follows random data output command. Random data output can be operated
multiple times regardless of how many times it is done in a page.

?

CLE

?

CE

??

WE

?

ALE

RE
I/Ox

tR

?

R/B

00h

Address(5Cycle)

Data Output(Serial Access)

30h

Col. Add.1,2 & Row Add.1,2,3

Data Field

Spare Field

Figure 6. Read Operation

- 42 -

Final Rev. 0.9.1

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

FLASH MEMORY

tR

R/B
RE
I/Ox

00h

Address
5Cycles

Data Output

30h/35h

Col. Add.1,2 & Row Add.1,2,3

05h

Address
2Cycles

E0h

Data Output

Col. Add.1,2

Data Field

Spare Field

Data Field

Spare Field

Figure 7. Random Data Output In a Page

5.2 CACHE READ
Cache Read is an extension of Page Read, which is executed with 8,628byte data registers, and is available only within a block. Since the device has 1
page of cache memory, serial data output may be executed while data in the memory cell is read into data registers.
Cache read is also initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command is latched.
Therefore only five address cycles and 30h command initiates that operation after initial power up. The 8,628 bytes of data within the selected page are
transferred to the cache registers via data registers in less than 400?s(tR). After issuing Cache Read command(31h), read data in the data registers is
transferred to cache registers for a short period of time(tDCBSYR). While the data in the cache registers is read out in 30ns cycle time by sequentially pulsing RE, data of next page is transferred to the data registers. By issuing Last Cache Read command(3Fh), last data is transferred to the cache registers
from the data registers after the completion of transfer from memory cell to data registers. Cache Read is available only within a block.

- 43 -

1

00h

Page Row
Address

Figure 8. Cache Read

- 44 -

30h

Page N

Column
Address

1

30h
tR

1

2

2
0

2

3

31h & RE clock

Page N+1

3

2

3

4

4
1

2

31h & RE clock

Page N+2

5

Page Address N+1

0

Page N+1

tDCBSYR

8627 31h

Page N

Page Address N

1

Page N

Column 0
tDCBSYR

31h

3

5

5

Page N+1

6

6

1

2

3Fh & RE clock

7

Page Address N+2

0

Page N+2

tDCBSYR

8627 3Fh

3

7

Page N+2

8627

datasheet

NOTE
-. If the 31h command is issued to the device, the data content of the next page is transferred to the data registers during serial data out from the cache registers, and therefore the tR
(Data transfer from memory cell to data register) will be reduced.
1. Normal read. Data is transferred from Page N to cache registers through data registers. During this time period, the device outputs Busy state for tR max.
2. After the Ready/Busy returns to Ready, 31h command is issued and data is transferred to cache registers from data registers again. This data transfer takes tDCBSYR max and the
completion of this time period can be detected by Ready/Busy signal.
3. Data of Page N+1 is transferred to data registers from cell while the data of Page N in cache registers can be read out by RE clock simultaneously.
4. The 31h command makes data of Page N+1 transfer to cache registers from data registers after the completion of the transfer from cell to data registers. The device outputs Busy
state for tDCBSYR max..This Busy period depends on the combination of the internal data transfer time from cell to data registers and the serial data out time.
5. Data of Page N+2 is transferred to data registers from cell while the data of Page N+1 in cache registers can be read out by RE clock simultaneously.
6. The 3Fh command makes the data of Page N+2 transfer to the cache registers from the data registers after the completion of transfer form cell to data registers. The device outputs
Busy state for tDCBSYR max.This Busy period depends on the combination of the internal data transfer time from cell to data registers and the transfer from data registers to cache
registers.
7. Data of Page N+2 in cache registers can be read out, but since the 3Fh command does not transfer the data from the memory cell to data registers, the device can accept new
command input immediately after the completion of serial data out.

Data register

Cache register

R/B

I/Ox

RE

ALE

WE

CE

CLE

The device has a Read operation with cache registers that enables the high speed read operation shown below. When the block address changes, this sequence has to be started
from the beginning.

K9GAG08U0E
K9LBG08U0E K9HCG08U1E
Final Rev. 0.9.1

FLASH MEMORY

Final Rev. 0.9.1

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

FLASH MEMORY

5.3 Page Program
The device is programmed basically on a page basis, and the number of consecutive partial page programming operation within the same page without
an intervening erase operation must not exceed 1 time for the page. The addressing should be done in sequential order in a block. A page program cycle
consists of a serial data loading period in which up to 8,628bytes of data may be loaded into the data registers via cache registers, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs and then serial data
loading. The words other than those to be programmed do not need to be loaded. The device supports random data input in a page. The column address
for the next data, which will be entered, may be changed to the address which follows random data input command(85h). Random data input may be
operated multiple times regardless of how many times it is done in a page.
The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate
the programming process. The internal write state controller automatically executes the algorithms and timings necessary for program and verify, thereby
freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only
the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/
O 0) may be checked. The internal write verify detects only errors for " 1 " s that are not successfully programmed to " 0 " s. The command register remains
in Read Status command mode until another valid command is written to the command register.

tPROG
R/B
I/Ox

80h

Address & Data Input

" 0 "

70h

10h

Pass

I/O0

Col. Add.1,2 & Row Add.1,2,3

" 1 "

Data

Fail

Figure 9. Program & Read Status Operation

tPROG
R/B
" 0 "

I/Ox

80h

Address & Data Input
Col. Add.1,2 & Row Add1,2,3
Data

85h

Address & Data Input

10h

Col. Add.1,2
Data

70h

I/O0
" 1 "
Fail

Figure 10. Random Data Input In a Page

- 45 -

Pass

Final Rev. 0.9.1

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

FLASH MEMORY

5.4 Copy-back Program
Copy-Back program with Read for Copy-Back is configured to quickly and efficiently rewrite data stored in one page without data re-loading when the bit
error is not in data stored. Since the time-consuming re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also needs to be copied to the newly assigned free block. Copy-Back operation is a
sequential execution of Read for Copy-Back and of copy-back program with the destination page address. A read operation with " 35h " command and the
address of the source page moves the whole 8,628byte data into the internal data buffer. A bit error is checked by sequential reading the data output. In
the case where there is no bit error, the data do not need to be reloaded. Therefore Copy-Back program operation is initiated by issuing Page-Copy DataInput command (85h) with destination page address. Actual programming operation begins after Program Confirm command (10h) is issued. Once the
program process starts, the Read Status Register command (70h) may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. When the Copy-Back Program is complete, the
Write Status Bit(I/O 0) may be checked. The command register remains in Read Status command mode until another valid command is written to the
command register.
During copy-back program, data modification is possible using random data input command (85h) as shown below.

tR

tPROG
?

R/B

00h

Add.(5Cycles)

Data Output

35h

?

I/Ox

Col. Add.1,2 & Row Add.1,2,3
Source Address

85h

Add.(5Cycles)

70h

10h

I/O0

Col. Add.1,2 & Row Add.1,2,3
Destination Address

" 0 "

Pass

" 1 "
Fail

Figure 11. Page Copy-Back Program Operation

tPROG

tR
?

R/B

00h

Add.(5Cycles)

35h

Col. Add.1,2 & Row Add.1,2,3
Source Address

Data Output

?

I/Ox

85h

Add.(5Cycles)

Data

Col. Add.1,2 & Row Add.1,2,3

85h

Add.(2Cycles)

Data

10h

Col. Add.1,2

Destination Address
There is no limitation for the number of repetition.

Figure 12. Page Copy-Back Program Operation with Random Data Input

- 46 -

70h

Final Rev. 0.9.1

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

FLASH MEMORY

5.5 Cache Program
Cache Program is an extension of Page Program, which is executed with 8,628byte data registers, and is available only within a block. Since the device
has 1 page of cache memory, serial data input may be executed while data stored in data registers are programmed into memory cell.
After writing the first set of data up to 8,628byte into the selected cache registers, Cache Program command (15h) instead of actual Page Program (10h)
is inputted to make cache registers free and to start internal program operation. To transfer data from cache registers to data registers, the device remains
in Busy state for a short period of time(tCBSY) and has its cache registers ready for the next data-input while the internal programming gets started with
the data loaded into data registers. Read Status command (70h) may be issued to find out when cache registers become ready by polling the Cache-Busy
status bit(I/O 6). Pass/fail status of only the previous page is available upon the return to Ready state. When the next set of data is inputted with the
Cache Program command, tCBSY is affected by the progress of pending internal programming. The programming of the cache registers is initiated only
when the pending program cycle is finished and the data registers are available for the transfer of data from cache registers. The status bit(I/O5) for internal Ready/Busy may be polled to identify the completion of internal programming. If the system monitors the progress of programming only with R/B, the
last page of the target programming sequence must be programmed with actual Page Program command (10h).

tCBSY

R/B
I/Ox

80h

Address &
Data Input*

15h

Col. Add1,2 & Row Add1,2,3
Data

tCBSY

80h

Address &
Data Input

15h

Col. Add1,2 & Row Add1,2,3
Data

tPROG*2

tCBSY

80h

Address &
Data Input

15h

Col. Add1,2 & Row Add1,2,3
Data

Address &
10h
Data Input
Col. Add1,2 & Row Add1,2,3
Data

80h

70h

Figure 13. Cache Program(1/2)

NOTE :
1) Cache Read operation is available only within a block.
2) Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if the previous program cycle with the cache data
has not finished, the actual program cycle of the last page is initiated only after completion of the previous cycle, which can be expressed as the following formula.
tPROG = Program time for the last page + Program time for the ( last -1)th page - (Program command cycle time + Last page data loading time)

- 47 -

80h

- 48 -

Figure 14. Cache Program(2/2)

page K

1

Page K

Max. 127 times repeatable

Din
N

1
2

15h

15h

page K

Din
M
tCBSY

2

80h

Page K

page K

page K+1

3

3

Last Page Input & Program

3

Page K+1

Din
N

4

10h

10h

page K+1

Din
M

4

tPROG*

4

70h

I/O

tPROG* = Program time for the last page + Program time for the ( last -1)th page - (command input cycle time + address input cycle time + Last page data loading time)

datasheet

- Issuing the 15h command to the device after serial data input initiates the program operation with cache registers.
1. Data for Page K is input to cache registers.
2. Data is transferred to the data registers by the 15h command. During the transfer the Ready/Busy outputs Busy State (tCBSY).
3. Data for Page K+1 is input to cache registers while the data of the Page K is being programmed.
4. The programming with cache registers is terminated by the 10h command . When the device becomes Ready, it shows that the internal programming of the Page K+1 is completed.

NOTE :

Page K

data register

Cache register

R/B

I/Ox

RE

ALE

WE

?
?

CE

?

?
?

CLE

?

K9GAG08U0E
K9LBG08U0E K9HCG08U1E
Final Rev. 0.9.1

FLASH MEMORY

- 49 -

True
Ready/Busy

Cache
Ready/Busy

R/B pin

Page 1

80h....15h

Page 1

Status
Out

Invalid

I/O0 = & gt;

70h

Invalid

I/O1 = & gt;

Example)

Page 2

80h....15h

Page 2

Status
Out

70h
Status
Out

Page2

Page1

Page N-1

80h....15h

70h

Page N

80h....10h

Page N-1

Status
Out

Invalid

Page N-2

70h

Page N

Status
Out

Invalid

Invalid

70h

Status
Out

Page N

Page N-1

datasheet

During both True Ready/Busy and Cache Ready/Busy return to Ready state, the Pass/Fail for previous
page and current page can be shown through I/O 1 and I/O 0 concurrently.

70h

Invalid

Page1

Pass/Fail status for each page programmed by the Cache Program operation can be detected by the Read Status operation.
o I/O 0 : Pass/Fail of the current page program operation.
o I/O 1 : Pass/Fail of the previous page program operation.
The Pass/Fail status on I/O 0 and I/O 1 are valid under the following conditions.
o Status on I/O 0 : True Ready/Busy is Ready state.
The True Ready/Busy is output on I/O 5 by Read Status operation or R/B pin after the 10h command.
o Status on I/O 1 :Cache Read/Busy is Ready State.
The Cache Ready/Busy is output on I/O 6 by Read Status operation or R/B pin after the 15h command.

K9GAG08U0E
K9LBG08U0E K9HCG08U1E
Final Rev. 0.9.1

FLASH MEMORY

Final Rev. 0.9.1

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

FLASH MEMORY

5.6 Block Erase
The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup command(60h). Only
Block address are valid while Page address is ignored. The Erase Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external
noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When the erase operation is
completed, the Write Status Bit(I/O 0) may be checked. Figure 20 details the sequence.

tBERS

R/B

" 0 "

I/Ox

60h

Address Input(3Cycle)

70h

D0h

Row Add 1,2,3

I/O0
" 1 "
Fail

Figure 15. Block Erase Operation

- 50 -

Pass

Final Rev. 0.9.1

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

FLASH MEMORY

5.7 Read Status
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase
operation is completed successfully. After writing 70h or F1h/F2h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in
multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to Table 2 for specific 70h Status Register definitions and Table 3 for specific F1h status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, the read command(00h) should be given before
starting read cycles.
[Table 4] Status Register Definition for 70h Command
I/O

Page Program

Block Erase

Cache Program

Read

Cache Read

I/O 0

Pass/Fail

Pass/Fail

Pass/Fail(N)

Not Use

Not Use

Pass : " 0 "

Fail : " 1 "

I/O 1

Not Use

Not Use

Pass/Fail(N-1)

Not Use

Not Use

Pass : " 0 "

Fail : " 1 "

I/O 2

Not Use

Not Use

Not Use

Not Use

Not Use

Don't -cared

I/O 3

Not Use

Not Use

Not Use

Not Use

Not Use

Don't -cared

I/O 4

Not Use

Not Use

Not Use

Not Use

Not Use

I/O 5

Not Use

Not Use

True Ready/Busy

Not Use

True Ready/Busy

Busy : " 0 "

Ready : " 1 "

Busy : " 0 "

Ready : " 1 "

Protected : " 0 "

Not Protected : " 1 "

I/O 6

Ready/Busy

Ready/Busy

Cache Ready/Busy

Ready/Busy

Cache Ready/Busy

I/O 7

Write Protect

Write Protect

Write Protect

Write Protect

Write Protect

Definition

Don't -cared

NOTE :
1) I/Os defined 'Not use' are recommended to be masked out when Read Status is being executed.
2) N : current page, N-1: previous page.

[Table 5] F1h Read Status Register Definition
I/O

Page Program

Block Erase

Cache Program

Read

Cache Read

Definition

I/O 0

Chip1 Pass/Fail

Chip1 Pass/Fail

Chip1 Pass/Fail(N)

Not Use

Not Use

Pass : " 0 "

Fail : " 1 "

I/O 1

Plane Pass/Fail

Plane Pass/Fail

Plane Pass/Fail(N)

Not Use

Not Use

Pass : " 0 "

Fail : " 1 "

I/O 2

Not Use

Not Use

Not Use

Not Use

Not Use

Don't-cared

I/O 3

Not Use

Not Use

Plane Pass/Fail(N-1)

Not Use

Not Use

Pass : " 0 "

Fail : " 1 "

I/O 4

Not Use

Not Use

Not Use

Not Use

Not Use

I/O 5

Not Use

Not Use

True Ready/Busy

Not Use

True Ready/Busy

Busy : " 0 "

Don't-cared
Ready : " 1 "

I/O 6

Ready/Busy

Ready/Busy

Cache Ready/Cache

Ready/Busy

Cache Ready/Busy

Busy : " 0 "

Ready : " 1 "

I/O 7

Write Protect

Write Protect

Write Protect

Write Protect

Write Protect

Protected : " 0 " Not Protected : " 1 "

NOTE :
1) I/Os defined 'Not use' are recommended to be masked out when Read Status is being executed.
2) N : current page,
N-1 : previous page.

[Table 6] F2h Read Status Register Definition
I/O

Page Program

Block Erase

Cache Program

Read

Cache Read

I/O 0

Chip2 Pass/Fail

Chip2 Pass/Fail

Chip2 Pass/Fail(N)

Not Use

Not Use

I/O 1

Plane Pass/Fail

Plane Pass/Fail

Plane Pass/Fail(N)

Not Use

I/O 2

Not Use

Not Use

Not Use

Not Use

I/O 3

Not Use

Not Use

Plane Pass/Fail(N-1)

Not Use

Not Use

Pass : " 0 "

Fail : " 1 "

Not Use

Pass : " 0 "

Fail : " 1 "

Not Use

Don't-cared

I/O 4

Not Use

Not Use

Not Use

Not Use

Not Use

I/O 5

Not Use

Not Use

True Ready/Busy

Not Use

True Ready/Busy

I/O 6

Ready/Busy

Ready/Busy

Cache Ready/Cache

Ready/Busy

Cache Ready/Busy

I/O 7

Write Protect

Write Protect

Write Protect

Write Protect

Write Protect

NOTE :
1) I/Os defined 'Not use' are recommended to be masked out when Read Status is being executed.
2) N : current page,
N-1 : previous page.

- 51 -

Definition
Pass : " 0 "

Fail : " 1 "

Don't-cared
Busy : " 0 "

Ready : " 1 "

Busy : " 0 "

Ready : " 1 "

Protected : " 0 " Not Protected : " 1 "

Final Rev. 0.9.1

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

FLASH MEMORY

5.8 Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Six read cycles
sequentially output the manufacturer code(ECh), the device code, 3rd, 4th, 5th and 6th cycle ID respectively. The command register remains in Read ID
mode until further commands are issued to it. Figure 22 shows the operation sequence.

tCLR

CLE

tCEA
CE
WE
tAR
ALE
tWHR
RE
I/OX

tREA
00h

ECh

Address. 1cycle

Maker code

90h

Device
Code

3rd Cyc.

4th Cyc.

5th Cyc.

6th Cyc.

Device code

Figure 16. Read ID Operation

Device

Device Code (2nd Cycle)

3rd Cycle

K9GAG08U0E

D5h

84h

K9LBG08U0E

D7h

4th Cycle

5th Cycle

6th Cycle

50h
72h

C5h

54h

42h

K9HCG08U1E

5.9 RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or
erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially
programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value E0h when WP is high.
Refer toTable 7 for device status after reset operation. If the device is already in reset state a new reset command will be accepted by the command register. The R/B pin changes to low for tRST after the Reset command is written. Refer to Figure 17 below.

tRST
R/B
I/OX

FFh

Figure 17. RESET Operation

[Table 7] Device Status
After Reset
Operation Mode

Waiting for next command

- 52 -

Final Rev. 0.9.1

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

FLASH MEMORY

5.10 Ready/Busy
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/
B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address
loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs
to be Or-tied. Because pull-up resistor value is related to tr(R/B) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Figure 18). Its value can be determined by the following guidance.

Rp
VCC

ibusy

3.3V device - VOL : 0.4V, VOH : 2.4V

Ready Vcc
R/B
open drain output

VOH

CL

VOL
Busy
tf

tr

GND
Device

Figure 18. Rp vs tr ,tf & Rp vs ibusy

@ Vcc = 3.3V, Ta = 25°C , CL = 50pF
2.4

100

100n
tr

tr,tf [s]

1.2

150

tf

1K

1m

0.8
0.6

50
3.6

2m
Ibusy [A]

200

Ibusy

200n

3.6

3.6

2K
3K
Rp(ohm)

4K

3.6

Rp value guidance
Rp(min, 3.3V part) =

3.2V

VCC(Max.) - VOL(Max.)
IOL + ?IL

=

8mA + ?IL

where IL is the sum of the input currents of all devices tied to the R/B pin.
Rp(max) is determined by maximum permissible limit of tr

- 53 -

Final Rev. 0.9.1

datasheet

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

FLASH MEMORY

6.0 DATA PROTECTION & POWER UP SEQUENCE

?

The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions
whenever Vcc is below about 2V. The Reset command(FFh) must be issued to all CEs as the first command after the NAND Flash device is powered on.
Each CE will be busy for a maximum of 5ms after a RESET command is issued. In this time period, the acceptable command is 70h/F1h/F2h.
WP pin provices hardware protection and is recommanded to be kept at VIL during power-up and power-down. The two step command sequence for program/erase provides additional software protection.

~ 2.7V

~ 2.7V

100?s

?

VCC

?

?

CLE

?

CE

Don't care

?

High

?

WP

?

Don't care

?

WE

I/Ox

?

FFh

R/B

100?s

5ms max

?

Operation

Invalid

Don't care

Figure 19. AC Waveforms for Power Transition

NOTE :
During the initialization, the device consumes a maximum current of 50mA (ICC1)

- 54 -

K9GAG08U0E
K9LBG08U0E K9HCG08U1E

datasheet

Final Rev. 0.9.1

FLASH MEMORY

6.1 WP AC Timing guide
Enabling WP during erase and program busy is prohibited. The erase and program operations are enabled and disabled as follows:

?

1. Enable Mode
WE
I/O

80h

10h

WP
R/B

tww(min.100ns)

?

2. Disable Mode
WE
I/O

80h

10h

WP
R/B

tww(min.100ns)

Figure B-1. Program Operation

?

1. Enable Mode
WE
I/O

60h

D0h

WP
R/B

tww(min.100ns)

?

2. Disable Mode
WE
60h

I/O
WP
R/B

tww(min.100ns)

Figure B-2. Erase Operation

- 55 -

D0h


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