Witam. Planuję zbudować sobie zegar nixie na lampach 6xZ566m lub 4xZ566m + 2xZ573m i do tego 2 podwójne separatory jak na zdjęciu niżej. Wszystko zamierzam zmontować na płytce uniwersalnej dlatego też wszytko jest rozplanowane w rastrze 100mils z możliwie jak najmniejszą ilością zwór i tak by wyglądało schludnie gdyż nie chcę niczego potem ukrywać. Ta magistralę od rejestrów prawdopodobnie będę próbował zrobić za pomocą wiązki (coś podobnego jak na zdjęciu niżej). Pierwszy raz robię coś na nixie więc mam też kilka pytań odnośnie układu: 1 - czy przetwornica ma dobrze dobrane elementy? Większość projektów nixie bazuje na mc34063 ale nie byłem w stanie znaleźć żadnego bez multipleksowania a tutaj go nie będzie i jeśli dobrze policzyłem to przetwornica powinna mi dostarczyć ~15-20ma. 2 - Tranzystor Q2 wszędzie podają, że jest to zwykły PNP jednak z moich symulacji wynika, że najlepszy efekt dałby tutaj darlington. To dobry pomysł czy nie bardzo? 3 - spotkałem się także z przypadkami, że DS1307 gubił sekundy w niektórych projektach nixie. Będzie to kwestia kwarcu, ekranowania przetwornicy czy też innych czynników? Czy nie warto np pomyśleć o jakimś innym układzie RTC? 4 - Przyciemnianie mam zamiar zrobić na bazie PWM, czy to jakoś wpłynie negatywnie na jakość świecenia lamp nixie? Będę wdzięczy za wszelkie wskazówki co można by tutaj jeszcze poprawić. W załączniku dodaję aktualną wersję projektu w Eaglu. 888986 https://obrazki.elektroda.pl/4859836600_1519287084_thumb.jpghttps://obrazki.elektroda.pl/8440679300_1519287084_thumb.jpg https://obrazki.elektroda.pl/5660669300_1519286944_thumb.jpg https://obrazki.elektroda.pl/1972485200_1519286944_thumb.jpg
Lith.3V
A IC
A IC
K1
K2
A IC
K1
K3
K0
K3
K9
K4
K5
K9
K4
K5
K8
K7
IC
K6
K8
K7
IC
K6
A IC
K1
K2
K0
U
D
K2
A IC
K1
K3
K0
K3
K9
K4
K5
K9
K4
K5
K8
K7
IC
2018-02-22 05:00 f=0.97 C:\Users\xXx\Documents\eagle\nixie clock\untitled.brd
K6
K8
K7
IC
K6
A IC
K1
K2
K0
U
D
K2
K1
K2
K0
K3
K0
K3
K9
K4
K5
K9
K4
K5
K8
K7
IC
K6
K8
K7
IC
K6
Lampy Nixie
GND
0
9
6
5
47k
AN6
A
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
GND
+5V
4
5
6
7
14
15
16
17
TPIC6B595N
18
C17
C18
C19
C20
C21
C22
C23
100n 100n 100n 100n 100n 100n 100n 100n
GND
2
10
11
19
SER_OUT
G
RCK
SRCLR DRAIN0
DRAIN1
SRCK
SER_IN DRAIN2
DRAIN3
DRAIN4
VCC
DRAIN5
GND
DRAIN6
GND
DRAIN7
GND
TPIC6B595N
IC6
9
12
8
13
3
2
10
11
19
GND
C24
+5V
+5V
GND
+5V
4
5
6
7
14
15
16
17
18
9
12
8
13
3
IC10
TPIC6B595N
+5V
2
10
11
19
7
U
SER_OUT
G
RCK
SRCLR DRAIN0
DRAIN1
SRCK
SER_IN DRAIN2
DRAIN3
DRAIN4
VCC
DRAIN5
GND
DRAIN6
GND
DRAIN7
GND
4
5
6
7
14
15
16
17
18
SER_OUT
G
RCK
SRCLR DRAIN0
DRAIN1
SRCK
SER_IN DRAIN2
DRAIN3
DRAIN4
VCC
DRAIN5
GND
DRAIN6
GND
DRAIN7
GND
GND
8
4
5
6
7
14
15
16
17
1
18
2
SER_OUT
G
RCK
SRCLR DRAIN0
DRAIN1
SRCK
SER_IN DRAIN2
DRAIN3
DRAIN4
VCC
DRAIN5
GND
DRAIN6
GND
DRAIN7
GND
3
IC5
4
9
12
8
13
3
TPIC6B595N
R14
47k
R8
200k
AN5
A
5
9
12
8
13
3
6
TPIC6B595N
7
2
10
11
19
8
+5V
9
4
5
6
7
14
15
16
17
0
18
1
SER_OUT
G
RCK
SRCLR DRAIN0
DRAIN1
SRCK
SER_IN DRAIN2
DRAIN3
DRAIN4
VCC
DRAIN5
GND
DRAIN6
GND
DRAIN7
GND
2
9
12
8
13
3
3
D
GND
R7
200k
R6
AN4
A
4
TPIC6B595N
5
IC9
6
2
10
11
19
7
+5V
+5V
8
+5V
SER_OUT
G
RCK
SRCLR DRAIN0
DRAIN1
SRCK
SER_IN DRAIN2
DRAIN3
DRAIN4
VCC
DRAIN5
GND
DRAIN6
GND
DRAIN7
GND
9
U
IC11
D
4
5
6
7
14
15
16
17
0
18
1
SER_OUT
G
RCK
SRCLR DRAIN0
DRAIN1
SRCK
SER_IN DRAIN2
DRAIN3
DRAIN4
VCC
DRAIN5
GND
DRAIN6
GND
DRAIN7
GND
2
IC12
3
47k
AN3
A
4
9
12
8
13
3
5
TPIC6B595N
6
2
10
11
19
7
9
12
8
13
3
IC14
8
4
5
6
7
14
15
16
17
9
18
0
SER_OUT
G
RCK
SRCLR DRAIN0
DRAIN1
SRCK
SER_IN DRAIN2
DRAIN3
DRAIN4
VCC
DRAIN5
GND
DRAIN6
GND
DRAIN7
GND
1
IC13
2
9
12
8
13
3
3
R5
47k
R4
200k
R3
200k
AN2
A
4
TPIC6B595N
5
2
10
11
19
6
4
5
6
7
14
15
16
17
7
18
8
2
10
11
19
AN1
A
9
R2
47k
R1
47k
R16
+170V
Operating Supply Voltage: 65 VAC, 90 VDC
Operating Supply Current: ~1 mA/bulb
110V-230V Drive needs ~100K-200K serial resistor.
Never use without serial resistor!
GND
GND
SER_IN
LATCH
CLOCK
PWM
RTC
10k
1
GND
+5V
GND
Programator
RST prowadzone przewodem
GND
GND
GND
GND
GND
VCC
MOSI
GND
2
4
6
SER_IN
GND
MISO
SCK
RST
+5V
1
3
5
GND
C12
100n
Sterowanie
Pullup wewnątrz AVR
GND
GND
ENCA
GND
+5V
C11
C13
100n
100n
GND
ENCB
BTN
2018-02-22 05:01 f=0.64 C:\Users\xXx\Documents\eagle\nixie clock\untitled.sch (Sheet: 1/1)
GND
GND GND
28
27
26
25
24
23
GND
(AIN1)PD7
(AIN0)PD6
(T1)PD5
(XCK/T0)PD4
(INT1)PD3
(INT0)PD2
(TXD)PD1
(RXD)PD0
SCL
SDA
LIGHT
SDA
SDA
6
5
SDA
ENCA
BTN
PWM
SQW
DQ
4k7
4k7
R20
+5V
VCC
SCL SQW/OUT
VBAT
DS1307
IC3
13
12
11
6
5
4
3
2
8
+5V
SCL
2
1
ENCB
VCC
C14
100n
GND
C
B
ISP1
7
8
A
MISO
CLOCK
RST
GND
R19
GNDGND
270k
LIGHT
GND
(ADC5/SCL)PC5
(ADC4/SDA)PC4
(ADC3)PC3
(ADC2)PC2
(ADC1)PC1
(ADC0)PC0
X2
2
C7
22p
10u
AREF
AVCC
GND
X1
Q3
1
C8
22p
GND
GND
4k7 +5V
R21
DQ
21
20
22
GND
C15
7
SQW
3
+
2
L2
CLOCK
MISO
SER_IN
LATCH
GND
CR2032V
DQ
2,2uF/350V
+5V
680k
C5
VDD
9
19
18
17
16
15
14
G1
100n
Czujnik światła
10
(SCK)PB5
(MISO)PB4
(MOSI/OC2)PB3
PB7(XTAL2/TOSC2) (SS/OC1B)PB2
(OC1A)PB1
(ICP)PB0
PB6(XTAL1/TOSC1)
PC6(/RESET)
-
C3
GND
GND
470p
3
GND
DQ
C1
100n
R9
C6
R12
1k
MC34063AP
Termometr
+5V
Q2
BC556
2
1.25 V
Ref
+
MC_FB
4k7
2k5
120V - 180V
R13
1
2
3
4
SWC
SWE
TC
GND
3
DC
IS
VCC
FB
Q1
IRF740
1
MC_FB
8
7
6
5
R10
IC1
GND
4
R15
U1
1
GND GND
SCL
100n
SQW
C4
2
C10
47u
100n 47u
100n
GND
+
3
GND
4k7
R18
+5V
VO
VI
C9
R17
+12V
330uH/1A
pin 3,24 - usunięte piny z podstawki
+5V
0R5
1
C2
+
L1
IC2
7805TV
+
R11
uC
+5V
Stabilizator 5V
+170V
+12V
Przetwornica HV
C16
10u
GND
MC34063A, MC33063A,
SC34063A, SC33063A,
NCV33063A
1.5 A, Step-Up/Down/
Inverting Switching
Regulators
www.onsemi.com
The MC34063A Series is a monolithic control circuit containing the
primary functions required for DC−to−DC converters. These devices
consist of an internal temperature compensated reference, comparator,
controlled duty cycle oscillator with an active current limit circuit,
driver and high current output switch. This series was specifically
designed to be incorporated in Step−Down and Step−Up and
Voltage−Inverting applications with a minimum number of external
components. Refer to Application Notes AN920A/D and AN954/D
for additional design information.
MARKING
DIAGRAMS
8
3x063
ALYWA
G
8
1
SOIC−8
D SUFFIX
CASE 751
1
8
3x063V
ALYWA
G
Features
•
•
•
•
•
•
•
•
•
Operation from 3.0 V to 40 V Input
Low Standby Current
Current Limiting
Output Switch Current to 1.5 A
Output Voltage Adjustable
Frequency Operation to 100 kHz
Precision 2% Reference
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
1
Drive 8
Collector
8
3x063AP1
AWL
YYWWG
PDIP−8
P, P1 SUFFIX
CASE 626
1
8
8
33063AVP
AWL
YYWWG
1
1
Switch
Collector
Q2
S Q
Q1
R
Ipk 7
Sense
1
100
DFN8
CASE 488AF
2
1
Switch
Emitter
33063
ALYWA
G
Ipk
Oscillator CT
6
VCC
3
Comparator
+
-
x
A
L, WL
Y, YY
W, WW
G or G
Timing
Capacitor
1.25 V
Reference
Regulator
Comparator 5
Inverting
Input
4
= 3 or 4
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
GND
(Bottom View)
This device contains 79 active transistors.
ORDERING INFORMATION
Figure 1. Representative Schematic Diagram
© Semiconductor Components Industries, LLC, 2016
December, 2016 − Rev. 24
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
1
Publication Order Number:
MC34063A/D
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
Driver
Collector
Switch
Emitter
2
7
Ipk Sense
Timing
Capacitor
3
6
VCC
GND
4
5
Comparator
Inverting
Input
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
8
Switch Collector
Switch Emitter
EP Flag
Timing Capacitor
GND
(Top View)
(Top View)
Ç
Ç
Ç
Ç
Ç
Ç
Ç
Ç
1
Switch
Collector
Driver Collector
Ipk Sense
VCC
Comparator
Inverting Input
Figure 2. Pin Connections
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Power Supply Voltage
VCC
40
Vdc
Comparator Input Voltage Range
VIR
−0.3 to + 40
Vdc
Switch Collector Voltage
VC(switch)
40
Vdc
Switch Emitter Voltage (VPin 1 = 40 V)
VE(switch)
40
Vdc
Switch Collector to Emitter Voltage
VCE(switch)
40
Vdc
Driver Collector Voltage
VC(driver)
40
Vdc
Driver Collector Current (Note 1)
IC(driver)
100
mA
ISW
1.5
A
PD
1.25
W
RqJA
115
°C/W
PD
625
mW
Thermal Resistance
RqJA
160
°C/W
Thermal Resistance
RqJC
45
°C/W
Switch Current
Power Dissipation and Thermal Characteristics
Plastic Package, P, P1 Suffix
TA = 25°C
Thermal Resistance
SOIC Package, D Suffix
TA = 25°C
DFN Package
TA = 25°C
PD
1.25
mW
RqJA
80
°C/W
Operating Junction Temperature
TJ
+150
°C
Operating Ambient Temperature Range
TA
Thermal Resistance
MC34063A, SC34063A
°C
0 to +70
MC33063AV, NCV33063A
−40 to +125
MC33063A, SC33063A
−40 to + 85
Storage Temperature Range
Tstg
−65 to +150
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Maximum package power dissipation limits must be observed.
2. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per MIL−STD−883, Method 3015.
Machine Model Method 400 V.
3. NCV prefix is for automotive and other applications requiring site and change control.
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2
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, TA = Tlow to Thigh [Note 4], unless otherwise specified.)
Symbol
Min
Typ
Max
Unit
fosc
Characteristics
24
33
42
kHz
OSCILLATOR
Frequency (VPin 5 = 0 V, CT = 1.0 nF, TA = 25°C)
Ichg
24
35
42
mA
Idischg
140
220
260
mA
Discharge to Charge Current Ratio (Pin 7 to VCC, TA = 25°C)
Idischg/Ichg
5.2
6.5
7.5
−
Current Limit Sense Voltage (Ichg = Idischg, TA = 25°C)
Vipk(sense)
250
300
350
mV
Saturation Voltage, Darlington Connection
( ISW = 1.0 A, Pins 1, 8 connected)
VCE(sat)
−
1.0
1.3
V
Saturation Voltage (Note 6)
(ISW = 1.0 A, RPin 8 = 82 W to VCC, Forced b ] 20)
VCE(sat)
−
0.45
0.7
V
hFE
50
75
−
−
IC(off)
−
0.01
100
mA
1.225
1.21
1.25
−
1.275
1.29
−
−
1.4
1.4
5.0
6.0
IIB
−
−20
−400
nA
ICC
−
−
4.0
mA
Charge Current (VCC = 5.0 V to 40 V, TA = 25°C)
Discharge Current (VCC = 5.0 V to 40 V, TA = 25°C)
OUTPUT SWITCH (Note 5)
DC Current Gain (ISW = 1.0 A, VCE = 5.0 V, TA = 25°C)
Collector Off−State Current (VCE = 40 V)
COMPARATOR
Threshold Voltage
TA = 25°C
TA = Tlow to Thigh
Vth
Threshold Voltage Line Regulation (VCC = 3.0 V to 40 V)
MC33063, MC34063
MC33063V, NCV33063
V
Regline
Input Bias Current (Vin = 0 V)
mV
TOTAL DEVICE
Supply Current (VCC = 5.0 V to 40 V, CT = 1.0 nF, Pin 7 = VCC,
VPin 5 & gt; Vth, Pin 2 = GND, remaining pins open)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Tlow = 0°C for MC34063, SC34063; − 40°C for MC33063, SC33063, MC33063V, NCV33063
Thigh = +70°C for MC34063, SC34063; + 85°C for MC33063, SC33063; +125°C for MC33063V, NCV33063
5. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient temperature as possible.
6. If the output switch is driven into hard saturation (non−Darlington configuration) at low switch currents (≤ 300 mA) and high driver currents
(≥ 30 mA), it may take up to 2.0 ms for it to come out of saturation. This condition will shorten the off time at frequencies ≥ 30 kHz, and is
magnified at high temperatures. This condition does not occur with a Darlington configuration, since the output switch cannot saturate. If a
non−Darlington configuration is used, the following output drive condition is recommended:
IC output
w 10
Forced b of output switch :
IC driver – 7.0 mA *
* The 100 W resistor in the emitter of the driver device requires about 7.0 mA before the output switch conducts.
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3
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
18
OFF TIME (ms)
14
140
12
120
ON TIME (ms)
10
100
8
80
6
OFF TIME (ms)
4
60
40
FREQUENCY (kHz)
2
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
20
200 mV/DIV
160
V OSC , OSCILLATOR VOLTAGE (V)
16
ON TIME (ms), FREQUENCY (kHz)
180
VCC = 5.0 V, Pin 7 = VCC
Pin 5 = GND, TA = 25°C
VCC = 5.0 V
Pin 7 = VCC
Pin 2 = GND
Pins 1, 5, 8 = Open
CT = 1.0 nF
TA = 25°C
0
5.0
10 ms/DIV
Figure 4. Timing Capacitor Waveform
Ct, TIMING CAPACITOR CAPACITANCE (nF)
Figure 3. Oscillator Frequency
VCE(sat), SATURATION VOLTAGE (V)
VCE(sat), SATURATION VOLTAGE (V)
1.8
1.7
1.6
1.5
1.4
1.3
VCC = 5.0 V
Pins 1, 7, 8 = VCC
Pins 3, 5 = GND
TA = 25°C
(See Note 7)
1.2
1.1
1.0
0
0.2
0.4
0.6
0.8
1.0
1.2
IE, EMITTER CURRENT (A)
1.4
1.1
1.0
0.9
0.7
0.6
0.4
0.3
0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
IC, COLLECTOR CURRENT(A)
1.4
1.6
Figure 6. Common Emitter Configuration Output
Switch Saturation Voltage versus
Collector Current
3.6
380
3.2
VCC = 5.0 V
Ichg = Idischg
I CC, SUPPLY CURRENT (mA)
VIPK(sense), CURRENT LIMIT SENSE VOLTAGE (V)
Forced b = 20
0.1
0
1.6
400
320
300
280
260
240
220
200
-55
VCC = 5.0 V
Pin 7 = VCC
Pins 2, 3, 5 = GND
TA = 25°C
(See Note 7)
0.5
Figure 5. Emitter Follower Configuration Output
Saturation Voltage versus Emitter Current
360
340
Darlington Connection
0.8
2.8
2.4
2.0
1.6
1.2
CT = 1.0 nF
Pin 7 = VCC
Pin 2 = GND
0.8
0.4
0
-25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
0
125
Figure 7. Current Limit Sense Voltage
versus Temperature
5.0
10
15
20
25
30
VCC, SUPPLY VOLTAGE (V)
35
Figure 8. Standby Supply Current versus
Supply Voltage
7. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient temperature as possible.
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4
40
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
170 mH
L
1
8
180
S Q
Q2
R
Q1
7
2
1N5819
Ipk
Rsc
0.22
Vin
12 V
OSC
6
+
CT
3
CT
VCC
100
+
-
Comp.
1.25 V
Ref
Reg
1500
pF
5
4
1.0 mH
R2
R1
Vout
28 V/175 mA
47 k
2.2 k
Vout
+
330
+
CO
100
Optional Filter
Test
Conditions
Results
Line Regulation
Vin = 8.0 V to 16 V, IO = 175 mA
30 mV = ±0.05%
Load Regulation
Vin = 12 V, IO = 75 mA to 175 mA
10 mV = ±0.017%
Output Ripple
Vin = 12 V, IO = 175 mA
400 mVpp
Efficiency
Vin = 12 V, IO = 175 mA
87.7%
Output Ripple With Optional Filter
Vin = 12 V, IO = 175 mA
40 mVpp
Figure 9. Step−Up Converter
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5
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
8
1
7
R
Vout
8
7
2
Rsc
Vin
1
Vout
2
Rsc
Vin
6
6
R ³ 0 for
constant Vin
Figure 10. External Current Boost Connections for IC Peak Greater than 1.5 A
9a. External NPN Switch
9b. External NPN Saturated Switch
(See Note 8)
8. If the output switch is driven into hard saturation (non−Darlington configuration) at low switch currents (≤ 300 mA) and high driver currents
(≥ 30 mA), it may take up to 2.0 ms to come out of saturation. This condition will shorten the off time at frequencies ≥ 30 kHz, and is magnified
at high temperatures. This condition does not occur with a Darlington configuration, since the output switch cannot saturate. If a
non−Darlington configuration is used, the following output drive condition is recommended.
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6
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
1
8
S Q
Q2
Q1
R
7
2
Ipk
Rsc
0.33
Vin
25 V
OSC
6
100
+
CT
1N5819
3
L
CT
VCC
+
-
1.25 V
Ref
Reg
Comp.
220 mH
470
pF
5
4
3.6 k
R1
1.0 mH
Vout
5.0 V/500 mA
R2
+
1.2 k
470
+
CO
Vout
100
Optional Filter
Test
Conditions
Results
Line Regulation
Vin = 15 V to 25 V, IO = 500 mA
12 mV = ±0.12%
Load Regulation
Vin = 25 V, IO = 50 mA to 500 mA
3.0 mV = ±0.03%
Output Ripple
Vin = 25 V, IO = 500 mA
120 mVpp
Short Circuit Current
Vin = 25 V, RL = 0.1 W
1.1 A
Efficiency
Vin = 25 V, IO = 500 mA
83.7%
Output Ripple With Optional Filter
Vin = 25 V, IO = 500 mA
40 mVpp
Figure 11. Step−Down Converter
8
1
1
V
8
7
Vout
Rsc
Vin
7
2
2
Rsc
6
Vin
6
Figure 12. External Current Boost Connections for IC Peak Greater than 1.5 A
11a. External NPN Switch
11b. External PNP Saturated Switch
www.onsemi.com
7
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
1
8
S Q
Q2
R
Q1
7
2
Ipk
Rsc
0.24
OSC
6
Vin
4.5 V to 6.0 V
88 mH
L
CT
VCC
3
+
100
+
-
Comp.
+
1.25 V
Ref
Reg
1500
pF
1N5819
4
5
1.0 mH
R1
Vout
-12 V/100 mA
953
R2
1000 mf
8.2 k
+
Vout
CO
+
100
Optional Filter
Test
Conditions
Results
Line Regulation
Vin = 4.5 V to 6.0 V, IO = 100 mA
3.0 mV = ± 0.012%
Load Regulation
Vin = 5.0 V, IO = 10 mA to 100 mA
0.022 V = ± 0.09%
Output Ripple
Vin = 5.0 V, IO = 100 mA
500 mVpp
Short Circuit Current
Vin = 5.0 V, RL = 0.1 W
910 mA
Efficiency
Vin = 5.0 V, IO = 100 mA
62.2%
Output Ripple With Optional Filter
Vin = 5.0 V, IO = 100 mA
70 mVpp
Figure 13. Voltage Inverting Converter
8
1
1
Vout
8
7
2
7
Vout
Vin
2
3
6
Vin
3 +
6
+
4
4
Figure 14. External Current Boost Connections for IC Peak Greater than 1.5 A
13a. External NPN Switch
13b. External PNP Saturated Switch
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8
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
Figure 15. Printed Circuit Board and Component Layout
(Circuits of Figures 9, 11, 13)
INDUCTOR DATA
Converter
Inductance (mH)
Turns/Wire
Step−Up
170
38 Turns of #22 AWG
Step−Down
220
48 Turns of #22 AWG
Voltage−Inverting
88
28 Turns of #22 AWG
All inductors are wound on Magnetics Inc. 55117 toroidal core.
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9
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
Figure 16. Printed Circuit Board for DFN Device
www.onsemi.com
10
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
Calculation
Step−Up
V out ) V
ton/toff
V
F
10−5
Ipk(switch)
2I
ǒ
out(max)
ton
4.0 x
ǒ
Ǔ
t on
) 1
t
off
* V sat)
in(min)
I
pk(switch)
9
Ǔ
2I
t
on(max)
ǒ
10−5
(V
in(min)
I
I
ripple(pp)
(ton + toff) − toff
4.0 x 10−5 ton
ton
2I
out(max)
0.3/Ipk(switch)
I outt on
V
off
ton
) 1
t
off
(ton + toff) − toff
0.3/Ipk(switch)
(V
F
* V sat
t on ) t
off
ton
) 1
t
off
(ton + toff) − toff
4.0 x
in
1
f
t on ) t
off
ton
) 1
t
off
CT
V
1
f
t on ) t
ton
CO
|V out| ) V
F
* V sat * V out
in(min)
1
f
toff
L(min)
V
Voltage−Inverting
V out ) V
* V
in(min)
* V sat
in(min)
(ton + toff)
Rsc
Step−Down
* V sat * V out)
pk(switch)
Ǔ
t
(t
) t )
pk(switch) on
off
8V
ripple(pp)
on(max)
ǒ
out(max)
ǒ
Ǔ
t on
) 1
t
off
0.3/Ipk(switch)
(V
* V sat)
in(min)
I
pk(switch)
9
Ǔ
t
on(max)
I outt on
V
ripple(pp)
Vsat = Saturation voltage of the output switch.
VF = Forward voltage drop of the output rectifier.
The following power supply characteristics must be chosen:
ǒ
Ǔ
Vin − Nominal input voltage.
Vout − Desired output voltage, |V out| + 1.25 1 ) R2
R1
Iout − Desired output current.
fmin − Minimum desired output switching frequency at the selected values of Vin and IO.
Vripple(pp) − Desired peak−to−peak output ripple voltage. In practice, the calculated capacitor value will need to be increased due to its
equivalent series resistance and board layout. The ripple voltage should be kept to a low value since it will directly affect the
line and load regulation.
NOTE: For further information refer to Application Note AN920A/D and AN954/D.
Figure 17. Design Formula Table
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11
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
ORDERING INFORMATION
Package
Shipping†
MC33063ADG
SOIC−8
(Pb−Free)
98 Units / Rail
MC33063ADR2G
SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
SC33063ADR2G
SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
MC33063AP1G
PDIP−8
(Pb−Free)
50 Units / Rail
MC33063AVDG
SOIC−8
(Pb−Free)
98 Units / Rail
MC33063AVDR2G
SOIC−8
(Pb−Free)
NCV33063AVDR2G*
SOIC−8
(Pb−Free)
MC33063AVPG
PDIP−8
(Pb−Free)
50 Units / Rail
MC34063ADG
SOIC−8
(Pb−Free)
98 Units / Rail
MC34063ADR2G
SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
SC34063ADR2G
SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
MC34063AP1G
PDIP−8
(Pb−Free)
50 Units / Rail
SC34063AP1G
PDIP−8
(Pb−Free)
50 Units / Rail
MC33063MNTXG
DFN8
(Pb−Free)
4000 Units / Tape & Reel
Device
2500 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
*NCV33063A: Tlow = −40°C, Thigh = +125°C. Guaranteed by design. NCV prefix is for automotive and other applications requiring site and
change control.
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12
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
K
−Y−
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm
ǒinchesǓ
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
13
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
PACKAGE DIMENSIONS
PDIP−8
P, P1 SUFFIX
CASE 626−05
ISSUE P
D
A
E
H
8
5
E1
1
4
NOTE 8
c
b2
B
END VIEW
TOP VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
e/2
NOTE 3
L
SEATING
PLANE
A1
C
M
D1
e
8X
SIDE VIEW
b
0.010
eB
END VIEW
M
C A
M
B
M
NOTE 6
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14
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.355 0.400
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
9.02
10.16
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
PACKAGE DIMENSIONS
DFN8, 4x4
CASE 488AF−01
ISSUE C
A
B
D
L
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. DETAILS A AND B SHOW OPTIONAL
CONSTRUCTIONS FOR TERMINALS.
L
L1
OPTIONAL
CONSTRUCTIONS
TOP VIEW
DETAIL B
0.10 C
A
ÇÇÇ
ÇÇ
0.08 C
EXPOSED Cu
A1
DETAIL B
(A3)
A1
NOTE 4
A3
MOLD CMPD
ÉÉ
ÉÉ
ÇÇ
0.15 C
2X
C
SIDE VIEW
SEATING
PLANE
ALTERNATE
CONSTRUCTIONS
ÇÇ
ÇÇ
ÉÉ
0.15 C
2X
8X
DETAIL A
E
ÉÉÉ
ÉÉÉ
PIN ONE
REFERENCE
8X
1
e
L
8X
2.21
4
ÇÇÇ
ÇÇ
ÇÇÇ
ÇÇ
ÇÇÇ
ÇÇ
8
K
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.25
0.35
4.00 BSC
1.91
2.21
4.00 BSC
2.09
2.39
0.80 BSC
0.20
−−−
0.30
0.50
−−−
0.15
SOLDERING FOOTPRINT*
D2
DETAIL A
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
0.63
E2
5
8X
4.30 2.39
b
0.10 C A B
0.05 C
PACKAGE
OUTLINE
NOTE 3
BOTTOM VIEW
8X
0.80
PITCH
0.35
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SENSEFET is a trademark of Semiconductor Components Industries, LLC.
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MC34063A/D
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Technical
Documents
TPIC6B595
SLIS032B – JULY 1995 – REVISED JUNE 2015
TPIC6B595 Power Logic 8-Bit Shift Register
1 Features
•
•
•
1
•
•
•
Low rDS(on),5 Ω (Typical)
Avalanche Energy, 30 mJ
Eight Power DMOS Transistor Outputs of 150-mA
Continuous Current
Output Clamp Voltage, 50 V
Devices are Cascadable
Low-Power Consumption
2 Applications
•
•
•
•
The storage register transfers data to the output
buffer when shift-register clear (SRCLR) is high.
When SRCLR is low, the input shift register is
cleared. When output enable (G) is held high, all data
in the output buffers is held low and all drain outputs
are off. When G is held low, data from the storage
register is transparent to the output buffers. When
data in the output buffers is low, the DMOS-transistor
outputs are off. When data is high, the DMOS
transistor outputs have sink-current capability. The
serial output (SER OUT) allows for cascading of the
data from the shift register to additional devices.
Outputs are low-side, open-drain DMOS transistors
with output ratings of 50 V and 150-mA continuous
sink-current capability. Each output provides a 500mA typical current limit at TC = 25°C. The current limit
decreases as the junction temperature increases for
additional device protection.
Instrumentation Clusters
Tell-Tale Lamps
LED Illumination and Controls
Automotive Relay or Solenoids Drivers
3 Description
The TPIC6B595 device is a monolithic, high-voltage,
medium-current power 8-bit shift register designed for
use in systems that require relatively high load power.
The device contains a built-in voltage clamp on the
outputs for inductive transient protection. Power
driver applications include relays, solenoids, and
other medium current or high-voltage loads.
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage
register. Data transfers through the shift and storage
registers on the rising edge of the shift-register clock
(SRCK) and the register clock (RCK), respectively.
The TPIC6B595 is characterized for operation over
the operating case temperature range of −40°C to
125°C.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SOIC (20)
PDIP (20)
TPIC6B595
12.80 mm × 7.50 mm
24.33 mm × 6.35 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Symbol
G
RCK
SRCLR
SRCK
SER IN
9
EN3
12
C2
8
R
SRG8
13
C1
3
4
1D
2
5
6
DRAIN0
DRAIN1
DRAIN2
7
DRAIN3
14
DRAIN4
15
DRAIN5
16
DRAIN6
17
DRAIN7
2
18
SER OUT
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPIC6B595
SLIS032B – JULY 1995 – REVISED JUNE 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
4
4
4
5
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 13
9
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application ................................................. 14
10 Power Supply Recommendations ..................... 16
11 Layout................................................................... 16
11.1 Layout Guidelines ................................................. 16
11.2 Layout Example .................................................... 17
12 Device and Documentation Support ................. 18
12.1
12.2
12.3
12.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
13 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
Changes from Revision A (May 2005) to Revision B
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 4
Changes from Original (July 1995) to Revision A
•
2
Page
Page
Changed SRCLR timing diagram .......................................................................................................................................... 9
Submit Documentation Feedback
Copyright © 1995–2015, Texas Instruments Incorporated
Product Folder Links: TPIC6B595
TPIC6B595
www.ti.com
SLIS032B – JULY 1995 – REVISED JUNE 2015
5 Pin Configuration and Functions
DW or N Package
20-Pin SOIC or PDIP
Top View
NC
VCC
SER IN
DRAIN0
DRAIN1
DRAIN2
DRAIN3
SRCLR
G
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
NC
GND
SER OUT
DRAIN7
DRAIN6
DRAIN5
DRAIN4
SRCK
RCK
GND
NC – No internal connection
Pin Functions
PIN
NAME
NO.
DRAIN0
5
DRAIN2
DESCRIPTION
4
DRAIN1
I/O
6
DRAIN3
7
DRAIN4
14
DRAIN5
15
DRAIN6
16
DRAIN7
17
G
GND
NC
O
Open-drain output
Output enable, active-low
9
I
10, 11, 19
—
Power ground
No internal connection
1, 20
—
RCK
12
I
Register clock
SERIN
3
I
Serial data input
SEROUT
18
O
Serial data output
SRCK
15
I
Shift register clock
SRCLR
8
I
Shift register clear, active-low
VCC
2
I
Power supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
VCC
Logic supply voltage (2)
–0.3
7
V
VI
Logic input voltage
–0.3
7
V
VDS
Power DMOS drain-to-source voltage (3)
–0.3
50
V
Continuous source-to-drain diode anode current
0
500
mA
Pulsed source-to-drain diode anode current (4)
0
1
A
ID
Pulsed drain current, each output, all outputs ON, TC = 25°C (4)
0
500
mA
ID
Continuous drain current, each output, all outputs ON, TC = 25°C (4)
0
150
mA
mA
(4)
IDM
Peak drain current single output, TC = 25°C
0
500
EAS
Single-pulse avalanche energy (see Figure 11)
0
30
mJ
IAS
Avalanche current (5)
0
500
mA
Continuous total dissipation
See Thermal Information
TJ
Operating virtual junction temperature
–40
150
°C
TC
Operating case temperature
–40
125
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
(3)
(4)
(5)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to GND.
Each power DMOS source is internally connected to GND.
Pulse duration ≤ 100 μs and duty cycle ≤ 2%.
DRAIN supply voltage = 15 V, starting junction temperature (TJS) = 25°C, L = 1.5 H, IAS = 200 mA (see Figure 11).
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic discharge
Charged-device model (CDM), per AEC
Q100-011
UNIT
±2000
All pins
±500
Corner pins (1, 10, 20,
11)
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VCC
Logic supply voltage
VIH
High-level input voltage
VIL
4.5
Low-level input voltage
NOM
MAX
5.5
0.85 VCC
–500
V
V
0.15 VCC
Pulsed drain output current, TC = 25°C, VCC = 5 V, all outputs on (1) (2) (see
Figure 7)
UNIT
500
V
mA
tsu
Setup time, SER IN high before SRCKM ↑ (see Figure 9)
20
ns
th
Hold time, SER IN high after SRCKM ↑, (see Figure 9)
20
ns
tw
Pulse duration (see Figure 9)
40
ns
TC
Operating case temperature
–40
(1)
(2)
4
125
°C
Pulse duration ≤ 100 μs and duty cycle ≤ 2%.
Technique should limit TJ − TC to 10°C maximum.
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6.4 Thermal Information
TPIC6B595
THERMAL METRIC (1)
DW (SOIC)
N (PDIP)
20 PINS
20 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
75.3
57
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
39.8
58.5
°C/W
RθJB
Junction-to-board thermal resistance
43.1
38
°C/W
ψJT
Junction-to-top characterization parameter
15.4
25.2
°C/W
ψJB
Junction-to-board characterization parameter
42.6
37.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
V(BR)DSX
Drain-to-source breakdown
voltage
ID = 1 mA
VSD
Source-to-drain diode forward
voltage
IF = 100 mA
VOH
High-level output voltage, SER
OUT
IOH = −20 µA,
VCC = 4.5 V
4.4
4.49
IOH = −4 mA,
VCC = 4.5 V
4
4.2
VOL
Low-level output voltage, SER
OUT
IOL = 20 µA,
VCC = 4.5 V
0.005
0.1
IOL = 4 mA,
VCC = 4.5 V
0.3
0.5
IIH
High-level input current
VCC = 5.5 V,
VI = VCC
IIL
Low-level input current
VCC = 5.5 V,
VI = 0
50
UNIT
V
0.85
1
V
V
V
1
µA
–1
µA
All outputs OFF
20
100
All outputs ON
150
300
0.4
5
ICC
Logic supply current
VCC = 5.5 V
ICC(FRQ)
Logic supply current at
frequency
fSRCK = 5 MHz,
All outputs off,
CL = 30 pF,
See Figure 9 and Figure 2
IN
Nominal current
VDS(on) = 0.5 V,
IN = ID,
TC = 85°C
See
(1) (2) (3)
90
VDS = 40 V,
VCC = 5.5 V
0.1
5
IDSX
OFF-state drain current
VDS = 40 V
TC = 125°C
VCC = 5.5 V
0.15
8
4.2
5.7
6.8
9.5
5.5
8
ID = 100 mA,
VCC = 4.5 V
rDS(on)
Static drain-source ON-state
resistance
ID = 100 mA,
TC = 125°C,
VCC = 4.5 V
See (1) and (2) and Figure 3
and Figure 4
ID = 350 mA,
VCC = 4.5 V
(1)
(2)
(3)
µA
mA
mA
µA
Ω
Technique should limit TJ − TC to 10°C maximum.
These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a voltage
drop of 0.5 V at TC = 85°C.
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6.6 Switching Characteristics
VCC = 5 V, TC = 25°C
PARAMETER
tPLH
TEST CONDITIONS
MIN
Propagation delay time, low-to-high-level output
from G
TYP
150
MAX
UNIT
ns
tr
Propagation delay time, high-to-low-level output CL = 30 pF, ID = 100 mA, See Figure 5,
from G
Figure 8 and Figure 9
Rise time, drain output
200
ns
tf
Fall time, drain output
200
ns
ta
Reverse-recovery-current rise time
100
ns
trr
Reverse-recovery time
tPHL
(1)
(2)
6
IF = 100 mA, di/dt = 10 A/µs (1)
See Figure 10
(2)
,
90
ns
300
Technique should limit TJ − TC to 10°C maximum.
These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
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6.7 Typical Characteristics
2.5
10
VCC = 5 V
TC = − 40°C to 125°C
4
I CC − Supply Current − mA
IAS − Peak Avalanche Current − A
TC = 25°C
2
1
0.4
2
1.5
1
0.5
0.2
0.1
0.1
0.2
0.4
1
2
4
0
0.1
10
1
tav − Time Duration of Avalanche − ms
VCC = 5 V
See Note A
16
14
TC = 125°C
12
10
8
6
TC = 25°C
4
TC = − 40°C
2
0
0
100
500
200
300
400
ID − Drain Current − mA
600
700
Figure 3. Drain-to-Source On-State Resistance
vs Drain Current
ID = 100 mA
See Note A
7
TC = 125°C
6
5
TC = 25°C
4
3
TC = − 40°C
2
1
0
4
4.5
5
5.5
6
6.5
VCC − Logic Supply Voltage − V
7
Figure 4. Static Drain-to-Source On-State Resistance
vs Logic Supply Voltage
0.45
tf
tr
200
tPLH
150
tPHL
100
50
−50
I D − Maximum Continuous Drain Current
of Each Output − A
ID = 100 mA
See Note A
250
Switching Time − ns
8
Technique should limit TJ − TC to 10°C maximum.
Technique should limit TJ − TC to 10°C maximum.
300
Figure 2. Supply Current vs Frequency
r DS(on) − Static Drain-to-Source On-State Resistance − Ω
r DS(on) − Drain-to-Source On-State Resistance − Ω
Figure 1. Peak Avalanche Current vs Time Duration of
Avalanche
18
100
10
f − Frequency − MHz
VCC = 5 V
0.4
0.35
0.3
0.25
TC = 25°C
0.2
0.15
TC = 100°C
0.1
TC = 125°C
0.05
0
−25
0
25
50
75
100
TC − Case Temperature − °C
1
125
2
3
4
5
6
7
8
N − Number of Outputs Conducting Simultaneously
Technique should limit TJ − TC to 10°C maximum
Figure 5. Switching Time vs Case Temperature
Figure 6. Maximum Continuous Drain Current of
Each Output vs Number of Outputs Conducting
Simultaneously
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I D − Maximum Peak Drain Current of Each Output − A
Typical Characteristics (continued)
0.5
d = 10%
0.45
d = 20%
0.4
0.35
d = 50%
0.3
0.25
d = 80%
0.2
0.15
VCC = 5 V
TC = 25°C
d = tw/tperiod
= 1 ms/tperiod
0.1
0.05
0
1
2
3
4
5
6
7
8
N − Number of Outputs Conducting Simultaneously
Figure 7. Maximum Peak Drain Current of
Each Output vs Number of Outputs Conducting Simultaneously
8
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7 Parameter Measurement Information
5V
24 V
7
2
8
13
Word
Generator
(see Note A)
3
12
SRCLR
DUT
DRAIN
SER IN
4
3
2
1
0
5V
0V
4 −7,
14 −17
Output
CL = 30 pF
(see Note B)
RCK
9
5
ID
VCC
G
5V
G
RL = 235 Ω
SRCK
6
SRCK
0V
5V
SER IN
0V
5V
RCK
0V
5V
SRCLR
0V
GND
10, 11, 19
24 V
DRAIN1
0.5 V
VOLTAGE WAVEFORMS
TEST CIRCUIT
A.
The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, tw = 300 ns, pulsed repetition rate
(PRR) = 5 kHz, ZO = 50 Ω.
B.
CL includes probe and jig capacitance.
Figure 8. Resistive-Load Test Circuit and Voltage Waveforms
5V
G
5V
50%
50%
0V
24 V
tPLH
tPHL
2
8
13
Word
Generator
(see Note A)
3
12
9
V
SRCLR CC
SRCK
ID
4 −7,
14 −17
DUT
RL = 235 Ω
tr
GND
5V
50%
SRCK
0V
tsu
10, 11, 19
TEST CIRCUIT
0.5 V
tf
SWITCHING TIMES
CL = 30 pF
(see Note B)
RCK
10%
10%
Output
24 V
90%
90%
DRAIN
SER IN
G
Output
th
5V
SER IN
50%
50%
0V
tw
INPUT SETUP AND HOLD WAVEFORMS
A.
The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, tw = 300 ns, pulsed repetition rate
(PRR) = 5 kHz, ZO = 50 Ω.
B.
CL includes probe and jig capacitance.
Figure 9. Test Circuit, Switching Times, and Voltage Waveforms
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Parameter Measurement Information (continued)
TP K
DRAIN
Circuit
Under
Test
0.1 A
2500 µF
250 V
di/dt = 20 A/µs
+
25 V
L = 1 mH
IF
(see Note A)
IF
−
0
TP A
25% of IRM
t2
t1
t3
Driver
IRM
RG
VGG
(see Note B)
ta
50 Ω
trr
TEST CIRCUIT
CURRENT WAVEFORM
A.
The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and
connected to the TP A test point.
B.
The VGG amplitude and RG are adjusted for di/dt = 20 A/µs. A VGG double-pulse train is used to set IF = 0.1 A, where
t1 = 10 µs, t2 = 7 µs, and t3 = 3 µs.
Figure 10. Reverse-Recovery-Current Test Circuit and Waveforms of Source-to-Drain Diode
5V
15 V
tw
2
8
V
SRCLR CC
10.5 Ω
Word
Generator
(see Note A)
3
12
9
DUT
G
See Note B
200 mH
SER IN
4 −7,
14 −17
DRAIN
RCK
5V
Input
ID
13 SRCK
tav
0V
IAS = 0.5 A
ID
VDS
GND
V(BR)DSX = 50 V
MIN
VDS
10, 11, 19
SINGLE-PULSE AVALANCHE ENERGY TEST CIRCUIT
VOLTAGE AND CURRENT WAVEFORMS
A.
The word generator has the following characteristics: tr ≤ 10 ns, tf ≤10 ns, ZO = 50 Ω.
B.
Input pulse duration, tw, is increased until peak current IAS = 0.5 mA.
Energy test level is defined as EAS = IAS × V(BR)DSX × tav/2 = 30 mJ.
Figure 11. Single-Pulse Avalanche Energy Test Circuit and Waveforms
10
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8 Detailed Description
8.1 Overview
The TPIC6B595 device is a monolithic, high-voltage, medium-current power 8-bit shift register designed for use
in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for
inductive transient protection, so it can also drive relays, solenoids, and other medium-current or high-voltage
loads.
8.2 Functional Block Diagram
G
RCK
SRCLR
9
12
4
D
SRCK
13
C1
D
C2
CLR
SER IN
DRAIN0
8
5
3
D
C1
D
C2
CLR
D
C1
6
C1
7
C1
14
C1
15
C1
16
C1
DRAIN6
D
C2
17
CLR
D
DRAIN5
D
C2
CLR
D
DRAIN4
D
C2
CLR
D
DRAIN3
D
C2
CLR
D
DRAIN2
D
C2
CLR
D
DRAIN1
DRAIN7
D
C2
CLR
10, 11, 19
18
GND
SER OUT
Figure 12. Logic Diagram (Positive Logic)
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Functional Block Diagram (continued)
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL DRAIN OUTPUTS
VCC
DRAIN
50 V
Input
25 V
20 V
12 V
GND
GND
Figure 13. Schematic of Inputs
8.3 Feature Description
8.3.1 Serial-In Interface
This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data
transfers through both the shift and storage registers on the rising edge of the shift register clock (SRCK) and the
register clock (RCK), respectively. The storage register transfers data to the output buffer when shift register
clear (SRCLR) is high.
8.3.2 Clear Register
A logical low on (SRCLR) clears all registers in the device. TI suggests clearing the device during power up or
initialization.
8.3.3 Output Control
Holding the output enable (G) high holds all data in the output buffers low, and all drain outputs are off. Holding
(G) low makes data from the storage register transparent to the output buffers. When data in the output buffers is
low, the DMOS transistor outputs are OFF. When data is high, the DMOS transistor outputs have sink-current
capability. This pin can also be used for global PWM dimming.
8.3.4 Cascaded Application
The serial output (SER OUT) allows for cascading of the data from the shift register to additional devices.
Connect the device (SEROUT) pin to the next device (SERIN) for daisy Chain. This provides improved
performance for applications where clock signals may be skewed, devices are not located near one another, or
the system must tolerate electromagnetic interference.
8.3.5 Current Limit Function
Outputs are low-side, open-drain DMOS transistors with output ratings of 50 V and 150-mA continuous sink
current capability. Each output provides a 500-mA typical current limit at TC = 25°C. The current limit decreases
as the junction temperature increases for additional device protection.
12
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8.4 Device Functional Modes
8.4.1 Operation With V(VCC) & lt; 4.5 (Minimum V(VCC))
This device works normally during 4.5 V ≤ V(VCC) ≤ 5.5 V, when operation voltage is lower than 4.5 V. TI can't
ensure the behavior of device, including communication interface and current capability.
8.4.2 Operating With 5.5 V & lt; V(VCC) & lt; 6 V
This device works normally during this voltage range, but reliability issues may occur while the device works for a
long time in this voltage range.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPIC6B595 device is a serial-in parallel-out, Power+LogicE 8-bit shift register with low-side switch DMOS
outputs rating of a 150 mA per channel. The device is designed for use in systems that require relatively high
load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power
driver applications include relays, solenoids, and other medium currentor high-voltage loads. The following
focuses on automotive cluster applications for the TPIC6B595 device.
9.2 Typical Application
The typical application of the TPIC6B595 device is the automotive cluster driver. In this example, two TPIC6B595
power shift registers are cascaded and used to turn on LEDs in the cluster panel. In this case, the LED must be
updated after all 16 bits of data have been loaded into the serial shift registers. MCU outputs the data to the
serial input (SER IN) while clocking the shift register clock (SRCK). After the 16th clock, a pulse to the register
clock (RCK) transfers the data to the storage registers. If output enable (G) is low, then the LEDs are turned ON
corresponding to the status word with ones being ON and zeros OFF. With this simple scheme, MCU use SPI
interface can turn on 16 LEDs using only two ICs as illustrated in Figure 14.
Vbattery
Vbattery
5V
5V
R1
R2
R3
R4
R5
R6
R7
R9
R8
0.1 uF
10 k
R9
R9
R9
R9
R9
R9
D9
D10
D11
D12
D13
D14
D15
D16
10 k
VCC
VCC
TPIC6B595
TPIC6B595
DRAIN0
SRCK
D1
D2
D3
D4
D5
D6
D7
DRAIN0
D8
SRCK
DRQIN2
DRAIN1
RCK
DRAIN1
RCK
MCU
R9
0.1 uF
DRQIN2
SER IN
DRAIN3
SER IN
DRAIN3
SRCLR
DRAIN4
SRCLR
DRAIN4
G
DRAIN5
G
DRAIN5
DRAIN6
DRAIN6
DRAIN7
DRAIN7
SER OUT
SER OUT
GND
TO SERIAL INPUT OF THE NEXT
STAGE
GND
Figure 14. Typical Application Schematic
9.2.1 Design Requirements
Use the design parameters in Table 1 for this design example.
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VSUPPLY
9-16 V
V(D1), V(D2), V(D3), V(D4), V(D5), V(D6),V(D7), V(D8)
3.3 V
I(D1), I(D2), I(D3), I(D4), I(D5), I(D6),I(D7), I(D8)
20mA When Vbattery is 12 V
I(D9), I(D10), I(D11), I(D12), I(D13), I(D14),I(D15), I(D16)
14
2V
V(D9), V(D10),V(D11), V(D12), V(D13), V(D14),V(D15), V(D16)
30mA When Vbattery is 12 V
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9.2.2 Detailed Design Procedure
To
•
•
•
begin the design process, one must decide on a few parameters. The designer must know the following:
Vsupply - LED supply is connect battery directly or fix voltage, this application connect the battery directly.
V(Dx) – LED forward voltage
I(Dx) – LED setting current when battery is 12 V.
R1,R2,R3,R4,R5,R6,R7,R8
R1
R2
R3
R4
R5
R6
R7
R8
V supply V(Dx) 12V 2V
I(Dx )
0.02A
500 :
(1)
When Vsupply is 9 V,
I(D1)
I(D2 )
I(D3 )
I(D4 )
I(D5 )
I(D6 )
I(D7 )
I(D4 )
I(D5 )
I(D6 )
I(D7 )
V supply V(Dx)
I(D8 )
I(D8 )
Rx
14mA
(2)
When Vsupply is 16 V,
I(D1)
I(D2 )
I(D3 )
V supply V(Dx)
Rx
28mA
(3)
R9,R10,R11,R12,R13,R14,R15,R16
R9
R10
R11
R12
R13
R14
R15
R16
V supply V(Dx) 12V 3.3V
I( Dx )
0.03A
290 :
(4)
When Vsupply is 9 V,
I(D9) I(D10 ) I(D11) I(D12 ) I(D13 ) I(D14 ) I(D15 ) I(D16 )
V supply V(Dx)
Rx
19.7mA
(5)
When Vsupply is 16 V,
I( D9 )
I( D10 )
I( D11)
I(D12 )
I(D13 )
I( D14 )
I( D15 )
I( D16 )
V supply V(Dx)
Rx
43.8mA
(6)
NOTE
If customers can accept the current variation when battery voltage is changing, they can
connect to the battery directly. If customers need the less variation of current, they must
use the voltage regulator as supply voltage of LED, or change to constant current LED
driver directly.
9.2.3 Application Curve
Figure 15. CH1 is SRCK, CH2 is RCK, CH3 is SER IN, CH4 is D1 current
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Copyright © 1995–2015, Texas Instruments Incorporated
Product Folder Links: TPIC6B595
15
TPIC6B595
SLIS032B – JULY 1995 – REVISED JUNE 2015
www.ti.com
10 Power Supply Recommendations
The TPIC6B595 device is designed to operate from an input voltage supply range from 4.5 V and 5.5 V. This
input supply should be well regulated. TI recommends placing the ceramic bypass capacitors near the VCC pin.
11 Layout
11.1 Layout Guidelines
There is no special layout requirement for the digital signal pin; the only requirement is placing the ceramic
bypass capacitors near the corresponding pin. Because the TPIC6B595 device does not have a thermal
shutdown protection function, to prevent thermal damage, TJ must be less than 150°C. If the total sink current is
high, the power dissipation might be large. The devices are currently not available in the thermal pad package,
so good PCB design can optimize heat transfer, which is absolutely essential for the long-term reliability of the
device. Maximize the copper coverage on the PCB to increase the thermal conductivity of the board, because the
major heat-flow path from the package to the ambient is through the copper on the PCB. Maximum copper is
extremely important when the design does not include heat sinks attached to the PCB on the other side of the
package.
• Add as many thermal vias as possible directly under the package ground pad to optimize the thermal
conductivity of the board.
• All thermal vias should be either plated shut or plugged and capped on both sides of the board to prevent
solder voids. To ensure reliability and performance, the solder coverage should be at least 85%.
16
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Copyright © 1995–2015, Texas Instruments Incorporated
Product Folder Links: TPIC6B595
TPIC6B595
www.ti.com
SLIS032B – JULY 1995 – REVISED JUNE 2015
11.2 Layout Example
Power Ground both
in TOP and Bottom
NC
NC
TPIC6B595
Vcc
GND
VIA to Ground
SER IN
SER OUT
DRAIN0
DRAIN7
DRAIN1
DRAIN6
DRAIN2
DRAIN5
DRAIN3
DRAIN4
SRCK
SRCLR
G
RCK
GND
GND
Figure 16. TPIC6B595 Layout Example
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Copyright © 1995–2015, Texas Instruments Incorporated
Product Folder Links: TPIC6B595
17
TPIC6B595
SLIS032B – JULY 1995 – REVISED JUNE 2015
www.ti.com
12 Device and Documentation Support
12.1 Community Resources
The following links connect to TI community resources. Linked contents are provided " AS IS " by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
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Product Folder Links: TPIC6B595
PACKAGE OPTION ADDENDUM
www.ti.com
15-Sep-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
TPIC6B595DW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPIC6B595DWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPIC6B595DWRG4
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPIC6B595N
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
Device Marking
(4/5)
Level-1-260C-UNLIM
TPIC6B595DWR
Op Temp (°C)
-40 to 125
TPIC6B595
TPIC6B595
-40 to 125
TPIC6B595
TPIC6B595
-40 to 125
TPIC6B595N
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms " Lead-Free " or " Pb-Free " mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines " Green " to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a " ~ " will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
15-Sep-2014
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Sep-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPIC6B595DWR
Package Package Pins
Type Drawing
SOIC
DW
20
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
24.4
Pack Materials-Page 1
10.8
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
13.3
2.7
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Sep-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPIC6B595DWR
SOIC
DW
20
2000
367.0
367.0
45.0
Pack Materials-Page 2
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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