Po ostatnich wątkach postanowiłem napisać mikroporadnik bo czytać się już tego nie da. Część pierwsza - jak podłaczyć STM32F103 BluePill do ST-Link z Nucleo i jak skonfigurować Atollic for STM32. Nieco przykurzone Nucleo STM32F446RE i BluePill 1. Zdejmij jumpery ze zworki ST-Link https://obrazki.elektroda.pl/9000536300_1547567868_thumb.jpg 2. Podłaczyć kabelkami zgodnie z poniższym rysunkiem. Można zamiast zasilania z USB użyć 3.3V z Nucleo (czerwony kabelek). Należy go podłaczyć do najniższego pinu w porcie SDW BluePill (to ten dolny niepodłączony na zdjęciu) https://obrazki.elektroda.pl/8184453600_1547567619_bigthumb.jpg 3. Zaimportować przykładowy projekt z tego postu (patrz na dole załączniki) Rozpakować archiwum do jakiegoś katalogu W Atollic: File-> Import https://obrazki.elektroda.pl/5327968900_1547384814_bigthumb.jpg Następnie: https://obrazki.elektroda.pl/4261784000_1547384853_bigthumb.jpg Później: (skopiuj pliki projektu bo zawsze możesz go skasować i jeszcze raz zaimportować jak coś schrzanisz) https://obrazki.elektroda.pl/9504563100_1547384936_bigthumb.jpg 4. "Odbuduj" projekt (ten młotek na żółto - w Twoim programie nie będzie na żółto - zaznaczyłem dla łatwiejszego znalezienia) https://obrazki.elektroda.pl/9648950100_1547568607_bigthumb.jpg 5. Następnie ustaw debugger https://obrazki.elektroda.pl/8781547300_1547569528_bigthumb.jpg Sprawdź czy widać tu nazwę naszego programu -tam gdzie wskazuje strzałka (strzałki nie będzie - została narysowana dla ułatwienia) https://obrazki.elektroda.pl/6840060000_1547569557_bigthumb.jpg Zmień zakładkę zgodnie z poniższym zdjęciem Sprawdź czy wybrany jest właściwy debugger -tam gdzie wskazuje strzałka (strzałki nie będzie - została narysowana dla ułatwienia) https://obrazki.elektroda.pl/3694200300_1547569693_bigthumb.jpg Kliknij DEBUG Powinno zacząć coś się dziać na elkranie i po kilku chwilach program się załaduje, a jego wykonywanie przerwane w funkcji main. Od tej pory możesz sobie debugować do woli. https://obrazki.elektroda.pl/6813597300_1547569841_bigthumb.jpg
/**
******************************************************************************
* @file stm32f1xx_hal_dma.c
* @author MCD Application Team
* @brief DMA HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Direct Memory Access (DMA) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral State and errors functions
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
(#) Enable and configure the peripheral to be connected to the DMA Channel
(except for internal SRAM / FLASH memories: no initialization is
necessary). Please refer to the Reference manual for connection between peripherals
and DMA requests.
(#) For a given Channel, program the required configuration through the following parameters:
Channel request, Transfer Direction, Source and Destination data formats,
Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
using HAL_DMA_Init() function.
(#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
detection.
(#) Use HAL_DMA_Abort() function to abort the current transfer
-@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
*** Polling mode IO operation ***
=================================
[..]
(+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
address and destination address and the Length of data to be transferred
(+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
case a fixed Timeout can be configured by User depending from his application.
*** Interrupt mode IO operation ***
===================================
[..]
(+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
(+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
(+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
Source address and destination address and the Length of data to be transferred.
In this case the DMA interrupt is configured
(+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
(+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
add his own function by customization of function pointer XferCpltCallback and
XferErrorCallback (i.e. a member of DMA handle structure).
*** DMA HAL driver macros list ***
=============================================
[..]
Below the list of most used macros in DMA HAL driver.
(+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
(+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
(+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
(+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
(+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
(+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
(+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
[..]
(@) You can refer to the DMA HAL driver header file for more useful macros
@endverbatim
******************************************************************************
* @attention
*
* & lt; h2 & gt; & lt; center & gt; & copy; COPYRIGHT(c) 2017 STMicroelectronics & lt; /center & gt; & lt; /h2 & gt;
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS " AS IS "
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include " stm32f1xx_hal.h "
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @defgroup DMA DMA
* @brief DMA HAL module driver
* @{
*/
#ifdef HAL_DMA_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup DMA_Private_Functions DMA Private Functions
* @{
*/
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
/**
* @}
*/
/* Exported functions ---------------------------------------------------------*/
/** @defgroup DMA_Exported_Functions DMA Exported Functions
* @{
*/
/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and de-initialization functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..]
This section provides functions allowing to initialize the DMA Channel source
and destination addresses, incrementation and data sizes, transfer direction,
circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
[..]
The HAL_DMA_Init() function follows the DMA configuration procedures as described in
reference manual.
@endverbatim
* @{
*/
/**
* @brief Initialize the DMA according to the specified
* parameters in the DMA_InitTypeDef and initialize the associated handle.
* @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
uint32_t tmp = 0U;
/* Check the DMA handle allocation */
if(hdma == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma- & gt; Instance));
assert_param(IS_DMA_DIRECTION(hdma- & gt; Init.Direction));
assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma- & gt; Init.PeriphInc));
assert_param(IS_DMA_MEMORY_INC_STATE(hdma- & gt; Init.MemInc));
assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma- & gt; Init.PeriphDataAlignment));
assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma- & gt; Init.MemDataAlignment));
assert_param(IS_DMA_MODE(hdma- & gt; Init.Mode));
assert_param(IS_DMA_PRIORITY(hdma- & gt; Init.Priority));
#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
/* calculation of the channel index */
if ((uint32_t)(hdma- & gt; Instance) & lt; (uint32_t)(DMA2_Channel1))
{
/* DMA1 */
hdma- & gt; ChannelIndex = (((uint32_t)hdma- & gt; Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) & lt; & lt; 2;
hdma- & gt; DmaBaseAddress = DMA1;
}
else
{
/* DMA2 */
hdma- & gt; ChannelIndex = (((uint32_t)hdma- & gt; Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) & lt; & lt; 2;
hdma- & gt; DmaBaseAddress = DMA2;
}
#else
/* DMA1 */
hdma- & gt; ChannelIndex = (((uint32_t)hdma- & gt; Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) & lt; & lt; 2;
hdma- & gt; DmaBaseAddress = DMA1;
#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F100xE || STM32F105xC || STM32F107xC */
/* Change DMA peripheral state */
hdma- & gt; State = HAL_DMA_STATE_BUSY;
/* Get the CR register value */
tmp = hdma- & gt; Instance- & gt; CCR;
/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
tmp & = ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
DMA_CCR_DIR));
/* Prepare the DMA Channel configuration */
tmp |= hdma- & gt; Init.Direction |
hdma- & gt; Init.PeriphInc | hdma- & gt; Init.MemInc |
hdma- & gt; Init.PeriphDataAlignment | hdma- & gt; Init.MemDataAlignment |
hdma- & gt; Init.Mode | hdma- & gt; Init.Priority;
/* Write to DMA Channel CR register */
hdma- & gt; Instance- & gt; CCR = tmp;
/* Clean callbacks */
hdma- & gt; XferCpltCallback = NULL;
hdma- & gt; XferHalfCpltCallback = NULL;
hdma- & gt; XferErrorCallback = NULL;
hdma- & gt; XferAbortCallback = NULL;
/* Initialise the error code */
hdma- & gt; ErrorCode = HAL_DMA_ERROR_NONE;
/* Initialize the DMA state*/
hdma- & gt; State = HAL_DMA_STATE_READY;
/* Allocate lock resource and initialize it */
hdma- & gt; Lock = HAL_UNLOCKED;
return HAL_OK;
}
/**
* @brief DeInitialize the DMA peripheral.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
{
/* Check the DMA handle allocation */
if(hdma == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma- & gt; Instance));
/* Disable the selected DMA Channelx */
__HAL_DMA_DISABLE(hdma);
/* Reset DMA Channel control register */
hdma- & gt; Instance- & gt; CCR = 0U;
/* Reset DMA Channel Number of Data to Transfer register */
hdma- & gt; Instance- & gt; CNDTR = 0U;
/* Reset DMA Channel peripheral address register */
hdma- & gt; Instance- & gt; CPAR = 0U;
/* Reset DMA Channel memory address register */
hdma- & gt; Instance- & gt; CMAR = 0U;
#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
/* calculation of the channel index */
if ((uint32_t)(hdma- & gt; Instance) & lt; (uint32_t)(DMA2_Channel1))
{
/* DMA1 */
hdma- & gt; ChannelIndex = (((uint32_t)hdma- & gt; Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) & lt; & lt; 2;
hdma- & gt; DmaBaseAddress = DMA1;
}
else
{
/* DMA2 */
hdma- & gt; ChannelIndex = (((uint32_t)hdma- & gt; Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) & lt; & lt; 2;
hdma- & gt; DmaBaseAddress = DMA2;
}
#else
/* DMA1 */
hdma- & gt; ChannelIndex = (((uint32_t)hdma- & gt; Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) & lt; & lt; 2;
hdma- & gt; DmaBaseAddress = DMA1;
#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F100xE || STM32F105xC || STM32F107xC */
/* Clear all flags */
hdma- & gt; DmaBaseAddress- & gt; IFCR = (DMA_ISR_GIF1 & lt; & lt; (hdma- & gt; ChannelIndex));
/* Initialize the error code */
hdma- & gt; ErrorCode = HAL_DMA_ERROR_NONE;
/* Initialize the DMA state */
hdma- & gt; State = HAL_DMA_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hdma);
return HAL_OK;
}
/**
* @}
*/
/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
* @brief Input and Output operation functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure the source, destination address and data length and Start DMA transfer
(+) Configure the source, destination address and data length and
Start DMA transfer with interrupt
(+) Abort DMA transfer
(+) Poll for transfer complete
(+) Handle DMA interrupt request
@endverbatim
* @{
*/
/**
* @brief Start the DMA Transfer.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @param SrcAddress: The source memory Buffer address
* @param DstAddress: The destination memory Buffer address
* @param DataLength: The length of data to be transferred from source to destination
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
/* Process locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma- & gt; State)
{
/* Change DMA peripheral state */
hdma- & gt; State = HAL_DMA_STATE_BUSY;
hdma- & gt; ErrorCode = HAL_DMA_ERROR_NONE;
/* Disable the peripheral */
__HAL_DMA_DISABLE(hdma);
/* Configure the source, destination address and the data length & clear flags*/
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
/* Enable the Peripheral */
__HAL_DMA_ENABLE(hdma);
}
else
{
/* Process Unlocked */
__HAL_UNLOCK(hdma);
status = HAL_BUSY;
}
return status;
}
/**
* @brief Start the DMA Transfer with interrupt enabled.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @param SrcAddress: The source memory Buffer address
* @param DstAddress: The destination memory Buffer address
* @param DataLength: The length of data to be transferred from source to destination
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
/* Process locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma- & gt; State)
{
/* Change DMA peripheral state */
hdma- & gt; State = HAL_DMA_STATE_BUSY;
hdma- & gt; ErrorCode = HAL_DMA_ERROR_NONE;
/* Disable the peripheral */
__HAL_DMA_DISABLE(hdma);
/* Configure the source, destination address and the data length & clear flags*/
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
/* Enable the transfer complete interrupt */
/* Enable the transfer Error interrupt */
if(NULL != hdma- & gt; XferHalfCpltCallback)
{
/* Enable the Half transfer complete interrupt as well */
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
}
else
{
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
}
/* Enable the Peripheral */
__HAL_DMA_ENABLE(hdma);
}
else
{
/* Process Unlocked */
__HAL_UNLOCK(hdma);
/* Remain BUSY */
status = HAL_BUSY;
}
return status;
}
/**
* @brief Abort the DMA Transfer.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{
HAL_StatusTypeDef status = HAL_OK;
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
/* Clear all flags */
hdma- & gt; DmaBaseAddress- & gt; IFCR = (DMA_ISR_GIF1 & lt; & lt; hdma- & gt; ChannelIndex);
/* Change the DMA state */
hdma- & gt; State = HAL_DMA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
return status;
}
/**
* @brief Aborts the DMA Transfer in Interrupt mode.
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{
HAL_StatusTypeDef status = HAL_OK;
if(HAL_DMA_STATE_BUSY != hdma- & gt; State)
{
/* no transfer ongoing */
hdma- & gt; ErrorCode = HAL_DMA_ERROR_NO_XFER;
status = HAL_ERROR;
}
else
{
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
/* Clear all flags */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
/* Change the DMA state */
hdma- & gt; State = HAL_DMA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
/* Call User Abort callback */
if(hdma- & gt; XferAbortCallback != NULL)
{
hdma- & gt; XferAbortCallback(hdma);
}
}
return status;
}
/**
* @brief Polling for transfer complete.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @param CompleteLevel: Specifies the DMA level complete.
* @param Timeout: Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
{
uint32_t temp;
uint32_t tickstart = 0U;
if(HAL_DMA_STATE_BUSY != hdma- & gt; State)
{
/* no transfer ongoing */
hdma- & gt; ErrorCode = HAL_DMA_ERROR_NO_XFER;
__HAL_UNLOCK(hdma);
return HAL_ERROR;
}
/* Polling mode not supported in circular mode */
if (RESET != (hdma- & gt; Instance- & gt; CCR & DMA_CCR_CIRC))
{
hdma- & gt; ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
return HAL_ERROR;
}
/* Get the level transfer complete flag */
if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
{
/* Transfer Complete flag */
temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
}
else
{
/* Half Transfer Complete flag */
temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
}
/* Get tick */
tickstart = HAL_GetTick();
while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
{
if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET))
{
/* When a DMA transfer error occurs */
/* A hardware clear of its EN bits is performed */
/* Clear all flags */
hdma- & gt; DmaBaseAddress- & gt; IFCR = (DMA_ISR_GIF1 & lt; & lt; hdma- & gt; ChannelIndex);
/* Update error code */
SET_BIT(hdma- & gt; ErrorCode, HAL_DMA_ERROR_TE);
/* Change the DMA state */
hdma- & gt; State= HAL_DMA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
return HAL_ERROR;
}
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0U) || ((HAL_GetTick() - tickstart) & gt; Timeout))
{
/* Update error code */
SET_BIT(hdma- & gt; ErrorCode, HAL_DMA_ERROR_TIMEOUT);
/* Change the DMA state */
hdma- & gt; State = HAL_DMA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
return HAL_ERROR;
}
}
}
if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
{
/* Clear the transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
/* The selected Channelx EN bit is cleared (DMA is disabled and
all transfers are complete) */
hdma- & gt; State = HAL_DMA_STATE_READY;
}
else
{
/* Clear the half transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
}
/* Process unlocked */
__HAL_UNLOCK(hdma);
return HAL_OK;
}
/**
* @brief Handles DMA interrupt request.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval None
*/
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
{
uint32_t flag_it = hdma- & gt; DmaBaseAddress- & gt; ISR;
uint32_t source_it = hdma- & gt; Instance- & gt; CCR;
/* Half Transfer Complete Interrupt management ******************************/
if (((flag_it & (DMA_FLAG_HT1 & lt; & lt; hdma- & gt; ChannelIndex)) != RESET) & & ((source_it & DMA_IT_HT) != RESET))
{
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
if((hdma- & gt; Instance- & gt; CCR & DMA_CCR_CIRC) == 0U)
{
/* Disable the half transfer interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
}
/* Clear the half transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
/* DMA peripheral state is not updated in Half Transfer */
/* but in Transfer Complete case */
if(hdma- & gt; XferHalfCpltCallback != NULL)
{
/* Half transfer callback */
hdma- & gt; XferHalfCpltCallback(hdma);
}
}
/* Transfer Complete Interrupt management ***********************************/
else if (((flag_it & (DMA_FLAG_TC1 & lt; & lt; hdma- & gt; ChannelIndex)) != RESET) & & ((source_it & DMA_IT_TC) != RESET))
{
if((hdma- & gt; Instance- & gt; CCR & DMA_CCR_CIRC) == 0U)
{
/* Disable the transfer complete and error interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
/* Change the DMA state */
hdma- & gt; State = HAL_DMA_STATE_READY;
}
/* Clear the transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
/* Process Unlocked */
__HAL_UNLOCK(hdma);
if(hdma- & gt; XferCpltCallback != NULL)
{
/* Transfer complete callback */
hdma- & gt; XferCpltCallback(hdma);
}
}
/* Transfer Error Interrupt management **************************************/
else if (( RESET != (flag_it & (DMA_FLAG_TE1 & lt; & lt; hdma- & gt; ChannelIndex))) & & (RESET != (source_it & DMA_IT_TE)))
{
/* When a DMA transfer error occurs */
/* A hardware clear of its EN bits is performed */
/* Disable ALL DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
/* Clear all flags */
hdma- & gt; DmaBaseAddress- & gt; IFCR = (DMA_ISR_GIF1 & lt; & lt; hdma- & gt; ChannelIndex);
/* Update error code */
hdma- & gt; ErrorCode = HAL_DMA_ERROR_TE;
/* Change the DMA state */
hdma- & gt; State = HAL_DMA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
if (hdma- & gt; XferErrorCallback != NULL)
{
/* Transfer error callback */
hdma- & gt; XferErrorCallback(hdma);
}
}
return;
}
/**
* @brief Register callbacks
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @param CallbackID: User Callback identifer
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
* @param pCallback: pointer to private callbacsk function which has pointer to
* a DMA_HandleTypeDef structure as parameter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma- & gt; State)
{
switch (CallbackID)
{
case HAL_DMA_XFER_CPLT_CB_ID:
hdma- & gt; XferCpltCallback = pCallback;
break;
case HAL_DMA_XFER_HALFCPLT_CB_ID:
hdma- & gt; XferHalfCpltCallback = pCallback;
break;
case HAL_DMA_XFER_ERROR_CB_ID:
hdma- & gt; XferErrorCallback = pCallback;
break;
case HAL_DMA_XFER_ABORT_CB_ID:
hdma- & gt; XferAbortCallback = pCallback;
break;
default:
status = HAL_ERROR;
break;
}
}
else
{
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hdma);
return status;
}
/**
* @brief UnRegister callbacks
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @param CallbackID: User Callback identifer
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma- & gt; State)
{
switch (CallbackID)
{
case HAL_DMA_XFER_CPLT_CB_ID:
hdma- & gt; XferCpltCallback = NULL;
break;
case HAL_DMA_XFER_HALFCPLT_CB_ID:
hdma- & gt; XferHalfCpltCallback = NULL;
break;
case HAL_DMA_XFER_ERROR_CB_ID:
hdma- & gt; XferErrorCallback = NULL;
break;
case HAL_DMA_XFER_ABORT_CB_ID:
hdma- & gt; XferAbortCallback = NULL;
break;
case HAL_DMA_XFER_ALL_CB_ID:
hdma- & gt; XferCpltCallback = NULL;
hdma- & gt; XferHalfCpltCallback = NULL;
hdma- & gt; XferErrorCallback = NULL;
hdma- & gt; XferAbortCallback = NULL;
break;
default:
status = HAL_ERROR;
break;
}
}
else
{
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hdma);
return status;
}
/**
* @}
*/
/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief Peripheral State and Errors functions
*
@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
===============================================================================
[..]
This subsection provides functions allowing to
(+) Check the DMA state
(+) Get error code
@endverbatim
* @{
*/
/**
* @brief Return the DMA hande state.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL state
*/
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
{
/* Return DMA handle state */
return hdma- & gt; State;
}
/**
* @brief Return the DMA error code.
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval DMA Error Code
*/
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
{
return hdma- & gt; ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup DMA_Private_Functions
* @{
*/
/**
* @brief Sets the DMA Transfer parameter.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @param SrcAddress: The source memory Buffer address
* @param DstAddress: The destination memory Buffer address
* @param DataLength: The length of data to be transferred from source to destination
* @retval HAL status
*/
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
/* Clear all flags */
hdma- & gt; DmaBaseAddress- & gt; IFCR = (DMA_ISR_GIF1 & lt; & lt; hdma- & gt; ChannelIndex);
/* Configure DMA Channel data length */
hdma- & gt; Instance- & gt; CNDTR = DataLength;
/* Memory to Peripheral */
if((hdma- & gt; Init.Direction) == DMA_MEMORY_TO_PERIPH)
{
/* Configure DMA Channel destination address */
hdma- & gt; Instance- & gt; CPAR = DstAddress;
/* Configure DMA Channel source address */
hdma- & gt; Instance- & gt; CMAR = SrcAddress;
}
/* Peripheral to Memory */
else
{
/* Configure DMA Channel source address */
hdma- & gt; Instance- & gt; CPAR = SrcAddress;
/* Configure DMA Channel destination address */
hdma- & gt; Instance- & gt; CMAR = DstAddress;
}
}
/**
* @}
*/
#endif /* HAL_DMA_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file stm32f1xx_hal_tim.c
* @author MCD Application Team
* @brief TIM HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the Timer (TIM) peripheral:
* + Time Base Initialization
* + Time Base Start
* + Time Base Start Interruption
* + Time Base Start DMA
* + Time Output Compare/PWM Initialization
* + Time Output Compare/PWM Channel Configuration
* + Time Output Compare/PWM Start
* + Time Output Compare/PWM Start Interruption
* + Time Output Compare/PWM Start DMA
* + Time Input Capture Initialization
* + Time Input Capture Channel Configuration
* + Time Input Capture Start
* + Time Input Capture Start Interruption
* + Time Input Capture Start DMA
* + Time One Pulse Initialization
* + Time One Pulse Channel Configuration
* + Time One Pulse Start
* + Time Encoder Interface Initialization
* + Time Encoder Interface Start
* + Time Encoder Interface Start Interruption
* + Time Encoder Interface Start DMA
* + Commutation Event configuration with Interruption and DMA
* + Time OCRef clear configuration
* + Time External Clock configuration
@verbatim
==============================================================================
##### TIMER Generic features #####
==============================================================================
[..] The Timer features include:
(#) 16-bit up, down, up/down auto-reload counter.
(#) 16-bit programmable prescaler allowing dividing (also on the fly) the
counter clock frequency either by any factor between 1 and 65536.
(#) Up to 4 independent channels for:
(++) Input Capture
(++) Output Compare
(++) PWM generation (Edge and Center-aligned Mode)
(++) One-pulse mode output
##### How to use this driver #####
==============================================================================
[..]
(#) Initialize the TIM low level resources by implementing the following functions
depending from feature used :
(++) Time Base : HAL_TIM_Base_MspInit()
(++) Input Capture : HAL_TIM_IC_MspInit()
(++) Output Compare : HAL_TIM_OC_MspInit()
(++) PWM generation : HAL_TIM_PWM_MspInit()
(++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
(++) Encoder mode output : HAL_TIM_Encoder_MspInit()
(#) Initialize the TIM low level resources :
(##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
(##) TIM pins configuration
(+++) Enable the clock for the TIM GPIOs using the following function:
__HAL_RCC_GPIOx_CLK_ENABLE();
(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
(#) The external Clock can be configured, if needed (the default clock is the
internal clock from the APBx), using the following function:
HAL_TIM_ConfigClockSource, the clock configuration should be done before
any start function.
(#) Configure the TIM in the desired functioning mode using one of the
Initialization function of this driver:
(++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
(++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
Output Compare signal.
(++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
PWM signal.
(++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
external signal.
(++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
in One Pulse Mode.
(++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
(#) Activate the TIM peripheral using one of the start functions depending from the feature used:
(++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
(++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
(++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
(++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
(++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
(++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
(#) The DMA Burst is managed with the two following functions:
HAL_TIM_DMABurst_WriteStart()
HAL_TIM_DMABurst_ReadStart()
@endverbatim
******************************************************************************
* @attention
*
* & lt; h2 & gt; & lt; center & gt; & copy; COPYRIGHT(c) 2016 STMicroelectronics & lt; /center & gt; & lt; /h2 & gt;
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS " AS IS "
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include " stm32f1xx_hal.h "
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @defgroup TIM TIM
* @brief TIM HAL module driver
* @{
*/
#ifdef HAL_TIM_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup TIM_Private_Functions TIM Private Functions
* @{
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
uint32_t TIM_ICFilter);
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
uint32_t TIM_ICFilter);
static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
uint32_t TIM_ICFilter);
static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
TIM_SlaveConfigTypeDef * sSlaveConfig);
/**
* @}
*/
/* Exported functions ---------------------------------------------------------*/
/** @defgroup TIM_Exported_Functions TIM Exported Functions
* @{
*/
/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
* @brief Time Base functions
*
@verbatim
==============================================================================
##### Time Base functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Initialize and configure the TIM base.
(+) De-initialize the TIM base.
(+) Start the Time Base.
(+) Stop the Time Base.
(+) Start the Time Base and enable interrupt.
(+) Stop the Time Base and disable interrupt.
(+) Start the Time Base and enable DMA transfer.
(+) Stop the Time Base and disable DMA transfer.
@endverbatim
* @{
*/
/**
* @brief Initializes the TIM Time base Unit according to the specified
* parameters in the TIM_HandleTypeDef and create the associated handle.
* @param htim : TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
/* Check the TIM handle allocation */
if(htim == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim- & gt; Instance));
assert_param(IS_TIM_COUNTER_MODE(htim- & gt; Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim- & gt; Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim- & gt; Init.AutoReloadPreload));
if(htim- & gt; State == HAL_TIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
htim- & gt; Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
}
/* Set the TIM state */
htim- & gt; State= HAL_TIM_STATE_BUSY;
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim- & gt; Instance, & htim- & gt; Init);
/* Initialize the TIM state*/
htim- & gt; State= HAL_TIM_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitializes the TIM Base peripheral
* @param htim : TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim- & gt; Instance));
htim- & gt; State = HAL_TIM_STATE_BUSY;
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspDeInit(htim);
/* Change TIM state */
htim- & gt; State = HAL_TIM_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(htim);
return HAL_OK;
}
/**
* @brief Initializes the TIM Base MSP.
* @param htim : TIM handle
* @retval None
*/
__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_Base_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes TIM Base MSP.
* @param htim : TIM handle
* @retval None
*/
__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_Base_MspDeInit could be implemented in the user file
*/
}
/**
* @brief Starts the TIM Base generation.
* @param htim : TIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim- & gt; Instance));
/* Set the TIM state */
htim- & gt; State= HAL_TIM_STATE_BUSY;
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
/* Change the TIM state*/
htim- & gt; State= HAL_TIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Stops the TIM Base generation.
* @param htim : TIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim- & gt; Instance));
/* Set the TIM state */
htim- & gt; State= HAL_TIM_STATE_BUSY;
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Change the TIM state*/
htim- & gt; State= HAL_TIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Starts the TIM Base generation in interrupt mode.
* @param htim : TIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim- & gt; Instance));
/* Enable the TIM Update interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Stops the TIM Base generation in interrupt mode.
* @param htim : TIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim- & gt; Instance));
/* Disable the TIM Update interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Starts the TIM Base generation in DMA mode.
* @param htim : TIM handle
* @param pData : The source Buffer address.
* @param Length : The length of data to be transferred from memory to peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
{
/* Check the parameters */
assert_param(IS_TIM_DMA_INSTANCE(htim- & gt; Instance));
if((htim- & gt; State == HAL_TIM_STATE_BUSY))
{
return HAL_BUSY;
}
else if((htim- & gt; State == HAL_TIM_STATE_READY))
{
if((pData == 0U) & & (Length & gt; 0U))
{
return HAL_ERROR;
}
else
{
htim- & gt; State = HAL_TIM_STATE_BUSY;
}
}
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_UPDATE]- & gt; XferCpltCallback = TIM_DMAPeriodElapsedCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_UPDATE]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t) & htim- & gt; Instance- & gt; ARR, Length);
/* Enable the TIM Update DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Stops the TIM Base generation in DMA mode.
* @param htim : TIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
{
/* Check the parameters */
assert_param(IS_TIM_DMA_INSTANCE(htim- & gt; Instance));
/* Disable the TIM Update DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Change the htim state */
htim- & gt; State = HAL_TIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
* @brief Time Output Compare functions
*
@verbatim
==============================================================================
##### Time Output Compare functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Initialize and configure the TIM Output Compare.
(+) De-initialize the TIM Output Compare.
(+) Start the Time Output Compare.
(+) Stop the Time Output Compare.
(+) Start the Time Output Compare and enable interrupt.
(+) Stop the Time Output Compare and disable interrupt.
(+) Start the Time Output Compare and enable DMA transfer.
(+) Stop the Time Output Compare and disable DMA transfer.
@endverbatim
* @{
*/
/**
* @brief Initializes the TIM Output Compare according to the specified
* parameters in the TIM_HandleTypeDef and create the associated handle.
* @param htim : TIM Output Compare handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
{
/* Check the TIM handle allocation */
if(htim == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim- & gt; Instance));
assert_param(IS_TIM_COUNTER_MODE(htim- & gt; Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim- & gt; Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim- & gt; Init.AutoReloadPreload));
if(htim- & gt; State == HAL_TIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
htim- & gt; Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_OC_MspInit(htim);
}
/* Set the TIM state */
htim- & gt; State= HAL_TIM_STATE_BUSY;
/* Init the base time for the Output Compare */
TIM_Base_SetConfig(htim- & gt; Instance, & htim- & gt; Init);
/* Initialize the TIM state*/
htim- & gt; State= HAL_TIM_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitializes the TIM peripheral
* @param htim : TIM Output Compare handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim- & gt; Instance));
htim- & gt; State = HAL_TIM_STATE_BUSY;
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
HAL_TIM_OC_MspDeInit(htim);
/* Change TIM state */
htim- & gt; State = HAL_TIM_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(htim);
return HAL_OK;
}
/**
* @brief Initializes the TIM Output Compare MSP.
* @param htim : TIM handle
* @retval None
*/
__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_OC_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes TIM Output Compare MSP.
* @param htim : TIM handle
* @retval None
*/
__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_OC_MspDeInit could be implemented in the user file
*/
}
/**
* @brief Starts the TIM Output Compare signal generation.
* @param htim : TIM Output Compare handle
* @param Channel : TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim- & gt; Instance, Channel));
/* Enable the Output compare channel */
TIM_CCxChannelCmd(htim- & gt; Instance, Channel, TIM_CCx_ENABLE);
if(IS_TIM_BREAK_INSTANCE(htim- & gt; Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Stops the TIM Output Compare signal generation.
* @param htim : TIM handle
* @param Channel : TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim- & gt; Instance, Channel));
/* Disable the Output compare channel */
TIM_CCxChannelCmd(htim- & gt; Instance, Channel, TIM_CCx_DISABLE);
if(IS_TIM_BREAK_INSTANCE(htim- & gt; Instance) != RESET)
{
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
}
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Starts the TIM Output Compare signal generation in interrupt mode.
* @param htim : TIM OC handle
* @param Channel : TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim- & gt; Instance, Channel));
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
}
break;
case TIM_CHANNEL_2:
{
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
}
break;
case TIM_CHANNEL_3:
{
/* Enable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
}
break;
case TIM_CHANNEL_4:
{
/* Enable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
}
break;
default:
break;
}
/* Enable the Output compare channel */
TIM_CCxChannelCmd(htim- & gt; Instance, Channel, TIM_CCx_ENABLE);
if(IS_TIM_BREAK_INSTANCE(htim- & gt; Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Stops the TIM Output Compare signal generation in interrupt mode.
* @param htim : TIM Output Compare handle
* @param Channel : TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim- & gt; Instance, Channel));
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Disable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
}
break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
}
break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
}
break;
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
}
break;
default:
break;
}
/* Disable the Output compare channel */
TIM_CCxChannelCmd(htim- & gt; Instance, Channel, TIM_CCx_DISABLE);
if(IS_TIM_BREAK_INSTANCE(htim- & gt; Instance) != RESET)
{
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
}
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Starts the TIM Output Compare signal generation in DMA mode.
* @param htim : TIM Output Compare handle
* @param Channel : TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @param pData : The source Buffer address.
* @param Length : The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim- & gt; Instance, Channel));
if((htim- & gt; State == HAL_TIM_STATE_BUSY))
{
return HAL_BUSY;
}
else if((htim- & gt; State == HAL_TIM_STATE_READY))
{
if(((uint32_t)pData == 0U) & & (Length & gt; 0U))
{
return HAL_ERROR;
}
else
{
htim- & gt; State = HAL_TIM_STATE_BUSY;
}
}
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_CC1]- & gt; XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_CC1]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t) & htim- & gt; Instance- & gt; CCR1, Length);
/* Enable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
}
break;
case TIM_CHANNEL_2:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_CC2]- & gt; XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_CC2]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t) & htim- & gt; Instance- & gt; CCR2, Length);
/* Enable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
}
break;
case TIM_CHANNEL_3:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_CC3]- & gt; XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_CC3]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t) & htim- & gt; Instance- & gt; CCR3,Length);
/* Enable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
}
break;
case TIM_CHANNEL_4:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_CC4]- & gt; XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_CC4]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t) & htim- & gt; Instance- & gt; CCR4, Length);
/* Enable the TIM Capture/Compare 4 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
}
break;
default:
break;
}
/* Enable the Output compare channel */
TIM_CCxChannelCmd(htim- & gt; Instance, Channel, TIM_CCx_ENABLE);
if(IS_TIM_BREAK_INSTANCE(htim- & gt; Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Stops the TIM Output Compare signal generation in DMA mode.
* @param htim : TIM Output Compare handle
* @param Channel : TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim- & gt; Instance, Channel));
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Disable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
}
break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
}
break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
}
break;
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
}
break;
default:
break;
}
/* Disable the Output compare channel */
TIM_CCxChannelCmd(htim- & gt; Instance, Channel, TIM_CCx_DISABLE);
if(IS_TIM_BREAK_INSTANCE(htim- & gt; Instance) != RESET)
{
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
}
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Change the htim state */
htim- & gt; State = HAL_TIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
* @brief Time PWM functions
*
@verbatim
==============================================================================
##### Time PWM functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Initialize and configure the TIM PWM.
(+) De-initialize the TIM PWM.
(+) Start the Time PWM.
(+) Stop the Time PWM.
(+) Start the Time PWM and enable interrupt.
(+) Stop the Time PWM and disable interrupt.
(+) Start the Time PWM and enable DMA transfer.
(+) Stop the Time PWM and disable DMA transfer.
@endverbatim
* @{
*/
/**
* @brief Initializes the TIM PWM Time Base according to the specified
* parameters in the TIM_HandleTypeDef and create the associated handle.
* @param htim : TIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
/* Check the TIM handle allocation */
if(htim == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim- & gt; Instance));
assert_param(IS_TIM_COUNTER_MODE(htim- & gt; Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim- & gt; Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim- & gt; Init.AutoReloadPreload));
if(htim- & gt; State == HAL_TIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
htim- & gt; Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
}
/* Set the TIM state */
htim- & gt; State= HAL_TIM_STATE_BUSY;
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim- & gt; Instance, & htim- & gt; Init);
/* Initialize the TIM state*/
htim- & gt; State= HAL_TIM_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitializes the TIM peripheral
* @param htim : TIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim- & gt; Instance));
htim- & gt; State = HAL_TIM_STATE_BUSY;
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspDeInit(htim);
/* Change TIM state */
htim- & gt; State = HAL_TIM_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(htim);
return HAL_OK;
}
/**
* @brief Initializes the TIM PWM MSP.
* @param htim : TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes TIM PWM MSP.
* @param htim : TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspDeInit could be implemented in the user file
*/
}
/**
* @brief Starts the PWM signal generation.
* @param htim : TIM handle
* @param Channel : TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim- & gt; Instance, Channel));
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim- & gt; Instance, Channel, TIM_CCx_ENABLE);
if(IS_TIM_BREAK_INSTANCE(htim- & gt; Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Stops the PWM signal generation.
* @param htim : TIM handle
* @param Channel : TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim- & gt; Instance, Channel));
/* Disable the Capture compare channel */
TIM_CCxChannelCmd(htim- & gt; Instance, Channel, TIM_CCx_DISABLE);
if(IS_TIM_BREAK_INSTANCE(htim- & gt; Instance) != RESET)
{
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
}
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Change the htim state */
htim- & gt; State = HAL_TIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Starts the PWM signal generation in interrupt mode.
* @param htim : TIM handle
* @param Channel : TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim- & gt; Instance, Channel));
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
}
break;
case TIM_CHANNEL_2:
{
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
}
break;
case TIM_CHANNEL_3:
{
/* Enable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
}
break;
case TIM_CHANNEL_4:
{
/* Enable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
}
break;
default:
break;
}
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim- & gt; Instance, Channel, TIM_CCx_ENABLE);
if(IS_TIM_BREAK_INSTANCE(htim- & gt; Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Stops the PWM signal generation in interrupt mode.
* @param htim : TIM handle
* @param Channel : TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim- & gt; Instance, Channel));
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Disable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
}
break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
}
break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
}
break;
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
}
break;
default:
break;
}
/* Disable the Capture compare channel */
TIM_CCxChannelCmd(htim- & gt; Instance, Channel, TIM_CCx_DISABLE);
if(IS_TIM_BREAK_INSTANCE(htim- & gt; Instance) != RESET)
{
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
}
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Starts the TIM PWM signal generation in DMA mode.
* @param htim : TIM handle
* @param Channel : TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @param pData : The source Buffer address.
* @param Length : The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim- & gt; Instance, Channel));
if((htim- & gt; State == HAL_TIM_STATE_BUSY))
{
return HAL_BUSY;
}
else if((htim- & gt; State == HAL_TIM_STATE_READY))
{
if(((uint32_t)pData == 0U) & & (Length & gt; 0U))
{
return HAL_ERROR;
}
else
{
htim- & gt; State = HAL_TIM_STATE_BUSY;
}
}
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_CC1]- & gt; XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_CC1]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t) & htim- & gt; Instance- & gt; CCR1, Length);
/* Enable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
}
break;
case TIM_CHANNEL_2:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_CC2]- & gt; XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_CC2]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t) & htim- & gt; Instance- & gt; CCR2, Length);
/* Enable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
}
break;
case TIM_CHANNEL_3:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_CC3]- & gt; XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_CC3]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t) & htim- & gt; Instance- & gt; CCR3,Length);
/* Enable the TIM Output Capture/Compare 3 request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
}
break;
case TIM_CHANNEL_4:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_CC4]- & gt; XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_CC4]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t) & htim- & gt; Instance- & gt; CCR4, Length);
/* Enable the TIM Capture/Compare 4 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
}
break;
default:
break;
}
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim- & gt; Instance, Channel, TIM_CCx_ENABLE);
if(IS_TIM_BREAK_INSTANCE(htim- & gt; Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Stops the TIM PWM signal generation in DMA mode.
* @param htim : TIM handle
* @param Channel : TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim- & gt; Instance, Channel));
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Disable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
}
break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
}
break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
}
break;
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
}
break;
default:
break;
}
/* Disable the Capture compare channel */
TIM_CCxChannelCmd(htim- & gt; Instance, Channel, TIM_CCx_DISABLE);
if(IS_TIM_BREAK_INSTANCE(htim- & gt; Instance) != RESET)
{
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
}
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Change the htim state */
htim- & gt; State = HAL_TIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
* @brief Time Input Capture functions
*
@verbatim
==============================================================================
##### Time Input Capture functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Initialize and configure the TIM Input Capture.
(+) De-initialize the TIM Input Capture.
(+) Start the Time Input Capture.
(+) Stop the Time Input Capture.
(+) Start the Time Input Capture and enable interrupt.
(+) Stop the Time Input Capture and disable interrupt.
(+) Start the Time Input Capture and enable DMA transfer.
(+) Stop the Time Input Capture and disable DMA transfer.
@endverbatim
* @{
*/
/**
* @brief Initializes the TIM Input Capture Time base according to the specified
* parameters in the TIM_HandleTypeDef and create the associated handle.
* @param htim : TIM Input Capture handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
{
/* Check the TIM handle allocation */
if(htim == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim- & gt; Instance));
assert_param(IS_TIM_COUNTER_MODE(htim- & gt; Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim- & gt; Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim- & gt; Init.AutoReloadPreload));
if(htim- & gt; State == HAL_TIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
htim- & gt; Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_IC_MspInit(htim);
}
/* Set the TIM state */
htim- & gt; State= HAL_TIM_STATE_BUSY;
/* Init the base time for the input capture */
TIM_Base_SetConfig(htim- & gt; Instance, & htim- & gt; Init);
/* Initialize the TIM state*/
htim- & gt; State= HAL_TIM_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitializes the TIM peripheral
* @param htim : TIM Input Capture handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim- & gt; Instance));
htim- & gt; State = HAL_TIM_STATE_BUSY;
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
HAL_TIM_IC_MspDeInit(htim);
/* Change TIM state */
htim- & gt; State = HAL_TIM_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(htim);
return HAL_OK;
}
/**
* @brief Initializes the TIM Input Capture MSP.
* @param htim : TIM handle
* @retval None
*/
__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_IC_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes TIM Input Capture MSP.
* @param htim : TIM handle
* @retval None
*/
__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_IC_MspDeInit could be implemented in the user file
*/
}
/**
* @brief Starts the TIM Input Capture measurement.
* @param htim : TIM Input Capture handle
* @param Channel : TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim- & gt; Instance, Channel));
/* Enable the Input Capture channel */
TIM_CCxChannelCmd(htim- & gt; Instance, Channel, TIM_CCx_ENABLE);
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Stops the TIM Input Capture measurement.
* @param htim : TIM handle
* @param Channel : TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim- & gt; Instance, Channel));
/* Disable the Input Capture channel */
TIM_CCxChannelCmd(htim- & gt; Instance, Channel, TIM_CCx_DISABLE);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Starts the TIM Input Capture measurement in interrupt mode.
* @param htim : TIM Input Capture handle
* @param Channel : TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim- & gt; Instance, Channel));
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
}
break;
case TIM_CHANNEL_2:
{
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
}
break;
case TIM_CHANNEL_3:
{
/* Enable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
}
break;
case TIM_CHANNEL_4:
{
/* Enable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
}
break;
default:
break;
}
/* Enable the Input Capture channel */
TIM_CCxChannelCmd(htim- & gt; Instance, Channel, TIM_CCx_ENABLE);
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Stops the TIM Input Capture measurement in interrupt mode.
* @param htim : TIM handle
* @param Channel : TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim- & gt; Instance, Channel));
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Disable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
}
break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
}
break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
}
break;
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
}
break;
default:
break;
}
/* Disable the Input Capture channel */
TIM_CCxChannelCmd(htim- & gt; Instance, Channel, TIM_CCx_DISABLE);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Starts the TIM Input Capture measurement in DMA mode.
* @param htim : TIM Input Capture handle
* @param Channel : TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @param pData : The destination Buffer address.
* @param Length : The length of data to be transferred from TIM peripheral to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim- & gt; Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim- & gt; Instance));
if((htim- & gt; State == HAL_TIM_STATE_BUSY))
{
return HAL_BUSY;
}
else if((htim- & gt; State == HAL_TIM_STATE_READY))
{
if((pData == 0U) & & (Length & gt; 0U))
{
return HAL_ERROR;
}
else
{
htim- & gt; State = HAL_TIM_STATE_BUSY;
}
}
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_CC1]- & gt; XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_CC1]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_CC1], (uint32_t) & htim- & gt; Instance- & gt; CCR1, (uint32_t)pData, Length);
/* Enable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
}
break;
case TIM_CHANNEL_2:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_CC2]- & gt; XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_CC2]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_CC2], (uint32_t) & htim- & gt; Instance- & gt; CCR2, (uint32_t)pData, Length);
/* Enable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
}
break;
case TIM_CHANNEL_3:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_CC3]- & gt; XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_CC3]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_CC3], (uint32_t) & htim- & gt; Instance- & gt; CCR3, (uint32_t)pData, Length);
/* Enable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
}
break;
case TIM_CHANNEL_4:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_CC4]- & gt; XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_CC4]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_CC4], (uint32_t) & htim- & gt; Instance- & gt; CCR4, (uint32_t)pData, Length);
/* Enable the TIM Capture/Compare 4 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
}
break;
default:
break;
}
/* Enable the Input Capture channel */
TIM_CCxChannelCmd(htim- & gt; Instance, Channel, TIM_CCx_ENABLE);
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Stops the TIM Input Capture measurement in DMA mode.
* @param htim : TIM Input Capture handle
* @param Channel : TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim- & gt; Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim- & gt; Instance));
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Disable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
}
break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
}
break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
}
break;
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
}
break;
default:
break;
}
/* Disable the Input Capture channel */
TIM_CCxChannelCmd(htim- & gt; Instance, Channel, TIM_CCx_DISABLE);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Change the htim state */
htim- & gt; State = HAL_TIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
* @brief Time One Pulse functions
*
@verbatim
==============================================================================
##### Time One Pulse functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Initialize and configure the TIM One Pulse.
(+) De-initialize the TIM One Pulse.
(+) Start the Time One Pulse.
(+) Stop the Time One Pulse.
(+) Start the Time One Pulse and enable interrupt.
(+) Stop the Time One Pulse and disable interrupt.
(+) Start the Time One Pulse and enable DMA transfer.
(+) Stop the Time One Pulse and disable DMA transfer.
@endverbatim
* @{
*/
/**
* @brief Initializes the TIM One Pulse Time Base according to the specified
* parameters in the TIM_HandleTypeDef and create the associated handle.
* @param htim : TIM OnePulse handle
* @param OnePulseMode : Select the One pulse mode.
* This parameter can be one of the following values:
* @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
* @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
{
/* Check the TIM handle allocation */
if(htim == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim- & gt; Instance));
assert_param(IS_TIM_COUNTER_MODE(htim- & gt; Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim- & gt; Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim- & gt; Init.AutoReloadPreload));
assert_param(IS_TIM_OPM_MODE(OnePulseMode));
if(htim- & gt; State == HAL_TIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
htim- & gt; Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_OnePulse_MspInit(htim);
}
/* Set the TIM state */
htim- & gt; State= HAL_TIM_STATE_BUSY;
/* Configure the Time base in the One Pulse Mode */
TIM_Base_SetConfig(htim- & gt; Instance, & htim- & gt; Init);
/* Reset the OPM Bit */
htim- & gt; Instance- & gt; CR1 & = ~TIM_CR1_OPM;
/* Configure the OPM Mode */
htim- & gt; Instance- & gt; CR1 |= OnePulseMode;
/* Initialize the TIM state*/
htim- & gt; State= HAL_TIM_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitializes the TIM One Pulse
* @param htim : TIM One Pulse handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim- & gt; Instance));
htim- & gt; State = HAL_TIM_STATE_BUSY;
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_TIM_OnePulse_MspDeInit(htim);
/* Change TIM state */
htim- & gt; State = HAL_TIM_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(htim);
return HAL_OK;
}
/**
* @brief Initializes the TIM One Pulse MSP.
* @param htim : TIM handle
* @retval None
*/
__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_OnePulse_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes TIM One Pulse MSP.
* @param htim : TIM handle
* @retval None
*/
__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
*/
}
/**
* @brief Starts the TIM One Pulse signal generation.
* @param htim : TIM One Pulse handle
* @param OutputChannel : TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(OutputChannel);
/* Enable the Capture compare and the Input Capture channels
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
No need to enable the counter, it's enabled automatically by hardware
(the counter starts in response to a stimulus and generate a pulse */
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
if(IS_TIM_BREAK_INSTANCE(htim- & gt; Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
/* Return function status */
return HAL_OK;
}
/**
* @brief Stops the TIM One Pulse signal generation.
* @param htim : TIM One Pulse handle
* @param OutputChannel : TIM Channels to be disable
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(OutputChannel);
/* Disable the Capture compare and the Input Capture channels
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
if(IS_TIM_BREAK_INSTANCE(htim- & gt; Instance) != RESET)
{
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
}
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Starts the TIM One Pulse signal generation in interrupt mode.
* @param htim : TIM One Pulse handle
* @param OutputChannel : TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(OutputChannel);
/* Enable the Capture compare and the Input Capture channels
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
No need to enable the counter, it's enabled automatically by hardware
(the counter starts in response to a stimulus and generate a pulse */
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
if(IS_TIM_BREAK_INSTANCE(htim- & gt; Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
/* Return function status */
return HAL_OK;
}
/**
* @brief Stops the TIM One Pulse signal generation in interrupt mode.
* @param htim : TIM One Pulse handle
* @param OutputChannel : TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(OutputChannel);
/* Disable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
/* Disable the Capture compare and the Input Capture channels
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
if(IS_TIM_BREAK_INSTANCE(htim- & gt; Instance) != RESET)
{
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
}
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
* @brief Time Encoder functions
*
@verbatim
==============================================================================
##### Time Encoder functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Initialize and configure the TIM Encoder.
(+) De-initialize the TIM Encoder.
(+) Start the Time Encoder.
(+) Stop the Time Encoder.
(+) Start the Time Encoder and enable interrupt.
(+) Stop the Time Encoder and disable interrupt.
(+) Start the Time Encoder and enable DMA transfer.
(+) Stop the Time Encoder and disable DMA transfer.
@endverbatim
* @{
*/
/**
* @brief Initializes the TIM Encoder Interface and create the associated handle.
* @param htim : TIM Encoder Interface handle
* @param sConfig : TIM Encoder Interface configuration structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
{
uint32_t tmpsmcr = 0U;
uint32_t tmpccmr1 = 0U;
uint32_t tmpccer = 0U;
/* Check the TIM handle allocation */
if(htim == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim- & gt; Instance));
assert_param(IS_TIM_COUNTER_MODE(htim- & gt; Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim- & gt; Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim- & gt; Init.AutoReloadPreload));
assert_param(IS_TIM_ENCODER_MODE(sConfig- & gt; EncoderMode));
assert_param(IS_TIM_IC_SELECTION(sConfig- & gt; IC1Selection));
assert_param(IS_TIM_IC_SELECTION(sConfig- & gt; IC2Selection));
assert_param(IS_TIM_IC_POLARITY(sConfig- & gt; IC1Polarity));
assert_param(IS_TIM_IC_POLARITY(sConfig- & gt; IC2Polarity));
assert_param(IS_TIM_IC_PRESCALER(sConfig- & gt; IC1Prescaler));
assert_param(IS_TIM_IC_PRESCALER(sConfig- & gt; IC2Prescaler));
assert_param(IS_TIM_IC_FILTER(sConfig- & gt; IC1Filter));
assert_param(IS_TIM_IC_FILTER(sConfig- & gt; IC2Filter));
if(htim- & gt; State == HAL_TIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
htim- & gt; Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_Encoder_MspInit(htim);
}
/* Set the TIM state */
htim- & gt; State= HAL_TIM_STATE_BUSY;
/* Reset the SMS bits */
htim- & gt; Instance- & gt; SMCR & = ~TIM_SMCR_SMS;
/* Configure the Time base in the Encoder Mode */
TIM_Base_SetConfig(htim- & gt; Instance, & htim- & gt; Init);
/* Get the TIMx SMCR register value */
tmpsmcr = htim- & gt; Instance- & gt; SMCR;
/* Get the TIMx CCMR1 register value */
tmpccmr1 = htim- & gt; Instance- & gt; CCMR1;
/* Get the TIMx CCER register value */
tmpccer = htim- & gt; Instance- & gt; CCER;
/* Set the encoder Mode */
tmpsmcr |= sConfig- & gt; EncoderMode;
/* Select the Capture Compare 1 and the Capture Compare 2 as input */
tmpccmr1 & = ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
tmpccmr1 |= (sConfig- & gt; IC1Selection | (sConfig- & gt; IC2Selection & lt; & lt; 8U));
/* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
tmpccmr1 & = ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
tmpccmr1 & = ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
tmpccmr1 |= sConfig- & gt; IC1Prescaler | (sConfig- & gt; IC2Prescaler & lt; & lt; 8U);
tmpccmr1 |= (sConfig- & gt; IC1Filter & lt; & lt; 4U) | (sConfig- & gt; IC2Filter & lt; & lt; 12U);
/* Set the TI1 and the TI2 Polarities */
tmpccer & = ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
tmpccer & = ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
tmpccer |= sConfig- & gt; IC1Polarity | (sConfig- & gt; IC2Polarity & lt; & lt; 4U);
/* Write to TIMx SMCR */
htim- & gt; Instance- & gt; SMCR = tmpsmcr;
/* Write to TIMx CCMR1 */
htim- & gt; Instance- & gt; CCMR1 = tmpccmr1;
/* Write to TIMx CCER */
htim- & gt; Instance- & gt; CCER = tmpccer;
/* Initialize the TIM state*/
htim- & gt; State= HAL_TIM_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitializes the TIM Encoder interface
* @param htim : TIM Encoder handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim- & gt; Instance));
htim- & gt; State = HAL_TIM_STATE_BUSY;
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_TIM_Encoder_MspDeInit(htim);
/* Change TIM state */
htim- & gt; State = HAL_TIM_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(htim);
return HAL_OK;
}
/**
* @brief Initializes the TIM Encoder Interface MSP.
* @param htim : TIM handle
* @retval None
*/
__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_Encoder_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes TIM Encoder Interface MSP.
* @param htim : TIM handle
* @retval None
*/
__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
*/
}
/**
* @brief Starts the TIM Encoder Interface.
* @param htim : TIM Encoder Interface handle
* @param Channel : TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim- & gt; Instance));
/* Enable the encoder interface channels */
switch (Channel)
{
case TIM_CHANNEL_1:
{
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
break;
}
case TIM_CHANNEL_2:
{
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
break;
}
default :
{
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
break;
}
}
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Stops the TIM Encoder Interface.
* @param htim : TIM Encoder Interface handle
* @param Channel : TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim- & gt; Instance));
/* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
switch (Channel)
{
case TIM_CHANNEL_1:
{
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
break;
}
case TIM_CHANNEL_2:
{
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
break;
}
default :
{
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
break;
}
}
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Starts the TIM Encoder Interface in interrupt mode.
* @param htim : TIM Encoder Interface handle
* @param Channel : TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim- & gt; Instance));
/* Enable the encoder interface channels */
/* Enable the capture compare Interrupts 1 and/or 2 */
switch (Channel)
{
case TIM_CHANNEL_1:
{
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
break;
}
case TIM_CHANNEL_2:
{
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
break;
}
default :
{
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
break;
}
}
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Stops the TIM Encoder Interface in interrupt mode.
* @param htim : TIM Encoder Interface handle
* @param Channel : TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim- & gt; Instance));
/* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
if(Channel == TIM_CHANNEL_1)
{
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
/* Disable the capture compare Interrupts 1 */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
}
else if(Channel == TIM_CHANNEL_2)
{
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
/* Disable the capture compare Interrupts 2 */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
}
else
{
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
/* Disable the capture compare Interrupts 1 and 2 */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
}
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Change the htim state */
htim- & gt; State = HAL_TIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Starts the TIM Encoder Interface in DMA mode.
* @param htim : TIM Encoder Interface handle
* @param Channel : TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @param pData1 : The destination Buffer address for IC1.
* @param pData2 : The destination Buffer address for IC2.
* @param Length : The length of data to be transferred from TIM peripheral to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
{
/* Check the parameters */
assert_param(IS_TIM_DMA_CC_INSTANCE(htim- & gt; Instance));
if((htim- & gt; State == HAL_TIM_STATE_BUSY))
{
return HAL_BUSY;
}
else if((htim- & gt; State == HAL_TIM_STATE_READY))
{
if((((pData1 == 0U) || (pData2 == 0U) )) & & (Length & gt; 0U))
{
return HAL_ERROR;
}
else
{
htim- & gt; State = HAL_TIM_STATE_BUSY;
}
}
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_CC1]- & gt; XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_CC1]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_CC1], (uint32_t) & htim- & gt; Instance- & gt; CCR1, (uint32_t )pData1, Length);
/* Enable the TIM Input Capture DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
}
break;
case TIM_CHANNEL_2:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_CC2]- & gt; XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_CC2]- & gt; XferErrorCallback = TIM_DMAError;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_CC2], (uint32_t) & htim- & gt; Instance- & gt; CCR2, (uint32_t)pData2, Length);
/* Enable the TIM Input Capture DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
}
break;
case TIM_CHANNEL_ALL:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_CC1]- & gt; XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_CC1]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_CC1], (uint32_t) & htim- & gt; Instance- & gt; CCR1, (uint32_t)pData1, Length);
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_CC2]- & gt; XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_CC2]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_CC2], (uint32_t) & htim- & gt; Instance- & gt; CCR2, (uint32_t)pData2, Length);
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
/* Enable the TIM Input Capture DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
/* Enable the TIM Input Capture DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
}
break;
default:
break;
}
/* Return function status */
return HAL_OK;
}
/**
* @brief Stops the TIM Encoder Interface in DMA mode.
* @param htim : TIM Encoder Interface handle
* @param Channel : TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_DMA_CC_INSTANCE(htim- & gt; Instance));
/* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
if(Channel == TIM_CHANNEL_1)
{
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
/* Disable the capture compare DMA Request 1 */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
}
else if(Channel == TIM_CHANNEL_2)
{
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
/* Disable the capture compare DMA Request 2 */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
}
else
{
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
/* Disable the capture compare DMA Request 1 and 2 */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
}
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Change the htim state */
htim- & gt; State = HAL_TIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
* @brief IRQ handler management
*
@verbatim
==============================================================================
##### IRQ handler management #####
==============================================================================
[..]
This section provides Timer IRQ handler function.
@endverbatim
* @{
*/
/**
* @brief This function handles TIM interrupts requests.
* @param htim : TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
/* Capture compare 1 event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
{
if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
{
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
htim- & gt; Channel = HAL_TIM_ACTIVE_CHANNEL_1;
/* Input capture event */
if((htim- & gt; Instance- & gt; CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
{
HAL_TIM_IC_CaptureCallback(htim);
}
/* Output compare event */
else
{
HAL_TIM_OC_DelayElapsedCallback(htim);
HAL_TIM_PWM_PulseFinishedCallback(htim);
}
htim- & gt; Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
}
}
/* Capture compare 2 event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
{
if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
htim- & gt; Channel = HAL_TIM_ACTIVE_CHANNEL_2;
/* Input capture event */
if((htim- & gt; Instance- & gt; CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
{
HAL_TIM_IC_CaptureCallback(htim);
}
/* Output compare event */
else
{
HAL_TIM_OC_DelayElapsedCallback(htim);
HAL_TIM_PWM_PulseFinishedCallback(htim);
}
htim- & gt; Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
}
/* Capture compare 3 event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
{
if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
htim- & gt; Channel = HAL_TIM_ACTIVE_CHANNEL_3;
/* Input capture event */
if((htim- & gt; Instance- & gt; CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
{
HAL_TIM_IC_CaptureCallback(htim);
}
/* Output compare event */
else
{
HAL_TIM_OC_DelayElapsedCallback(htim);
HAL_TIM_PWM_PulseFinishedCallback(htim);
}
htim- & gt; Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
}
/* Capture compare 4 event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
{
if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
htim- & gt; Channel = HAL_TIM_ACTIVE_CHANNEL_4;
/* Input capture event */
if((htim- & gt; Instance- & gt; CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
{
HAL_TIM_IC_CaptureCallback(htim);
}
/* Output compare event */
else
{
HAL_TIM_OC_DelayElapsedCallback(htim);
HAL_TIM_PWM_PulseFinishedCallback(htim);
}
htim- & gt; Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
}
/* TIM Update event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
{
if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
HAL_TIM_PeriodElapsedCallback(htim);
}
}
/* TIM Break input event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
{
if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
HAL_TIMEx_BreakCallback(htim);
}
}
/* TIM Trigger detection event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
{
if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
HAL_TIM_TriggerCallback(htim);
}
}
/* TIM commutation event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
{
if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
HAL_TIMEx_CommutationCallback(htim);
}
}
}
/**
* @}
*/
/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
(+) Configure External Clock source.
(+) Configure Complementary channels, break features and dead time.
(+) Configure Master and the Slave synchronization.
(+) Configure the DMA Burst Mode.
@endverbatim
* @{
*/
/**
* @brief Initializes the TIM Output Compare Channels according to the specified
* parameters in the TIM_OC_InitTypeDef.
* @param htim : TIM Output Compare handle
* @param sConfig : TIM Output Compare configuration structure
* @param Channel : TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CHANNELS(Channel));
assert_param(IS_TIM_OC_MODE(sConfig- & gt; OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig- & gt; OCPolarity));
/* Check input state */
__HAL_LOCK(htim);
htim- & gt; State = HAL_TIM_STATE_BUSY;
switch (Channel)
{
case TIM_CHANNEL_1:
{
assert_param(IS_TIM_CC1_INSTANCE(htim- & gt; Instance));
/* Configure the TIM Channel 1 in Output Compare */
TIM_OC1_SetConfig(htim- & gt; Instance, sConfig);
}
break;
case TIM_CHANNEL_2:
{
assert_param(IS_TIM_CC2_INSTANCE(htim- & gt; Instance));
/* Configure the TIM Channel 2 in Output Compare */
TIM_OC2_SetConfig(htim- & gt; Instance, sConfig);
}
break;
case TIM_CHANNEL_3:
{
assert_param(IS_TIM_CC3_INSTANCE(htim- & gt; Instance));
/* Configure the TIM Channel 3 in Output Compare */
TIM_OC3_SetConfig(htim- & gt; Instance, sConfig);
}
break;
case TIM_CHANNEL_4:
{
assert_param(IS_TIM_CC4_INSTANCE(htim- & gt; Instance));
/* Configure the TIM Channel 4 in Output Compare */
TIM_OC4_SetConfig(htim- & gt; Instance, sConfig);
}
break;
default:
break;
}
htim- & gt; State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
return HAL_OK;
}
/**
* @brief Initializes the TIM Input Capture Channels according to the specified
* parameters in the TIM_IC_InitTypeDef.
* @param htim : TIM IC handle
* @param sConfig : TIM Input Capture configuration structure
* @param Channel : TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim- & gt; Instance));
assert_param(IS_TIM_IC_POLARITY(sConfig- & gt; ICPolarity));
assert_param(IS_TIM_IC_SELECTION(sConfig- & gt; ICSelection));
assert_param(IS_TIM_IC_PRESCALER(sConfig- & gt; ICPrescaler));
assert_param(IS_TIM_IC_FILTER(sConfig- & gt; ICFilter));
__HAL_LOCK(htim);
htim- & gt; State = HAL_TIM_STATE_BUSY;
if (Channel == TIM_CHANNEL_1)
{
/* TI1 Configuration */
TIM_TI1_SetConfig(htim- & gt; Instance,
sConfig- & gt; ICPolarity,
sConfig- & gt; ICSelection,
sConfig- & gt; ICFilter);
/* Reset the IC1PSC Bits */
htim- & gt; Instance- & gt; CCMR1 & = ~TIM_CCMR1_IC1PSC;
/* Set the IC1PSC value */
htim- & gt; Instance- & gt; CCMR1 |= sConfig- & gt; ICPrescaler;
}
else if (Channel == TIM_CHANNEL_2)
{
/* TI2 Configuration */
assert_param(IS_TIM_CC2_INSTANCE(htim- & gt; Instance));
TIM_TI2_SetConfig(htim- & gt; Instance,
sConfig- & gt; ICPolarity,
sConfig- & gt; ICSelection,
sConfig- & gt; ICFilter);
/* Reset the IC2PSC Bits */
htim- & gt; Instance- & gt; CCMR1 & = ~TIM_CCMR1_IC2PSC;
/* Set the IC2PSC value */
htim- & gt; Instance- & gt; CCMR1 |= (sConfig- & gt; ICPrescaler & lt; & lt; 8U);
}
else if (Channel == TIM_CHANNEL_3)
{
/* TI3 Configuration */
assert_param(IS_TIM_CC3_INSTANCE(htim- & gt; Instance));
TIM_TI3_SetConfig(htim- & gt; Instance,
sConfig- & gt; ICPolarity,
sConfig- & gt; ICSelection,
sConfig- & gt; ICFilter);
/* Reset the IC3PSC Bits */
htim- & gt; Instance- & gt; CCMR2 & = ~TIM_CCMR2_IC3PSC;
/* Set the IC3PSC value */
htim- & gt; Instance- & gt; CCMR2 |= sConfig- & gt; ICPrescaler;
}
else
{
/* TI4 Configuration */
assert_param(IS_TIM_CC4_INSTANCE(htim- & gt; Instance));
TIM_TI4_SetConfig(htim- & gt; Instance,
sConfig- & gt; ICPolarity,
sConfig- & gt; ICSelection,
sConfig- & gt; ICFilter);
/* Reset the IC4PSC Bits */
htim- & gt; Instance- & gt; CCMR2 & = ~TIM_CCMR2_IC4PSC;
/* Set the IC4PSC value */
htim- & gt; Instance- & gt; CCMR2 |= (sConfig- & gt; ICPrescaler & lt; & lt; 8U);
}
htim- & gt; State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
return HAL_OK;
}
/**
* @brief Initializes the TIM PWM channels according to the specified
* parameters in the TIM_OC_InitTypeDef.
* @param htim : TIM handle
* @param sConfig : TIM PWM configuration structure
* @param Channel : TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
{
__HAL_LOCK(htim);
/* Check the parameters */
assert_param(IS_TIM_CHANNELS(Channel));
assert_param(IS_TIM_PWM_MODE(sConfig- & gt; OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig- & gt; OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig- & gt; OCFastMode));
htim- & gt; State = HAL_TIM_STATE_BUSY;
switch (Channel)
{
case TIM_CHANNEL_1:
{
assert_param(IS_TIM_CC1_INSTANCE(htim- & gt; Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim- & gt; Instance, sConfig);
/* Set the Preload enable bit for channel1 */
htim- & gt; Instance- & gt; CCMR1 |= TIM_CCMR1_OC1PE;
/* Configure the Output Fast mode */
htim- & gt; Instance- & gt; CCMR1 & = ~TIM_CCMR1_OC1FE;
htim- & gt; Instance- & gt; CCMR1 |= sConfig- & gt; OCFastMode;
}
break;
case TIM_CHANNEL_2:
{
assert_param(IS_TIM_CC2_INSTANCE(htim- & gt; Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim- & gt; Instance, sConfig);
/* Set the Preload enable bit for channel2 */
htim- & gt; Instance- & gt; CCMR1 |= TIM_CCMR1_OC2PE;
/* Configure the Output Fast mode */
htim- & gt; Instance- & gt; CCMR1 & = ~TIM_CCMR1_OC2FE;
htim- & gt; Instance- & gt; CCMR1 |= sConfig- & gt; OCFastMode & lt; & lt; 8;
}
break;
case TIM_CHANNEL_3:
{
assert_param(IS_TIM_CC3_INSTANCE(htim- & gt; Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim- & gt; Instance, sConfig);
/* Set the Preload enable bit for channel3 */
htim- & gt; Instance- & gt; CCMR2 |= TIM_CCMR2_OC3PE;
/* Configure the Output Fast mode */
htim- & gt; Instance- & gt; CCMR2 & = ~TIM_CCMR2_OC3FE;
htim- & gt; Instance- & gt; CCMR2 |= sConfig- & gt; OCFastMode;
}
break;
case TIM_CHANNEL_4:
{
assert_param(IS_TIM_CC4_INSTANCE(htim- & gt; Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim- & gt; Instance, sConfig);
/* Set the Preload enable bit for channel4 */
htim- & gt; Instance- & gt; CCMR2 |= TIM_CCMR2_OC4PE;
/* Configure the Output Fast mode */
htim- & gt; Instance- & gt; CCMR2 & = ~TIM_CCMR2_OC4FE;
htim- & gt; Instance- & gt; CCMR2 |= sConfig- & gt; OCFastMode & lt; & lt; 8;
}
break;
default:
break;
}
htim- & gt; State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
return HAL_OK;
}
/**
* @brief Initializes the TIM One Pulse Channels according to the specified
* parameters in the TIM_OnePulse_InitTypeDef.
* @param htim : TIM One Pulse handle
* @param sConfig : TIM One Pulse configuration structure
* @param OutputChannel : TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @param InputChannel : TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
{
TIM_OC_InitTypeDef temp1;
/* Check the parameters */
assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
if(OutputChannel != InputChannel)
{
__HAL_LOCK(htim);
htim- & gt; State = HAL_TIM_STATE_BUSY;
/* Extract the Ouput compare configuration from sConfig structure */
temp1.OCMode = sConfig- & gt; OCMode;
temp1.Pulse = sConfig- & gt; Pulse;
temp1.OCPolarity = sConfig- & gt; OCPolarity;
temp1.OCNPolarity = sConfig- & gt; OCNPolarity;
temp1.OCIdleState = sConfig- & gt; OCIdleState;
temp1.OCNIdleState = sConfig- & gt; OCNIdleState;
switch (OutputChannel)
{
case TIM_CHANNEL_1:
{
assert_param(IS_TIM_CC1_INSTANCE(htim- & gt; Instance));
TIM_OC1_SetConfig(htim- & gt; Instance, & temp1);
}
break;
case TIM_CHANNEL_2:
{
assert_param(IS_TIM_CC2_INSTANCE(htim- & gt; Instance));
TIM_OC2_SetConfig(htim- & gt; Instance, & temp1);
}
break;
default:
break;
}
switch (InputChannel)
{
case TIM_CHANNEL_1:
{
assert_param(IS_TIM_CC1_INSTANCE(htim- & gt; Instance));
TIM_TI1_SetConfig(htim- & gt; Instance, sConfig- & gt; ICPolarity,
sConfig- & gt; ICSelection, sConfig- & gt; ICFilter);
/* Reset the IC1PSC Bits */
htim- & gt; Instance- & gt; CCMR1 & = ~TIM_CCMR1_IC1PSC;
/* Select the Trigger source */
htim- & gt; Instance- & gt; SMCR & = ~TIM_SMCR_TS;
htim- & gt; Instance- & gt; SMCR |= TIM_TS_TI1FP1;
/* Select the Slave Mode */
htim- & gt; Instance- & gt; SMCR & = ~TIM_SMCR_SMS;
htim- & gt; Instance- & gt; SMCR |= TIM_SLAVEMODE_TRIGGER;
}
break;
case TIM_CHANNEL_2:
{
assert_param(IS_TIM_CC2_INSTANCE(htim- & gt; Instance));
TIM_TI2_SetConfig(htim- & gt; Instance, sConfig- & gt; ICPolarity,
sConfig- & gt; ICSelection, sConfig- & gt; ICFilter);
/* Reset the IC2PSC Bits */
htim- & gt; Instance- & gt; CCMR1 & = ~TIM_CCMR1_IC2PSC;
/* Select the Trigger source */
htim- & gt; Instance- & gt; SMCR & = ~TIM_SMCR_TS;
htim- & gt; Instance- & gt; SMCR |= TIM_TS_TI2FP2;
/* Select the Slave Mode */
htim- & gt; Instance- & gt; SMCR & = ~TIM_SMCR_SMS;
htim- & gt; Instance- & gt; SMCR |= TIM_SLAVEMODE_TRIGGER;
}
break;
default:
break;
}
htim- & gt; State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
* @param htim : TIM handle
* @param BurstBaseAddress : TIM Base address from where the DMA will start the Data write
* This parameter can be one of the following values:
* @arg TIM_DMABASE_CR1
* @arg TIM_DMABASE_CR2
* @arg TIM_DMABASE_SMCR
* @arg TIM_DMABASE_DIER
* @arg TIM_DMABASE_SR
* @arg TIM_DMABASE_EGR
* @arg TIM_DMABASE_CCMR1
* @arg TIM_DMABASE_CCMR2
* @arg TIM_DMABASE_CCER
* @arg TIM_DMABASE_CNT
* @arg TIM_DMABASE_PSC
* @arg TIM_DMABASE_ARR
* @arg TIM_DMABASE_RCR
* @arg TIM_DMABASE_CCR1
* @arg TIM_DMABASE_CCR2
* @arg TIM_DMABASE_CCR3
* @arg TIM_DMABASE_CCR4
* @arg TIM_DMABASE_BDTR
* @arg TIM_DMABASE_DCR
* @param BurstRequestSrc : TIM DMA Request sources
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
* @arg TIM_DMA_COM: TIM Commutation DMA source
* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
* @param BurstBuffer : The Buffer address.
* @param BurstLength : DMA Burst length. This parameter can be one value
* between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
uint32_t* BurstBuffer, uint32_t BurstLength)
{
/* Check the parameters */
assert_param(IS_TIM_DMABURST_INSTANCE(htim- & gt; Instance));
assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
if((htim- & gt; State == HAL_TIM_STATE_BUSY))
{
return HAL_BUSY;
}
else if((htim- & gt; State == HAL_TIM_STATE_READY))
{
if((BurstBuffer == 0U) & & (BurstLength & gt; 0U))
{
return HAL_ERROR;
}
else
{
htim- & gt; State = HAL_TIM_STATE_BUSY;
}
}
switch(BurstRequestSrc)
{
case TIM_DMA_UPDATE:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_UPDATE]- & gt; XferCpltCallback = TIM_DMAPeriodElapsedCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_UPDATE]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t) & htim- & gt; Instance- & gt; DMAR, ((BurstLength) & gt; & gt; 8U) + 1U);
}
break;
case TIM_DMA_CC1:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_CC1]- & gt; XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_CC1]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t) & htim- & gt; Instance- & gt; DMAR, ((BurstLength) & gt; & gt; 8U) + 1U);
}
break;
case TIM_DMA_CC2:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_CC2]- & gt; XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_CC2]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t) & htim- & gt; Instance- & gt; DMAR, ((BurstLength) & gt; & gt; 8U) + 1U);
}
break;
case TIM_DMA_CC3:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_CC3]- & gt; XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_CC3]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t) & htim- & gt; Instance- & gt; DMAR, ((BurstLength) & gt; & gt; 8U) + 1U);
}
break;
case TIM_DMA_CC4:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_CC4]- & gt; XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_CC4]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t) & htim- & gt; Instance- & gt; DMAR, ((BurstLength) & gt; & gt; 8U) + 1U);
}
break;
case TIM_DMA_COM:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_COMMUTATION]- & gt; XferCpltCallback = TIMEx_DMACommutationCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_COMMUTATION]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t) & htim- & gt; Instance- & gt; DMAR, ((BurstLength) & gt; & gt; 8U) + 1U);
}
break;
case TIM_DMA_TRIGGER:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_TRIGGER]- & gt; XferCpltCallback = TIM_DMATriggerCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_TRIGGER]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t) & htim- & gt; Instance- & gt; DMAR, ((BurstLength) & gt; & gt; 8U) + 1U);
}
break;
default:
break;
}
/* configure the DMA Burst Mode */
htim- & gt; Instance- & gt; DCR = BurstBaseAddress | BurstLength;
/* Enable the TIM DMA Request */
__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
htim- & gt; State = HAL_TIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Stops the TIM DMA Burst mode
* @param htim : TIM handle
* @param BurstRequestSrc : TIM DMA Request sources to disable
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
{
/* Check the parameters */
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
/* Abort the DMA transfer (at least disable the DMA channel) */
switch(BurstRequestSrc)
{
case TIM_DMA_UPDATE:
{
HAL_DMA_Abort(htim- & gt; hdma[TIM_DMA_ID_UPDATE]);
}
break;
case TIM_DMA_CC1:
{
HAL_DMA_Abort(htim- & gt; hdma[TIM_DMA_ID_CC1]);
}
break;
case TIM_DMA_CC2:
{
HAL_DMA_Abort(htim- & gt; hdma[TIM_DMA_ID_CC2]);
}
break;
case TIM_DMA_CC3:
{
HAL_DMA_Abort(htim- & gt; hdma[TIM_DMA_ID_CC3]);
}
break;
case TIM_DMA_CC4:
{
HAL_DMA_Abort(htim- & gt; hdma[TIM_DMA_ID_CC4]);
}
break;
case TIM_DMA_COM:
{
HAL_DMA_Abort(htim- & gt; hdma[TIM_DMA_ID_COMMUTATION]);
}
break;
case TIM_DMA_TRIGGER:
{
HAL_DMA_Abort(htim- & gt; hdma[TIM_DMA_ID_TRIGGER]);
}
break;
default:
break;
}
/* Disable the TIM Update DMA request */
__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
/* Return function status */
return HAL_OK;
}
/**
* @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
* @param htim : TIM handle
* @param BurstBaseAddress : TIM Base address from where the DMA will starts the Data read
* This parameter can be one of the following values:
* @arg TIM_DMABASE_CR1
* @arg TIM_DMABASE_CR2
* @arg TIM_DMABASE_SMCR
* @arg TIM_DMABASE_DIER
* @arg TIM_DMABASE_SR
* @arg TIM_DMABASE_EGR
* @arg TIM_DMABASE_CCMR1
* @arg TIM_DMABASE_CCMR2
* @arg TIM_DMABASE_CCER
* @arg TIM_DMABASE_CNT
* @arg TIM_DMABASE_PSC
* @arg TIM_DMABASE_ARR
* @arg TIM_DMABASE_RCR
* @arg TIM_DMABASE_CCR1
* @arg TIM_DMABASE_CCR2
* @arg TIM_DMABASE_CCR3
* @arg TIM_DMABASE_CCR4
* @arg TIM_DMABASE_BDTR
* @arg TIM_DMABASE_DCR
* @param BurstRequestSrc : TIM DMA Request sources
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
* @arg TIM_DMA_COM: TIM Commutation DMA source
* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
* @param BurstBuffer : The Buffer address.
* @param BurstLength : DMA Burst length. This parameter can be one value
* between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
uint32_t *BurstBuffer, uint32_t BurstLength)
{
/* Check the parameters */
assert_param(IS_TIM_DMABURST_INSTANCE(htim- & gt; Instance));
assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
if((htim- & gt; State == HAL_TIM_STATE_BUSY))
{
return HAL_BUSY;
}
else if((htim- & gt; State == HAL_TIM_STATE_READY))
{
if((BurstBuffer == 0U) & & (BurstLength & gt; 0U))
{
return HAL_ERROR;
}
else
{
htim- & gt; State = HAL_TIM_STATE_BUSY;
}
}
switch(BurstRequestSrc)
{
case TIM_DMA_UPDATE:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_UPDATE]- & gt; XferCpltCallback = TIM_DMAPeriodElapsedCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_UPDATE]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_UPDATE], (uint32_t) & htim- & gt; Instance- & gt; DMAR, (uint32_t)BurstBuffer, ((BurstLength) & gt; & gt; 8U) + 1U);
}
break;
case TIM_DMA_CC1:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_CC1]- & gt; XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_CC1]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_CC1], (uint32_t) & htim- & gt; Instance- & gt; DMAR, (uint32_t)BurstBuffer, ((BurstLength) & gt; & gt; 8U) + 1U);
}
break;
case TIM_DMA_CC2:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_CC2]- & gt; XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_CC2]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_CC2], (uint32_t) & htim- & gt; Instance- & gt; DMAR, (uint32_t)BurstBuffer, ((BurstLength) & gt; & gt; 8U) + 1U);
}
break;
case TIM_DMA_CC3:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_CC3]- & gt; XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_CC3]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_CC3], (uint32_t) & htim- & gt; Instance- & gt; DMAR, (uint32_t)BurstBuffer, ((BurstLength) & gt; & gt; 8U) + 1U);
}
break;
case TIM_DMA_CC4:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_CC4]- & gt; XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_CC4]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_CC4], (uint32_t) & htim- & gt; Instance- & gt; DMAR, (uint32_t)BurstBuffer, ((BurstLength) & gt; & gt; 8U) + 1U);
}
break;
case TIM_DMA_COM:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_COMMUTATION]- & gt; XferCpltCallback = TIMEx_DMACommutationCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_COMMUTATION]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_COMMUTATION], (uint32_t) & htim- & gt; Instance- & gt; DMAR, (uint32_t)BurstBuffer, ((BurstLength) & gt; & gt; 8U) + 1U);
}
break;
case TIM_DMA_TRIGGER:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_TRIGGER]- & gt; XferCpltCallback = TIM_DMATriggerCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_TRIGGER]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_TRIGGER], (uint32_t) & htim- & gt; Instance- & gt; DMAR, (uint32_t)BurstBuffer, ((BurstLength) & gt; & gt; 8U) + 1U);
}
break;
default:
break;
}
/* configure the DMA Burst Mode */
htim- & gt; Instance- & gt; DCR = BurstBaseAddress | BurstLength;
/* Enable the TIM DMA Request */
__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
htim- & gt; State = HAL_TIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Stop the DMA burst reading
* @param htim : TIM handle
* @param BurstRequestSrc : TIM DMA Request sources to disable.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
{
/* Check the parameters */
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
/* Abort the DMA transfer (at least disable the DMA channel) */
switch(BurstRequestSrc)
{
case TIM_DMA_UPDATE:
{
HAL_DMA_Abort(htim- & gt; hdma[TIM_DMA_ID_UPDATE]);
}
break;
case TIM_DMA_CC1:
{
HAL_DMA_Abort(htim- & gt; hdma[TIM_DMA_ID_CC1]);
}
break;
case TIM_DMA_CC2:
{
HAL_DMA_Abort(htim- & gt; hdma[TIM_DMA_ID_CC2]);
}
break;
case TIM_DMA_CC3:
{
HAL_DMA_Abort(htim- & gt; hdma[TIM_DMA_ID_CC3]);
}
break;
case TIM_DMA_CC4:
{
HAL_DMA_Abort(htim- & gt; hdma[TIM_DMA_ID_CC4]);
}
break;
case TIM_DMA_COM:
{
HAL_DMA_Abort(htim- & gt; hdma[TIM_DMA_ID_COMMUTATION]);
}
break;
case TIM_DMA_TRIGGER:
{
HAL_DMA_Abort(htim- & gt; hdma[TIM_DMA_ID_TRIGGER]);
}
break;
default:
break;
}
/* Disable the TIM Update DMA request */
__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
/* Return function status */
return HAL_OK;
}
/**
* @brief Generate a software event
* @param htim : TIM handle
* @param EventSource : specifies the event source.
* This parameter can be one of the following values:
* @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
* @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
* @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
* @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
* @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
* @arg TIM_EVENTSOURCE_COM: Timer COM event source
* @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
* @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
* @note TIM6 and TIM7 can only generate an update event.
* @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1, TIM15, TIM16 and TIM17.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim- & gt; Instance));
assert_param(IS_TIM_EVENT_SOURCE(EventSource));
/* Process Locked */
__HAL_LOCK(htim);
/* Change the TIM state */
htim- & gt; State = HAL_TIM_STATE_BUSY;
/* Set the event sources */
htim- & gt; Instance- & gt; EGR = EventSource;
/* Change the TIM state */
htim- & gt; State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Configures the OCRef clear feature
* @param htim : TIM handle
* @param sClearInputConfig : pointer to a TIM_ClearInputConfigTypeDef structure that
* contains the OCREF clear feature and parameters for the TIM peripheral.
* @param Channel : specifies the TIM Channel
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1
* @arg TIM_CHANNEL_2: TIM Channel 2
* @arg TIM_CHANNEL_3: TIM Channel 3
* @arg TIM_CHANNEL_4: TIM Channel 4
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
{
uint32_t tmpsmcr = 0U;
/* Check the parameters */
assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim- & gt; Instance));
assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig- & gt; ClearInputSource));
assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig- & gt; ClearInputPolarity));
assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig- & gt; ClearInputPrescaler));
assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig- & gt; ClearInputFilter));
/* Process Locked */
__HAL_LOCK(htim);
htim- & gt; State = HAL_TIM_STATE_BUSY;
switch (sClearInputConfig- & gt; ClearInputSource)
{
case TIM_CLEARINPUTSOURCE_NONE:
{
/* Clear the ETR Bits */
tmpsmcr & = ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
/* Set TIMx_SMCR */
htim- & gt; Instance- & gt; SMCR = tmpsmcr;
}
break;
case TIM_CLEARINPUTSOURCE_ETR:
{
TIM_ETR_SetConfig(htim- & gt; Instance,
sClearInputConfig- & gt; ClearInputPrescaler,
sClearInputConfig- & gt; ClearInputPolarity,
sClearInputConfig- & gt; ClearInputFilter);
}
break;
default:
break;
}
switch (Channel)
{
case TIM_CHANNEL_1:
{
if(sClearInputConfig- & gt; ClearInputState != RESET)
{
/* Enable the Ocref clear feature for Channel 1 */
htim- & gt; Instance- & gt; CCMR1 |= TIM_CCMR1_OC1CE;
}
else
{
/* Disable the Ocref clear feature for Channel 1 */
htim- & gt; Instance- & gt; CCMR1 & = ~TIM_CCMR1_OC1CE;
}
}
break;
case TIM_CHANNEL_2:
{
assert_param(IS_TIM_CC2_INSTANCE(htim- & gt; Instance));
if(sClearInputConfig- & gt; ClearInputState != RESET)
{
/* Enable the Ocref clear feature for Channel 2 */
htim- & gt; Instance- & gt; CCMR1 |= TIM_CCMR1_OC2CE;
}
else
{
/* Disable the Ocref clear feature for Channel 2 */
htim- & gt; Instance- & gt; CCMR1 & = ~TIM_CCMR1_OC2CE;
}
}
break;
case TIM_CHANNEL_3:
{
assert_param(IS_TIM_CC3_INSTANCE(htim- & gt; Instance));
if(sClearInputConfig- & gt; ClearInputState != RESET)
{
/* Enable the Ocref clear feature for Channel 3 */
htim- & gt; Instance- & gt; CCMR2 |= TIM_CCMR2_OC3CE;
}
else
{
/* Disable the Ocref clear feature for Channel 3 */
htim- & gt; Instance- & gt; CCMR2 & = ~TIM_CCMR2_OC3CE;
}
}
break;
case TIM_CHANNEL_4:
{
assert_param(IS_TIM_CC4_INSTANCE(htim- & gt; Instance));
if(sClearInputConfig- & gt; ClearInputState != RESET)
{
/* Enable the Ocref clear feature for Channel 4 */
htim- & gt; Instance- & gt; CCMR2 |= TIM_CCMR2_OC4CE;
}
else
{
/* Disable the Ocref clear feature for Channel 4 */
htim- & gt; Instance- & gt; CCMR2 & = ~TIM_CCMR2_OC4CE;
}
}
break;
default:
break;
}
htim- & gt; State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
return HAL_OK;
}
/**
* @brief Configures the clock source to be used
* @param htim : TIM handle
* @param sClockSourceConfig : pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
{
uint32_t tmpsmcr = 0U;
/* Process Locked */
__HAL_LOCK(htim);
htim- & gt; State = HAL_TIM_STATE_BUSY;
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig- & gt; ClockSource));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim- & gt; Instance- & gt; SMCR;
tmpsmcr & = ~(TIM_SMCR_SMS | TIM_SMCR_TS);
tmpsmcr & = ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
htim- & gt; Instance- & gt; SMCR = tmpsmcr;
switch (sClockSourceConfig- & gt; ClockSource)
{
case TIM_CLOCKSOURCE_INTERNAL:
{
assert_param(IS_TIM_INSTANCE(htim- & gt; Instance));
/* Disable slave mode to clock the prescaler directly with the internal clock */
htim- & gt; Instance- & gt; SMCR & = ~TIM_SMCR_SMS;
}
break;
case TIM_CLOCKSOURCE_ETRMODE1:
{
/* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim- & gt; Instance));
/* Check ETR input conditioning related parameters */
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig- & gt; ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig- & gt; ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig- & gt; ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim- & gt; Instance,
sClockSourceConfig- & gt; ClockPrescaler,
sClockSourceConfig- & gt; ClockPolarity,
sClockSourceConfig- & gt; ClockFilter);
/* Get the TIMx SMCR register value */
tmpsmcr = htim- & gt; Instance- & gt; SMCR;
/* Reset the SMS and TS Bits */
tmpsmcr & = ~(TIM_SMCR_SMS | TIM_SMCR_TS);
/* Select the External clock mode1 and the ETRF trigger */
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
/* Write to TIMx SMCR */
htim- & gt; Instance- & gt; SMCR = tmpsmcr;
}
break;
case TIM_CLOCKSOURCE_ETRMODE2:
{
/* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim- & gt; Instance));
/* Check ETR input conditioning related parameters */
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig- & gt; ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig- & gt; ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig- & gt; ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim- & gt; Instance,
sClockSourceConfig- & gt; ClockPrescaler,
sClockSourceConfig- & gt; ClockPolarity,
sClockSourceConfig- & gt; ClockFilter);
/* Enable the External clock mode2 */
htim- & gt; Instance- & gt; SMCR |= TIM_SMCR_ECE;
}
break;
case TIM_CLOCKSOURCE_TI1:
{
/* Check whether or not the timer instance supports external clock mode 1 */
assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim- & gt; Instance));
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig- & gt; ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig- & gt; ClockFilter));
TIM_TI1_ConfigInputStage(htim- & gt; Instance,
sClockSourceConfig- & gt; ClockPolarity,
sClockSourceConfig- & gt; ClockFilter);
TIM_ITRx_SetConfig(htim- & gt; Instance, TIM_CLOCKSOURCE_TI1);
}
break;
case TIM_CLOCKSOURCE_TI2:
{
/* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim- & gt; Instance));
/* Check TI2 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig- & gt; ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig- & gt; ClockFilter));
TIM_TI2_ConfigInputStage(htim- & gt; Instance,
sClockSourceConfig- & gt; ClockPolarity,
sClockSourceConfig- & gt; ClockFilter);
TIM_ITRx_SetConfig(htim- & gt; Instance, TIM_CLOCKSOURCE_TI2);
}
break;
case TIM_CLOCKSOURCE_TI1ED:
{
/* Check whether or not the timer instance supports external clock mode 1 */
assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim- & gt; Instance));
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig- & gt; ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig- & gt; ClockFilter));
TIM_TI1_ConfigInputStage(htim- & gt; Instance,
sClockSourceConfig- & gt; ClockPolarity,
sClockSourceConfig- & gt; ClockFilter);
TIM_ITRx_SetConfig(htim- & gt; Instance, TIM_CLOCKSOURCE_TI1ED);
}
break;
case TIM_CLOCKSOURCE_ITR0:
{
/* Check whether or not the timer instance supports external clock mode 1 */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim- & gt; Instance));
TIM_ITRx_SetConfig(htim- & gt; Instance, TIM_CLOCKSOURCE_ITR0);
}
break;
case TIM_CLOCKSOURCE_ITR1:
{
/* Check whether or not the timer instance supports external clock mode 1 */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim- & gt; Instance));
TIM_ITRx_SetConfig(htim- & gt; Instance, TIM_CLOCKSOURCE_ITR1);
}
break;
case TIM_CLOCKSOURCE_ITR2:
{
/* Check whether or not the timer instance supports external clock mode 1 */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim- & gt; Instance));
TIM_ITRx_SetConfig(htim- & gt; Instance, TIM_CLOCKSOURCE_ITR2);
}
break;
case TIM_CLOCKSOURCE_ITR3:
{
/* Check whether or not the timer instance supports external clock mode 1 */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim- & gt; Instance));
TIM_ITRx_SetConfig(htim- & gt; Instance, TIM_CLOCKSOURCE_ITR3);
}
break;
default:
break;
}
htim- & gt; State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
return HAL_OK;
}
/**
* @brief Selects the signal connected to the TI1 input: direct from CH1_input
* or a XOR combination between CH1_input, CH2_input & CH3_input
* @param htim : TIM handle.
* @param TI1_Selection : Indicate whether or not channel 1 is connected to the
* output of a XOR gate.
* This parameter can be one of the following values:
* @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
* @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
* pins are connected to the TI1 input (XOR combination)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
{
uint32_t tmpcr2 = 0U;
/* Check the parameters */
assert_param(IS_TIM_XOR_INSTANCE(htim- & gt; Instance));
assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
/* Get the TIMx CR2 register value */
tmpcr2 = htim- & gt; Instance- & gt; CR2;
/* Reset the TI1 selection */
tmpcr2 & = ~TIM_CR2_TI1S;
/* Set the the TI1 selection */
tmpcr2 |= TI1_Selection;
/* Write to TIMxCR2 */
htim- & gt; Instance- & gt; CR2 = tmpcr2;
return HAL_OK;
}
/**
* @brief Configures the TIM in Slave mode
* @param htim : TIM handle.
* @param sSlaveConfig : pointer to a TIM_SlaveConfigTypeDef structure that
* contains the selected trigger (internal trigger input, filtered
* timer input or external trigger input) and the ) and the Slave
* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
{
/* Check the parameters */
assert_param(IS_TIM_SLAVE_INSTANCE(htim- & gt; Instance));
assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig- & gt; SlaveMode));
assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig- & gt; InputTrigger));
__HAL_LOCK(htim);
htim- & gt; State = HAL_TIM_STATE_BUSY;
TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
/* Disable Trigger Interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
/* Disable Trigger DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
htim- & gt; State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
return HAL_OK;
}
/**
* @brief Configures the TIM in Slave mode in interrupt mode
* @param htim: TIM handle.
* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
* contains the selected trigger (internal trigger input, filtered
* timer input or external trigger input) and the ) and the Slave
* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
TIM_SlaveConfigTypeDef * sSlaveConfig)
{
/* Check the parameters */
assert_param(IS_TIM_SLAVE_INSTANCE(htim- & gt; Instance));
assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig- & gt; SlaveMode));
assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig- & gt; InputTrigger));
__HAL_LOCK(htim);
htim- & gt; State = HAL_TIM_STATE_BUSY;
TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
/* Enable Trigger Interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
/* Disable Trigger DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
htim- & gt; State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
return HAL_OK;
}
/**
* @brief Read the captured value from Capture Compare unit
* @param htim : TIM handle.
* @param Channel : TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1 : TIM Channel 1 selected
* @arg TIM_CHANNEL_2 : TIM Channel 2 selected
* @arg TIM_CHANNEL_3 : TIM Channel 3 selected
* @arg TIM_CHANNEL_4 : TIM Channel 4 selected
* @retval Captured value
*/
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
{
uint32_t tmpreg = 0U;
__HAL_LOCK(htim);
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim- & gt; Instance));
/* Return the capture 1 value */
tmpreg = htim- & gt; Instance- & gt; CCR1;
break;
}
case TIM_CHANNEL_2:
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim- & gt; Instance));
/* Return the capture 2 value */
tmpreg = htim- & gt; Instance- & gt; CCR2;
break;
}
case TIM_CHANNEL_3:
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim- & gt; Instance));
/* Return the capture 3 value */
tmpreg = htim- & gt; Instance- & gt; CCR3;
break;
}
case TIM_CHANNEL_4:
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim- & gt; Instance));
/* Return the capture 4 value */
tmpreg = htim- & gt; Instance- & gt; CCR4;
break;
}
default:
break;
}
__HAL_UNLOCK(htim);
return tmpreg;
}
/**
* @}
*/
/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
* @brief TIM Callbacks functions
*
@verbatim
==============================================================================
##### TIM Callbacks functions #####
==============================================================================
[..]
This section provides TIM callback functions:
(+) Timer Period elapsed callback
(+) Timer Output Compare callback
(+) Timer Input capture callback
(+) Timer Trigger callback
(+) Timer Error callback
@endverbatim
* @{
*/
/**
* @brief Period elapsed callback in non blocking mode
* @param htim : TIM handle
* @retval None
*/
__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
*/
}
/**
* @brief Output Compare callback in non blocking mode
* @param htim : TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
/**
* @brief Input Capture callback in non blocking mode
* @param htim : TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
/**
* @brief PWM Pulse finished callback in non blocking mode
* @param htim : TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
/**
* @brief Hall Trigger detection callback in non blocking mode
* @param htim : TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
/**
* @brief Timer error callback in non blocking mode
* @param htim : TIM handle
* @retval None
*/
__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_ErrorCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
* @brief Peripheral State functions
*
@verbatim
==============================================================================
##### Peripheral State functions #####
==============================================================================
[..]
This subsection permit to get in run-time the status of the peripheral
and the data flow.
@endverbatim
* @{
*/
/**
* @brief Return the TIM Base state
* @param htim : TIM Base handle
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
{
return htim- & gt; State;
}
/**
* @brief Return the TIM OC state
* @param htim : TIM Ouput Compare handle
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
{
return htim- & gt; State;
}
/**
* @brief Return the TIM PWM state
* @param htim : TIM handle
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
{
return htim- & gt; State;
}
/**
* @brief Return the TIM Input Capture state
* @param htim : TIM IC handle
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
{
return htim- & gt; State;
}
/**
* @brief Return the TIM One Pulse Mode state
* @param htim : TIM OPM handle
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
{
return htim- & gt; State;
}
/**
* @brief Return the TIM Encoder Mode state
* @param htim : TIM Encoder handle
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
{
return htim- & gt; State;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup TIM_Private_Functions
* @{
*/
/**
* @brief TIM DMA error callback
* @param hdma : pointer to DMA handle.
* @retval None
*/
void TIM_DMAError(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)- & gt; Parent;
htim- & gt; State= HAL_TIM_STATE_READY;
HAL_TIM_ErrorCallback(htim);
}
/**
* @brief TIM DMA Delay Pulse complete callback.
* @param hdma : pointer to DMA handle.
* @retval None
*/
void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)- & gt; Parent;
htim- & gt; State= HAL_TIM_STATE_READY;
if (hdma == htim- & gt; hdma[TIM_DMA_ID_CC1])
{
htim- & gt; Channel = HAL_TIM_ACTIVE_CHANNEL_1;
}
else if (hdma == htim- & gt; hdma[TIM_DMA_ID_CC2])
{
htim- & gt; Channel = HAL_TIM_ACTIVE_CHANNEL_2;
}
else if (hdma == htim- & gt; hdma[TIM_DMA_ID_CC3])
{
htim- & gt; Channel = HAL_TIM_ACTIVE_CHANNEL_3;
}
else if (hdma == htim- & gt; hdma[TIM_DMA_ID_CC4])
{
htim- & gt; Channel = HAL_TIM_ACTIVE_CHANNEL_4;
}
HAL_TIM_PWM_PulseFinishedCallback(htim);
htim- & gt; Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
/**
* @brief TIM DMA Capture complete callback.
* @param hdma : pointer to DMA handle.
* @retval None
*/
void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)- & gt; Parent;
htim- & gt; State= HAL_TIM_STATE_READY;
if (hdma == htim- & gt; hdma[TIM_DMA_ID_CC1])
{
htim- & gt; Channel = HAL_TIM_ACTIVE_CHANNEL_1;
}
else if (hdma == htim- & gt; hdma[TIM_DMA_ID_CC2])
{
htim- & gt; Channel = HAL_TIM_ACTIVE_CHANNEL_2;
}
else if (hdma == htim- & gt; hdma[TIM_DMA_ID_CC3])
{
htim- & gt; Channel = HAL_TIM_ACTIVE_CHANNEL_3;
}
else if (hdma == htim- & gt; hdma[TIM_DMA_ID_CC4])
{
htim- & gt; Channel = HAL_TIM_ACTIVE_CHANNEL_4;
}
HAL_TIM_IC_CaptureCallback(htim);
htim- & gt; Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
/**
* @brief TIM DMA Period Elapse complete callback.
* @param hdma : pointer to DMA handle.
* @retval None
*/
static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)- & gt; Parent;
htim- & gt; State= HAL_TIM_STATE_READY;
HAL_TIM_PeriodElapsedCallback(htim);
}
/**
* @brief TIM DMA Trigger callback.
* @param hdma : pointer to DMA handle.
* @retval None
*/
static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)- & gt; Parent;
htim- & gt; State= HAL_TIM_STATE_READY;
HAL_TIM_TriggerCallback(htim);
}
/**
* @brief Time Base configuration
* @param TIMx : TIM periheral
* @param Structure : TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
{
uint32_t tmpcr1 = 0U;
tmpcr1 = TIMx- & gt; CR1;
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
{
/* Select the Counter Mode */
tmpcr1 & = ~(TIM_CR1_DIR | TIM_CR1_CMS);
tmpcr1 |= Structure- & gt; CounterMode;
}
if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
{
/* Set the clock division */
tmpcr1 & = ~TIM_CR1_CKD;
tmpcr1 |= (uint32_t)Structure- & gt; ClockDivision;
}
/* Set the auto-reload preload */
tmpcr1 & = ~TIM_CR1_ARPE;
tmpcr1 |= (uint32_t)Structure- & gt; AutoReloadPreload;
TIMx- & gt; CR1 = tmpcr1;
/* Set the Autoreload value */
TIMx- & gt; ARR = (uint32_t)Structure- & gt; Period ;
/* Set the Prescaler value */
TIMx- & gt; PSC = (uint32_t)Structure- & gt; Prescaler;
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
{
/* Set the Repetition Counter value */
TIMx- & gt; RCR = Structure- & gt; RepetitionCounter;
}
/* Generate an update event to reload the Prescaler
and the repetition counter(only for TIM1 and TIM8) value immediatly */
TIMx- & gt; EGR = TIM_EGR_UG;
}
/**
* @brief Time Ouput Compare 1 configuration
* @param TIMx to select the TIM peripheral
* @param OC_Config : The ouput configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
uint32_t tmpccmrx = 0U;
uint32_t tmpccer = 0U;
uint32_t tmpcr2 = 0U;
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx- & gt; CCER & = ~TIM_CCER_CC1E;
/* Get the TIMx CCER register value */
tmpccer = TIMx- & gt; CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx- & gt; CR2;
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx- & gt; CCMR1;
/* Reset the Output Compare Mode Bits */
tmpccmrx & = ~TIM_CCMR1_OC1M;
tmpccmrx & = ~TIM_CCMR1_CC1S;
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config- & gt; OCMode;
/* Reset the Output Polarity level */
tmpccer & = ~TIM_CCER_CC1P;
/* Set the Output Compare Polarity */
tmpccer |= OC_Config- & gt; OCPolarity;
if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config- & gt; OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer & = ~TIM_CCER_CC1NP;
/* Set the Output N Polarity */
tmpccer |= OC_Config- & gt; OCNPolarity;
/* Reset the Output N State */
tmpccer & = ~TIM_CCER_CC1NE;
}
if(IS_TIM_BREAK_INSTANCE(TIMx))
{
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config- & gt; OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config- & gt; OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 & = ~TIM_CR2_OIS1;
tmpcr2 & = ~TIM_CR2_OIS1N;
/* Set the Output Idle state */
tmpcr2 |= OC_Config- & gt; OCIdleState;
/* Set the Output N Idle state */
tmpcr2 |= OC_Config- & gt; OCNIdleState;
}
/* Write to TIMx CR2 */
TIMx- & gt; CR2 = tmpcr2;
/* Write to TIMx CCMR1 */
TIMx- & gt; CCMR1 = tmpccmrx;
/* Set the Capture Compare Register value */
TIMx- & gt; CCR1 = OC_Config- & gt; Pulse;
/* Write to TIMx CCER */
TIMx- & gt; CCER = tmpccer;
}
/**
* @brief Time Ouput Compare 2 configuration
* @param TIMx to select the TIM peripheral
* @param OC_Config : The ouput configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
uint32_t tmpccmrx = 0U;
uint32_t tmpccer = 0U;
uint32_t tmpcr2 = 0U;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx- & gt; CCER & = ~TIM_CCER_CC2E;
/* Get the TIMx CCER register value */
tmpccer = TIMx- & gt; CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx- & gt; CR2;
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx- & gt; CCMR1;
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx & = ~TIM_CCMR1_OC2M;
tmpccmrx & = ~TIM_CCMR1_CC2S;
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config- & gt; OCMode & lt; & lt; 8U);
/* Reset the Output Polarity level */
tmpccer & = ~TIM_CCER_CC2P;
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config- & gt; OCPolarity & lt; & lt; 4U);
if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config- & gt; OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer & = ~TIM_CCER_CC2NP;
/* Set the Output N Polarity */
tmpccer |= (OC_Config- & gt; OCNPolarity & lt; & lt; 4U);
/* Reset the Output N State */
tmpccer & = ~TIM_CCER_CC2NE;
}
if(IS_TIM_BREAK_INSTANCE(TIMx))
{
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config- & gt; OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config- & gt; OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 & = ~TIM_CR2_OIS2;
tmpcr2 & = ~TIM_CR2_OIS2N;
/* Set the Output Idle state */
tmpcr2 |= (OC_Config- & gt; OCIdleState & lt; & lt; 2);
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config- & gt; OCNIdleState & lt; & lt; 2);
}
/* Write to TIMx CR2 */
TIMx- & gt; CR2 = tmpcr2;
/* Write to TIMx CCMR1 */
TIMx- & gt; CCMR1 = tmpccmrx;
/* Set the Capture Compare Register value */
TIMx- & gt; CCR2 = OC_Config- & gt; Pulse;
/* Write to TIMx CCER */
TIMx- & gt; CCER = tmpccer;
}
/**
* @brief Time Ouput Compare 3 configuration
* @param TIMx to select the TIM peripheral
* @param OC_Config : The ouput configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
uint32_t tmpccmrx = 0U;
uint32_t tmpccer = 0U;
uint32_t tmpcr2 = 0U;
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx- & gt; CCER & = ~TIM_CCER_CC3E;
/* Get the TIMx CCER register value */
tmpccer = TIMx- & gt; CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx- & gt; CR2;
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx- & gt; CCMR2;
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx & = ~TIM_CCMR2_OC3M;
tmpccmrx & = ~TIM_CCMR2_CC3S;
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config- & gt; OCMode;
/* Reset the Output Polarity level */
tmpccer & = ~TIM_CCER_CC3P;
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config- & gt; OCPolarity & lt; & lt; 8U);
if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config- & gt; OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer & = ~TIM_CCER_CC3NP;
/* Set the Output N Polarity */
tmpccer |= (OC_Config- & gt; OCNPolarity & lt; & lt; 8U);
/* Reset the Output N State */
tmpccer & = ~TIM_CCER_CC3NE;
}
if(IS_TIM_BREAK_INSTANCE(TIMx))
{
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config- & gt; OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config- & gt; OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 & = ~TIM_CR2_OIS3;
tmpcr2 & = ~TIM_CR2_OIS3N;
/* Set the Output Idle state */
tmpcr2 |= (OC_Config- & gt; OCIdleState & lt; & lt; 4U);
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config- & gt; OCNIdleState & lt; & lt; 4U);
}
/* Write to TIMx CR2 */
TIMx- & gt; CR2 = tmpcr2;
/* Write to TIMx CCMR2 */
TIMx- & gt; CCMR2 = tmpccmrx;
/* Set the Capture Compare Register value */
TIMx- & gt; CCR3 = OC_Config- & gt; Pulse;
/* Write to TIMx CCER */
TIMx- & gt; CCER = tmpccer;
}
/**
* @brief Time Ouput Compare 4 configuration
* @param TIMx to select the TIM peripheral
* @param OC_Config : The ouput configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
uint32_t tmpccmrx = 0U;
uint32_t tmpccer = 0U;
uint32_t tmpcr2 = 0U;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx- & gt; CCER & = ~TIM_CCER_CC4E;
/* Get the TIMx CCER register value */
tmpccer = TIMx- & gt; CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx- & gt; CR2;
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx- & gt; CCMR2;
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx & = ~TIM_CCMR2_OC4M;
tmpccmrx & = ~TIM_CCMR2_CC4S;
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config- & gt; OCMode & lt; & lt; 8U);
/* Reset the Output Polarity level */
tmpccer & = ~TIM_CCER_CC4P;
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config- & gt; OCPolarity & lt; & lt; 12U);
if(IS_TIM_BREAK_INSTANCE(TIMx))
{
assert_param(IS_TIM_OCIDLE_STATE(OC_Config- & gt; OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 & = ~TIM_CR2_OIS4;
/* Set the Output Idle state */
tmpcr2 |= (OC_Config- & gt; OCIdleState & lt; & lt; 6);
}
/* Write to TIMx CR2 */
TIMx- & gt; CR2 = tmpcr2;
/* Write to TIMx CCMR2 */
TIMx- & gt; CCMR2 = tmpccmrx;
/* Set the Capture Compare Register value */
TIMx- & gt; CCR4 = OC_Config- & gt; Pulse;
/* Write to TIMx CCER */
TIMx- & gt; CCER = tmpccer;
}
/**
* @brief Time Slave configuration
* @param htim: pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @param sSlaveConfig: The slave configuration structure
* @retval None
*/
static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
TIM_SlaveConfigTypeDef * sSlaveConfig)
{
uint32_t tmpsmcr = 0U;
uint32_t tmpccmr1 = 0U;
uint32_t tmpccer = 0U;
/* Get the TIMx SMCR register value */
tmpsmcr = htim- & gt; Instance- & gt; SMCR;
/* Reset the Trigger Selection Bits */
tmpsmcr & = ~TIM_SMCR_TS;
/* Set the Input Trigger source */
tmpsmcr |= sSlaveConfig- & gt; InputTrigger;
/* Reset the slave mode Bits */
tmpsmcr & = ~TIM_SMCR_SMS;
/* Set the slave mode */
tmpsmcr |= sSlaveConfig- & gt; SlaveMode;
/* Write to TIMx SMCR */
htim- & gt; Instance- & gt; SMCR = tmpsmcr;
/* Configure the trigger prescaler, filter, and polarity */
switch (sSlaveConfig- & gt; InputTrigger)
{
case TIM_TS_ETRF:
{
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim- & gt; Instance));
assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig- & gt; TriggerPrescaler));
assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig- & gt; TriggerPolarity));
assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig- & gt; TriggerFilter));
/* Configure the ETR Trigger source */
TIM_ETR_SetConfig(htim- & gt; Instance,
sSlaveConfig- & gt; TriggerPrescaler,
sSlaveConfig- & gt; TriggerPolarity,
sSlaveConfig- & gt; TriggerFilter);
}
break;
case TIM_TS_TI1F_ED:
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim- & gt; Instance));
assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig- & gt; TriggerFilter));
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = htim- & gt; Instance- & gt; CCER;
htim- & gt; Instance- & gt; CCER & = ~TIM_CCER_CC1E;
tmpccmr1 = htim- & gt; Instance- & gt; CCMR1;
/* Set the filter */
tmpccmr1 & = ~TIM_CCMR1_IC1F;
tmpccmr1 |= ((sSlaveConfig- & gt; TriggerFilter) & lt; & lt; 4U);
/* Write to TIMx CCMR1 and CCER registers */
htim- & gt; Instance- & gt; CCMR1 = tmpccmr1;
htim- & gt; Instance- & gt; CCER = tmpccer;
}
break;
case TIM_TS_TI1FP1:
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim- & gt; Instance));
assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig- & gt; TriggerPolarity));
assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig- & gt; TriggerFilter));
/* Configure TI1 Filter and Polarity */
TIM_TI1_ConfigInputStage(htim- & gt; Instance,
sSlaveConfig- & gt; TriggerPolarity,
sSlaveConfig- & gt; TriggerFilter);
}
break;
case TIM_TS_TI2FP2:
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim- & gt; Instance));
assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig- & gt; TriggerPolarity));
assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig- & gt; TriggerFilter));
/* Configure TI2 Filter and Polarity */
TIM_TI2_ConfigInputStage(htim- & gt; Instance,
sSlaveConfig- & gt; TriggerPolarity,
sSlaveConfig- & gt; TriggerFilter);
}
break;
case TIM_TS_ITR0:
{
/* Check the parameter */
assert_param(IS_TIM_CC2_INSTANCE(htim- & gt; Instance));
}
break;
case TIM_TS_ITR1:
{
/* Check the parameter */
assert_param(IS_TIM_CC2_INSTANCE(htim- & gt; Instance));
}
break;
case TIM_TS_ITR2:
{
/* Check the parameter */
assert_param(IS_TIM_CC2_INSTANCE(htim- & gt; Instance));
}
break;
case TIM_TS_ITR3:
{
/* Check the parameter */
assert_param(IS_TIM_CC2_INSTANCE(htim- & gt; Instance));
}
break;
default:
break;
}
}
/**
* @brief Configure the TI1 as Input.
* @param TIMx to select the TIM peripheral.
* @param TIM_ICPolarity : The Input Polarity.
* This parameter can be one of the following values:
* @arg TIM_ICPOLARITY_RISING
* @arg TIM_ICPOLARITY_FALLING
* @param TIM_ICSelection : specifies the input to be used.
* This parameter can be one of the following values:
* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
* @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
* @param TIM_ICFilter : Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
* (on channel2 path) is used as the input signal. Therefore CCMR1 must be
* protected against un-initialized filter and polarity values.
*/
void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
uint32_t TIM_ICFilter)
{
uint32_t tmpccmr1 = 0U;
uint32_t tmpccer = 0U;
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx- & gt; CCER & = ~TIM_CCER_CC1E;
tmpccmr1 = TIMx- & gt; CCMR1;
tmpccer = TIMx- & gt; CCER;
/* Select the Input */
if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
{
tmpccmr1 & = ~TIM_CCMR1_CC1S;
tmpccmr1 |= TIM_ICSelection;
}
else
{
tmpccmr1 |= TIM_CCMR1_CC1S_0;
}
/* Set the filter */
tmpccmr1 & = ~TIM_CCMR1_IC1F;
tmpccmr1 |= ((TIM_ICFilter & lt; & lt; 4U) & TIM_CCMR1_IC1F);
/* Select the Polarity and set the CC1E Bit */
tmpccer & = ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
/* Write to TIMx CCMR1 and CCER registers */
TIMx- & gt; CCMR1 = tmpccmr1;
TIMx- & gt; CCER = tmpccer;
}
/**
* @brief Configure the Polarity and Filter for TI1.
* @param TIMx to select the TIM peripheral.
* @param TIM_ICPolarity : The Input Polarity.
* This parameter can be one of the following values:
* @arg TIM_ICPOLARITY_RISING
* @arg TIM_ICPOLARITY_FALLING
* @param TIM_ICFilter : Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
uint32_t tmpccmr1 = 0U;
uint32_t tmpccer = 0U;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx- & gt; CCER;
TIMx- & gt; CCER & = ~TIM_CCER_CC1E;
tmpccmr1 = TIMx- & gt; CCMR1;
/* Set the filter */
tmpccmr1 & = ~TIM_CCMR1_IC1F;
tmpccmr1 |= (TIM_ICFilter & lt; & lt; 4U);
/* Select the Polarity and set the CC1E Bit */
tmpccer & = ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
tmpccer |= TIM_ICPolarity;
/* Write to TIMx CCMR1 and CCER registers */
TIMx- & gt; CCMR1 = tmpccmr1;
TIMx- & gt; CCER = tmpccer;
}
/**
* @brief Configure the TI2 as Input.
* @param TIMx to select the TIM peripheral
* @param TIM_ICPolarity : The Input Polarity.
* This parameter can be one of the following values:
* @arg TIM_ICPOLARITY_RISING
* @arg TIM_ICPOLARITY_FALLING
* @param TIM_ICSelection : specifies the input to be used.
* This parameter can be one of the following values:
* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
* @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
* @param TIM_ICFilter : Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
* (on channel1 path) is used as the input signal. Therefore CCMR1 must be
* protected against un-initialized filter and polarity values.
*/
static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
uint32_t TIM_ICFilter)
{
uint32_t tmpccmr1 = 0U;
uint32_t tmpccer = 0U;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx- & gt; CCER & = ~TIM_CCER_CC2E;
tmpccmr1 = TIMx- & gt; CCMR1;
tmpccer = TIMx- & gt; CCER;
/* Select the Input */
tmpccmr1 & = ~TIM_CCMR1_CC2S;
tmpccmr1 |= (TIM_ICSelection & lt; & lt; 8U);
/* Set the filter */
tmpccmr1 & = ~TIM_CCMR1_IC2F;
tmpccmr1 |= ((TIM_ICFilter & lt; & lt; 12U) & TIM_CCMR1_IC2F);
/* Select the Polarity and set the CC2E Bit */
tmpccer & = ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
tmpccer |= ((TIM_ICPolarity & lt; & lt; 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
/* Write to TIMx CCMR1 and CCER registers */
TIMx- & gt; CCMR1 = tmpccmr1 ;
TIMx- & gt; CCER = tmpccer;
}
/**
* @brief Configure the Polarity and Filter for TI2.
* @param TIMx to select the TIM peripheral.
* @param TIM_ICPolarity : The Input Polarity.
* This parameter can be one of the following values:
* @arg TIM_ICPOLARITY_RISING
* @arg TIM_ICPOLARITY_FALLING
* @param TIM_ICFilter : Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
uint32_t tmpccmr1 = 0U;
uint32_t tmpccer = 0U;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx- & gt; CCER & = ~TIM_CCER_CC2E;
tmpccmr1 = TIMx- & gt; CCMR1;
tmpccer = TIMx- & gt; CCER;
/* Set the filter */
tmpccmr1 & = ~TIM_CCMR1_IC2F;
tmpccmr1 |= (TIM_ICFilter & lt; & lt; 12U);
/* Select the Polarity and set the CC2E Bit */
tmpccer & = ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
tmpccer |= (TIM_ICPolarity & lt; & lt; 4U);
/* Write to TIMx CCMR1 and CCER registers */
TIMx- & gt; CCMR1 = tmpccmr1 ;
TIMx- & gt; CCER = tmpccer;
}
/**
* @brief Configure the TI3 as Input.
* @param TIMx to select the TIM peripheral
* @param TIM_ICPolarity : The Input Polarity.
* This parameter can be one of the following values:
* @arg TIM_ICPOLARITY_RISING
* @arg TIM_ICPOLARITY_FALLING
* @param TIM_ICSelection : specifies the input to be used.
* This parameter can be one of the following values:
* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
* @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
* @param TIM_ICFilter : Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
* protected against un-initialized filter and polarity values.
*/
static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
uint32_t TIM_ICFilter)
{
uint32_t tmpccmr2 = 0U;
uint32_t tmpccer = 0U;
/* Disable the Channel 3: Reset the CC3E Bit */
TIMx- & gt; CCER & = ~TIM_CCER_CC3E;
tmpccmr2 = TIMx- & gt; CCMR2;
tmpccer = TIMx- & gt; CCER;
/* Select the Input */
tmpccmr2 & = ~TIM_CCMR2_CC3S;
tmpccmr2 |= TIM_ICSelection;
/* Set the filter */
tmpccmr2 & = ~TIM_CCMR2_IC3F;
tmpccmr2 |= ((TIM_ICFilter & lt; & lt; 4U) & TIM_CCMR2_IC3F);
/* Select the Polarity and set the CC3E Bit */
tmpccer & = ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
tmpccer |= ((TIM_ICPolarity & lt; & lt; 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
/* Write to TIMx CCMR2 and CCER registers */
TIMx- & gt; CCMR2 = tmpccmr2;
TIMx- & gt; CCER = tmpccer;
}
/**
* @brief Configure the TI4 as Input.
* @param TIMx to select the TIM peripheral
* @param TIM_ICPolarity : The Input Polarity.
* This parameter can be one of the following values:
* @arg TIM_ICPOLARITY_RISING
* @arg TIM_ICPOLARITY_FALLING
* @param TIM_ICSelection : specifies the input to be used.
* This parameter can be one of the following values:
* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
* @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
* @param TIM_ICFilter : Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
* protected against un-initialized filter and polarity values.
* @retval None
*/
static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
uint32_t TIM_ICFilter)
{
uint32_t tmpccmr2 = 0U;
uint32_t tmpccer = 0U;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx- & gt; CCER & = ~TIM_CCER_CC4E;
tmpccmr2 = TIMx- & gt; CCMR2;
tmpccer = TIMx- & gt; CCER;
/* Select the Input */
tmpccmr2 & = ~TIM_CCMR2_CC4S;
tmpccmr2 |= (TIM_ICSelection & lt; & lt; 8U);
/* Set the filter */
tmpccmr2 & = ~TIM_CCMR2_IC4F;
tmpccmr2 |= ((TIM_ICFilter & lt; & lt; 12U) & TIM_CCMR2_IC4F);
/* Select the Polarity and set the CC4E Bit */
tmpccer & = ~TIM_CCER_CC4P;
tmpccer |= ((TIM_ICPolarity & lt; & lt; 12U) & TIM_CCER_CC4P);
/* Write to TIMx CCMR2 and CCER registers */
TIMx- & gt; CCMR2 = tmpccmr2;
TIMx- & gt; CCER = tmpccer ;
}
/**
* @brief Selects the Input Trigger source
* @param TIMx to select the TIM peripheral
* @param InputTriggerSource : The Input Trigger source.
* This parameter can be one of the following values:
* @arg TIM_TS_ITR0 : Internal Trigger 0
* @arg TIM_TS_ITR1 : Internal Trigger 1
* @arg TIM_TS_ITR2 : Internal Trigger 2
* @arg TIM_TS_ITR3 : Internal Trigger 3
* @arg TIM_TS_TI1F_ED : TI1 Edge Detector
* @arg TIM_TS_TI1FP1 : Filtered Timer Input 1
* @arg TIM_TS_TI2FP2 : Filtered Timer Input 2
* @arg TIM_TS_ETRF : External Trigger input
* @retval None
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
{
uint32_t tmpsmcr = 0U;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx- & gt; SMCR;
/* Reset the TS Bits */
tmpsmcr & = ~TIM_SMCR_TS;
/* Set the Input Trigger source and the slave mode*/
tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
/* Write to TIMx SMCR */
TIMx- & gt; SMCR = tmpsmcr;
}
/**
* @brief Configures the TIMx External Trigger (ETR).
* @param TIMx to select the TIM peripheral
* @param TIM_ExtTRGPrescaler : The external Trigger Prescaler.
* This parameter can be one of the following values:
* @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
* @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
* @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
* @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
* @param TIM_ExtTRGPolarity : The external Trigger Polarity.
* This parameter can be one of the following values:
* @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
* @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
* @param ExtTRGFilter : External Trigger Filter.
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
uint32_t tmpsmcr = 0U;
tmpsmcr = TIMx- & gt; SMCR;
/* Reset the ETR Bits */
tmpsmcr & = ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter & lt; & lt; 8U)));
/* Write to TIMx SMCR */
TIMx- & gt; SMCR = tmpsmcr;
}
/**
* @brief Enables or disables the TIM Capture Compare Channel x.
* @param TIMx to select the TIM peripheral
* @param Channel : specifies the TIM Channel
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1
* @arg TIM_CHANNEL_2: TIM Channel 2
* @arg TIM_CHANNEL_3: TIM Channel 3
* @arg TIM_CHANNEL_4: TIM Channel 4
* @param ChannelState : specifies the TIM Channel CCxE bit new state.
* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
* @retval None
*/
void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
{
uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
assert_param(IS_TIM_CHANNELS(Channel));
tmp = TIM_CCER_CC1E & lt; & lt; Channel;
/* Reset the CCxE Bit */
TIMx- & gt; CCER & = ~tmp;
/* Set or reset the CCxE Bit */
TIMx- & gt; CCER |= (uint32_t)(ChannelState & lt; & lt; Channel);
}
/**
* @}
*/
#endif /* HAL_TIM_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file stm32f1xx_hal_tim_ex.c
* @author MCD Application Team
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer Extended peripheral:
* + Time Hall Sensor Interface Initialization
* + Time Hall Sensor Interface Start
* + Time Complementary signal bread and dead time configuration
* + Time Master and Slave synchronization configuration
* + Timer remapping capabilities configuration
@verbatim
==============================================================================
##### TIMER Extended features #####
==============================================================================
[..]
The Timer Extended features include:
(#) Complementary outputs with programmable dead-time for :
(++) Output Compare
(++) PWM generation (Edge and Center-aligned Mode)
(++) One-pulse mode output
(#) Synchronization circuit to control the timer with external signals and to
interconnect several timers together.
(#) Break input to put the timer output signals in reset state or in a known state.
(#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
positioning purposes
##### How to use this driver #####
==============================================================================
[..]
(#) Initialize the TIM low level resources by implementing the following functions
depending from feature used :
(++) Complementary Output Compare : HAL_TIM_OC_MspInit()
(++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
(++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
(++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
(#) Initialize the TIM low level resources :
(##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
(##) TIM pins configuration
(+++) Enable the clock for the TIM GPIOs using the following function:
__HAL_RCC_GPIOx_CLK_ENABLE();
(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
(#) The external Clock can be configured, if needed (the default clock is the
internal clock from the APBx), using the following function:
HAL_TIM_ConfigClockSource, the clock configuration should be done before
any start function.
(#) Configure the TIM in the desired functioning mode using one of the
initialization function of this driver:
(++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
Timer Hall Sensor Interface and the commutation event with the corresponding
Interrupt and DMA request if needed (Note that One Timer is used to interface
with the Hall sensor Interface and another Timer should be used to use
the commutation event).
(#) Activate the TIM peripheral using one of the start functions:
(++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
(++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
(++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
(++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
@endverbatim
******************************************************************************
* @attention
*
* & lt; h2 & gt; & lt; center & gt; & copy; COPYRIGHT(c) 2016 STMicroelectronics & lt; /center & gt; & lt; /h2 & gt;
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS " AS IS "
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include " stm32f1xx_hal.h "
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @defgroup TIMEx TIMEx
* @brief TIM Extended HAL module driver
* @{
*/
#ifdef HAL_TIM_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
#if defined (STM32F100xB) || defined (STM32F100xE) || \
defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
defined (STM32F105xC) || defined (STM32F107xC)
/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
* @{
*/
static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
/**
* @}
*/
#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
/* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
/* defined(STM32F105xC) || defined(STM32F107xC) */
/* Exported functions ---------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions
* @{
*/
/** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions
* @brief Timer Hall Sensor functions
*
@verbatim
==============================================================================
##### Timer Hall Sensor functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Initialize and configure TIM HAL Sensor.
(+) De-initialize TIM HAL Sensor.
(+) Start the Hall Sensor Interface.
(+) Stop the Hall Sensor Interface.
(+) Start the Hall Sensor Interface and enable interrupts.
(+) Stop the Hall Sensor Interface and disable interrupts.
(+) Start the Hall Sensor Interface and enable DMA transfers.
(+) Stop the Hall Sensor Interface and disable DMA transfers.
@endverbatim
* @{
*/
/**
* @brief Initializes the TIM Hall Sensor Interface and create the associated handle.
* @param htim : TIM Encoder Interface handle
* @param sConfig : TIM Hall Sensor configuration structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
{
TIM_OC_InitTypeDef OC_Config;
/* Check the TIM handle allocation */
if(htim == NULL)
{
return HAL_ERROR;
}
assert_param(IS_TIM_XOR_INSTANCE(htim- & gt; Instance));
assert_param(IS_TIM_COUNTER_MODE(htim- & gt; Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim- & gt; Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim- & gt; Init.AutoReloadPreload));
assert_param(IS_TIM_IC_POLARITY(sConfig- & gt; IC1Polarity));
assert_param(IS_TIM_IC_PRESCALER(sConfig- & gt; IC1Prescaler));
assert_param(IS_TIM_IC_FILTER(sConfig- & gt; IC1Filter));
if(htim- & gt; State == HAL_TIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
htim- & gt; Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIMEx_HallSensor_MspInit(htim);
}
/* Set the TIM state */
htim- & gt; State= HAL_TIM_STATE_BUSY;
/* Configure the Time base in the Encoder Mode */
TIM_Base_SetConfig(htim- & gt; Instance, & htim- & gt; Init);
/* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
TIM_TI1_SetConfig(htim- & gt; Instance, sConfig- & gt; IC1Polarity, TIM_ICSELECTION_TRC, sConfig- & gt; IC1Filter);
/* Reset the IC1PSC Bits */
htim- & gt; Instance- & gt; CCMR1 & = ~TIM_CCMR1_IC1PSC;
/* Set the IC1PSC value */
htim- & gt; Instance- & gt; CCMR1 |= sConfig- & gt; IC1Prescaler;
/* Enable the Hall sensor interface (XOR function of the three inputs) */
htim- & gt; Instance- & gt; CR2 |= TIM_CR2_TI1S;
/* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
htim- & gt; Instance- & gt; SMCR & = ~TIM_SMCR_TS;
htim- & gt; Instance- & gt; SMCR |= TIM_TS_TI1F_ED;
/* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
htim- & gt; Instance- & gt; SMCR & = ~TIM_SMCR_SMS;
htim- & gt; Instance- & gt; SMCR |= TIM_SLAVEMODE_RESET;
/* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
OC_Config.OCMode = TIM_OCMODE_PWM2;
OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
OC_Config.Pulse = sConfig- & gt; Commutation_Delay;
TIM_OC2_SetConfig(htim- & gt; Instance, & OC_Config);
/* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
register to 101 */
htim- & gt; Instance- & gt; CR2 & = ~TIM_CR2_MMS;
htim- & gt; Instance- & gt; CR2 |= TIM_TRGO_OC2REF;
/* Initialize the TIM state*/
htim- & gt; State= HAL_TIM_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitializes the TIM Hall Sensor interface
* @param htim : TIM Hall Sensor handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim- & gt; Instance));
htim- & gt; State = HAL_TIM_STATE_BUSY;
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_TIMEx_HallSensor_MspDeInit(htim);
/* Change TIM state */
htim- & gt; State = HAL_TIM_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(htim);
return HAL_OK;
}
/**
* @brief Initializes the TIM Hall Sensor MSP.
* @param htim : TIM handle
* @retval None
*/
__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes TIM Hall Sensor MSP.
* @param htim : TIM handle
* @retval None
*/
__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
*/
}
/**
* @brief Starts the TIM Hall Sensor Interface.
* @param htim : TIM Hall Sensor handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
{
/* Check the parameters */
assert_param(IS_TIM_XOR_INSTANCE(htim- & gt; Instance));
/* Enable the Input Capture channel 1
(in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Stops the TIM Hall sensor Interface.
* @param htim : TIM Hall Sensor handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
{
/* Check the parameters */
assert_param(IS_TIM_XOR_INSTANCE(htim- & gt; Instance));
/* Disable the Input Capture channel 1
(in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Starts the TIM Hall Sensor Interface in interrupt mode.
* @param htim : TIM Hall Sensor handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
{
/* Check the parameters */
assert_param(IS_TIM_XOR_INSTANCE(htim- & gt; Instance));
/* Enable the capture compare Interrupts 1 event */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
/* Enable the Input Capture channel 1
(in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Stops the TIM Hall Sensor Interface in interrupt mode.
* @param htim : TIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
{
/* Check the parameters */
assert_param(IS_TIM_XOR_INSTANCE(htim- & gt; Instance));
/* Disable the Input Capture channel 1
(in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
/* Disable the capture compare Interrupts event */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Starts the TIM Hall Sensor Interface in DMA mode.
* @param htim : TIM Hall Sensor handle
* @param pData : The destination Buffer address.
* @param Length : The length of data to be transferred from TIM peripheral to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
{
/* Check the parameters */
assert_param(IS_TIM_XOR_INSTANCE(htim- & gt; Instance));
if((htim- & gt; State == HAL_TIM_STATE_BUSY))
{
return HAL_BUSY;
}
else if((htim- & gt; State == HAL_TIM_STATE_READY))
{
if(((uint32_t)pData == 0U) & & (Length & gt; 0U))
{
return HAL_ERROR;
}
else
{
htim- & gt; State = HAL_TIM_STATE_BUSY;
}
}
/* Enable the Input Capture channel 1
(in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
/* Set the DMA Input Capture 1 Callback */
htim- & gt; hdma[TIM_DMA_ID_CC1]- & gt; XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_CC1]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel for Capture 1*/
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_CC1], (uint32_t) & htim- & gt; Instance- & gt; CCR1, (uint32_t)pData, Length);
/* Enable the capture compare 1 Interrupt */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Stops the TIM Hall Sensor Interface in DMA mode.
* @param htim : TIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
{
/* Check the parameters */
assert_param(IS_TIM_XOR_INSTANCE(htim- & gt; Instance));
/* Disable the Input Capture channel 1
(in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim- & gt; Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
/* Disable the capture compare Interrupts 1 event */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
#if defined (STM32F100xB) || defined (STM32F100xE) || \
defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
defined (STM32F105xC) || defined (STM32F107xC)
/** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions
* @brief Timer Complementary Output Compare functions
*
@verbatim
==============================================================================
##### Timer Complementary Output Compare functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Start the Complementary Output Compare/PWM.
(+) Stop the Complementary Output Compare/PWM.
(+) Start the Complementary Output Compare/PWM and enable interrupts.
(+) Stop the Complementary Output Compare/PWM and disable interrupts.
(+) Start the Complementary Output Compare/PWM and enable DMA transfers.
(+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
@endverbatim
* @{
*/
/**
* @brief Starts the TIM Output Compare signal generation on the complementary
* output.
* @param htim : TIM Output Compare handle
* @param Channel : TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim- & gt; Instance, Channel));
/* Enable the Capture compare channel N */
TIM_CCxNChannelCmd(htim- & gt; Instance, Channel, TIM_CCxN_ENABLE);
/* Enable the Main Ouput */
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Stops the TIM Output Compare signal generation on the complementary
* output.
* @param htim : TIM handle
* @param Channel : TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim- & gt; Instance, Channel));
/* Disable the Capture compare channel N */
TIM_CCxNChannelCmd(htim- & gt; Instance, Channel, TIM_CCxN_DISABLE);
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Starts the TIM Output Compare signal generation in interrupt mode
* on the complementary output.
* @param htim : TIM OC handle
* @param Channel : TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim- & gt; Instance, Channel));
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Enable the TIM Output Compare interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
}
break;
case TIM_CHANNEL_2:
{
/* Enable the TIM Output Compare interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
}
break;
case TIM_CHANNEL_3:
{
/* Enable the TIM Output Compare interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
}
break;
default:
break;
}
/* Enable the TIM Break interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
/* Enable the Capture compare channel N */
TIM_CCxNChannelCmd(htim- & gt; Instance, Channel, TIM_CCxN_ENABLE);
/* Enable the Main Ouput */
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Stops the TIM Output Compare signal generation in interrupt mode
* on the complementary output.
* @param htim : TIM Output Compare handle
* @param Channel : TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
uint32_t tmpccer = 0U;
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim- & gt; Instance, Channel));
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Disable the TIM Output Compare interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
}
break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Output Compare interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
}
break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Output Compare interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
}
break;
default:
break;
}
/* Disable the Capture compare channel N */
TIM_CCxNChannelCmd(htim- & gt; Instance, Channel, TIM_CCxN_DISABLE);
/* Disable the TIM Break interrupt (only if no more channel is active) */
tmpccer = htim- & gt; Instance- & gt; CCER;
if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
{
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
}
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Starts the TIM Output Compare signal generation in DMA mode
* on the complementary output.
* @param htim : TIM Output Compare handle
* @param Channel : TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @param pData : The source Buffer address.
* @param Length : The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim- & gt; Instance, Channel));
if((htim- & gt; State == HAL_TIM_STATE_BUSY))
{
return HAL_BUSY;
}
else if((htim- & gt; State == HAL_TIM_STATE_READY))
{
if(((uint32_t)pData == 0U) & & (Length & gt; 0U))
{
return HAL_ERROR;
}
else
{
htim- & gt; State = HAL_TIM_STATE_BUSY;
}
}
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_CC1]- & gt; XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_CC1]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t) & htim- & gt; Instance- & gt; CCR1, Length);
/* Enable the TIM Output Compare DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
}
break;
case TIM_CHANNEL_2:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_CC2]- & gt; XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_CC2]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t) & htim- & gt; Instance- & gt; CCR2, Length);
/* Enable the TIM Output Compare DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
}
break;
case TIM_CHANNEL_3:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_CC3]- & gt; XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_CC3]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t) & htim- & gt; Instance- & gt; CCR3,Length);
/* Enable the TIM Output Compare DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
}
break;
default:
break;
}
/* Enable the Capture compare channel N */
TIM_CCxNChannelCmd(htim- & gt; Instance, Channel, TIM_CCxN_ENABLE);
/* Enable the Main Ouput */
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Stops the TIM Output Compare signal generation in DMA mode
* on the complementary output.
* @param htim : TIM Output Compare handle
* @param Channel : TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim- & gt; Instance, Channel));
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Disable the TIM Output Compare DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
}
break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Output Compare DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
}
break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Output Compare DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
}
break;
default:
break;
}
/* Disable the Capture compare channel N */
TIM_CCxNChannelCmd(htim- & gt; Instance, Channel, TIM_CCxN_DISABLE);
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Change the htim state */
htim- & gt; State = HAL_TIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions
* @brief Timer Complementary PWM functions
*
@verbatim
==============================================================================
##### Timer Complementary PWM functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Start the Complementary PWM.
(+) Stop the Complementary PWM.
(+) Start the Complementary PWM and enable interrupts.
(+) Stop the Complementary PWM and disable interrupts.
(+) Start the Complementary PWM and enable DMA transfers.
(+) Stop the Complementary PWM and disable DMA transfers.
(+) Start the Complementary Input Capture measurement.
(+) Stop the Complementary Input Capture.
(+) Start the Complementary Input Capture and enable interrupts.
(+) Stop the Complementary Input Capture and disable interrupts.
(+) Start the Complementary Input Capture and enable DMA transfers.
(+) Stop the Complementary Input Capture and disable DMA transfers.
(+) Start the Complementary One Pulse generation.
(+) Stop the Complementary One Pulse.
(+) Start the Complementary One Pulse and enable interrupts.
(+) Stop the Complementary One Pulse and disable interrupts.
@endverbatim
* @{
*/
/**
* @brief Starts the PWM signal generation on the complementary output.
* @param htim : TIM handle
* @param Channel : TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim- & gt; Instance, Channel));
/* Enable the complementary PWM output */
TIM_CCxNChannelCmd(htim- & gt; Instance, Channel, TIM_CCxN_ENABLE);
/* Enable the Main Ouput */
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Stops the PWM signal generation on the complementary output.
* @param htim : TIM handle
* @param Channel : TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim- & gt; Instance, Channel));
/* Disable the complementary PWM output */
TIM_CCxNChannelCmd(htim- & gt; Instance, Channel, TIM_CCxN_DISABLE);
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Starts the PWM signal generation in interrupt mode on the
* complementary output.
* @param htim : TIM handle
* @param Channel : TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim- & gt; Instance, Channel));
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
}
break;
case TIM_CHANNEL_2:
{
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
}
break;
case TIM_CHANNEL_3:
{
/* Enable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
}
break;
default:
break;
}
/* Enable the TIM Break interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
/* Enable the complementary PWM output */
TIM_CCxNChannelCmd(htim- & gt; Instance, Channel, TIM_CCxN_ENABLE);
/* Enable the Main Ouput */
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Stops the PWM signal generation in interrupt mode on the
* complementary output.
* @param htim : TIM handle
* @param Channel : TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
uint32_t tmpccer = 0U;
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim- & gt; Instance, Channel));
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Disable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
}
break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
}
break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
}
break;
default:
break;
}
/* Disable the complementary PWM output */
TIM_CCxNChannelCmd(htim- & gt; Instance, Channel, TIM_CCxN_DISABLE);
/* Disable the TIM Break interrupt (only if no more channel is active) */
tmpccer = htim- & gt; Instance- & gt; CCER;
if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
{
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
}
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Starts the TIM PWM signal generation in DMA mode on the
* complementary output
* @param htim : TIM handle
* @param Channel : TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @param pData : The source Buffer address.
* @param Length : The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim- & gt; Instance, Channel));
if((htim- & gt; State == HAL_TIM_STATE_BUSY))
{
return HAL_BUSY;
}
else if((htim- & gt; State == HAL_TIM_STATE_READY))
{
if(((uint32_t)pData == 0U) & & (Length & gt; 0U))
{
return HAL_ERROR;
}
else
{
htim- & gt; State = HAL_TIM_STATE_BUSY;
}
}
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_CC1]- & gt; XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_CC1]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t) & htim- & gt; Instance- & gt; CCR1, Length);
/* Enable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
}
break;
case TIM_CHANNEL_2:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_CC2]- & gt; XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_CC2]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t) & htim- & gt; Instance- & gt; CCR2, Length);
/* Enable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
}
break;
case TIM_CHANNEL_3:
{
/* Set the DMA Period elapsed callback */
htim- & gt; hdma[TIM_DMA_ID_CC3]- & gt; XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_CC3]- & gt; XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim- & gt; hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t) & htim- & gt; Instance- & gt; CCR3,Length);
/* Enable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
}
break;
default:
break;
}
/* Enable the complementary PWM output */
TIM_CCxNChannelCmd(htim- & gt; Instance, Channel, TIM_CCxN_ENABLE);
/* Enable the Main Ouput */
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Stops the TIM PWM signal generation in DMA mode on the complementary
* output
* @param htim : TIM handle
* @param Channel : TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim- & gt; Instance, Channel));
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Disable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
}
break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
}
break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
}
break;
default:
break;
}
/* Disable the complementary PWM output */
TIM_CCxNChannelCmd(htim- & gt; Instance, Channel, TIM_CCxN_DISABLE);
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Change the htim state */
htim- & gt; State = HAL_TIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions
* @brief Timer Complementary One Pulse functions
*
@verbatim
==============================================================================
##### Timer Complementary One Pulse functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Start the Complementary One Pulse generation.
(+) Stop the Complementary One Pulse.
(+) Start the Complementary One Pulse and enable interrupts.
(+) Stop the Complementary One Pulse and disable interrupts.
@endverbatim
* @{
*/
/**
* @brief Starts the TIM One Pulse signal generation on the complemetary
* output.
* @param htim : TIM One Pulse handle
* @param OutputChannel : TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim- & gt; Instance, OutputChannel));
/* Enable the complementary One Pulse output */
TIM_CCxNChannelCmd(htim- & gt; Instance, OutputChannel, TIM_CCxN_ENABLE);
/* Enable the Main Ouput */
__HAL_TIM_MOE_ENABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Stops the TIM One Pulse signal generation on the complementary
* output.
* @param htim : TIM One Pulse handle
* @param OutputChannel : TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim- & gt; Instance, OutputChannel));
/* Disable the complementary One Pulse output */
TIM_CCxNChannelCmd(htim- & gt; Instance, OutputChannel, TIM_CCxN_DISABLE);
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Starts the TIM One Pulse signal generation in interrupt mode on the
* complementary channel.
* @param htim : TIM One Pulse handle
* @param OutputChannel : TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim- & gt; Instance, OutputChannel));
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
/* Enable the complementary One Pulse output */
TIM_CCxNChannelCmd(htim- & gt; Instance, OutputChannel, TIM_CCxN_ENABLE);
/* Enable the Main Ouput */
__HAL_TIM_MOE_ENABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Stops the TIM One Pulse signal generation in interrupt mode on the
* complementary channel.
* @param htim : TIM One Pulse handle
* @param OutputChannel : TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim- & gt; Instance, OutputChannel));
/* Disable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
/* Disable the complementary One Pulse output */
TIM_CCxNChannelCmd(htim- & gt; Instance, OutputChannel, TIM_CCxN_DISABLE);
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
/* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
/* defined(STM32F105xC) || defined(STM32F107xC) */
/** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Configure the commutation event in case of use of the Hall sensor interface.
(+) Configure Complementary channels, break features and dead time.
(+) Configure Master synchronization.
@endverbatim
* @{
*/
#if defined (STM32F100xB) || defined (STM32F100xE) || \
defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
defined (STM32F105xC) || defined (STM32F107xC)
/**
* @brief Configure the TIM commutation event sequence.
* @note: this function is mandatory to use the commutation event in order to
* update the configuration at each commutation detection on the TRGI input of the Timer,
* the typical use of this feature is with the use of another Timer(interface Timer)
* configured in Hall sensor interface, this interface Timer will generate the
* commutation at its TRGO output (connected to Timer used in this function) each time
* the TI1 of the Interface Timer detect a commutation at its input TI1.
* @param htim : TIM handle
* @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
* This parameter can be one of the following values:
* @arg TIM_TS_ITR0: Internal trigger 0 selected
* @arg TIM_TS_ITR1: Internal trigger 1 selected
* @arg TIM_TS_ITR2: Internal trigger 2 selected
* @arg TIM_TS_ITR3: Internal trigger 3 selected
* @arg TIM_TS_NONE: No trigger is needed
* @param CommutationSource : the Commutation Event source
* This parameter can be one of the following values:
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
{
/* Check the parameters */
assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim- & gt; Instance));
assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
__HAL_LOCK(htim);
if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
(InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
{
/* Select the Input trigger */
htim- & gt; Instance- & gt; SMCR & = ~TIM_SMCR_TS;
htim- & gt; Instance- & gt; SMCR |= InputTrigger;
}
/* Select the Capture Compare preload feature */
htim- & gt; Instance- & gt; CR2 |= TIM_CR2_CCPC;
/* Select the Commutation event source */
htim- & gt; Instance- & gt; CR2 & = ~TIM_CR2_CCUS;
htim- & gt; Instance- & gt; CR2 |= CommutationSource;
__HAL_UNLOCK(htim);
return HAL_OK;
}
/**
* @brief Configure the TIM commutation event sequence with interrupt.
* @note: this function is mandatory to use the commutation event in order to
* update the configuration at each commutation detection on the TRGI input of the Timer,
* the typical use of this feature is with the use of another Timer(interface Timer)
* configured in Hall sensor interface, this interface Timer will generate the
* commutation at its TRGO output (connected to Timer used in this function) each time
* the TI1 of the Interface Timer detect a commutation at its input TI1.
* @param htim : TIM handle
* @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
* This parameter can be one of the following values:
* @arg TIM_TS_ITR0: Internal trigger 0 selected
* @arg TIM_TS_ITR1: Internal trigger 1 selected
* @arg TIM_TS_ITR2: Internal trigger 2 selected
* @arg TIM_TS_ITR3: Internal trigger 3 selected
* @arg TIM_TS_NONE: No trigger is needed
* @param CommutationSource : the Commutation Event source
* This parameter can be one of the following values:
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
{
/* Check the parameters */
assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim- & gt; Instance));
assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
__HAL_LOCK(htim);
if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
(InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
{
/* Select the Input trigger */
htim- & gt; Instance- & gt; SMCR & = ~TIM_SMCR_TS;
htim- & gt; Instance- & gt; SMCR |= InputTrigger;
}
/* Select the Capture Compare preload feature */
htim- & gt; Instance- & gt; CR2 |= TIM_CR2_CCPC;
/* Select the Commutation event source */
htim- & gt; Instance- & gt; CR2 & = ~TIM_CR2_CCUS;
htim- & gt; Instance- & gt; CR2 |= CommutationSource;
/* Enable the Commutation Interrupt Request */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
__HAL_UNLOCK(htim);
return HAL_OK;
}
/**
* @brief Configure the TIM commutation event sequence with DMA.
* @note: this function is mandatory to use the commutation event in order to
* update the configuration at each commutation detection on the TRGI input of the Timer,
* the typical use of this feature is with the use of another Timer(interface Timer)
* configured in Hall sensor interface, this interface Timer will generate the
* commutation at its TRGO output (connected to Timer used in this function) each time
* the TI1 of the Interface Timer detect a commutation at its input TI1.
* @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
* @param htim : TIM handle
* @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
* This parameter can be one of the following values:
* @arg TIM_TS_ITR0: Internal trigger 0 selected
* @arg TIM_TS_ITR1: Internal trigger 1 selected
* @arg TIM_TS_ITR2: Internal trigger 2 selected
* @arg TIM_TS_ITR3: Internal trigger 3 selected
* @arg TIM_TS_NONE: No trigger is needed
* @param CommutationSource : the Commutation Event source
* This parameter can be one of the following values:
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
{
/* Check the parameters */
assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim- & gt; Instance));
assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
__HAL_LOCK(htim);
if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
(InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
{
/* Select the Input trigger */
htim- & gt; Instance- & gt; SMCR & = ~TIM_SMCR_TS;
htim- & gt; Instance- & gt; SMCR |= InputTrigger;
}
/* Select the Capture Compare preload feature */
htim- & gt; Instance- & gt; CR2 |= TIM_CR2_CCPC;
/* Select the Commutation event source */
htim- & gt; Instance- & gt; CR2 & = ~TIM_CR2_CCUS;
htim- & gt; Instance- & gt; CR2 |= CommutationSource;
/* Enable the Commutation DMA Request */
/* Set the DMA Commutation Callback */
htim- & gt; hdma[TIM_DMA_ID_COMMUTATION]- & gt; XferCpltCallback = TIMEx_DMACommutationCplt;
/* Set the DMA error callback */
htim- & gt; hdma[TIM_DMA_ID_COMMUTATION]- & gt; XferErrorCallback = TIM_DMAError;
/* Enable the Commutation DMA Request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
__HAL_UNLOCK(htim);
return HAL_OK;
}
/**
* @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
* and the AOE(automatic output enable).
* @param htim : TIM handle
* @param sBreakDeadTimeConfig : pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
* contains the BDTR Register configuration information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
{
uint32_t tmpbdtr = 0U;
/* Check the parameters */
assert_param(IS_TIM_BREAK_INSTANCE(htim- & gt; Instance));
assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig- & gt; OffStateRunMode));
assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig- & gt; OffStateIDLEMode));
assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig- & gt; LockLevel));
assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig- & gt; DeadTime));
assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig- & gt; BreakState));
assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig- & gt; BreakPolarity));
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig- & gt; AutomaticOutput));
/* Process Locked */
__HAL_LOCK(htim);
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
/* Set the BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig- & gt; DeadTime);
MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig- & gt; LockLevel);
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig- & gt; OffStateIDLEMode);
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig- & gt; OffStateRunMode);
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig- & gt; BreakState);
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig- & gt; BreakPolarity);
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig- & gt; AutomaticOutput);
MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig- & gt; AutomaticOutput);
/* Set TIMx_BDTR */
htim- & gt; Instance- & gt; BDTR = tmpbdtr;
__HAL_UNLOCK(htim);
return HAL_OK;
}
#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
/* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
/* defined(STM32F105xC) || defined(STM32F107xC) */
/**
* @brief Configures the TIM in master mode.
* @param htim : TIM handle.
* @param sMasterConfig : pointer to a TIM_MasterConfigTypeDef structure that
* contains the selected trigger output (TRGO) and the Master/Slave
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
{
/* Check the parameters */
assert_param(IS_TIM_MASTER_INSTANCE(htim- & gt; Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig- & gt; MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig- & gt; MasterSlaveMode));
__HAL_LOCK(htim);
htim- & gt; State = HAL_TIM_STATE_BUSY;
/* Reset the MMS Bits */
htim- & gt; Instance- & gt; CR2 & = ~TIM_CR2_MMS;
/* Select the TRGO source */
htim- & gt; Instance- & gt; CR2 |= sMasterConfig- & gt; MasterOutputTrigger;
/* Reset the MSM Bit */
htim- & gt; Instance- & gt; SMCR & = ~TIM_SMCR_MSM;
/* Set or Reset the MSM Bit */
htim- & gt; Instance- & gt; SMCR |= sMasterConfig- & gt; MasterSlaveMode;
htim- & gt; State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
return HAL_OK;
}
/**
* @}
*/
/** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions
* @brief Extension Callbacks functions
*
@verbatim
==============================================================================
##### Extension Callbacks functions #####
==============================================================================
[..]
This section provides Extension TIM callback functions:
(+) Timer Commutation callback
(+) Timer Break callback
@endverbatim
* @{
*/
/**
* @brief Hall commutation changed callback in non blocking mode
* @param htim : TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIMEx_CommutationCallback could be implemented in the user file
*/
}
/**
* @brief Hall Break detection callback in non blocking mode
* @param htim : TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
/**
* @brief TIM DMA Commutation callback.
* @param hdma : pointer to DMA handle.
* @retval None
*/
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)- & gt; Parent;
htim- & gt; State= HAL_TIM_STATE_READY;
HAL_TIMEx_CommutationCallback(htim);
}
/**
* @}
*/
#if defined (STM32F100xB) || defined (STM32F100xE) || \
defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
defined (STM32F105xC) || defined (STM32F107xC)
/** @defgroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions
* @brief Extension Peripheral State functions
*
@verbatim
==============================================================================
##### Extension Peripheral State functions #####
==============================================================================
[..]
This subsection permit to get in run-time the status of the peripheral
and the data flow.
@endverbatim
* @{
*/
/**
* @brief Return the TIM Hall Sensor interface state
* @param htim : TIM Hall Sensor handle
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
{
return htim- & gt; State;
}
/**
* @}
*/
#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
/* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
/* defined(STM32F105xC) || defined(STM32F107xC) */
/**
* @}
*/
#if defined (STM32F100xB) || defined (STM32F100xE) || \
defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
defined (STM32F105xC) || defined (STM32F107xC)
/** @addtogroup TIMEx_Private_Functions
* @{
*/
/**
* @brief Enables or disables the TIM Capture Compare Channel xN.
* @param TIMx to select the TIM peripheral
* @param Channel : specifies the TIM Channel
* This parameter can be one of the following values:
* @arg TIM_Channel_1: TIM Channel 1
* @arg TIM_Channel_2: TIM Channel 2
* @arg TIM_Channel_3: TIM Channel 3
* @param ChannelNState : specifies the TIM Channel CCxNE bit new state.
* This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
* @retval None
*/
static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
{
uint32_t tmp = 0U;
tmp = TIM_CCER_CC1NE & lt; & lt; Channel;
/* Reset the CCxNE Bit */
TIMx- & gt; CCER & = ~tmp;
/* Set or reset the CCxNE Bit */
TIMx- & gt; CCER |= (uint32_t)(ChannelNState & lt; & lt; Channel);
}
/**
* @}
*/
#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
/* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
/* defined(STM32F105xC) || defined(STM32F107xC) */
#endif /* HAL_TIM_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file stm32f1xx_hal_cortex.c
* @author MCD Application Team
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:
* + Initialization and de-initialization functions
* + Peripheral Control functions
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
*** How to configure Interrupts using CORTEX HAL driver ***
===========================================================
[..]
This section provides functions allowing to configure the NVIC interrupts (IRQ).
The Cortex-M3 exceptions are managed by CMSIS functions.
(#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
function according to the following table.
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
(#) please refer to programming manual for details in how to configure priority.
-@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
The pending IRQ priority will be managed only by the sub priority.
-@- IRQ priority order (sorted by highest to lowest priority):
(+@) Lowest preemption priority
(+@) Lowest sub priority
(+@) Lowest hardware priority (IRQ number)
[..]
*** How to configure Systick using CORTEX HAL driver ***
========================================================
[..]
Setup SysTick Timer for time base.
(+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
is a CMSIS function that:
(++) Configures the SysTick Reload register with value passed as function parameter.
(++) Configures the SysTick IRQ priority to the lowest value 0x0F.
(++) Resets the SysTick Counter register.
(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
(++) Enables the SysTick Interrupt.
(++) Starts the SysTick Counter.
(+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
__HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
inside the stm32f1xx_hal_cortex.h file.
(+) You can change the SysTick IRQ priority by calling the
HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
(+) To adjust the SysTick time base, use the following formula:
Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
(++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
(++) Reload Value should not exceed 0xFFFFFF
@endverbatim
******************************************************************************
* @attention
*
* & lt; h2 & gt; & lt; center & gt; & copy; COPYRIGHT(c) 2017 STMicroelectronics & lt; /center & gt; & lt; /h2 & gt;
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS " AS IS "
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include " stm32f1xx_hal.h "
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @defgroup CORTEX CORTEX
* @brief CORTEX HAL module driver
* @{
*/
#ifdef HAL_CORTEX_MODULE_ENABLED
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
* @{
*/
/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
[..]
This section provides the CORTEX HAL driver functions allowing to configure Interrupts
Systick functionalities
@endverbatim
* @{
*/
/**
* @brief Sets the priority grouping field (preemption priority and subpriority)
* using the required unlock sequence.
* @param PriorityGroup: The priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
* 4 bits for subpriority
* @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
* 3 bits for subpriority
* @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
* 2 bits for subpriority
* @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
* 1 bits for subpriority
* @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
* 0 bits for subpriority
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
}
/**
* @brief Sets the priority of an interrupt.
* @param IRQn: External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xx.h))
* @param PreemptPriority: The preemption priority for the IRQn channel.
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority
* @param SubPriority: the subpriority level for the IRQ channel.
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t prioritygroup = 0x00U;
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
}
/**
* @brief Enables a device specific interrupt in the NVIC interrupt controller.
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
* function should be called before.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
}
/**
* @brief Disables a device specific interrupt in the NVIC interrupt controller.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
* @retval None
*/
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Disable interrupt */
NVIC_DisableIRQ(IRQn);
}
/**
* @brief Initiates a system reset request to reset the MCU.
* @retval None
*/
void HAL_NVIC_SystemReset(void)
{
/* System Reset */
NVIC_SystemReset();
}
/**
* @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
* Counter is in free running mode to generate periodic interrupts.
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
return SysTick_Config(TicksNumb);
}
/**
* @}
*/
/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
* @brief Cortex control functions
*
@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to control the CORTEX
(NVIC, SYSTICK, MPU) functionalities.
@endverbatim
* @{
*/
#if (__MPU_PRESENT == 1U)
/**
* @brief Disables the MPU
* @retval None
*/
void HAL_MPU_Disable(void)
{
/* Make sure outstanding transfers are done */
__DMB();
/* Disable fault exceptions */
SCB- & gt; SHCSR & = ~SCB_SHCSR_MEMFAULTENA_Msk;
/* Disable the MPU and clear the control register*/
MPU- & gt; CTRL = 0U;
}
/**
* @brief Enable the MPU.
* @param MPU_Control: Specifies the control mode of the MPU during hard fault,
* NMI, FAULTMASK and privileged access to the default memory
* This parameter can be one of the following values:
* @arg MPU_HFNMI_PRIVDEF_NONE
* @arg MPU_HARDFAULT_NMI
* @arg MPU_PRIVILEGED_DEFAULT
* @arg MPU_HFNMI_PRIVDEF
* @retval None
*/
void HAL_MPU_Enable(uint32_t MPU_Control)
{
/* Enable the MPU */
MPU- & gt; CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
/* Enable fault exceptions */
SCB- & gt; SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
/* Ensure MPU setting take effects */
__DSB();
__ISB();
}
/**
* @brief Initializes and configures the Region and the memory to be protected.
* @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
* the initialization and configuration information.
* @retval None
*/
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
{
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(MPU_Init- & gt; Number));
assert_param(IS_MPU_REGION_ENABLE(MPU_Init- & gt; Enable));
/* Set the Region number */
MPU- & gt; RNR = MPU_Init- & gt; Number;
if ((MPU_Init- & gt; Enable) != RESET)
{
/* Check the parameters */
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init- & gt; DisableExec));
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init- & gt; AccessPermission));
assert_param(IS_MPU_TEX_LEVEL(MPU_Init- & gt; TypeExtField));
assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init- & gt; IsShareable));
assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init- & gt; IsCacheable));
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init- & gt; IsBufferable));
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init- & gt; SubRegionDisable));
assert_param(IS_MPU_REGION_SIZE(MPU_Init- & gt; Size));
MPU- & gt; RBAR = MPU_Init- & gt; BaseAddress;
MPU- & gt; RASR = ((uint32_t)MPU_Init- & gt; DisableExec & lt; & lt; MPU_RASR_XN_Pos) |
((uint32_t)MPU_Init- & gt; AccessPermission & lt; & lt; MPU_RASR_AP_Pos) |
((uint32_t)MPU_Init- & gt; TypeExtField & lt; & lt; MPU_RASR_TEX_Pos) |
((uint32_t)MPU_Init- & gt; IsShareable & lt; & lt; MPU_RASR_S_Pos) |
((uint32_t)MPU_Init- & gt; IsCacheable & lt; & lt; MPU_RASR_C_Pos) |
((uint32_t)MPU_Init- & gt; IsBufferable & lt; & lt; MPU_RASR_B_Pos) |
((uint32_t)MPU_Init- & gt; SubRegionDisable & lt; & lt; MPU_RASR_SRD_Pos) |
((uint32_t)MPU_Init- & gt; Size & lt; & lt; MPU_RASR_SIZE_Pos) |
((uint32_t)MPU_Init- & gt; Enable & lt; & lt; MPU_RASR_ENABLE_Pos);
}
else
{
MPU- & gt; RBAR = 0x00U;
MPU- & gt; RASR = 0x00U;
}
}
#endif /* __MPU_PRESENT */
/**
* @brief Gets the priority grouping field from the NVIC Interrupt Controller.
* @retval Priority grouping field (SCB- & gt; AIRCR [10:8] PRIGROUP field)
*/
uint32_t HAL_NVIC_GetPriorityGrouping(void)
{
/* Get the PRIGROUP[10:8] field value */
return NVIC_GetPriorityGrouping();
}
/**
* @brief Gets the priority of an interrupt.
* @param IRQn: External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
* @param PriorityGroup: the priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
* 4 bits for subpriority
* @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
* 3 bits for subpriority
* @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
* 2 bits for subpriority
* @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
* 1 bits for subpriority
* @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
* 0 bits for subpriority
* @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
* @param pSubPriority: Pointer on the Subpriority value (starting from 0).
* @retval None
*/
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
{
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Get priority for Cortex-M system or device specific interrupts */
NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
}
/**
* @brief Sets Pending bit of an external interrupt.
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
* @retval None
*/
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Set interrupt pending */
NVIC_SetPendingIRQ(IRQn);
}
/**
* @brief Gets Pending Interrupt (reads the pending register in the NVIC
* and returns the pending bit for the specified interrupt).
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
* @retval status: - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
*/
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Return 1 if pending else 0 */
return NVIC_GetPendingIRQ(IRQn);
}
/**
* @brief Clears the pending bit of an external interrupt.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
* @retval None
*/
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Clear pending interrupt */
NVIC_ClearPendingIRQ(IRQn);
}
/**
* @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
* @retval status: - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
*/
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Return 1 if active else 0 */
return NVIC_GetActive(IRQn);
}
/**
* @brief Configures the SysTick clock source.
* @param CLKSource: specifies the SysTick clock source.
* This parameter can be one of the following values:
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
* @retval None
*/
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
{
/* Check the parameters */
assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
{
SysTick- & gt; CTRL |= SYSTICK_CLKSOURCE_HCLK;
}
else
{
SysTick- & gt; CTRL & = ~SYSTICK_CLKSOURCE_HCLK;
}
}
/**
* @brief This function handles SYSTICK interrupt request.
* @retval None
*/
void HAL_SYSTICK_IRQHandler(void)
{
HAL_SYSTICK_Callback();
}
/**
* @brief SYSTICK callback.
* @retval None
*/
__weak void HAL_SYSTICK_Callback(void)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SYSTICK_Callback could be implemented in the user file
*/
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_CORTEX_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file stm32f1xx_hal.c
* @author MCD Application Team
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The common HAL driver contains a set of generic and common APIs that can be
used by the PPP peripheral drivers and the user to start using the HAL.
[..]
The HAL contains two APIs' categories:
(+) Common HAL APIs
(+) Services HAL APIs
@endverbatim
******************************************************************************
* @attention
*
* & lt; h2 & gt; & lt; center & gt; & copy; COPYRIGHT(c) 2016 STMicroelectronics & lt; /center & gt; & lt; /h2 & gt;
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS " AS IS "
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include " stm32f1xx_hal.h "
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @defgroup HAL HAL
* @brief HAL module driver.
* @{
*/
#ifdef HAL_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup HAL_Private_Constants HAL Private Constants
* @{
*/
/**
* @brief STM32F1xx HAL Driver version number V1.1.2
*/
#define __STM32F1xx_HAL_VERSION_MAIN (0x01U) /*! & lt; [31:24] main version */
#define __STM32F1xx_HAL_VERSION_SUB1 (0x01U) /*! & lt; [23:16] sub1 version */
#define __STM32F1xx_HAL_VERSION_SUB2 (0x02U) /*! & lt; [15:8] sub2 version */
#define __STM32F1xx_HAL_VERSION_RC (0x00U) /*! & lt; [7:0] release candidate */
#define __STM32F1xx_HAL_VERSION ((__STM32F1xx_HAL_VERSION_MAIN & lt; & lt; 24)\
|(__STM32F1xx_HAL_VERSION_SUB1 & lt; & lt; 16)\
|(__STM32F1xx_HAL_VERSION_SUB2 & lt; & lt; 8 )\
|(__STM32F1xx_HAL_VERSION_RC))
#define IDCODE_DEVID_MASK 0x00000FFFU
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup HAL_Private_Variables HAL Private Variables
* @{
*/
__IO uint32_t uwTick;
uint32_t uwTickPrio = (1UL & lt; & lt; __NVIC_PRIO_BITS); /* Invalid PRIO */
HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions ---------------------------------------------------------*/
/** @defgroup HAL_Exported_Functions HAL Exported Functions
* @{
*/
/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
* @brief Initialization and de-initialization functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initializes the Flash interface, the NVIC allocation and initial clock
configuration. It initializes the systick also when timeout is needed
and the backup domain when enabled.
(+) de-Initializes common part of the HAL.
(+) Configure The time base source to have 1ms time base with a dedicated
Tick interrupt priority.
(++) SysTick timer is used by default as source of time base, but user
can eventually implement his proper time base source (a general purpose
timer for example or other time source), keeping in mind that Time base
duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
handled in milliseconds basis.
(++) Time base configuration function (HAL_InitTick ()) is called automatically
at the beginning of the program after reset by HAL_Init() or at any time
when clock is configured, by HAL_RCC_ClockConfig().
(++) Source of time base is configured to generate interrupts at regular
time intervals. Care must be taken if HAL_Delay() is called from a
peripheral ISR process, the Tick interrupt line must have higher priority
(numerically lower) than the peripheral interrupt. Otherwise the caller
ISR process will be blocked.
(++) functions affecting time base configurations are declared as __weak
to make override possible in case of other implementations in user file.
@endverbatim
* @{
*/
/**
* @brief This function is used to initialize the HAL Library; it must be the first
* instruction to be executed in the main program (before to call any other
* HAL function), it performs the following:
* Configure the Flash prefetch.
* Configures the SysTick to generate an interrupt each 1 millisecond,
* which is clocked by the HSI (at this stage, the clock is not yet
* configured and thus the system is running from the internal HSI at 16 MHz).
* Set NVIC Group Priority to 4.
* Calls the HAL_MspInit() callback function defined in user file
* " stm32f1xx_hal_msp.c " to do the global low level hardware initialization
*
* @note SysTick is used as time base for the HAL_Delay() function, the application
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
/* Configure Flash prefetch */
#if (PREFETCH_ENABLE != 0)
#if defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || \
defined(STM32F102x6) || defined(STM32F102xB) || \
defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
defined(STM32F105xC) || defined(STM32F107xC)
/* Prefetch buffer is not available on value line devices */
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
/* Init the low level hardware */
HAL_MspInit();
/* Return function status */
return HAL_OK;
}
/**
* @brief This function de-Initializes common part of the HAL and stops the systick.
* of time base.
* @note This function is optional.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DeInit(void)
{
/* Reset of all peripherals */
__HAL_RCC_APB1_FORCE_RESET();
__HAL_RCC_APB1_RELEASE_RESET();
__HAL_RCC_APB2_FORCE_RESET();
__HAL_RCC_APB2_RELEASE_RESET();
#if defined(STM32F105xC) || defined(STM32F107xC)
__HAL_RCC_AHB_FORCE_RESET();
__HAL_RCC_AHB_RELEASE_RESET();
#endif
/* De-Init the low level hardware */
HAL_MspDeInit();
/* Return function status */
return HAL_OK;
}
/**
* @brief Initialize the MSP.
* @retval None
*/
__weak void HAL_MspInit(void)
{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes the MSP.
* @retval None
*/
__weak void HAL_MspDeInit(void)
{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MspDeInit could be implemented in the user file
*/
}
/**
* @brief This function configures the source of the time base.
* The time source is configured to have 1ms time base with a dedicated
* Tick interrupt priority.
* @note This function is called automatically at the beginning of program after
* reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
* @note In the default implementation, SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals.
* Care must be taken if HAL_Delay() is called from a peripheral ISR process,
* The SysTick interrupt must have higher priority (numerically lower)
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
* The function is declared as __weak to be overwritten in case of other
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) & gt; 0U)
{
return HAL_ERROR;
}
/* Configure the SysTick IRQ priority */
if (TickPriority & lt; (1UL & lt; & lt; __NVIC_PRIO_BITS))
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
uwTickPrio = TickPriority;
}
else
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
* @brief HAL Control functions
*
@verbatim
===============================================================================
##### HAL Control functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Provide a tick value in millisecond
(+) Provide a blocking delay in millisecond
(+) Suspend the time base source interrupt
(+) Resume the time base source interrupt
(+) Get the HAL API driver version
(+) Get the device identifier
(+) Get the device revision identifier
(+) Enable/Disable Debug module during SLEEP mode
(+) Enable/Disable Debug module during STOP mode
(+) Enable/Disable Debug module during STANDBY mode
@endverbatim
* @{
*/
/**
* @brief This function is called to increment a global variable " uwTick "
* used as application time base.
* @note In the default implementation, this variable is incremented each 1ms
* in SysTick ISR.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
uwTick += uwTickFreq;
}
/**
* @brief Provides a tick value in millisecond.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
return uwTick;
}
/**
* @brief This function returns a tick priority.
* @retval tick priority
*/
uint32_t HAL_GetTickPrio(void)
{
return uwTickPrio;
}
/**
* @brief Set new tick Freq.
* @retval Status
*/
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
{
HAL_StatusTypeDef status = HAL_OK;
assert_param(IS_TICKFREQ(Freq));
if (uwTickFreq != Freq)
{
uwTickFreq = Freq;
/* Apply the new tick Freq */
status = HAL_InitTick(uwTickPrio);
}
return status;
}
/**
* @brief Return tick frequency.
* @retval tick period in Hz
*/
HAL_TickFreqTypeDef HAL_GetTickFreq(void)
{
return uwTickFreq;
}
/**
* @brief This function provides minimum delay (in milliseconds) based
* on variable incremented.
* @note In the default implementation , SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals where uwTick
* is incremented.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
uint32_t tickstart = HAL_GetTick();
uint32_t wait = Delay;
/* Add a freq to guarantee minimum wait */
if (wait & lt; HAL_MAX_DELAY)
{
wait += (uint32_t)(uwTickFreq);
}
while ((HAL_GetTick() - tickstart) & lt; wait)
{
}
}
/**
* @brief Suspend Tick increment.
* @note In the default implementation , SysTick timer is the source of time base. It is
* used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
* is called, the SysTick interrupt will be disabled and so Tick increment
* is suspended.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_SuspendTick(void)
{
/* Disable SysTick Interrupt */
CLEAR_BIT(SysTick- & gt; CTRL, SysTick_CTRL_TICKINT_Msk);
}
/**
* @brief Resume Tick increment.
* @note In the default implementation , SysTick timer is the source of time base. It is
* used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
* is called, the SysTick interrupt will be enabled and so Tick increment
* is resumed.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_ResumeTick(void)
{
/* Enable SysTick Interrupt */
SET_BIT(SysTick- & gt; CTRL, SysTick_CTRL_TICKINT_Msk);
}
/**
* @brief Returns the HAL revision
* @retval version 0xXYZR (8bits for each decimal, R for RC)
*/
uint32_t HAL_GetHalVersion(void)
{
return __STM32F1xx_HAL_VERSION;
}
/**
* @brief Returns the device revision identifier.
* Note: On devices STM32F10xx8 and STM32F10xxB,
* STM32F101xC/D/E and STM32F103xC/D/E,
* STM32F101xF/G and STM32F103xF/G
* STM32F10xx4 and STM32F10xx6
* Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
* debug mode (not accessible by the user software in normal mode).
* Refer to errata sheet of these devices for more details.
* @retval Device revision identifier
*/
uint32_t HAL_GetREVID(void)
{
return ((DBGMCU- & gt; IDCODE) & gt; & gt; DBGMCU_IDCODE_REV_ID_Pos);
}
/**
* @brief Returns the device identifier.
* Note: On devices STM32F10xx8 and STM32F10xxB,
* STM32F101xC/D/E and STM32F103xC/D/E,
* STM32F101xF/G and STM32F103xF/G
* STM32F10xx4 and STM32F10xx6
* Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
* debug mode (not accessible by the user software in normal mode).
* Refer to errata sheet of these devices for more details.
* @retval Device identifier
*/
uint32_t HAL_GetDEVID(void)
{
return ((DBGMCU- & gt; IDCODE) & IDCODE_DEVID_MASK);
}
/**
* @brief Enable the Debug Module during SLEEP mode
* @retval None
*/
void HAL_DBGMCU_EnableDBGSleepMode(void)
{
SET_BIT(DBGMCU- & gt; CR, DBGMCU_CR_DBG_SLEEP);
}
/**
* @brief Disable the Debug Module during SLEEP mode
* Note: On devices STM32F10xx8 and STM32F10xxB,
* STM32F101xC/D/E and STM32F103xC/D/E,
* STM32F101xF/G and STM32F103xF/G
* STM32F10xx4 and STM32F10xx6
* Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
* debug mode (not accessible by the user software in normal mode).
* Refer to errata sheet of these devices for more details.
* @retval None
*/
void HAL_DBGMCU_DisableDBGSleepMode(void)
{
CLEAR_BIT(DBGMCU- & gt; CR, DBGMCU_CR_DBG_SLEEP);
}
/**
* @brief Enable the Debug Module during STOP mode
* Note: On devices STM32F10xx8 and STM32F10xxB,
* STM32F101xC/D/E and STM32F103xC/D/E,
* STM32F101xF/G and STM32F103xF/G
* STM32F10xx4 and STM32F10xx6
* Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
* debug mode (not accessible by the user software in normal mode).
* Refer to errata sheet of these devices for more details.
* Note: On all STM32F1 devices:
* If the system tick timer interrupt is enabled during the Stop mode
* debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup
* the system from Stop mode.
* Workaround: To debug the Stop mode, disable the system tick timer
* interrupt.
* Refer to errata sheet of these devices for more details.
* Note: On all STM32F1 devices:
* If the system tick timer interrupt is enabled during the Stop mode
* debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup
* the system from Stop mode.
* Workaround: To debug the Stop mode, disable the system tick timer
* interrupt.
* Refer to errata sheet of these devices for more details.
* @retval None
*/
void HAL_DBGMCU_EnableDBGStopMode(void)
{
SET_BIT(DBGMCU- & gt; CR, DBGMCU_CR_DBG_STOP);
}
/**
* @brief Disable the Debug Module during STOP mode
* Note: On devices STM32F10xx8 and STM32F10xxB,
* STM32F101xC/D/E and STM32F103xC/D/E,
* STM32F101xF/G and STM32F103xF/G
* STM32F10xx4 and STM32F10xx6
* Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
* debug mode (not accessible by the user software in normal mode).
* Refer to errata sheet of these devices for more details.
* @retval None
*/
void HAL_DBGMCU_DisableDBGStopMode(void)
{
CLEAR_BIT(DBGMCU- & gt; CR, DBGMCU_CR_DBG_STOP);
}
/**
* @brief Enable the Debug Module during STANDBY mode
* Note: On devices STM32F10xx8 and STM32F10xxB,
* STM32F101xC/D/E and STM32F103xC/D/E,
* STM32F101xF/G and STM32F103xF/G
* STM32F10xx4 and STM32F10xx6
* Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
* debug mode (not accessible by the user software in normal mode).
* Refer to errata sheet of these devices for more details.
* @retval None
*/
void HAL_DBGMCU_EnableDBGStandbyMode(void)
{
SET_BIT(DBGMCU- & gt; CR, DBGMCU_CR_DBG_STANDBY);
}
/**
* @brief Disable the Debug Module during STANDBY mode
* Note: On devices STM32F10xx8 and STM32F10xxB,
* STM32F101xC/D/E and STM32F103xC/D/E,
* STM32F101xF/G and STM32F103xF/G
* STM32F10xx4 and STM32F10xx6
* Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
* debug mode (not accessible by the user software in normal mode).
* Refer to errata sheet of these devices for more details.
* @retval None
*/
void HAL_DBGMCU_DisableDBGStandbyMode(void)
{
CLEAR_BIT(DBGMCU- & gt; CR, DBGMCU_CR_DBG_STANDBY);
}
/**
* @brief Return the unique device identifier (UID based on 96 bits)
* @param UID pointer to 3 words array.
* @retval Device identifier
*/
void HAL_GetUID(uint32_t *UID)
{
UID[0] = (uint32_t)(READ_REG(*((uint32_t *)UID_BASE)));
UID[1] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
UID[2] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file stm32f1xx_hal_rcc_ex.c
* @author MCD Application Team
* @brief Extended RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities RCC extension peripheral:
* + Extended Peripheral Control functions
*
******************************************************************************
* @attention
*
* & lt; h2 & gt; & lt; center & gt; & copy; COPYRIGHT(c) 2016 STMicroelectronics & lt; /center & gt; & lt; /h2 & gt;
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS " AS IS "
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include " stm32f1xx_hal.h "
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
#ifdef HAL_RCC_MODULE_ENABLED
/** @defgroup RCCEx RCCEx
* @brief RCC Extension HAL module driver.
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
* @{
*/
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
* @{
*/
/** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions
* @brief Extended Peripheral Control functions
*
@verbatim
===============================================================================
##### Extended Peripheral Control functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to control the RCC Clocks
frequencies.
[..]
(@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
select the RTC clock source; in this case the Backup domain will be reset in
order to modify the RTC Clock source, as consequence RTC registers (including
the backup registers) are set to their reset values.
@endverbatim
* @{
*/
/**
* @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
* RCC_PeriphCLKInitTypeDef.
* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
* contains the configuration information for the Extended Peripherals clocks(RTC clock).
*
* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
* the RTC clock source; in this case the Backup domain will be reset in
* order to modify the RTC Clock source, as consequence RTC registers (including
* the backup registers) are set to their reset values.
*
* @note In case of STM32F105xC or STM32F107xC devices, PLLI2S will be enabled if requested on
* one of 2 I2S interfaces. When PLLI2S is enabled, you need to call HAL_RCCEx_DisablePLLI2S to
* manually disable it.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
uint32_t tickstart = 0U, temp_reg = 0U;
#if defined(STM32F105xC) || defined(STM32F107xC)
uint32_t pllactive = 0U;
#endif /* STM32F105xC || STM32F107xC */
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit- & gt; PeriphClockSelection));
/*------------------------------- RTC/LCD Configuration ------------------------*/
if ((((PeriphClkInit- & gt; PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
{
/* check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit- & gt; RTCClockSelection));
FlagStatus pwrclkchanged = RESET;
/* As soon as function is called to change RTC clock source, activation of the
power domain is done. */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
{
__HAL_RCC_PWR_CLK_ENABLE();
pwrclkchanged = SET;
}
if(HAL_IS_BIT_CLR(PWR- & gt; CR, PWR_CR_DBP))
{
/* Enable write access to Backup domain */
SET_BIT(PWR- & gt; CR, PWR_CR_DBP);
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
while(HAL_IS_BIT_CLR(PWR- & gt; CR, PWR_CR_DBP))
{
if((HAL_GetTick() - tickstart) & gt; RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
temp_reg = (RCC- & gt; BDCR & RCC_BDCR_RTCSEL);
if((temp_reg != 0x00000000U) & & (temp_reg != (PeriphClkInit- & gt; RTCClockSelection & RCC_BDCR_RTCSEL)))
{
/* Store the content of BDCR register before the reset of Backup Domain */
temp_reg = (RCC- & gt; BDCR & ~(RCC_BDCR_RTCSEL));
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
__HAL_RCC_BACKUPRESET_RELEASE();
/* Restore the Content of BDCR register */
RCC- & gt; BDCR = temp_reg;
/* Wait for LSERDY if LSE was enabled */
if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
{
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
if((HAL_GetTick() - tickstart) & gt; RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit- & gt; RTCClockSelection);
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
{
__HAL_RCC_PWR_CLK_DISABLE();
}
}
/*------------------------------ ADC clock Configuration ------------------*/
if(((PeriphClkInit- & gt; PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
{
/* Check the parameters */
assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit- & gt; AdcClockSelection));
/* Configure the ADC clock source */
__HAL_RCC_ADC_CONFIG(PeriphClkInit- & gt; AdcClockSelection);
}
#if defined(STM32F105xC) || defined(STM32F107xC)
/*------------------------------ I2S2 Configuration ------------------------*/
if(((PeriphClkInit- & gt; PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2)
{
/* Check the parameters */
assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit- & gt; I2s2ClockSelection));
/* Configure the I2S2 clock source */
__HAL_RCC_I2S2_CONFIG(PeriphClkInit- & gt; I2s2ClockSelection);
}
/*------------------------------ I2S3 Configuration ------------------------*/
if(((PeriphClkInit- & gt; PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3)
{
/* Check the parameters */
assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit- & gt; I2s3ClockSelection));
/* Configure the I2S3 clock source */
__HAL_RCC_I2S3_CONFIG(PeriphClkInit- & gt; I2s3ClockSelection);
}
/*------------------------------ PLL I2S Configuration ----------------------*/
/* Check that PLLI2S need to be enabled */
if (HAL_IS_BIT_SET(RCC- & gt; CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC- & gt; CFGR2, RCC_CFGR2_I2S3SRC))
{
/* Update flag to indicate that PLL I2S should be active */
pllactive = 1;
}
/* Check if PLL I2S need to be enabled */
if (pllactive == 1)
{
/* Enable PLL I2S only if not active */
if (HAL_IS_BIT_CLR(RCC- & gt; CR, RCC_CR_PLL3ON))
{
/* Check the parameters */
assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit- & gt; PLLI2S.PLLI2SMUL));
assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit- & gt; PLLI2S.HSEPrediv2Value));
/* Prediv2 can be written only when the PLL2 is disabled. */
/* Return an error only if new value is different from the programmed value */
if (HAL_IS_BIT_SET(RCC- & gt; CR,RCC_CR_PLL2ON) & & \
(__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit- & gt; PLLI2S.HSEPrediv2Value))
{
return HAL_ERROR;
}
/* Configure the HSE prediv2 factor --------------------------------*/
__HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit- & gt; PLLI2S.HSEPrediv2Value);
/* Configure the main PLLI2S multiplication factors. */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit- & gt; PLLI2S.PLLI2SMUL);
/* Enable the main PLLI2S. */
__HAL_RCC_PLLI2S_ENABLE();
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till PLLI2S is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) & gt; PLLI2S_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
else
{
/* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */
if (READ_BIT(RCC- & gt; CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit- & gt; PLLI2S.PLLI2SMUL)
{
return HAL_ERROR;
}
}
}
#endif /* STM32F105xC || STM32F107xC */
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|| defined(STM32F105xC) || defined(STM32F107xC)
/*------------------------------ USB clock Configuration ------------------*/
if(((PeriphClkInit- & gt; PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
{
/* Check the parameters */
assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit- & gt; UsbClockSelection));
/* Configure the USB clock source */
__HAL_RCC_USB_CONFIG(PeriphClkInit- & gt; UsbClockSelection);
}
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
return HAL_OK;
}
/**
* @brief Get the PeriphClkInit according to the internal
* RCC configuration registers.
* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
* returns the configuration information for the Extended Peripherals clocks(RTC, I2S, ADC clocks).
* @retval None
*/
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
uint32_t srcclk = 0U;
/* Set all possible values for the extended clock type parameter------------*/
PeriphClkInit- & gt; PeriphClockSelection = RCC_PERIPHCLK_RTC;
/* Get the RTC configuration -----------------------------------------------*/
srcclk = __HAL_RCC_GET_RTC_SOURCE();
/* Source clock is LSE or LSI*/
PeriphClkInit- & gt; RTCClockSelection = srcclk;
/* Get the ADC clock configuration -----------------------------------------*/
PeriphClkInit- & gt; PeriphClockSelection |= RCC_PERIPHCLK_ADC;
PeriphClkInit- & gt; AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
#if defined(STM32F105xC) || defined(STM32F107xC)
/* Get the I2S2 clock configuration -----------------------------------------*/
PeriphClkInit- & gt; PeriphClockSelection |= RCC_PERIPHCLK_I2S2;
PeriphClkInit- & gt; I2s2ClockSelection = __HAL_RCC_GET_I2S2_SOURCE();
/* Get the I2S3 clock configuration -----------------------------------------*/
PeriphClkInit- & gt; PeriphClockSelection |= RCC_PERIPHCLK_I2S3;
PeriphClkInit- & gt; I2s3ClockSelection = __HAL_RCC_GET_I2S3_SOURCE();
#endif /* STM32F105xC || STM32F107xC */
#if defined(STM32F103xE) || defined(STM32F103xG)
/* Get the I2S2 clock configuration -----------------------------------------*/
PeriphClkInit- & gt; PeriphClockSelection |= RCC_PERIPHCLK_I2S2;
PeriphClkInit- & gt; I2s2ClockSelection = RCC_I2S2CLKSOURCE_SYSCLK;
/* Get the I2S3 clock configuration -----------------------------------------*/
PeriphClkInit- & gt; PeriphClockSelection |= RCC_PERIPHCLK_I2S3;
PeriphClkInit- & gt; I2s3ClockSelection = RCC_I2S3CLKSOURCE_SYSCLK;
#endif /* STM32F103xE || STM32F103xG */
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|| defined(STM32F105xC) || defined(STM32F107xC)
/* Get the USB clock configuration -----------------------------------------*/
PeriphClkInit- & gt; PeriphClockSelection |= RCC_PERIPHCLK_USB;
PeriphClkInit- & gt; UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
}
/**
* @brief Returns the peripheral clock frequency
* @note Returns 0 if peripheral clock is unknown
* @param PeriphClk Peripheral clock identifier
* This parameter can be one of the following values:
* @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
* @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock
@if STM32F103xE
* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
@endif
@if STM32F103xG
* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
@endif
@if STM32F105xC
* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
@endif
@if STM32F107xC
* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
@endif
@if STM32F102xx
* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
@endif
@if STM32F103xx
* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
@endif
* @retval Frequency in Hz (0: means that no available frequency for the peripheral)
*/
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
#if defined(STM32F105xC) || defined(STM32F107xC)
const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U;
uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U;
#endif /* STM32F105xC || STM32F107xC */
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || \
defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
const uint8_t aPredivFactorTable[2] = {1, 2};
uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U;
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
uint32_t temp_reg = 0U, frequency = 0U;
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
switch (PeriphClk)
{
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|| defined(STM32F105xC) || defined(STM32F107xC)
case RCC_PERIPHCLK_USB:
{
/* Get RCC configuration ------------------------------------------------------*/
temp_reg = RCC- & gt; CFGR;
/* Check if PLL is enabled */
if (HAL_IS_BIT_SET(RCC- & gt; CR,RCC_CR_PLLON))
{
pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) & gt; & gt; RCC_CFGR_PLLMULL_Pos];
if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
{
#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
|| defined(STM32F100xE)
prediv1 = aPredivFactorTable[(uint32_t)(RCC- & gt; CFGR2 & RCC_CFGR2_PREDIV1) & gt; & gt; RCC_CFGR2_PREDIV1_Pos];
#else
prediv1 = aPredivFactorTable[(uint32_t)(RCC- & gt; CFGR & RCC_CFGR_PLLXTPRE) & gt; & gt; RCC_CFGR_PLLXTPRE_Pos];
#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
#if defined(STM32F105xC) || defined(STM32F107xC)
if(HAL_IS_BIT_SET(RCC- & gt; CFGR2, RCC_CFGR2_PREDIV1SRC))
{
/* PLL2 selected as Prediv1 source */
/* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
prediv2 = ((RCC- & gt; CFGR2 & RCC_CFGR2_PREDIV2) & gt; & gt; RCC_CFGR2_PREDIV2_Pos) + 1;
pll2mul = ((RCC- & gt; CFGR2 & RCC_CFGR2_PLL2MUL) & gt; & gt; RCC_CFGR2_PLL2MUL_Pos) + 2;
pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul);
}
else
{
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
}
/* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
/* In this case need to divide pllclk by 2 */
if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) & gt; & gt; RCC_CFGR_PLLMULL_Pos])
{
pllclk = pllclk / 2;
}
#else
if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
{
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
}
#endif /* STM32F105xC || STM32F107xC */
}
else
{
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((HSI_VALUE & gt; & gt; 1) * pllmul);
}
/* Calcul of the USB frequency*/
#if defined(STM32F105xC) || defined(STM32F107xC)
/* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */
if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2)
{
/* Prescaler of 2 selected for USB */
frequency = pllclk;
}
else
{
/* Prescaler of 3 selected for USB */
frequency = (2 * pllclk) / 3;
}
#else
/* USBCLK = PLLCLK / USB prescaler */
if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL)
{
/* No prescaler selected for USB */
frequency = pllclk;
}
else
{
/* Prescaler of 1.5 selected for USB */
frequency = (pllclk * 2) / 3;
}
#endif
}
break;
}
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
case RCC_PERIPHCLK_I2S2:
{
#if defined(STM32F103xE) || defined(STM32F103xG)
/* SYSCLK used as source clock for I2S2 */
frequency = HAL_RCC_GetSysClockFreq();
#else
if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK)
{
/* SYSCLK used as source clock for I2S2 */
frequency = HAL_RCC_GetSysClockFreq();
}
else
{
/* Check if PLLI2S is enabled */
if (HAL_IS_BIT_SET(RCC- & gt; CR, RCC_CR_PLL3ON))
{
/* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
prediv2 = ((RCC- & gt; CFGR2 & RCC_CFGR2_PREDIV2) & gt; & gt; RCC_CFGR2_PREDIV2_Pos) + 1;
pll3mul = ((RCC- & gt; CFGR2 & RCC_CFGR2_PLL3MUL) & gt; & gt; RCC_CFGR2_PLL3MUL_Pos) + 2;
frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
}
}
#endif /* STM32F103xE || STM32F103xG */
break;
}
case RCC_PERIPHCLK_I2S3:
{
#if defined(STM32F103xE) || defined(STM32F103xG)
/* SYSCLK used as source clock for I2S3 */
frequency = HAL_RCC_GetSysClockFreq();
#else
if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK)
{
/* SYSCLK used as source clock for I2S3 */
frequency = HAL_RCC_GetSysClockFreq();
}
else
{
/* Check if PLLI2S is enabled */
if (HAL_IS_BIT_SET(RCC- & gt; CR, RCC_CR_PLL3ON))
{
/* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
prediv2 = ((RCC- & gt; CFGR2 & RCC_CFGR2_PREDIV2) & gt; & gt; RCC_CFGR2_PREDIV2_Pos) + 1;
pll3mul = ((RCC- & gt; CFGR2 & RCC_CFGR2_PLL3MUL) & gt; & gt; RCC_CFGR2_PLL3MUL_Pos) + 2;
frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
}
}
#endif /* STM32F103xE || STM32F103xG */
break;
}
#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
case RCC_PERIPHCLK_RTC:
{
/* Get RCC BDCR configuration ------------------------------------------------------*/
temp_reg = RCC- & gt; BDCR;
/* Check if LSE is ready if RTC clock selection is LSE */
if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) & & (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY)))
{
frequency = LSE_VALUE;
}
/* Check if LSI is ready if RTC clock selection is LSI */
else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) & & (HAL_IS_BIT_SET(RCC- & gt; CSR, RCC_CSR_LSIRDY)))
{
frequency = LSI_VALUE;
}
else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) & & (HAL_IS_BIT_SET(RCC- & gt; CR, RCC_CR_HSERDY)))
{
frequency = HSE_VALUE / 128U;
}
/* Clock not enabled for RTC*/
else
{
frequency = 0U;
}
break;
}
case RCC_PERIPHCLK_ADC:
{
frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() & gt; & gt; RCC_CFGR_ADCPRE_Pos) + 1) * 2);
break;
}
default:
{
break;
}
}
return(frequency);
}
/**
* @}
*/
#if defined(STM32F105xC) || defined(STM32F107xC)
/** @defgroup RCCEx_Exported_Functions_Group2 PLLI2S Management function
* @brief PLLI2S Management functions
*
@verbatim
===============================================================================
##### Extended PLLI2S Management functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to control the PLLI2S
activation or deactivation
@endverbatim
* @{
*/
/**
* @brief Enable PLLI2S
* @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that
* contains the configuration information for the PLLI2S
* @note The PLLI2S configuration not modified if used by I2S2 or I2S3 Interface.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit)
{
uint32_t tickstart = 0U;
/* Check that PLL I2S has not been already enabled by I2S2 or I2S3*/
if (HAL_IS_BIT_CLR(RCC- & gt; CFGR2, RCC_CFGR2_I2S2SRC) & & HAL_IS_BIT_CLR(RCC- & gt; CFGR2, RCC_CFGR2_I2S3SRC))
{
/* Check the parameters */
assert_param(IS_RCC_PLLI2S_MUL(PLLI2SInit- & gt; PLLI2SMUL));
assert_param(IS_RCC_HSE_PREDIV2(PLLI2SInit- & gt; HSEPrediv2Value));
/* Prediv2 can be written only when the PLL2 is disabled. */
/* Return an error only if new value is different from the programmed value */
if (HAL_IS_BIT_SET(RCC- & gt; CR,RCC_CR_PLL2ON) & & \
(__HAL_RCC_HSE_GET_PREDIV2() != PLLI2SInit- & gt; HSEPrediv2Value))
{
return HAL_ERROR;
}
/* Disable the main PLLI2S. */
__HAL_RCC_PLLI2S_DISABLE();
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till PLLI2S is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) & gt; PLLI2S_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Configure the HSE prediv2 factor --------------------------------*/
__HAL_RCC_HSE_PREDIV2_CONFIG(PLLI2SInit- & gt; HSEPrediv2Value);
/* Configure the main PLLI2S multiplication factors. */
__HAL_RCC_PLLI2S_CONFIG(PLLI2SInit- & gt; PLLI2SMUL);
/* Enable the main PLLI2S. */
__HAL_RCC_PLLI2S_ENABLE();
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till PLLI2S is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) & gt; PLLI2S_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
else
{
/* PLLI2S cannot be modified as already used by I2S2 or I2S3 */
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Disable PLLI2S
* @note PLLI2S is not disabled if used by I2S2 or I2S3 Interface.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
{
uint32_t tickstart = 0U;
/* Disable PLL I2S as not requested by I2S2 or I2S3*/
if (HAL_IS_BIT_CLR(RCC- & gt; CFGR2, RCC_CFGR2_I2S2SRC) & & HAL_IS_BIT_CLR(RCC- & gt; CFGR2, RCC_CFGR2_I2S3SRC))
{
/* Disable the main PLLI2S. */
__HAL_RCC_PLLI2S_DISABLE();
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till PLLI2S is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) & gt; PLLI2S_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
else
{
/* PLLI2S is currently used by I2S2 or I2S3. Cannot be disabled.*/
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @}
*/
/** @defgroup RCCEx_Exported_Functions_Group3 PLL2 Management function
* @brief PLL2 Management functions
*
@verbatim
===============================================================================
##### Extended PLL2 Management functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to control the PLL2
activation or deactivation
@endverbatim
* @{
*/
/**
* @brief Enable PLL2
* @param PLL2Init pointer to an RCC_PLL2InitTypeDef structure that
* contains the configuration information for the PLL2
* @note The PLL2 configuration not modified if used indirectly as system clock.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init)
{
uint32_t tickstart = 0U;
/* This bit can not be cleared if the PLL2 clock is used indirectly as system
clock (i.e. it is used as PLL clock entry that is used as system clock). */
if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) & & \
(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) & & \
((READ_BIT(RCC- & gt; CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
{
return HAL_ERROR;
}
else
{
/* Check the parameters */
assert_param(IS_RCC_PLL2_MUL(PLL2Init- & gt; PLL2MUL));
assert_param(IS_RCC_HSE_PREDIV2(PLL2Init- & gt; HSEPrediv2Value));
/* Prediv2 can be written only when the PLLI2S is disabled. */
/* Return an error only if new value is different from the programmed value */
if (HAL_IS_BIT_SET(RCC- & gt; CR,RCC_CR_PLL3ON) & & \
(__HAL_RCC_HSE_GET_PREDIV2() != PLL2Init- & gt; HSEPrediv2Value))
{
return HAL_ERROR;
}
/* Disable the main PLL2. */
__HAL_RCC_PLL2_DISABLE();
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till PLL2 is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
{
if((HAL_GetTick() - tickstart ) & gt; PLL2_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Configure the HSE prediv2 factor --------------------------------*/
__HAL_RCC_HSE_PREDIV2_CONFIG(PLL2Init- & gt; HSEPrediv2Value);
/* Configure the main PLL2 multiplication factors. */
__HAL_RCC_PLL2_CONFIG(PLL2Init- & gt; PLL2MUL);
/* Enable the main PLL2. */
__HAL_RCC_PLL2_ENABLE();
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till PLL2 is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
{
if((HAL_GetTick() - tickstart ) & gt; PLL2_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
return HAL_OK;
}
/**
* @brief Disable PLL2
* @note PLL2 is not disabled if used indirectly as system clock.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void)
{
uint32_t tickstart = 0U;
/* This bit can not be cleared if the PLL2 clock is used indirectly as system
clock (i.e. it is used as PLL clock entry that is used as system clock). */
if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) & & \
(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) & & \
((READ_BIT(RCC- & gt; CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
{
return HAL_ERROR;
}
else
{
/* Disable the main PLL2. */
__HAL_RCC_PLL2_DISABLE();
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till PLL2 is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
{
if((HAL_GetTick() - tickstart ) & gt; PLL2_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
return HAL_OK;
}
/**
* @}
*/
#endif /* STM32F105xC || STM32F107xC */
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_RCC_MODULE_ENABLED */
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file stm32f1xx_hal_flash_ex.c
* @author MCD Application Team
* @brief Extended FLASH HAL module driver.
*
* This file provides firmware functions to manage the following
* functionalities of the FLASH peripheral:
* + Extended Initialization/de-initialization functions
* + Extended I/O operation functions
* + Extended Peripheral Control functions
*
@verbatim
==============================================================================
##### Flash peripheral extended features #####
==============================================================================
##### How to use this driver #####
==============================================================================
[..] This driver provides functions to configure and program the FLASH memory
of all STM32F1xxx devices. It includes
(++) Set/Reset the write protection
(++) Program the user Option Bytes
(++) Get the Read protection Level
@endverbatim
******************************************************************************
* @attention
*
* & lt; h2 & gt; & lt; center & gt; & copy; COPYRIGHT(c) 2016 STMicroelectronics & lt; /center & gt; & lt; /h2 & gt;
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS " AS IS "
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include " stm32f1xx_hal.h "
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
#ifdef HAL_FLASH_MODULE_ENABLED
/** @addtogroup FLASH
* @{
*/
/** @addtogroup FLASH_Private_Variables
* @{
*/
/* Variables used for Erase pages under interruption*/
extern FLASH_ProcessTypeDef pFlash;
/**
* @}
*/
/**
* @}
*/
/** @defgroup FLASHEx FLASHEx
* @brief FLASH HAL Extension module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants
* @{
*/
#define FLASH_POSITION_IWDGSW_BIT FLASH_OBR_IWDG_SW_Pos
#define FLASH_POSITION_OB_USERDATA0_BIT FLASH_OBR_DATA0_Pos
#define FLASH_POSITION_OB_USERDATA1_BIT FLASH_OBR_DATA1_Pos
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
* @{
*/
/* Erase operations */
static void FLASH_MassErase(uint32_t Banks);
void FLASH_PageErase(uint32_t PageAddress);
/* Option bytes control */
static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage);
static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage);
static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel);
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig);
static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data);
static uint32_t FLASH_OB_GetWRP(void);
static uint32_t FLASH_OB_GetRDP(void);
static uint8_t FLASH_OB_GetUser(void);
/**
* @}
*/
/* Exported functions ---------------------------------------------------------*/
/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
* @{
*/
/** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions
* @brief FLASH Memory Erasing functions
*
@verbatim
==============================================================================
##### FLASH Erasing Programming functions #####
==============================================================================
[..] The FLASH Memory Erasing functions, includes the following functions:
(+) @ref HAL_FLASHEx_Erase: return only when erase has been done
(+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback
is called with parameter 0xFFFFFFFF
[..] Any operation of erase should follow these steps:
(#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and
program memory access.
(#) Call the desired function to erase page.
(#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access
(recommended to protect the FLASH memory against possible unwanted operation).
@endverbatim
* @{
*/
/**
* @brief Perform a mass erase or erase the specified FLASH memory pages
* @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
* must be called before.
* Call the @ref HAL_FLASH_Lock() to disable the flash memory access
* (recommended to protect the FLASH memory against possible unwanted operation)
* @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
* contains the configuration information for the erasing.
*
* @param[out] PageError pointer to variable that
* contains the configuration information on faulty page in case of error
* (0xFFFFFFFF means that all the pages have been correctly erased)
*
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
{
HAL_StatusTypeDef status = HAL_ERROR;
uint32_t address = 0U;
/* Process Locked */
__HAL_LOCK( & pFlash);
/* Check the parameters */
assert_param(IS_FLASH_TYPEERASE(pEraseInit- & gt; TypeErase));
if (pEraseInit- & gt; TypeErase == FLASH_TYPEERASE_MASSERASE)
{
#if defined(FLASH_BANK2_END)
if (pEraseInit- & gt; Banks == FLASH_BANK_BOTH)
{
/* Mass Erase requested for Bank1 and Bank2 */
/* Wait for last operation to be completed */
if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) & & \
(FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK))
{
/*Mass erase to be done*/
FLASH_MassErase(FLASH_BANK_BOTH);
/* Wait for last operation to be completed */
if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) & & \
(FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK))
{
status = HAL_OK;
}
/* If the erase operation is completed, disable the MER Bit */
CLEAR_BIT(FLASH- & gt; CR, FLASH_CR_MER);
CLEAR_BIT(FLASH- & gt; CR2, FLASH_CR2_MER);
}
}
else if (pEraseInit- & gt; Banks == FLASH_BANK_2)
{
/* Mass Erase requested for Bank2 */
/* Wait for last operation to be completed */
if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
{
/*Mass erase to be done*/
FLASH_MassErase(FLASH_BANK_2);
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE);
/* If the erase operation is completed, disable the MER Bit */
CLEAR_BIT(FLASH- & gt; CR2, FLASH_CR2_MER);
}
}
else
#endif /* FLASH_BANK2_END */
{
/* Mass Erase requested for Bank1 */
/* Wait for last operation to be completed */
if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
{
/*Mass erase to be done*/
FLASH_MassErase(FLASH_BANK_1);
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
/* If the erase operation is completed, disable the MER Bit */
CLEAR_BIT(FLASH- & gt; CR, FLASH_CR_MER);
}
}
}
else
{
/* Page Erase is requested */
/* Check the parameters */
assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit- & gt; PageAddress));
assert_param(IS_FLASH_NB_PAGES(pEraseInit- & gt; PageAddress, pEraseInit- & gt; NbPages));
#if defined(FLASH_BANK2_END)
/* Page Erase requested on address located on bank2 */
if(pEraseInit- & gt; PageAddress & gt; FLASH_BANK1_END)
{
/* Wait for last operation to be completed */
if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
{
/*Initialization of PageError variable*/
*PageError = 0xFFFFFFFFU;
/* Erase by page by page to be done*/
for(address = pEraseInit- & gt; PageAddress;
address & lt; (pEraseInit- & gt; PageAddress + (pEraseInit- & gt; NbPages)*FLASH_PAGE_SIZE);
address += FLASH_PAGE_SIZE)
{
FLASH_PageErase(address);
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE);
/* If the erase operation is completed, disable the PER Bit */
CLEAR_BIT(FLASH- & gt; CR2, FLASH_CR2_PER);
if (status != HAL_OK)
{
/* In case of error, stop erase procedure and return the faulty address */
*PageError = address;
break;
}
}
}
}
else
#endif /* FLASH_BANK2_END */
{
/* Page Erase requested on address located on bank1 */
/* Wait for last operation to be completed */
if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
{
/*Initialization of PageError variable*/
*PageError = 0xFFFFFFFFU;
/* Erase page by page to be done*/
for(address = pEraseInit- & gt; PageAddress;
address & lt; ((pEraseInit- & gt; NbPages * FLASH_PAGE_SIZE) + pEraseInit- & gt; PageAddress);
address += FLASH_PAGE_SIZE)
{
FLASH_PageErase(address);
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
/* If the erase operation is completed, disable the PER Bit */
CLEAR_BIT(FLASH- & gt; CR, FLASH_CR_PER);
if (status != HAL_OK)
{
/* In case of error, stop erase procedure and return the faulty address */
*PageError = address;
break;
}
}
}
}
}
/* Process Unlocked */
__HAL_UNLOCK( & pFlash);
return status;
}
/**
* @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled
* @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
* must be called before.
* Call the @ref HAL_FLASH_Lock() to disable the flash memory access
* (recommended to protect the FLASH memory against possible unwanted operation)
* @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
* contains the configuration information for the erasing.
*
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process Locked */
__HAL_LOCK( & pFlash);
/* If procedure already ongoing, reject the next one */
if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_FLASH_TYPEERASE(pEraseInit- & gt; TypeErase));
/* Enable End of FLASH Operation and Error source interrupts */
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
#if defined(FLASH_BANK2_END)
/* Enable End of FLASH Operation and Error source interrupts */
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2);
#endif
if (pEraseInit- & gt; TypeErase == FLASH_TYPEERASE_MASSERASE)
{
/*Mass erase to be done*/
pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
FLASH_MassErase(pEraseInit- & gt; Banks);
}
else
{
/* Erase by page to be done*/
/* Check the parameters */
assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit- & gt; PageAddress));
assert_param(IS_FLASH_NB_PAGES(pEraseInit- & gt; PageAddress, pEraseInit- & gt; NbPages));
pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE;
pFlash.DataRemaining = pEraseInit- & gt; NbPages;
pFlash.Address = pEraseInit- & gt; PageAddress;
/*Erase 1st page and wait for IT*/
FLASH_PageErase(pEraseInit- & gt; PageAddress);
}
return status;
}
/**
* @}
*/
/** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions
* @brief Option Bytes Programming functions
*
@verbatim
==============================================================================
##### Option Bytes Programming functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to control the FLASH
option bytes operations.
@endverbatim
* @{
*/
/**
* @brief Erases the FLASH option bytes.
* @note This functions erases all option bytes except the Read protection (RDP).
* The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
* The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
* The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
* (system reset will occur)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FLASHEx_OBErase(void)
{
uint8_t rdptmp = OB_RDP_LEVEL_0;
HAL_StatusTypeDef status = HAL_ERROR;
/* Get the actual read protection Option Byte value */
rdptmp = FLASH_OB_GetRDP();
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* If the previous operation is completed, proceed to erase the option bytes */
SET_BIT(FLASH- & gt; CR, FLASH_CR_OPTER);
SET_BIT(FLASH- & gt; CR, FLASH_CR_STRT);
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
/* If the erase operation is completed, disable the OPTER Bit */
CLEAR_BIT(FLASH- & gt; CR, FLASH_CR_OPTER);
if(status == HAL_OK)
{
/* Restore the last read protection Option Byte value */
status = FLASH_OB_RDP_LevelConfig(rdptmp);
}
}
/* Return the erase status */
return status;
}
/**
* @brief Program option bytes
* @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
* The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
* The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
* (system reset will occur)
*
* @param pOBInit pointer to an FLASH_OBInitStruct structure that
* contains the configuration information for the programming.
*
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
{
HAL_StatusTypeDef status = HAL_ERROR;
/* Process Locked */
__HAL_LOCK( & pFlash);
/* Check the parameters */
assert_param(IS_OPTIONBYTE(pOBInit- & gt; OptionType));
/* Write protection configuration */
if((pOBInit- & gt; OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
{
assert_param(IS_WRPSTATE(pOBInit- & gt; WRPState));
if (pOBInit- & gt; WRPState == OB_WRPSTATE_ENABLE)
{
/* Enable of Write protection on the selected page */
status = FLASH_OB_EnableWRP(pOBInit- & gt; WRPPage);
}
else
{
/* Disable of Write protection on the selected page */
status = FLASH_OB_DisableWRP(pOBInit- & gt; WRPPage);
}
if (status != HAL_OK)
{
/* Process Unlocked */
__HAL_UNLOCK( & pFlash);
return status;
}
}
/* Read protection configuration */
if((pOBInit- & gt; OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
{
status = FLASH_OB_RDP_LevelConfig(pOBInit- & gt; RDPLevel);
if (status != HAL_OK)
{
/* Process Unlocked */
__HAL_UNLOCK( & pFlash);
return status;
}
}
/* USER configuration */
if((pOBInit- & gt; OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
{
status = FLASH_OB_UserConfig(pOBInit- & gt; USERConfig);
if (status != HAL_OK)
{
/* Process Unlocked */
__HAL_UNLOCK( & pFlash);
return status;
}
}
/* DATA configuration*/
if((pOBInit- & gt; OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA)
{
status = FLASH_OB_ProgramData(pOBInit- & gt; DATAAddress, pOBInit- & gt; DATAData);
if (status != HAL_OK)
{
/* Process Unlocked */
__HAL_UNLOCK( & pFlash);
return status;
}
}
/* Process Unlocked */
__HAL_UNLOCK( & pFlash);
return status;
}
/**
* @brief Get the Option byte configuration
* @param pOBInit pointer to an FLASH_OBInitStruct structure that
* contains the configuration information for the programming.
*
* @retval None
*/
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
{
pOBInit- & gt; OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER;
/*Get WRP*/
pOBInit- & gt; WRPPage = FLASH_OB_GetWRP();
/*Get RDP Level*/
pOBInit- & gt; RDPLevel = FLASH_OB_GetRDP();
/*Get USER*/
pOBInit- & gt; USERConfig = FLASH_OB_GetUser();
}
/**
* @brief Get the Option byte user data
* @param DATAAdress Address of the option byte DATA
* This parameter can be one of the following values:
* @arg @ref OB_DATA_ADDRESS_DATA0
* @arg @ref OB_DATA_ADDRESS_DATA1
* @retval Value programmed in USER data
*/
uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress)
{
uint32_t value = 0;
if (DATAAdress == OB_DATA_ADDRESS_DATA0)
{
/* Get value programmed in OB USER Data0 */
value = READ_BIT(FLASH- & gt; OBR, FLASH_OBR_DATA0) & gt; & gt; FLASH_POSITION_OB_USERDATA0_BIT;
}
else
{
/* Get value programmed in OB USER Data1 */
value = READ_BIT(FLASH- & gt; OBR, FLASH_OBR_DATA1) & gt; & gt; FLASH_POSITION_OB_USERDATA1_BIT;
}
return value;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup FLASHEx_Private_Functions
* @{
*/
/**
* @brief Full erase of FLASH memory Bank
* @param Banks Banks to be erased
* This parameter can be one of the following values:
* @arg @ref FLASH_BANK_1 Bank1 to be erased
@if STM32F101xG
* @arg @ref FLASH_BANK_2 Bank2 to be erased
* @arg @ref FLASH_BANK_BOTH Bank1 and Bank2 to be erased
@endif
@if STM32F103xG
* @arg @ref FLASH_BANK_2 Bank2 to be erased
* @arg @ref FLASH_BANK_BOTH Bank1 and Bank2 to be erased
@endif
*
* @retval None
*/
static void FLASH_MassErase(uint32_t Banks)
{
/* Check the parameters */
assert_param(IS_FLASH_BANK(Banks));
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
#if defined(FLASH_BANK2_END)
if(Banks == FLASH_BANK_BOTH)
{
/* bank1 & bank2 will be erased*/
SET_BIT(FLASH- & gt; CR, FLASH_CR_MER);
SET_BIT(FLASH- & gt; CR2, FLASH_CR2_MER);
SET_BIT(FLASH- & gt; CR, FLASH_CR_STRT);
SET_BIT(FLASH- & gt; CR2, FLASH_CR2_STRT);
}
else if(Banks == FLASH_BANK_2)
{
/*Only bank2 will be erased*/
SET_BIT(FLASH- & gt; CR2, FLASH_CR2_MER);
SET_BIT(FLASH- & gt; CR2, FLASH_CR2_STRT);
}
else
{
#endif /* FLASH_BANK2_END */
#if !defined(FLASH_BANK2_END)
/* Prevent unused argument(s) compilation warning */
UNUSED(Banks);
#endif /* FLASH_BANK2_END */
/* Only bank1 will be erased*/
SET_BIT(FLASH- & gt; CR, FLASH_CR_MER);
SET_BIT(FLASH- & gt; CR, FLASH_CR_STRT);
#if defined(FLASH_BANK2_END)
}
#endif /* FLASH_BANK2_END */
}
/**
* @brief Enable the write protection of the desired pages
* @note An option byte erase is done automatically in this function.
* @note When the memory read protection level is selected (RDP level = 1),
* it is not possible to program or erase the flash page i if
* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
*
* @param WriteProtectPage specifies the page(s) to be write protected.
* The value of this parameter depend on device used within the same series
* @retval HAL status
*/
static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
{
HAL_StatusTypeDef status = HAL_OK;
uint16_t WRP0_Data = 0xFFFF;
#if defined(FLASH_WRP1_WRP1)
uint16_t WRP1_Data = 0xFFFF;
#endif /* FLASH_WRP1_WRP1 */
#if defined(FLASH_WRP2_WRP2)
uint16_t WRP2_Data = 0xFFFF;
#endif /* FLASH_WRP2_WRP2 */
#if defined(FLASH_WRP3_WRP3)
uint16_t WRP3_Data = 0xFFFF;
#endif /* FLASH_WRP3_WRP3 */
/* Check the parameters */
assert_param(IS_OB_WRP(WriteProtectPage));
/* Get current write protected pages and the new pages to be protected ******/
WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage));
#if defined(OB_WRP_PAGES0TO15MASK)
WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
#elif defined(OB_WRP_PAGES0TO31MASK)
WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK);
#endif /* OB_WRP_PAGES0TO31MASK */
#if defined(OB_WRP_PAGES16TO31MASK)
WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) & gt; & gt; 8U);
#elif defined(OB_WRP_PAGES32TO63MASK)
WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) & gt; & gt; 8U);
#endif /* OB_WRP_PAGES32TO63MASK */
#if defined(OB_WRP_PAGES64TO95MASK)
WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) & gt; & gt; 16U);
#endif /* OB_WRP_PAGES64TO95MASK */
#if defined(OB_WRP_PAGES32TO47MASK)
WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) & gt; & gt; 16U);
#endif /* OB_WRP_PAGES32TO47MASK */
#if defined(OB_WRP_PAGES96TO127MASK)
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) & gt; & gt; 24U);
#elif defined(OB_WRP_PAGES48TO255MASK)
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) & gt; & gt; 24U);
#elif defined(OB_WRP_PAGES48TO511MASK)
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) & gt; & gt; 24U);
#elif defined(OB_WRP_PAGES48TO127MASK)
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) & gt; & gt; 24U);
#endif /* OB_WRP_PAGES96TO127MASK */
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* To be able to write again option byte, need to perform a option byte erase */
status = HAL_FLASHEx_OBErase();
if (status == HAL_OK)
{
/* Enable write protection */
SET_BIT(FLASH- & gt; CR, FLASH_CR_OPTPG);
#if defined(FLASH_WRP0_WRP0)
if(WRP0_Data != 0xFFU)
{
OB- & gt; WRP0 & = WRP0_Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
}
#endif /* FLASH_WRP0_WRP0 */
#if defined(FLASH_WRP1_WRP1)
if((status == HAL_OK) & & (WRP1_Data != 0xFFU))
{
OB- & gt; WRP1 & = WRP1_Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
}
#endif /* FLASH_WRP1_WRP1 */
#if defined(FLASH_WRP2_WRP2)
if((status == HAL_OK) & & (WRP2_Data != 0xFFU))
{
OB- & gt; WRP2 & = WRP2_Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
}
#endif /* FLASH_WRP2_WRP2 */
#if defined(FLASH_WRP3_WRP3)
if((status == HAL_OK) & & (WRP3_Data != 0xFFU))
{
OB- & gt; WRP3 & = WRP3_Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
}
#endif /* FLASH_WRP3_WRP3 */
/* if the program operation is completed, disable the OPTPG Bit */
CLEAR_BIT(FLASH- & gt; CR, FLASH_CR_OPTPG);
}
}
return status;
}
/**
* @brief Disable the write protection of the desired pages
* @note An option byte erase is done automatically in this function.
* @note When the memory read protection level is selected (RDP level = 1),
* it is not possible to program or erase the flash page i if
* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
*
* @param WriteProtectPage specifies the page(s) to be write unprotected.
* The value of this parameter depend on device used within the same series
* @retval HAL status
*/
static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
{
HAL_StatusTypeDef status = HAL_OK;
uint16_t WRP0_Data = 0xFFFF;
#if defined(FLASH_WRP1_WRP1)
uint16_t WRP1_Data = 0xFFFF;
#endif /* FLASH_WRP1_WRP1 */
#if defined(FLASH_WRP2_WRP2)
uint16_t WRP2_Data = 0xFFFF;
#endif /* FLASH_WRP2_WRP2 */
#if defined(FLASH_WRP3_WRP3)
uint16_t WRP3_Data = 0xFFFF;
#endif /* FLASH_WRP3_WRP3 */
/* Check the parameters */
assert_param(IS_OB_WRP(WriteProtectPage));
/* Get current write protected pages and the new pages to be unprotected ******/
WriteProtectPage = (FLASH_OB_GetWRP() | WriteProtectPage);
#if defined(OB_WRP_PAGES0TO15MASK)
WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
#elif defined(OB_WRP_PAGES0TO31MASK)
WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK);
#endif /* OB_WRP_PAGES0TO31MASK */
#if defined(OB_WRP_PAGES16TO31MASK)
WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) & gt; & gt; 8U);
#elif defined(OB_WRP_PAGES32TO63MASK)
WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) & gt; & gt; 8U);
#endif /* OB_WRP_PAGES32TO63MASK */
#if defined(OB_WRP_PAGES64TO95MASK)
WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) & gt; & gt; 16U);
#endif /* OB_WRP_PAGES64TO95MASK */
#if defined(OB_WRP_PAGES32TO47MASK)
WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) & gt; & gt; 16U);
#endif /* OB_WRP_PAGES32TO47MASK */
#if defined(OB_WRP_PAGES96TO127MASK)
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) & gt; & gt; 24U);
#elif defined(OB_WRP_PAGES48TO255MASK)
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) & gt; & gt; 24U);
#elif defined(OB_WRP_PAGES48TO511MASK)
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) & gt; & gt; 24U);
#elif defined(OB_WRP_PAGES48TO127MASK)
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) & gt; & gt; 24U);
#endif /* OB_WRP_PAGES96TO127MASK */
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* To be able to write again option byte, need to perform a option byte erase */
status = HAL_FLASHEx_OBErase();
if (status == HAL_OK)
{
SET_BIT(FLASH- & gt; CR, FLASH_CR_OPTPG);
#if defined(FLASH_WRP0_WRP0)
if(WRP0_Data != 0xFFU)
{
OB- & gt; WRP0 |= WRP0_Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
}
#endif /* FLASH_WRP0_WRP0 */
#if defined(FLASH_WRP1_WRP1)
if((status == HAL_OK) & & (WRP1_Data != 0xFFU))
{
OB- & gt; WRP1 |= WRP1_Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
}
#endif /* FLASH_WRP1_WRP1 */
#if defined(FLASH_WRP2_WRP2)
if((status == HAL_OK) & & (WRP2_Data != 0xFFU))
{
OB- & gt; WRP2 |= WRP2_Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
}
#endif /* FLASH_WRP2_WRP2 */
#if defined(FLASH_WRP3_WRP3)
if((status == HAL_OK) & & (WRP3_Data != 0xFFU))
{
OB- & gt; WRP3 |= WRP3_Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
}
#endif /* FLASH_WRP3_WRP3 */
/* if the program operation is completed, disable the OPTPG Bit */
CLEAR_BIT(FLASH- & gt; CR, FLASH_CR_OPTPG);
}
}
return status;
}
/**
* @brief Set the read protection level.
* @param ReadProtectLevel specifies the read protection level.
* This parameter can be one of the following values:
* @arg @ref OB_RDP_LEVEL_0 No protection
* @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
* @retval HAL status
*/
static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel));
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* If the previous operation is completed, proceed to erase the option bytes */
SET_BIT(FLASH- & gt; CR, FLASH_CR_OPTER);
SET_BIT(FLASH- & gt; CR, FLASH_CR_STRT);
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
/* If the erase operation is completed, disable the OPTER Bit */
CLEAR_BIT(FLASH- & gt; CR, FLASH_CR_OPTER);
if(status == HAL_OK)
{
/* Enable the Option Bytes Programming operation */
SET_BIT(FLASH- & gt; CR, FLASH_CR_OPTPG);
WRITE_REG(OB- & gt; RDP, ReadProtectLevel);
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
/* if the program operation is completed, disable the OPTPG Bit */
CLEAR_BIT(FLASH- & gt; CR, FLASH_CR_OPTPG);
}
}
return status;
}
/**
* @brief Program the FLASH User Option Byte.
* @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
* @param UserConfig The FLASH User Option Bytes values FLASH_OBR_IWDG_SW(Bit2),
* FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4).
* And BFBF2(Bit5) for STM32F101xG and STM32F103xG .
* @retval HAL status
*/
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_OB_IWDG_SOURCE((UserConfig & OB_IWDG_SW)));
assert_param(IS_OB_STOP_SOURCE((UserConfig & OB_STOP_NO_RST)));
assert_param(IS_OB_STDBY_SOURCE((UserConfig & OB_STDBY_NO_RST)));
#if defined(FLASH_BANK2_END)
assert_param(IS_OB_BOOT1((UserConfig & OB_BOOT1_SET)));
#endif /* FLASH_BANK2_END */
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* Enable the Option Bytes Programming operation */
SET_BIT(FLASH- & gt; CR, FLASH_CR_OPTPG);
#if defined(FLASH_BANK2_END)
OB- & gt; USER = (UserConfig | 0xF0U);
#else
OB- & gt; USER = (UserConfig | 0x88U);
#endif /* FLASH_BANK2_END */
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
/* if the program operation is completed, disable the OPTPG Bit */
CLEAR_BIT(FLASH- & gt; CR, FLASH_CR_OPTPG);
}
return status;
}
/**
* @brief Programs a half word at a specified Option Byte Data address.
* @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
* The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
* The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
* (system reset will occur)
* Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
* @param Address specifies the address to be programmed.
* This parameter can be 0x1FFFF804 or 0x1FFFF806.
* @param Data specifies the data to be programmed.
* @retval HAL status
*/
static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data)
{
HAL_StatusTypeDef status = HAL_ERROR;
/* Check the parameters */
assert_param(IS_OB_DATA_ADDRESS(Address));
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* Enables the Option Bytes Programming operation */
SET_BIT(FLASH- & gt; CR, FLASH_CR_OPTPG);
*(__IO uint16_t*)Address = Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
/* If the program operation is completed, disable the OPTPG Bit */
CLEAR_BIT(FLASH- & gt; CR, FLASH_CR_OPTPG);
}
/* Return the Option Byte Data Program Status */
return status;
}
/**
* @brief Return the FLASH Write Protection Option Bytes value.
* @retval The FLASH Write Protection Option Bytes value
*/
static uint32_t FLASH_OB_GetWRP(void)
{
/* Return the FLASH write protection Register value */
return (uint32_t)(READ_REG(FLASH- & gt; WRPR));
}
/**
* @brief Returns the FLASH Read Protection level.
* @retval FLASH RDP level
* This parameter can be one of the following values:
* @arg @ref OB_RDP_LEVEL_0 No protection
* @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
*/
static uint32_t FLASH_OB_GetRDP(void)
{
uint32_t readstatus = OB_RDP_LEVEL_0;
uint32_t tmp_reg = 0U;
/* Read RDP level bits */
tmp_reg = READ_BIT(FLASH- & gt; OBR, FLASH_OBR_RDPRT);
if (tmp_reg == FLASH_OBR_RDPRT)
{
readstatus = OB_RDP_LEVEL_1;
}
else
{
readstatus = OB_RDP_LEVEL_0;
}
return readstatus;
}
/**
* @brief Return the FLASH User Option Byte value.
* @retval The FLASH User Option Bytes values: FLASH_OBR_IWDG_SW(Bit2),
* FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4).
* And FLASH_OBR_BFB2(Bit5) for STM32F101xG and STM32F103xG .
*/
static uint8_t FLASH_OB_GetUser(void)
{
/* Return the User Option Byte */
return (uint8_t)((READ_REG(FLASH- & gt; OBR) & FLASH_OBR_USER) & gt; & gt; FLASH_POSITION_IWDGSW_BIT);
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup FLASH
* @{
*/
/** @addtogroup FLASH_Private_Functions
* @{
*/
/**
* @brief Erase the specified FLASH memory page
* @param PageAddress FLASH page to erase
* The value of this parameter depend on device used within the same series
*
* @retval None
*/
void FLASH_PageErase(uint32_t PageAddress)
{
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
#if defined(FLASH_BANK2_END)
if(PageAddress & gt; FLASH_BANK1_END)
{
/* Proceed to erase the page */
SET_BIT(FLASH- & gt; CR2, FLASH_CR2_PER);
WRITE_REG(FLASH- & gt; AR2, PageAddress);
SET_BIT(FLASH- & gt; CR2, FLASH_CR2_STRT);
}
else
{
#endif /* FLASH_BANK2_END */
/* Proceed to erase the page */
SET_BIT(FLASH- & gt; CR, FLASH_CR_PER);
WRITE_REG(FLASH- & gt; AR, PageAddress);
SET_BIT(FLASH- & gt; CR, FLASH_CR_STRT);
#if defined(FLASH_BANK2_END)
}
#endif /* FLASH_BANK2_END */
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_FLASH_MODULE_ENABLED */
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file stm32f1xx_hal_flash.c
* @author MCD Application Team
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
* + Program operations functions
* + Memory Control functions
* + Peripheral State functions
*
@verbatim
==============================================================================
##### FLASH peripheral features #####
==============================================================================
[..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
to the Flash memory. It implements the erase and program Flash memory operations
and the read and write protection mechanisms.
[..] The Flash memory interface accelerates code execution with a system of instruction
prefetch.
[..] The FLASH main features are:
(+) Flash memory read operations
(+) Flash memory program/erase operations
(+) Read / write protections
(+) Prefetch on I-Code
(+) Option Bytes programming
##### How to use this driver #####
==============================================================================
[..]
This driver provides functions and macros to configure and program the FLASH
memory of all STM32F1xx devices.
(#) FLASH Memory I/O Programming functions: this group includes all needed
functions to erase and program the main memory:
(++) Lock and Unlock the FLASH interface
(++) Erase function: Erase page, erase all pages
(++) Program functions: half word, word and doubleword
(#) FLASH Option Bytes Programming functions: this group includes all needed
functions to manage the Option Bytes:
(++) Lock and Unlock the Option Bytes
(++) Set/Reset the write protection
(++) Set the Read protection Level
(++) Program the user Option Bytes
(++) Launch the Option Bytes loader
(++) Erase Option Bytes
(++) Program the data Option Bytes
(++) Get the Write protection.
(++) Get the user option bytes.
(#) Interrupts and flags management functions : this group
includes all needed functions to:
(++) Handle FLASH interrupts
(++) Wait for last FLASH operation according to its status
(++) Get error flag status
[..] In addition to these function, this driver includes a set of macros allowing
to handle the following operations:
(+) Set/Get the latency
(+) Enable/Disable the prefetch buffer
(+) Enable/Disable the half cycle access
(+) Enable/Disable the FLASH interrupts
(+) Monitor the FLASH flags status
@endverbatim
******************************************************************************
* @attention
*
* & lt; h2 & gt; & lt; center & gt; & copy; COPYRIGHT(c) 2016 STMicroelectronics & lt; /center & gt; & lt; /h2 & gt;
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS " AS IS "
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include " stm32f1xx_hal.h "
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
#ifdef HAL_FLASH_MODULE_ENABLED
/** @defgroup FLASH FLASH
* @brief FLASH HAL module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup FLASH_Private_Constants FLASH Private Constants
* @{
*/
/**
* @}
*/
/* Private macro ---------------------------- ---------------------------------*/
/** @defgroup FLASH_Private_Macros FLASH Private Macros
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup FLASH_Private_Variables FLASH Private Variables
* @{
*/
/* Variables used for Erase pages under interruption*/
FLASH_ProcessTypeDef pFlash;
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup FLASH_Private_Functions FLASH Private Functions
* @{
*/
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
static void FLASH_SetErrorCode(void);
extern void FLASH_PageErase(uint32_t PageAddress);
/**
* @}
*/
/* Exported functions ---------------------------------------------------------*/
/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
* @{
*/
/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
* @brief Programming operation functions
*
@verbatim
@endverbatim
* @{
*/
/**
* @brief Program halfword, word or double word at a specified address
* @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
* The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
*
* @note If an erase and a program operations are requested simultaneously,
* the erase operation is performed before the program one.
*
* @note FLASH should be previously erased before new programmation (only exception to this
* is when 0x0000 is programmed)
*
* @param TypeProgram: Indicate the way to program at a specified address.
* This parameter can be a value of @ref FLASH_Type_Program
* @param Address: Specifies the address to be programmed.
* @param Data: Specifies the data to be programmed
*
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
{
HAL_StatusTypeDef status = HAL_ERROR;
uint8_t index = 0;
uint8_t nbiterations = 0;
/* Process Locked */
__HAL_LOCK( & pFlash);
/* Check the parameters */
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
#if defined(FLASH_BANK2_END)
if(Address & lt; = FLASH_BANK1_END)
{
#endif /* FLASH_BANK2_END */
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
#if defined(FLASH_BANK2_END)
}
else
{
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE);
}
#endif /* FLASH_BANK2_END */
if(status == HAL_OK)
{
if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
{
/* Program halfword (16-bit) at a specified address. */
nbiterations = 1U;
}
else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
{
/* Program word (32-bit = 2*16-bit) at a specified address. */
nbiterations = 2U;
}
else
{
/* Program double word (64-bit = 4*16-bit) at a specified address. */
nbiterations = 4U;
}
for (index = 0U; index & lt; nbiterations; index++)
{
FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data & gt; & gt; (16U*index)));
#if defined(FLASH_BANK2_END)
if(Address & lt; = FLASH_BANK1_END)
{
#endif /* FLASH_BANK2_END */
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
/* If the program operation is completed, disable the PG Bit */
CLEAR_BIT(FLASH- & gt; CR, FLASH_CR_PG);
#if defined(FLASH_BANK2_END)
}
else
{
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE);
/* If the program operation is completed, disable the PG Bit */
CLEAR_BIT(FLASH- & gt; CR2, FLASH_CR2_PG);
}
#endif /* FLASH_BANK2_END */
/* In case of error, stop programation procedure */
if (status != HAL_OK)
{
break;
}
}
}
/* Process Unlocked */
__HAL_UNLOCK( & pFlash);
return status;
}
/**
* @brief Program halfword, word or double word at a specified address with interrupt enabled.
* @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
* The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
*
* @note If an erase and a program operations are requested simultaneously,
* the erase operation is performed before the program one.
*
* @param TypeProgram: Indicate the way to program at a specified address.
* This parameter can be a value of @ref FLASH_Type_Program
* @param Address: Specifies the address to be programmed.
* @param Data: Specifies the data to be programmed
*
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process Locked */
__HAL_LOCK( & pFlash);
/* Check the parameters */
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
#if defined(FLASH_BANK2_END)
/* If procedure already ongoing, reject the next one */
if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
{
return HAL_ERROR;
}
if(Address & lt; = FLASH_BANK1_END)
{
/* Enable End of FLASH Operation and Error source interrupts */
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1);
}else
{
/* Enable End of FLASH Operation and Error source interrupts */
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2);
}
#else
/* Enable End of FLASH Operation and Error source interrupts */
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
#endif /* FLASH_BANK2_END */
pFlash.Address = Address;
pFlash.Data = Data;
if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
{
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD;
/* Program halfword (16-bit) at a specified address. */
pFlash.DataRemaining = 1U;
}
else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
{
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD;
/* Program word (32-bit : 2*16-bit) at a specified address. */
pFlash.DataRemaining = 2U;
}
else
{
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD;
/* Program double word (64-bit : 4*16-bit) at a specified address. */
pFlash.DataRemaining = 4U;
}
/* Program halfword (16-bit) at a specified address. */
FLASH_Program_HalfWord(Address, (uint16_t)Data);
return status;
}
/**
* @brief This function handles FLASH interrupt request.
* @retval None
*/
void HAL_FLASH_IRQHandler(void)
{
uint32_t addresstmp = 0U;
/* Check FLASH operation error flags */
#if defined(FLASH_BANK2_END)
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK1) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK1) || \
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)))
#else
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
#endif /* FLASH_BANK2_END */
{
/* Return the faulty address */
addresstmp = pFlash.Address;
/* Reset address */
pFlash.Address = 0xFFFFFFFFU;
/* Save the Error code */
FLASH_SetErrorCode();
/* FLASH error interrupt user callback */
HAL_FLASH_OperationErrorCallback(addresstmp);
/* Stop the procedure ongoing */
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
}
/* Check FLASH End of Operation flag */
#if defined(FLASH_BANK2_END)
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK1))
{
/* Clear FLASH End of Operation pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK1);
#else
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
{
/* Clear FLASH End of Operation pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
#endif /* FLASH_BANK2_END */
/* Process can continue only if no error detected */
if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
{
if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
{
/* Nb of pages to erased can be decreased */
pFlash.DataRemaining--;
/* Check if there are still pages to erase */
if(pFlash.DataRemaining != 0U)
{
addresstmp = pFlash.Address;
/*Indicate user which sector has been erased */
HAL_FLASH_EndOfOperationCallback(addresstmp);
/*Increment sector number*/
addresstmp = pFlash.Address + FLASH_PAGE_SIZE;
pFlash.Address = addresstmp;
/* If the erase operation is completed, disable the PER Bit */
CLEAR_BIT(FLASH- & gt; CR, FLASH_CR_PER);
FLASH_PageErase(addresstmp);
}
else
{
/* No more pages to Erase, user callback can be called. */
/* Reset Sector and stop Erase pages procedure */
pFlash.Address = addresstmp = 0xFFFFFFFFU;
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
/* FLASH EOP interrupt user callback */
HAL_FLASH_EndOfOperationCallback(addresstmp);
}
}
else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
{
/* Operation is completed, disable the MER Bit */
CLEAR_BIT(FLASH- & gt; CR, FLASH_CR_MER);
#if defined(FLASH_BANK2_END)
/* Stop Mass Erase procedure if no pending mass erase on other bank */
if (HAL_IS_BIT_CLR(FLASH- & gt; CR2, FLASH_CR2_MER))
{
#endif /* FLASH_BANK2_END */
/* MassErase ended. Return the selected bank */
/* FLASH EOP interrupt user callback */
HAL_FLASH_EndOfOperationCallback(0U);
/* Stop Mass Erase procedure*/
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
}
#if defined(FLASH_BANK2_END)
}
#endif /* FLASH_BANK2_END */
else
{
/* Nb of 16-bit data to program can be decreased */
pFlash.DataRemaining--;
/* Check if there are still 16-bit data to program */
if(pFlash.DataRemaining != 0U)
{
/* Increment address to 16-bit */
pFlash.Address += 2U;
addresstmp = pFlash.Address;
/* Shift to have next 16-bit data */
pFlash.Data = (pFlash.Data & gt; & gt; 16U);
/* Operation is completed, disable the PG Bit */
CLEAR_BIT(FLASH- & gt; CR, FLASH_CR_PG);
/*Program halfword (16-bit) at a specified address.*/
FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);
}
else
{
/* Program ended. Return the selected address */
/* FLASH EOP interrupt user callback */
if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD)
{
HAL_FLASH_EndOfOperationCallback(pFlash.Address);
}
else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD)
{
HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U);
}
else
{
HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U);
}
/* Reset Address and stop Program procedure */
pFlash.Address = 0xFFFFFFFFU;
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
}
}
}
}
#if defined(FLASH_BANK2_END)
/* Check FLASH End of Operation flag */
if(__HAL_FLASH_GET_FLAG( FLASH_FLAG_EOP_BANK2))
{
/* Clear FLASH End of Operation pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2);
/* Process can continue only if no error detected */
if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
{
if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
{
/* Nb of pages to erased can be decreased */
pFlash.DataRemaining--;
/* Check if there are still pages to erase*/
if(pFlash.DataRemaining != 0U)
{
/* Indicate user which page address has been erased*/
HAL_FLASH_EndOfOperationCallback(pFlash.Address);
/* Increment page address to next page */
pFlash.Address += FLASH_PAGE_SIZE;
addresstmp = pFlash.Address;
/* Operation is completed, disable the PER Bit */
CLEAR_BIT(FLASH- & gt; CR2, FLASH_CR2_PER);
FLASH_PageErase(addresstmp);
}
else
{
/*No more pages to Erase*/
/*Reset Address and stop Erase pages procedure*/
pFlash.Address = 0xFFFFFFFFU;
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
/* FLASH EOP interrupt user callback */
HAL_FLASH_EndOfOperationCallback(pFlash.Address);
}
}
else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
{
/* Operation is completed, disable the MER Bit */
CLEAR_BIT(FLASH- & gt; CR2, FLASH_CR2_MER);
if (HAL_IS_BIT_CLR(FLASH- & gt; CR, FLASH_CR_MER))
{
/* MassErase ended. Return the selected bank*/
/* FLASH EOP interrupt user callback */
HAL_FLASH_EndOfOperationCallback(0U);
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
}
}
else
{
/* Nb of 16-bit data to program can be decreased */
pFlash.DataRemaining--;
/* Check if there are still 16-bit data to program */
if(pFlash.DataRemaining != 0U)
{
/* Increment address to 16-bit */
pFlash.Address += 2U;
addresstmp = pFlash.Address;
/* Shift to have next 16-bit data */
pFlash.Data = (pFlash.Data & gt; & gt; 16U);
/* Operation is completed, disable the PG Bit */
CLEAR_BIT(FLASH- & gt; CR2, FLASH_CR2_PG);
/*Program halfword (16-bit) at a specified address.*/
FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);
}
else
{
/*Program ended. Return the selected address*/
/* FLASH EOP interrupt user callback */
if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD)
{
HAL_FLASH_EndOfOperationCallback(pFlash.Address);
}
else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD)
{
HAL_FLASH_EndOfOperationCallback(pFlash.Address-2U);
}
else
{
HAL_FLASH_EndOfOperationCallback(pFlash.Address-6U);
}
/* Reset Address and stop Program procedure*/
pFlash.Address = 0xFFFFFFFFU;
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
}
}
}
}
#endif
if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
{
#if defined(FLASH_BANK2_END)
/* Operation is completed, disable the PG, PER and MER Bits for both bank */
CLEAR_BIT(FLASH- & gt; CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER));
CLEAR_BIT(FLASH- & gt; CR2, (FLASH_CR2_PG | FLASH_CR2_PER | FLASH_CR2_MER));
/* Disable End of FLASH Operation and Error source interrupts for both banks */
__HAL_FLASH_DISABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1 | FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2);
#else
/* Operation is completed, disable the PG, PER and MER Bits */
CLEAR_BIT(FLASH- & gt; CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER));
/* Disable End of FLASH Operation and Error source interrupts */
__HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
#endif /* FLASH_BANK2_END */
/* Process Unlocked */
__HAL_UNLOCK( & pFlash);
}
}
/**
* @brief FLASH end of operation interrupt callback
* @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
* - Mass Erase: No return value expected
* - Pages Erase: Address of the page which has been erased
* (if 0xFFFFFFFF, it means that all the selected pages have been erased)
* - Program: Address which was selected for data program
* @retval none
*/
__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(ReturnValue);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
*/
}
/**
* @brief FLASH operation error interrupt callback
* @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
* - Mass Erase: No return value expected
* - Pages Erase: Address of the page which returned an error
* - Program: Address which was selected for data program
* @retval none
*/
__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(ReturnValue);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FLASH_OperationErrorCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
* @brief management functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to control the FLASH
memory operations.
@endverbatim
* @{
*/
/**
* @brief Unlock the FLASH control register access
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
{
HAL_StatusTypeDef status = HAL_OK;
if(READ_BIT(FLASH- & gt; CR, FLASH_CR_LOCK) != RESET)
{
/* Authorize the FLASH Registers access */
WRITE_REG(FLASH- & gt; KEYR, FLASH_KEY1);
WRITE_REG(FLASH- & gt; KEYR, FLASH_KEY2);
/* Verify Flash is unlocked */
if(READ_BIT(FLASH- & gt; CR, FLASH_CR_LOCK) != RESET)
{
status = HAL_ERROR;
}
}
#if defined(FLASH_BANK2_END)
if(READ_BIT(FLASH- & gt; CR2, FLASH_CR2_LOCK) != RESET)
{
/* Authorize the FLASH BANK2 Registers access */
WRITE_REG(FLASH- & gt; KEYR2, FLASH_KEY1);
WRITE_REG(FLASH- & gt; KEYR2, FLASH_KEY2);
/* Verify Flash BANK2 is unlocked */
if(READ_BIT(FLASH- & gt; CR2, FLASH_CR2_LOCK) != RESET)
{
status = HAL_ERROR;
}
}
#endif /* FLASH_BANK2_END */
return status;
}
/**
* @brief Locks the FLASH control register access
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Lock(void)
{
/* Set the LOCK Bit to lock the FLASH Registers access */
SET_BIT(FLASH- & gt; CR, FLASH_CR_LOCK);
#if defined(FLASH_BANK2_END)
/* Set the LOCK Bit to lock the FLASH BANK2 Registers access */
SET_BIT(FLASH- & gt; CR2, FLASH_CR2_LOCK);
#endif /* FLASH_BANK2_END */
return HAL_OK;
}
/**
* @brief Unlock the FLASH Option Control Registers access.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
{
if (HAL_IS_BIT_CLR(FLASH- & gt; CR, FLASH_CR_OPTWRE))
{
/* Authorizes the Option Byte register programming */
WRITE_REG(FLASH- & gt; OPTKEYR, FLASH_OPTKEY1);
WRITE_REG(FLASH- & gt; OPTKEYR, FLASH_OPTKEY2);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Lock the FLASH Option Control Registers access.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
{
/* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */
CLEAR_BIT(FLASH- & gt; CR, FLASH_CR_OPTWRE);
return HAL_OK;
}
/**
* @brief Launch the option byte loading.
* @note This function will reset automatically the MCU.
* @retval None
*/
void HAL_FLASH_OB_Launch(void)
{
/* Initiates a system reset request to launch the option byte loading */
HAL_NVIC_SystemReset();
}
/**
* @}
*/
/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions
* @brief Peripheral errors functions
*
@verbatim
===============================================================================
##### Peripheral Errors functions #####
===============================================================================
[..]
This subsection permit to get in run-time errors of the FLASH peripheral.
@endverbatim
* @{
*/
/**
* @brief Get the specific FLASH error flag.
* @retval FLASH_ErrorCode The returned value can be:
* @ref FLASH_Error_Codes
*/
uint32_t HAL_FLASH_GetError(void)
{
return pFlash.ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup FLASH_Private_Functions
* @{
*/
/**
* @brief Program a half-word (16-bit) at a specified address.
* @param Address specify the address to be programmed.
* @param Data specify the data to be programmed.
* @retval None
*/
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
{
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
#if defined(FLASH_BANK2_END)
if(Address & lt; = FLASH_BANK1_END)
{
#endif /* FLASH_BANK2_END */
/* Proceed to program the new data */
SET_BIT(FLASH- & gt; CR, FLASH_CR_PG);
#if defined(FLASH_BANK2_END)
}
else
{
/* Proceed to program the new data */
SET_BIT(FLASH- & gt; CR2, FLASH_CR2_PG);
}
#endif /* FLASH_BANK2_END */
/* Write data in the address */
*(__IO uint16_t*)Address = Data;
}
/**
* @brief Wait for a FLASH operation to complete.
* @param Timeout maximum flash operation timeout
* @retval HAL Status
*/
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
{
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
Even if the FLASH operation fails, the BUSY flag will be reset and an error
flag will be set */
uint32_t tickstart = HAL_GetTick();
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
{
if (Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0U) || ((HAL_GetTick()-tickstart) & gt; Timeout))
{
return HAL_TIMEOUT;
}
}
}
/* Check FLASH End of Operation flag */
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
{
/* Clear FLASH End of Operation pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
{
/*Save the error code*/
FLASH_SetErrorCode();
return HAL_ERROR;
}
/* There is no error flag set */
return HAL_OK;
}
#if defined(FLASH_BANK2_END)
/**
* @brief Wait for a FLASH BANK2 operation to complete.
* @param Timeout maximum flash operation timeout
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout)
{
/* Wait for the FLASH BANK2 operation to complete by polling on BUSY flag to be reset.
Even if the FLASH BANK2 operation fails, the BUSY flag will be reset and an error
flag will be set */
uint32_t tickstart = HAL_GetTick();
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY_BANK2))
{
if (Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0U) || ((HAL_GetTick()-tickstart) & gt; Timeout))
{
return HAL_TIMEOUT;
}
}
}
/* Check FLASH End of Operation flag */
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK2))
{
/* Clear FLASH End of Operation pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2);
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))
{
/*Save the error code*/
FLASH_SetErrorCode();
return HAL_ERROR;
}
/* If there is an error flag set */
return HAL_OK;
}
#endif /* FLASH_BANK2_END */
/**
* @brief Set the specific FLASH error flag.
* @retval None
*/
static void FLASH_SetErrorCode(void)
{
uint32_t flags = 0U;
#if defined(FLASH_BANK2_END)
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2))
#else
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
#endif /* FLASH_BANK2_END */
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
#if defined(FLASH_BANK2_END)
flags |= FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2;
#else
flags |= FLASH_FLAG_WRPERR;
#endif /* FLASH_BANK2_END */
}
#if defined(FLASH_BANK2_END)
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))
#else
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
#endif /* FLASH_BANK2_END */
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
#if defined(FLASH_BANK2_END)
flags |= FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2;
#else
flags |= FLASH_FLAG_PGERR;
#endif /* FLASH_BANK2_END */
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
}
/* Clear FLASH error pending bits */
__HAL_FLASH_CLEAR_FLAG(flags);
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_FLASH_MODULE_ENABLED */
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file : main.h
* @brief : Header for main.c file.
* This file contains the common defines of the application.
******************************************************************************
** This notice applies to any and all portions of this file
* that are not between comment pairs USER CODE BEGIN and
* USER CODE END. Other portions of this file, whether
* inserted by the user or by software development tools
* are owned by their respective copyright owners.
*
* COPYRIGHT(c) 2019 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS " AS IS "
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MAIN_H__
#define __MAIN_H__
/* Includes ------------------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private define ------------------------------------------------------------*/
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the " assert_param " macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1U */
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
#ifdef __cplusplus
extern " C " {
#endif
void _Error_Handler(char *, int);
#define Error_Handler() _Error_Handler(__FILE__, __LINE__)
#ifdef __cplusplus
}
#endif
#endif /* __MAIN_H__ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
/**************************************************************************//**
* @file core_cm4.h
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS " AS IS "
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) & & (__ARMCC_VERSION & gt; = 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM4_H_GENERIC
#define __CORE_CM4_H_GENERIC
#include & lt; stdint.h & gt;
#ifdef __cplusplus
extern " C " {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file. & lt; br & gt;
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'. & lt; br & gt;
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined. & lt; br & gt;
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M4
@{
*/
/* CMSIS CM4 definitions */
#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*! & lt; [31:16] CMSIS HAL main version */
#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*! & lt; [15:0] CMSIS HAL sub version */
#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN & lt; & lt; 16U) | \
__CM4_CMSIS_VERSION_SUB ) /*! & lt; CMSIS HAL version number */
#define __CORTEX_M (0x04U) /*! & lt; Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*! & lt; asm keyword for ARM Compiler */
#define __INLINE __inline /*! & lt; inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined(__ARMCC_VERSION) & & (__ARMCC_VERSION & gt; = 6010050)
#define __ASM __asm /*! & lt; asm keyword for ARM Compiler */
#define __INLINE __inline /*! & lt; inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*! & lt; asm keyword for GNU Compiler */
#define __INLINE inline /*! & lt; inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*! & lt; asm keyword for IAR Compiler */
#define __INLINE inline /*! & lt; inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __TMS470__ )
#define __ASM __asm /*! & lt; asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*! & lt; asm keyword for TASKING Compiler */
#define __INLINE inline /*! & lt; inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __CSMC__ )
#define __packed
#define __ASM _asm /*! & lt; asm keyword for COSMIC Compiler */
#define __INLINE inline /*! & lt; inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline
#else
#error Unknown compiler
#endif
/** __FPU_USED indicates whether an FPU is used or not.
For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
*/
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#if (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error " Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) "
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#elif defined(__ARMCC_VERSION) & & (__ARMCC_VERSION & gt; = 6010050)
#if defined __ARM_PCS_VFP
#if (__FPU_PRESENT == 1)
#define __FPU_USED 1U
#else
#warning " Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) "
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) & & !defined(__SOFTFP__)
#if (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error " Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) "
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#if (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error " Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) "
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#elif defined ( __TMS470__ )
#if defined __TI_VFP_SUPPORT__
#if (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error " Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) "
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#if (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error " Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) "
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#if (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error " Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) "
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#endif
#include " core_cmInstr.h " /* Core Instruction Access */
#include " core_cmFunc.h " /* Core Function Access */
#include " core_cmSimd.h " /* Compiler specific SIMD Intrinsics */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM4_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM4_H_DEPENDANT
#define __CORE_CM4_H_DEPENDANT
#ifdef __cplusplus
extern " C " {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM4_REV
#define __CM4_REV 0x0000U
#warning " __CM4_REV not defined in device header file; using default! "
#endif
#ifndef __FPU_PRESENT
#define __FPU_PRESENT 0U
#warning " __FPU_PRESENT not defined in device header file; using default! "
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning " __MPU_PRESENT not defined in device header file; using default! "
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 4U
#warning " __NVIC_PRIO_BITS not defined in device header file; using default! "
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning " __Vendor_SysTickConfig not defined in device header file; using default! "
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
& lt; strong & gt; IO Type Qualifiers & lt; /strong & gt; are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*! & lt; Defines 'read only' permissions */
#else
#define __I volatile const /*! & lt; Defines 'read only' permissions */
#endif
#define __O volatile /*! & lt; Defines 'write only' permissions */
#define __IO volatile /*! & lt; Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M4 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core Debug Register
- Core MPU Register
- Core FPU Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:16; /*! & lt; bit: 0..15 Reserved */
uint32_t GE:4; /*! & lt; bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*! & lt; bit: 20..26 Reserved */
uint32_t Q:1; /*! & lt; bit: 27 Saturation condition flag */
uint32_t V:1; /*! & lt; bit: 28 Overflow condition code flag */
uint32_t C:1; /*! & lt; bit: 29 Carry condition code flag */
uint32_t Z:1; /*! & lt; bit: 30 Zero condition code flag */
uint32_t N:1; /*! & lt; bit: 31 Negative condition code flag */
} b; /*! & lt; Structure used for bit access */
uint32_t w; /*! & lt; Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*! & lt; APSR: N Position */
#define APSR_N_Msk (1UL & lt; & lt; APSR_N_Pos) /*! & lt; APSR: N Mask */
#define APSR_Z_Pos 30U /*! & lt; APSR: Z Position */
#define APSR_Z_Msk (1UL & lt; & lt; APSR_Z_Pos) /*! & lt; APSR: Z Mask */
#define APSR_C_Pos 29U /*! & lt; APSR: C Position */
#define APSR_C_Msk (1UL & lt; & lt; APSR_C_Pos) /*! & lt; APSR: C Mask */
#define APSR_V_Pos 28U /*! & lt; APSR: V Position */
#define APSR_V_Msk (1UL & lt; & lt; APSR_V_Pos) /*! & lt; APSR: V Mask */
#define APSR_Q_Pos 27U /*! & lt; APSR: Q Position */
#define APSR_Q_Msk (1UL & lt; & lt; APSR_Q_Pos) /*! & lt; APSR: Q Mask */
#define APSR_GE_Pos 16U /*! & lt; APSR: GE Position */
#define APSR_GE_Msk (0xFUL & lt; & lt; APSR_GE_Pos) /*! & lt; APSR: GE Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*! & lt; bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*! & lt; bit: 9..31 Reserved */
} b; /*! & lt; Structure used for bit access */
uint32_t w; /*! & lt; Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*! & lt; IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /* & lt; & lt; IPSR_ISR_Pos*/) /*! & lt; IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*! & lt; bit: 0.. 8 Exception number */
uint32_t _reserved0:7; /*! & lt; bit: 9..15 Reserved */
uint32_t GE:4; /*! & lt; bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*! & lt; bit: 20..23 Reserved */
uint32_t T:1; /*! & lt; bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*! & lt; bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*! & lt; bit: 27 Saturation condition flag */
uint32_t V:1; /*! & lt; bit: 28 Overflow condition code flag */
uint32_t C:1; /*! & lt; bit: 29 Carry condition code flag */
uint32_t Z:1; /*! & lt; bit: 30 Zero condition code flag */
uint32_t N:1; /*! & lt; bit: 31 Negative condition code flag */
} b; /*! & lt; Structure used for bit access */
uint32_t w; /*! & lt; Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*! & lt; xPSR: N Position */
#define xPSR_N_Msk (1UL & lt; & lt; xPSR_N_Pos) /*! & lt; xPSR: N Mask */
#define xPSR_Z_Pos 30U /*! & lt; xPSR: Z Position */
#define xPSR_Z_Msk (1UL & lt; & lt; xPSR_Z_Pos) /*! & lt; xPSR: Z Mask */
#define xPSR_C_Pos 29U /*! & lt; xPSR: C Position */
#define xPSR_C_Msk (1UL & lt; & lt; xPSR_C_Pos) /*! & lt; xPSR: C Mask */
#define xPSR_V_Pos 28U /*! & lt; xPSR: V Position */
#define xPSR_V_Msk (1UL & lt; & lt; xPSR_V_Pos) /*! & lt; xPSR: V Mask */
#define xPSR_Q_Pos 27U /*! & lt; xPSR: Q Position */
#define xPSR_Q_Msk (1UL & lt; & lt; xPSR_Q_Pos) /*! & lt; xPSR: Q Mask */
#define xPSR_IT_Pos 25U /*! & lt; xPSR: IT Position */
#define xPSR_IT_Msk (3UL & lt; & lt; xPSR_IT_Pos) /*! & lt; xPSR: IT Mask */
#define xPSR_T_Pos 24U /*! & lt; xPSR: T Position */
#define xPSR_T_Msk (1UL & lt; & lt; xPSR_T_Pos) /*! & lt; xPSR: T Mask */
#define xPSR_GE_Pos 16U /*! & lt; xPSR: GE Position */
#define xPSR_GE_Msk (0xFUL & lt; & lt; xPSR_GE_Pos) /*! & lt; xPSR: GE Mask */
#define xPSR_ISR_Pos 0U /*! & lt; xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /* & lt; & lt; xPSR_ISR_Pos*/) /*! & lt; xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*! & lt; bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*! & lt; bit: 1 Stack to be used */
uint32_t FPCA:1; /*! & lt; bit: 2 FP extension active flag */
uint32_t _reserved0:29; /*! & lt; bit: 3..31 Reserved */
} b; /*! & lt; Structure used for bit access */
uint32_t w; /*! & lt; Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_FPCA_Pos 2U /*! & lt; CONTROL: FPCA Position */
#define CONTROL_FPCA_Msk (1UL & lt; & lt; CONTROL_FPCA_Pos) /*! & lt; CONTROL: FPCA Mask */
#define CONTROL_SPSEL_Pos 1U /*! & lt; CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL & lt; & lt; CONTROL_SPSEL_Pos) /*! & lt; CONTROL: SPSEL Mask */
#define CONTROL_nPRIV_Pos 0U /*! & lt; CONTROL: nPRIV Position */
#define CONTROL_nPRIV_Msk (1UL /* & lt; & lt; CONTROL_nPRIV_Pos*/) /*! & lt; CONTROL: nPRIV Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[8U]; /*! & lt; Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[24U];
__IOM uint32_t ICER[8U]; /*! & lt; Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[24U];
__IOM uint32_t ISPR[8U]; /*! & lt; Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[24U];
__IOM uint32_t ICPR[8U]; /*! & lt; Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[24U];
__IOM uint32_t IABR[8U]; /*! & lt; Offset: 0x200 (R/W) Interrupt Active bit Register */
uint32_t RESERVED4[56U];
__IOM uint8_t IP[240U]; /*! & lt; Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
uint32_t RESERVED5[644U];
__OM uint32_t STIR; /*! & lt; Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
} NVIC_Type;
/* Software Triggered Interrupt Register Definitions */
#define NVIC_STIR_INTID_Pos 0U /*! & lt; STIR: INTLINESNUM Position */
#define NVIC_STIR_INTID_Msk (0x1FFUL /* & lt; & lt; NVIC_STIR_INTID_Pos*/) /*! & lt; STIR: INTLINESNUM Mask */
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*! & lt; Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*! & lt; Offset: 0x004 (R/W) Interrupt Control and State Register */
__IOM uint32_t VTOR; /*! & lt; Offset: 0x008 (R/W) Vector Table Offset Register */
__IOM uint32_t AIRCR; /*! & lt; Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*! & lt; Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*! & lt; Offset: 0x014 (R/W) Configuration Control Register */
__IOM uint8_t SHP[12U]; /*! & lt; Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
__IOM uint32_t SHCSR; /*! & lt; Offset: 0x024 (R/W) System Handler Control and State Register */
__IOM uint32_t CFSR; /*! & lt; Offset: 0x028 (R/W) Configurable Fault Status Register */
__IOM uint32_t HFSR; /*! & lt; Offset: 0x02C (R/W) HardFault Status Register */
__IOM uint32_t DFSR; /*! & lt; Offset: 0x030 (R/W) Debug Fault Status Register */
__IOM uint32_t MMFAR; /*! & lt; Offset: 0x034 (R/W) MemManage Fault Address Register */
__IOM uint32_t BFAR; /*! & lt; Offset: 0x038 (R/W) BusFault Address Register */
__IOM uint32_t AFSR; /*! & lt; Offset: 0x03C (R/W) Auxiliary Fault Status Register */
__IM uint32_t PFR[2U]; /*! & lt; Offset: 0x040 (R/ ) Processor Feature Register */
__IM uint32_t DFR; /*! & lt; Offset: 0x048 (R/ ) Debug Feature Register */
__IM uint32_t ADR; /*! & lt; Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t MMFR[4U]; /*! & lt; Offset: 0x050 (R/ ) Memory Model Feature Register */
__IM uint32_t ISAR[5U]; /*! & lt; Offset: 0x060 (R/ ) Instruction Set Attributes Register */
uint32_t RESERVED0[5U];
__IOM uint32_t CPACR; /*! & lt; Offset: 0x088 (R/W) Coprocessor Access Control Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*! & lt; SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL & lt; & lt; SCB_CPUID_IMPLEMENTER_Pos) /*! & lt; SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*! & lt; SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL & lt; & lt; SCB_CPUID_VARIANT_Pos) /*! & lt; SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*! & lt; SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL & lt; & lt; SCB_CPUID_ARCHITECTURE_Pos) /*! & lt; SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*! & lt; SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL & lt; & lt; SCB_CPUID_PARTNO_Pos) /*! & lt; SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*! & lt; SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /* & lt; & lt; SCB_CPUID_REVISION_Pos*/) /*! & lt; SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*! & lt; SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL & lt; & lt; SCB_ICSR_NMIPENDSET_Pos) /*! & lt; SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*! & lt; SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL & lt; & lt; SCB_ICSR_PENDSVSET_Pos) /*! & lt; SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*! & lt; SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL & lt; & lt; SCB_ICSR_PENDSVCLR_Pos) /*! & lt; SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*! & lt; SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL & lt; & lt; SCB_ICSR_PENDSTSET_Pos) /*! & lt; SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*! & lt; SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL & lt; & lt; SCB_ICSR_PENDSTCLR_Pos) /*! & lt; SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*! & lt; SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL & lt; & lt; SCB_ICSR_ISRPREEMPT_Pos) /*! & lt; SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*! & lt; SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL & lt; & lt; SCB_ICSR_ISRPENDING_Pos) /*! & lt; SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*! & lt; SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL & lt; & lt; SCB_ICSR_VECTPENDING_Pos) /*! & lt; SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_RETTOBASE_Pos 11U /*! & lt; SCB ICSR: RETTOBASE Position */
#define SCB_ICSR_RETTOBASE_Msk (1UL & lt; & lt; SCB_ICSR_RETTOBASE_Pos) /*! & lt; SCB ICSR: RETTOBASE Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*! & lt; SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /* & lt; & lt; SCB_ICSR_VECTACTIVE_Pos*/) /*! & lt; SCB ICSR: VECTACTIVE Mask */
/* SCB Vector Table Offset Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 7U /*! & lt; SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL & lt; & lt; SCB_VTOR_TBLOFF_Pos) /*! & lt; SCB VTOR: TBLOFF Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*! & lt; SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL & lt; & lt; SCB_AIRCR_VECTKEY_Pos) /*! & lt; SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*! & lt; SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL & lt; & lt; SCB_AIRCR_VECTKEYSTAT_Pos) /*! & lt; SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*! & lt; SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL & lt; & lt; SCB_AIRCR_ENDIANESS_Pos) /*! & lt; SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_PRIGROUP_Pos 8U /*! & lt; SCB AIRCR: PRIGROUP Position */
#define SCB_AIRCR_PRIGROUP_Msk (7UL & lt; & lt; SCB_AIRCR_PRIGROUP_Pos) /*! & lt; SCB AIRCR: PRIGROUP Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*! & lt; SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL & lt; & lt; SCB_AIRCR_SYSRESETREQ_Pos) /*! & lt; SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*! & lt; SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL & lt; & lt; SCB_AIRCR_VECTCLRACTIVE_Pos) /*! & lt; SCB AIRCR: VECTCLRACTIVE Mask */
#define SCB_AIRCR_VECTRESET_Pos 0U /*! & lt; SCB AIRCR: VECTRESET Position */
#define SCB_AIRCR_VECTRESET_Msk (1UL /* & lt; & lt; SCB_AIRCR_VECTRESET_Pos*/) /*! & lt; SCB AIRCR: VECTRESET Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*! & lt; SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL & lt; & lt; SCB_SCR_SEVONPEND_Pos) /*! & lt; SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*! & lt; SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL & lt; & lt; SCB_SCR_SLEEPDEEP_Pos) /*! & lt; SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*! & lt; SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL & lt; & lt; SCB_SCR_SLEEPONEXIT_Pos) /*! & lt; SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*! & lt; SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL & lt; & lt; SCB_CCR_STKALIGN_Pos) /*! & lt; SCB CCR: STKALIGN Mask */
#define SCB_CCR_BFHFNMIGN_Pos 8U /*! & lt; SCB CCR: BFHFNMIGN Position */
#define SCB_CCR_BFHFNMIGN_Msk (1UL & lt; & lt; SCB_CCR_BFHFNMIGN_Pos) /*! & lt; SCB CCR: BFHFNMIGN Mask */
#define SCB_CCR_DIV_0_TRP_Pos 4U /*! & lt; SCB CCR: DIV_0_TRP Position */
#define SCB_CCR_DIV_0_TRP_Msk (1UL & lt; & lt; SCB_CCR_DIV_0_TRP_Pos) /*! & lt; SCB CCR: DIV_0_TRP Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*! & lt; SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL & lt; & lt; SCB_CCR_UNALIGN_TRP_Pos) /*! & lt; SCB CCR: UNALIGN_TRP Mask */
#define SCB_CCR_USERSETMPEND_Pos 1U /*! & lt; SCB CCR: USERSETMPEND Position */
#define SCB_CCR_USERSETMPEND_Msk (1UL & lt; & lt; SCB_CCR_USERSETMPEND_Pos) /*! & lt; SCB CCR: USERSETMPEND Mask */
#define SCB_CCR_NONBASETHRDENA_Pos 0U /*! & lt; SCB CCR: NONBASETHRDENA Position */
#define SCB_CCR_NONBASETHRDENA_Msk (1UL /* & lt; & lt; SCB_CCR_NONBASETHRDENA_Pos*/) /*! & lt; SCB CCR: NONBASETHRDENA Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_USGFAULTENA_Pos 18U /*! & lt; SCB SHCSR: USGFAULTENA Position */
#define SCB_SHCSR_USGFAULTENA_Msk (1UL & lt; & lt; SCB_SHCSR_USGFAULTENA_Pos) /*! & lt; SCB SHCSR: USGFAULTENA Mask */
#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*! & lt; SCB SHCSR: BUSFAULTENA Position */
#define SCB_SHCSR_BUSFAULTENA_Msk (1UL & lt; & lt; SCB_SHCSR_BUSFAULTENA_Pos) /*! & lt; SCB SHCSR: BUSFAULTENA Mask */
#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*! & lt; SCB SHCSR: MEMFAULTENA Position */
#define SCB_SHCSR_MEMFAULTENA_Msk (1UL & lt; & lt; SCB_SHCSR_MEMFAULTENA_Pos) /*! & lt; SCB SHCSR: MEMFAULTENA Mask */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*! & lt; SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL & lt; & lt; SCB_SHCSR_SVCALLPENDED_Pos) /*! & lt; SCB SHCSR: SVCALLPENDED Mask */
#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*! & lt; SCB SHCSR: BUSFAULTPENDED Position */
#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL & lt; & lt; SCB_SHCSR_BUSFAULTPENDED_Pos) /*! & lt; SCB SHCSR: BUSFAULTPENDED Mask */
#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*! & lt; SCB SHCSR: MEMFAULTPENDED Position */
#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL & lt; & lt; SCB_SHCSR_MEMFAULTPENDED_Pos) /*! & lt; SCB SHCSR: MEMFAULTPENDED Mask */
#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*! & lt; SCB SHCSR: USGFAULTPENDED Position */
#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL & lt; & lt; SCB_SHCSR_USGFAULTPENDED_Pos) /*! & lt; SCB SHCSR: USGFAULTPENDED Mask */
#define SCB_SHCSR_SYSTICKACT_Pos 11U /*! & lt; SCB SHCSR: SYSTICKACT Position */
#define SCB_SHCSR_SYSTICKACT_Msk (1UL & lt; & lt; SCB_SHCSR_SYSTICKACT_Pos) /*! & lt; SCB SHCSR: SYSTICKACT Mask */
#define SCB_SHCSR_PENDSVACT_Pos 10U /*! & lt; SCB SHCSR: PENDSVACT Position */
#define SCB_SHCSR_PENDSVACT_Msk (1UL & lt; & lt; SCB_SHCSR_PENDSVACT_Pos) /*! & lt; SCB SHCSR: PENDSVACT Mask */
#define SCB_SHCSR_MONITORACT_Pos 8U /*! & lt; SCB SHCSR: MONITORACT Position */
#define SCB_SHCSR_MONITORACT_Msk (1UL & lt; & lt; SCB_SHCSR_MONITORACT_Pos) /*! & lt; SCB SHCSR: MONITORACT Mask */
#define SCB_SHCSR_SVCALLACT_Pos 7U /*! & lt; SCB SHCSR: SVCALLACT Position */
#define SCB_SHCSR_SVCALLACT_Msk (1UL & lt; & lt; SCB_SHCSR_SVCALLACT_Pos) /*! & lt; SCB SHCSR: SVCALLACT Mask */
#define SCB_SHCSR_USGFAULTACT_Pos 3U /*! & lt; SCB SHCSR: USGFAULTACT Position */
#define SCB_SHCSR_USGFAULTACT_Msk (1UL & lt; & lt; SCB_SHCSR_USGFAULTACT_Pos) /*! & lt; SCB SHCSR: USGFAULTACT Mask */
#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*! & lt; SCB SHCSR: BUSFAULTACT Position */
#define SCB_SHCSR_BUSFAULTACT_Msk (1UL & lt; & lt; SCB_SHCSR_BUSFAULTACT_Pos) /*! & lt; SCB SHCSR: BUSFAULTACT Mask */
#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*! & lt; SCB SHCSR: MEMFAULTACT Position */
#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /* & lt; & lt; SCB_SHCSR_MEMFAULTACT_Pos*/) /*! & lt; SCB SHCSR: MEMFAULTACT Mask */
/* SCB Configurable Fault Status Register Definitions */
#define SCB_CFSR_USGFAULTSR_Pos 16U /*! & lt; SCB CFSR: Usage Fault Status Register Position */
#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL & lt; & lt; SCB_CFSR_USGFAULTSR_Pos) /*! & lt; SCB CFSR: Usage Fault Status Register Mask */
#define SCB_CFSR_BUSFAULTSR_Pos 8U /*! & lt; SCB CFSR: Bus Fault Status Register Position */
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL & lt; & lt; SCB_CFSR_BUSFAULTSR_Pos) /*! & lt; SCB CFSR: Bus Fault Status Register Mask */
#define SCB_CFSR_MEMFAULTSR_Pos 0U /*! & lt; SCB CFSR: Memory Manage Fault Status Register Position */
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /* & lt; & lt; SCB_CFSR_MEMFAULTSR_Pos*/) /*! & lt; SCB CFSR: Memory Manage Fault Status Register Mask */
/* SCB Hard Fault Status Register Definitions */
#define SCB_HFSR_DEBUGEVT_Pos 31U /*! & lt; SCB HFSR: DEBUGEVT Position */
#define SCB_HFSR_DEBUGEVT_Msk (1UL & lt; & lt; SCB_HFSR_DEBUGEVT_Pos) /*! & lt; SCB HFSR: DEBUGEVT Mask */
#define SCB_HFSR_FORCED_Pos 30U /*! & lt; SCB HFSR: FORCED Position */
#define SCB_HFSR_FORCED_Msk (1UL & lt; & lt; SCB_HFSR_FORCED_Pos) /*! & lt; SCB HFSR: FORCED Mask */
#define SCB_HFSR_VECTTBL_Pos 1U /*! & lt; SCB HFSR: VECTTBL Position */
#define SCB_HFSR_VECTTBL_Msk (1UL & lt; & lt; SCB_HFSR_VECTTBL_Pos) /*! & lt; SCB HFSR: VECTTBL Mask */
/* SCB Debug Fault Status Register Definitions */
#define SCB_DFSR_EXTERNAL_Pos 4U /*! & lt; SCB DFSR: EXTERNAL Position */
#define SCB_DFSR_EXTERNAL_Msk (1UL & lt; & lt; SCB_DFSR_EXTERNAL_Pos) /*! & lt; SCB DFSR: EXTERNAL Mask */
#define SCB_DFSR_VCATCH_Pos 3U /*! & lt; SCB DFSR: VCATCH Position */
#define SCB_DFSR_VCATCH_Msk (1UL & lt; & lt; SCB_DFSR_VCATCH_Pos) /*! & lt; SCB DFSR: VCATCH Mask */
#define SCB_DFSR_DWTTRAP_Pos 2U /*! & lt; SCB DFSR: DWTTRAP Position */
#define SCB_DFSR_DWTTRAP_Msk (1UL & lt; & lt; SCB_DFSR_DWTTRAP_Pos) /*! & lt; SCB DFSR: DWTTRAP Mask */
#define SCB_DFSR_BKPT_Pos 1U /*! & lt; SCB DFSR: BKPT Position */
#define SCB_DFSR_BKPT_Msk (1UL & lt; & lt; SCB_DFSR_BKPT_Pos) /*! & lt; SCB DFSR: BKPT Mask */
#define SCB_DFSR_HALTED_Pos 0U /*! & lt; SCB DFSR: HALTED Position */
#define SCB_DFSR_HALTED_Msk (1UL /* & lt; & lt; SCB_DFSR_HALTED_Pos*/) /*! & lt; SCB DFSR: HALTED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[1U];
__IM uint32_t ICTR; /*! & lt; Offset: 0x004 (R/ ) Interrupt Controller Type Register */
__IOM uint32_t ACTLR; /*! & lt; Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/* Interrupt Controller Type Register Definitions */
#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*! & lt; ICTR: INTLINESNUM Position */
#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /* & lt; & lt; SCnSCB_ICTR_INTLINESNUM_Pos*/) /*! & lt; ICTR: INTLINESNUM Mask */
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*! & lt; ACTLR: DISOOFP Position */
#define SCnSCB_ACTLR_DISOOFP_Msk (1UL & lt; & lt; SCnSCB_ACTLR_DISOOFP_Pos) /*! & lt; ACTLR: DISOOFP Mask */
#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*! & lt; ACTLR: DISFPCA Position */
#define SCnSCB_ACTLR_DISFPCA_Msk (1UL & lt; & lt; SCnSCB_ACTLR_DISFPCA_Pos) /*! & lt; ACTLR: DISFPCA Mask */
#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*! & lt; ACTLR: DISFOLD Position */
#define SCnSCB_ACTLR_DISFOLD_Msk (1UL & lt; & lt; SCnSCB_ACTLR_DISFOLD_Pos) /*! & lt; ACTLR: DISFOLD Mask */
#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*! & lt; ACTLR: DISDEFWBUF Position */
#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL & lt; & lt; SCnSCB_ACTLR_DISDEFWBUF_Pos) /*! & lt; ACTLR: DISDEFWBUF Mask */
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*! & lt; ACTLR: DISMCYCINT Position */
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /* & lt; & lt; SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*! & lt; ACTLR: DISMCYCINT Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*! & lt; Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*! & lt; Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*! & lt; Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*! & lt; Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*! & lt; SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL & lt; & lt; SysTick_CTRL_COUNTFLAG_Pos) /*! & lt; SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*! & lt; SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL & lt; & lt; SysTick_CTRL_CLKSOURCE_Pos) /*! & lt; SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*! & lt; SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL & lt; & lt; SysTick_CTRL_TICKINT_Pos) /*! & lt; SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*! & lt; SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /* & lt; & lt; SysTick_CTRL_ENABLE_Pos*/) /*! & lt; SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*! & lt; SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /* & lt; & lt; SysTick_LOAD_RELOAD_Pos*/) /*! & lt; SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*! & lt; SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /* & lt; & lt; SysTick_VAL_CURRENT_Pos*/) /*! & lt; SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*! & lt; SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL & lt; & lt; SysTick_CALIB_NOREF_Pos) /*! & lt; SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*! & lt; SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL & lt; & lt; SysTick_CALIB_SKEW_Pos) /*! & lt; SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*! & lt; SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /* & lt; & lt; SysTick_CALIB_TENMS_Pos*/) /*! & lt; SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
@{
*/
/**
\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
*/
typedef struct
{
__OM union
{
__OM uint8_t u8; /*! & lt; Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
__OM uint16_t u16; /*! & lt; Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
__OM uint32_t u32; /*! & lt; Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
} PORT [32U]; /*! & lt; Offset: 0x000 ( /W) ITM Stimulus Port Registers */
uint32_t RESERVED0[864U];
__IOM uint32_t TER; /*! & lt; Offset: 0xE00 (R/W) ITM Trace Enable Register */
uint32_t RESERVED1[15U];
__IOM uint32_t TPR; /*! & lt; Offset: 0xE40 (R/W) ITM Trace Privilege Register */
uint32_t RESERVED2[15U];
__IOM uint32_t TCR; /*! & lt; Offset: 0xE80 (R/W) ITM Trace Control Register */
uint32_t RESERVED3[29U];
__OM uint32_t IWR; /*! & lt; Offset: 0xEF8 ( /W) ITM Integration Write Register */
__IM uint32_t IRR; /*! & lt; Offset: 0xEFC (R/ ) ITM Integration Read Register */
__IOM uint32_t IMCR; /*! & lt; Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
uint32_t RESERVED4[43U];
__OM uint32_t LAR; /*! & lt; Offset: 0xFB0 ( /W) ITM Lock Access Register */
__IM uint32_t LSR; /*! & lt; Offset: 0xFB4 (R/ ) ITM Lock Status Register */
uint32_t RESERVED5[6U];
__IM uint32_t PID4; /*! & lt; Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
__IM uint32_t PID5; /*! & lt; Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
__IM uint32_t PID6; /*! & lt; Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
__IM uint32_t PID7; /*! & lt; Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
__IM uint32_t PID0; /*! & lt; Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
__IM uint32_t PID1; /*! & lt; Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
__IM uint32_t PID2; /*! & lt; Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
__IM uint32_t PID3; /*! & lt; Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
__IM uint32_t CID0; /*! & lt; Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
__IM uint32_t CID1; /*! & lt; Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
__IM uint32_t CID2; /*! & lt; Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
__IM uint32_t CID3; /*! & lt; Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
} ITM_Type;
/* ITM Trace Privilege Register Definitions */
#define ITM_TPR_PRIVMASK_Pos 0U /*! & lt; ITM TPR: PRIVMASK Position */
#define ITM_TPR_PRIVMASK_Msk (0xFUL /* & lt; & lt; ITM_TPR_PRIVMASK_Pos*/) /*! & lt; ITM TPR: PRIVMASK Mask */
/* ITM Trace Control Register Definitions */
#define ITM_TCR_BUSY_Pos 23U /*! & lt; ITM TCR: BUSY Position */
#define ITM_TCR_BUSY_Msk (1UL & lt; & lt; ITM_TCR_BUSY_Pos) /*! & lt; ITM TCR: BUSY Mask */
#define ITM_TCR_TraceBusID_Pos 16U /*! & lt; ITM TCR: ATBID Position */
#define ITM_TCR_TraceBusID_Msk (0x7FUL & lt; & lt; ITM_TCR_TraceBusID_Pos) /*! & lt; ITM TCR: ATBID Mask */
#define ITM_TCR_GTSFREQ_Pos 10U /*! & lt; ITM TCR: Global timestamp frequency Position */
#define ITM_TCR_GTSFREQ_Msk (3UL & lt; & lt; ITM_TCR_GTSFREQ_Pos) /*! & lt; ITM TCR: Global timestamp frequency Mask */
#define ITM_TCR_TSPrescale_Pos 8U /*! & lt; ITM TCR: TSPrescale Position */
#define ITM_TCR_TSPrescale_Msk (3UL & lt; & lt; ITM_TCR_TSPrescale_Pos) /*! & lt; ITM TCR: TSPrescale Mask */
#define ITM_TCR_SWOENA_Pos 4U /*! & lt; ITM TCR: SWOENA Position */
#define ITM_TCR_SWOENA_Msk (1UL & lt; & lt; ITM_TCR_SWOENA_Pos) /*! & lt; ITM TCR: SWOENA Mask */
#define ITM_TCR_DWTENA_Pos 3U /*! & lt; ITM TCR: DWTENA Position */
#define ITM_TCR_DWTENA_Msk (1UL & lt; & lt; ITM_TCR_DWTENA_Pos) /*! & lt; ITM TCR: DWTENA Mask */
#define ITM_TCR_SYNCENA_Pos 2U /*! & lt; ITM TCR: SYNCENA Position */
#define ITM_TCR_SYNCENA_Msk (1UL & lt; & lt; ITM_TCR_SYNCENA_Pos) /*! & lt; ITM TCR: SYNCENA Mask */
#define ITM_TCR_TSENA_Pos 1U /*! & lt; ITM TCR: TSENA Position */
#define ITM_TCR_TSENA_Msk (1UL & lt; & lt; ITM_TCR_TSENA_Pos) /*! & lt; ITM TCR: TSENA Mask */
#define ITM_TCR_ITMENA_Pos 0U /*! & lt; ITM TCR: ITM Enable bit Position */
#define ITM_TCR_ITMENA_Msk (1UL /* & lt; & lt; ITM_TCR_ITMENA_Pos*/) /*! & lt; ITM TCR: ITM Enable bit Mask */
/* ITM Integration Write Register Definitions */
#define ITM_IWR_ATVALIDM_Pos 0U /*! & lt; ITM IWR: ATVALIDM Position */
#define ITM_IWR_ATVALIDM_Msk (1UL /* & lt; & lt; ITM_IWR_ATVALIDM_Pos*/) /*! & lt; ITM IWR: ATVALIDM Mask */
/* ITM Integration Read Register Definitions */
#define ITM_IRR_ATREADYM_Pos 0U /*! & lt; ITM IRR: ATREADYM Position */
#define ITM_IRR_ATREADYM_Msk (1UL /* & lt; & lt; ITM_IRR_ATREADYM_Pos*/) /*! & lt; ITM IRR: ATREADYM Mask */
/* ITM Integration Mode Control Register Definitions */
#define ITM_IMCR_INTEGRATION_Pos 0U /*! & lt; ITM IMCR: INTEGRATION Position */
#define ITM_IMCR_INTEGRATION_Msk (1UL /* & lt; & lt; ITM_IMCR_INTEGRATION_Pos*/) /*! & lt; ITM IMCR: INTEGRATION Mask */
/* ITM Lock Status Register Definitions */
#define ITM_LSR_ByteAcc_Pos 2U /*! & lt; ITM LSR: ByteAcc Position */
#define ITM_LSR_ByteAcc_Msk (1UL & lt; & lt; ITM_LSR_ByteAcc_Pos) /*! & lt; ITM LSR: ByteAcc Mask */
#define ITM_LSR_Access_Pos 1U /*! & lt; ITM LSR: Access Position */
#define ITM_LSR_Access_Msk (1UL & lt; & lt; ITM_LSR_Access_Pos) /*! & lt; ITM LSR: Access Mask */
#define ITM_LSR_Present_Pos 0U /*! & lt; ITM LSR: Present Position */
#define ITM_LSR_Present_Msk (1UL /* & lt; & lt; ITM_LSR_Present_Pos*/) /*! & lt; ITM LSR: Present Mask */
/*@}*/ /* end of group CMSIS_ITM */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
\brief Type definitions for the Data Watchpoint and Trace (DWT)
@{
*/
/**
\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
*/
typedef struct
{
__IOM uint32_t CTRL; /*! & lt; Offset: 0x000 (R/W) Control Register */
__IOM uint32_t CYCCNT; /*! & lt; Offset: 0x004 (R/W) Cycle Count Register */
__IOM uint32_t CPICNT; /*! & lt; Offset: 0x008 (R/W) CPI Count Register */
__IOM uint32_t EXCCNT; /*! & lt; Offset: 0x00C (R/W) Exception Overhead Count Register */
__IOM uint32_t SLEEPCNT; /*! & lt; Offset: 0x010 (R/W) Sleep Count Register */
__IOM uint32_t LSUCNT; /*! & lt; Offset: 0x014 (R/W) LSU Count Register */
__IOM uint32_t FOLDCNT; /*! & lt; Offset: 0x018 (R/W) Folded-instruction Count Register */
__IM uint32_t PCSR; /*! & lt; Offset: 0x01C (R/ ) Program Counter Sample Register */
__IOM uint32_t COMP0; /*! & lt; Offset: 0x020 (R/W) Comparator Register 0 */
__IOM uint32_t MASK0; /*! & lt; Offset: 0x024 (R/W) Mask Register 0 */
__IOM uint32_t FUNCTION0; /*! & lt; Offset: 0x028 (R/W) Function Register 0 */
uint32_t RESERVED0[1U];
__IOM uint32_t COMP1; /*! & lt; Offset: 0x030 (R/W) Comparator Register 1 */
__IOM uint32_t MASK1; /*! & lt; Offset: 0x034 (R/W) Mask Register 1 */
__IOM uint32_t FUNCTION1; /*! & lt; Offset: 0x038 (R/W) Function Register 1 */
uint32_t RESERVED1[1U];
__IOM uint32_t COMP2; /*! & lt; Offset: 0x040 (R/W) Comparator Register 2 */
__IOM uint32_t MASK2; /*! & lt; Offset: 0x044 (R/W) Mask Register 2 */
__IOM uint32_t FUNCTION2; /*! & lt; Offset: 0x048 (R/W) Function Register 2 */
uint32_t RESERVED2[1U];
__IOM uint32_t COMP3; /*! & lt; Offset: 0x050 (R/W) Comparator Register 3 */
__IOM uint32_t MASK3; /*! & lt; Offset: 0x054 (R/W) Mask Register 3 */
__IOM uint32_t FUNCTION3; /*! & lt; Offset: 0x058 (R/W) Function Register 3 */
} DWT_Type;
/* DWT Control Register Definitions */
#define DWT_CTRL_NUMCOMP_Pos 28U /*! & lt; DWT CTRL: NUMCOMP Position */
#define DWT_CTRL_NUMCOMP_Msk (0xFUL & lt; & lt; DWT_CTRL_NUMCOMP_Pos) /*! & lt; DWT CTRL: NUMCOMP Mask */
#define DWT_CTRL_NOTRCPKT_Pos 27U /*! & lt; DWT CTRL: NOTRCPKT Position */
#define DWT_CTRL_NOTRCPKT_Msk (0x1UL & lt; & lt; DWT_CTRL_NOTRCPKT_Pos) /*! & lt; DWT CTRL: NOTRCPKT Mask */
#define DWT_CTRL_NOEXTTRIG_Pos 26U /*! & lt; DWT CTRL: NOEXTTRIG Position */
#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL & lt; & lt; DWT_CTRL_NOEXTTRIG_Pos) /*! & lt; DWT CTRL: NOEXTTRIG Mask */
#define DWT_CTRL_NOCYCCNT_Pos 25U /*! & lt; DWT CTRL: NOCYCCNT Position */
#define DWT_CTRL_NOCYCCNT_Msk (0x1UL & lt; & lt; DWT_CTRL_NOCYCCNT_Pos) /*! & lt; DWT CTRL: NOCYCCNT Mask */
#define DWT_CTRL_NOPRFCNT_Pos 24U /*! & lt; DWT CTRL: NOPRFCNT Position */
#define DWT_CTRL_NOPRFCNT_Msk (0x1UL & lt; & lt; DWT_CTRL_NOPRFCNT_Pos) /*! & lt; DWT CTRL: NOPRFCNT Mask */
#define DWT_CTRL_CYCEVTENA_Pos 22U /*! & lt; DWT CTRL: CYCEVTENA Position */
#define DWT_CTRL_CYCEVTENA_Msk (0x1UL & lt; & lt; DWT_CTRL_CYCEVTENA_Pos) /*! & lt; DWT CTRL: CYCEVTENA Mask */
#define DWT_CTRL_FOLDEVTENA_Pos 21U /*! & lt; DWT CTRL: FOLDEVTENA Position */
#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL & lt; & lt; DWT_CTRL_FOLDEVTENA_Pos) /*! & lt; DWT CTRL: FOLDEVTENA Mask */
#define DWT_CTRL_LSUEVTENA_Pos 20U /*! & lt; DWT CTRL: LSUEVTENA Position */
#define DWT_CTRL_LSUEVTENA_Msk (0x1UL & lt; & lt; DWT_CTRL_LSUEVTENA_Pos) /*! & lt; DWT CTRL: LSUEVTENA Mask */
#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*! & lt; DWT CTRL: SLEEPEVTENA Position */
#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL & lt; & lt; DWT_CTRL_SLEEPEVTENA_Pos) /*! & lt; DWT CTRL: SLEEPEVTENA Mask */
#define DWT_CTRL_EXCEVTENA_Pos 18U /*! & lt; DWT CTRL: EXCEVTENA Position */
#define DWT_CTRL_EXCEVTENA_Msk (0x1UL & lt; & lt; DWT_CTRL_EXCEVTENA_Pos) /*! & lt; DWT CTRL: EXCEVTENA Mask */
#define DWT_CTRL_CPIEVTENA_Pos 17U /*! & lt; DWT CTRL: CPIEVTENA Position */
#define DWT_CTRL_CPIEVTENA_Msk (0x1UL & lt; & lt; DWT_CTRL_CPIEVTENA_Pos) /*! & lt; DWT CTRL: CPIEVTENA Mask */
#define DWT_CTRL_EXCTRCENA_Pos 16U /*! & lt; DWT CTRL: EXCTRCENA Position */
#define DWT_CTRL_EXCTRCENA_Msk (0x1UL & lt; & lt; DWT_CTRL_EXCTRCENA_Pos) /*! & lt; DWT CTRL: EXCTRCENA Mask */
#define DWT_CTRL_PCSAMPLENA_Pos 12U /*! & lt; DWT CTRL: PCSAMPLENA Position */
#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL & lt; & lt; DWT_CTRL_PCSAMPLENA_Pos) /*! & lt; DWT CTRL: PCSAMPLENA Mask */
#define DWT_CTRL_SYNCTAP_Pos 10U /*! & lt; DWT CTRL: SYNCTAP Position */
#define DWT_CTRL_SYNCTAP_Msk (0x3UL & lt; & lt; DWT_CTRL_SYNCTAP_Pos) /*! & lt; DWT CTRL: SYNCTAP Mask */
#define DWT_CTRL_CYCTAP_Pos 9U /*! & lt; DWT CTRL: CYCTAP Position */
#define DWT_CTRL_CYCTAP_Msk (0x1UL & lt; & lt; DWT_CTRL_CYCTAP_Pos) /*! & lt; DWT CTRL: CYCTAP Mask */
#define DWT_CTRL_POSTINIT_Pos 5U /*! & lt; DWT CTRL: POSTINIT Position */
#define DWT_CTRL_POSTINIT_Msk (0xFUL & lt; & lt; DWT_CTRL_POSTINIT_Pos) /*! & lt; DWT CTRL: POSTINIT Mask */
#define DWT_CTRL_POSTPRESET_Pos 1U /*! & lt; DWT CTRL: POSTPRESET Position */
#define DWT_CTRL_POSTPRESET_Msk (0xFUL & lt; & lt; DWT_CTRL_POSTPRESET_Pos) /*! & lt; DWT CTRL: POSTPRESET Mask */
#define DWT_CTRL_CYCCNTENA_Pos 0U /*! & lt; DWT CTRL: CYCCNTENA Position */
#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /* & lt; & lt; DWT_CTRL_CYCCNTENA_Pos*/) /*! & lt; DWT CTRL: CYCCNTENA Mask */
/* DWT CPI Count Register Definitions */
#define DWT_CPICNT_CPICNT_Pos 0U /*! & lt; DWT CPICNT: CPICNT Position */
#define DWT_CPICNT_CPICNT_Msk (0xFFUL /* & lt; & lt; DWT_CPICNT_CPICNT_Pos*/) /*! & lt; DWT CPICNT: CPICNT Mask */
/* DWT Exception Overhead Count Register Definitions */
#define DWT_EXCCNT_EXCCNT_Pos 0U /*! & lt; DWT EXCCNT: EXCCNT Position */
#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /* & lt; & lt; DWT_EXCCNT_EXCCNT_Pos*/) /*! & lt; DWT EXCCNT: EXCCNT Mask */
/* DWT Sleep Count Register Definitions */
#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*! & lt; DWT SLEEPCNT: SLEEPCNT Position */
#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /* & lt; & lt; DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*! & lt; DWT SLEEPCNT: SLEEPCNT Mask */
/* DWT LSU Count Register Definitions */
#define DWT_LSUCNT_LSUCNT_Pos 0U /*! & lt; DWT LSUCNT: LSUCNT Position */
#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /* & lt; & lt; DWT_LSUCNT_LSUCNT_Pos*/) /*! & lt; DWT LSUCNT: LSUCNT Mask */
/* DWT Folded-instruction Count Register Definitions */
#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*! & lt; DWT FOLDCNT: FOLDCNT Position */
#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /* & lt; & lt; DWT_FOLDCNT_FOLDCNT_Pos*/) /*! & lt; DWT FOLDCNT: FOLDCNT Mask */
/* DWT Comparator Mask Register Definitions */
#define DWT_MASK_MASK_Pos 0U /*! & lt; DWT MASK: MASK Position */
#define DWT_MASK_MASK_Msk (0x1FUL /* & lt; & lt; DWT_MASK_MASK_Pos*/) /*! & lt; DWT MASK: MASK Mask */
/* DWT Comparator Function Register Definitions */
#define DWT_FUNCTION_MATCHED_Pos 24U /*! & lt; DWT FUNCTION: MATCHED Position */
#define DWT_FUNCTION_MATCHED_Msk (0x1UL & lt; & lt; DWT_FUNCTION_MATCHED_Pos) /*! & lt; DWT FUNCTION: MATCHED Mask */
#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*! & lt; DWT FUNCTION: DATAVADDR1 Position */
#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL & lt; & lt; DWT_FUNCTION_DATAVADDR1_Pos) /*! & lt; DWT FUNCTION: DATAVADDR1 Mask */
#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*! & lt; DWT FUNCTION: DATAVADDR0 Position */
#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL & lt; & lt; DWT_FUNCTION_DATAVADDR0_Pos) /*! & lt; DWT FUNCTION: DATAVADDR0 Mask */
#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*! & lt; DWT FUNCTION: DATAVSIZE Position */
#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL & lt; & lt; DWT_FUNCTION_DATAVSIZE_Pos) /*! & lt; DWT FUNCTION: DATAVSIZE Mask */
#define DWT_FUNCTION_LNK1ENA_Pos 9U /*! & lt; DWT FUNCTION: LNK1ENA Position */
#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL & lt; & lt; DWT_FUNCTION_LNK1ENA_Pos) /*! & lt; DWT FUNCTION: LNK1ENA Mask */
#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*! & lt; DWT FUNCTION: DATAVMATCH Position */
#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL & lt; & lt; DWT_FUNCTION_DATAVMATCH_Pos) /*! & lt; DWT FUNCTION: DATAVMATCH Mask */
#define DWT_FUNCTION_CYCMATCH_Pos 7U /*! & lt; DWT FUNCTION: CYCMATCH Position */
#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL & lt; & lt; DWT_FUNCTION_CYCMATCH_Pos) /*! & lt; DWT FUNCTION: CYCMATCH Mask */
#define DWT_FUNCTION_EMITRANGE_Pos 5U /*! & lt; DWT FUNCTION: EMITRANGE Position */
#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL & lt; & lt; DWT_FUNCTION_EMITRANGE_Pos) /*! & lt; DWT FUNCTION: EMITRANGE Mask */
#define DWT_FUNCTION_FUNCTION_Pos 0U /*! & lt; DWT FUNCTION: FUNCTION Position */
#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /* & lt; & lt; DWT_FUNCTION_FUNCTION_Pos*/) /*! & lt; DWT FUNCTION: FUNCTION Mask */
/*@}*/ /* end of group CMSIS_DWT */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_TPI Trace Port Interface (TPI)
\brief Type definitions for the Trace Port Interface (TPI)
@{
*/
/**
\brief Structure type to access the Trace Port Interface Register (TPI).
*/
typedef struct
{
__IOM uint32_t SSPSR; /*! & lt; Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
__IOM uint32_t CSPSR; /*! & lt; Offset: 0x004 (R/W) Current Parallel Port Size Register */
uint32_t RESERVED0[2U];
__IOM uint32_t ACPR; /*! & lt; Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
uint32_t RESERVED1[55U];
__IOM uint32_t SPPR; /*! & lt; Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
uint32_t RESERVED2[131U];
__IM uint32_t FFSR; /*! & lt; Offset: 0x300 (R/ ) Formatter and Flush Status Register */
__IOM uint32_t FFCR; /*! & lt; Offset: 0x304 (R/W) Formatter and Flush Control Register */
__IM uint32_t FSCR; /*! & lt; Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
uint32_t RESERVED3[759U];
__IM uint32_t TRIGGER; /*! & lt; Offset: 0xEE8 (R/ ) TRIGGER */
__IM uint32_t FIFO0; /*! & lt; Offset: 0xEEC (R/ ) Integration ETM Data */
__IM uint32_t ITATBCTR2; /*! & lt; Offset: 0xEF0 (R/ ) ITATBCTR2 */
uint32_t RESERVED4[1U];
__IM uint32_t ITATBCTR0; /*! & lt; Offset: 0xEF8 (R/ ) ITATBCTR0 */
__IM uint32_t FIFO1; /*! & lt; Offset: 0xEFC (R/ ) Integration ITM Data */
__IOM uint32_t ITCTRL; /*! & lt; Offset: 0xF00 (R/W) Integration Mode Control */
uint32_t RESERVED5[39U];
__IOM uint32_t CLAIMSET; /*! & lt; Offset: 0xFA0 (R/W) Claim tag set */
__IOM uint32_t CLAIMCLR; /*! & lt; Offset: 0xFA4 (R/W) Claim tag clear */
uint32_t RESERVED7[8U];
__IM uint32_t DEVID; /*! & lt; Offset: 0xFC8 (R/ ) TPIU_DEVID */
__IM uint32_t DEVTYPE; /*! & lt; Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
} TPI_Type;
/* TPI Asynchronous Clock Prescaler Register Definitions */
#define TPI_ACPR_PRESCALER_Pos 0U /*! & lt; TPI ACPR: PRESCALER Position */
#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /* & lt; & lt; TPI_ACPR_PRESCALER_Pos*/) /*! & lt; TPI ACPR: PRESCALER Mask */
/* TPI Selected Pin Protocol Register Definitions */
#define TPI_SPPR_TXMODE_Pos 0U /*! & lt; TPI SPPR: TXMODE Position */
#define TPI_SPPR_TXMODE_Msk (0x3UL /* & lt; & lt; TPI_SPPR_TXMODE_Pos*/) /*! & lt; TPI SPPR: TXMODE Mask */
/* TPI Formatter and Flush Status Register Definitions */
#define TPI_FFSR_FtNonStop_Pos 3U /*! & lt; TPI FFSR: FtNonStop Position */
#define TPI_FFSR_FtNonStop_Msk (0x1UL & lt; & lt; TPI_FFSR_FtNonStop_Pos) /*! & lt; TPI FFSR: FtNonStop Mask */
#define TPI_FFSR_TCPresent_Pos 2U /*! & lt; TPI FFSR: TCPresent Position */
#define TPI_FFSR_TCPresent_Msk (0x1UL & lt; & lt; TPI_FFSR_TCPresent_Pos) /*! & lt; TPI FFSR: TCPresent Mask */
#define TPI_FFSR_FtStopped_Pos 1U /*! & lt; TPI FFSR: FtStopped Position */
#define TPI_FFSR_FtStopped_Msk (0x1UL & lt; & lt; TPI_FFSR_FtStopped_Pos) /*! & lt; TPI FFSR: FtStopped Mask */
#define TPI_FFSR_FlInProg_Pos 0U /*! & lt; TPI FFSR: FlInProg Position */
#define TPI_FFSR_FlInProg_Msk (0x1UL /* & lt; & lt; TPI_FFSR_FlInProg_Pos*/) /*! & lt; TPI FFSR: FlInProg Mask */
/* TPI Formatter and Flush Control Register Definitions */
#define TPI_FFCR_TrigIn_Pos 8U /*! & lt; TPI FFCR: TrigIn Position */
#define TPI_FFCR_TrigIn_Msk (0x1UL & lt; & lt; TPI_FFCR_TrigIn_Pos) /*! & lt; TPI FFCR: TrigIn Mask */
#define TPI_FFCR_EnFCont_Pos 1U /*! & lt; TPI FFCR: EnFCont Position */
#define TPI_FFCR_EnFCont_Msk (0x1UL & lt; & lt; TPI_FFCR_EnFCont_Pos) /*! & lt; TPI FFCR: EnFCont Mask */
/* TPI TRIGGER Register Definitions */
#define TPI_TRIGGER_TRIGGER_Pos 0U /*! & lt; TPI TRIGGER: TRIGGER Position */
#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /* & lt; & lt; TPI_TRIGGER_TRIGGER_Pos*/) /*! & lt; TPI TRIGGER: TRIGGER Mask */
/* TPI Integration ETM Data Register Definitions (FIFO0) */
#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*! & lt; TPI FIFO0: ITM_ATVALID Position */
#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL & lt; & lt; TPI_FIFO0_ITM_ATVALID_Pos) /*! & lt; TPI FIFO0: ITM_ATVALID Mask */
#define TPI_FIFO0_ITM_bytecount_Pos 27U /*! & lt; TPI FIFO0: ITM_bytecount Position */
#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL & lt; & lt; TPI_FIFO0_ITM_bytecount_Pos) /*! & lt; TPI FIFO0: ITM_bytecount Mask */
#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*! & lt; TPI FIFO0: ETM_ATVALID Position */
#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL & lt; & lt; TPI_FIFO0_ETM_ATVALID_Pos) /*! & lt; TPI FIFO0: ETM_ATVALID Mask */
#define TPI_FIFO0_ETM_bytecount_Pos 24U /*! & lt; TPI FIFO0: ETM_bytecount Position */
#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL & lt; & lt; TPI_FIFO0_ETM_bytecount_Pos) /*! & lt; TPI FIFO0: ETM_bytecount Mask */
#define TPI_FIFO0_ETM2_Pos 16U /*! & lt; TPI FIFO0: ETM2 Position */
#define TPI_FIFO0_ETM2_Msk (0xFFUL & lt; & lt; TPI_FIFO0_ETM2_Pos) /*! & lt; TPI FIFO0: ETM2 Mask */
#define TPI_FIFO0_ETM1_Pos 8U /*! & lt; TPI FIFO0: ETM1 Position */
#define TPI_FIFO0_ETM1_Msk (0xFFUL & lt; & lt; TPI_FIFO0_ETM1_Pos) /*! & lt; TPI FIFO0: ETM1 Mask */
#define TPI_FIFO0_ETM0_Pos 0U /*! & lt; TPI FIFO0: ETM0 Position */
#define TPI_FIFO0_ETM0_Msk (0xFFUL /* & lt; & lt; TPI_FIFO0_ETM0_Pos*/) /*! & lt; TPI FIFO0: ETM0 Mask */
/* TPI ITATBCTR2 Register Definitions */
#define TPI_ITATBCTR2_ATREADY_Pos 0U /*! & lt; TPI ITATBCTR2: ATREADY Position */
#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /* & lt; & lt; TPI_ITATBCTR2_ATREADY_Pos*/) /*! & lt; TPI ITATBCTR2: ATREADY Mask */
/* TPI Integration ITM Data Register Definitions (FIFO1) */
#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*! & lt; TPI FIFO1: ITM_ATVALID Position */
#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL & lt; & lt; TPI_FIFO1_ITM_ATVALID_Pos) /*! & lt; TPI FIFO1: ITM_ATVALID Mask */
#define TPI_FIFO1_ITM_bytecount_Pos 27U /*! & lt; TPI FIFO1: ITM_bytecount Position */
#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL & lt; & lt; TPI_FIFO1_ITM_bytecount_Pos) /*! & lt; TPI FIFO1: ITM_bytecount Mask */
#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*! & lt; TPI FIFO1: ETM_ATVALID Position */
#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL & lt; & lt; TPI_FIFO1_ETM_ATVALID_Pos) /*! & lt; TPI FIFO1: ETM_ATVALID Mask */
#define TPI_FIFO1_ETM_bytecount_Pos 24U /*! & lt; TPI FIFO1: ETM_bytecount Position */
#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL & lt; & lt; TPI_FIFO1_ETM_bytecount_Pos) /*! & lt; TPI FIFO1: ETM_bytecount Mask */
#define TPI_FIFO1_ITM2_Pos 16U /*! & lt; TPI FIFO1: ITM2 Position */
#define TPI_FIFO1_ITM2_Msk (0xFFUL & lt; & lt; TPI_FIFO1_ITM2_Pos) /*! & lt; TPI FIFO1: ITM2 Mask */
#define TPI_FIFO1_ITM1_Pos 8U /*! & lt; TPI FIFO1: ITM1 Position */
#define TPI_FIFO1_ITM1_Msk (0xFFUL & lt; & lt; TPI_FIFO1_ITM1_Pos) /*! & lt; TPI FIFO1: ITM1 Mask */
#define TPI_FIFO1_ITM0_Pos 0U /*! & lt; TPI FIFO1: ITM0 Position */
#define TPI_FIFO1_ITM0_Msk (0xFFUL /* & lt; & lt; TPI_FIFO1_ITM0_Pos*/) /*! & lt; TPI FIFO1: ITM0 Mask */
/* TPI ITATBCTR0 Register Definitions */
#define TPI_ITATBCTR0_ATREADY_Pos 0U /*! & lt; TPI ITATBCTR0: ATREADY Position */
#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /* & lt; & lt; TPI_ITATBCTR0_ATREADY_Pos*/) /*! & lt; TPI ITATBCTR0: ATREADY Mask */
/* TPI Integration Mode Control Register Definitions */
#define TPI_ITCTRL_Mode_Pos 0U /*! & lt; TPI ITCTRL: Mode Position */
#define TPI_ITCTRL_Mode_Msk (0x1UL /* & lt; & lt; TPI_ITCTRL_Mode_Pos*/) /*! & lt; TPI ITCTRL: Mode Mask */
/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11U /*! & lt; TPI DEVID: NRZVALID Position */
#define TPI_DEVID_NRZVALID_Msk (0x1UL & lt; & lt; TPI_DEVID_NRZVALID_Pos) /*! & lt; TPI DEVID: NRZVALID Mask */
#define TPI_DEVID_MANCVALID_Pos 10U /*! & lt; TPI DEVID: MANCVALID Position */
#define TPI_DEVID_MANCVALID_Msk (0x1UL & lt; & lt; TPI_DEVID_MANCVALID_Pos) /*! & lt; TPI DEVID: MANCVALID Mask */
#define TPI_DEVID_PTINVALID_Pos 9U /*! & lt; TPI DEVID: PTINVALID Position */
#define TPI_DEVID_PTINVALID_Msk (0x1UL & lt; & lt; TPI_DEVID_PTINVALID_Pos) /*! & lt; TPI DEVID: PTINVALID Mask */
#define TPI_DEVID_MinBufSz_Pos 6U /*! & lt; TPI DEVID: MinBufSz Position */
#define TPI_DEVID_MinBufSz_Msk (0x7UL & lt; & lt; TPI_DEVID_MinBufSz_Pos) /*! & lt; TPI DEVID: MinBufSz Mask */
#define TPI_DEVID_AsynClkIn_Pos 5U /*! & lt; TPI DEVID: AsynClkIn Position */
#define TPI_DEVID_AsynClkIn_Msk (0x1UL & lt; & lt; TPI_DEVID_AsynClkIn_Pos) /*! & lt; TPI DEVID: AsynClkIn Mask */
#define TPI_DEVID_NrTraceInput_Pos 0U /*! & lt; TPI DEVID: NrTraceInput Position */
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /* & lt; & lt; TPI_DEVID_NrTraceInput_Pos*/) /*! & lt; TPI DEVID: NrTraceInput Mask */
/* TPI DEVTYPE Register Definitions */
#define TPI_DEVTYPE_MajorType_Pos 4U /*! & lt; TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL & lt; & lt; TPI_DEVTYPE_MajorType_Pos) /*! & lt; TPI DEVTYPE: MajorType Mask */
#define TPI_DEVTYPE_SubType_Pos 0U /*! & lt; TPI DEVTYPE: SubType Position */
#define TPI_DEVTYPE_SubType_Msk (0xFUL /* & lt; & lt; TPI_DEVTYPE_SubType_Pos*/) /*! & lt; TPI DEVTYPE: SubType Mask */
/*@}*/ /* end of group CMSIS_TPI */
#if (__MPU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__IM uint32_t TYPE; /*! & lt; Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*! & lt; Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*! & lt; Offset: 0x008 (R/W) MPU Region RNRber Register */
__IOM uint32_t RBAR; /*! & lt; Offset: 0x00C (R/W) MPU Region Base Address Register */
__IOM uint32_t RASR; /*! & lt; Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
__IOM uint32_t RBAR_A1; /*! & lt; Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
__IOM uint32_t RASR_A1; /*! & lt; Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
__IOM uint32_t RBAR_A2; /*! & lt; Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
__IOM uint32_t RASR_A2; /*! & lt; Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
__IOM uint32_t RBAR_A3; /*! & lt; Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
__IOM uint32_t RASR_A3; /*! & lt; Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
} MPU_Type;
/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U /*! & lt; MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL & lt; & lt; MPU_TYPE_IREGION_Pos) /*! & lt; MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8U /*! & lt; MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL & lt; & lt; MPU_TYPE_DREGION_Pos) /*! & lt; MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0U /*! & lt; MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /* & lt; & lt; MPU_TYPE_SEPARATE_Pos*/) /*! & lt; MPU TYPE: SEPARATE Mask */
/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*! & lt; MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL & lt; & lt; MPU_CTRL_PRIVDEFENA_Pos) /*! & lt; MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1U /*! & lt; MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL & lt; & lt; MPU_CTRL_HFNMIENA_Pos) /*! & lt; MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0U /*! & lt; MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /* & lt; & lt; MPU_CTRL_ENABLE_Pos*/) /*! & lt; MPU CTRL: ENABLE Mask */
/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U /*! & lt; MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /* & lt; & lt; MPU_RNR_REGION_Pos*/) /*! & lt; MPU RNR: REGION Mask */
/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_ADDR_Pos 5U /*! & lt; MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL & lt; & lt; MPU_RBAR_ADDR_Pos) /*! & lt; MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4U /*! & lt; MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL & lt; & lt; MPU_RBAR_VALID_Pos) /*! & lt; MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0U /*! & lt; MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL /* & lt; & lt; MPU_RBAR_REGION_Pos*/) /*! & lt; MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register Definitions */
#define MPU_RASR_ATTRS_Pos 16U /*! & lt; MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL & lt; & lt; MPU_RASR_ATTRS_Pos) /*! & lt; MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_XN_Pos 28U /*! & lt; MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL & lt; & lt; MPU_RASR_XN_Pos) /*! & lt; MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_AP_Pos 24U /*! & lt; MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL & lt; & lt; MPU_RASR_AP_Pos) /*! & lt; MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_TEX_Pos 19U /*! & lt; MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL & lt; & lt; MPU_RASR_TEX_Pos) /*! & lt; MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_S_Pos 18U /*! & lt; MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL & lt; & lt; MPU_RASR_S_Pos) /*! & lt; MPU RASR: ATTRS.S Mask */
#define MPU_RASR_C_Pos 17U /*! & lt; MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL & lt; & lt; MPU_RASR_C_Pos) /*! & lt; MPU RASR: ATTRS.C Mask */
#define MPU_RASR_B_Pos 16U /*! & lt; MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL & lt; & lt; MPU_RASR_B_Pos) /*! & lt; MPU RASR: ATTRS.B Mask */
#define MPU_RASR_SRD_Pos 8U /*! & lt; MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL & lt; & lt; MPU_RASR_SRD_Pos) /*! & lt; MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1U /*! & lt; MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL & lt; & lt; MPU_RASR_SIZE_Pos) /*! & lt; MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0U /*! & lt; MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL /* & lt; & lt; MPU_RASR_ENABLE_Pos*/) /*! & lt; MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
#if (__FPU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_FPU Floating Point Unit (FPU)
\brief Type definitions for the Floating Point Unit (FPU)
@{
*/
/**
\brief Structure type to access the Floating Point Unit (FPU).
*/
typedef struct
{
uint32_t RESERVED0[1U];
__IOM uint32_t FPCCR; /*! & lt; Offset: 0x004 (R/W) Floating-Point Context Control Register */
__IOM uint32_t FPCAR; /*! & lt; Offset: 0x008 (R/W) Floating-Point Context Address Register */
__IOM uint32_t FPDSCR; /*! & lt; Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
__IM uint32_t MVFR0; /*! & lt; Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
__IM uint32_t MVFR1; /*! & lt; Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
} FPU_Type;
/* Floating-Point Context Control Register Definitions */
#define FPU_FPCCR_ASPEN_Pos 31U /*! & lt; FPCCR: ASPEN bit Position */
#define FPU_FPCCR_ASPEN_Msk (1UL & lt; & lt; FPU_FPCCR_ASPEN_Pos) /*! & lt; FPCCR: ASPEN bit Mask */
#define FPU_FPCCR_LSPEN_Pos 30U /*! & lt; FPCCR: LSPEN Position */
#define FPU_FPCCR_LSPEN_Msk (1UL & lt; & lt; FPU_FPCCR_LSPEN_Pos) /*! & lt; FPCCR: LSPEN bit Mask */
#define FPU_FPCCR_MONRDY_Pos 8U /*! & lt; FPCCR: MONRDY Position */
#define FPU_FPCCR_MONRDY_Msk (1UL & lt; & lt; FPU_FPCCR_MONRDY_Pos) /*! & lt; FPCCR: MONRDY bit Mask */
#define FPU_FPCCR_BFRDY_Pos 6U /*! & lt; FPCCR: BFRDY Position */
#define FPU_FPCCR_BFRDY_Msk (1UL & lt; & lt; FPU_FPCCR_BFRDY_Pos) /*! & lt; FPCCR: BFRDY bit Mask */
#define FPU_FPCCR_MMRDY_Pos 5U /*! & lt; FPCCR: MMRDY Position */
#define FPU_FPCCR_MMRDY_Msk (1UL & lt; & lt; FPU_FPCCR_MMRDY_Pos) /*! & lt; FPCCR: MMRDY bit Mask */
#define FPU_FPCCR_HFRDY_Pos 4U /*! & lt; FPCCR: HFRDY Position */
#define FPU_FPCCR_HFRDY_Msk (1UL & lt; & lt; FPU_FPCCR_HFRDY_Pos) /*! & lt; FPCCR: HFRDY bit Mask */
#define FPU_FPCCR_THREAD_Pos 3U /*! & lt; FPCCR: processor mode bit Position */
#define FPU_FPCCR_THREAD_Msk (1UL & lt; & lt; FPU_FPCCR_THREAD_Pos) /*! & lt; FPCCR: processor mode active bit Mask */
#define FPU_FPCCR_USER_Pos 1U /*! & lt; FPCCR: privilege level bit Position */
#define FPU_FPCCR_USER_Msk (1UL & lt; & lt; FPU_FPCCR_USER_Pos) /*! & lt; FPCCR: privilege level bit Mask */
#define FPU_FPCCR_LSPACT_Pos 0U /*! & lt; FPCCR: Lazy state preservation active bit Position */
#define FPU_FPCCR_LSPACT_Msk (1UL /* & lt; & lt; FPU_FPCCR_LSPACT_Pos*/) /*! & lt; FPCCR: Lazy state preservation active bit Mask */
/* Floating-Point Context Address Register Definitions */
#define FPU_FPCAR_ADDRESS_Pos 3U /*! & lt; FPCAR: ADDRESS bit Position */
#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL & lt; & lt; FPU_FPCAR_ADDRESS_Pos) /*! & lt; FPCAR: ADDRESS bit Mask */
/* Floating-Point Default Status Control Register Definitions */
#define FPU_FPDSCR_AHP_Pos 26U /*! & lt; FPDSCR: AHP bit Position */
#define FPU_FPDSCR_AHP_Msk (1UL & lt; & lt; FPU_FPDSCR_AHP_Pos) /*! & lt; FPDSCR: AHP bit Mask */
#define FPU_FPDSCR_DN_Pos 25U /*! & lt; FPDSCR: DN bit Position */
#define FPU_FPDSCR_DN_Msk (1UL & lt; & lt; FPU_FPDSCR_DN_Pos) /*! & lt; FPDSCR: DN bit Mask */
#define FPU_FPDSCR_FZ_Pos 24U /*! & lt; FPDSCR: FZ bit Position */
#define FPU_FPDSCR_FZ_Msk (1UL & lt; & lt; FPU_FPDSCR_FZ_Pos) /*! & lt; FPDSCR: FZ bit Mask */
#define FPU_FPDSCR_RMode_Pos 22U /*! & lt; FPDSCR: RMode bit Position */
#define FPU_FPDSCR_RMode_Msk (3UL & lt; & lt; FPU_FPDSCR_RMode_Pos) /*! & lt; FPDSCR: RMode bit Mask */
/* Media and FP Feature Register 0 Definitions */
#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*! & lt; MVFR0: FP rounding modes bits Position */
#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL & lt; & lt; FPU_MVFR0_FP_rounding_modes_Pos) /*! & lt; MVFR0: FP rounding modes bits Mask */
#define FPU_MVFR0_Short_vectors_Pos 24U /*! & lt; MVFR0: Short vectors bits Position */
#define FPU_MVFR0_Short_vectors_Msk (0xFUL & lt; & lt; FPU_MVFR0_Short_vectors_Pos) /*! & lt; MVFR0: Short vectors bits Mask */
#define FPU_MVFR0_Square_root_Pos 20U /*! & lt; MVFR0: Square root bits Position */
#define FPU_MVFR0_Square_root_Msk (0xFUL & lt; & lt; FPU_MVFR0_Square_root_Pos) /*! & lt; MVFR0: Square root bits Mask */
#define FPU_MVFR0_Divide_Pos 16U /*! & lt; MVFR0: Divide bits Position */
#define FPU_MVFR0_Divide_Msk (0xFUL & lt; & lt; FPU_MVFR0_Divide_Pos) /*! & lt; MVFR0: Divide bits Mask */
#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*! & lt; MVFR0: FP exception trapping bits Position */
#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL & lt; & lt; FPU_MVFR0_FP_excep_trapping_Pos) /*! & lt; MVFR0: FP exception trapping bits Mask */
#define FPU_MVFR0_Double_precision_Pos 8U /*! & lt; MVFR0: Double-precision bits Position */
#define FPU_MVFR0_Double_precision_Msk (0xFUL & lt; & lt; FPU_MVFR0_Double_precision_Pos) /*! & lt; MVFR0: Double-precision bits Mask */
#define FPU_MVFR0_Single_precision_Pos 4U /*! & lt; MVFR0: Single-precision bits Position */
#define FPU_MVFR0_Single_precision_Msk (0xFUL & lt; & lt; FPU_MVFR0_Single_precision_Pos) /*! & lt; MVFR0: Single-precision bits Mask */
#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*! & lt; MVFR0: A_SIMD registers bits Position */
#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /* & lt; & lt; FPU_MVFR0_A_SIMD_registers_Pos*/) /*! & lt; MVFR0: A_SIMD registers bits Mask */
/* Media and FP Feature Register 1 Definitions */
#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*! & lt; MVFR1: FP fused MAC bits Position */
#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL & lt; & lt; FPU_MVFR1_FP_fused_MAC_Pos) /*! & lt; MVFR1: FP fused MAC bits Mask */
#define FPU_MVFR1_FP_HPFP_Pos 24U /*! & lt; MVFR1: FP HPFP bits Position */
#define FPU_MVFR1_FP_HPFP_Msk (0xFUL & lt; & lt; FPU_MVFR1_FP_HPFP_Pos) /*! & lt; MVFR1: FP HPFP bits Mask */
#define FPU_MVFR1_D_NaN_mode_Pos 4U /*! & lt; MVFR1: D_NaN mode bits Position */
#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL & lt; & lt; FPU_MVFR1_D_NaN_mode_Pos) /*! & lt; MVFR1: D_NaN mode bits Mask */
#define FPU_MVFR1_FtZ_mode_Pos 0U /*! & lt; MVFR1: FtZ mode bits Position */
#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /* & lt; & lt; FPU_MVFR1_FtZ_mode_Pos*/) /*! & lt; MVFR1: FtZ mode bits Mask */
/*@} end of group CMSIS_FPU */
#endif
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Type definitions for the Core Debug Registers
@{
*/
/**
\brief Structure type to access the Core Debug Register (CoreDebug).
*/
typedef struct
{
__IOM uint32_t DHCSR; /*! & lt; Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /*! & lt; Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /*! & lt; Offset: 0x008 (R/W) Debug Core Register Data Register */
__IOM uint32_t DEMCR; /*! & lt; Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
} CoreDebug_Type;
/* Debug Halting Control and Status Register Definitions */
#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*! & lt; CoreDebug DHCSR: DBGKEY Position */
#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL & lt; & lt; CoreDebug_DHCSR_DBGKEY_Pos) /*! & lt; CoreDebug DHCSR: DBGKEY Mask */
#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*! & lt; CoreDebug DHCSR: S_RESET_ST Position */
#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL & lt; & lt; CoreDebug_DHCSR_S_RESET_ST_Pos) /*! & lt; CoreDebug DHCSR: S_RESET_ST Mask */
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*! & lt; CoreDebug DHCSR: S_RETIRE_ST Position */
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL & lt; & lt; CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*! & lt; CoreDebug DHCSR: S_RETIRE_ST Mask */
#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*! & lt; CoreDebug DHCSR: S_LOCKUP Position */
#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL & lt; & lt; CoreDebug_DHCSR_S_LOCKUP_Pos) /*! & lt; CoreDebug DHCSR: S_LOCKUP Mask */
#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*! & lt; CoreDebug DHCSR: S_SLEEP Position */
#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL & lt; & lt; CoreDebug_DHCSR_S_SLEEP_Pos) /*! & lt; CoreDebug DHCSR: S_SLEEP Mask */
#define CoreDebug_DHCSR_S_HALT_Pos 17U /*! & lt; CoreDebug DHCSR: S_HALT Position */
#define CoreDebug_DHCSR_S_HALT_Msk (1UL & lt; & lt; CoreDebug_DHCSR_S_HALT_Pos) /*! & lt; CoreDebug DHCSR: S_HALT Mask */
#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*! & lt; CoreDebug DHCSR: S_REGRDY Position */
#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL & lt; & lt; CoreDebug_DHCSR_S_REGRDY_Pos) /*! & lt; CoreDebug DHCSR: S_REGRDY Mask */
#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*! & lt; CoreDebug DHCSR: C_SNAPSTALL Position */
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL & lt; & lt; CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*! & lt; CoreDebug DHCSR: C_SNAPSTALL Mask */
#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*! & lt; CoreDebug DHCSR: C_MASKINTS Position */
#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL & lt; & lt; CoreDebug_DHCSR_C_MASKINTS_Pos) /*! & lt; CoreDebug DHCSR: C_MASKINTS Mask */
#define CoreDebug_DHCSR_C_STEP_Pos 2U /*! & lt; CoreDebug DHCSR: C_STEP Position */
#define CoreDebug_DHCSR_C_STEP_Msk (1UL & lt; & lt; CoreDebug_DHCSR_C_STEP_Pos) /*! & lt; CoreDebug DHCSR: C_STEP Mask */
#define CoreDebug_DHCSR_C_HALT_Pos 1U /*! & lt; CoreDebug DHCSR: C_HALT Position */
#define CoreDebug_DHCSR_C_HALT_Msk (1UL & lt; & lt; CoreDebug_DHCSR_C_HALT_Pos) /*! & lt; CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*! & lt; CoreDebug DHCSR: C_DEBUGEN Position */
#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /* & lt; & lt; CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*! & lt; CoreDebug DHCSR: C_DEBUGEN Mask */
/* Debug Core Register Selector Register Definitions */
#define CoreDebug_DCRSR_REGWnR_Pos 16U /*! & lt; CoreDebug DCRSR: REGWnR Position */
#define CoreDebug_DCRSR_REGWnR_Msk (1UL & lt; & lt; CoreDebug_DCRSR_REGWnR_Pos) /*! & lt; CoreDebug DCRSR: REGWnR Mask */
#define CoreDebug_DCRSR_REGSEL_Pos 0U /*! & lt; CoreDebug DCRSR: REGSEL Position */
#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /* & lt; & lt; CoreDebug_DCRSR_REGSEL_Pos*/) /*! & lt; CoreDebug DCRSR: REGSEL Mask */
/* Debug Exception and Monitor Control Register Definitions */
#define CoreDebug_DEMCR_TRCENA_Pos 24U /*! & lt; CoreDebug DEMCR: TRCENA Position */
#define CoreDebug_DEMCR_TRCENA_Msk (1UL & lt; & lt; CoreDebug_DEMCR_TRCENA_Pos) /*! & lt; CoreDebug DEMCR: TRCENA Mask */
#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*! & lt; CoreDebug DEMCR: MON_REQ Position */
#define CoreDebug_DEMCR_MON_REQ_Msk (1UL & lt; & lt; CoreDebug_DEMCR_MON_REQ_Pos) /*! & lt; CoreDebug DEMCR: MON_REQ Mask */
#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*! & lt; CoreDebug DEMCR: MON_STEP Position */
#define CoreDebug_DEMCR_MON_STEP_Msk (1UL & lt; & lt; CoreDebug_DEMCR_MON_STEP_Pos) /*! & lt; CoreDebug DEMCR: MON_STEP Mask */
#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*! & lt; CoreDebug DEMCR: MON_PEND Position */
#define CoreDebug_DEMCR_MON_PEND_Msk (1UL & lt; & lt; CoreDebug_DEMCR_MON_PEND_Pos) /*! & lt; CoreDebug DEMCR: MON_PEND Mask */
#define CoreDebug_DEMCR_MON_EN_Pos 16U /*! & lt; CoreDebug DEMCR: MON_EN Position */
#define CoreDebug_DEMCR_MON_EN_Msk (1UL & lt; & lt; CoreDebug_DEMCR_MON_EN_Pos) /*! & lt; CoreDebug DEMCR: MON_EN Mask */
#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*! & lt; CoreDebug DEMCR: VC_HARDERR Position */
#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL & lt; & lt; CoreDebug_DEMCR_VC_HARDERR_Pos) /*! & lt; CoreDebug DEMCR: VC_HARDERR Mask */
#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*! & lt; CoreDebug DEMCR: VC_INTERR Position */
#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL & lt; & lt; CoreDebug_DEMCR_VC_INTERR_Pos) /*! & lt; CoreDebug DEMCR: VC_INTERR Mask */
#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*! & lt; CoreDebug DEMCR: VC_BUSERR Position */
#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL & lt; & lt; CoreDebug_DEMCR_VC_BUSERR_Pos) /*! & lt; CoreDebug DEMCR: VC_BUSERR Mask */
#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*! & lt; CoreDebug DEMCR: VC_STATERR Position */
#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL & lt; & lt; CoreDebug_DEMCR_VC_STATERR_Pos) /*! & lt; CoreDebug DEMCR: VC_STATERR Mask */
#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*! & lt; CoreDebug DEMCR: VC_CHKERR Position */
#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL & lt; & lt; CoreDebug_DEMCR_VC_CHKERR_Pos) /*! & lt; CoreDebug DEMCR: VC_CHKERR Mask */
#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*! & lt; CoreDebug DEMCR: VC_NOCPERR Position */
#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL & lt; & lt; CoreDebug_DEMCR_VC_NOCPERR_Pos) /*! & lt; CoreDebug DEMCR: VC_NOCPERR Mask */
#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*! & lt; CoreDebug DEMCR: VC_MMERR Position */
#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL & lt; & lt; CoreDebug_DEMCR_VC_MMERR_Pos) /*! & lt; CoreDebug DEMCR: VC_MMERR Mask */
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*! & lt; CoreDebug DEMCR: VC_CORERESET Position */
#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /* & lt; & lt; CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*! & lt; CoreDebug DEMCR: VC_CORERESET Mask */
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value & lt; & lt; field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) & gt; & gt; field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M4 Hardware */
#define SCS_BASE (0xE000E000UL) /*! & lt; System Control Space Base Address */
#define ITM_BASE (0xE0000000UL) /*! & lt; ITM Base Address */
#define DWT_BASE (0xE0001000UL) /*! & lt; DWT Base Address */
#define TPI_BASE (0xE0040000UL) /*! & lt; TPI Base Address */
#define CoreDebug_BASE (0xE000EDF0UL) /*! & lt; Core Debug Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*! & lt; SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*! & lt; NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*! & lt; System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*! & lt; System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*! & lt; SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*! & lt; SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*! & lt; NVIC configuration struct */
#define ITM ((ITM_Type *) ITM_BASE ) /*! & lt; ITM configuration struct */
#define DWT ((DWT_Type *) DWT_BASE ) /*! & lt; DWT configuration struct */
#define TPI ((TPI_Type *) TPI_BASE ) /*! & lt; TPI configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*! & lt; Core Debug configuration struct */
#if (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*! & lt; Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*! & lt; Memory Protection Unit */
#endif
#if (__FPU_PRESENT == 1U)
#define FPU_BASE (SCS_BASE + 0x0F30UL) /*! & lt; Floating Point Unit */
#define FPU ((FPU_Type *) FPU_BASE ) /*! & lt; Floating Point Unit */
#endif
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Debug Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/**
\brief Set Priority Grouping
\details Sets the priority grouping field using the required unlock sequence.
The parameter PriorityGroup is assigned to the field SCB- & gt; AIRCR [10:8] PRIGROUP field.
Only values from 0..7 are used.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB- & gt; AIRCR; /* read old register configuration */
reg_value & = ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
reg_value = (reg_value |
((uint32_t)0x5FAUL & lt; & lt; SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp & lt; & lt; 8U) ); /* Insert write key and priorty group */
SCB- & gt; AIRCR = reg_value;
}
/**
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB- & gt; AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
{
return ((uint32_t)((SCB- & gt; AIRCR & SCB_AIRCR_PRIGROUP_Msk) & gt; & gt; SCB_AIRCR_PRIGROUP_Pos));
}
/**
\brief Enable External Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC- & gt; ISER[(((uint32_t)(int32_t)IRQn) & gt; & gt; 5UL)] = (uint32_t)(1UL & lt; & lt; (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Disable External Interrupt
\details Disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC- & gt; ICER[(((uint32_t)(int32_t)IRQn) & gt; & gt; 5UL)] = (uint32_t)(1UL & lt; & lt; (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Get Pending Interrupt
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t)(((NVIC- & gt; ISPR[(((uint32_t)(int32_t)IRQn) & gt; & gt; 5UL)] & (1UL & lt; & lt; (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC- & gt; ISPR[(((uint32_t)(int32_t)IRQn) & gt; & gt; 5UL)] = (uint32_t)(1UL & lt; & lt; (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC- & gt; ICPR[(((uint32_t)(int32_t)IRQn) & gt; & gt; 5UL)] = (uint32_t)(1UL & lt; & lt; (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Get Active Interrupt
\details Reads the active register in NVIC and returns the active bit.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
*/
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
{
return((uint32_t)(((NVIC- & gt; IABR[(((uint32_t)(int32_t)IRQn) & gt; & gt; 5UL)] & (1UL & lt; & lt; (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Interrupt Priority
\details Sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) & lt; 0)
{
SCB- & gt; SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority & lt; & lt; (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
else
{
NVIC- & gt; IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority & lt; & lt; (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of an interrupt.
The interrupt number can be positive to specify an external (device specific) interrupt,
or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) & lt; 0)
{
return(((uint32_t)SCB- & gt; SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] & gt; & gt; (8U - __NVIC_PRIO_BITS)));
}
else
{
return(((uint32_t)NVIC- & gt; IP[((uint32_t)(int32_t)IRQn)] & gt; & gt; (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) & gt; (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) & lt; (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL & lt; & lt; (PreemptPriorityBits)) - 1UL)) & lt; & lt; SubPriorityBits) |
((SubPriority & (uint32_t)((1UL & lt; & lt; (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) & gt; (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) & lt; (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority & gt; & gt; SubPriorityBits) & (uint32_t)((1UL & lt; & lt; (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL & lt; & lt; (SubPriorityBits )) - 1UL);
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB- & gt; AIRCR = (uint32_t)((0x5FAUL & lt; & lt; SCB_AIRCR_VECTKEY_Pos) |
(SCB- & gt; AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable & lt; b & gt; __Vendor_SysTickConfig & lt; /b & gt; is set to 1, then the
function & lt; b & gt; SysTick_Config & lt; /b & gt; is not included. In this case, the file & lt; b & gt; & lt; i & gt; device & lt; /i & gt; .h & lt; /b & gt;
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) & gt; SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick- & gt; LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL & lt; & lt; __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick- & gt; VAL = 0UL; /* Load the SysTick Counter Value */
SysTick- & gt; CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
/* ##################################### Debug In/Output function ########################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_core_DebugFunctions ITM Functions
\brief Functions that access the ITM debug interface.
@{
*/
extern volatile int32_t ITM_RxBuffer; /*! & lt; External variable to receive characters. */
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*! & lt; Value identifying \ref ITM_RxBuffer is ready for next character. */
/**
\brief ITM Send Character
\details Transmits a character via the ITM channel 0, and
\li Just returns when no debugger is connected that has booked the output.
\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
\param [in] ch Character to transmit.
\returns Character to transmit.
*/
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
{
if (((ITM- & gt; TCR & ITM_TCR_ITMENA_Msk) != 0UL) & & /* ITM enabled */
((ITM- & gt; TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
{
while (ITM- & gt; PORT[0U].u32 == 0UL)
{
__NOP();
}
ITM- & gt; PORT[0U].u8 = (uint8_t)ch;
}
return (ch);
}
/**
\brief ITM Receive Character
\details Inputs a character via the external variable \ref ITM_RxBuffer.
\return Received character.
\return -1 No character pending.
*/
__STATIC_INLINE int32_t ITM_ReceiveChar (void)
{
int32_t ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
{
ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
}
return (ch);
}
/**
\brief ITM Check Character
\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
\return 0 No character available.
\return 1 Character available.
*/
__STATIC_INLINE int32_t ITM_CheckChar (void)
{
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
{
return (0); /* no character available */
}
else
{
return (1); /* character available */
}
}
/*@} end of CMSIS_core_DebugFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM4_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
/**************************************************************************//**
* @file cmsis_armcc_V6.h
* @brief CMSIS Cortex-M Core Function/Instruction Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS " AS IS "
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CMSIS_ARMCC_V6_H
#define __CMSIS_ARMCC_V6_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ( " cpsie i " : : : " memory " );
}
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ( " cpsid i " : : : " memory " );
}
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ( " MRS %0, control " : " =r " (result) );
return(result);
}
#if (__ARM_FEATURE_CMSE == 3U)
/**
\brief Get Control Register (non-secure)
\details Returns the content of the non-secure Control Register when in secure mode.
\return non-secure Control Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t result;
__ASM volatile ( " MRS %0, control_ns " : " =r " (result) );
return(result);
}
#endif
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ( " MSR control, %0 " : : " r " (control) : " memory " );
}
#if (__ARM_FEATURE_CMSE == 3U)
/**
\brief Set Control Register (non-secure)
\details Writes the given value to the non-secure Control Register when in secure state.
\param [in] control Control Register value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
{
__ASM volatile ( " MSR control_ns, %0 " : : " r " (control) : " memory " );
}
#endif
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ( " MRS %0, ipsr " : " =r " (result) );
return(result);
}
#if (__ARM_FEATURE_CMSE == 3U)
/**
\brief Get IPSR Register (non-secure)
\details Returns the content of the non-secure IPSR Register when in secure state.
\return IPSR Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void)
{
uint32_t result;
__ASM volatile ( " MRS %0, ipsr_ns " : " =r " (result) );
return(result);
}
#endif
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ( " MRS %0, apsr " : " =r " (result) );
return(result);
}
#if (__ARM_FEATURE_CMSE == 3U)
/**
\brief Get APSR Register (non-secure)
\details Returns the content of the non-secure APSR Register when in secure state.
\return APSR Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void)
{
uint32_t result;
__ASM volatile ( " MRS %0, apsr_ns " : " =r " (result) );
return(result);
}
#endif
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ( " MRS %0, xpsr " : " =r " (result) );
return(result);
}
#if (__ARM_FEATURE_CMSE == 3U)
/**
\brief Get xPSR Register (non-secure)
\details Returns the content of the non-secure xPSR Register when in secure state.
\return xPSR Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void)
{
uint32_t result;
__ASM volatile ( " MRS %0, xpsr_ns " : " =r " (result) );
return(result);
}
#endif
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ( " MRS %0, psp " : " =r " (result) );
return(result);
}
#if (__ARM_FEATURE_CMSE == 3U)
/**
\brief Get Process Stack Pointer (non-secure)
\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
\return PSP Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
{
register uint32_t result;
__ASM volatile ( " MRS %0, psp_ns " : " =r " (result) );
return(result);
}
#endif
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ( " MSR psp, %0 " : : " r " (topOfProcStack) : " sp " );
}
#if (__ARM_FEATURE_CMSE == 3U)
/**
\brief Set Process Stack Pointer (non-secure)
\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
{
__ASM volatile ( " MSR psp_ns, %0 " : : " r " (topOfProcStack) : " sp " );
}
#endif
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ( " MRS %0, msp " : " =r " (result) );
return(result);
}
#if (__ARM_FEATURE_CMSE == 3U)
/**
\brief Get Main Stack Pointer (non-secure)
\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
\return MSP Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
{
register uint32_t result;
__ASM volatile ( " MRS %0, msp_ns " : " =r " (result) );
return(result);
}
#endif
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ( " MSR msp, %0 " : : " r " (topOfMainStack) : " sp " );
}
#if (__ARM_FEATURE_CMSE == 3U)
/**
\brief Set Main Stack Pointer (non-secure)
\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
{
__ASM volatile ( " MSR msp_ns, %0 " : : " r " (topOfMainStack) : " sp " );
}
#endif
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ( " MRS %0, primask " : " =r " (result) );
return(result);
}
#if (__ARM_FEATURE_CMSE == 3U)
/**
\brief Get Priority Mask (non-secure)
\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
\return Priority Mask value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t result;
__ASM volatile ( " MRS %0, primask_ns " : " =r " (result) );
return(result);
}
#endif
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ( " MSR primask, %0 " : : " r " (priMask) : " memory " );
}
#if (__ARM_FEATURE_CMSE == 3U)
/**
\brief Set Priority Mask (non-secure)
\details Assigns the given value to the non-secure Priority Mask Register when in secure state.
\param [in] priMask Priority Mask
*/
__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
{
__ASM volatile ( " MSR primask_ns, %0 " : : " r " (priMask) : " memory " );
}
#endif
#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex & gt; =3 */
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ( " cpsie f " : : : " memory " );
}
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ( " cpsid f " : : : " memory " );
}
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ( " MRS %0, basepri " : " =r " (result) );
return(result);
}
#if (__ARM_FEATURE_CMSE == 3U)
/**
\brief Get Base Priority (non-secure)
\details Returns the current value of the non-secure Base Priority register when in secure state.
\return Base Priority register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t result;
__ASM volatile ( " MRS %0, basepri_ns " : " =r " (result) );
return(result);
}
#endif
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ( " MSR basepri, %0 " : : " r " (value) : " memory " );
}
#if (__ARM_FEATURE_CMSE == 3U)
/**
\brief Set Base Priority (non-secure)
\details Assigns the given value to the non-secure Base Priority register when in secure state.
\param [in] basePri Base Priority value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value)
{
__ASM volatile ( " MSR basepri_ns, %0 " : : " r " (value) : " memory " );
}
#endif
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
{
__ASM volatile ( " MSR basepri_max, %0 " : : " r " (value) : " memory " );
}
#if (__ARM_FEATURE_CMSE == 3U)
/**
\brief Set Base Priority with condition (non_secure)
\details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value)
{
__ASM volatile ( " MSR basepri_max_ns, %0 " : : " r " (value) : " memory " );
}
#endif
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ( " MRS %0, faultmask " : " =r " (result) );
return(result);
}
#if (__ARM_FEATURE_CMSE == 3U)
/**
\brief Get Fault Mask (non-secure)
\details Returns the current value of the non-secure Fault Mask register when in secure state.
\return Fault Mask register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t result;
__ASM volatile ( " MRS %0, faultmask_ns " : " =r " (result) );
return(result);
}
#endif
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ( " MSR faultmask, %0 " : : " r " (faultMask) : " memory " );
}
#if (__ARM_FEATURE_CMSE == 3U)
/**
\brief Set Fault Mask (non-secure)
\details Assigns the given value to the non-secure Fault Mask register when in secure state.
\param [in] faultMask Fault Mask value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
{
__ASM volatile ( " MSR faultmask_ns, %0 " : : " r " (faultMask) : " memory " );
}
#endif
#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */
#if (__ARM_ARCH_8M__ == 1U)
/**
\brief Get Process Stack Pointer Limit
\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
\return PSPLIM Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
{
register uint32_t result;
__ASM volatile ( " MRS %0, psplim " : " =r " (result) );
return(result);
}
#if (__ARM_FEATURE_CMSE == 3U) & & (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */
/**
\brief Get Process Stack Pointer Limit (non-secure)
\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
\return PSPLIM Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
{
register uint32_t result;
__ASM volatile ( " MRS %0, psplim_ns " : " =r " (result) );
return(result);
}
#endif
/**
\brief Set Process Stack Pointer Limit
\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
{
__ASM volatile ( " MSR psplim, %0 " : : " r " (ProcStackPtrLimit));
}
#if (__ARM_FEATURE_CMSE == 3U) & & (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */
/**
\brief Set Process Stack Pointer (non-secure)
\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
{
__ASM volatile ( " MSR psplim_ns, %0\n " : : " r " (ProcStackPtrLimit));
}
#endif
/**
\brief Get Main Stack Pointer Limit
\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
\return MSPLIM Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
{
register uint32_t result;
__ASM volatile ( " MRS %0, msplim " : " =r " (result) );
return(result);
}
#if (__ARM_FEATURE_CMSE == 3U) & & (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */
/**
\brief Get Main Stack Pointer Limit (non-secure)
\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
\return MSPLIM Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
{
register uint32_t result;
__ASM volatile ( " MRS %0, msplim_ns " : " =r " (result) );
return(result);
}
#endif
/**
\brief Set Main Stack Pointer Limit
\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
\param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
{
__ASM volatile ( " MSR msplim, %0 " : : " r " (MainStackPtrLimit));
}
#if (__ARM_FEATURE_CMSE == 3U) & & (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */
/**
\brief Set Main Stack Pointer Limit (non-secure)
\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
\param [in] MainStackPtrLimit Main Stack Pointer value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
{
__ASM volatile ( " MSR msplim_ns, %0 " : : " r " (MainStackPtrLimit));
}
#endif
#endif /* (__ARM_ARCH_8M__ == 1U) */
#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex & gt; =4 */
/**
\brief Get FPSCR
\details eturns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
#define __get_FPSCR __builtin_arm_get_fpscr
#if 0
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1U) & & (__FPU_USED == 1U)
uint32_t result;
__ASM volatile ( " " ); /* Empty asm statement works as a scheduling barrier */
__ASM volatile ( " VMRS %0, fpscr " : " =r " (result) );
__ASM volatile ( " " );
return(result);
#else
return(0);
#endif
}
#endif
#if (__ARM_FEATURE_CMSE == 3U)
/**
\brief Get FPSCR (non-secure)
\details Returns the current value of the non-secure Floating Point Status/Control register when in secure state.
\return Floating Point Status/Control register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void)
{
#if (__FPU_PRESENT == 1U) & & (__FPU_USED == 1U)
uint32_t result;
__ASM volatile ( " " ); /* Empty asm statement works as a scheduling barrier */
__ASM volatile ( " VMRS %0, fpscr_ns " : " =r " (result) );
__ASM volatile ( " " );
return(result);
#else
return(0);
#endif
}
#endif
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
#define __set_FPSCR __builtin_arm_set_fpscr
#if 0
__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1U) & & (__FPU_USED == 1U)
__ASM volatile ( " " ); /* Empty asm statement works as a scheduling barrier */
__ASM volatile ( " VMSR fpscr, %0 " : : " r " (fpscr) : " vfpcc " );
__ASM volatile ( " " );
#endif
}
#endif
#if (__ARM_FEATURE_CMSE == 3U)
/**
\brief Set FPSCR (non-secure)
\details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1U) & & (__FPU_USED == 1U)
__ASM volatile ( " " ); /* Empty asm statement works as a scheduling barrier */
__ASM volatile ( " VMSR fpscr_ns, %0 " : : " r " (fpscr) : " vfpcc " );
__ASM volatile ( " " );
#endif
}
#endif
#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/* Define macros for porting to both thumb1 and thumb2.
* For thumb1, use low register (r0-r7), specified by constraint " l "
* Otherwise, use general registers, specified by constraint " r " */
#if defined (__thumb__) & & !defined (__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) " =l " (r)
#define __CMSIS_GCC_USE_REG(r) " l " (r)
#else
#define __CMSIS_GCC_OUT_REG(r) " =r " (r)
#define __CMSIS_GCC_USE_REG(r) " r " (r)
#endif
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __builtin_arm_nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __builtin_arm_wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __builtin_arm_wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __builtin_arm_sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() __builtin_arm_isb(0xF);
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __builtin_arm_dsb(0xF);
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __builtin_arm_dmb(0xF);
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __builtin_bswap32
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */
#if 0
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ( " rev16 %0, %1 " : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
#endif
/**
\brief Reverse byte order in signed short value
\details Reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
/* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */
__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
int32_t result;
__ASM volatile ( " revsh %0, %1 " : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 & gt; & gt; op2) | (op1 & lt; & lt; (32U - op2));
}
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ( " bkpt " #value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
/* ToDo: ARMCC_V6: check if __builtin_arm_rbit is supported */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex & gt; =3 */
__ASM volatile ( " rbit %0, %1 " : " =r " (result) : " r " (value) );
#else
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value & gt; & gt; = 1U; value; value & gt; & gt; = 1U)
{
result & lt; & lt; = 1U;
result |= value & 1U;
s--;
}
result & lt; & lt; = s; /* shift when v's highest bits are zero */
#endif
return(result);
}
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __builtin_clz
#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex & gt; =3 */
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB (uint8_t)__builtin_arm_ldrex
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH (uint16_t)__builtin_arm_ldrex
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW (uint32_t)__builtin_arm_ldrex
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB (uint32_t)__builtin_arm_strex
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH (uint32_t)__builtin_arm_strex
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW (uint32_t)__builtin_arm_strex
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __builtin_arm_clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
/*#define __SSAT __builtin_arm_ssat*/
#define __SSAT(ARG1,ARG2) \
({ \
int32_t __RES, __ARG1 = (ARG1); \
__ASM ( " ssat %0, %1, %2 " : " =r " (__RES) : " I " (ARG2), " r " (__ARG1) ); \
__RES; \
})
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __builtin_arm_usat
#if 0
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ( " usat %0, %1, %2 " : " =r " (__RES) : " I " (ARG2), " r " (__ARG1) ); \
__RES; \
})
#endif
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM volatile ( " rrx %0, %1 " : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
{
uint32_t result;
__ASM volatile ( " ldrbt %0, %1 " : " =r " (result) : " Q " (*ptr) );
return ((uint8_t) result); /* Add explicit type cast here */
}
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
{
uint32_t result;
__ASM volatile ( " ldrht %0, %1 " : " =r " (result) : " Q " (*ptr) );
return ((uint16_t) result); /* Add explicit type cast here */
}
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
{
uint32_t result;
__ASM volatile ( " ldrt %0, %1 " : " =r " (result) : " Q " (*ptr) );
return(result);
}
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ( " strbt %1, %0 " : " =Q " (*ptr) : " r " ((uint32_t)value) );
}
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ( " strht %1, %0 " : " =Q " (*ptr) : " r " ((uint32_t)value) );
}
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ( " strt %1, %0 " : " =Q " (*ptr) : " r " (value) );
}
#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */
#if (__ARM_ARCH_8M__ == 1U)
/**
\brief Load-Acquire (8 bit)
\details Executes a LDAB instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t result;
__ASM volatile ( " ldab %0, %1 " : " =r " (result) : " Q " (*ptr) );
return ((uint8_t) result);
}
/**
\brief Load-Acquire (16 bit)
\details Executes a LDAH instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t result;
__ASM volatile ( " ldah %0, %1 " : " =r " (result) : " Q " (*ptr) );
return ((uint16_t) result);
}
/**
\brief Load-Acquire (32 bit)
\details Executes a LDA instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t result;
__ASM volatile ( " lda %0, %1 " : " =r " (result) : " Q " (*ptr) );
return(result);
}
/**
\brief Store-Release (8 bit)
\details Executes a STLB instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ( " stlb %1, %0 " : " =Q " (*ptr) : " r " ((uint32_t)value) );
}
/**
\brief Store-Release (16 bit)
\details Executes a STLH instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ( " stlh %1, %0 " : " =Q " (*ptr) : " r " ((uint32_t)value) );
}
/**
\brief Store-Release (32 bit)
\details Executes a STL instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ( " stl %1, %0 " : " =Q " (*ptr) : " r " ((uint32_t)value) );
}
/**
\brief Load-Acquire Exclusive (8 bit)
\details Executes a LDAB exclusive instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDAEXB (uint8_t)__builtin_arm_ldaex
/**
\brief Load-Acquire Exclusive (16 bit)
\details Executes a LDAH exclusive instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDAEXH (uint16_t)__builtin_arm_ldaex
/**
\brief Load-Acquire Exclusive (32 bit)
\details Executes a LDA exclusive instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDAEX (uint32_t)__builtin_arm_ldaex
/**
\brief Store-Release Exclusive (8 bit)
\details Executes a STLB exclusive instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STLEXB (uint32_t)__builtin_arm_stlex
/**
\brief Store-Release Exclusive (16 bit)
\details Executes a STLH exclusive instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STLEXH (uint32_t)__builtin_arm_stlex
/**
\brief Store-Release Exclusive (32 bit)
\details Executes a STL exclusive instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STLEX (uint32_t)__builtin_arm_stlex
#endif /* (__ARM_ARCH_8M__ == 1U) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if (__ARM_FEATURE_DSP == 1U) /* ToDo: ARMCC_V6: This should be ARCH & gt; = ARMv7-M + SIMD */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " sadd8 %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " qadd8 %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " shadd8 %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " uadd8 %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " uqadd8 %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " uhadd8 %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " ssub8 %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " qsub8 %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " shsub8 %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " usub8 %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " uqsub8 %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " uhsub8 %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " sadd16 %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " qadd16 %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " shadd16 %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " uadd16 %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " uqadd16 %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " uhadd16 %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " ssub16 %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " qsub16 %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " shsub16 %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " usub16 %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " uqsub16 %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " uhsub16 %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " sasx %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " qasx %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " shasx %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " uasx %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " uqasx %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " uhasx %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " ssax %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " qsax %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " shsax %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " usax %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " uqsax %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " uhsax %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " usad8 %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ( " usada8 %0, %1, %2, %3 " : " =r " (result) : " r " (op1), " r " (op2), " r " (op3) );
return(result);
}
#define __SSAT16(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ( " ssat16 %0, %1, %2 " : " =r " (__RES) : " I " (ARG2), " r " (__ARG1) ); \
__RES; \
})
#define __USAT16(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ( " usat16 %0, %1, %2 " : " =r " (__RES) : " I " (ARG2), " r " (__ARG1) ); \
__RES; \
})
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ( " uxtb16 %0, %1 " : " =r " (result) : " r " (op1));
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " uxtab16 %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ( " sxtb16 %0, %1 " : " =r " (result) : " r " (op1));
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " sxtab16 %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " smuad %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " smuadx %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ( " smlad %0, %1, %2, %3 " : " =r " (result) : " r " (op1), " r " (op2), " r " (op3) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ( " smladx %0, %1, %2, %3 " : " =r " (result) : " r " (op1), " r " (op2), " r " (op3) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ /* Little endian */
__ASM volatile ( " smlald %0, %1, %2, %3 " : " =r " (llr.w32[0]), " =r " (llr.w32[1]): " r " (op1), " r " (op2) , " 0 " (llr.w32[0]), " 1 " (llr.w32[1]) );
#else /* Big endian */
__ASM volatile ( " smlald %0, %1, %2, %3 " : " =r " (llr.w32[1]), " =r " (llr.w32[0]): " r " (op1), " r " (op2) , " 0 " (llr.w32[1]), " 1 " (llr.w32[0]) );
#endif
return(llr.w64);
}
__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ /* Little endian */
__ASM volatile ( " smlaldx %0, %1, %2, %3 " : " =r " (llr.w32[0]), " =r " (llr.w32[1]): " r " (op1), " r " (op2) , " 0 " (llr.w32[0]), " 1 " (llr.w32[1]) );
#else /* Big endian */
__ASM volatile ( " smlaldx %0, %1, %2, %3 " : " =r " (llr.w32[1]), " =r " (llr.w32[0]): " r " (op1), " r " (op2) , " 0 " (llr.w32[1]), " 1 " (llr.w32[0]) );
#endif
return(llr.w64);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " smusd %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " smusdx %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ( " smlsd %0, %1, %2, %3 " : " =r " (result) : " r " (op1), " r " (op2), " r " (op3) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ( " smlsdx %0, %1, %2, %3 " : " =r " (result) : " r " (op1), " r " (op2), " r " (op3) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ /* Little endian */
__ASM volatile ( " smlsld %0, %1, %2, %3 " : " =r " (llr.w32[0]), " =r " (llr.w32[1]): " r " (op1), " r " (op2) , " 0 " (llr.w32[0]), " 1 " (llr.w32[1]) );
#else /* Big endian */
__ASM volatile ( " smlsld %0, %1, %2, %3 " : " =r " (llr.w32[1]), " =r " (llr.w32[0]): " r " (op1), " r " (op2) , " 0 " (llr.w32[1]), " 1 " (llr.w32[0]) );
#endif
return(llr.w64);
}
__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ /* Little endian */
__ASM volatile ( " smlsldx %0, %1, %2, %3 " : " =r " (llr.w32[0]), " =r " (llr.w32[1]): " r " (op1), " r " (op2) , " 0 " (llr.w32[0]), " 1 " (llr.w32[1]) );
#else /* Big endian */
__ASM volatile ( " smlsldx %0, %1, %2, %3 " : " =r " (llr.w32[1]), " =r " (llr.w32[0]): " r " (op1), " r " (op2) , " 0 " (llr.w32[1]), " 1 " (llr.w32[0]) );
#endif
return(llr.w64);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ( " sel %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
{
int32_t result;
__ASM volatile ( " qadd %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
{
int32_t result;
__ASM volatile ( " qsub %0, %1, %2 " : " =r " (result) : " r " (op1), " r " (op2) );
return(result);
}
#define __PKHBT(ARG1,ARG2,ARG3) \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
__ASM ( " pkhbt %0, %1, %2, lsl %3 " : " =r " (__RES) : " r " (__ARG1), " r " (__ARG2), " I " (ARG3) ); \
__RES; \
})
#define __PKHTB(ARG1,ARG2,ARG3) \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
if (ARG3 == 0) \
__ASM ( " pkhtb %0, %1, %2 " : " =r " (__RES) : " r " (__ARG1), " r " (__ARG2) ); \
else \
__ASM ( " pkhtb %0, %1, %2, asr %3 " : " =r " (__RES) : " r " (__ARG1), " r " (__ARG2), " I " (ARG3) ); \
__RES; \
})
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
{
int32_t result;
__ASM volatile ( " smmla %0, %1, %2, %3 " : " =r " (result): " r " (op1), " r " (op2), " r " (op3) );
return(result);
}
#endif /* (__ARM_FEATURE_DSP == 1U) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_V6_H */