Ponieważ (LA-B972p) > Nie ma SM ani boardview to np. LA-B972P p.nr.: 790669-501 790669-001 for HP Pavilion 15-R G3 ENVY 15-R264DX (seria 200) SR23Y I5-5200U NV 820M Bios GD25b64bsig kbc KB9012QF-A4 charger BQ24738 popatrz w SM : 1. LA-B016P (ten sam kbc) Link lub 2. LA-A992P (ten sam ukł. wej. zasilania (z igiełką) - cewki plz2/ plz3 to uk. zasialnia +VCC Core na PU22 CSD9734cq oraz gl. driver PUZ1 TPS51624RS / str.50 SM -cweki plv2 to +VGA_Core na PUV1 RT8813 / str.53 Element PD1 to ESD.. https://obrazki.elektroda.pl/5060902900_1583425517_thumb.jpg
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Compal Confidential
Hasswell M/B Schematics Document
2
2
Intel ULV Processor with DDRIIIL
Date : 2014/02/08
3
3
Version 1.0
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/06/29
Deciphered Date
2011/06/29
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Cover Page
Document Number
Rev
0.1
LA-A992P
Thursday, March 20, 2014
Sheet
E
1
of
54
A
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C
D
E
Compal Confidential
Model Name : Haswell
1
VRAM*4
Single Rank
File Name :
LA-A992PR10
Nvidia
N15V-GM
17W
P37~P40
P32~P36
PCI-Ex4
Lane 7-Lane10
PCIe 2.0:5Gb/s
PCIe 3.0:8Gb/s
LVDS panel
RTD2132R
P20
CRT Conn
eDPx2
P15,16
DDR3L 1600MHz 1.35V
2.7Gb/s
P18
Haswell
Ultra Light & Thin
DDI
IT6513
P29
P29
SATA 3.0
GEN1 1.5Gb/s
GEN2 3Gb/s
GEN3 6Gb/s
Port 0
2.5 " SATA HDD
P22
ODD
P22
USB3.0 port
Port 1
P26
1168P BGA
HDMI
HDMI Conn
DDPB port
P19
1
DDR3-SO-DIMM X 2
Dual Channel
222.75MHz
(USW ULT)
USB3.0
5Gb/s
USB2.0
480Mb/s
Port 0
Port 0
2
2
PCI-E Card reader
RTS5239
10/100 1G LAN
8151/8166 Option
WLAN(MiniPCIe slot)
Lane 4
Port 1
PCI-E
PCIe 1.0:2.5Gb/s
PCIe 2.0:5Gb/s
P25
WLAN
P20
Camera
P19
Touch Screen
Port 3
Port 4
Port 3 (Reserved) USB2.0
480Mb/s
3
P27
P19
P24
Port 5
Port 3
P26
USB2.0 Port
Port 2
Lane 5
Lane 11 PCIe 1.0:2.5Gb/s
PCIe 2.0:5Gb/s
PCI-E
P23
USB2.0 port
3
SMBUS
1MHz
Int.KBD
Touch Pad
PS2
FAN
LPC
33MHz
ENE KB9012
P30
HDA
24MHz
HDA Aduio codec
ALC3227
TPM 1.2 @
SLB 9656 P28
Lid switch
Internal SPK
P25
Combo Jack
SPI
50MHz
4
SPI ROM
8M
4
P7
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/06/29
Deciphered Date
2011/06/29
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Block Diagrams
Rev
0.1
LA-A992P
Date:
A
B
C
D
Sheet
Thursday, March 20, 2014
E
2
of
54
A
B
C
D
DAX
Power rail
Control (EC)
Source (CPU)
+RTCVCC
X
X
VIN
X
X
BATT+
X
X
B+
X
X
+VL
EC_ON
X
+3VALW_EC
EC_ON
short@ : short pad , don't pop.
X
Part Number = DAZ14Z00100
PCB 14Z LA-A992P REV0 M/B 3
DESTINATION
ROYALTY HDMI W/LOGO+HDCP
Part Number = RO0000003HM
ROYALTY HDMI W/LOGO+HDCP
X
EC_ON
& lt; USB2.0 port & gt;
PCB & lt; BOM Structure & gt;
X
+3VALW
ZZZ1
@ is NO SMT part (empty)
X
X
+5VALW
1
X
+3VL
PCH_PWR_EN
X
SYSON
PM_SLP_S5#/PM_SLP_S4#
+5VS
SUSP#
PM_SLP_S3#
+3VS
SUSP#
PM_SLP_S3#
+1.5VS
SUSP#
PM_SLP_S3#
SUSP#
PM_SLP_S3#
+0.6V_0.675VS
SUSP#
VR12.5_VR_ON
CRT@,CRTEMI@ : Support CRT port
USB 2.0(right side)
USB 2.0(right side)
WLAN/BT
WLAN/BT
4
GCLK@ : Support GCLK
USB 2.0(right side)
3
LVDS@ : Support LVDS panel.
USB 2.0(right side)
2
ESD@ : ESD team request, must add.
USB 2.0/3.0(left side)
1
ZSO40@,ZSO50@ : Board ID config.
DIS@ : GPU BOM config.
USB 2.0/3.0(left side)
Camera
Camera
5
EMI@ : EMI team request, must add.
+1.05VS
Touch screen(Options)
Touch screen(Options)
6
X
X
1
X
7
eDP@,eDPEMI@ : Support eTP panel
2
Dis
0
RF@ : RF team request, must add.
+3V_PCH
X
UMA
USB2.0 port
@EMI@,@ESD@,@RF@ : Reserve , don't pop.
+1.35V_VDDQ
+VCC_CORE
E
45@
X
& lt; PCI-E,SATA,USB3.0 & gt;
UCPU1
2
+3V_PCH
+3VS
DESTINATION
Lane#
AP2
AH1
CPU
R=10K
R=2.2K
SMBCLK
SMBDATA
2N7002
PCH_SMBCLK
PCH_SMBDATA
+3V_PCH
AN1
AK1
SML0CLK
SML0DATA
SML1CLK
SML1DATA
SO‐DIMM A
SO‐DIMM B
R=1K
+3V_PCH
AU3
AH3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
+3VS
R=2.2K
R=2.2K
2N7002
EC_SMB_CK2
EC_SMB_DA2
+3VS
PCI-E
SATA
USB3.0
1
2
3
4
1
2
3
4
UMA
USB3.0
X
X
Dis
USB3.0
X
X
Card reader(PCI-E)
Card reader(PCI-E)
10/100/1000 LAN 10/100/1000 LAN
GPU(DIS only)
GPU(DIS only)
GPU(DIS only)
GPU(DIS only)
WLAN
X
ODD
2.5 " HDD
5
6
L3
L2
L1
L0
WLAN
X
ODD
2.5 " HDD
3
2
1
0
3
3
Thermal Sensor @
UK1:+3VALW_EC
+3VS
79
80
EC_SMB_CK2
EC_SMB_DA2
EC
eDP to LVDS bridge RTD2132R
+3VL
77
78
EC_SMB_CK1
EC_SMB_DA1
R=2.2K
R=100
BAT
Charger
G‐Sensor @
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/06/29
Deciphered Date
2011/06/29
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Notes List
Rev
0.1
LA-A992P
Sheet
Thursday, March 20, 2014
E
3
of
54
5
4
3
UCPU1A
& lt; 20 & gt;
& lt; 20 & gt;
& lt; 20 & gt;
& lt; 20 & gt;
& lt; 20 & gt;
& lt; 20 & gt;
& lt; 20 & gt;
& lt; 20 & gt;
D
& lt; HDMI & gt;
& lt; DP TO CRT & gt;
RC11
2
PCH_DPB_N2
PCH_DPB_P2
PCH_DPB_N1
PCH_DPB_P1
PCH_DPB_N0
PCH_DPB_P0
PCH_DPB_N3
PCH_DPB_P3
C54
C55
B58
C58
B55
A55
A57
B57
& lt; 29 & gt;
& lt; 29 & gt;
& lt; 29 & gt;
& lt; 29 & gt;
PCH_DPC_N0
PCH_DPC_P0
PCH_DPC_N1
PCH_DPC_P1
C51
C50
C53
B54
C49
B50
A53
B53
1 10K_0402_5% H_CPUPWRGD_R
DDI1_TXN0
DDI1_TXP0
DDI1_TXN1
DDI1_TXP1
DDI1_TXN2
DDI1_TXP2
DDI1_TXN3
DDI1_TXP3
2
L
HASWELL_MCP_E
C45
B46
A47
B47
EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1
DDI
EDP
CC97~CC102 must closed to connector not CPU
EDP_CPU_LANE_N0_C & lt; 18 & gt;
EDP_CPU_LANE_P0_C & lt; 18 & gt;
& lt; eDP & gt;
D
C47
C46
A49
B49
EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3
DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3
1
A45
B45
EDP_AUXN
EDP_AUXP
RC1
EDP_COMP
1
2 0_0201_5%
@
RC2
EDP_RCOMP
EDP_DISP_UTIL
& lt; eDP & gt;
EDP_CPU_AUX#_C & lt; 18 & gt;
EDP_CPU_AUX_C & lt; 18 & gt;
D20
A43
1
@
2 0_0201_5%
BKL_PWM_CPU & lt; 18,8 & gt;
COMPENSATION PU FOR eDP
+3V_PCH
L
+VCCIOA_OUT
1
1 OF 19
RC234
10K_0402_5%
1
RC4
62_0402_5%
C
EDP_COMP
24.9_0402_1%
HASWELL_MCP_E
UCPU1B
PROC_DETECT#
T51 @
PAD
D61
K61
N62
PROC_DETECT
CATERR
PECI
PROCHOT#
@ESD@
C295
10P_0402_50V8J
L
200_0402_1% 2
1 RC18
SM_RCOMP0
120_0402_1% 2
1 RC19
RC6
1
2 56_0402_5%
1
K63
PROCHOT
JTAG
THERMAL
@
& lt; 11,6 & gt; +1.05VS_PG
2
H_PROCHOT#_R
RC7 1
1K_0402_1%
2
H_CPUPWRGD_R C61
PROCPWRGD
1 RC20
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
DDR3_DRAMRST#
DDR_PG_CNTL
AU60
AV60
AU61
AV15
AV61
XDP_PRDY#
XDP_PREQ#
XDP_TCK
XDP_TMS_CPU
XDP_TRST#_CPU
XDP_TDI_CPU
XDP_TDO_CPU
J60
H60
H61
H62
K59
H63
K60
J61
XDP_OBS0_R
XDP_OBS1_R
XDP_OBS2_R
XDP_OBS3_R
XDP_OBS4_R
XDP_OBS5_R
XDP_OBS6_R
XDP_OBS7_R
T58 @ PAD
XDP_TCK & lt; 6 & gt;
XDP_TMS_CPU & lt; 6 & gt;
XDP_TDI_CPU & lt; 6 & gt;
XDP_TDO_CPU & lt; 6 & gt;
+1.05VS_VCCST
PWR
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_DRAMRST
SM_PG_CNTL1
SM_RCOMP1
100_0402_1% 2
RC3
C
J62
K62
E60
E61
E59
F63
F62
PRDY
PREQ
PROC_TCK
PROC_TMS
PROC_TRST
PROC_TDI
PROC_TDO
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
DG V0.5 Trace width=12~15 mil
Max length=500mil
DDR3 COMPENSATION SIGNALS
1
MISC
2
& lt; 30 & gt; H_PECI
& lt; 30,44 & gt; PROCHOT#
2
2
+VCCIO_OUT
DG V0.9 PEG_COMP
Trace width=20mil and spacing=25mil
Max length=100mil
SM_RCOMP2
DDR3
T80
T79
T52
T53
T54
T55
T56
T57
XDP_TDI_CPU @ RC12 2
@ PAD
@ PAD
@ PAD
@ PAD
@ PAD
@ PAD
@ PAD
@ PAD
XDP_TRST#_CPU
1
2
2 OF 19
1 51_0402_1%
@ RC13 2
XDP_PREQ#
1 51_0402_1%
XDP_TRST#_CPU & lt; 6 & gt;
@ESD@
CC99
0.1U_0402_16V7K
B
B
+1.35V_VDDQ
1
+1.35V_VDDQ
RC308
470_0402_5%
UC10
5
2
DDR3_DRAMRST#
VCC
NC
DDR3_DRAMRST# & lt; 15,16 & gt;
1
@ESD@
CC88
0.1U_0402_16V7K
2
& lt; 15 & gt; SM_PG_CTRL
4
A
Y
GND
1
2
DDR_PG_CNTL
3
74AUP1G07GW_TSSOP5
A
A
Compal Secret Data
Security Classification
Issued Date
2011/06/29
Deciphered Date
2011/06/29
Title
DDI,MSIC,XDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
0.1
LA-A992P
Date:
5
4
3
2
Thursday, March 20, 2014
Sheet
4
of
1
Compal Electronics, Inc.
54
5
4
3
& lt; 15 & gt; DDR_A_D[0..63]
2
& lt; 16 & gt; DDR_B_D[0..63]
UCPU1D
UCPU1C
D
C
B
1
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
AH63
AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57
AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54
AL55
AK55
AR54
AN54
AY58
AW58
AY56
AW56
AV58
AU58
AV56
AU56
AY54
AW54
AY52
AW52
AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
HASWELL_MCP_E
SA_CLK#0
SA_CLK0
SA_CLK#1
SA_CLK1
SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3
SA_CS#0
SA_CS#1
SA_ODT0
SA_RAS
SA_WE
SA_CAS
SA_BA0
SA_BA1
SA_BA2
DDR CHANNEL A
HASWELL_MCP_E
& lt; DDR3L & gt;
& lt; DDR3L & gt;
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7
SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7
SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1
AU37
AV37
AW36
AY36
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
M_CLK_DDR#0 & lt; 15 & gt;
M_CLK_DDR0 & lt; 15 & gt;
M_CLK_DDR#1 & lt; 15 & gt;
M_CLK_DDR1 & lt; 15 & gt;
AU43
AW43
AY42
AY43
DDR_CKE0_DIMMA & lt; 15 & gt;
DDR_CKE1_DIMMA & lt; 15 & gt;
AP33
AR32
DDR_CS0_DIMMA# & lt; 15 & gt;
DDR_CS1_DIMMA# & lt; 15 & gt;
AP32
AY34
AW34
AU34
DDR_A_RAS# & lt; 15 & gt;
DDR_A_WE# & lt; 15 & gt;
DDR_A_CAS# & lt; 15 & gt;
AU35
AV35
AY41
AU36
AY37
AR38
AP36
AU39
AR36
AV40
AW39
AY39
AU40
AP35
AW41
AU41
AR35
AV42
AU42
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
AJ61 DDR_A_DQS#0
AN62 DDR_A_DQS#1
AM58 DDR_A_DQS#2
AM55 DDR_A_DQS#3
AV57 DDR_A_DQS#4
AV53 DDR_A_DQS#5
AL43 DDR_A_DQS#6
AL48 DDR_A_DQS#7
AJ62 DDR_A_DQS0
AN61 DDR_A_DQS1
AN58 DDR_A_DQS2
AN55 DDR_A_DQS3
AW57 DDR_A_DQS4
AW53 DDR_A_DQS5
AL42 DDR_A_DQS6
AL49 DDR_A_DQS7
AP49 +V_SM_VREF_CNT
AR51 +V_DDR_REFA_R
AP51 +V_DDR_REFB_R
DDR_A_BS0 & lt; 15 & gt;
DDR_A_BS1 & lt; 15 & gt;
DDR_A_BS2 & lt; 15 & gt;
DDR_A_MA[0..15] & lt; 15 & gt;
DDR_A_DQS#[0..7] & lt; 15 & gt;
DDR_A_DQS[0..7] & lt; 15 & gt;
+V_SM_VREF_CNT
+V_DDR_REFA_R
+V_DDR_REFB_R
AY31
AW31
AY29
AW29
AV31
AU31
AV29
AU29
AY27
AW27
AY25
AW25
AV27
AU27
AV25
AU25
AM29
AK29
AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AK25
AL25
AY23
AW23
AY21
AW21
AV23
AU23
AV21
AU21
AY19
AW19
AY17
AW17
AV19
AU19
AV17
AU17
AR21
AR22
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18
AL18
AK20
AM20
AR18
AP18
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
SB_CK#0
SB_CK0
SB_CK#1
SB_CK1
SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3
SB_CS#0
SB_CS#1
SB_ODT0
SB_RAS
SB_WE
SB_CAS
SB_BA0
SB_BA1
SB_BA2
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
DDR CHANNEL B
SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7
SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7
AM38
AN38
AK38
AL38
M_CLK_DDR#2 & lt; 16 & gt;
M_CLK_DDR2 & lt; 16 & gt;
M_CLK_DDR#3 & lt; 16 & gt;
M_CLK_DDR3 & lt; 16 & gt;
AY49
AU50
AW49
AV50
D
DDR_CKE0_DIMMB & lt; 16 & gt;
DDR_CKE1_DIMMB & lt; 16 & gt;
AM32
AK32
DDR_CS0_DIMMB# & lt; 16 & gt;
DDR_CS1_DIMMB# & lt; 16 & gt;
AL32
AM35
AK35
AM33
DDR_B_RAS# & lt; 16 & gt;
DDR_B_WE# & lt; 16 & gt;
DDR_B_CAS# & lt; 16 & gt;
AL35
AM36
AU49
AP40
AR40
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AK36
AV47
AU47
AK33
AR46
AP46
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
DDR_B_BS0 & lt; 16 & gt;
DDR_B_BS1 & lt; 16 & gt;
DDR_B_BS2 & lt; 16 & gt;
DDR_B_MA[0..15] & lt; 16 & gt;
C
DDR_B_DQS#[0..7] & lt; 16 & gt;
AW30 DDR_B_DQS#0
AV26 DDR_B_DQS#1
AN28 DDR_B_DQS#2
AN25 DDR_B_DQS#3
AW22 DDR_B_DQS#4
AV18 DDR_B_DQS#5
AN21 DDR_B_DQS#6
AN18 DDR_B_DQS#7
DDR_B_DQS[0..7] & lt; 16 & gt;
AV30 DDR_B_DQS0
AW26 DDR_B_DQS1
AM28 DDR_B_DQS2
AM25 DDR_B_DQS3
AV22 DDR_B_DQS4
AW18 DDR_B_DQS5
AM21 DDR_B_DQS6
AM18 DDR_B_DQS7
B
4 OF 19
3 OF 19
A
A
Compal Secret Data
Security Classification
Issued Date
2011/06/29
Deciphered Date
2011/06/29
Title
DDRIII
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
0.1
LA-A992P
Date:
5
4
3
2
Compal Electronics, Inc.
Thursday, March 20, 2014
1
Sheet
5
of
54
5
4
3
2
1
+RTCBATT
+RTCVCC
PCH_RTCX1
XTAL@
1
RC31
2 RC236 PCH_INTVRMEN
1
INTVRMEN
* H：Integrated
L：Integrated
VRM enable
VRM disable
RC32
1
RC34
2
20K_0402_5%
2
20K_0402_5%
CC5
1U_0402_6.3V6K
2
2
CMOS
XTAL@
CC3
18P_0402_50V8J
JME1
SHORT PADS
+RTCBATT_R
-
+RTCBATT
+
1
15mils
+RTCVCC
1K_0402_5%
DC1
32.768KHZ Q13FC1350000500
1
CC4 XTAL@
18P_0402_50V8J
1
PCH_SRTCRST#
2
RTC BAT conn
PCH_RTCX2
2
JCMOS1
SHORT PADS
PCH_RTCRST#
1
2
10M_0402_5%
XTAL@
YC1
1
2
1
CC2
1U_0402_6.3V6K
1
1
+RTCVCC
2
330K_0402_5% 1
2
2
CC6
1U_0402_6.3V6K
ME CMOS
15mils
2
15mils
RC33
2
1
15mils
JRTC1
LOTES_AAA-BAT-054-K01
CONN@
1
3
1
+3VL
+3VS
BAV70W 3P C/C_SOT-323
2
D
D
1
RC353 short@
2
+RTCVCC
HDA_SYNC
RC35 1
2
AW5
AY5
AU6
AV7
AV6
AU7
PCH_RTCX1
PCH_RTCX2
SM_INTRUDER#
PCH_INTVRMEN
PCH_SRTCRST#
PCH_RTCRST#
1M_0402_5%
0_0402_5%
RTCX1
RTCX2
INTRUDER
INTVRMEN
SRTCRST
RTCRST
SATA_RN0/PERN6_L3
SATA_RP0/PERP6_L3
SATA_TN0/PETN6_L3
SATA_TP0/PETP6_L3
RTC
SATA_RN1/PERN6_L2
SATA_RP1/PERP6_L2
SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2
short@
RC356 1
2
0_0201_5%
HDA_BIT_CLK
HDA_SYNC
HDA_RST#
HDA_SDIN0
HDA_SDOUT
& lt; 25 & gt; HDA_SDIN0
HDA_SDOUT
EMI@ RC367
HDA_BITCLK_AUDIO 2
33_0402_5%
& lt; 25 & gt; HDA_BITCLK_AUDIO
1
HDA_BIT_CLK
SI# 2012.11.1 Add RC367 EMI@ to isolate
Audio Clock by EMI request
RP1
1
2
3
4
HDA_RST_AUDIO#
& lt; 25 & gt; HDA_RST_AUDIO#
& lt; 25 & gt; HDA_SYNC_AUDIO
& lt; 25 & gt; HDA_SDOUT_AUDIO
8
7
HDA_RST#
6
HDA_SYNC_R
5
HDA_SDOUT
33_0804_8P4R_5%
PAD
+3V_PCH
PAD
1
@
1
PCH_JTAG_TDO
CM28
2
AU62
AE62
AD61
AE61
AD62
AL11
AC4
AE63
AV2
XDP_TCK_JTAGX
T157
HDA_BITCLK_AUDIO
HDA_BCLK/I2S0_SCLK
HDA_SYNC/I2S0_SFRM
HDA_RST/I2S_MCLK
HDA_SDI0/I2S0_RXD
AUDIO
HDA_SDI1/I2S1_RXD
HDA_SDO/I2S0_TXD
DOCKEN/I2S1_TXD
HDA_DOCK_RST/I2S1_SFRM
I2S1_SCLK
SATA_RN2/PERN6_L1
SATA_RP2/PERP6_L1
SATA_TN2/PETN6_L1
SATA_TP2/PETP6_L1
SATA
RC218
1
2 100K_0402_5%
PCH_TRST
PCH_TCK
PCH_TDI
PCH_TDO
PCH_TMS
TP5
TP6
JTAGX
RSVD
SATA_IREF
TP7
TP8
SATA_RCOMP
SATALED
JTAG
J5
H5
B15
A15
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0
J8
H8
A17
B17
& lt; 22 & gt;
& lt; 22 & gt;
& lt; 22 & gt;
& lt; 22 & gt;
SATA_PRX_DTX_N1 & lt; 22 & gt;
SATA_PRX_DTX_P1 & lt; 22 & gt;
SATA_PTX_DRX_N1 & lt; 22 & gt;
SATA_PTX_DRX_P1 & lt; 22 & gt;
2.5 " HDD
ODD
J6
H6
B14
C15
F5
E5
C17 PCIE_PTX_DRX_N6
D17 PCIE_PTX_DRX_P6
V1
U1
ODD_PLUG#
V6
PCH_GPIO36
AC1 mSATA_DET#
A12
L11
K10
C12
U3
CC71
CC81
T159
PCIE_PRX_DTX_N6 & lt; 21 & gt;
PCIE_PRX_DTX_P6 & lt; 21 & gt;
PCIE_PTX_C_DRX_N6 & lt; 21 & gt;
PCIE_PTX_C_DRX_P6 & lt; 21 & gt;
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
PAD
WLAN
ODD_PLUG# & lt; 22 & gt;
mSATA_DET# & lt; 7 & gt;
RC39
3K_0402_1%
2
SATA_COMP 1
SATA_LED#
+1.05VS_VCCSATA3PLL
SATA_LED# & lt; 27,9 & gt;
& lt; Page 12 & gt;
C
DG V0.9 SATA_COMP
Width=12mil
Max length=500mil
L
22P_0402_50V8J
@
1
2
RC304 @
100_0402_1%
5 OF 19
CM29
2
HDA_RST_AUDIO#
22P_0402_50V8J
+3VS
RC240
+3V_PCH
1
2
5
PCH_JTAG_TMS
& lt; CPU site & gt;
1
2
2
XDP_TCK_JTAGX
6
XDP_TDI_CPU
RC303 @
100_0402_1%
1
1
R5
@
RC302
100_0402_1%
12
@
11
& lt; 4 & gt; XDP_TMS_CPU
2
RC301 @
100_0402_1%
15
2
2
3
XDP_TDO_CPU
RC46
210_0402_5%
R8
@ UC5
2
1OE
RC45 @
210_0402_5%
RC41 @
210_0402_5%
PCH_JTAG_TDI
2
EC_+1.05VS_PG
1
+3V_PCH
1
+3V_PCH
R4
SATA_RN3/PERN6_L0
SATA_RP3/PERP6_L0
SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0
SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37
1
R3d
2
RC283 @
210_0402_5%
AW8
AV11
AU8
AY10
AU12
AU11
AW10
AV10
AY8
PCH_JTAG_RST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
T156
9/17 add RF solution
C
2 10K_0402_5%
HASWELL_MCP_E
Intel ME update
& lt; 30 & gt; HDA_SDO
1
ODD_PLUG#
HDA_SYNC_R
RC217
PCH_RTCX1 & lt; 31 & gt;
UCPU1E
S1
XDP_TRST#
B
MPHY_PWREN
& lt; 9 & gt; MPHY_PWREN
PCH_RTCX1
1
RC37
& lt; 4 & gt; XDP_TRST#_CPU
2 0_0201_5%
@
& lt; XDP & gt;
XDP_TRST#_CPU
Contact ok
PCH_JTAG_RST#
PCH_JTAG_TMS
& lt; PCH site & gt;
Contact ok
1
RC196
@
1A
VCC
1B
8
& lt; PCH site & gt;
& lt; CPU site & gt;
PCH_JTAG_TCK
51_0402_5% 1
@
@ CC86
2
.1U_0402_16V7K
16
4
XDP_TDO
7
XDP_TDI_SWITCH
10
XDP_TMS
13
XDP_TRST#
2OE
2A
2B
3OE
3A
3B
4OE
4A
4B
NC
& lt; CPU site & gt;
GND
NC
1
9
B
74CBTLV3126DS_SSOP16
R6
2 0_0201_5% XDP_TMS_CPU
1
10K_0402_5%
2
RC38
+1.05VS_VCCST
XDP_TMS
1
& lt; XDP & gt;
S2
14
XDP_TRST#_CPU
@
1
RC307
1
RC200
short@
1
PCH_JTAG_TDO
& lt; PCH site & gt;
XDP_TDI
& lt; XDP & gt;
RC195
short@
1
S3
XDP_TDO
2 0_0201_5%
@
J3S
@
J4d
1
RC198
PCH_JTAG_TDI
& lt; PCH site & gt;
1
RC199
XDP_TDI_CPU
2 0_0201_5%
XDP_TDI_SWITCH
@
J3D
1
1
& lt; EC output & gt;
& lt; XDP & gt;
& lt; 30 & gt; EC_+1.05VS_PG
XDP_TDI_SWITCH
+1.05VS_VCCST
XDP_TDO_CPU
2 0_0201_5%
XDP_TDO_CPU
RC10 2
1 51_0402_1%
XDP_TDO_CPU & lt; 4 & gt;
+1.05VS_VCCST
2 0_0201_5%
& lt; PCH site & gt;
PCH_JTAG_TDO
R7
@
RC14 2
A
PCH_JTAG_TCK
XDP_TCK
J1S
& lt; PCH site & gt;
XDP_TCK_JTAGX
XDP_TCK_JTAGX
& lt; PCH site & gt;
RC193
short@
1
@
J2D
J2S
RC306
1
@
2 0_0201_5%
XDP_TCK
XDP_TCK & lt; 4 & gt;
RC15 2
1 51_0402_1%
4
& lt; CPU,XDP,XDP Switch & gt;
+1.05VS_PG & lt; 11,4 & gt;
Resistors
Stuffed
Resistors
ufStuffed
- Run control oper.
- ME/Sx debug
R1d,R2,R3d,
R4,R5,J1d
J2d,J3d*
J4d and Rs5*
J1s, J2s,
J3s
R6,R7,R8,R9
-B oundary Scan/
Manufacturing est
J1s,J2s,J3s**
R2,R4,R5,R5s**
Topolog
Description
Be st Use for
Default Setting: Dual
TCK S can Chains
(also known as
" Shared JTAG " in
other docum ent)
In this topology, the
CPU JTAG chain will be
controlled by TCK0 and
TCK1 will control
the PCH JTAG chain.
In th is topolog y, PCH
TDI- TDO and CPU TDI-TDO
will be chained to form
one JTAG scan chain
controlled by TCK0
Compal Secret Data
Security Classification
Issued Date
& lt; XDP & gt;
XDP_TDO
Y
GND
R1d,r3d,J1d,J2d
J3d**,J4d,
R6,R7,R8,R9
2011/06/29
Deciphered Date
Compal Electronics, Inc.
2011/06/29
Title
RTC,SATA,HDA,JTAG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
0.1
LA-A992P
Date:
5
4
A
& lt; CPU and XDP & gt;
2 0_0201_5%
2 0_0201_5%
A
5
1 51_0402_1%
R2
1
VCC
Single TCK scan chain
(also known as " Com m on
JTAG " in other docum
ent)
R1d
XDP_TCK:XDP contact with CPU No 0ohm(RS5)
RC197
2
NC
74AUP1G07GW_TSSOP5
XDP_TDO
& lt; PCH site & gt;
EC_+1.05VS_PG
3
2 0_0201_5%
R511
10K_0402_5%
U16
1 51_0402_1%
@
2 0_0201_5% XDP_TDI
S4
+3V_PCH
R9
& lt; CPU & gt;
XDP_TRST#_CPU RC16 2
& lt; XDP & gt;
RC194
short@
XDP_TDI_CPU & lt; 4 & gt;
2
XDP_TDI_SWITCH
3
2
Thursday, March 20, 2014
1
Sheet
6
of
54
5
4
3
2
1
CPU_XTAL24_IN
CPU_XTAL24_IN
CPU_XTAL24_IN & lt; 31 & gt;
CPU_XTAL24_OUT
XTAL@
2
1
1M_0402_5%
RC48
HASWELL_MCP_E
UCPU1F
3
D
CLK_PCIE_LAN#
CLK_PCIE_LAN
PCIECLKREQ0#
& lt; 23 & gt; CLK_PCIE_LAN#
& lt; 23 & gt; CLK_PCIE_LAN
PCIE LAN
CLK_PCIE_CR#
CLK_PCIE_CR
CR_CLKREQ#
& lt; 23 & gt; CLK_PCIE_CR#
& lt; 23 & gt; CLK_PCIE_CR
& lt; 23,9 & gt; CR_CLKREQ#
PCIE Card reader
& lt; 23 & gt; LAN_CLKREQ#
CLK_PCIE_GPU#
CLK_PCIE_GPU
GPU_CLKREQ#
& lt; 32 & gt; CLK_PCIE_GPU#
& lt; 32 & gt; CLK_PCIE_GPU
& lt; 32,8 & gt; GPU_CLKREQ#
GPU
+3VS
4
3
2
1
5
6
7
8
LAN_CLKREQ#
SYS_RESET#
EC_KBRST#
MSATA_DET#
MINI1_CLKREQ#
& lt; 21 & gt; MINI1_CLKREQ#
SYS_RESET# & lt; 8 & gt;
EC_KBRST# & lt; 30,9 & gt;
MSATA_DET# & lt; 6 & gt;
B38
C37
N1
A39
B39
PCIECLKREQ4# U5
& lt; 9 & gt; PCIECLKREQ4#
RPH11
B41
A41
Y5
CLK_PCIE_MINI1# C41
CLK_PCIE_MINI1 B42
AD1
LAN_CLKREQ#
& lt; 21 & gt; CLK_PCIE_MINI1#
& lt; 21 & gt; CLK_PCIE_MINI1
WLAN
C43
C42
U2
B37
A37
T2
CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
PCIECLKRQ0/GPIO18
A25
B25
XTAL24_IN
XTAL24_OUT
K21
M21
C26 PCH_CLK_BIASREF
TP15
TP16
DIFFCLK_BIASREF
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
PCIECLKRQ1/GPIO19
C35
C34
AK8
AL8
TP19
TP20
TP21
TP22
CLOCK
SIGNALS
CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
PCIECLKRQ2/GPIO20
CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
PCIECLKRQ3/GPIO21
B35
A35
CLKOUT_ITPXDP
CLKOUT_ITPXDP_P
XTAL@
CC9
RC52
3K_0402_1%
1
2
4
3
2
1
TESTLOW1
TESTLOW2
TESTLOW3
TESTLOW4
AN15 CLK_PCI0
AP15 CLK_PCI1
CLKOUT_LPC_0
CLKOUT_LPC_1
CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
PCIECLKRQ4/GPIO22
CPU_XTAL24_IN
CPU_XTAL24_OUT
EMI@ RC61
EMI@ RC62
1
1
18P_0402_50V8J
1
1
GND
1 XTAL@
CC10
4 XTAL@ 2
18P_0402_50V8J
YC2
2
24MHZ 12PF 5YEA24000122IF40Q3
2
& lt; Page12 & gt;
+1.05VS_AXCK_LCPLL
3
GND
1
D
5 RPH22
6
& lt; PV & gt; PRH13 change to RPH22.
7
8
10K_0804_8P4R_5%
2 22_0402_5%
CLK_PCI_LPC
& lt; EC & gt;
CLK_PCI_LPC & lt; 30 & gt;
2 22_0402_5%
CLK_PCI_TPM
CLK_PCI_TPM & lt; 28 & gt;
CLK_CPU_ITP#
CLK_CPU_ITP
T82 @ PAD
T81 @ PAD
& lt; XDP CLK reserve TP & gt;
9/17 add RF solution
CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
PCIECLKRQ5/GPIO23
+3V_PCH
@RF@
1
6 OF 19
CM30
2
CLK_PCI_LPC
10K_0804_8P4R_5%
22P_0402_50V8J
HASWELL_MCP_E
UCPU1G
PCIECLKREQ0#
MINI1_CLKREQ#
PCI_PIRQB#
PCH_GPIO33
C
10K_0804_8P4R_5%
RPH19
8
7
6
5
PCH_SPI_CS0#
PCH_SPI_SO
PCH_SPI_SI
PCH_SPI_HOLD#
DB# 2013.08.27 RC368 place near CPU
& lt; 30 & gt; EC_SPI_SI
& lt; 30 & gt; EC_SPI_SO
& lt; 30 & gt; EC_SPI_CS0#
1
2
3
4
PCH_SPI_CS0#_R
PCH_SPI_SO_R
PCH_SPI_SI_R
PCH_SPI_SIO3
1
PCH_SPI_CLK_R
1
2
3
4
PCH_SPI_SI_R
PCH_SPI_SO_R
PCH_SPI_CS0#_R
PCH_SPI_WP#
LAD0
LAD1
LAD2
LAD3
LFRAME
AA3
PCH_SPI_CLK
Y7
PCH_SPI_CS0#
Y4
AC2
AA2
PCH_SPI_SI
AA4
PCH_SPI_SO
Y6
PCH_SPI_SIO2
PCH_SPI_SIO3 AF1
15_0804_8P4R_5%
2
15_0402_5%
RPH20
8
7
6
5
PCH_SPI_SIO2
PCH_SPI_CLK RC368
EMI@
AU14
LPC_AD0
AW12
LPC_AD1
AY12
LPC_AD2
AW11
LPC_AD3
LPC_FRAME# AV12
& lt; 28,30 & gt; LPC_AD0
& lt; 28,30 & gt; LPC_AD1
& lt; 28,30 & gt; LPC_AD2
& lt; 28,30 & gt; LPC_AD3
& lt; 28,30 & gt; LPC_FRAME#
PCI_PIRQB# & lt; 8 & gt;
PCH_GPIO33 & lt; 9 & gt;
SPI_CLK
SPI_CS0
SPI_CS1
SPI_CS2
SPI_MOSI
SPI_MISO
SPI_IO2
SPI_IO3
& lt; 30 & gt; EC_SPI_CLK
SPI
CL_CLK
CL_DATA
CL_RST
C-LINK
AN2
AP2
AH1
AL2
AN1
AK1
AU4
AU3
AH3
SMBALERT#
SMBCLK
SMBDATA
USB_CR_PWREN
SML0CLK
SML0DATA
SML1ALERT#
SML1CLK
SML1DATA
1
SMBALERT# & lt; 9 & gt;
USB_CR_PWREN
SML0CLK
2
@RF@
1
SML1ALERT# & lt; 9 & gt;
CM33
2
PCH_SPI_CLK_R
+3VS
RC78
10K_0402_5%
6
SMBCLK
DB# 2013.08.27 RC369 place near SPI ROM
2
RC80
3.3K_0402_5%
SPI ROM 8M
1
PCH_SMBCLK & lt; 15,16 & gt;
2
3.3K_0402_5%
FL
FL
FL
FL
64M
64M
64M
64M
5
IC
IC
IC
IC
EN25Q64-104HIP SOP 8P
MX25L6473EM2I-10G SOP 8P
W25Q64FVSSIQ SOIC 8P SPI ROM
+3V_PCH
N25Q064A13ESEC0F SO8W 8P
2N7002DWH_SOT363-6
QC2B
3
SMBDATA
4
PCH_SMBDATA & lt; 15,16 & gt;
B
UC2
PCH_SPI_CS0#_R
PCH_SPI_SO_R
PCH_SPI_WP#
1
2
3
4
CS#
SO/SIO1
WP#
GND
VCC
HOLD#
SCLK
SI/SIO0
8
7
6
5
PCH_SPI_HOLD#
PCH_SPI_CLK_R
PCH_SPI_SI_R
2
1 RC84
3.3K_0402_5%
1
2
EN25Q64-104HIP
CC11
0.1U_0402_16V7K
@
2N7002DWH_SOT363-6
SML1CLK
6
1
EC_SMB_CK2 & lt; 18,30,32 & gt;
5
1
RC85
S
S
S
S
+3VS
1
+3V_PCH
RC79
10K_0402_5%
2
@
B
+3VS
QC2A 2N7002DWH_SOT363-6
+3V_PCH
SA000046400
SA00006N100
SA000039A30
SA00005L100
8 2.2K_0804_8P4R_5%
7
C
6
5
AF2
AD2
AF4
PCH_SPI_CLK_R
EON
MXIC
WINBOND
Micron
2 RC73
1
2
3
4
RP2
22P_0402_50V8J
SI# 2012.11.1 Add RC368 ,RC369 to
Isolate SPI Clock by EMI request
2 0_0402_5%
2 RC72
1
SMBCLK
SMBDATA
SML1CLK
SML1DATA
7 OF 19
2
short@ RC56 1
15_0402_5%
1
1K_0402_5%
CLK_PCI_TPM
22P_0402_50V8J
& lt; 8 & gt;
1K_0402_5%
SML0DATA
CM31
2
1
SMBALERT/GPIO11
SMBCLK
SMBDATA
SMBUS
SML0ALERT/GPIO60
SML0CLK
SML0DATA
SML1ALERT/PCHHOT/GPIO73
SML1CLK/GPIO75
SML1DATA/GPIO74
LPC
15_0804_8P4R_5%
EMI@ RC369
@RF@
2
5
6
7
8
1
4
3
2
1
2
RPH12
1
+3VS
QC6A
SML1DATA
3
4
EC_SMB_DA2 & lt; 18,30,32 & gt;
2N7002DWH_SOT363-6
QC6B
remove thernal sensor 10/14
A
A
Compal Secret Data
Security Classification
Issued Date
2011/06/29
2011/06/29
Deciphered Date
Title
Compal Electronics, Inc.
CLK,SPI,SMB,LPC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
0.1
LA-A992P
Date:
5
4
3
2
Sheet
Thursday, March 20, 2014
1
7
of
54
5
4
3
2
1
+RTCVCC
short@ RC268
1
RC269
T83
2
0_0201_5%
1
DSWODVREN - On Die DSW VR Enable
PM_SLP_S0#_R
2 0_0201_5%
*
PM_SLP_S3#
@
Non Deep S3 RC91-- & gt; SMT
Deep S3 RC93-- & gt; SMT
H：Enable
DSWODVREN RC254
2
L：Disable
PAD
DSWODVREN RC255
2
1 330K_0402_5%
1 330K_0402_5%
@
HASWELL_MCP_E
UCPU1H
@
SUSWARN#_R RC91 1
& lt; 9 & gt; SUSWARN#_R
& lt; 30 & gt; SUSACK#
1
short@ RC93
2
0_0201_5%
AK2
SUSACK#_R
AC3
SYS_RESET#
AG2
SYS_PWROK
PM_PWROK_R AY7
AB5
APWROK_R
AG7
PLT_RST#_PCH
& lt; 7 & gt; SYS_RESET#
D
& lt; 30 & gt; SYS_PWROK
PCH_PWROK
& lt; 30 & gt; PCH_PWROK
& lt; 30 & gt; PCH_RSMRST#
& lt; 30 & gt; PCH_SUSWARN#
& lt; 30 & gt; PBTN_OUT#
& lt; 30,44,45,46 & gt; ACIN
Deep S3
C70 ESD@
1
2
short@ RC99 1
short@ RC1001
SYSTEM POWER MANAGEMENT
2 0_0201_5%
2 0_0402_5%
2 0_0402_5%
PCH_RSMRST#
SUSWARN#_R
PBTN_OUT#_R
ACIN_R
PM_BATLOW#
PM_SLP_S0#_R
PCH_SLP_WLAN#
short@ RC1041
short@ RC1031
2 0_0402_5%
2 0_0402_5%
1
2 DC2
CH751H-40PT_SOD323-2
AW6
AV4
AL7
AJ8
AN4
AF3
AM5
SUSACK
SYS_RESET
SYS_PWROK
PCH_PWROK
APWROK
PLTRST
DSWVRMEN
DPWROK
WAKE
CLKRUN/GPIO32
SUS_STAT/GPIO61
SUSCLK/GPIO62
SLP_S5/GPIO63
RSMRST
SUSWARN/SUSPWRDNACK/GPIO30
PWRBTN
ACPRESENT/GPIO31
BATLOW/GPIO72
SLP_S0
SLP_WLAN/GPIO29
SLP_S4
SLP_S3
SLP_A
SLP_SUS
SLP_LAN
8 OF 19
1 100K_0402_5%
2 0_0402_5%
AOAC_PME#
D
WAKE# & lt; 41 & gt;
+3V_DSW_P
PM_CLKRUN# & lt; 30 & gt;
1
RC98
2 1K_0402_5%
PM_SLP_S4# & lt; 30 & gt;
PM_SLP_S3# & lt; 30 & gt;
PM_SLP_S3#
T145PAD @
2 0_0201_5%
1
WAKE#
PM_SLP_S5# & lt; 30 & gt;
PAD
@
PM_SLP_SUS# & lt; 30 & gt;
PCH_RSMRST#
2
RC106
1 10K_0402_5%
Non Deep S3 RC286-- & gt; @
S3 RC286-- & gt; SMT T144
T143Deep
PAD
@
PAD
@
Deep S3:DSW power choose on page12
CH751H-40PT_SOD323-2
1
2 DC3
PCH_PWROK
+3V_DSW_P
CH751H-40PT_SOD323-2
1
DC4 2
SYS_PWROK
1
short@ RC286
T142
PAD
@
PCH_RSMRST#
2
AJ6
AT4
AL5
AP4
AJ7
RC371
short@
T147
V5
PM_CLKRUN#
AG4 SUS_STAT#
AE6
AP5
PCH_PWROK
0.047U_0402_16V7K
RC112
AW7 DSWODVREN
AV5 PCH_DPWROK_R
AJ5 WAKE#
SPOK & lt; 47 & gt;
C
C
PCH_DPWROK_R
RC316
short@
1
2
0_0201_5%
PCH_DPWROK & lt; 30 & gt;
HASWELL_MCP_E
UCPU1I
PANEL_BKEN_CPU PD 100K on Page20
& lt; 18,4 & gt; BKL_PWM_CPU
& lt; 30 & gt; ENBKL
& lt; 19 & gt; ENVDD_CPU
short@ RC114
short@ RC115
ENVDD_CPU RC116
short@
1
1
1
2 0_0402_5%
2 0_0402_5%
2 0_0402_5%
& lt; 9 & gt; EC_SMI#
& lt; 7 & gt; PCI_PIRQB#
& lt; 9 & gt; PCI_PIRQC#
& lt; 30 & gt; AOAC_PME#
AOAC_PME#
1
RC305
PAD
PAD
1
RC120
B
PCH_SLP_WLAN#
BKL_PWM_CPU_R
ENBKL_CPU
ENVDD_CPU_R
EC_SMI#
PCI_PIRQB#
PCI_PIRQC#
@ PCH_GPIO80
2
AOAC_PME#_R
0_0402_5%
T146 @
T154 @
RPH15
1
2
3
4
PM_BATLOW#
USB_CR_PWREN
& lt; 7 & gt; USB_CR_PWREN
TS_RST#
PCH_MC_WAKE#
PCH_MIC_DET
PCH_HP_DET
B8
A9
C6
U6
P4
N4
N2
AD4
U7
L1
L3
R5
L4
EDP_BKLCTL
EDP_BKLEN
EDP_VDDEN
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
eDP SIDEBAND
PIRQA/GPIO77
PIRQB/GPIO78
PIRQC/GPIO79
PIRQD/GPIO80
PME
DISPLAY
GPIO
GPIO55
GPIO52
GPIO54
GPIO51
GPIO53
DDPB_AUXN
DDPC_AUXN
DDPB_AUXP
DDPC_AUXP
DDPB_HPD
DDPC_HPD
EDP_HPD
B9
C9
D9 @
D11
C5
B6
B5
A6
PCH_DDPB_CLK
PCH_DDPB_CLK & lt; 20 & gt;
PCH_DDPB_DAT
PCH_DDPB_DAT & lt; 20 & gt;
1
2 2.2K_0402_5%
RC107
1
RC102
2
2.2K_0402_5%
ACIN_R
& lt; HDMI & gt;
1
RC101
8
7
6
5
10K_0804_8P4R_5%
2 10K_0402_5%
+3VS
& lt; SI & gt; Displayport Port C Enable pin RC102 pull high +3VS
DDI1_AUX_DN
C8
A8
D6
+3VS
DDI1_AUX_DN & lt; 29 & gt;
DDI1_AUX_DP
DDI1_AUX_DP & lt; 29 & gt;
& lt; DP TO CRT HPD & gt;
& lt; HDMI & gt;
PCH_DDPB_HPD & lt; 20 & gt;
DDI1_HPD & lt; 29 & gt;
& lt; DP TO CRT
EDP_HPD & lt; 18 & gt;
PM_CLKRUN# RC110
2
1 8.2K_0402_5%
HPD & gt;
& lt; eDP HPD & gt;
2 100K_0402_5% ENVDD_CPU
B
9 OF 19
+3VS
@
1
RC300
RPH27
4
3
2
1
5
GPU_CLKREQ#
6
PCH_GPIO80
7
PCH_HP_DET
8
DEVSLP1
10K_0804_8P4R_5%
2
0_0402_5%
1 10K_0402_5% PCH_MC_WAKE#
+3VS
GPU_CLKREQ# & lt; 32,7 & gt;
5
2
UC9
P
RC125
DEVSLP1 & lt; 22,9 & gt;
& lt; 21,23,28,30,32 & gt; PLT_RST#
PLT_RST#
4
IN1
O
G
IN2
3
& lt; PV & gt; PRH18 change to RPH27.
1
PLT_RST#_PCH
& lt; CPU & gt;
2
SN74AHC1G08DCKR_SC70-5
PD on KBC page
A
A
Compal Secret Data
Security Classification
Issued Date
2011/06/29
Deciphered Date
2011/06/29
Title
PM,GPIO,DDI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
0.1
LA-A992P
Date:
5
4
3
2
Thursday, March 20, 2014
Sheet
1
8
of
54
5
4
3
2
1
1
+1.05VS_VCCST
HASWELL_MCP_E
UCPU1J
RC242
1K_0402_5%
& lt; 23 & gt; LAN_PWR_EN
& lt; 30 & gt; EC_LID_OUT#
& lt; 30 & gt; EC_FB_CLAMP_TGL_REQ#
& lt; 34 & gt; DGPU_GC6_EN
D
& lt; 23,30 & gt; EC_PME#
RC122 1
@
RC123 1
@
EC_PME#
PAD
T148
PAD
T149
AG6
AP1
2 PCH_GPIO58
AL4
RC119 1
@
& lt; 30,32 & gt; DGPU_HOLD_RST#
AT5
0_0201_5% WL_OFF#
& lt; 10,21 & gt; WL_OFF#
AK4
NMI_DBG#_CPU
& lt; 30 & gt; NMI_DBG#_CPU
AB6
LPDDR3_ID1
U4
LPDDR3_ID2
Y3
LPDDR3_ID3
P3
PAD
T150
Y2
MPHY_PWREN
& lt; 6 & gt; MPHY_PWREN
USB32_P0_PWREN_R# AT3
AH4
AM4
USB_CAM_PWREN
AG5
TS_GPIO_CPU
& lt; 19 & gt; TS_GPIO_CPU
AG3
ACCEL_INT#
& lt; 28 & gt; ACCEL_INT#
BT_ON
& lt; 30 & gt; EC_SCI#
& lt; 7 & gt; PCH_GPIO33
& lt; 22,8 & gt; DEVSLP1
PCH_GPIO9
EC_SCI#
PCH_GPIO33
PAD
T158
Dummy
DEVSLP1
HDA_SPKR
& lt; 25 & gt; HDA_SPKR
C
AM3
AM2
P2
C4
L2
N5
V2
BMBUSY/GPIO76
GPIO8
LAN_PHY_PWR_CTRL/GPIO12
GPIO15
GPIO16
GPIO17
GPIO24
GPIO27
GPIO28
GPIO26
GPIO56
GPIO57
GPIO58
GPIO59
GPIO44
GPIO47
GPIO48
GPIO49
GPIO50
HSIOPC/GPIO71
GPIO13
GPIO14
GPIO25
GPIO45
GPIO46
CPU/
MISC
GPIO
LPIO
GPIO9
GPIO10
DEVSLP0/GPIO33
SDIO_POWER_EN/GPIO70
DEVSLP1/GPIO38
DEVSLP2/GPIO39
SPKR/GPIO81
+3VS
+3V_PCH
THRMTRIP
RCIN/GPIO82
SERIRQ
OPI_COMP2
RSVD
RSVD
GSPI0_CS/GPIO83
GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86
GSPI1_CS/GPIO87
GSPI1_CLK/GPIO88
GSPI1_MISO/GPIO89
GSPI_MOSI/GPIO90
UART0_RXD/GPIO91
UART0_TXD/GPIO92
UART0_RTS/GPIO93
UART0_CTS/GPIO94
UART1_RXD/GPIO0
UART1_TXD/GPIO1
UART1_RST/GPIO2
UART1_CTS/GPIO3
I2C0_SDA/GPIO4
I2C0_SCL/GPIO5
I2C1_SDA/GPIO6
I2C1_SCL/GPIO7
SDIO_CLK/GPIO64
SDIO_CMD/GPIO65
SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69
D60 H_THERMTRIP#_C
V4
EC_KBRST#
T4
SERIRQ
AW15PCH_OPIRCOMP
AF20
AB21
R6
L6
N6
L8
R7
L5
N7
K2
J1
K3
J2
G1
K4
G2
J3
J4
F2
F3
G4
F1
E3
F4
D3
E4
C3
E2
RC129
0_0402_5%
1
2 H_THEMTRIP#
2
short@
P1
AU2
AM7
LAN_PWR_EN
AD6
EC_LID_OUT#
2 0_0201_5% PCH_GPIO16
Y1
2 0_0201_5% PCH_GPIO17
T3
AD5
UART_WAKE#
AN5
AD7
AN3
PCH_AUDIO_PWREN
EC_KBRST# & lt; 30,7 & gt;
SERIRQ & lt; 28,30 & gt;
1
RC131
49.9_0402_1%
2
NGFF_WIFI_3.3_PWREN
WWAN_PWREN
PCH_GPIO85 RC108 1
@
MSATA_SSD_PWREN
L
DG V0.9 PCH_OPIRCOMP
Width=12mil,spacing=12mil
Max length=500mil
Boot BIOS Strap
2 0_0201_5%
PCH_GPIO86
DGPU_PWR_EN & lt; 30,35,53 & gt;
TOUCH_PANEL_PWREN
SATA1_PWREN
PCH_LAN_RST#
PCH_LAN_WAKE#
PCH_CR_RST#
PCH_CR_WAKE#
ODD_DA#
I2C_0_SDA
I2C_0_SCL
I2C_1_SDA
I2C_1_SCL
ODD_PWR
ODD_DA# & lt; 22 & gt;
4
NGFF_WIFI_3.3_PWREN
3
WWAN_PWREN
2
MSATA_SSD_PWREN
1
TOUCH_PANEL_PWREN
10K_0804_8P4R_5%
ODD_PWR & lt; 22 & gt;
10 OF 19
5
USB_OC2#
6
7
ACCEL_INT#
8
PCH_GPIO58
10K_0804_8P4R_5%
+3VS
1
+3VS
+3VS
2
2
10K_0402_5%
@
& lt; PV & gt; PRH19 change to RPH28.
PCH_CR_WAKE#
PCH_CR_RST#
PCH_LAN_WAKE#
PCH_LAN_RST#
1
1
USB_OC0# & lt; 10,24 & gt;
@
RC263
@
RC264
10K_0402_5%
4
3
2
1
10K_0804_8P4R_5%
@
RC265
10K_0402_5%
5 RPH28
6
7
8
10K_0402_5%
@
8
7
6
5
I2C_1_SDA
I2C_0_SCL
I2C_0_SDA
I2C_1_SCL
2
& lt; PV & gt; PRH14 change to RPH23.
PRH15 change to RPH24.
PRH16 change to RPH25.
B
RC262
10K_0402_5%
@
2
5
USB_OC0#
6
USB32_P0_PWREN_R#
7
PCH_GPIO9
8
NMI_DBG#_CPU
10K_0804_8P4R_5%
2
LPDDR3_ID1
LPDDR3_ID2
LPDDR3_ID3
RC261
10K_0402_5%
@
1
4
3
2
1
USB_OC2# & lt; 10 & gt;
2
RPH25
C
+3VS
1
4
3
2
1
+3V_PCH
RC135
RPH24
5 RPH21
6
7
8
& lt; PV & gt; PRH12 change to RPH21.
5
ODD_DA#
6
EC_LID_OUT#
7
UART_WAKE#
8
BT_ON
10K_0804_8P4R_5%
1
4
3
2
1
*
Boot BIOS Location
SPI
0
9/12 reserve DGPU_PWR_EN on GPIO85
& lt; SI & gt; PRH14.4 change from +3V_PCH to +3VS for S3 leakage
RPH23
D
1 RPH18
2
3
4
B
RPH13
4
3
2
1
RPH26
RPH10
4
3
2
1
5
6
7
8
1K_0804_8P4R_5%
CR_CLKREQ#
SERIRQ
SATA_LED#
10K_0804_8P4R_5%
5
PCH_GPIO17
6
EC_SMI#
7
PCIECLKREQ4#
8
PCI_PIRQC#
10K_0804_8P4R_5%
4
3
2
1
@
CR_CLKREQ# & lt; 23,7 & gt;
+3V_PCH
SATA_LED# & lt; 27,6 & gt;
RPH14
EC_SMI# & lt; 8 & gt;
PCIECLKREQ4# & lt; 7 & gt;
PCI_PIRQC# & lt; 8 & gt;
5
SATA1_PWREN
6
PCH_AUDIO_PWREN
7
USB_CAM_PWREN
8
LAN_PWR_EN
10K_0804_8P4R_5%
4
3
2
1
5
SUSWARN#_R
6
SML1ALERT#
7
SMBALERT#
8
EC_SCI#
10K_0804_8P4R_5%
SUSWARN#_R & lt; 8 & gt;
SML1ALERT# & lt; 7 & gt;
SMBALERT# & lt; 7 & gt;
& lt; PV & gt; PRH10 change to RPH10.
PRH17 change to RPH26.
+3V_DSW_P
DSW power choose on page12
*
GPIO27
RC277
A
1
2 10K_0402_5% EC_PME#
A
PCH_GPIO27 (Have internal Pull-High)
High: VCCVRM VR Enable
Low: VCCVRM VR Disable
Compal Secret Data
Security Classification
Issued Date
2011/06/29
Deciphered Date
2011/06/29
Title
GPIO,UART,I2C
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
0.1
LA-A992P
Date:
5
4
3
2
Thursday, March 20, 2014
Sheet
1
9
of
54
5
4
3
2
1
HASWELL_MCP_E
UCPU1K
& lt; DB & gt; change AC cap to 0.22uF review by Nvidia
PEG_GTX_C_HRX_N7
PEG_GTX_C_HRX_P7
& lt; 32 & gt; PEG_GTX_C_HRX_N7
& lt; 32 & gt; PEG_GTX_C_HRX_P7
D
0.22U_0402_6.3V6K DIS@ 1
0.22U_0402_6.3V6K DIS@ 1
& lt; 32 & gt; PEG_HTX_C_GRX_N7
& lt; 32 & gt; PEG_HTX_C_GRX_P7
2 CC90
2 CC91
0.22U_0402_6.3V6K DIS@ 1
0.22U_0402_6.3V6K DIS@ 1
& lt; 32 & gt; PEG_HTX_C_GRX_N8
& lt; 32 & gt; PEG_HTX_C_GRX_P8
2 CC89
2 CC92
0.22U_0402_6.3V6K DIS@ 1
0.22U_0402_6.3V6K DIS@ 1
& lt; 32 & gt; PEG_HTX_C_GRX_N9
& lt; 32 & gt; PEG_HTX_C_GRX_P9
B23
PEG_HTX_GRX_N8
A23
PEG_HTX_GRX_P8
H10
G10
PEG_HTX_GRX_N9
PEG_HTX_GRX_P9
B21
C21
2 CC93
2 CC94
PEG_GTX_C_HRX_N10
PEG_GTX_C_HRX_P10
& lt; 32 & gt; PEG_GTX_C_HRX_N10
& lt; 32 & gt; PEG_GTX_C_HRX_P10
0.22U_0402_6.3V6K DIS@ 1
0.22U_0402_6.3V6K DIS@ 1
& lt; 32 & gt; PEG_HTX_C_GRX_N10
& lt; 32 & gt; PEG_HTX_C_GRX_P10
10/100/1G LAN
F8
E8
PEG_GTX_C_HRX_N9
PEG_GTX_C_HRX_P9
& lt; 32 & gt; PEG_GTX_C_HRX_N9
& lt; 32 & gt; PEG_GTX_C_HRX_P9
C
C23
PEG_HTX_GRX_N7
C22
PEG_HTX_GRX_P7
PEG_GTX_C_HRX_N8
PEG_GTX_C_HRX_P8
& lt; 32 & gt; PEG_GTX_C_HRX_N8
& lt; 32 & gt; PEG_GTX_C_HRX_P8
F10
E10
2 CC95
2 CC96
E6
F6
PEG_HTX_GRX_N10 B22
PEG_HTX_GRX_P10 A21
PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3
& lt; 23 & gt; PCIE_PRX_DTX_N3
& lt; 23 & gt; PCIE_PRX_DTX_P3
CC12 2
CC13 2
& lt; 23 & gt; PCIE_PTX_C_DRX_N3
& lt; 23 & gt; PCIE_PTX_C_DRX_P3
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
G11
F11
PCIE_PTX_DRX_N3
PCIE_PTX_DRX_P3
C29
B30
F13
G13
B29
A29
G17
F17
C30
C31
PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
& lt; 23 & gt; PCIE_PRX_DTX_N2
& lt; 23 & gt; PCIE_PRX_DTX_P2
PCI-E Card reader
CC16 2
CC17 2
& lt; 23 & gt; PCIE_PTX_C_DRX_N2
& lt; 23 & gt; PCIE_PTX_C_DRX_P2
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
F15
G15
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2
B31
A31
PERN5_L0
PERP5_L0
USB2N0
USB2P0
PETN5_L0
PETP5_L0
USB2N1
USB2P1
PERN5_L1
PERP5_L1
USB2N2
USB2P2
PETN5_L1
PETP5_L1
USB2N3
USB2P3
PERN5_L2
PERP5_L2
USB2N4
USB2P4
PETN5_L2
PETP5_L2
USB2N5
USB2P5
PERN5_L3
PERP5_L3
USB2N6
USB2P6
PETN5_L3
PETP5_L3
USB2N7
USB2P7
PERN3
PERP3
PETN3
PETP3
USB3RN0
USB3RP0
USB
PCIe
PERN4
PERP4
USB3RN1
USB3RP1
PETN4
PETP4
USB3TN1
USB3TP1
& lt; Page12 & gt;
+1.05VS_VCCUSB3PLL
L
PCH_PCIE_RCOMP
E15
E13
A27
B27
USB20_N0 & lt; 24 & gt;
USB20_P0 & lt; 24 & gt;
Camera
USB20_N5 & lt; 19 & gt;
USB20_P5 & lt; 19 & gt;
AM13
AN13
WLAN/BT
USB20_N4 & lt; 19 & gt;
USB20_P4 & lt; 19 & gt;
AM15
AL15
USB2.0
USB20_N3 & lt; 21 & gt;
USB20_P3 & lt; 21 & gt;
AR10
AT10
USB2.0
USB20_N2 & lt; 24 & gt;
USB20_P2 & lt; 24 & gt;
AR8
AP8
USB2.0/USB3.0
USB20_N1 & lt; 24 & gt;
USB20_P1 & lt; 24 & gt;
AR7
AT7
Touch screen
PETN1/USB3TN2
PETP1/USB3TP2
USBRBIAS
USBRBIAS
TP13
TP14
PERN2/USB3RN3
PERP2/USB3RP3
PETN2/USB3TN3
PETP2/USB3TP3
OC0/GPIO40
OC1/GPIO41
OC2/GPIO42
OC3/GPIO43
TP3
TP4
PCIE_RCOMP
PCIE_IREF
D
AP11
AN11
AR13
AP13
C
G20
H20
USB3_RX0_N & lt; 24 & gt;
USB3_RX0_P & lt; 24 & gt;
C33
B34
USB2.0/USB3.0
USB3_TX0_N & lt; 24 & gt;
USB3_TX0_P & lt; 24 & gt;
E18
F18
B33
A33
DG V0.9 USBRBIAS
Trace width=50ohm and spacing=15mil
Max length=500mil
22.6_0402_1%
L
PERN1/USB3RN2
PERP1/USB3RP2
B
RC151
3K_0402_1%
1
2
USB3TN0
USB3TP0
AN8
AM8
AJ10
AJ11
AN10
AM10
AL3
AT1
AH2
AV3
USBRBIAS
USB_OC0#
USB_OC1#
USB_OC2#
USB1_PWR_EN
RC148
1
2
USB_OC0# & lt; 24,9 & gt;
USB_OC1# & lt; 24 & gt;
USB_OC2# & lt; 9 & gt;
B
+3V_PCH
RPH17
DG V0.9 PCIE_RCOMP
Width=12mil,spacing=12mil
Max length=500mil
11 OF 19
USB_OC1#
WL_OFF#
USB1_PWR_EN
& lt; 21,9 & gt; WL_OFF#
4
3
2
1
5
6
7
8
10K_0804_8P4R_5%
& lt; PV & gt; PRH11 change to RPH17.
A
A
Compal Secret Data
Security Classification
Issued Date
2011/06/29
Deciphered Date
2011/06/29
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
PCIE,USB
Document Number
Rev
0.1
LA-A992P
Thursday, March 20, 2014
Sheet
1
10
of
54
5
4
3
2
1
+VCC_CORE@10000mA
+VCC_CORE
HASWELL_MCP_E
UCPU1L
L59
J58
+1.35V_VDDQ
2500mA AH26
+VCC_CORE
AJ31
AJ33
AJ37
AN33
AP43
AR48
AY35
AY40
AY44
AY50
D
+1.05VS_VCCST
SVID ALERT
DG V0.5 H_CPU_SVIDALRT#
RC154 close to CPU & lt; 300mil
Max length=1000~2000mil
1
L
RC154
VCC_SENSE
& lt; PWR VR12.6 & gt;
H_CPU_SVIDALRT#
1
& lt; 4,6 & gt; +1.05VS_PG
& lt; 50 & gt; VR12.5_VR_ON
VR12.6PG_MCP
RC156
110_0402_1%
CPU_PWR_DEBUG
2
& lt; PWR VR12.6 & gt;
C
VR_SVID_DAT
& lt; 50 & gt; VR_SVID_DAT
+VCCIO_OUT
+1.05VS_VCCST
@
& lt; CPU & gt;
RC294
+1.05VS
L
1
+VCC_CORE
2 0_0402_5%
L62
N63
L63
B59
F60
C59
H_CPU_SVIDALRT#
VR_SVID_CLK
VR_SVID_DAT
& lt; 50 & gt; VR_SVID_CLK
+1.05VS_VCCST
SVID DATA
+VCCIO_OUT
+VCCIOA_OUT
& lt; VR IV and CPU & gt;
& lt; EDP_COMP power rail & gt;
2
2
RC155 1
43_0402_1%
& lt; 50 & gt; VR_SVID_ALRT#
E63
AB23
A59
E20
AD23
AA23
AE59
VCCSENSE
& lt; 50 & gt; VCCSENSE
75_0402_5%
& lt; PWR VR12.6 & gt;
F59
N58
AC58
PH on power page
600mA
D63
H59
P62
P60
P61
N59
N61
T59
AD60
AD59
AA59
AE60
AC59
AG58
U59
V59
AC22
AE22
AE23
AB57
AD57
AG57
C24
C28
C32
DG V0.5 VIDSOUT
RC156 close to CPU & lt; 500mil
Max length=1000~2000mil
RSVD
RSVD
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VCCIN
RSVD
RSVD
VCC_SENSE
RSVD
VCCIO_OUT
VCCIOA_OUT
RSVD
RSVD
RSVD
VIDALERT
VIDSCLK
VIDSOUT
VCCST_PWRGD
VR_EN
VR_READY
HSW ULT POWER
VSS
PWR_DEBUG
VSS
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCCST
VCCST
VCCST
VCC
VCC
VCC
VCC
VCC
VCC
C36
C40
C44
C48
C52
C56
E23
E25
E27
E29
E31
E33
E35
E37
E39
E41
E43
E45
E47
E49
E51
E53
E55
E57
F24
F28
F32
F36
F40
F44
F48
F52
F56
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
H23
J23
K23
K57
L22
M23
M57
P57
U57
W57
D
C
12 OF 19
+1.05VS_VCCST
+3V_PCH
short@
RC223 1
CC71
22U_0805_6.3V6M
0_0805_5%
@
RC167
10K_0402_5%
10K_0402_5%
1
2
& lt; 50 & gt; VGATE
2
1
2
B
RC288
10K_0402_5%
UC8
1
CPU_PWR_DEBUG
2
+1.05VS_VCCST
3
NC
VCC
5
2
+1.05VS
CC72
1U_0402_6.3V6K
1
2
RC166
150_0402_5%
150_0402_5%
B
1
+1.05VS_VCCST
A
Y
4
VR12.6PG_MCP
GND
74AUP1G07GW_TSSOP5
1
@
2
+1.35V_VDDQ
2
@
1
2
1
2
@
1
2
1
2
@
1
2
1
2
CC31
10U_0603_6.3V6M
+
CC30
CC30
10U_0603_6.3V6M
330U_2.5V_M
CC29
10U_0603_6.3V6M
2
1
CC25
CC28
10U_0603_6.3V6M
2
330U_2.5V_M
+
CC27
10U_0603_6.3V6M
2
1
CC24
CC26
10U_0603_6.3V6M
10U_0603_6.3V6M
2
1
CC23
2.2U_0402_6.3V6M
1
@
CC22
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
1
CC21
2.2U_0402_6.3V6M
2
CC20
2.2U_0402_6.3V6M
1
+1.35V_VDDQ
@
A
A
Compal Secret Data
Security Classification
2011/06/29
Issued Date
Deciphered Date
2011/06/29
Title
Compal Electronics, Inc.
Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
0.1
LA-A992P
Date:
5
4
3
2
Thursday, March 20, 2014
Sheet
1
11
of
54
Use +1.05V
RC173
0_0402_5%
+1.05V
1 @
2
2
1
CC45
1
CC46
10U_0603_6.3V6M
2
1U_0402_6.3V6K
Y20
AA21
W21
+1.05VS_APPLOPI
AH14
RC172
1
2 0_0402_5%
2
RC176
+1.05VS_APPLOPI
2
+3VS
2
1
2
B
RC281
1
+1.05VS
2
short@
0_0603_5%
+V1.05S_SSCFF
1
1
CORE
AXALIA/HDA
VCCSUSHDA
VRM/USB2/AZALIA
DCPSUS2
VCCSUS3_3
VCCSUS3_3
VCCDSW3_3
VCC3_3
VCC3_3
GPIO/LCC
THERMAL SENSOR
VCC1P05
VCC1P05
VCC1P05
VCC1P05
VCC1P05
DCPSUSBYP
DCPSUSBYP
VCCASW
VCCASW
VCCASW
DCPSUS1
DCPSUS1
VCCTS1_5
VCC3_3
VCC3_3
+1.05VS_AXCK_LCPLL
+V1.05S_SSCF100
+V1.05S_SSCFF
+3V_PCH
124mA
J18
K19
A20
J17
R21
T21
K18
M20
V21
AE20
AE21
VCC1P05
VCC1P05
VCCACLKPLL
VCCCLK
VCCCLK
VCCCLK
VCCCLK
VCCCLK
VCCCLK
VCCSUS3_3
VCCSUS3_3
+1.05VS
2
CC44 @
0.1U_0402_16V7K
1.6A
J11
H11
H15
AE8
AF22
AG19
AG20
AE9
AF9
AG8
AD10
AD8
1
RC174
5.11_0402_1%
2
1
CC52
1U_0402_6.3V6K
1
2
+1.05VS_VCCASW
+1.05V_DCPSUS
J15
K14
K16
USB2
DCPSUS4
VCCAPLL
VCCIO
VCCIO
1
+1.05V_AOSCSUS
2
AC20
AG16
AG17
1
13 OF 19
2
+3V_DSW_P
2
RC182
2 0_0402_5%
1
Deep S3 RC285-- & gt; SMT
2 0_0402_5% +3V_DSW_P
1
Non Deep S3 RC182-- & gt; SMT
+1.05VS_AXCK_LCPLL
2.2UH_LQM2MPN2R2NG0L_30%
1
A
2
1
2
31mA
2
+1.05VS
C
2
+1.05VS
0_0805_5%
1
2
RC178
short@
1
2 0_0603_5%
+3VS
@
+1.05VS
B
RC180
1
+1.05V_AOSCSUS
@
2
+1.05V
2.2UH_LQM2MPN2R2NG0L_30%
1
1
2
2
@
Total 1.5VS=3mA
2
2
2
1
2
short@
RC175 1
Total 1.05VS=1838+2274=4111mA
@
RC181
1
1
+3V_PCH
+1.05VS_AXCK_LCPLL
+1.05VS
RC285
1
1
2
0.1U_0402_16V7K
+3V_1V8_SDIO
U8
T9
AB8
2
0.658A
+1.5VS
+3VS
LPT LP POWER
SUS OSCILLATOR
SPI ROM power rail
+3V_PCH
1
VCCSDIO
VCCSDIO
2
1
AG14
AG13
CC76
SDIO/PLSS
@
18mA
Y8
ICC
+1.05VS_AXCKDCB
+3VALW
CC69
1U_0402_6.3V6K
2
VCCASW
VCCASW
2
2 0.1U_0402_16V7K
short@
CC68
47U_0805_6.3V6M
2.2UH_LQM2MPN2R2NG0L_30% 1
VCCSPI
AH11
AG10
AE7 CC40 1
Deep S3 and Non Deep S3
+1.05VS_AXCKDCB
CC64
1U_0402_6.3V6K
2
CC63
47U_0805_6.3V6M
RC179
1
VCCSUS3
VCCRTC
DCPRTC
DCPSUS3
2
62mA
2
+1.05VS
1
+V1.05S_SSCF100
0_0603_5%
AC9
AA9
AH10
V8
W9
+3V_DSW_P
1
OPI
CC70
1U_0402_6.3V6K
1 RC280
+1.05VS
2
+3V_PCH
57mA
CC55
22U_0805_6.3V6M
2
1
CC58
1U_0402_6.3V6K
1
CC61
1U_0402_6.3V6K
2.2UH_LQM2MPN2R2NG0L_30%
CC62
1U_0402_6.3V6K
2
CC57
22U_0805_6.3V6M
+1.05VS
1
AH13
CC59
22U_0805_6.3V6M
+1.5VS
CC51
1U_0402_6.3V6K
1
short@
& lt; DB & gt; Aduio code power rail
SPI
VCCAPLL
VCCAPLL
VCCAPLL
USB3
J13
+1.05V_DCPSUS
+VCCSUSHDA
C
RTC
mPHY
D
1
CC50
10U_0603_6.3V6M
2
2
42mA
+RTCVCC
1
VCCHSIO
VCCHSIO
VCCHSIO
VCCIO
VCCIO
VCCUSB3PLL
VCCSATA3PLL
+3V_PCH
CC49
1U_0402_6.3V6K
1
+1.05VS_VCCUSB3PLL
+1.05VS_VCCSATA3PLL
K9
L10
M9
N8
P9
B18
B11
+RTCVCC
HASWELL_MCP_E
UCPU1M
1 0_0402_5%
CC67
100U_1206_6.3V6K
2
CC43
1U_0402_6.3V6K
+1.05VS_VCCSATA3PLL
1
2
short@
RC169 2
CC48
1U_0402_6.3V6K
2
CC42
47U_0805_6.3V6M
1
2.2UH_LQM2MPN2R2NG0L_30%
1
CC39
1U_0402_6.3V6K
1
+3V_DSW_PRTCSUS
CC54
22U_0805_6.3V6M
+1.05VS
+1.05VS_VCCSATA3PLL
2
65mA
1U_0402_6.3V6K
CC66
2
1
CC32
1U_0402_6.3V6K
41mA
RC171
+1.05VS_MODPHY
+1.05VS_VCCHSIO
1
CC53
1U_0402_6.3V6K
2
1.838A
1
CC37
CC37
0.1U_0402_16V7K
0.1U_0402_16V7K
2
D
1
2
0_0805_5%
CC41
1U_0402_6.3V6K
1
CC36
1U_0402_6.3V6K
2.2UH_LQM2MPN2R2NG0L_30%
CC35
47U_0805_6.3V6M
+1.05VS_MODPHY
+1.05VS_VCCUSB3PLL
2
CC65
1U_0402_6.3V6K
short@
RC168 1
+1.05VS_MODPHY
2
CC34
1U_0402_6.3V6K
+1.05VS_VCCUSB3PLL
RC170
1
3
CC60
1U_0402_6.3V6K
4
CC33
1U_0402_6.3V6K
5
Total 1.8VS=7mA
Total 3VS=0mA
Total 3VALW=200+62=262mA
Total 3V_PCH=99mA
Total 1.05V=540+109=649mA
Compal Secret Data
Security Classification
Issued Date
A
2011/06/29
2011/06/29
Deciphered Date
Title
Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
0.1
LA-A992P
Date:
5
4
3
2
Sheet
Thursday, March 20, 2014
1
12
of
54
5
4
3
2
1
UCPU1NHASWELL_MCP_E
D
C
B
A11
A14
A18
A24
A28
A32
A36
A40
A44
A48
A52
A56
AA1
AA58
AB10
AB20
AB22
AB7
AC61
AD21
AD3
AD63
AE10
AE5
AE58
AF11
AF12
AF14
AF15
AF17
AF18
AG1
AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57
AJ13
AJ14
AJ23
AJ25
AJ27
AJ29
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20
UCPU1O
AP22
AP23
AP26
AP29
AP3
AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49
AR5
AR52
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63
AU1
AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
HASWELL_MCP_E
15 OF 19
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AV59
AV8
AW16
AW24
AW33
AW35
AW37
AW4
AW40
AW42
AW44
AW47
AW50
AW51
AW59
AW60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33
AY4
AY51
AY53
AY57
AY59
AY6
B20
B24
B26
B28
B32
B36
B4
B40
B44
B48
B52
B56
B60
C11
C14
C18
C20
C25
C27
C38
C39
C57
D12
D14
D18
D2
D21
D23
D25
D26
D27
D29
D30
D31
UCPU1P
D33
D34
D35
D37
D38
D39
D41
D42
D43
D45
D46
D47
D49
D5
D50
D51
D53
D54
D55
D57
D59
D62
D8
E11
E17
F20
F26
F30
F34
F38
F42
F46
F50
F54
F58
F61
G18
G22
G3
G5
G6
G8
H13
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
HASWELL_MCP_E
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_SENSE
VSS
16 OF 19
D
H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63
C
V58
AH46
V23
E62
AH16
& lt; PWR VR12.6 & gt;
VSSSENSE & lt; 50 & gt;
B
14 OF 19
A
A
Compal Secret Data
Security Classification
Issued Date
2010/05/27
Deciphered Date
2011/05/11
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Compal Electronics, Inc.
GND/VSSSEN
Document Number
Rev
0.1
LA-A992P
Thursday, March 20, 2014
Sheet
1
13
of
54
5
4
3
2
1
HASWELL_MCP_E
CFG4
1
UCPU1Q
DC_TEST_AY61_AW61
DC_TEST_AY61_AW62
TP_DC_TEST_A3_B3
DC_TEST_A61_B61
DC_TEST_B62_B63
D
DC_TEST_C1_C2
AY2
AY3
AY60
AY61
AY62
B2
B3
B61
B62
B63
C1
C2
DAISY_CHAIN_NCTF_AY2
DAISY_CHAIN_NCTF_AY3
DAISY_CHAIN_NCTF_AY60
DAISY_CHAIN_NCTF_AY61
DAISY_CHAIN_NCTF_AY62
DAISY_CHAIN_NCTF_B2
DAISY_CHAIN_NCTF_B3
DAISY_CHAIN_NCTF_B61
DAISY_CHAIN_NCTF_B62
DAISY_CHAIN_NCTF_B63
DAISY_CHAIN_NCTF_C1
DAISY_CHAIN_NCTF_C2
DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4
17 OF 19
DAISY_CHAIN_NCTF_A60
DAISY_CHAIN_NCTF_A61
DAISY_CHAIN_NCTF_A62
DAISY_CHAIN_NCTF_AV1
DAISY_CHAIN_NCTF_AW1
DAISY_CHAIN_NCTF_AW2
DAISY_CHAIN_NCTF_AW3
DAISY_CHAIN_NCTF_AW61
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AW63
A3
A4
TP_DC_TEST_A3_B3
RC185
1K_0402_1%
A60
A61 DC_TEST_A61_B61
A62
AV1
AW1
AW2 DC_TEST_AY2_AW2
AW3 DC_TEST_AY3_AW3
AW61 DC_TEST_AY61_AW61
AW62 DC_TEST_AY61_AW62
AW63
2
DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
D
Display Port Presence Strap
CFG4
AT2
AU44
AV44
D15
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
F22
H22
J21
C
*
HASWELL_MCP_E
UCPU1R
RSVD
RSVD
RSVD
RSVD
RSVD
TP2
TP1
RSVD
RSVD
RSVD
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
N23
R23
T23
U10
AL1
AM11
AP7
AU10
AU15
AW14
AY14
C
18 OF 19
UCPU1S
PAD @
PAD @
PAD @
PAD @
PAD @
PAD @
PAD @
PAD @
PAD @
PAD @
PAD @
PAD @
PAD @
PAD @
PAD @
T64
T65
T66
T67
T68
T69
T70
T71
T72
T73
T74
PAD @
PAD @
PAD @
PAD @
B
T59
T60
T61
T63
T75
T76
T77
T78
2
RC188
AC60
AC62
AC63
AA63
AA60
Y62
Y61
Y60
V62
V61
V60
U60
T63
T62
T61
T60
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
AA62
U63
AA61
U62
CFG16
CFG18
CFG17
CFG19
1
CFG_RCOMP
49.9_0402_1%
V63
A5
1
RC191
E1
D1
J20
H18
B12
2
TD_IREF
8.2K_0402_5%
HASWELL_MCP_E
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
EDP_SPARE
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RESERVED
RSVD
RSVD
OPI_COMP1
CFG16
CFG18
CFG17
CFG19
RSVD
RSVD
CFG_RCOMP
VSS
VSS
RSVD
HVM_CLK
HVM_CLK_P
TP9
TP10
TP11
TP12
TD_IREF
AV63
AU63
C63
C62
B43
A51
B51
L60
B
N60
W23
Y22
AY15
MCP_RSVD_29
PROC_OPI_COMP
RC296
RC186
2
2
1 49.9_0402_1%
1 49.9_0402_1%
@
L
AV62
D58
DG V0.9 PROC_OPI_COMP
Width=12mil,spacing=12mil
Max length=500mil
P22
N21
P20
R20
19 OF 19
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/06/29
Deciphered Date
2011/06/29
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
RSVD/CFG
Document Number
Rev
0.1
LA-A992P
Thursday, March 20, 2014
Sheet
1
14
of
54
5
4
3
+V_VDDR_REFA_DQ
2
+1.35V_VDDQ
1
+1.35V_VDDQ
JDIMM1
DDR_A_D29
DDR_A_D28
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_A_D44
DDR_A_D41
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D43
DDR_A_D47
DDR_A_D51
DDR_A_D50
D
DDR_A_D9
DDR_A_D12
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D15
DDR_A_D11
DDR_A_D25
DDR_A_D24
DDR3_DRAMRST#
DDR3_DRAMRST#
1
DDR_A_D27
DDR_A_D26
2
DDR_A_D45
DDR_A_D40
& lt; 16,4 & gt;
@ESD@
CD99
0.1U_0402_16V7K
+1.35V_VDDQ
+5VALW
DDR_A_D42
DDR_A_D46
QD1
BSS138_NL_SOT23-3
1
3
RD20 1
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D54
DDR_A_D55
@
RD25
2 66.5_0402_1% M_ODT1
RD23 1
2 66.5_0402_1% M_ODT2
RD24 1
220K_0402_5%
2 66.5_0402_1% M_ODT0
RD22 1
RD21
DDR_A_D52
DDR_A_D53
2 66.5_0402_1% M_ODT3
SM_PG_CTRL
M_ODT2 & lt; 16 & gt;
M_ODT3 & lt; 16 & gt;
SM_PG_CTRL & lt; 4 & gt;
2M_0402_5%
2
DDR_A_D49
DDR_A_D48
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
S
& lt; 5 & gt; DDR_A_MA[0..15]
DDR_A_D14
DDR_A_D10
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
D
2
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
2
G
& lt; 5 & gt; DDR_A_DQS#[0..7]
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
1
& lt; 5 & gt; DDR_A_DQS[0..7]
DDR_A_D13
DDR_A_D8
2
1
CD1
0.1U_0402_16V7K
& lt; 5 & gt; DDR_A_D[0..63]
1
+V_VDDR_REFA_DQ
D
C
C
DDR_CKE0_DIMMA
& lt; 5 & gt; DDR_CKE0_DIMMA
DDR_A_BS2
& lt; 5 & gt; DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
M_CLK_DDR0
M_CLK_DDR#0
& lt; 5 & gt; M_CLK_DDR0
& lt; 5 & gt; M_CLK_DDR#0
& lt; 5 & gt; DDR_A_BS0
DDR_A_MA10
DDR_A_BS0
& lt; 5 & gt; DDR_A_WE#
& lt; 5 & gt; DDR_A_CAS#
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_CS1_DIMMA#
& lt; 5 & gt; DDR_CS1_DIMMA#
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D6
B
DDR_A_D21
DDR_A_D20
DDR_A_D17
DDR_A_D16
DDR_A_D36
DDR_A_D33
+1.35V_VDDQ
2
1
2
1
2
CD13
10U_0603_6.3V6M
2
@
CD12
CD12
10U_0603_6.3V6M
10U_0603_6.3V6M
2
1
CD11
10U_0603_6.3V6M
2
1
@
CD10
10U_0603_6.3V6M
2
1
CD9
10U_0603_6.3V6M
2
1
CD8
10U_0603_6.3V6M
1
@
CD7
10U_0603_6.3V6M
CD6
10U_0603_6.3V6M
1
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D38
@
DDR_A_D62
DDR_A_D58
DDR_A_D60
DDR_A_D61
+1.35V_VDDQ
2
205
G1
G2
DDR_CKE1_DIMMA
& lt; 5 & gt;
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
M_CLK_DDR1
M_CLK_DDR#1
M_CLK_DDR1 & lt; 5 & gt;
M_CLK_DDR#1 & lt; 5 & gt;
DDR_A_BS1
DDR_A_RAS#
DDR_A_BS1 & lt; 5 & gt;
DDR_A_RAS# & lt; 5 & gt;
DDR_CS0_DIMMA#
M_ODT0
DDR_CS0_DIMMA#
& lt; 5 & gt;
+V_VDDR_REFA_CA
M_ODT1
+V_VDDR_REFA_CA
DDR_A_D5
DDR_A_D4
1
DDR_A_D3
DDR_A_D7
2
DDR_A_D18
DDR_A_D19
B
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D22
DDR_A_D23
DDR_A_D37
DDR_A_D32
DDR_A_D35
DDR_A_D39
DDR_A_D63
DDR_A_D59
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D56
DDR_A_D57
+0.6V_0.675VS
PCH_SMBDATA
PCH_SMBCLK
PCH_SMBDATA & lt; 16,7 & gt;
PCH_SMBCLK & lt; 16,7 & gt;
1
+0.6V_0.675VS
206
2
FOX_AS0A626-U4R6-7H
1
2
CONN@
1
2
10U_0603_6.3V6M
2
DDR_CKE1_DIMMA
CD24
2
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
CD21
0.1U_0402_16V7K
2
1
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
CD19
0.1U_0402_16V7K
2
+3VS
CD17
CD17
0.1U_0402_16V7K
0.1U_0402_16V7K
@
1
CD66
1U_0402_6.3V6K
2
1
CD65
CD65
1U_0402_6.3V6K
1U_0402_6.3V6K
@
1
CD64
1U_0402_6.3V6K
2
1
CD63
1U_0402_6.3V6K
@
1
CD58
1U_0402_6.3V6K
2
1
CD57
1U_0402_6.3V6K
1
CD56
1U_0402_6.3V6K
2
CD55
1U_0402_6.3V6K
1
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
CD3
0.1U_0402_16V7K
DDR_A_D0
DDR_A_D1
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
A
A
Compal Secret Data
Security Classification
Issued Date
2011/06/29
Deciphered Date
2011/06/29
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
DDR3L DIMM0
Document Number
Rev
0.1
LA-A992P
Sheet
Thursday, March 20, 2014
1
15
of
54
5
4
3
+V_VDDR_REFB_DQ
2
+1.35V_VDDQ
1
+1.35V_VDDQ
JDIMM2
+V_VDDR_REFB_DQ
1
& lt; 5 & gt; DDR_B_DQS[0..7]
D
& lt; 5 & gt; DDR_B_DQS#[0..7]
2
& lt; 5 & gt; DDR_B_MA[0..15]
CD27
0.1U_0402_16V7K
& lt; 5 & gt; DDR_B_D[0..63]
DDR_B_D8
DDR_B_D14
DDR_B_D10
DDR_B_D11
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D26
DDR_B_D27
DDR_B_D40
DDR_B_D41
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D42
DDR_B_D56
DDR_B_D57
DDR_B_D59
DDR_B_D58
DDR_CKE0_DIMMB
& lt; 5 & gt; DDR_CKE0_DIMMB
DDR_B_BS2
& lt; 5 & gt; DDR_B_BS2
C
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
M_CLK_DDR2
M_CLK_DDR#2
& lt; 5 & gt; M_CLK_DDR2
& lt; 5 & gt; M_CLK_DDR#2
& lt; 5 & gt; DDR_B_BS0
DDR_B_MA10
DDR_B_BS0
& lt; 5 & gt; DDR_B_WE#
& lt; 5 & gt; DDR_B_CAS#
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_CS1_DIMMB#
& lt; 5 & gt; DDR_CS1_DIMMB#
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D3
DDR_B_D7
DDR_B_D21
DDR_B_D20
B
DDR_B_D22
DDR_B_D23
DDR_B_D36
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
+1.35V_VDDQ
DDR_B_D35
DDR_B_D39
2
2
@
DDR_B_D48
DDR_B_D53
2
2
DDR_B_DQS#1
DDR_B_DQS1
D
DDR_B_D13
DDR_B_D15
DDR_B_D25
DDR_B_D24
DDR3_DRAMRST#
DDR3_DRAMRST#
& lt; 15,4 & gt;
DDR_B_D30
DDR_B_D31
DDR_B_D45
DDR_B_D44
DDR_B_D47
DDR_B_D43
DDR_B_D61
DDR_B_D60
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D63
DDR_B_D62
DDR_CKE1_DIMMB
DDR_CKE1_DIMMB
& lt; 5 & gt;
DDR_B_MA15
DDR_B_MA14
C
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3
M_CLK_DDR3 & lt; 5 & gt;
M_CLK_DDR#3 & lt; 5 & gt;
DDR_B_BS1
DDR_B_RAS#
DDR_B_BS1 & lt; 5 & gt;
DDR_B_RAS# & lt; 5 & gt;
DDR_CS0_DIMMB#
M_ODT2
DDR_CS0_DIMMB#
M_ODT2 & lt; 15 & gt;
M_ODT3
M_ODT3 & lt; 15 & gt;
& lt; 5 & gt;
+V_VDDR_REFA_CA
+V_VDDR_REFA_CA
DDR_B_D5
DDR_B_D0
1
DDR_B_D2
DDR_B_D6
2
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
B
DDR_B_D19
DDR_B_D18
DDR_B_D37
DDR_B_D32
DDR_B_D34
DDR_B_D38
DDR_B_D51
DDR_B_D55
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D54
DDR_B_D50
+0.6V_0.675VS
PCH_SMBDATA
PCH_SMBCLK
PCH_SMBDATA & lt; 15,7 & gt;
PCH_SMBCLK & lt; 15,7 & gt;
+0.6V_0.675VS
1
206
FOX_AS0A626-U4R6-7H
2
CONN@
1
2
1
2
10U_0603_6.3V6M
@
G2
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
DDR_B_D12
DDR_B_D9
CD50
2
G1
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
CD46
0.1U_0402_16V7K
@
1
CD70
1U_0402_6.3V6K
2
1
CD69
CD69
1U_0402_6.3V6K
1U_0402_6.3V6K
@
1
CD68
1U_0402_6.3V6K
2
1
CD67
1U_0402_6.3V6K
2
1
CD62
1U_0402_6.3V6K
2
1
CD61
1U_0402_6.3V6K
1
CD60
1U_0402_6.3V6K
2
CD59
1U_0402_6.3V6K
1
+3VS
205
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
CD45
0.1U_0402_16V7K
2
+1.35V_VDDQ
RD4
10K_0402_5%
1
CD44
CD44
0.1U_0402_16V7K
0.1U_0402_16V7K
+3VS
1
@
DDR_B_D52
DDR_B_D49
2
2
1
CD40
10U_0603_6.3V6M
2
1
CD39
CD39
10U_0603_6.3V6M
10U_0603_6.3V6M
@
1
CD38
10U_0603_6.3V6M
2
1
CD37
10U_0603_6.3V6M
2
1
CD36
10U_0603_6.3V6M
2
1
CD35
10U_0603_6.3V6M
@
1
CD34
10U_0603_6.3V6M
2
CD33
10U_0603_6.3V6M
1
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
CD29
0.1U_0402_16V7K
DDR_B_D4
DDR_B_D1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
A
A
Compal Secret Data
Security Classification
Issued Date
2010/05/27
Deciphered Date
2011/05/11
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Compal Electronics, Inc.
DDR3L DIMM1
Document Number
Rev
0.1
LA-A992P
Sheet
Thursday, March 20, 2014
1
16
of
54
5
4
3
2
1
DDR3L VREF
+1.35V_VDDQ
+1.35V_VDDQ
1
D
1
D
RD5
1.8K_0402_1%
RD6
1.8K_0402_1%
+V_VDDR_REFA_DQ
1
& lt; DDR3L_A & gt;
& lt; CPU & gt;
2_0402_1%
2
+V_VDDR_REFA_CA
1
RD10
1.8K_0402_1%
2
2
RD12
@
24.9_0402_1%
2
& lt; DDR3L_A_CA & gt;
& lt; DDR3L_B_CA & gt;
2_0402_1%
2
1
1
RD9
1.8K_0402_1%
RD11
@
24.9_0402_1%
2
1
CD53
0.022U_0402_25V7K
1
CD52
0.022U_0402_25V7K
1
+V_SM_VREF_CNT
2
RD8
2
2
1
+V_DDR_REFA_R
2
RD7
& lt; CPU & gt;
@
@
+1.35V_VDDQ
C
1
C
RD13
1.8K_0402_1%
1
+V_DDR_REFB_R
2
2
RD15
& lt; CPU & gt;
+V_VDDR_REFB_DQ
1
1
2
RD17
1.8K_0402_1%
2
RD19
@
24.9_0402_1%
2
1
CD54
0.022U_0402_25V7K
& lt; DDR3L_B & gt;
2_0402_1%
@
B
B
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/06/29
Deciphered Date
2011/06/29
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
DDR3L VREF
Document Number
Rev
0.1
LA-A992P
Thursday, March 20, 2014
Sheet
1
17
of
54
@ JPHW7
2
Close to Pin13
JUMP_43X79
1
2
CT15
CT15
0.1U_0402_16V4Z
2
CT14
0.1U_0402_16V4Z
+3VS_RT
LVDS@ LVDS@
2
LVDS@
LVDS@
LVDS@
LVDS@
LVDS@
LVDS@
MIIC_SDA
+3VS_RT
UT1
LVDS@
@
SWR
LDO
Do not support
& lt; SI & gt; LT7 change to 0 ohm short pad
use LDO mode translator only
mount LT7
TXE1+
TXE1TXE0+
TXE0-
19
20
LVDS_CLKP
LVDS_CLKN
21
22
LVDS_TXP2
LVDS_TXN2
23
24
LVDS_TXP1
LVDS_TXN1
D
25
26
LVDS_TXP0
LVDS_TXN0
RT3
4.7K_0402_5%
LVDS@
MIIC_SCL
LVDS_TXP0 & lt; 19 & gt;
LVDS_TXN0 & lt; 19 & gt;
2132S@
@
RT5
4.7K_0402_5%
LVDS_TXP1 & lt; 19 & gt;
LVDS_TXN1 & lt; 19 & gt;
LVDS_CLKP & lt; 19 & gt;
LVDS_CLKN & lt; 19 & gt;
RT4
4.7K_0402_5%
LVDS@
PIN30
PIN31
& lt; CONN & gt;
+3VS_RT
LVDS@
LCD_EDID_CLK
RTD2132S
2
1
EDP_CPU_LANE_P0
EDP_CPU_LANE_N0
5
6
RT6
LANE0P
LANE0N
1
2 4.7K_0402_5%
LVDS@
LCD_EDID_DATA
AUX_P
AUX_N
DP-IN
DP-IN
EDP_CPU_AUX
EDP_CPU_AUX#
mount LT7
Use 0 ohm
TXE2+
TXE2-
SWR_LX
SWR_VCCK
VCCK
DP_V12
LVDS
SWR / LDO Mode select
SWR_VDD
PVCC
GPIO
+SWR_V12
DP_V33
TXEC+
TXEC-
Power
Power
1 +DP_V33
LT6 2
40mil 3
FBMA-L11-201209-221LMA30T_0805
LVDS@
100mil 13
1 +SWR_VDD
LT5 2
40mil 18
FBMA-L11-201209-221LMA30T_0805
2
1
+SWR_LX
40mil 12
LT7
0_1206_5%
40mil 11
40mil 27
40mil 7
+3VS_RT
2132S@
@
RT2
4.7K_0402_5%
2
1
80mil
2132R
2
1
LVDS@
LVDS@
2132S
1
CT13
2
CT12
2
1
0.1U_0402_16V4Z
10U_0603_6.3V6M
10U_0603_6.3V6M
2
+SWR_V12
1
CT11
0.1U_0402_16V4Z
1
CT10
CT10
CT9
2
0.1U_0402_16V4Z
LVDS@
22U_0603_6.3V6M
CT17
CT17
2
2
1
※ROM only mode : PIN 30 4.7k pull low, Pin 31 4.7k pull high.
EP mode : PIN 30 4.7k pull high, Pin 31 4.7k pull low.
EEPROM : PIN 30 4.7k pull high, Pin 31 4.7k pull high.
〈 ※Default mode 〉
Close to Pin7
CT18
0.1U_0402_16V4Z
CT16
0.1U_0402_16V4Z
10U_0603_6.3V6M
LVDS@
1
2
1
CT8
+DP_V33
1
0.1U_0402_16V4Z
CT7
10U_0603_6.3V6M
Close to Pin3
D
2
Close to
Pin27
+SWR_VDD
Layout note
1
Close to Pin11
2
2
Close to Pin18
1
1
Layout note
Layout note
Close to LT5
2
1
+3VS_RT
80mil
1
1
80mil
2
2
JPHW7 need to short
+3VS
3
1
4
1
5
GPIO(PWM OUT)
GPIO(Panel_VCC)
GPIO(PWM IN)
GPIO(BL_EN)
14
15
16
17
DP_INT_PWM
+DP_ENVDD
BKL_PWM_CPU
TS_BKOFF#
29
28
LCD_EDID_CLK
LCD_EDID_DATA
DP_INT_PWM & lt; 19 & gt;
+DP_ENVDD & lt; 19 & gt;
BKL_PWM_CPU & lt; 4,8 & gt;
RT7
& lt; CONN & gt;
& lt; CPU & gt;
1
2 4.7K_0402_5%
PIN15
PIN16
Accept voltage input (high level)
C
C
※ If use 2132R, please select LDO mode as default.
9
10
& lt; CPU CTRL & gt;
CIICSCL1
CIICSDA1
LVDS@
1
2 RT192
1K_0402_1%
2
RT11
100K_0402_5%
2
RT8
12K_0402_1%
LVDS@
32
8
4
HPD
LVDS
EDID
ROM
MIICSCL1
MIICDA1
MIICSCL0
MIICSDA0
DP_REXT
DP_GND
LVDS@
GND
31
30
2132S
2132R
MIIC_SCL
MIIC_SDA
TL_ENVDD
2132S
+LCD_VDD *
33
2132R
Different between 2132S and 2132R
Layout note
1
2
RT9
0_0805_5%
LVDS@
Close to Pin15
1
2 .1U_0402_16V7K
2 .1U_0402_16V7K
2 .1U_0402_16V7K
EDP_CPU_LANE_N0
RT10
100K_0402_5%
LVDS@
EDP_CPU_LANE_P0
1
2
CT23
4.7U_0603_6.3V6K
LVDS@ 1
EDP_CPU_AUX#
1
CC97
& lt; 4 & gt; EDP_CPU_LANE_N0_C
EDP_CPU_AUX
CC98
& lt; 4 & gt; EDP_CPU_LANE_P0_C
2 .1U_0402_16V7K
CC101
& lt; 4 & gt; EDP_CPU_AUX#_C
B
1
2
CC102
1
+DP_ENVDD
80ml trace width
2132R
1. Support SWR mode 1. Support LDO mode and SWR mode
2. Internal ROM
3. Support LCD_VDD(internal Power switch)
4. Integrates Level shifter
+LCDVDD
Close to Pin8
& lt; 4 & gt; EDP_CPU_AUX_C
1.5~3.3V
RTD2132R-CG QFN32
SA000069200
2132S
& lt; CPU & gt;
3.3V
* Version R has internal level shifter, remove
level shifter circuit on AMD platform
* Version R internal Power Switch, can
output 1A, Rds(on)=0.2 ohm
1
1
EDP_HPD
& lt; 8 & gt; EDP_HPD
Other
& lt; 30,32,7 & gt; EC_SMB_CK2
& lt; 30,32,7 & gt; EC_SMB_DA2
B
Close to Panel conn.
& lt; CPU by PASS eDP & gt;
& lt; eDP to connector & gt;
0_0804_8P4R_5%
EDP_CPU_LANE_N0
EDP_CPU_LANE_P0
EDP_CPU_AUX
EDP_CPU_AUX#
10/9 colay eDP use close Connector
1
2
3
4
8
7
6
5
RP6
RP9
EDP_LANE_N0
EDP_LANE_P0
EDP_AUX
EDP_AUX#
eDP@
EDP_AUX
EDP_AUX#
EDP_LANE_N0
EDP_LANE_P0
SD309000080
4
3
2
1
RT34 1
eDP@ 2 0_0201_5%
EDP_HPD_PANEL
BKL_PWM_CPU
RT35 1
eDP@ 2 0_0201_5%
DP_INT_PWM
@
1
+3VS
P
5
& lt; PV & gt; Add RT12
2
TC7SH08FUF_SSOP5
LVDS@
RT12
100K_0402_5%
LVDS@
Y
A
LCD_EDID_CLK
LCD_EDID_DATA
LVDS_TXN2
LVDS_TXP2
UT3
4
EC_TS_BKOFF# & lt; 19 & gt;
& lt; LVDS Panel & gt;
G
EC_BKOFF#
0_0804_8P4R_5%
1
2
3
4
8
7
6
5
RP10
& lt; PV & gt; Change PR37 pin define , Add PR38.
& lt; PV & gt; PR36 Change to RP6.
PR37 change to RP9.
LCD_CLK
LCD_DATA
PR38 change to RP10.
LVDS_TXN2_LN0
LVDS_TXP2_LP0
LVDS@ SD309000080
A
3
& lt; 30 & gt; EC_BKOFF#
1
& lt; EC CTRL & gt;
B
& lt; SI & gt; Update UT3 footprint (As UV11)
PD 100K on LVDS page
2
A
1
& lt; LVDS to connector & gt;
2
0.1U_0402_16V7K
TS_BKOFF#
EDP_HPD_PANEL & lt; 19 & gt;
2 0_0402_5%
CT24
& lt; RTS2132 & gt;
Issued Date
2 0_0402_5%
Compal Electronics, Inc.
Compal Secret Data
Security Classification
eDP@
RT15 1
2013/3/1
Deciphered Date
2015/3/1
Title
LVDS Translator-RTD2132R
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
LCD_CLK & lt; 19 & gt;
LCD_DATA & lt; 19 & gt;
LVDS_TXN2_LN0 & lt; 19 & gt;
LVDS_TXP2_LP0 & lt; 19 & gt;
4
EDP_HPD
@
SD309000080
LCD_CLK
LCD_DATA
LVDS_TXN2_LN0
LVDS_TXP2_LP0
0_0804_8P4R_5%
2
RT14 1
eDP@
5
6
7
8
4
3
2
Document Number
Rev
0.1
LA-A992P
Thursday, March 20, 2014
1
Sheet
18
of
54
5
4
2
+3VALW
eDP@
UG1
OUT
1
4
eDP@ 2
SS
1
CG1
eDP@
1500P_0402_50V7K
EN
1
2132S@
3
APL3512_SOT23-5
2132S@
2
1
4.7U_0603_6.3V6K
2
@
eDP@
RTS1
1K_0402_5%
2 0_0402_5%
1
3
2 0_0402_5%
& lt; PV & gt; Change BOM structure
Camera
R170
@
1
1
& lt; 10 & gt; USB20_N4
Part Number = SM070003Y00
4
& lt; 10 & gt; USB20_P4
C
1
2
4
3
2
INVTPWM
USB20_P4_R
3
USB20_N4_R
USB20_P4_R
3
C
@ESD@ SCA00000U10
LCD/LED PANEL Conn.
1
+LCDVDD
LCD_CLK
LCD_DATA
& lt; 18 & gt; LCD_CLK
& lt; 18 & gt; LCD_DATA
2
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
& lt; 18 & gt; LVDS_TXP0
& lt; 18 & gt; LVDS_TXN0
PESD5V0U2BT_SOT23-3
& lt; 18 & gt; LVDS_TXP1
& lt; 18 & gt; LVDS_TXN1
@ESD@ SCA00000U10
& lt; DB & gt; LA1/LA2 closed to Aduio codec
DISPOFF#
& lt; 18 & gt; LVDS_TXP2_LP0
& lt; 18 & gt; LVDS_TXN2_LN0
EMI@
1
& lt; 18 & gt; EC_TS_BKOFF#
B
1 220P_0402_50V7K DISPOFF#
PESD5V0U2BT_SOT23-3
2 0_0402_5%
D3
D_MIC_L_DATA
R166 33_0402_5%
2
1 220P_0402_50V7K INVTPWM
C122 2
1
1
D
CONN@
JLVDS1
D_MIC_L_CLK
EC_TS_BKOFF#
SM010014520 3000ma
220ohm@100mhz
DCR 0.04
C121 2
@
R163
10K_0402_5%
2
2 0_0402_5%
C118
68P_0402_50V8J
2
@
0_0402_5%
R258 1 @
2
& lt; PV & gt; Change Touch power to 3V
& lt; PV & gt; L12 change PN.
& lt; 18 & gt; DP_INT_PWM
1
1
1 R171
2
@EMI@ C117
680P_0402_50V7K
TOUCH_ON# & lt; 30 & gt;
D5
USB20_N4_R
WCM-2012-900T_4P
@
2
G
1
2
D
2 0_0402_5%
L12 EMI@
1
R259
@EMI@ 0_0805_5%
1 L2
2
1 eDP@
eDP@
CTS1
0.1U_0402_16V4Z QTS2
S TR LP2301ALT1G 1P SOT-23-3
2
eDP@
& lt; 30 & gt; EC_INVT_PWM
@EMI@
1 L1
0_0805_5% 2
S
+3VS
S
S
D
R172 1
& lt; 8 & gt; ENVDD_CPU
B+
0.047U_0402_16V7K
G
1 @
2
+VCC_TOUCH
RG3
eDP@
QTS1
2N7002K_SOT23
CTS2
1
2
eDP@
2
2
& lt; 18 & gt; +DP_ENVDD
1
eDP@
RTS2
100K_0402_5%
2132S@
1 eDP@
CG2
W=60mils
INVPWR_B+
+LCDVDD
2
CG3
0.1U_0402_16V7K
RG1
GND
W=60mils
2
IN
Touch Screen Power
1
5
0_0201_5%
1
3
+3VS
D
3
2132S@
1
LVDS Power
& lt; 25 & gt; D_MIC_CLK
& lt; 25 & gt; D_MIC_DATA
R167
10K_0402_5%
D_MIC_CLK
D_MIC_DATA
LA1
1
1
LA2
@
FBMA-L10-160808-301LMT_2P
2 D_MIC_L_CLK
2
D_MIC_L_DATA
0_0603_5%
& lt; 18 & gt; LVDS_CLKP
& lt; 18 & gt; LVDS_CLKN
2
& lt; PV & gt; LA1,LA2 change PN, LA2 change to 0ohm.
& lt; MV & gt; LA2 change to short pad.
USB20_N4_R
USB20_P4_R
USB20_P5_R
USB20_N5_R
& lt; 9 & gt; TS_GPIO_CPU
& lt; 30 & gt; TS_GPIO_EC
1
TS_GPIO_CPU R260
@
2
TS_GPIO
DISPOFF#
INVTPWM
TS_GPIO
0_0402_5%
TS_GPIO_EC
1
R261
@
2
0_0402_5%
INVPWR_B+
+VCC_TOUCH
& lt; PV & gt; L13 change PN,BS.
& lt; PV & gt; Remove R168,R169.
Touch Screen
3
1
A
1
& lt; 10 & gt; USB20_P5
2
USB20_N5_R
2 0_0402_5%
D_MIC_L_CLK
D_MIC_L_DATA
L13 eDPEMI@
D6
USB20_P5_R
+3VS
@
1
R173
1
2
4
3
2
USB20_P5_R
3
USB20_N5_R
& lt; 18 & gt; EDP_HPD_PANEL
Part Number = SM070003Y00
4
& lt; 10 & gt; USB20_N5
WCM-2012-900T_4P
PESD5V0U2BT_SOT23-3
1 R174
@ESD@ SCA00000U10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
G1
G2
G3
G4
G5
G6
41
42
43
44
45
46
B
STARC_107K40-000001-G2
2 0_0402_5%
A
& lt; PV & gt; JLVDS1 pin40 change to NC.
@
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/02/26
2015/07/08
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
LVDS Connector
Document Number
Rev
0.1
LA-A992P
Sheet
Thursday, March 20, 2014
1
19
of
54
5
4
3
2
1
+3VS
PCH_DPB_P0_C
PCH_DPB_N0_C
1
1
2
2
CG29
CG30
PCH_DPB_P1_C
PCH_DPB_N1_C
PCH_DPB_P2 0.1U_0402_16V7K
PCH_DPB_N2 0.1U_0402_16V7K
1
1
2
2
CG31
CG32
PCH_DPB_P2_C
PCH_DPB_N2_C
PCH_DPB_P3 0.1U_0402_16V7K
PCH_DPB_N3 0.1U_0402_16V7K
1
1
2
2
CG33
CG34
PCH_DPB_P3_C
PCH_DPB_N3_C
RG47
5
6
7
8
5V Level
1
RG56
CM17 @
220P_0402_50V7K
2
2
2N7002KDW_SOT363-6
QG1B
3
4
D
HP_DETECT
QG1A
2N7002KDW_SOT363-6
4
3
2
1
5
6
7
8
4
3
2
1
RP4
470_0804_8P4R_5%
5
RP3
470_0804_8P4R_5%
6
1
1
& lt; 8 & gt; PCH_DDPB_HPD
20K_0402_5%
& lt; 4 & gt; PCH_DPB_P3
& lt; 4 & gt; PCH_DPB_N3
1M_0402_5%
2
& lt; 4 & gt; PCH_DPB_P2
& lt; 4 & gt; PCH_DPB_N2
D
CG27
CG28
PCH_DPB_P1 0.1U_0402_16V7K
PCH_DPB_N1 0.1U_0402_16V7K
& lt; 4 & gt; PCH_DPB_P1
& lt; 4 & gt; PCH_DPB_N1
2
2
2
& lt; CPU & gt;
1
1
1
PCH_DPB_P0 0.1U_0402_16V7K
PCH_DPB_N0 0.1U_0402_16V7K
& lt; 4 & gt; PCH_DPB_P0
& lt; 4 & gt; PCH_DPB_N0
+3VS
+3VS
@
RG59 1
PCH_DPB_P3_C
4
EMI@ CMMI21T-900Y-N
SM070003K00 LM13
1
1
HDMI_R_CK+
3
2
RG60 1
PCH_DPB_N3_C
0_0402_5%
3
2
2
0_0402_5%
PCH_DDPB_CLK
& lt; 8 & gt; PCH_DDPB_CLK
HDMI_R_CK-
QG2B
4
@
1
2
1
0_0402_5%
HDMI_R_D0-
2
2
4
4
3
3
RG63 1
PCH_DPB_P0_C
2
0_0402_5%
RG64 1
4
EMI@ CMMI21T-900Y-N
SM070003K00 LM15
1
@
2
1
RG65
RG66
1
HDMI_SDATA
HDMI_R_D1+
+3VS
3
RG105
1
2
3
4
2
2
1
PCH_DPB_P2_C
0_0402_5%
3
6
2N7002DWH_SOT363-6
SB00000DH00 QG2A
+HDMI_5V_OUT
4
PCH_DPB_N1_C
1
PCH_DDPB_DAT
& lt; 8 & gt; PCH_DDPB_DAT
HDMI_R_D0+
@
PCH_DPB_P1_C
HDMI_SCLK
2
EMI@ LM14
SM070003K00 CMMI21T-900Y-N
3
2N7002DWH_SOT363-6
SB00000DH00
+3VS
@
RG61 1
PCH_DPB_N0_C
C
5
C
2
4
2
0_0402_5%
HDMI_R_D1-
2
0_0402_5%
8
7
6
5
HDMI_SDATA
HDMI_SCLK
PCH_DDPB_DAT
PCH_DDPB_CLK
HDMI_R_D2+
@
2.2K_0804_8P4R_5%
@
B
B
4
EMI@ CMMI21T-900Y-N
SM070003K00 LM16
1
4
1
2
RG70 1
PCH_DPB_N2_C
3
3
2
HDMI Conn.
2
0_0402_5%
HDMI_R_D2-
@
JHDMI1
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HP_DETECT
HP_DETECT
+HDMI_5V_OUT
109
HP_DETECT
98
HDMI_SDATA
4 4
77
HDMI_SCLK
66
HDMI_R_CK@
OUT
+5VS
1
3
@
1
CM26
3 3
IN
GND
AP2330W-7_SC59-3
2
1
2
8
CG46
0.1U_0402_16V7K 2
IP4292CZ10-TB
1
2
10P_0402_50V8J
2 2
HDMI_SCLK
5 5
+HDMI_5V_OUT
HDMI_SDATA
HDMI_SCLK
10P_0402_50V8J
10P_0402_50V8J
HDMI_SDATA
W=40mils
FG1
@ESD@ DG1
1 1
SC300002800
HDMI_R_CK+
HDMI_R_D0-
CM27
HDMI_R_D0+
HDMI_R_D1HDMI_R_D1+
HDMI_R_D2HDMI_R_D2+
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
20
21
22
23
CONCR_099AKAC19NBLCNF
CONN@
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/06/29
Issued Date
Deciphered Date
2011/06/29
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
A
2
HDMI Conn/Level shift
Document Number
Rev
0.1
LA-A992P
Thursday, March 20, 2014
Sheet
1
20
of
54
5
4
3
2
1
1
+3VS_WLAN
+3VS_WLAN
& lt; 41 & gt; MC_WAKE#
0_0201_5%
2
2
short@
1
RN13
& lt; 30 & gt; EC_PCIE_WAKE#
BT_ON_EC
& lt; 7 & gt; MINI1_CLKREQ#
& lt; 7 & gt; CLK_PCIE_MINI1#
& lt; 7 & gt; CLK_PCIE_MINI1
& lt; 6 & gt; PCIE_PRX_DTX_N6
& lt; 6 & gt; PCIE_PRX_DTX_P6
& lt; 6 & gt; PCIE_PTX_C_DRX_N6
& lt; 6 & gt; PCIE_PTX_C_DRX_P6
C
E51TXD_P80DATA
E51RXD_P80CLK
& lt; 30 & gt; E51TXD_P80DATA
& lt; 30 & gt; E51RXD_P80CLK
+1.5VS_WLAN
RN3
10K_0402_5%
+3VS_WLAN
JMINI1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND1
GND2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
WL_OFF#
C
MINI1_LED# & lt; 30 & gt;
54
2
2
E51RXD_P80CLK
1
1 RC160
1K_0402_1%
BT_ON_EC
RN7
4.7K_0402_5%
BELLW_80053-1021
CONN@
R216
100K_0402_5%
WL_OFF# & lt; 10,9 & gt;
PLT_RST# & lt; 23,28,30,32,8 & gt;
+3VS_WLAN
USB20_N3 & lt; 10 & gt;
USB20_P3 & lt; 10 & gt;
2
53
& lt; 30 & gt; BT_ON_EC
D
1
D
+3VS_WLAN
+1.5VS
+1.5VS_WLAN
RN1 @
B
1
B
2
0_0603_5%
1
& lt; PV & gt; Change WLAN power to single load switch.
+5VALW
CN1
+3VALW
Q23
2
4.7U_0603_6.3V6K
1
2
@
& lt; 30 & gt; WL_PWREN_EC
+3VS_WLAN
WL_PWREN_EC
ON
3
VBIAS
R271 @
1
CT
GND
GND
2
1@
CN2
2
4.7U_0603_6.3V6K
1
2
CN3
CN3
0.1U_0402_16V7K
0_0805_5%
& lt; PV & gt; R271 change to 0805
7
8
+3VS_WLAN_R
1
6
1
5
9
2
TPS22967DSGR_SON8_2X2
C558
C558
100P_0402_50V8J
4
VOUT
VOUT
2
C571
10U_0603_6.3V6M
+3VS_WLAN_R
VIN
VIN
& lt; PV & gt; C558 change to 100pf for SVTP spec.
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/02/26
Deciphered Date
2015/07/08
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
WLAN
Document Number
Rev
0.1
LA-A992P
Thursday, March 20, 2014
Sheet
1
21
of
54
5
4
2.5 " SATA HDD connector
3
2
JHDD1
+5VS_HDD1
C155 1
C156 1
0_0603_5%
2
+5VS_HDD1
0_0603_5%
2
2
1
2
C150
0.1U_0402_16V7K
0.1U_0402_16V7K
@
R201 1
@
R212 1
1
C149
C149
10U_0603_6.3V6M
+5VS
& lt; 6 & gt; SATA_PRX_DTX_N0
& lt; 6 & gt; SATA_PRX_DTX_P0
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
1
2
3
4
5
6
7
SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0
C153 1
C154 1
& lt; 6 & gt; SATA_PTX_DRX_P0
& lt; 6 & gt; SATA_PTX_DRX_N0
D
1
SATA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0
& lt; SI & gt; RS11 change to un pop
RS11 1
& lt; 8,9 & gt; DEVSLP1
@
@
2 0_0402_5%
GND
GND
23
24
D
2 0_0402_5%
RS12 1
+3VS
GND
A+
AGND
BB+
GND
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
JHDD_P10
+5VS_HDD1
VCC3.3
VCC3.3
VCC3.3
GND
GND
GND
VCC5
VCC5
VCC5
GND
RESERVED
GND
VCC12
VCC12
VCC12
SANTA_193202-1
CONN@
Change to dual load switch for ODD and WLAN
& lt; PV & gt; Q22 change to single load switch.
C
C
+5VALW +5VS
Q22
1
2
C555 1
2
1
100P_0402_50V8J
4
VBIAS
GND
GND
5
9
2
TPS22967DSGR_SON8_2X2
1
1
& lt; MV & gt; Add 22UF for RF suggestion ,4/10.
2
2
@
1
2
1
2
CS12
CS12
10U_0805_10V6K
6
CS13
0.1U_0402_25V6K
CT
Pleace near ODD Connector
+5VS_ODD
CC73
22U_0805_6.3V6M
ON
7
8
CS16
1000P_0402_50V7K
3
VOUT
VOUT
C576
10U_0603_6.3V6M
ODD_PWR
& lt; 9 & gt; ODD_PWR
+5VS_ODD
VIN
VIN
JODD1
CS11
CS14
& lt; 6 & gt; SATA_PTX_DRX_P1
& lt; 6 & gt; SATA_PTX_DRX_N1
B
& lt; 6 & gt; SATA_PRX_DTX_N1
& lt; 6 & gt; SATA_PRX_DTX_P1
2
2
1 0.01U_0402_16V7K
1 0.01U_0402_16V7K
CS15
CS18
2
2
1 0.01U_0402_16V7K
1 0.01U_0402_16V7K
1
2
3
4
5
6
7
SATA_PTX_C_DRX_P1
SATA_PTX_C_DRX_N1
SATA_PRX_C_DTX_N1
SATA_PRX_C_DTX_P1
8
9
10
11
12
13
& lt; 6 & gt; ODD_PLUG#
ODD_DA#
& lt; 9 & gt; ODD_DA#
& lt; SI & gt; Delete Q84, R954
GND
RX+
RXGND
TXTX+
GND
DP
+5V
+5V
MD
GND
GND
B
GND1
GND2
14
15
OCTEK_SLS-13HCAB
1
2
CS17
0.1U_0402_25V6K
ESD@
CONN@
Place CS17 close to JODD
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/02/26
Deciphered Date
2015/07/08
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
ODD/SATA Conn
Document Number
Rev
0.1
LA-A992P
Thursday, March 20, 2014
Sheet
1
22
of
54
3
2
LDO mode
JHW1
3
@
2
1 10K_0402_5%
LAN_PWR_EN_R
2
CL19 close to UL1: Pin 32
LAN_CLKREQ#2
PLT_RST#
& lt; 7 & gt; LAN_CLKREQ#
& lt; 21,28,30,32,8 & gt; PLT_RST#
LAN_CLKREQ#_R
SP050005L00 Footprint
RL11
2.49K_0402_1%
8161@
TCT3
TD3+
TD3-
MCT3
MX3+
MX3-
TCT4
TD4+
TD4-
MCT4
MX4+
MX4-
21
20
19
RJ45_TX2RJ45_TX2+
RP5
1
2
3
4
8
7
6
5
MDIP0
MDIN0
MDIP1
MDIN1
MDIP2
MDIN2
MDIP3
MDIN3
1
RJ45_TX0RJ45_TX0+
YSLC05CH_SOT23-3
ESD@
DL1
@
CL1
0.01U_0402_16V7K
1
1
2
@EMI@
CL4
0.1U_0402_16V7K
LANKO_LG-2446S-1
SP050006800
S X’FORM_ LG-2446S-1 100/1000BASE-TX LAN
TSL1
8166@
SCA00000U10
1
2
1
CL26
8166@
1
CL27
@8166@
2
D
2
EC_LAN_ISOLATEB#
1K_0402_5%
1
RL5
+3VS
RTL8111G
CLKREQB
PERSTB
RSET
LED0
LED1/GPO
LED2
28
29
CKXTAL1
CKXTAL2
LANWAKEB
EC_LAN_ISOLATEB#
27
26
25
LED0
LED1/GPO
LED2(LED1)
HSIP
HSIN
HSOP
HSON
+LAN_VDD_3V3
+VDDREG
RL10 1
+LAN_REGOUT
0_0603_5%
21
20
VDDREG(VDD33)
REGOUT
1
XTLO
XTLO & lt; 31 & gt;
XTLI
+LAN_VDD_3V3
23
24
LANWAKEB
ISOLATEB
REFCLK_P
REFCLK_N
+LAN_VDD_3V3
11
32
AVDD33
AVDD33
+VDDREG=40mil
2
2
1M_0402_5%
@
RL15
10K_0402_5%
1
RL7
XTLO
XTAL@
XTLI
XTLO
EC_PME# & lt; 30,9 & gt;
XTAL@ 1
CL25
TH2
TH1
TH3
2
XTAL@
YL1
XTAL@ 1
CL24
2
C
33
GND
25MHZ 10PF 5YEA25000102IF50Q3
SA00005YT00
& lt; PV & gt; CL24,CL25 change to 10pf.
8166@
SA000063500
RTL8166EH-CG QFN 32P E-LAN CTRL
SANTA_130456-291
RJ45_TX3-
7
RJ45_RX1-
6
RJ45_TX2-
5
RJ45_TX2+
4
RJ45_RX1+
3
RJ45_TX0-
EMI@
CL3
120P_0402_50V8
8
RJ45_TX3+
CL2
SE167100J80
10P_1808_3KV
LANGND
2
2
L
2
RJ45_TX0+
2
RJ45_RX1RJ45_RX1+
15
14
13
2
+LAN_REGOUT=60mil
3
8
30
22
AVDD10
AVDD10
AVDD10
DVDD10
(SA000063500) 10/100 8166@
(SA00005YT00) Giga 8151@
75_0804_8P4R_1%
SD300002E80
18
17
16
1
CL15
@8161@
15K_0402_5%
1
LAN_MDIN0
LAN_MDIP0
10
11
12
MCT2
MX2+
MX2-
RJ45_TX3RJ45_TX3+
1
LAN_MDIN1
LAN_MDIP1
7
8
9
TCT2
TD2+
TD2-
24
23
22
2
4
5
6
MCT1
MX1+
MX1-
2
LAN_MDIN2
LAN_MDIP2
TCT1
TD1+
TD1-
3
1
2
3
2
RL8
+LAN_VDD_1V0
UL1
+V_DAC
LAN_MDIN3
LAN_MDIP3
1
CL14
8161@
2
31
2
10P_0402_50V8J
10P_0402_50V8J
13
14
2 0.1U_0402_10V7K PCIE_PRX_C_DTX_P3 17
2 0.1U_0402_10V7K PCIE_PRX_C_DTX_N3 18
RSET
TSL1
12
19
15
16
PCIE_PTX_C_DRX_P3
PCIE_PTX_C_DRX_N3
PCIE_PRX_DTX_P3
CR11 1
PCIE_PRX_DTX_N3
CR13 1
& lt; 10 & gt; PCIE_PTX_C_DRX_P3
& lt; 10 & gt; PCIE_PTX_C_DRX_N3
& lt; 10 & gt; PCIE_PRX_DTX_P3
& lt; 10 & gt; PCIE_PRX_DTX_N3
C
@ RL6 1 0_0201_5%
CLK_PCIE_LAN
CLK_PCIE_LAN#
& lt; 7 & gt; CLK_PCIE_LAN
& lt; 7 & gt; CLK_PCIE_LAN#
1
10P_0402_50V8J
CL20 close to UL1: Pin 11
CL13
Place CL11~CL13 close UL1 Pin 3, 8 , 22
@
CL10 & CL16 close to UL1: Pin 23
2
+LAN_VDD_3V3=40mil
8161@
UL1
1
2
4
5
6
7
9
10
1
CL8 & CL18 close LL2
8151/8166 Co‐Lay
LAN_MDIP0
LAN_MDIN0
LAN_MDIP1
LAN_MDIN1
LAN_MDIP2
LAN_MDIN2
LAN_MDIP3
LAN_MDIN3
CL12
OSC
@
2
GND
CL9 & CL5 close to UL1: Pin 11,32
2
1
@
CL11
3
2
@
2
1
CL5
2
1
@ CL29
0.1U_0402_16V7K
CL16
0.1U_0402_16V7K
2
1
CL10
CL9
1
4.7U_0603_6.3V6K
2
1
0.1U_0402_16V7K
1
0.1U_0402_16V7K
2
@
CL19
4.7U_0603_6.3V6K
1
4.7U_0603_6.3V6K
@8161@
CL20
1
@
LL2, CL8, CL23 for 8161
1
+VDDREG
+LAN_VDD_3V3
2
OSC
RL29 2
& lt; 9 & gt; LAN_PWR_EN
1
@
0.1U_0402_16V7K
CL21
0.1U_0402_16V7K
1
1U_0402_6.3V6K
APL3512_SOT23-5
2
1500P_0402_50V7K
1U_0402_6.3V6K
1
2
2.2UH +-5% NLC252018T-2R2J-N
+LAN_REGOUT
@ CL28
D
CL14 & CL15 close UL1 Pin22
CL26 & CL27 close UL1 Pin30
@ LL2
0.1U_0402_16V7K
EN
0.1U_0402_16V7K
SS
1
4
+LAN_VDD_1V0
2
2
0_0201_5% 1
SMT
2
0_0603_5%
2
GND
1 RL35
@
LL1 1
SMT
@
GND
OUT
+LAN_VDD_3V3
@
0.1U_0402_16V7K
IN
1
@
LL2
0.1U_0402_16V7K
5
@
SMT
4
@ UG5
SMT
CL21
RTL8151G (LDO mode)
+LAN_VDD_3V3 Rising time
need & gt; 0.5mS and & lt; 100mS
JUMP_43X79
+3VALW
Switcing mode
LL1
CL8
2
2
CL8
1
4.7U_0603_6.3V6K
CL23
@
1
1
2
4
JHW1 need to short
0.1U_0402_16V7K
5
1
JLAN1 CONN@
PR4GND
GND
PR4+
10
9
PR2PR3PR3+
LANGND
PR2+
PR1PR1+
SP050003P00
S X'FORM_ NS892404 ETHERNET 10/100
(SP050003P00) 10/100 8166@
(SP050006800) Giga
8161@
B
B
RR1
1
+3VS
2
+3VS_CR
0_0603_5%
short@
1
CR9
4.7U_0402_6.3V6M
+3VS_CR
RTS5239
CR10
2
Card Reader Connector
1
2 0.1U_0402_16V7K
RR4-RR9 close to chip
CR12-CR13 close to chip or socket
CONN@
JREAD1
SD_D3_R
1
+3VS_CR
SD_CD#
2
10K_0402_5%
1
6.2K_0402_1%
RR8
2 RR9
RREF
8
CLKREQ#
PERST#
MS_INS#
SD_CD#
GPIO
DV33_18
DV12_S
15
11
@EMI@
@EMI@
EMI@
@EMI@
@EMI@
@EMI@
1
1
1
1
1
1
2
2
2
2
2
2
RR2
RR4
RR5
RR3
RR6
RR7
0_0402_5%
0_0402_5%
33_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
1
CR14
+DVDD12
SD_D1_R 208MHz
SD_D0_R
@ CR12
1
2
SD_CLK_R
SD_CMD_R
SD_D3_R 6.8P_0402_50V8C
SD_D2_R
2
1U_0402_6.3V4Z
+CR_VDD_3V3
3V3_IN
AV12
CARD_3V3
RREF
9
7
10
2
3
Close to Conn
+CR_VDD_3V3
CR7
1
SP1
SP2
SP3
SP4
SP5
SP6
SP7
SD_D1
SD_D0
SD_CLK
SD_CMD
SD_D3
SD_D2
SD_WP
Close to Chip
4.7U_0603_6.3V6M
24
23
22
21
19
CR_CLKREQ#
PLT_RST#
& lt; 7,9 & gt; CR_CLKREQ#
HSIP
HSIN
REFCLKP
REFCLKN
HSOP
HSON
12
13
14
16
17
18
20
2
CLK_PCIE_CR
CLK_PCIE_CR#
2 0.1U_0402_16V7K PCIE_PRX_C_DTX_P2
CL17 1
2 0.1U_0402_16V7K PCIE_PRX_C_DTX_N2
CL18 1
1
2
3
4
5
6
CR8
1
2
4
SD_CLK_R
0.1U_0402_16V7K
& lt; 10 & gt; PCIE_PTX_C_DRX_P2
& lt; 10 & gt; PCIE_PTX_C_DRX_N2
& lt; 7 & gt; CLK_PCIE_CR
& lt; 7 & gt; CLK_PCIE_CR#
& lt; 10 & gt; PCIE_PRX_DTX_P2
& lt; 10 & gt; PCIE_PRX_DTX_N2
PCIE_PTX_C_DRX_P2
PCIE_PTX_C_DRX_N2
1
SD_CMD_R
UR1
Close to Chip
5
6
+CR_VDD_3V3
SD_D1_R
8
9
SD_CD#
RTS5239-GR_QFN24_4X4
10
SD_WP
GND
25
7
SD_D2_R
+3VS_CR
+AVDD12
SD_D0_R
11
RR9 close to chip
DAT3
CMD
VSS1
VDD
CLK
VSS2
DAT0
DAT1
DAT2
CD
G1
WP
G2
12
13
TAITW_PSDAT0-09GLBS1ZZ4H1
A
A
+DVDD12
1
2
2
CR3
CR4
1
2
CR5
4.7U_0402_6.3V6M
1
1
2
2
CR6
@
0.1U_0402_16V7K
2
Close to Chip
+3VS_CR
0.1U_0402_16V7K
0.1U_0402_16V7K
1
4.7U_0603_6.3V6M
CR2
+AVDD12
+AVDD12
0.1U_0402_16V7K
4.7U_0603_6.3V6M
CR1
1
+DVDD12
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/02/26
Deciphered Date
2015/07/08
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
LAN 8111G
Document Number
Rev
0.1
LA-A992P
Sheet
Thursday, March 20, 2014
1
23
of
54
RS1
1
1 CS1 USB3_TX0_C_P
@
0_0402_5%
2
D
USB3TXDP0_C_R
CMMI21T-900Y-N
4
4
3
3
1
2
USB3_TX0_N
0.1U_0402_16V7K
& lt; 10 & gt; USB3_TX0_N
RS3
1
& lt; 10 & gt; USB3_RX0_P
@
1 CS2 USB3_TX0_C_N
0_0402_5%
2
1
LM1
1
RS2
2
1
4
3
3
& lt; EC & gt;
EMI@
1
& lt; 10 & gt; USB3_RX0_N
1
LM2
1
RS6
RS7
1
& lt; 10 & gt; USB20_P0
2
USB_ON#
& lt; 30 & gt; USB_ON#
1
@
G547I2P81U_MSOP8
0_0402_5%
2
CS4
CS3
0.1U_0402_16V7K
2
@
1
2 RS4
0_0402_5%
RS5 1
0_0402_5%
2
1
2
@
2
USB_OC0#
1
USB_OC0# & lt; 10,9 & gt;
1
3
USB20_P0_C
USB20_P0_C
1
2
4
3
2
USB2.0/USB3.0 port 1
Part Number = SM070003Y00
3
WCM-2012-900T_4P
1
2
RS8
@ 0_0402_5%
& lt; 10 & gt; USB20_N0
1
CS5
YSLC05CH_SOT23-3
EMI@
4
1
@ESD@
DM1 SCA00000U10
2 USB20_N0_C
USB3RXDN0_C
LM3
2
8
7
6
5
2
SM070003K00
2
@ 0_0402_5%
@
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
USB3RXDP0_C
CMMI21T-900Y-N
4
1
2
3
4
USB3TXDN0_C_R
2
W=100mils
US1
W=100mils
2
SM070003K00
2
@ 0_0402_5%
+USB_VCCA
+5VALW
EMI@
1
E
USB3.0 need support 2.5A
change USB PWR SW SA00005VN00
low active
CS6
47U_0805_6.3V6M
2
USB3_TX0_P
0.1U_0402_16V7K
& lt; 10 & gt; USB3_TX0_P
C
0.1U_0402_16V7K
B
1000P_0402_50V7K
A
DM2
ESD@
1 1
USB3RXDN0_C
USB20_N0_C
SC300002800
JUSB1
109
USB3RXDN0_C
USB3TXDP0_C_R
USB3TXDN0_C_R
USB20_P0_C
USB3RXDP0_C
2 2
98
USB3RXDP0_C
USB3TXDN0_C_R
4 4
77
5 5
66
USB3TXDP0_C_R
9
1
8
3
7
2
6
4
5
USB3TXDN0_C_R
USB3TXDP0_C_R
& lt; PV & gt; LM3 change PN.
2
+USB_VCCA
USB20_N0_C
USB3RXDP0_C
3 3
USB3RXDN0_C
8
SSTX+
VBUS
SSTXD+
GND
DSSRX+
GND
SSRX-
10
11
12
13
GND
GND
GND
GND
ACON_TARA4-9K1311
CONN@
IP4292CZ10-TB
3
USB2.0 port x 2
@ RS13
1
& lt; 10 & gt; USB20_N2
0_0402_5%
2
& lt; PV & gt; LM4,LM5 change PN.
USB20_N2_C
3
LM4
1
+USB_VCCB
+5VALW
W=100mils
1
2
US2
1
2
3
4
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
4
W=100mils
8
7
6
5
1
2
EMI@
& lt; 10 & gt; USB20_P2
G547I2P81U_MSOP8
CS10
0.1U_0402_16V7K
4
3
@ RS15
1
& lt; 10 & gt; USB20_N1
0_0402_5%
2
1
2
4
3
EMI@
1
2
@ RS10
0_0402_5%
Part Number = SM070003Y00
3
4
RS9 1
0_0402_5%
@
2
USB_OC1#
USB_OC1# & lt; 10 & gt;
USB20_N1_C
USB20_P2_C
USB20_N2_C
USB20_P1_C
USB20_N1_C
2
Part Number = SM070003Y00
3
WCM-2012-900T_4P
1
2
@ RS16
0_0402_5%
& lt; 10 & gt; USB20_P1
12
11
10
9
8
7
6
5
4
3
2
1
USB20_P2_C
LM5
1
USB_ON#
+USB_VCCB
2
WCM-2012-900T_4P
1
2
@ RS14
0_0402_5%
E-T_6916K-Q12N-00L
12
11
10
9
8
7
6
5
4
3
2
1
G2
G1
14
13
JUSB2
USB20_P1_C
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/02/26
Deciphered Date
2015/07/08
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
USB 3.0/2.0 conn
Document Number
Rev
0.1
LA-A992P
Thursday, March 20, 2014
Sheet
E
24
of
54
4
3
2
UA1
23
24
16
D
PC_BEEP
+3VS
10
& lt; 6 & gt; HDA_SYNC_AUDIO
CA11
1
2 10U_0603_6.3V6M
ALDO_CAP
CA14
CA17
4.7U_0603_6.3V6K
1
2 2.2U_0402_6.3V6M
ACPVEE
CPVDD
CBN
CBP
CA15
1
2 2.2U_0402_6.3V6M
7
34
36
35
37
2
3
& lt; 19 & gt; D_MIC_DATA
& lt; 19 & gt; D_MIC_CLK
PLUG_IN#
RA10
1
2 39.2K_0402_1% SENSEA
13
14
1
SPK_L+
SPK_L-
HPOUT_R
HPOUT_L
33
32
SDATA_OUT
SDATA_IN
LDO3-CAP
BCLK
LINE1_L
LINE1_R
SPDIFO/GPIO2
GPIO0/DMIC_DATA
GPIO1/DMIC_CLK
JDREF
VREF
LDO1_CAP
LDO2_CAP
SENSE_A
SENSE_B
AVSS1
AVSS2
DVSS
Thermal Pad
5
8
1
1
HPOUT_R RA4
HPOUT_L RA5
2 75_0402_1%
2 75_0402_1%
HP_OUTR
HP_OUTL
+5VS
+1.5VS_AVDD
HDA_SDOUT_AUDIO
HDA_SDIN0 & lt; 6 & gt;
2 22_0402_5%
6
22
21
48
2
JDREF RA9
AVREF CA16 2
1
CA18
1
CA19
& lt; 6 & gt;
2
MIC_JD
15
28
27
39
& lt; 6 & gt;
1
600ohms @100MHz 1A
Main:SM010007Z00
2nd:SM01000BU00
2
1
Place near Pin26
1 20K_0402_1%
1 .1U_0402_16V7K
2 10U_0603_6.3V6M
2 10U_0603_6.3V6M
2 RA29
@
2
1
2
LA5
SUPPRE_ KC FBMA-10-100505-101T 0402
PCB Footprint = R_0402
2
1
GNDA
+5VS_PVDD
+5VS
1 100K_0402_5%
4
49
GNDA
AVREFCA24
1
Place near Pin40
GNDA
LA6
25
38
+1.5VS
1
2
FBMA-L11160808601LMA10T_2P
Headphone
HDA_BITCLK_AUDIO
1
SDATA_IN RA7
ALC3227-CG_MQFN48P_6X6
1
2
D
1
2 2.2U_0402_6.3V6M
1
2
1
2
2
1
1
2
FBMA-L11-201209601LMA20T_2P
2
MUTE_LED & lt; 26 & gt;
600ohms @100MHz 2A
Main:SM01000NS00
2nd:SM01000EE00
DA8
YSLC05CH_SOT23-3
SCA00002900
1
GNDA
10K_0402_5%
RA12
2
PD#
C
C
1
2
DA3
CH751H-40PT_SOD323-2
& lt; 30 & gt; EC_MUTE#
C
Internal SPK
& lt; DB & gt; Relace RA13/RA14/RA15/RA16 close to UA1
1
Part Number = SB000008E10
QA1
MMBT3904WH_SOT323-3
Power down (PD#) power stage for save power
0V: Power down power stage
3.3V: Power up power stage
10K_0402_5%
RA11
2
C
Q4B
2N7002KDW_SOT363-6
5
MUTE_LED_CTR
GNDA
2
2 2
E
1
2
1
Place near Pin9
+5VS_AVDD
RESET#
PDB
2
1
LA4
SYNC
CPVEE
CPVDD
CBN
CBP
1
Place near Pin1
Internal Speaker
PCBEEP
1K_0402_5%
RA26
B
B
3
HDA_RST_AUDIO#
42
43
2
CA23
10U_0603_6.3V6M
& lt; SI & gt; QA2 change from NMOS to BJT
& lt; PV & gt; QA2 change to QA1.
SPK_OUT_L+
SPK_OUT_L-
1
SPK_R+
SPK_R-
CA22
10U_0603_6.3V6M
RA25
2.2K_0402_5%
MONO_OUT
45
44
CA21
.1U_0402_16V7K
+DVDD
SPK_OUT_R+
SPK_OUT_R-
CA20
.1U_0402_16V7K
47
+1.5VS
LINE2_R
LINE2_L
RA2
0_0603_5%
+5VS_PVDD
CA13
4.7U_0603_6.3V6K
1
2
@
RA6
4.7K_0402_5%
PVDD1
PVDD2
+5VS_AVDD
+1.5VS_AVDD
41
46
CA12
.1U_0402_16V7K
1
+3VS
MIC1_VREFO_L
MIC1_VREFO_R
MIC2_VREFO
26
40
CA10
4.7U_0603_6.3V6K
CPVDD
11
AVDD1
AVDD2
CA9
.1U_0402_16V7K
HDA_RST_AUDIO#
& lt; 6 & gt; HDA_RST_AUDIO#
2
12
MIC2_R
MIC2_L
3
+MIC2_VREFO
31
30
29
4
MUTE_LED_CTR
18
17
+1.5VS
1
2
LA3
SUPPRE_ KC FBMA-10-100505-101T 0402
PCB Footprint = R_0402
1
2 4.7U_0402_6.3V6M INT_MICR_C
2 4.7U_0402_6.3V6M INT_MICL_C
+DVDD_IO
2
@
1
1
1
1
CA8
10U_0603_6.3V6M
CA1
CA4
+DVDD
+DVDD_IO
CA7
CA7
.1U_0402_16V7K
.1U_0402_16V7K
2 1K_0402_5%
+DVDD
1
9
CA6
10U_0603_6.3V6M
1
RA3
DVDD
DVDD_IO
CA5
.1U_0402_16V7K
INT_MIC
+3VS
MIC1_R
MIC1_L
3
20
19
1
2
5
& lt; PV & gt; RA13~RA16 change to SM010008A00, 30-ohm.
JSPK1
SPK_R- EMI@ RA13 1
SPK_R+ EMI@ RA14 1
SPK_L- EMI@ RA15 1
SPK_L+ EMI@ RA16 1
2
2
2
2
PBY160808T-300Y-N_2P
PBY160808T-300Y-N_2P
PBY160808T-300Y-N_2P
PBY160808T-300Y-N_2P
1
2
3
4
SPK_R-_CONN
SPK_R+_CONN
SPK_L-_CONN
SPK_L+_CONN
1
2
3 GND
4 GND
5
6
DA1 @ESD@
SCA00002900
L03ESDL5V0CC3-2_SOT23-3
@EMI@ C126
2
1
HP_OUTR_R
HP_OUTL_R
DA4
YSLC05CH_SOT23-3
SCA00002900
ESD@
DA6
YSLC05CH_SOT23-3
SCA00000U10
@ESD@
RA17
2.2K_0402_5%
1
1
CA32
10U_0603_6.3V6M
Close to Codec pin12
B
1
2
RA18
22K_0402_5%
MIC_JD
2
RA20
10K_0402_5%
+MIC2_VREFO
Jack detect
Combo Mic = High
Normal HP = Low
1
GNDA
2
1
2
PC_BEEP
CA34
.1U_0402_16V7K
3
1
2
CA33
.1U_0402_16V7K
2
& lt; 9 & gt; HDA_SPKR
2
Reserve for ESD request.
INT_MIC_R
RA19
47K_0402_5%
1
2
3
SB Beep
1
2 PC_BEEP_R
CA31
.1U_0402_16V7K
2
& lt; 30 & gt; EC_BEEP#
1
EC Beep
B
2
CONN@
1
DA2 @ESD@
SCA00002900
L03ESDL5V0CC3-2_SOT23-3
1
PC Beep
2
1
3
2
3
2
SPK_L+_CONN
1
@EMI@ C125
220P_0402_50V7K
SPK_L-_CONN
SPK_R+_CONN
1
@EMI@ C124
220P_0402_50V7K
SPK_R-_CONN
Delete ESD Diode
220P_0402_50V7K
wide 40 MIL
@EMI@ C123
220P_0402_50V7K
E-T_3703-Q04N-11R
INT_MIC
2
1
GNDA
COMBO AUDIO JACK
RA27 1 @
2 0_0402_5%
HPR, HPL, 15mil Keep 30mil
EMI@
RA21 1
INT_MIC
JHP1
2 BLM15AG601SN1D_2P
3
INT_MIC_R
6
2 0_0402_5%
EMI@
HP_OUTL
RA23 1
2 BLM15AG601SN1D_2P
HP_OUTL_R
1
2 BLM15AG601SN1D_2P
HP_OUTR_R
2
4
EMI@
1
2
CA29
EMI@
.1U_0402_16V7K
GNDA
Issued Date
2
1
SINGA_2SJ-E960-001F
2
GNDA
Pin6 and Pin5
Normal OPEN
Compal Electronics, Inc.
Compal Secret Data
2013/01/04
Deciphered Date
2015/01/04
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
GNDA
Date:
5
4
3
A
CONN@
GNDA GNDA GNDA
Security Classification
1
2
CA30
EMI@
.1U_0402_16V7K
2
@EMI@
2
Delete ESD Diode
@EMI@
1
1
2
CA39
@EMI@
.1U_0402_16V7K
5
1
CA37
10P_0402_50V8J
RA24
22K_0402_5%
PLUG_IN#
CA36
10P_0402_50V8J
1
2
CA38
@EMI@
.1U_0402_16V7K
& lt; PV & gt; RA21~23 change to
Main : SM01000II00
1
2nd : SM01000I000
CA35
100P_0402_50V8J
A
RA22 1
HP_OUTR
1
2
CA40
@EMI@
.1U_0402_16V7K
@EMI@
RA28 1 @
2
AUDIO ALC3227-CG
Document Number
Rev
0.1
LA-A992P
Sheet
Thursday, March 20, 2014
1
25
of
54
& lt; 30 & gt; KSI[0..7]
Touch pad conn
& lt; 30 & gt; KSO[0..17]
KSI0
C193
Keyboard conn
KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0
KSO17
KSO16
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0
ESD@
2
1 100P_0402_50V8J
CAP_LOCK# R203 1
MUTE_LED R207 1
WL_WHIT
WL_AMBER
& lt; 30 & gt; CAP_LOCK#
& lt; 25 & gt; MUTE_LED
CONN@ JKB1
1
2 1
3 2
4 3
5 4
6 5
7 6
8 7
9 8
10 9
11 10
12 11
13 12
14 13
15 14
16 15
17 16
18 17
19 18
20 19
21 20
22 21
23 22
24 23
25 24
26 25
27 26
28 27
29 28
30 29
31 30
G1
32 31
32
G2
KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
KSO16
KSO17
+5VS
2 3.3K_0402_5%
2 3.3K_0402_5%
+5VS
33
34
ACES_50690-0320N-P01
+5VALW
+5VALW
+3VALW
JTP1
1
2
3
4
TP_CLK
TP_DATA
1
2
3
4
1
G1
G2
5
6
2
@EMI@
C134
470P_0402_50V8J
CAP_LOCK#
MUTE_LED
1
Amber
3
Issued Date
2013/02/26
2
CC123
100P_0402_50V8J
ESD@
3
WL_WHIT
5
WLAN_ON_LED# & lt; 30 & gt;
Compal Electronics, Inc.
Compal Secret Data
Security Classification
1
CC122
100P_0402_50V8J
2
ESD@
4
1
2
Q20B
Q20B
Q20A
Q20A
& lt; 30 & gt; WLAN_OFF_LED#
2N7002KDW_SOT363-6
6
WL_AMBER
1
White
R158
3.3K_0402_5%
2
R157
3.3K_0402_5%
2N7002KDW_SOT363-6
DM5
YSLC05CH_SOT23-3
SCA00000U10
@ESD@
2
2
1
HB_A090420-SAHR21
CONN@
1
& lt; 30 & gt; TP_CLK
& lt; 30 & gt; TP_DATA
Deciphered Date
2015/07/08
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
KB/TP
Document Number
Rev
0.1
LA-A992P
Thursday, March 20, 2014
Sheet
26
of
54
A
B
C
D
E
Powert Button Connector
+3VL
1
LED10
JPWR1
LID_SW#
ON/OFF#
1
2
3
4
1
2
3
4
G1
G2
5
6
220_0402_5%
2
PWR_LED#
& lt; 30 & gt; PWR_LED#
CC124
100P_0402_50V8J
2
ESD@
@ESD@
remove at SI phase
2
0.1U_0402_16V7K
2
White
LED9
R215
ON/OFF# 2
1
LTW-110DC5-C_WHITE
1
CS20
+3VL
HB_A090420-SAHR21
CONN@
R2744
1
+3VALW
3
1
2
& lt; 30 & gt; LID_SW#
& lt; 30 & gt; ON/OFF#
1
White
LID_SW#
1
& lt; 6,9 & gt; SATA_LED#
220_0402_5%
2
SATA_LED#
100K_0402_5%
remove at SI phase
R2743
1
@ESD@ 1
CS19
0.1U_0402_16V7K
1
+3VS
2
LTW-110DC5-C_WHITE
3
remove at SI phase
@EMI@ 1
C166
0.1U_0402_16V7K
2
2
2
& lt; SI & gt; Del New Lid SW conn
3
3
+FAN_POWER
FAN conn
1
+3VS
+FAN_POWER
1
CE22
RE50
10K_0402_5%
+5VS
2
1
CE25
2.2U_0603_6.3V6K
2
CONN@
40mil
1
2
2.2U_0603_6.3V6K
40mil
2
3
& lt; 30 & gt; FAN_SPEED1
UE3
1
2
3
4
& lt; 30 & gt; EN_DFAN1
VEN
VIN
VO
VSET
GND
GND
GND
GND
8
7
6
5
4
5
1
2
CE24
0.01U_0402_16V7K
JFAN1
1
2
3
GND
GND
ACES_85204-0300N
APE8873M SOP 8P
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/02/26
Deciphered Date
2015/07/08
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
PWRBTN/FAN
Document Number
Rev
0.1
LA-A992P
Thursday, March 20, 2014
Sheet
E
27
of
54
5
4
ACCELEROMETER
+3VS
+3VL
TPM1.2
1
2
@
+3V_GSEN
+3V_GSEN
0_0402_5%
1
@ RH503
0_0402_5%
1
5
24
19
10
1
XTALO
XTALI
+3VS
1
R1383
LPC_FRAME#
PLT_RST#
SERIRQ
@
2
TPM
SLB 9656 TT 1.2
LCLK
LFRAME#
GPIO2
LRESET#
GPIO
SERIRQ
CLKRUN#
PP
NC
NC
NC
1
GND
GND
GND
GND
4.7K_0402_5%
21
22
16
27
15
7
BADD
1
EC_SMB_CK1
EC_SMB_DA1
& lt; 30,45,46 & gt; EC_SMB_CK1
& lt; 30,45,46 & gt; EC_SMB_DA1
2 PLT_RST#
@ R1413 0_0402_5%
+3V_GSEN
14
13
2 @ R208 1
10K_0402_5%
2
3
@ R227
0_0402_5%
@
2
6
T48 PAD
T47 PAD
@
4
6
7
8
2
Vdd_IO
INT2
INT1
VDD
ACCEL_INT# & lt; 9 & gt;
SCL/SPC
SDA/SDI/SDO
SDO/SA0
CS
GND
GND
RES
RES
RES
RES
NC
NC
+3V_GSEN
9
11
14
D
5
12
10
13
15
16
C231
0.1U_0402_16V7K
HP3DC2TR
1
1
2
2
1
3
12
C232
10U_0603_6.3V6M
@
@
@
R209
0_0402_5%
SLB 9656 TT 1.2
2
@
R1414
0_0402_5%
4
11
18
25
& lt; 7 & gt; CLK_PCI_TPM
& lt; 30,7 & gt; LPC_FRAME#
& lt; 21,23,30,32,8 & gt; PLT_RST#
& lt; 30,9 & gt; SERIRQ
28
9
8
1
LPCPD#
TESTB1/BADD
TEST1
DH8
CH751H-40PT_SOD323-2
@
U25
1
LAD0
LAD1
LAD2
LAD3
@
1
ACCEL_INT#_R
+3V_GSEN
2
VDD
VDD
VDD
26
23
20
17
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
& lt; 30,7 & gt; LPC_AD0
& lt; 30,7 & gt; LPC_AD1
& lt; 30,7 & gt; LPC_AD2
& lt; 30,7 & gt; LPC_AD3
SI# 2012.04.10 Change ACCEL_INT# to INT1
@
C1061
*
0.1U_0402_16V4Z
2
2
0.1U_0402_16V4Z
2
@
U70
2
VSB
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
1@
1@
C1059
C1058
1@
C1060
D
RH411
2
1
+3VS
3
Screw Hole
H6
H_2P8
HOLEA
HOLEA
C
@
H15
H_5P0
H16
H_5P0
HOLEA
HOLEA
HOLEA
@
@
@
@
@
FD3
FD4
@
@
@
FIDUCIAL_C40M80
FD1
@
FIDUCIAL_C40M80
@
FIDUCIAL_C40M80
1
@
1
@
1
@
1
@
1
@
1
1
FIDUCIAL_C40M80
@
FD2
1
HOLEA
H13
H_5P0
HOLEA
1
HOLEA
H11
H_5P0
HOLEA
1
HOLEA
H10
H_5P0
HOLEA
H19
H_2P0X2P5
1
HOLEA
H18
H_2P0
1
HOLEA
H17
H_2P8
1
HOLEA
H12
H_2P8
1
H9
H_5P0
H2
H_2P8
1
HOLEA
@
1
H1
H_2P8
1
@
@
H14
H_2P8
1
@
H7
H_2P8
1
HOLEA
1
@
H5
H_2P8
HOLEA
1
C
H4
H_2P8
HOLEA
1
H3
H_2P8
Compal Secret Data
Security Classification
Issued Date
2013/02/26
2015/07/08
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Compal Electronics, Inc.
LED/Screw hole
Document Number
Rev
0.1
LA-A992P
Thursday, March 20, 2014
Sheet
28
of
54
B
B
A
A
5
4
3
2
1
5
4
3
2
2
1
2
1
2
1
Note: Depend on
Project, if Vp-p small
the 50mV change to 0
ohm
2
1
2
@
+DAC_1.8V
L4108
BLM15PD600SN1D_2P
1
2
CRT@
Rated current 500mA, DC 0.1ohm
1
Note: Depend on
Project, if Vp-p small
the 50mV change to 0
ohm
2
1
2
1
2
C4136 CRT@
0.1U_0402_16V4Z
1
CRT@ C4112
0.1U_0402_16V4Z
1
CRT@ C4104
0.1U_0402_16V4Z
2
2
CRT@
CRT@ C4103
0.1U_0402_16V4Z
2
1
1
CRT@ C4115
1U_0402_6.3V6K
2
1
CRT@ C4111
10U_0603_6.3V6M
1
CRT@ C4110
0.1U_0402_16V4Z
2
CRT@ C4101
0.1U_0402_16V4Z
1
1
+IVDDO_1.8V
C4109 CRT@
0.1U_0402_16V4Z
+IVDDO_1.8V
L4106
BLM15PD600SN1D_2P
1 0_0603_5%
short@
CRT@ C4108
1U_0402_6.3V6K
R4110 2
+RXIVDD_1.8V
L4107
BLM15PD600SN1D_2P
1
2
CRT@
Rated current 500mA, DC 0.1ohm
+RXVCC_1.8V
C4107 CRT@
1U_0402_6.3V6K
+IVDDO_1.8V
If Vp-p small than 50mV
change L4106 to 0 ohm
+3VS_OVDD
C4106 CRT@
0.1U_0402_16V4Z
+3VS
2
Use 0 ohm for material shortage
C4105
4.7U_0603_6.3V6K
Use 0 ohm for material shortage
Note: Place close pin 24
Note: Place close pin 10
+3VS_IVDD33
D
1 100K_0402_5%
1 1M_0402_5%
@
CRT@
+RXIVDD_1.8V
MCUVDDH
45
38
39
35
36
1
2
RX1P
RX1N
MCURSTN
ISPSCL
ISPSDA
RXAUXP
RXAUXN
VGADDCCLK
VGADDCSDA
DCAUXP
DCAUXN
C4125 CRT@
0.1U_0402_16V4Z
C4114 CRT@
0.1U_0402_16V4Z
C4116 @
2 0.1U_0402_16V4Z
1
VSYNC
HSYNC
MCURSTN
DT3
+HDMI_5V_OUT
@
28
@
15
16
ISPSCL_R
ISPSDA_R
3
4
T4102
T4101
1
2
3
4
23
21
VSYNC
HSYNC
RP4102
CRT@
8
7
6
5
56.95mA
41.6mA
65.5mA VDDC
IOGP
CRT_CLK
CRT_DATA
CRT_R
L4103
PBY160808T-600Y-N
1
2 CRTEMI@
L4104
PBY160808T-600Y-N
1
2 CRTEMI@
L4105
PBY160808T-600Y-N
1
2 CRTEMI@
1
1
CRT_R
9
CRT_G
CRT_G
8
CRT_B
CRT_B
49
37
7
6
34
33
CRT@
T4104
2
100_0402_1%
+DAC_1.8V
1
CRT@
2 C4133
0.1U_0402_16V4Z
XTALIN_6513
XTALOUT_6513
1
2
CRT@
RP4100
75_0804_8P4R_1%
Pin41_VGADETECT is not use in IT6513.
2
1
CRTEMI@
1
R4118
PAD
PWDNB
5
@
8
7
6
5
1
COMP
XTALIN
XTALOUT
VGADETECT
CRTEMI@
VDDA
41
1
2
SM010005N00
2
2
T4103
@
CRT_R_2
CRT_DATA
CRT_G_2
CRT_HSYNC_2
CRT_B_2
1
2
1
2
+HDMI_5V_OUT
CRT_VSYNC_2
+HDMI_5V_OUT
W=40mils
1
@
2
& lt; MV & gt; EMI fine tune Pi-filiter to 60-ohm and 6.8pf .
CRT_CLK
0.1U_0402_16V4Z
C4132
2
CRT_B_2
C
C4131
6.8P_0402_50V8C
1
1
CRT Connector
C4130
6.8P_0402_50V8C
2
11
C4129
6.8P_0402_50V8C
6.8P_0402_50V8C
RSET
6.158mA
PCSDA
PCSCL
+HDMI_5V_OUT
I/O1
JCRT1
C4128
6.8P_0402_50V8C
43
42
GND
I/O3
CRB1.0 use 33ohm@100Mhz Bead
C4127
6.8P_0402_50V8C
ASPVCC
PCSDA
PCSDA
PCSCL
CRT_G_2
RGB Trace must less than 2000mils.
C4126
6.8P_0402_50V8C
NC/VGADETECT
Note: need external PU to 2K ~ 10K
3
2
AZC099-04S.R7G_SOT23-6
CRT_CLK
CRT_DATA
47.3mA
0.293mA
PCSCL
I/O2
VDD
4
1
2
3
4
DVDD18
IOBP
32
@ESD@
SC300001G00
I/O4
5
10
IT6513FN
+HDMI_5V_OUT
CRT@
CRT@
R4123
R4126
4.7K_0402_5% 4.7K_0402_5%
CRT_CLK
R_out & B_out can be swapped.
IORP
24
1
22_0804_8P4R_5%
C4137 CRT@
0.1U_0402_16V4Z
PVCC
CRT_VSYNC_2
Note: ISPSCL/ISPSDA for F/W update
C
22
6
CRT_R_2
+DAC_1.8V
AVCC
AVCC
I/O1
3
2
+HDMI_5V_OUT
47
+RXVCC_1.8V
25
31
I/O3
12
14
44
46
IVDD
IVDD
IVDD
IVDD
IVDDO
IVDDO
100.5mA
CRTEMI@
R4113 2
R4114 2
+3VS
4.2mA
CRTEMI@
2
2
& lt; 8 & gt; DDI1_AUX_DP
& lt; 8 & gt; DDI1_AUX_DN
C4121 CRT@
0.1U_0402_16V7K
1
DDI1_AUX_C_DP 20
1
DDI1_AUX_C_DN 19
C4122 CRT@
0.1U_0402_16V7K
18
DDI1_AUX_DP
17
DDI1_AUX_DN
GND
AZC099-04S.R7G_SOT23-6
RX0P
RX0N
URDBG
1 1M_0402_5%
1 100K_0402_5%
I/O2
VDD
4
CRT_DATA
+HDMI_5V_OUT
1.52mA
CRTEMI@
R4108 2 CRT@
R4104 2
@
+3VS
(2-Lane only)
HPD
@ESD@
SC300001G00
I/O4
5
Note: Place close pin 12,14,44,46
CRTEMI@
CPU DDI1
+IVDDO_1.8V
1
& lt; 4 & gt; PCH_DPC_P1
& lt; 4 & gt; PCH_DPC_N1
29
30
DT4
6
CRT_HSYNC_2
+HDMI_5V_OUT
1
26
27
1 0.1U_0402_16V7K PCH_DPC_C_P1
1 0.1U_0402_16V7K PCH_DPC_C_N1
2
+RXIVDD_1.8V
2
1 0.1U_0402_16V7K PCH_DPC_C_P0
1 0.1U_0402_16V7K PCH_DPC_C_N0
2
2
1
2
2
2
CRT@ C4120
CRT@ C4124
2
CRT@
CRT@
2.2K_0402_5%
R4125
CRT@ C4123
CRT@ C4119
+3VS_OVDD
1
CRT@
CRT@
2.2K_0402_5%
R4124
& lt; 4 & gt; PCH_DPC_P0
& lt; 4 & gt; PCH_DPC_N0
DDCSCL
DDCSDA
40
2
Pin38,39 LDO output +IVDDO_1.8V.
UT5
VGA_HPD
22_0402_5%
R4101
R4102
4.7K_0402_5%
@
1
2
1
2
@
R4103
4.7K_0402_5%
R4100
22_0402_5%
+3VS
1
+3VS_IVDD33
CRT@
C4113 CRT@
0.1U_0402_16V4Z
ISPSCL_R
ISPSDA_R
CRT@
IVDD33
IVDD33
2
13
48
1
OVDD
OVDD
short@
1
1
1 0_0603_5%
CRT@ C4100
10U_0603_6.3V6M
R4109 2
Note: Place close pin 38,39
Note: Place close pin 22,15,31,32
LDO input
2
2
D
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
G
G
16
17
C-H_13-12201560CP
CONN@
DC060006E00
IT6513FN_QFN48_6X6
CRT@
CRT@
R4120 1
2 0_0402_5%
1
R4121
+5VS
+HDMI_5V_OUT
2
10K_0402_5%
CRT@
RT26
CRT@
1
2 CRT@
CT27 0.1U_0402_16V4Z
2
VGA_HPD
A
Y
UT2 CRT@
74AHCT1G125GW_SOT353-5
4
2
33_0402_5%
@
CT26
10P_0402_50V8J
CRT_HSYNC_1
CRT_HSYNC_2
1
2
CRT_VSYNC_2
1
B
@
CT28
2 10P_0402_50V8J
3
R4122
4.7K_0402_5%
CRT@
2
33_0402_5%
1 CRT@
LT15
G
1
D
+HDMI_5V_OUT
P
VSYNC
2
A
G
R4127
1M_0402_5%
@
XTALIN_6513
3
XTALOUT_6513
OE#
2 0.1U_0402_16V4Z
CRT@
5
CT25 1
1
2
Q4100
L2N7002LT1G_SOT23-3
@
2
HSYNC
OE#
1
P
3
& lt; 8 & gt; DDI1_HPD
S
B
1 CRT@
LT14
1
10K_0402_5%
1
5
G
2
& lt; PV & gt; Add R4121 by vender recommand.
Y
4
CRT_VSYNC_1
UT4 CRT@
74AHCT1G125GW_SOT353-5
X4100 @
27MHZ_10PF_X3G027000BA1H-U
Crystal
3
4
OUT
GND
GND
IN
1
1
@
C4135
2
18P_0402_50V8J
2
18P_0402_50V8J
2
1
@
C4134
A
A
Compal Secret Data
Security Classification
2011/06/30
Issued Date
Deciphered Date
2013/06/30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Compal Electronics, Inc.
eDP to CRT
Size Document Number
Custom
Rev
0.1
LA-A992P
Date:
Thursday, March 20, 2014
1
Sheet
29
of
54
4
3
2
+3VALW_EC
PV# 2013.01.29 Add CK4 for ESD protection
1
2
2
RK6
100K_0402_5%
CK7
0.1U_0402_16V7K
BOARD_ID
D
2
CK4
2
1
& lt; 8 & gt; PM_CLKRUN#
& lt; 21 & gt; EC_PCIE_WAKE#
+3VALW_EC
& lt; 26 & gt; KSI[0..7]
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
EC_SMB_CK2_R
EC_SMB_DA2_R
77
78
79
80
+3VS
RP7
1
2
3
4
8
7
6
5
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
& lt; 26 & gt; KSO[0..17]
2.2K_0804_8P4R_5%
@
+3VS
RK36
1
12
13
37
20
38
2 10K_0402_5% EC_SCI#
& lt; 28,45,46 & gt;
& lt; 28,45,46 & gt;
& lt; 18,32,7 & gt;
& lt; 18,32,7 & gt;
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
RK39 1 short@
RK40 1
short@
& lt; 8 & gt; PM_SLP_S3#
& lt; 8 & gt; PM_SLP_S5#
& lt; 8 & gt; SUSACK#
& lt; 21 & gt; MINI1_LED#
& lt; 8 & gt; PCH_SUSWARN#
B
2 0_0402_5%
2 0_0402_5%
PM_SLP_S3#
PM_SLP_S5#
SUSACK#
PCH_SUSWARN#
& lt; 6 & gt; EC_+1.05VS_PG
& lt; 19 & gt; EC_INVT_PWM
& lt; 27 & gt; FAN_SPEED1
& lt; 8 & gt; PM_SLP_SUS#
& lt; 21 & gt; E51TXD_P80DATA
& lt; 21 & gt; E51RXD_P80CLK
& lt; 8 & gt; PCH_PWROK
& lt; 44 & gt; AC_LED#
FAN_SPEED1
PM_SLP_SUS#
E51TXD_P80DATA
E51RXD_P80CLK
PCH_PWROK
AC_LED#
122
123
GPU_THERMAL_DET#
& lt; 32 & gt; GPU_THERMAL_DET#
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
AD
EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
SM
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A
XCLKI/GPIO5D
XCLKO/GPIO5E
KB9012QF-A3_LQFP128_14X14
Part Number = SA00004OB30
PV
MV
27K ohm
43K ohm
130k ohm 200k ohm 270k ohm 430k ohm
& lt; DB & gt; RK13 change to 12K === & gt; for 15 " UMA
D
CH751H-40PT_SOD323-2
1
2
EC_ACIN
EC_VDD/AVCC
2
CK8
GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13
21
23
26
27
GPU_HOT# & lt; 53 & gt;
EC_BEEP# & lt; 25 & gt;
TS_GPIO_EC & lt; 19 & gt;
AC_AND_CHAG & lt; 45 & gt;
ACIN & lt; 44,45,46,8 & gt;
63
64
65
66
75
76
B/I#
BOARD_ID
ADP_I
68
70
71
72
+1.05V_VS_PG_PWR
1 100P_0402_50V8J
VR_HOT#
& lt; 50 & gt; VR_HOT#
BATT_TEMP/AD0/GPIO38
AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
IMON/AD5/GPIO43
short@ RK17
0_0402_5%
1
2
PROCHOT# & lt; 4,44 & gt;
B/I# & lt; 44,45 & gt;
ADP_I & lt; 44,46 & gt;
ADP_ID
ENBKL
ADP_ID & lt; 44 & gt;
ENBKL & lt; 8 & gt;
short@ RK53 1
DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F
DA Output
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
SI
15K ohm
DK1
PWM Output
CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D
UMA
RK13
DIS
RK13
H_PROCHOT#_EC 2
G
QK1
2N7002_SOT23-3
& lt; 44 & gt; H_PROCHOT#_EC
3
CLK_PCI_LPC
PLT_RST#
EC_RST#
EC_SCI#
& lt; 9 & gt; EC_SCI#
1
2
@
PM_CLKRUN#_R
2 0_0402_5%
RK59 1
RK61
short@
0_0402_5%
GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC & MISC
LPC_AD0
DB
0 ohm
14 "
160k ohm 240k ohm 330k ohm 560k ohm
56K_0402_1%
SD034560280
EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F
PS2 Interface
CPU1.5V_S3_GATE/GPXIOA00
WOL_EN/GPXIOA01
ME_EN/GPXIOA02
VCIN0_PH/GPXIOD00
83
84
85
86
87
88
97
98
99
109
SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A
SPI Flash ROM
2 0_0201_5%
+1.05V_VS_PG_PWR & lt; 49 & gt;
D
S
& lt; PWR & gt;
EN_DFAN1 & lt; 27 & gt;
DGPU_HOLD_RST# & lt; 32,9 & gt;
SYS_PWROK & lt; 8 & gt;
EC_MUTE# & lt; 25 & gt;
PM_SLP_S4# & lt; 8 & gt;
WLAN_OFF_LED#
PM_SLP_S4#
WLAN_OFF_LED#
TP_CLK
TP_DATA
+3VALW_EC
C
& lt; 26 & gt;
TP_CLK & lt; 26 & gt;
TP_DATA & lt; 26 & gt;
EC_PME#
EC_FB_CLAMP_TGL_REQ#
EC_PME# & lt; 23,9 & gt;
WL_PWREN_EC & lt; 21 & gt;
HDA_SDO & lt; 6 & gt;
VCIN0_PH & lt; 44 & gt;
HDA_SDO
VCIN0_PH
SPI Device Interface
119
120
126
128
EC_SPI_SO & lt; 7 & gt;
EC_SPI_SI & lt; 7 & gt;
EC_SPI_CLK & lt; 7 & gt;
EC_SPI_CS0# & lt; 7 & gt;
RK60
1 @DIS@ 2 10K_0402_5%
& lt; PV & gt; N15V don,t support GC6,RK60 change to @DIS@.
& lt; SI & gt; Update Pin119 and Pin120 net name
+3VALW
GPIO
Bus
GPIO
EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11
GPI
AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07
V18R
73
74
89
90
91
92
93
95
121
127
TOUCH_ON#
EC_FB_CLAMP_TGL_REQ#
AOAC_PME#
100
101
102
103
104
105
106
107
108
PCH_RSMRST#
110
112
114
115
116
117
118
EC_ACIN
EC_ON
ON/OFF#
LID_SW#
SUSP#
NMI_DBG#
EC_PECI RK34 1
124
TP_CLK
RK2
1
2
4.7K_0402_5%
TP_DATA
ENBKL/AD6/GPIO40
PECI_KB930/AD7/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
BATT_LOW_LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59
AGND/AGND
1
2
3
4
5
7
8
10
EC_KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
RK4
1
2
4.7K_0402_5%
+V18R
TOUCH_ON# & lt; 19 & gt;
EC_FB_CLAMP_TGL_REQ# & lt; 9 & gt;
AOAC_PME# & lt; 8 & gt;
BAT_CHG_LED & lt; 44 & gt;
CAP_LOCK# & lt; 26 & gt;
PWR_LED# & lt; 27 & gt;
WLAN_ON_LED# & lt; 26 & gt;
SYSON & lt; 40,48 & gt;
BT_ON_EC & lt; 21 & gt;
PCH_DPWROK & lt; 8 & gt;
CAP_LOCK#
PWR_LED#
SYSON
BT_ON_EC
PCH_DPWROK
PCH_RSMRST# & lt; 8 & gt;
CK10 2
VCIN1_PH
H_PROCHOT#_EC
MAINPWON
EC_BKOFF#
PBTN_OUT#
PCH_PWR_EN
USB_ON#
1
+3VL
RP8
PCH_PWR_EN 8
7
PLT_RST#
6
EC_ON
5
EC_ACIN
1 100P_0402_50V8J ECAGND
EC_LID_OUT# & lt; 9 & gt;
VCIN1_PH & lt; 44 & gt;
MAINPWON & lt; 47 & gt;
EC_BKOFF# & lt; 18 & gt;
PBTN_OUT# & lt; 8 & gt;
PCH_PWR_EN & lt; 42 & gt;
USB_ON# & lt; 24 & gt;
1
2
3
4
B
100K_0804_8P4R_5%
EC_ON & lt; 47 & gt;
ON/OFF# & lt; 27 & gt;
LID_SW# & lt; 27 & gt;
SUSP# & lt; 40,48,49,52,55 & gt;
2
43_0402_1%
H_PECI & lt; 4 & gt;
+3VALW_EC
CK17
LID_SW#
2
69
& lt; 35,53,9 & gt; DGPU_PWR_EN
& lt; 7,9 & gt; EC_KBRST#
& lt; 28,9 & gt; SERIRQ
& lt; 28,7 & gt; LPC_FRAME#
& lt; 28,7 & gt; LPC_AD3
& lt; 28,7 & gt; LPC_AD2
& lt; 28,7 & gt; LPC_AD1
& lt; 28,7 & gt; LPC_AD0
& lt; 7 & gt; CLK_PCI_LPC
& lt; 21,23,28,32,8 & gt; PLT_RST#
C
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC
EC_RST#
0.1U_0402_16V7K
GND/GND
GND/GND
GND/GND
GND/GND
GND0
1 330K_0402_5%
2
11
24
35
94
113
1
CK9
MV
56K ohm
UMA@
RK13
67
9
22
33
96
111
125
0.1U_0402_16V7K
RK15 2
DIS@
RK13
560K_0402_1%
SD034560380
+3VL
1
0_0402_5%
+3VALW_EC
PV
33K ohm
& lt; DB & gt; RK13 change to 160K == & gt; for 15 " DIS
2
RK12 short@
1
PLT_RST#
UK1
SI
12k ohm 20K ohm
Board ID control
+3V_EC_VDD
ESD@
UMA
RK13
DIS
RK13
2
1
DB
15 "
+3VALW_EC
LK1
FBMA-L11-160808-800LMT_0603
1
2 +EC_VCCA
+3VALW_EC
ECAGND
2
CK3
CK3
0.1U_0402_16V7K
0.1U_0402_16V7K
1
0_0603_5%
CK2
0.1U_0402_16V7K
short@ RK57
1
2
1
1
+3VL
1
5
RK44
2
1
47K_0402_5%
4.7U_0603_6.3V6K
20mil
LK2
1
ECAGND 2
FBMA-L11-160808-800LMT_0603
+3VALW_EC
100K_0402_5%
2 PCH_DPWROK
100K_0402_5%
2 PCH_PWROK
ECAGND & lt; 44 & gt;
1
@ RK49
1
@ RK50
1
A
A
2
RK18
10K_0402_5%
NMI_DBG#
1
2
NMI_DBG#_CPU & lt; 9 & gt;
Compal Secret Data
Security Classification
DK2
CH751H-40PT_SOD323-2
Issued Date
2011/06/29
Deciphered Date
2011/06/29
Title
Compal Electronics, Inc.
EC ENE-KB9012
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
0.1
LA-A992P
Date:
5
4
3
2
Thursday, March 20, 2014
Sheet
1
30
of
54
5
4
3
2
1
BOM control
Platform
Silego P/N
Compal PN
Intel ULT UMA
SLG3NB3375V
SA00006RE00
1
1
1
X
X
GCLKUMA@
Intel ULT Dis
D
25MHz(A)
32.768KHz 24MHz(B)
27MHz
8MHz Remark
SLG3NB3374V
SA00006RD00
1
1
1
1
X
GCLKDIS@
D
Base on A32 32.768KHz use 10ppm, G‐CLK 25MHz X'TAL use 10ppm.
+RTCBATT
1
+RTCVCC
+1.05VS
+LAN_VDD_3V3 +3VL
+3VALW
1
RG107 @
0_0402_5%
2
+3VGS
RG106 GCLK@
330_0402_5%
GCLK@
2
1
CG51
CG52
22U_0805_6.3V6M
2
GCLK@
1
1
2
GCLKDIS@
UG2
GCLK_VRTC
Place close
to UG2.8
10
15
+3VL
2
+3VALW
VBAT
2
VDD_RTC_OUT
S CRYSTAL 25MHZ 12PF +-10PPM FL2500048
SJ10000G600
1
16
CPU 32.768M(P.6)
Place RG114 close to YC1
VDDIO_25M_A
25MHz_A
VDDIO_25M_B
25MHz_B
1
RG114
2
0_0402_5%
GCLKDIS@
1
2 33_0402_5%
12
VGA_X1_R
6
LAN_X1_R
RG1111
5
PCH_X1_R
RG1131
RG109
XTAL_IN
XTAL_OUT
S IC SLG3NB3374VTR TQFN 16P CRYSTAL
SA00006RD00
2 33_0402_5%
& lt; SI & gt; Change RG109 to 33 ohm recommend by vender
2 0_0402_5%
GCLK@
CG54
5P_0402_50V8C
GCLK@
VGA 27M(P.32)
Place RG110 close to YV1
PCH_RTCX1 & lt; 6 & gt;
XTALIN_R
XTLI_R
GCLK@
1
CLK_X1
CLK_X2
27MHz
GND4
3
VDDIO_27M
GND1
GND2
GND3
8
PCH_RTCX1_R
C
GCLK@
CPU_XTAL24_IN & lt; 7 & gt;
1
1
GCLK@
IN
CG59
18P_0402_50V8J
OUT
GND
2
& lt; GPU & gt;
XTLO & lt; 23 & gt;
& lt; LAN & gt;
CPU_CLK 24M(P.7)
Place RG113 close to YC2
& lt; CPU & gt;
RG3, RG7,RG8, RG6 0ohm_0402
for isolated CLK tail
CLK_X2
2
1
GCLK@
CG58
18P_0402_50V8J
VGA_X1_R
UG2
GCLKUMA@
SA00006RE00
S IC SLG3NB3375VTR TQFN 16P CRYSTAL
CLK_X1
2
B
1
2
GND
3
XTALIN & lt; 32 & gt;
LAN 25M(P.23)
Place RG112 close to YL1
YG1 GCLK@
4
& lt; CPU RTC & gt;
GCLKDIS@
1
2
RG110
0_0402_5%
1
2
RG112 GCLK@
0_0402_5%
17
+LAN_VDD_3V3
+1.05VS
Check Power Rail
9
@
VDD
4
7
13
11
RTC_VOUT
+V3.3A
32kHz
+3VGS
14
2
CG50
2
0.1U_0402_10V7K
CG49
2
GCLK@
1
0.1U_0402_10V7K
CG48
2
1 GCLK@
0.1U_0402_10V7K
CG47
2
0.1U_0402_10V7K
Depop if GCLK
with UMA
1 GCLK@
1
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
CG53
CG53
C
0.1U_0402_10V7K
GCLKDIS@
& lt; SI & gt; Change CG58, CG59 to 18pf recommend by vender
CG57
5P_0402_50V8C
@
B
Reserve CG57 for vendor
Place close to RG109
A
A
Compal Secret Data
Security Classification
Issued Date
2013/06/10
Deciphered Date
2014/07/01
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Compal Electronics, Inc.
GCLK
Document Number
Rev
0.1
LA-A992P
Thursday, March 20, 2014
1
Sheet
31
of
54
1
2
3
4
5
+3VGS
#9/2 , Add RV191 between.
GPU_PWR_LEVEL# and GPU_THERMAL_DET#
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
B
PEG_GTX_HRX_P7 AC9
PEG_GTX_HRX_N7 AB9
PEG_GTX_HRX_P8 AB10
PEG_GTX_HRX_N8 AC10
PEG_GTX_HRX_P9 AD11
PEG_GTX_HRX_N9 AC11
PEG_GTX_HRX_P10 AC12
PEG_GTX_HRX_N10 AB12
AB13
AC13
AD14
AC14
AC15
AB15
AB16
AC16
AD17
AC17
AC18
AB18
AB19
AC19
AD20
AC20
AC21
AB21
AD23
AE23
AF24
AE24
AG24
AG25
AE8
AD8
& lt; 7 & gt; CLK_PCIE_GPU
& lt; 7 & gt; CLK_PCIE_GPU#
& lt; CPU & gt;
AF22
AE22
1
2
PEX_TERMP
RV27 DIS@ 2.49K_0402_1%
PLT_RST_VGA#
Differential signal
1 DIS@ 2
PEX_TSTCLK_OUT
RV26
200_0402_1% PEX_TSTCLK_OUT#
AF25
AC7
GPU_CLKREQ#_R
C
AC6
PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DACA_RED
DACA_BLUE
DACA_GREEN
DACA_VREF
DACA_RSET
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
TESTMODE
GPIO
I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
I2CC_SCL
I2CC_SDA
I2CS_SCL
I2CS_SDA
C6
B2
D6
C7
F9
A3
A4
B6
A6
F8
C5
E7
D7
B4
B3
C3
D5
D4
C2
F7
E6
C4
RV62
1 DIS@
2 100K_0402_5%
RV43
1 DIS@
2 10K_0402_5%
RV44
1 DIS@
2 10K_0402_5%
RV46
1 DIS@
2 10K_0402_5%
GPU_GPIO9
RV48
1 DIS@
2 10K_0402_5%
GPU_GPIO0
GPU_GPIO6
A
GPU_GPIO8
GPU_GPIO9
NVVDD_PWM_VID
GPU_PWR_LEVEL# RV191
NVVDD_PSI
1 DIS@
NVVDD_PWM_VID & lt; 53 & gt;
GPU_THERMAL_DET# & lt; 30 & gt;
NVVDD_PSI & lt; 53 & gt;
2 0_0402_5%
AE3
AE4
CHECK!!
GPU_GPIO0
#8/19 ,N15V-GM didn't support GC6,
unpop QV13 ,QV14.
AG3
AF3
AF4
AE2
AF2
AE5
AE6
AF6
AD6
AG4
GPU_JTAG_TCK
AD9
TESTMODE
B7
A7
I2CA_SCL
I2CA_SDA
C9
C8
I2CB_SCL
I2CB_SDA
A9
B9
I2CC_SCL
I2CC_SDA
D9
D8
I2CS_SCL
I2CS_SDA
A10
XTALSSIN
RV23 1 DIS@
2 10K_0402_5%
C10
XTALOUT
RV25 1 DIS@
2 10K_0402_5%
B10
XTAL_OUT
C11
XTALIN
RV58 1 DIS@
2 10K_0402_5%
T1402
T1403
T1404
GPU_JTAG_TRST
B
RV14 1 DIS@
RV15 1 DIS@
2 2.2K_0402_5%
2 2.2K_0402_5%
#08/22,unused I2C change to pull‐down.
+3VGS
+3VGS
RV21 1 DIS@
RV22 1 DIS@
DIS@
GPU_JTAG_TCK
TESTMODE
GPU_JTAG_TRST
GPU_CLKREQ#_R
2 2.2K_0402_5%
2 2.2K_0402_5%
RV36
1
2
3
4
DIS@ RV16
1
2
3
4
I2CB_SDA
I2CB_SCL
I2CC_SDA
I2CC_SCL
8
7
6
5
2.2K_0804_8P4R_5%
XTAL_OUTBUFF
XTAL_OUT
XTAL_IN
10K_0804_8P4R_5%
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N
+3VGS
NC
PEX_RST_N
NC
PEX_CLKREQ_N
NC
AB6
D10
E9
C
2
DIS@
EC_SMB_DA2 & lt; 18,30,7 & gt;
2N7002KDWH_SOT363-6
RV20
2
1
1
2 0_0402_5%
@
PU AT EC SIDE, +3VS AND 4.7K
G
2
2
2 0_0402_5%
@
QV2A
6
1
I2CS_SDA
P
CV17
1
QV10
DIS@
2N7002K_SOT23-3
2
1
GPU_CLKREQ#_R
@
RV188
1
D
1
@
0.1U_0402_16V7K
2
RV186
10K_0402_5%
DIS@
3
S
1
& lt; 7,8 & gt; GPU_CLKREQ#
0_0402_5%
XTALIN
RV187
10K_0402_5%
@
2
XTALIN & lt; 31 & gt;
XTALIN
2
Compal Secret Data
2011/07/12
Deciphered Date
2012/07/01
1
1
3
GND
4
3
XTAL_OUT
GND
2
CV10
XTALDIS@
27MHZ 10PF 5YEA27000102IF50Q3
1
2
& lt; PV & gt; CV9,CV10 change to 10pf.
Compal Electronics, Inc.
N15V-GM PCIE/DAC/GPIO
Size Document Number
Custom
LA-A992P 32 of 54
Thursday, March 20, 2014
Date:
Sheet
2
3
4
D
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
10P_0402_50V8J
1
10P_0402_50V8J
CV9
XTALDIS@
Security Classification
XTALDIS@
2 10M_0402_5%
XTALDIS@
YV1
D
Issued Date
RV24 1
2
5
EC_SMB_CK2 & lt; 18,30,7 & gt;
PLT_RST_VGA#
G
Y
A
4
3
TC7SH08FUF_SSOP5
DIS@
UV11
1
DIS@
2
B
SI 11/05 change RV182.1
change to +3VGS from GPU_PWR_EN
0.01U_0402_16V7K
EC or CPU control
DGPU_HOLD_RST#
1
2
CV12
& lt; 30,9 & gt; DGPU_HOLD_RST#
PLT_RST#
RV13 1
10K_0402_5%
DIS@
RV182
+3VGS
1
& lt; 21,23,28,30,8 & gt; PLT_RST#
DIS@
2N7002KDWH_SOT363-6
+3VGS
RV184
10K_0402_5%
@
QV2B
3
4
I2CS_SCL
2
RV183 1
@ 0_0402_5%
8
7
6
5
#08/22,unused I2C change to pull‐down.
N15V-GM
DIS@
+3VGS
2 10K_0402_5%
Internal Thermal Sensor
XTAL_SSIN
PEX_REFCLK
PEX_REFCLK_N
PEX_TERMP
1 DIS@
RV49
5
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DACA
PEG_GTX_C_HRX_P7 CV1
PEG_GTX_C_HRX_N7 CV2
PEG_GTX_C_HRX_P8 CV3
PEG_GTX_C_HRX_N8 CV4
PEG_GTX_C_HRX_P9 CV5
PEG_GTX_C_HRX_N9 CV6
PEG_GTX_C_HRX_P10 CV7
PEG_GTX_C_HRX_N10 CV8
PCI EXPRESS
PEG_GTX_C_HRX_P7
PEG_GTX_C_HRX_N7
PEG_GTX_C_HRX_P8
PEG_GTX_C_HRX_N8
PEG_GTX_C_HRX_P9
PEG_GTX_C_HRX_N9
PEG_GTX_C_HRX_P10
PEG_GTX_C_HRX_N10
TEST
& lt; CPU & gt;
& lt; 10 & gt;
& lt; 10 & gt;
& lt; 10 & gt;
& lt; 10 & gt;
& lt; 10 & gt;
& lt; 10 & gt;
& lt; 10 & gt;
& lt; 10 & gt;
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
DACA_HSYNC
DACA_VSYNC
I2C
A
CLK
& lt; CPU & gt;
PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
GPU_GPIO6
GPU_GPIO8
Part 1 of 5
AG6
AG7
AF7
AE7
AE9
AF9
AG9
AG10
AF10
AE10
AE12
AF12
AG12
AG13
AF13
AE13
AE15
AF15
AG15
AG16
AF16
AE16
AE18
AF18
AG18
AG19
AF19
AE19
AE21
AF21
AG21
AG22
PEG_HTX_C_GRX_P7
PEG_HTX_C_GRX_N7
PEG_HTX_C_GRX_P8
PEG_HTX_C_GRX_N8
PEG_HTX_C_GRX_P9
PEG_HTX_C_GRX_N9
PEG_HTX_C_GRX_P10
PEG_HTX_C_GRX_N10
PEG_HTX_C_GRX_P7
PEG_HTX_C_GRX_N7
PEG_HTX_C_GRX_P8
PEG_HTX_C_GRX_N8
PEG_HTX_C_GRX_P9
PEG_HTX_C_GRX_N9
PEG_HTX_C_GRX_P10
PEG_HTX_C_GRX_N10
GPU_PWR_LEVEL#
NVVDD_PSI
UV1A
& lt; 10 & gt;
& lt; 10 & gt;
& lt; 10 & gt;
& lt; 10 & gt;
& lt; 10 & gt;
& lt; 10 & gt;
& lt; 10 & gt;
& lt; 10 & gt;
5
Rev
0.1
1
2
3
4
5
UV1C
Part 3 of 5
N4
N5
T2
T3
T1
R1
R2
R3
N2
N3
B
P3
P4
V3
V4
U3
U4
T4
T5
R4
R5
J2
J3
N1
M1
M2
M3
K2
K3
K1
J1
C
H3
H4
M4
M5
L3
L4
K4
K5
J4
J5
STRAP
IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N
IFPC_AUX_I2CW_SCL
IFPC_AUX_I2CW_SDA_N
IFPC_L0
IFPC_L0_N
IFPC_L1
IFPC_L1_N
IFPC_L2
IFPC_L2_N
IFPC_L3
IFPC_L3_N
GENERAL
AB5
AB4
AB3
AB2
AD3
AD2
AE1
AD1
AD4
AD5
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
NC
BUFRST_N
THERMDN
THERMDP
ROM_SCLK
ROM_SI
ROM_SO
IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA_N
NC
NC
NC
NC
NC
NC
NC
NC
IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N
NC
NC
NC
NC
NC
NC
NC
NC
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
DIS@
RV28 1
D11
& lt; 39 & gt;
& lt; 39 & gt;
& lt; 39 & gt;
& lt; 39 & gt;
& lt; 39 & gt;
A
2 100K_0402_5%
E12
F12
D12 ROM_CS
RV29
1
C12 ROM_SCLK
B12
+3VGS
ROM_SCLK & lt; 39 & gt;
ROM_SI
A12
2 10K_0402_5%
ROM_SO
ROM_SI & lt; 39 & gt;
ROM_SO & lt; 39 & gt;
B
IFPAB_RSET
IFPC_RSET
IFPD_RSET
NC
IFPD_AUX_I2CX_SCL
IFPD_AUX_I2CX_SDA_N
IFPD_L0
IFPD_L0_N
IFPD_L1
IFPD_L1_N
IFPD_L2
IFPD_L2_N
IFPD_L3
IFPD_L3_N
D1
D2
E4
E3
D3
C1
DIS@
ROM_CS_N
SERIAL
A
IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N
LVDS / TMDS
AC3
AC4
Y4
Y3
AA3
AA2
AB1
AA1
AA4
AA5
NC
NC
NC
NC_G1
NC_G2
NC_G3
NC_G4
NC_G5
NC_G6
NC_G7
NC_V1
NC_V2
NC_V5
NC_V6
NC_W1
NC_W2
NC_W3
NC_W4
NC
NC
AA6
T6
U6
K6
AD10
AD7
B19
G1
G2
G3
G4
G5
G6
G7
V1
V2
V5
V6
C
W1
W2
W3
W4
E10
F10
N15V-GM
D
D
Compal Secret Data
Security Classification
Issued Date
2011/07/12
Deciphered Date
2012/07/01
Compal Electronics, Inc.
N15V-GM LVDS/HDMI/DP/THM Rev
Size Document Number
B
0.1
LA-A992P 33 of 54
Thursday, March 20, 2014
Date:
Sheet
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
3
4
5
1
2
3
4
5
+1.5VGS
UV1D
Part 4 of 5
DIS@
2
Reference circuit:
0.1uF *2
1 uF*2
4.7uF*2
10uF*1
22uF*1
A
AA10
AA12
AA13
AA16
AA18
AA19
AA20
AA21
AB22
AC23
AD24
AE25
AF26
AF27
+1.05VGS
2
2
& lt; 9 & gt; DGPU_GC6_EN
RV47 1
short@
DIS@
DIS@
1
FB_CLAMP
4.7U_0603_6.3V6K
DIS@
DIS@
2
CV77
1
1U_0402_6.3V6K
CV76
DIS@
2
0.1U_0402_10V7K
CV75
1
+PEXPLL_VDD
NC
NC
1
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
2 0_0402_5%
IFPD_PLLVDD
IFPD_PLLVDD
2
CV68
CV68
RV45 1
short@
FB_CLAMP
DIS@
+1.05VGS
FB_CAL_PD_VDDQ
2
1
1U_0402_6.3V6K
F3
2
1
CV67
+FB_CAL_PD_VDDQ D22
IFPC_PLLVDD
IFPC_PLLVDD
DACA_VDD
2
DIS@
W5
AB8 +PEX_3V3_NV
1
0.1U_0402_10V7K
2
IFPAB_PLLVDD
IFPAB_PLLVDD
F11
1
CV66
DIS@
2
1
22U_0805_6.3V6M
1
CV74
DIS@
PCB Footprint = R_0402
+GPU_PLLVDD
+FB_PLLAVDD
0.1U_0402_10V7K
#8/19,LV1 change to
Z=30 ohm , RDC=0.05
SM01000F100
IFPA_IOVDD
IFPB_IOVDD
IFPC_IOVDD
IFPD_IOVDD
NC
NC
PEX_PLLVDD
PEX_PLLVDD
VID_PLLVDD
SP_PLLVDD
CORE_PLLVDD
FB_PLLAVDD
FB_PLLAVDD
FB_DLLAVDD
G10
G12
G8
G9
VCCSENSE_VGA & lt; 53 & gt;
DIS@
+GPU_SP_PLLVDD
LV1
BLM18PG121SN1D_0603
1
2
PEX_SVDD_3V3
Power :VDD_SENSE & GND_SENSE
Differential signal
VCCSENSE_VGA
0.1U_0402_10V7K
+1.05VGS
CV73
2
AA14
AA15
N6
M6
L6
F16
P22
H22
DIS@
PEX_PLL_HVDD
PEX_PLL_HVDD
A
CV65
1
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
DIS@
DIS@
2
CV72
1
4.7U_0603_6.3V6K
CV71
DIS@
2
0.1U_0402_10V7K
CV70
1
VDD33
VDD33
VDD33
VDD33
F2
+VGA_CORE
DIS@
+3VGS
+PEX_3V3_NV
AA8
AA9
+PEXPLL_VDD
& lt; SI & gt; LV1 use R_0402 footprint
2 0_0402_5%
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
NC
+PEX_3V3_NV
RV34 1
short@
VDD_SENSE
K10
K12
K14
K16
K18
L11
L13
L15
L17
M10
M12
M14
M16
M18
N11
N13
N15
N17
P10
P12
P14
P16
P18
R11
R13
R15
R17
T10
T12
T14
T16
T18
U11
U13
U15
U17
V10
V12
V14
V16
V18
0.1U_0402_10V7K
DIS@
2
AA22
AB23
AC24
AD25
AE26
AE27
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CV64
1
22U_0805_6.3V6M
CV69
DIS@
DIS@
DIS@
2
1
22U_0805_6.3V6M
1
CV57
2
22U_0805_6.3V6M
22U_0805_6.3V6M
CV63
CV63
DIS@
DIS@
DIS@
2
1
22U_0805_6.3V6M
22U_0805_6.3V6M
1
CV56
CV56
2
10U_0805_6.3V6M
CV62
DIS@
DIS@
2
1
10U_0805_6.3V6M
1
CV55
2
10U_0805_6.3V6M
CV61
DIS@
DIS@
2
1
10U_0805_6.3V6M
1
CV54
2
4.7U_0603_6.3V6K
CV60
DIS@
DIS@
2
1
4.7U_0603_6.3V6K
1
CV53
2
1U_0402_6.3V6K
CV59
DIS@
DIS@
DIS@
2
1
1U_0402_6.3V6K
CV58
CV58
1
CV52
2
1U_0402_6.3V6K
DIS@
DIS@
Reference circuit:
1uF *2
4.7uF*1
10uF*2
22uF*2
B
1
1U_0402_6.3V6K
CV51
CV51
Reference circuit:
1uF *2
4.7uF*1
10uF*2
22uF*2
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
POWER
1
22U_0805_6.3V6M
DIS@
2
CV26
1
10U_0603_6.3V6M
2
CV29
DIS@
2
1
4.7U_0603_6.3V6K
1
CV24
DIS@
4.7U_0603_6.3V6K
2
CV23
DIS@
DIS@
2
1
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CV22
CV22
DIS@
DIS@
2
1U_0402_6.3V6K
1
CV21
0.1U_0402_10V7K
CV20
DIS@
2
0.1U_0402_10V7K
CV28
1
B26
C25
E23
E26
F14
F21
G13
G14
G15
G16
G18
G19
G20
G21
H24
H26
J21
K21
L22
L24
L26
M21
N21
R21
T21
V21
W21
2
short@1 RV30
0_0603_5%
+3VGS
B
W6
Y6
P6
R6
H6
J6
V7
W7
Remove IFPC_PLLVDD,IFPD_PLLVDD,IFPC_IOVDD,IFPD_IOVDD,IFPAB_PLLVDD,+DACA_VDD,IFPA_IOVDD
M7
N7
R7
T7
J7
K7
2 0_0402_5%
N15V-GM
DIS@
C
C
+1.05VGS
DIS@
LV3
BLM18PG121SN1D_0603
1
2
1
DIS@
DIS@
2
22U_0805_6.3V6M
22U_0805_6.3V6M
2
CV85
CV85
+1.05VGS
1
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
DG:LV4‐ & gt; Z=30 ohm , RDC=0.01 ohm.0603
DIS@
2
CV84
DIS@
2
1
0.1U_0402_10V7K
1
+GPU_SP_PLLVDD
CV83
DIS@
& lt; PV & gt; LV3,LV4 change PN.
Main:SM01000BW00
2nd:SM01000CC00
0.1U_0402_10V7K
CV82
DG : LV3 ‐ & gt; Z=180 ohm , RDC=0.2 ohm.0603
DIS@
+1.5VGS
1
RV50
2 +FB_CAL_PD_VDDQ
40.2_0402_1%
#7/27 Follow DG to chenge
R1591 to 40.2 ohm
+FB_PLLAVDD
LV4
DIS@
BLM18PG121SN1D_0603
1
2
1
DIS@
2
22U_0805_6.3V6M
22U_0805_6.3V6M
DIS@
2
CV89
1
0.1U_0402_10V7K
DIS@
2
CV88
1
0.1U_0402_10V7K
CV90
DIS@
2
0.1U_0402_10V7K
CV91
D
1
D
Compal Secret Data
Security Classification
Issued Date
2011/07/12
Deciphered Date
2012/07/01
Compal Electronics, Inc.
N15V-GM POWER
Size Document Number
Custom
LA-A992P 34 of 54
Thursday, March 20, 2014
Date:
Sheet
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
3
4
5
Rev
0.1
1
2
3
4
5
UV1E
Part 5 of 5
A
B
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AA7
A2
A26
AB11
AB14
AB17
AB20
AB24
AC2
AC22
AC26
AC5
AC8
AD12
AD13
AD15
AD16
AD18
AD19
AD21
AD22
AE11
AE14
AE17
AE20
AF1
AF11
AF14
AF17
AF20
AF23
AF5
AF8
AG2
AG26
B1
B11
B14
B17
B20
B23
B27
B5
B8
E11
E14
E17
E2
E20
E22
E25
E5
E8
H2
H23
H25
H5
K11
K13
K15
K17
FB_CAL_PU_GND
FB_CAL_TERM_GND
MULTI_STRAP_REF0_GND
NC
NC
GND_SENSE
L10
L12
L14
L16
L18
L2
L23
L25
L5
M11
M13
M15
M17
N10
N12
N14
N16
N18
P11
P13
P15
P17
P2
P23
P26
P5
R10
R12
R14
R16
R18
T11
T13
T15
T17
U10
U12
U14
U16
U18
U2
U23
U26
U5
V11
V13
V15
V17
Y2
Y23
Y26
Y5
AB7
A
#8/20 : N15V‐GM don't support GC6 function. UV20 unpop.
B
+1.05VGS=1.6A,4vias.
J2
1 DIS@ 2
RV67
42.2_0402_1%
1 DIS@ 2
RV68
51.1_0402_1%
1
2 40.2K_0402_1%
RV70 @
C24
B25
F6
F4
F5
F1
VSSSENSE_VGA
N15V-GM
DIS@
2
1
@
1
+1.05VGS
JUMP_43X79
#8/19.RV70 unpop , N15V‐GM use binary mode.
Contrl by power
+3VALW to +3VGS
+1.05V to +1.05VGS
VSSSENSE_VGA & lt; 53 & gt;
Power :VDD_SENSE & GND_SENSE
Differential signal
DIS@
QV12
1
2
RV92
DGPU_PWROK
DGPU_PWR_EN
+3VGS
+1.5VGS=3.6A,8vias.
J3
+VGA_CORE
2
+1.5VGS_GPU
2
1
@
1
4
20K_0402_5%
5
DGPU_PWR_EN
6
7
+1.5VGS
JUMP_43X118
DGPU_PWROK
& lt; 30,53,9 & gt; DGPU_PWR_EN
3
DIS@
+5VALW
VIN1
VIN1
VOUT1
VOUT1
ON1
CT1
VBIAS
GND
ON2
CT2
VIN2
VIN2
VOUT2
VOUT2
GPAD
#8/19.QV15 change to TPS22967
14
13
11
+1.5VS
C
15
+3VGS=0.5A,2vias.
CT
VBIAS
1
5
9
2
TPS22967DSGR_SON8_2X2
1
CV78 @
0.01U_0603_50V7K
1
2
CV80
DIS@
1 DIS@
CV79
2
RC370 DIS@
18_0402_5%
RV210
DIS@
100K_0402_5%
SD028180A80
DIS@
QV17B
DMN66D0LDW-7_SOT363-6
5
4
6
2
DIS@
CV183
10U_0603_6.3V6M
#08/20 Don't support GC6,Add RV66.
Unpop QV16,RV41,RV42,CV78.
6
2
ON
+3VALW
1
4
+1.05VGS
7
8
1U 6.3V K X5R 0402
+5VALW
VOUT
VOUT
3
3
2
VIN
VIN
100P_0402_50V8J
DIS@
2
RV66 1
47K_0402_5%
+3VGS
TPS22966DPUR_SON14_2X3-D
1
1
GND
GND
DGPU_PWROK
2 100P_0402_50V8J
DIS@
2
DIS@ CV81
10U_0603_6.3V6M
CV182 1
9
8
QV15
1
2
40us & lt; Rt & lt; 2ms
2 680P_0402_50V7K
DIS@
10
+1.5VGS_GPU
+1.5VGS
CV181 1
12
+1.5V to +1.5VGS
+1.05VGS
& lt; 53 & gt; DGPU_PWROK
+1.05V_GPU
+3VALW +1.05V
Power on
C
2
+1.05V_GPU
DIS@
QV17A
DMN66D0LDW-7_SOT363-6
2
1
DGPU_PWROK
D
D
PV# 2013.01.08 Add +1.05VGS discharge circuit
Compal Secret Data
Security Classification
Issued Date
2011/07/12
Deciphered Date
2012/07/01
Compal Electronics, Inc.
N15V-GM VGA CORE, GND
Size Document Number
Custom
LA-A992P 35 of 54
Thursday, March 20, 2014
Date:
Sheet
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
3
4
5
Rev
0.1
1
2
3
4
5
PU for X16 mode
UV1B
B
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
D23
T1405
& lt; 37 & gt; CLKA0
& lt; 37 & gt; CLKA0#
C
& lt; 38 & gt; CLKA1
& lt; 38 & gt; CLKA1#
E18
F18
E16
F17
D20
D21
F20
E21
E15
D15
F15
F13
C13
B13
E13
D13
B15
C16
A13
A15
B18
A18
A19
C19
B24
C23
A25
A24
A21
B21
C20
C21
R22
R24
T22
R23
N25
N26
N23
N24
V23
V22
T23
U22
Y24
AA24
Y22
AA23
AD27
AB25
AD26
AC25
AA27
AA26
W26
Y25
R26
T25
N27
R27
V26
V27
W27
W25
CLKA0
CLKA0#
D24
D25
CLKA1 N22
CLKA1# M22
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
MEMORY INTERFACE
Part 2 of 5
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
A
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
FBA_WCK01
FBA_WCK01_N
FBA_WCK23
FBA_WCK23_N
FB_VREF_PROBE
FBA_WCK45
FBA_WCK45_N
FBA_CLK0
FBA_WCK67
FBA_CLK0_N
FBA_WCK67_N
FBA_CLK1
FBA_CLK1_N
C27
C26
E24
F24
D27
D26
F25
F26
F23
G22
G23
G24
F27
G25
G27
G26
M24
M23
K24
K23
M27
M26
M25
K26
K22
J23
J25
J24
K27
K25
J27
J26
CMDA0
CMDA0 & lt; 37 & gt;
Dummy
CMDA2
CMDA3
CMDA4
CMDA5
CMDA6
CMDA7
CMDA8
CMDA9
CMDA10
CMDA11
CMDA12
CMDA13
Dummy
CMDA15
CMDA16
CMDA18
CMDA19
CMDA20
CMDA21
CMDA22
CMDA23
CMDA24
CMDA25
CMDA26
CMDA27
CMDA28
CMDA29
CMDA30
1
CMDA2
DIS@
2 RV170
1
CMDA18
DIS@
2 RV185
1
CMDA3
Mode D Command Mapping
10K_0402_1%
RANK 0
10K_0402_1%
Address
DIS@
2 RV189
1
CMDA19
DIS@
2 RV190
1
CMDA5
FBx_CMD0
10K_0402_1%
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 37,38 & gt;
& lt; 37,38 & gt;
& lt; 37,38 & gt;
& lt; 37,38 & gt;
& lt; 37,38 & gt;
& lt; 37,38 & gt;
& lt; 37,38 & gt;
& lt; 37,38 & gt;
& lt; 37,38 & gt;
& lt; 37,38 & gt;
& lt; 37,38 & gt;
0..31
32..63
CS0#
FBx_CMD1
10K_0402_1%
FBx_CMD2
ODT
FBx_CMD3
CKE
FBx_CMD4
A14
FBx_CMD5
RST
RST
FBx_CMD6
A9
A9
A14
DQSA0
DQSA1
DQSA2
DQSA3
DQSA4
DQSA5
DQSA6
DQSA7
DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7
DQSA#0
DQSA#1
DQSA#2
DQSA#3
DQSA#4
DQSA#5
DQSA#6
DQSA#7
DQSA0
DQSA1
DQSA2
DQSA3
DQSA4
DQSA5
DQSA6
DQSA7
FBx_CMD7
A7
A2
A2
A0
A0
FBx_CMD10
A4
A4
FBx_CMD11
A1
A1
FBx_CMD12
BA0
BA0
FBx_CMD13
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
A7
FBx_CMD8
FBx_CMD9
DQSA#0
DQSA#1
DQSA#2
DQSA#3
DQSA#4
DQSA#5
DQSA#6
DQSA#7
E19
C15
B16
B22
R25
W23
AB26
T26
CMDA18
CMDA19
CMDA20
CMDA21
CMDA22
CMDA23
CMDA24
CMDA25
CMDA26
CMDA27
CMDA28
CMDA29
CMDA30
DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7
F19
C14
A16
A22
P25
W22
AB27
T27
DIS@
2 RV169
10K_0402_1%
CMDA15 & lt; 37,38 & gt;
CMDA16 & lt; 38 & gt;
Dummy
D19
D14
C17
C22
P24
W24
AA25
U25
A
Note: DG use 1%
CMDA2 & lt; 37 & gt;
CMDA3 & lt; 37 & gt;
CMDA4 & lt; 37,38 & gt;
CMDA5 & lt; 37,38 & gt;
CMDA6 & lt; 37,38 & gt;
CMDA7 & lt; 37,38 & gt;
CMDA8 & lt; 37,38 & gt;
CMDA9 & lt; 37,38 & gt;
CMDA10 & lt; 37,38 & gt;
CMDA11 & lt; 37,38 & gt;
CMDA12 & lt; 37,38 & gt;
CMDA13 & lt; 37,38 & gt;
WE#
WE#
CAS#
CAS#
B
FBx_CMD14
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
FBx_CMD15
FBx_CMD16
CS0#
FBx_CMD17
FBx_CMD18
ODT
FBx_CMD19
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 37 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
& lt; 38 & gt;
CKE
FBx_CMD20
A13
A8
A8
FBx_CMD22
A6
A6
FBx_CMD23
A11
A11
FBx_CMD24
A5
A5
FBx_CMD25
A3
A3
FBx_CMD26
BA2
BA2
FBx_CMD27
BA1
BA1
FBx_CMD28
A12
A12
FBx_CMD29
A10
A10
FBx_CMD30
D18
C18
D17
D16
T24
U24
V24
V25
A13
FBx_CMD21
RAS#
RAS#
C
FBA_DEBUG0
FBA_DEBUG1
F22
J22
RV137 1
RV138 1
@
@
2 60.4_0402_1%
2 60.4_0402_1%
+1.5VGS
N15V-GM
DIS@
D
D
Compal Secret Data
Security Classification
Issued Date
2011/07/12
Deciphered Date
2012/07/01
Compal Electronics, Inc.
N15V-GM MEM Interface
Size Document Number
Custom
LA-A992P 36 of 54
Thursday, March 20, 2014
Date:
Sheet
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
3
4
5
Rev
0.1
1
2
3
4
Memory Partition A RANK 0
Data0~Data31
Rank 0
1
+1.5VGS
RV139
1.33K_0402_1%
DIS@
2
UV12
+FBA_VREF0
A
1
DIS@
DIS@
2
1
2
0.01U_0402_16V7K
CV96
CV96
RV140
1.33K_0402_1%
DIS@
M8
H1
+FBA_VREF0
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
CMDA9
CMDA11
CMDA8
CMDA25
CMDA10
CMDA24
CMDA22
CMDA7
CMDA21
CMDA6
CMDA29
CMDA23
CMDA28
CMDA20
CMDA4
1
CLKA0
RV141
162_0402_1%
DIS@
M2
N8
M3
2
CMDA12
CMDA27
CMDA26
#8/19 , change CLK
termination to 162 ohm.
K1
L2
J3
K3
L3
CMDA2
CMDA0
CMDA30
CMDA15
CMDA13
H:Group 1
L:Group 2
DML
DMU
G3
B7
DQSA#2
DQSA#1
& lt; 36 & gt; DQSA#2
& lt; 36 & gt; DQSA#1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
T2
CMDA5
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQSL
DQSU
E7
D3
DQMA2
DQMA1
& lt; 36 & gt; DQMA2
& lt; 36 & gt; DQMA1
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
ODT/ODT0
CS/CS0
RAS
CAS
WE
F3
C7
DQSA2
DQSA1
& lt; 36 & gt; DQSA2
& lt; 36 & gt; DQSA1
Rank 0
E3
F7
F2
F8
H3
H8
G2
H7
MDA19
MDA21
MDA16
MDA22
MDA18
MDA23
MDA17
MDA20
D7
C3
C8
C2
A7
A2
B8
A3
MDA10
MDA13
MDA11
MDA14
MDA8
MDA15
MDA9
MDA12
M8
H1
+FBA_VREF0
Group 2
Group 1
RESET
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
L:Group 0
H:Group 3
DML
DMU
G3
B7
DQSA#0
DQSA#3
& lt; 36 & gt; DQSA#0
& lt; 36 & gt; DQSA#3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
T2
CMDA5
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQSL
DQSU
E7
D3
DQMA0
DQMA3
& lt; 36 & gt; DQMA0
& lt; 36 & gt; DQMA3
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
ODT/ODT0
CS/CS0
RAS
CAS
WE
F3
C7
DQSA0
DQSA3
& lt; 36 & gt; DQSA0
& lt; 36 & gt; DQSA3
E3
F7
F2
F8
H3
H8
G2
H7
MDA4
MDA0
MDA5
MDA2
MDA7
MDA1
MDA6
MDA3
D7
C3
C8
C2
A7
A2
B8
A3
MDA31
MDA27
MDA30
MDA25
MDA28
MDA26
MDA29
MDA24
A
Group 0
Mode D Command Mapping
RANK 0
Address
FBx_CMD0
Group 3
RESET
0..31
32..63
CS0#
FBx_CMD1
FBx_CMD2
B2
D9
G7
K2
K8
N1
N9
R1
R9
ODT
FBx_CMD3
+1.5VGS
CK
CK
CKE/CKE0
K1
L2
J3
K3
L3
CMDA2
CMDA0
CMDA30
CMDA15
CMDA13
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
BA0
BA1
BA2
J7
K7
K9
CLKA0
CLKA0#
CMDA3
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
M2
N8
M3
CMDA12
CMDA27
CMDA26
X76@
VREFCA
VREFDQ
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
CMDA9
CMDA11
CMDA8
CMDA25
CMDA10
CMDA24
CMDA22
CMDA7
CMDA21
CMDA6
CMDA29
CMDA23
CMDA28
CMDA20
CMDA4
+1.5VGS
CK
CK
CKE/CKE0
B
160 ohm:SD00000XP00
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
BA0
BA1
BA2
J7
K7
K9
CLKA0
CLKA0#
CMDA3
& lt; 36 & gt; CLKA0
& lt; 36 & gt; CLKA0#
CMDA[30..0] & lt; 36,38 & gt;
UV14
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
CLKA0#
MDA[0..63] & lt; 36,38 & gt;
X76@
VREFCA
VREFDQ
5
CKE
FBx_CMD4
A14
A14
FBx_CMD5
RST
RST
FBx_CMD6
A9
A9
FBx_CMD7
A7
A7
FBx_CMD8
A2
A2
FBx_CMD9
A0
A0
FBx_CMD10
A4
A4
FBx_CMD11
A1
A1
FBx_CMD12
BA0
BA0
FBx_CMD13
WE#
WE#
B
A1
A8
C1
C9
D2
E9
F1
H2
H9
FBx_CMD14
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
FBx_CMD15
CAS#
CAS#
CS0#
FBx_CMD16
FBx_CMD17
ODT
FBx_CMD18
CKE
FBx_CMD19
1
1
B1
B9
D1
D8
E2
E8
F9
G1
G9
J1
L1
J9
L9
RV150
243_0402_1%
DIS@
96-BALL
SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96
+1.5VGS
L
1
A6
A6
FBx_CMD23
A11
A11
FBx_CMD24
A5
A5
FBx_CMD25
A3
A3
FBx_CMD26
BA2
BA2
FBx_CMD27
BA1
BA1
FBx_CMD28
A12
A12
A10
A10
RAS#
RAS#
A13
C
1
DIS@
2
1U_0402_6.3V6K
DIS@
2
CV127
1
1U_0402_6.3V6K
1U_0402_6.3V6K
DIS@
DIS@
2
CV126
1
1U_0402_6.3V6K
DIS@
2
CV125
CV125
1
1U_0402_6.3V6K
DIS@
2
CV124
1
1U_0402_6.3V6K
1U_0402_6.3V6K
DIS@
1
CV123
2
0.1U_0402_16V7K
DIS@
1
CV122
2
0.1U_0402_16V7K
DIS@
DIS@
1
CV121
2
0.1U_0402_16V7K
DIS@
1
CV120
CV120
2
0.1U_0402_16V7K
DIS@
1
CV119
2
Closed to UV14
L
0.1U_0402_16V7K
0.1U_0402_16V7K
CV118
DIS@
2
1U_0402_6.3V6K
DIS@
DIS@
2
CV106
1
1U_0402_6.3V6K
DIS@
2
CV105
CV105
1
1U_0402_6.3V6K
DIS@
2
CV104
1
1U_0402_6.3V6K
1U_0402_6.3V6K
DIS@
2
CV103
1
1U_0402_6.3V6K
DIS@
1
CV102
2
0.1U_0402_16V7K
DIS@
DIS@
1
CV101
2
0.1U_0402_16V7K
DIS@
1
CV100
CV100
2
A8
FBx_CMD22
B1
B9
D1
D8
E2
E8
F9
G1
G9
A8
Closed to UV12
0.1U_0402_16V7K
CV99
DIS@
1
0.1U_0402_16V7K
0.1U_0402_16V7K
CV98
DIS@
DIS@
0.1U_0402_16V7K
CV97
CV97
1
2
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
FBx_CMD21
96-BALL
SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96
+1.5VGS
2
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
2
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
2
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
ZQ/ZQ0
A13
FBx_CMD30
J1
L1
J9
L9
RV145
243_0402_1%
DIS@
C
ZQ/ZQ0
L8
FBx_CMD20
FBx_CMD29
L8
D
D
Compal Secret Data
Security Classification
Issued Date
2011/07/12
2012/07/01
Deciphered Date
Compal Electronics, Inc.
N15V-GM VRAM A Lower
Size Document Number
Custom
LA-A992P 37 of 54
Date:
Sheet
Thursday, March 20, 2014
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
3
4
5
Rev
0.1
1
2
3
4
Memory Partition A RANK 0 32 bits
5
MDA[0..63] & lt; 36,37 & gt;
+1.5VGS
CMDA[30..0] & lt; 36,37 & gt;
1
Rank 0
Data32~Data63
Rank 0
2
RV152
1.33K_0402_1%
DIS@
A
DIS@
DIS@
2
1
2
UV16 X76@
0.01U_0402_16V7K
RV153
1.33K_0402_1%
DIS@
CV138
CV138
1
+FBA_VREF1
M8
H1
+FBA_VREF1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
CMDA9
CMDA11
CMDA8
CMDA25
CMDA10
CMDA24
CMDA22
CMDA7
CMDA21
CMDA6
CMDA29
CMDA23
CMDA28
CMDA20
CMDA4
1
CLKA1
CMDA12
CMDA27
CMDA26
M2
N8
M3
CLKA1
CLKA1#
CMDA19
J7
K7
K9
CMDA18
CMDA16
CMDA30
CMDA15
CMDA13
K1
L2
J3
K3
L3
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
B
CLKA1#
& lt; 36 & gt; CLKA1
& lt; 36 & gt; CLKA1#
#8/19 , change CLK
termination to 162 ohm.
DQSA4
DQSA7
L:Group 4
H:Group 7
& lt; 36 & gt; DQMA4
& lt; 36 & gt; DQMA7
F3
C7
DQMA4
DQMA7
& lt; 36 & gt; DQSA4
& lt; 36 & gt; DQSA7
E7
D3
G3
B7
DQSA#4
DQSA#7
& lt; 36 & gt; DQSA#4
& lt; 36 & gt; DQSA#7
E3
F7
F2
F8
H3
H8
G2
H7
MDA35
MDA37
MDA34
MDA39
MDA32
MDA38
MDA33
MDA36
D7
C3
C8
C2
A7
A2
B8
A3
MDA56
MDA60
MDA58
MDA61
MDA57
MDA63
MDA59
MDA62
M8
H1
+FBA_VREF1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
CMDA9
CMDA11
CMDA8
CMDA25
CMDA10
CMDA24
CMDA22
CMDA7
CMDA21
CMDA6
CMDA29
CMDA23
CMDA28
CMDA20
CMDA4
Group 4
Group 7
BA0
BA1
BA2
310mA
CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQSL
DQSU
DML
DMU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
B2
D9
G7
K2
K8
N1
N9
R1
R9
CMDA12
CMDA27
CMDA26
CMDA18
CMDA16
CMDA30
CMDA15
CMDA13
A1
A8
C1
C9
D2
E9
F1
H2
H9
J7
K7
K9
K1
L2
J3
K3
L3
DQSA6
DQSA5
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
L:Group 6
H:Group 5
& lt; 36 & gt; DQMA6
& lt; 36 & gt; DQMA5
Mode D Command Mapping
RANK 0
FBx_CMD0
DQSL
DQSU
DML
DMU
CKE
FBx_CMD4
A14
FBx_CMD5
RST
RST
FBx_CMD6
A9
A9
A14
FBx_CMD7
A7
A7
FBx_CMD8
A2
A2
FBx_CMD9
A0
A0
FBx_CMD10
A4
A4
FBx_CMD11
A1
A1
FBx_CMD12
BA0
BA0
FBx_CMD13
WE#
WE#
CAS#
CAS#
FBx_CMD15
FBx_CMD16
CS0#
FBx_CMD17
FBx_CMD18
ODT
FBx_CMD19
CKE
J1
L1
J9
L9
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
2
RV155
243_0402_1%
DIS@
ZQ/ZQ0
T2
CMDA5
B1
B9
D1
D8
E2
E8
F9
G1
G9
A6
A11
A11
FBx_CMD24
A5
A5
FBx_CMD25
A3
A3
FBx_CMD26
BA2
BA2
FBx_CMD27
BA1
BA1
FBx_CMD28
A12
A12
FBx_CMD29
A10
A10
RAS#
RAS#
1
DIS@
2
Issued Date
D
Compal Secret Data
Security Classification
2011/07/12
Deciphered Date
2012/07/01
Compal Electronics, Inc.
N15V-GM VRAM C Lower
Size Document Number
Custom
LA-A992P 38 of 54
Thursday, March 20, 2014
Date:
Sheet
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
3
C
1U_0402_6.3V6K
DIS@
2
CV169
1
1U_0402_6.3V6K
DIS@
2
CV168
1
1U_0402_6.3V6K
DIS@
2
CV167
1
1U_0402_6.3V6K
DIS@
DIS@
2
CV166
1
1U_0402_6.3V6K
DIS@
1
CV165
CV165
2
0.1U_0402_16V7K
0.1U_0402_16V7K
DIS@
1
CV164
2
A6
FBx_CMD23
B1
B9
D1
D8
E2
E8
F9
G1
G9
A8
FBx_CMD22
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A13
A8
Closed to UV18
0.1U_0402_16V7K
DIS@
1
CV163
2
0.1U_0402_16V7K
DIS@
1
CV162
2
0.1U_0402_16V7K
DIS@
1
CV161
2
L
0.1U_0402_16V7K
DIS@
DIS@
2
CV160
1
1U_0402_6.3V6K
1U_0402_6.3V6K
DIS@
2
CV148
CV148
1
1U_0402_6.3V6K
DIS@
2
CV147
1
1U_0402_6.3V6K
DIS@
2
CV146
1
1U_0402_6.3V6K
DIS@
2
CV145
1
+1.5VGS
1U_0402_6.3V6K
DIS@
DIS@
1
CV144
2
0.1U_0402_16V7K
CV143
CV143
DIS@
DIS@
1
0.1U_0402_16V7K
0.1U_0402_16V7K
DIS@
1
2
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
A13
FBx_CMD21
96-BALL
SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96
Closed to UV16
CV142
CV142
2
0.1U_0402_16V7K
DIS@
1
CV141
2
0.1U_0402_16V7K
CV140
DIS@
1
0.1U_0402_16V7K
CV139
D
2
L
ZQ/ZQ0
J1
L1
J9
L9
RV162
243_0402_1%
DIS@
96-BALL
SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96
+1.5VGS
RESET
L8
1
C
RESET
2
1
L8
FBx_CMD20
FBx_CMD30
T2
CMDA5
B
FBx_CMD14
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
ODT
FBx_CMD3
A1
A8
C1
C9
D2
E9
F1
H2
H9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
32..63
CS0#
FBx_CMD2
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
0..31
FBx_CMD1
Group 5
+1.5VGS
ODT/ODT0
CS/CS0
RAS
CAS
WE
G3
B7
DQSA#6
DQSA#5
& lt; 36 & gt; DQSA#6
& lt; 36 & gt; DQSA#5
MDA44
MDA40
MDA46
MDA41
MDA45
MDA43
MDA47
MDA42
Group 6
Address
CK
CK
CKE/CKE0
E7
D3
MDA52
MDA49
MDA53
MDA50
MDA54
MDA48
MDA55
MDA51
D7
C3
C8
C2
A7
A2
B8
A3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
BA0
BA1
BA2
F3
C7
DQMA6
DQMA5
& lt; 36 & gt; DQSA6
& lt; 36 & gt; DQSA5
E3
F7
F2
F8
H3
H8
G2
H7
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
M2
N8
M3
CLKA1
CLKA1#
CMDA19
A
X76@
VREFCA
VREFDQ
+1.5VGS
2
RV154
162_0402_1%
DIS@
UV18
4
5
Rev
0.1
1
2
3
4
10K
Pull-down to GND if no VBIOS ROM.
VGA_DEVICE
10K
Pull-down to GND(no diaplay).
RAM_CFG[0]
10K
RAM_CFG[1]
10K
RAM_CFG[2]
10K
RAM_CFG[3]
10K
PCIE_MAX_SPEED
10K
2
2
2
2
SUB_VENDOR
ROM_SO
1
1
1
1
1
2
Pull-down to GND.
ROM_SI
RV168
10K_0402_5%
@
10K
STRAP2
RV167
10K_0402_5%
X76@
SMB_ALT_ADDR
STRAP1
RV166
10K_0402_5%
X76@
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
Resistance
Polarity
Logical
Strapping Bit0
1
1
STRAP4
RV175
10K_0402_5%
DIS@
2
RV174
10K_0402_5%
X76@
2
2
RV173
10K_0402_5%
X76@
SMBUS_ALT_ADDR
Pull-down to GND(PCIE Gen1).
SUB_VENDOR
2
RV172
10K_0402_5%
X76@
RV171
10K_0402_5%
X76@
2
1
1
A
1
A
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
RV165
10K_0402_5%
X76@
Strap Mapping
STRAP0
RV164
10K_0402_5%
X76@
Strap pin
Name
ROM_SCLK
STRAP3
Check Strap pin status
& lt; 33 & gt;
& lt; 33 & gt;
& lt; 33 & gt;
& lt; 33 & gt;
& lt; 33 & gt;
5
Table 123
+3VGS
0
0x9E (Default)
0
1
0x9C (Multi-GPU usage)
1
Disable (Default)
+3VGS
VGA_DEVICE
Non-Primary 3D Acceleration Device(Class Code 302h)(Default)
1
RV178
10K_0402_5%
@
Primary Display or VGA Device .
2
RV177
10K_0402_5%
@
2
2
RV176
10K_0402_5%
@
0
1
1
1
Check SPI pin status
PCIE_MAX_SPEED
& lt; 33 & gt; ROM_SI
& lt; 33 & gt; ROM_SO
& lt; 33 & gt; ROM_SCLK
ROM_SI
ROM_SO
ROM_SCLK
ZZZ001
ZZZ001
SAM@
MIC@
1G SAMSUNG
X7654132L21
GPU
Project
VRAM size
CH
Compal VRAM P/N
N15V-GM (23x23) 64bit
(One CH single rank)
DDR3 Hynix 128Mx16 1.5V
SA00006H400
128M(X16) CHA
DDR3 Micron 128Mx16 1.5V
SA000067500
128M(X16) CHA
ZSO40
ZSO50
128M(X16) CHA
Description
PCIE Gen 2/3 Capable
B
ZZZ001
RV181
10K_0402_5%
DIS@
2
RV180
10K_0402_5%
DIS@
2
2
RV179
10K_0402_5%
DIS@
1
1
B
Limit to PCIE Gen1
1
1
0
DDR3 Samsung 128Mx16 1.5V SA000068U40
VRAM description
ROM CFG setup
[3...0]
HY@
1G MICRON
X7654132L23
RAM_CFG
1G HYNIX
X7654132L22
R P/N
H5TC2G63FFR-11C 1000MHz
1100
RV171+RV172+RV167+RV166
MT41J128M16JT-093G:K 1000MHz
0001
RV164+RV172+RV173+RV174
K4W2G1646Q-BC1A 1000MHz
1110
RV165+RV166+RV167+RV171
#9/5 RAM_CFG follow RVL‐06891‐001 table 1.
Dule Rank layout with single Rank population.
USER Straps
User[3:0]
1000-1100
C
Customer defined
C
D
D
Compal Secret Data
Security Classification
Issued Date
2011/07/12
Deciphered Date
2012/07/01
Compal Electronics, Inc.
N15V-GM MISC
Size Document Number
Custom
LA-A992P 39 of 54
Thursday, March 20, 2014
Date:
Sheet
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
3
4
5
Rev
1.0
A
B
C
D
E
& lt; MV & gt; Remove R563, delete net +5VS_IN ,4/10.
+5VALW
2
Q21
1
4
SUSP#
5
6
7
ON1
VBIAS
CT1
GND
ON2
CT2
VIN2
VIN2
VOUT2
VOUT2
GPAD
12
C554 1
& lt; MV & gt; Add 22UF for RF suggestion ,4/10.
2 100P_0402_50V8J
SYSON#
SUSP
11
10
C557 1
1
3
3
@
Q18A
Q18B
2 680P_0402_50V7K
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
9
8
& lt; 30,48 & gt; SYSON
SYSON
2
15
5
SUSP#
SUSP# & lt; 30,48,49,52,55 & gt;
4
SUSP#
VOUT1
VOUT1
2
6
+5VALW
VIN1
VIN1
14
13
1
1
2
1
CC56
22U_0805_6.3V6M
+3VALW
+5VS
C575
10U_0603_6.3V6M
1
+3VS
TPS22966DPUR_SON14_2X3-D
2
& lt; MV & gt; Remove R564, delete net +3VS_IN ,4/10.
C570
C570
10U_0603_6.3V6M
1
+5VALW
SYSON
SUSP
SYSON#
SUSP#
+1.05V TO +1.05VS
RPH16
8
7
6
5
1
2
3
4
100K_0804_8P4R_5%
+1.05V
+1.05VS
J1 need to short
J1
1
2
AO4430L
VGS Max=+/- 20V
VGS(Th) max=2.5V
1
2
2
2
JUMP_43X79
@
Rds Max=5.5m @VGS=10V
Rds Max=7.5m @VGS=4.5V
+V1.05DX_MODPHY
+V1.05A
+1.05VS_MODPHY
+1.05V
short@
R570
1
2
0_0805_5%
CPU +V1.05DX_MODPHY
Max Rdson & lt; 6m ohm
1840mA
3
3
AO4430L
VGS Max=+/- 20V
VGS(Th) max=2.5V
Rds Max=5.5m @VGS=10V
Rds Max=7.5m @VGS=4.5V
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/06/29
2011/06/29
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DC Interface
Rev
0.1
LA-A992P
Date:
A
B
C
D
Sheet
Thursday, March 20, 2014
E
40
of
54
5
4
3
2
1
NGFF and WLAN
D
D
+3VS_WLAN
2
+3VS
1
WAKE#
3
S
& lt; 8 & gt; WAKE#
D
1
2
G
@
RL25
100K_0402_5%
MC_WAKE#
MC_WAKE# & lt; 21 & gt;
@
QB8
2N7002H_SOT23-3
PV# 2013.01.23 Add QB8 abd RL25 to support OBFF
PV# 2013.02.22 Unpop QB4 and RL23 for not support OBFF
C
C
B
B
A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Issued Date
Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
WAKE and RST-1
Rev
0.1
LA-A992P
Date:
5
4
3
2
Thursday, March 20, 2014
Sheet
1
41
of
54
B
C
Q30
AO3413L_SOT23-3
+3VALW
1
+3VALW
E
+3V_PCH
1
1
20mils
2
G
S
3
D
D
A
2
1
R559
100K_0402_5%
C590
1U_0402_6.3V6K
S
2
G
1
Q31
2N7002_SOT23-3
@
2
C591
0.1U_0402_16V7K
1
& lt; 30 & gt; PCH_PWR_EN
D
3
1
2
2
2
3
3
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/06/29
2011/06/29
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DC DC Device-1
Rev
0.1
LA-A992P
Date:
A
B
C
D
Sheet
Thursday, March 20, 2014
E
42
of
54
5
4
CMSRC
2
1
ACDRV
ACFET
3
RBFET
B+
DC IN
D
D
+3VALWP
RT8243
Jumper +3VALW
SY8003 UMA only
+1.5VSP
Charger
BQ24738
Jumper
+1.5VS
SUSP#
+5VALWP
EN
Jumper +5VALW
EC_ON
EN
BATDRV
+1.35V_VDDQP Jumper +1.35V_VDDQ
RT8207M
Battery
RBFET
BATT
+0.6V_0.675VSP
+0.6V_0.675VS
Jumper
SYSON
SUSP#
EN
C
C
SY8208D
+1.05VSP
Jumper
+1.05VS
SUSP#
EN
TPS51622
+VCC_CORE
VR12.5_VR_ON
EN
B
B
RT8813
DIS only
+VGA_CORE
GPU_PWR_EN
EN
SY8208D DIS only
+1.5VDIS
Jumper
+1.5VS
SUSP#
EN
A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/08/07
Issued Date
Deciphered Date
2016/08/06
Title
Power Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Document Number
Rev
0.4
LA-A992P
Thursday, March 20, 2014
Sheet
1
43
of
55
5
4
3
PL1 EMI@
HCB2012KF-121T50_0805
1
2
ADPIN
2
VIN
1
2
2
1
EMI@ PC4
1000P_0402_50V7K
1
2
D
PR3
100K_0402_5%
PR1
10K_0402_5%
2
ADP_ID & lt; 30 & gt;
1
& lt; 30 & gt; BAT_CHG_LED
PR8
100K_0402_5%
2
1
2
1
2
PR5
2K_0402_5%
1
2 Charge_LED
PC6
1000P_0402_50V7K
ESD@ PD2
L30ESD24VC3-2_SOT23-3
PR7
10K_0402_5%
1
2
1
1
ESD@ PD1
L30ESD24VC3-2_SOT23-3
@ PR2
0_0402_5%
1
2ACIN_LED
& lt; 30 & gt; AC_LED#
3
2
2
3
ADP_SIGNAL1
EMI@ PC3
100P_0402_50V8J
ACIN_LED
1
1
7
@ PC5
100P_0402_50V8J
7
ADP_SIGNAL
1
5
8
5
@ PD3
GLZ3.6B_LL34-2
6
8
3
2
Charge_LED
3
2
4
6
EMI@ PC2
1000P_0402_50V7K
4
2
D
EMI@ PC1
100P_0402_50V8J
PL2 EMI@
HCB2012KF-121T50_0805
1
2
@ PJP1
ACES_59012-0080N-002
2
1
2
1
1
+5VS
+3VALW
C
1
1
C
2
4
@
1
3
@
PR12
54.9K_0402_1%
2
P
2
@
PR13
1.5M_0402_5%
2
2
@
PD4
CD4148WN-1_1206-2
+
O
1
1
8
1
1
PQ2A
L2N7002DW1T1G_SC88-6
2
@
PR11
10K_0402_1%
PU1A
LM393DR_SO8
2
PC9
100P_0402_50V8J
2
1
6
@
PC8
0.022U_0402_16V7K
1
2
G
@
PR10
47K_0402_1%
& lt; 30,4 & gt; PROCHOT#
B/I# & lt; 30,45 & gt;
+5VS
ADP_I & lt; 30,46 & gt;
+3VALW_EC
1
2
ECAGND & lt; 30 & gt;
1
1
PR27
10K_0402_1%
@ PR28
10K_0402_1%
2
2
1
1
PH1
100K_0402_1%_NCP15WF104F03RC
VCIN1_PH & lt; 30 & gt;
2
2
1
VCIN0_PH & lt; 30 & gt;
2
2
PR21
100K_0402_1%
2
4
5
6
@ PC15
0.1U_0402_16V7K
-
1
+
O
B
PR26
5.9K_0402_1%
PR25
10K_0402_1%
2
7
PR18
10K_0402_1%
PC13
100P_0402_50V8J
2
1
P
1
PR20
1.5M_0402_5%
2
2
PD5
CD4148WN-1_1206-2
PU1B
LM393DR_SO8
G
PC12
0.022U_0402_16V7K
1
2
4
1
PQ2B
L2N7002DW1T1G_SC88-6
5
8
2
3
PR17
47K_0402_1%
@ PC16
0.1U_0402_16V7K
B
1
1
1
+3VALW
H_PROCHOT#_EC & lt; 30 & gt;
ACIN & lt; 30,45,46,8 & gt;
A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/08/07
Issued Date
Deciphered Date
2016/08/06
Title
DC Conn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Document Number
Rev
0.4
LA-A992P
Thursday, March 20, 2014
Sheet
1
44
of
55
5
4
3
2
1
@ PJPB2
1
BATT++
EMI@ PC11
0.01U_0402_25V7K
@ PR14
470K_0402_5%
1
2
1
2
PQ3A @
L2N7002DW1T1G_SC88-6
2
+3VL
1
1
EC_SMB_CK1 & lt; 28,30,46 & gt;
PR23 @
220K_0402_5%
+3VL
1
5 @
PQ3B
L2N7002DW1T1G_SC88-6
C
+3VL
PR24 @
220K_0402_5%
6
4
3
2
2
3
B/I# & lt; 30,44 & gt;
PC14 @
100P_0402_50V8J
4
2
ESD@ PD7
L30ESD24VC3-2_SOT23-3
1
1
ESD@ PD6
L30ESD24VC3-2_SOT23-3
1
1
3
PQ4A
@
L2N7002DW1T1G_SC88-6
2
2
PR29
100K_0402_5%
1
2
2
C
EC_SMB_DA1 & lt; 28,30,46 & gt;
PR22
100_0402_5%
1
2
3
PR30
100_0402_5%
2
1
OCTEK_BTJ-08FUAB
PR16 @
4.7K_0402_5%
6 2
PR15 @
470K_0402_5%
PR19
100_0402_5%
1
2
D
BATT
1
1
EMI@ PC10
1000P_0402_50V7K
2
PQ1 @
SI4483ADY-T1-GE3_SO8
1
8
2
7
3
6
5
2
1
1
2
3
4
5
6
7
8
9
10
2
1
2
3
4
5
6
7
8
GND
GND
2
BATT+
EMI@ PL4
HCB2012KF-121T50_0805
1
2
@ PJPB1
1
JUMP_43X118
4
D
EMI@ PL3
HCB2012KF-121T50_0805
1
2
5
ACIN & lt; 30,44,46,8 & gt;
PQ4B @
L2N7002DW1T1G_SC88-6
AC_AND_CHAG & lt; 30 & gt;
Need to define " AC_AND_CHAG " signal with EC
B
B
A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/08/07
Issued Date
Deciphered Date
2016/08/06
Title
BATT Conn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Document Number
Rev
0.4
LA-A992P
Thursday, March 20, 2014
Sheet
1
45
of
55
1
B
PR101
D
S
2
G
1
C
D
3
A
PQ102
2N7002KW_SOT323-3
PR102
2
1
1M_0402_5%
2
3M_0402_5%
1
1
REGN_CHG
SRN_CHG
1
2
PC107
0.01U_0402_50V7K
1
PC115
10U_0805_25V6K
2
1
PC114
10U_0805_25V6K
2
1
RB551V-30_SOD323-2
2
PD103
PC116
0.1U_0402_25V6
CSON1
3
1
1
CSOP1
2
2
CHG
2
1
2
PC118
0.1U_0603_16V7K
2
2
PR110
0.01_1206_1%
1
4
ILIM
BATDRV_CHG
1
+3VL
PC119
0.01U_0402_25V7K
2
3
2
1
ILIM_CHG
10
SCL
SDA
11
CSON1
SRP_CHG
PR115
357K_0402_1%
1
2
PR116
100K_0402_1%
7
PR117
422K_0402_1%
VIN
9
6
ACDET_CHG
3
IOUT_CHG
ACDET
BATDRV
12
CSOP1
PR113
0_0603_5%
1
2
1SNB_CHG 2
PR112
0_0603_1%
1
2
@EMI@ PR111
4.7_1206_5%
3
2
1
5
SRN
13
4
DL_CHG
3
2
1
15
14
1
SRP
ACDRV
& lt; 30,44,45,8 & gt; ACIN
1
PQ106
AON7506_DFN33-8-5
GND
CMSRC
ACPRES
PL102
4.7UH_ETQP3W4R7WFN_5.5A_20%
LX_CHG
ACP
8
4
5
1
4
BATT
LODRV
IOUT
ACDRV_CHG
PR114
10K_0402_1%
1
2
PQ105
AON7408L_DFN8-5
4
2
BTST
ACN
@ PR107
0_0603_5%
1
2
PC112
1U_0603_25V6K
1
2
BQ24738RGRR_QFN20_3P5X3P5
CMSRC_CHG 3
2
1
16
5
2
BST_CHG
17
1
PR106
2.2_0603_5%
2
1
DH_CHG
18
PR105
10_1206_1%
LX_CHG
19
DH_CHG
REGN
2
HIDRV
ACP_CHG
PAD
PHASE
1
PD102
RB751V-40_SOD323-2
@EMI@ PC117
680P_0603_50V8J
1
ACN_CHG
VCC
21
2
VCC_CHG
1
PC110
0.047U_0402_25V7K
1
2
20
2
1
PC108
0.1U_0402_25V6
2
1
1
2
PU101
+3VL
PR104
4.12K_0603_1%
2 BATDRV1_CHG
BATDRV_CHG 1
PD101
BAS40CW_SOT323-3
PC111
1U_0603_25V6K
1
2
PR109
4.12K_0603_1%
1
2
2
PQ104
AON7506_DFN33-8-5
1
2
5
3
PC105
10U_0805_25V6K
2
PC106
0.1U_0402_25V6
2
3
2
2
VIN
1
1
3
1
EMI@ PL101
1.2UH_NRS4018T1R2NDGJ_2.6A_30%
1
2
PC104
10U_0805_25V6K
2
5
PR103
0.01_1206_1%
4
4
1
2
PC102
0.1U_0402_25V6
4
1
1
2
3
ACDRV1_CHG
PR108
4.12K_0603_1%
2
1
5
PC101
2200P_0402_50V7K
PQ103
AON7506_DFN33-8-5
1
2
3
2
PQ101
AON6414AL_DFN8-5
B+
PC113
0.1U_0402_25V6
P2
@EMI@ PC123
2200P_0402_50V7K
P1
PC109
0.1U_0402_25V6
VIN
Vin Dectector
ADP_I & lt; 30,44 & gt;
1
PC121
100P_0402_50V8J
2
1
1
2
EC_SMB_DA1 & lt; 28,30,45 & gt;
@ PR119
0_0402_5%
1
2
2
ILIM and external DPM
3.61A
PR118
66.5K_0402_1%
EC_SMB_CK1 & lt; 28,30,45 & gt;
Max.
1
Typ
17.23V
17.63V
2
H-- & gt; L
L-- & gt; H
PC120
0.1U_0402_25V6
Min.
@ PC122
0.1U_0402_10V7K
locate the RC Near EC chip
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/08/07
Deciphered Date
2016/08/06
Title
CHARGER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
0.4
LA‐A992P
Date:
A
B
C
Sheet
D
46
of
55
A
B
C
D
PR302
165K_0402_1%
1
2
PR303
56K_0402_1%
1
2
1
PR301
14K_0402_1%
1
2
5
9
PHASE2
18
DH_5V
17
LX_5V
16
4
LG_5V
PQ302
AON7408L_DFN8-5
@EMI@ PR312
4.7_1206_5%
1
3
2
1
+3VL
SNUB_5V 2
+3VLP
+5VLP
1
(100mA,40mils ,Via NO.= 2)
+5VALWP
1
+
2
PC310
4.7U_0603_10V6K
2
1
2
+3VLP
@ PJ301
JUMP_43X39
1
2
1
2
PC314
1U_0603_10V6K
1
2
PR314
100K_0402_1%
1
PC313
0.1U_0603_25V7K
PR313
499K_0402_1%
1
2
1
PU301
RT8243AZQW_WQFN20_3X3
4
3/5V_B+
PL302
2.2UH_ETQP3W2R2WFN_8.5A_20%
1
2
2
LGATE1
2
@EMI@ PC312
680P_0603_50V8J
LDO5
ENM
ENLDO
LDO3
15
4
14
11
PQ303
AON7506_DFN33-8-5
13
LGATE2
12
10
VIN
5
PR310
PC306
2.2_0402_1%
0.1U_0402_10V7K
1
2 BST1_5V 1
2
BST_5V
PQ304
AON7506_DFN33-8-5
1
2
3
LG_3V
2
PR315
2.2K_0402_1%
1
2
& lt; 30 & gt; EC_ON
3
@ PR316
0_0402_5%
1
2
@ PJ304
JUMP_43X39
1
2
1
2
+VL
@ PR317
100K_0402_5%
2
1
1
(100mA,40mils ,Via NO.= 2)
PC309
4.7U_0603_10V6K
2
2
1
& lt; 30 & gt; MAINPWON
@ PC315
4.7U_0603_6.3V6K
3
UGATE2
PHASE1
1
2
3
1
SNUB_3V 2
1
@EMI@ PR311
4.7_1206_5%
LX_3V
2
2
8
UGATE1
@EMI@ PC311
680P_0603_50V8J
+
PC316
220U_C6_6.3V_M_R15
1
DH_3V
20
19
PC317
220U_C6_6.3V_M_R15
BOOT1
+3VALWP
1
FB_5V
FB1
BOOT2
3
2
1
7
PAD
BYP1
2
PL303
3.3UH_PCMB063T-3R3MS_6.5A_20%
1
2
@
21
5
BST_3V
PGOOD
TON
6
PC305
PR309
0.1U_0402_10V7K
2.2_0402_1%
1
2 BST1_3V 1
2
ENTRIP1
4
FB2
PQ301
AON7408L_DFN8-5
ENTRIP2
5
& lt; 8 & gt; SPOK
2
ENTRIP_5V
2
1
1
TON_35V
2
ENTRIP_3V
4
2
@
3
PR318
10K_0402_1%
PC304
10U_0805_25V6K
FB_3V
PR307
19.1K_0402_1%
1
2
5
1
PC307
4.7U_0805_25V6-K
1
PC303
10U_0805_25V6K
2
1
PR306
20K_0402_1%
1
2
PC308
4.7U_0805_25V6-K
3/5V_B+
+3VALW
2
1
2
PR305
30K_0402_1%
1
2
3/5V_B+
EMI@ PL301
HCB2012KF-121T50_0805
1
2
@EMI@ PC318
2200P_0402_50V7K
B+
1
PR304
143K_0402_1%
1
2
@ PC302
100P_0402_50V8J
1
2
@ PJ302
+3VALWP
1
1
2
2
+3VALW
JUMP_43X118
@ PJ303
+5VALWP
1
1
2
2
+5VALW
JUMP_43X118
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/08/07
Deciphered Date
2016/08/06
Title
3VALW/5VALW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
0.4
LA‐A992P
Date:
A
B
C
Sheet
D
47
of
55
5
EMI@
PLM1
HCB2012KF-121T50_0805
1
2
1
PRM1
2.2_0402_1%
1
2
D
1
1
@EMI@
PCM13
2200P_0402_50V7K
2
PCM2
0.22U_0402_10V6K
1
2
BST_DDR-1
PCM1
10U_0805_25V6K
PCM3
4.7U_0805_25V6-K
+1.35V_VDDQP
+0.6V_0.675VSP
1
PCM5
10U_0805_6.3V6K
2
21
2
1
VTT
20
19
1
2
3
4
VTTREF_DDRT
C
+1.35V_VDDQP
1
5
PCM10
0.033U_0402_16V7K
7
6
S3_DDR
FB_DDR
PRM5
8.06K_0402_1%
1
2
+1.35V_VDDQP
1
8
10
S5_DDR
2
FB
S3
PCM9
1U_0603_10V6K
VDDQ
S5
VDD
VTTREF
TON
PCM8
1U_0603_10V6K
VLDOIN
VDDP
GND
TON_DDR
2
11
VTTSNS
PUM1
RT8207PGQW_WQFN20_3X3
1
VDD_DDR
PGND
CS
PAD
VTTGND
9
12
+5VALW
2
1
2
3
+5VALW
@EMI@
PCM7
680P_0603_50V7K
PRM4
5.1_0603_5%
1
2
1
2
2
1SNB_DDR
1
2
PCM26
22U_0603_6.3V6M
1
PCM21
22U_0603_6.3V6M
2
1
PCM22
22U_0603_6.3V6M
2
1
2
PCM23
22U_0603_6.3V6M
PCM24
22U_0603_6.3V6M
1
PCM25
22U_0603_6.3V6M
2
1
2
4
PQM2
AON7506_DFN33-8-5
13
LGATE
PGOOD
PRM3
13.3K_0402_1%
1
2
CS_DDR
@EMI@
PRM2
4.7_1206_5%
C
15
14
5
1
+1.35V_VDDQP
DL_DDR
PCM4
10U_0805_6.3V6K
BST_DDR
18
PHASE
1
2
3
PLM2
1.5UH_PCMC063T-1R5MN_9A_20%
1
2
BOOT
DH_DDR
17
4
PQM1
AON7408L_DFN8-5
UGATE
LX_DDR
16
5
2
2
1
D
3
B+_DDR
2
B+
4
B+_DDR
2
PRM8
10K_0402_1%
PRM6
432K_0402_1%
1
2
@ PRM9
0_0402_5%
1
2
B
& lt; 30,40 & gt; SYSON
@ PJPM2
+1.35V_VDDQP
2
1
2
@
PCM11
0.1U_0402_10V7K
1
@ PRM11
0_0402_5%
1
2
& lt; 30,40,49,52,55 & gt; SUSP#
+0.6V_0.675VSP
@
PCM12
0.1U_0402_10V7K
1
1
2
2
B
+1.35V_VDDQ
JUMP_43X118
@ PJPM1
JUMP_43X39
1
2
1
2
+0.6V_0.675VS
A
A
Compal Secret Data
Security Classification
Issued Date
2013/08/07
Deciphered Date
2016/08/06
Title
Compal Electronics, Inc.
1.35V/0.675VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Thursday, March 20, 2014
Date:
Rev
0.4
LA-A992P
5
4
3
2
Sheet
1
48
of
55
5
4
3
2
1
D
D
EN pin don't floating
If have pull down resistor at HW side, pls delete PR2
@ PRH1
0_0402_5%
1
2
1
1
SUSP# & lt; 30,40,48,52,55 & gt;
@ PCH1
0.22U_0402_10V6K
2
2
PRH2
1M_0402_1%
2
1
2
PCH11
22U_0805_6.3VAM
1
2
1
2
+3VALW
PCH10
22U_0805_6.3VAM
LDO_3V
PCH7
330P_0402_50V7K
7
5
2
LDO
PRH5
100K_0402_1%
C
1
BYP
PG
1
ILMT
1
2
FB_1.05V
PCH13
4.7U_0603_6.3V6K
ILMT_1.05V 3
PRH6
10K_0402_5%
1
2
4
2
FB
+1.05VS
@ PJH1
JUMP_43X118
1
2
1
2
1
10 LX_1.05V
+1.05VSP
PLH2
1UH_PCMB063T-1R0MS_12A_20%
1
2
2
LX
PCH3
0.1U_0603_25V7K
1
2
BST_1.05Vn
PCH9
47U_0805_6.3V6M
GND
@ PRH4
0_0603_5%
2
BST_1.05V 1
1
9
6
1
BS
2
PUH1
SY8206DQNC_QFN10_3X3
1
IN
EN
PCH8
47U_0805_6.3V6M
8
@EMI@
@EMI@
PRH3
PCH2
4.7_1206_5%
680P_0603_50V7K
1
2 SNB_1.05V
1
2
PCH12
4.7U_0603_6.3V6K
1
2
PCH6
10U_0805_25V6K
1
+3VS
PCH5
10U_0805_25V6K
C
2
2
1
B+_1.05V
EMI@ PCH4
2200P_0402_50V7K
B+
EMI@
PLH1
HCB2012KF-121T50_0805
1
2
PRH7
133K_0402_1%
2
& lt; 30 & gt; +1.05V_VS_PG_PWR
Pin 7 BYP is for CS.
Common NB can delete
+3VALW and PC15
continuous 6A
peak 12A
1
+3VALW
PRH8 @
0_0402_5%
B
2
B
1
ILMT_1.05V
2
PRH9 @0@
0_0402_5%
The current limit is set to 8A, 12A or 16A when this pin
is pull low, floating or pull high
A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/08/07
Issued Date
Deciphered Date
2016/08/06
Title
1.05V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Document Number
Rev
0.4
LA-A992P
Thursday, March 20, 2014
Sheet
1
49
of
55
PCZ7
33U_25V_M
PCZ6
10U_0805_25V6K
PCZ11
10U_0805_25V6K
2
1
PCZ10
10U_0805_25V6K
2
1
1
1
PCZ5
10U_0805_25V6K
2
1
2
2
D
2
4
PCZ15
1U_0603_10V6K
1
PWM1
@
PRZ16
0_0402_5%
VGATE & lt; 11 & gt;
SKIP
1
2
PCZ18
1U_0402_6.3V6K
1
33
PAD
1
VR_SVID_DAT
PRZ22
10K_0402_1%
2
PRZ23
2.43K_0402_1%
1
2
2
3
1
PUZ2
CSD97374CQ4M_SON8_3P5X4P5
PCZ17
0.15U_0402_10V6K
CSN1
2
1
1
SKIP#
PCZ16
0.22U_0402_10V6K
VDD
PWM
+VCC_CORE
3
2
BOOT
2
+5VS
PHZ2
10K_0402_1%_TSM0A103F34D1RZ
8
3
PRZ17
3K_0402_1%
1 2
1
PWM2
7
BOOT_R PGND1
4
PRZ18
12.1K_0402_1%
2
1
5
2
PCZ14
.1U_0402_16V7K
VSW
1
PWM1
PGND2
2
SKIP
6
VIN
2
1
7
PRZ21
1_0402_5%
2
1
O-USR
F-IMAX
ALERT#
VCLK
32
31
VDIO
VR12.5_VR_ON & lt; 11 & gt;
6
C
@
CSP1
NTC
B value=3435 K
2
VR_SVID_ALRT#
PRZ24
4.87K_0402_1%
1
2
2@
PLZ2
0.15UH_ETQP4LR15AFM_29A_20%
1
4
9
9
10
11
B-RAMP
OCP-I
GND
VR_HOT#
30
VFB
VDD
8
@EMI@
PCZ20
680P_0402_50V7K
1
2
+3VS
@EMI@
PRZ26
4.7_1206_5%
1
2
VREF
CPU_B+
@ PLZ3
0.15UH_ETQP4LR15AFM_29A_20%
1
4
9
SKIP
@
@ PRZ35
1.82K_0402_1%
1
2
@
@
1
@
PCZ28
0.15U_0402_10V6K
@
PCZ25
1U_0603_10V6K
2
1
PRZ34
130_0402_1%
2
1
PWM2
@
PRZ30
0_0402_5%
VR_SVID_CLK
& lt; 11 & gt; VR_SVID_CLK
@
CSP2
VR_SVID_ALRT#
& lt; 11 & gt; VR_SVID_ALRT#
VR_SVID_DAT
& lt; 11 & gt; VR_SVID_DAT
VR_HOT#
2
@ PCZ29
47P_0402_50V8J
1
& lt; 30 & gt; VR_HOT#
PRZ33
54.9_0402_1%
2
1
2
PCZ26
.1U_0402_16V7K
B
CSN2
1
1
PCZ27
0.22U_0402_10V6K
SKIP#
2
2
VDD
+VCC_CORE
3
PHZ3
10K_0402_1%_TSM0A103F34D1RZ
PWM
2
+5VS
2
BOOT
3
PRZ31
2.43K_0402_1%
1 2
1
8
BOOT_R PGND1
4
PRZ32
36K_0402_1%
2
1
7
VSW
@ PUZ3
CSD97374CQ4M_SON8_3P5X4P5
1
PCZ24
1U_0603_10V6K
2
@ PCZ23
.1U_0402_16V7K
PGND2
1
1
+1.05VS_VCCST
6
VIN
2
PRZ29
10_0603_1%
1
2
5
2
@ PRZ28
2.2_0402_1%
1
2
1
+5VS
12
14
GFB
PRZ27
PCZ21
4.87K_0402_1% 4700P_0402_25V7K
1
2
1
2
PCZ22
0.33U_0402_10V6K
B
IMON
PGOOD
VR_SVID_CLK
PRZ25
10K_0402_1%
1
2
PWM3
CSN3
VR_HOT#
@ PCZ19
100P_0402_50V8J
1
2
THERM
TPS51624RSM_QFN32_4X4
CSP3
29
0_0402_5%
PRZ20
PWM2
25
@
CSP2
V5A
24
PWM1
VREF
23
VFB
2
SKIP#
CSN2
28
& lt; 11 & gt; VCCSENSE
GFB
1
CSN1
27
& lt; 13 & gt; VSSSENSE
22
@ PRZ19
0_0402_5%
1
2
VR_ON
5
PRZ14
2.2_0402_1%
1
2
1
21
+3VS
@
+
B+
CPU_B+
2
20
@
+
1
EMI@
EMI@
PCZ13
PRZ13
680P_0402_50V7K 4.7_1206_5%
1
2
1
2
F-IMAX
2
CSP2
13
15
16
VBAT
SLEWA
19
COMP
C
18
CSN2
CSP1
DROOP
CSN1
PRZ15
0_0402_5%
1
2
17
26
CSP1
2
68P_0402_50V8J
RF@
PCZ4
1
2
0.1U_0402_25V6
EMI@
PCZ2
2
1
2200P_0402_50V7K
EMI@
PCZ3
1
2
150K_0402_1%
1
PRZ11
2
1
PRZ10
2
100K_0402_1%
2
PRZ9
150K_0402_1%
1
1
2
PRZ8
39K_0402_1%
@
1
PCZ8
100U_25V_M
EMI@ PLZ1
HCB2012KF-121T50_0805
1
2
O-USR
PUZ1
1
CPU_B+
PCZ9
4.7U_0805_25V6-K
1
2
9.31K_0402_1%
PRZ5
2
1
PRZ4
2
680K_0402_1%
1
100K_0402_1%
PRZ3
@
2
2
PRZ2
1
332K_0402_1%
4700P_0402_16V7K
1
SLEWA
B-RAM
PRZ12
10K_0402_1%
1
2
CPU_B+
PRZ7
9.09K_0402_1%
2
1
2
PRZ6
39K_0402_1%
OCP-I
D
2
PHZ1
1
2
2
1
@ PRZ1
10K_0402_1%
3
PCZ12
.001U_0402_50V7-M
2
1
1
VREF
PCZ1
4
100K_0402_1%_NCP15WF104F03RC
5
A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/08/07
Issued Date
Deciphered Date
2016/08/06
Title
CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Document Number
Rev
0.4
LA-A992P
Thursday, March 20, 2014
Sheet
1
50
of
55
5
4
3
2
1
2
1
+
2
PCZ70
220U_D2 SX_2VY_R9M
@
1
PCZ59
22U_0603_6.3V6M
1
PCZ58
22U_0603_6.3V6M
2
1
1
1
PCZ57
22U_0603_6.3V6M
@
2
@
PCZ56
22U_0603_6.3V6M
2@
2
2@
PCZ55
22U_0603_6.3V6M
2@
1
2
1
PCZ54
22U_0603_6.3V6M
2@
1
PCZ53
22U_0603_6.3V6M
@
1
PCZ52
22U_0603_6.3V6M
2
1
D
PCZ51
22U_0603_6.3V6M
PCZ50
22U_0603_6.3V6M
+VCC_CORE
D
@
1
2
PCZ69
22U_0603_6.3V6M
1
PCZ68
22U_0603_6.3V6M
@
2
1
PCZ67
22U_0603_6.3V6M
2
1
PCZ66
22U_0603_6.3V6M
2
PCZ65
22U_0603_6.3V6M
1
2
1
PCZ64
22U_0603_6.3V6M
@
2
1
PCZ63
22U_0603_6.3V6M
2@
2
2
1
PCZ62
22U_0603_6.3V6M
2
1
PCZ61
2.2U_0402_10V6M
1
PCZ60
22U_0603_6.3V6M
acoustic noise
acoustic noise
C
C
B
B
A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/08/07
Issued Date
Deciphered Date
2016/08/06
Title
PROCESSOR DECOUPLING
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Document Number
Rev
0.4
LA-A992P
Thursday, March 20, 2014
Sheet
1
51
of
55
A
B
C
D
@UMA@
PR1502
0_0402_5%
1
2
1
1
SUSP# & lt; 30,40,48,49,55 & gt;
2
1
@EMIUMA@
PR1504
4.7_0603_5%
SY8003DFC_DFN8_2X2
UMA@
PR1505
30.1K_0402_1%
UMA@
PC1503
68P_0402_50V8J
UMA@
PC1504
22U_0805_6.3VAM
1
NC
LX_1.5V
2
PGND
6
5
1
LX
+1.5VSP
UMA@
PL1501
1UH_PH041H-1R0MS_3.8A_20%
1
2
EN_1.5V
2
IN
7
1
UMA@
PC1501
22U_0805_6.3VAM
EN
2
4
PG
9
8
@
PJ1502
JUMP_43X79
1
2
1
2
+1.5VS
1
3
1
UMA@
PC1505
22U_0805_6.3VAM
@EMIUMA@
PC1506
680P_0402_50V7K
UMA@
PR1506
20K_0402_1%
continuous 3A
2
2
1
1
2
VIN_1.5V
PGND
SGND
1
2
FB
2
2
1
+3VALW
@
PJ1501
JUMP_43X79
1
2
1
2
1
UMA@
PR1503
1M_0402_5%
2
UMA@
PU1501
FB_1.5V
@UMA@
PC1502
.1U_0402_16V7K
2
2
3
3
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/08/07
Deciphered Date
2016/08/06
Title
1.5VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
Document Number
Rev
0.4
LA-A992P
Sheet
Thursday, March 20, 2014
D
52
of
55
5
4
3
2
1
D
D
@VGA@
PRV1
1K_0402_5%
1
2
+3VGS
NVVDD_PWM_VID & lt; 32 & gt;
GPU_B+
2.4V to 5.5V
4
VGA@
PCV5
0.22U_0603_25V7K
1
2
U2_LGATE1
U2_PWM3 U2_PWM3
106.38C
110C
113.4C
2
3
2
1
3
2
1
3
2
1
2
1
VGA@
PRV25
100K_0402_1%
1
2
1
+
2
A
@EMIVGA@
PCV26
680P_0603_50V7K
Co-Lay
VGA@
PCV27
1U_0402_6.3V6K
Compal Secret Data
Security Classification
Issued Date
& lt; 30 & gt; GPU_HOT#
4
VGA@ PCV25
390U_2.5V_M
1
5
+5VS
U2_LGATE2
+3VS
+VGA_CORE
@EMIVGA@
PRV23
4.7_1206_5%
2
DGPU_PWROK & lt; 35 & gt;
VGA@
PQV4
MDU1511RH_POWERDFN56-8-5
4
2013/08/07
Deciphered Date
2016/08/06
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
VGA@ PCV19
100U_25V_M
1
1
2
VGA@ PCV22
10U_0805_25V6K
1
2
VGA@ PCV21
10U_0805_25V6K
1
2
5
EMIVGA@ PCV20
2200P_0402_50V7K
18
1
VGA@ PLV3
0.22UH_PCME064T-R22MS_28A_20%
1
2
VGA@
PRV24
2.2_0603_5%
1
2
103.1C
B
Co-Lay
VGA@
PQV3
SIR472DP-T1-GE3_POWERPAK8-5
U2_PHASE2
2
PRV21=13K
4
VGA@
PCV18
0.22U_0603_25V7K
1
2
1SNB_VGA22
1
2
VGA@
PHV1
470K_0402_5%_TSM0B474J4702RE
T_max
100C
@VGA@
PRV20
0_0603_5%
1
2
VGA@
PRV22
10K_0402_1%
2
T_typical
@EMIVGA@
PCV15
680P_0603_50V7K
+3VGS
3. Thermal monitoring:
(VGPU_VREF-VTSNS)/PRV21=VTSNS/Rth
T_min
+
2
GPU_B+
A
PRV21=18.7K 96.73C
2
1
Co-Lay
U2_UGATE2
1
1
VGA@
PCV23
1U_0402_6.3V6K
1
U2_PHASE2
VGA@
PRV19
2.2_0603_5%
2
U2_BOOT21
VGA@
PRV21
18.7K_0402_1%
2
2. Switching frequency setting:
Fsw=(Vin-0.5)/(2*Vin*Rton*3.2p)=448Khz
VGA@
PRV15
12.7K_0402_1%
Rocset
+VGA_CORE
+
1
U2_LGATE2
19
2
21
20
+VGA_CORE
EDP-Continuous 33.5A
EDP-Peak 51.5A
OCP 66A
@EMIVGA@
PRV14
4.7_1206_5%
1SNB_VGA12
23
22
VGA@
PQV2
MDU1511RH_POWERDFN56-8-5
4
U2_LGATE1
GPU_VREF
1. VSNS Soft-Start time (Internal) is 0.7ms (PCV17 un-pop)
Tss=(Css*Vrefin)/Iss+2.3ms
=0.01U*0.9V/5uA+2.3ms=4.1ms (PCV17 pop)
1
5
U2_PHASE1
U2_BOOT2
BOOT2
PHASE2
24
2
VGA@ PLV2
0.22UH_PCME064T-R22MS_28A_20%
1
2
1
BOOT1
2
3
EN
PSI
4
5
VID
UGATE1
UGATE2
PGOOD
17
+VGA_CORE
16
GPU_TSNS/ISEN3
VGA@
PRV18
100_0402_1%
1
2
U2_UGATE2
@VGA@
PCV17
0.01U_0402_16V7K
2 Css
GPU_PGOOD1
1
& lt; 34 & gt; VCCSENSE_VGA
SS
LAGTE2
VCC/ISNE1
12
REFADJ
6
GPU_COMP
VSNS
TALERT/ISEN2
1
2
11
GND/PWM3
VGA@
PUV1
RGND RT8813AGQW_WQFN24_4X4 PVCC
TSNS/ISEN3
GPU_FB
@VGA@
PCV16
47P_0402_50V8J
10
LGATE1
TON
15
GPU_FBRTN
PHASE1
VREF
GPU_DSBL/ISEN1
9
GND
8
GPU_TON
REFIN
14
GPU_VREF
B
@VGA@
PRV17
0_0402_5%
1
2
7
13
GPU_REFIN
25
@VGA@
PRV16
0_0402_5%
1
2
& lt; 35 & gt; VSSSENSE_VGA
VGA@
PRV13
340K_0402_1%
1
2
1 Rton
@VGA@
PCV14
0.01UF_0402_25V7K
2
GPU_HOT#
GPU_B+
2
1
2
Reserve Location
U2_PHASE1
VGA@
PRV12
100_0402_1%
1
2
+
C
VGA@ PCV10
390U_2.5V_M
1
2
U2_BOOT1
U2_BOOT1
@VGA@
PCV9
0.1U_0402_25V6
1
VGA@
PQV1
SIR472DP-T1-GE3_POWERPAK8-5
DGPU_PWR_EN & lt; 30,35,9 & gt;
VGA@
PRV7
2.2_0603_5%
1
2
B+
VGA@ PCV12
390U_2.5V_M
U2_UGATE1
VGA@ PCV6
10U_0805_25V6K
+3VGS
Pull high on HW side
2
5
@VGA@
PRV10
0_0603_5%
1
2
VGA@ PCV4
10U_0805_25V6K
EMIVGA@
PLV1
HCB2012KF-121T50_0805
1
2
1
VGA@ PRV9
1K_0402_5%
1
2
U2_UGATE1
VGA@
PRV11
1.74K_0402_1%
1
2
1.2V to 1.8V
Active phase with CCM
@VGA@ PRV27
1K_0402_5%
1
2
C
GPU_EN
2
@VGA@ PRV28
10K_0402_5%
1
2
GPU_VID
Rref2
VGA@
PRV8
6.2K_0402_1%
1
2
0V to 0.8V
1 phase with CCM
NVVDD_PSI & lt; 32 & gt;
VGA@
PCV8
5600P_0402_50V7K
GPU_FBRTN
@VGA@
PCV7
0.01U_0402_16V7K
1
2
1 phase with DEM
+3VGS
PSI Pull high on HW side
PSI Voltage setting
EMIVGA@ PCV3
2200P_0402_50V7K
VGA@
PRV5
27K_0402_1%
1
2
Rrefadj
1
@VGA@
PRV4
0_0402_5%
1
2
Rboot
Operation phase Number
@VGA@ PRV26
1K_0402_5%
1
2
@VGA@
PRV6
0_0402_5%
1
2
3
2
1
2
C
Rref1
VGA@
PRV3
7.5K_0402_1%
GPU_PSI
1
VGA@
PCV1
1U_0402_6.3V6K
GPU_REFADJ
2
1
@VGA@
PRV2
0_0402_5%
1
2
3
2
Compal Electronics, Inc.
VGA_CORE
Document Number
Rev
0.4
LA-A992P
Thursday, March 20, 2014
1
Sheet
53
of
55
A
B
C
D
E
+VGA_CORE
PLACE UNDER GPU
VGA@
PCV59
4.7U_0603_6.3V6M
1
2
1
1
2
VGA@
PCV54
4.7U_0603_6.3V6M
2
VGA@
PCV58
4.7U_0603_6.3V6M
1
1
2
VGA@
PCV53
4.7U_0603_6.3V6M
2
VGA@
PCV57
4.7U_0603_6.3V6M
1
VGA@
PCV52
4.7U_0603_6.3V6M
2
2
1
VGA@
PCV56
4.7U_0603_6.3V6M
2
2
1
2
VGA@
PCV51
4.7U_0603_6.3V6M
1
1
1
1
VGA@
PCV55
4.7U_0603_6.3V6M
VGA@
PCV60
4.7U_0603_6.3V6M
1
VGA@
PCV63
1U_0402_6.3V6K
2
1
VGA@
PCV62
1U_0402_6.3V6K
2
2
2
VGA@
PCV61
1U_0402_6.3V6K
1
2
1
2
VGA@
PCV64
1U_0402_6.3V6K
1
VGA@
PCV68
4.7U_0603_6.3V6K
2
1
VGA@
PCV67
4.7U_0603_6.3V6K
2
1
VGA@
PCV66
4.7U_0603_6.3V6K
2
1
VGA@
PCV65
4.7U_0603_6.3V6K
2
2
1
PLACE NEAR GPU
VGA@
PCV69
4.7U_0603_6.3V6K
2
2
VGA@
PCV70
22U_0603_6.3V6M
1
3
1
3
VGA@
PCV71
47U_0805_6.3V6M
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/08/07
Deciphered Date
2016/08/06
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
VGA CHIP DECOUPLING
Document Number
Rev
0.4
LA-A992P
Thursday, March 20, 2014
Sheet
E
54
of
55
5
4
3
@VGA@
PRW1
0_0402_5%
1
2
2
1
D
@VGA@
PCW1
0.01UF_0402_25V7K
2
VGA@
PRW2
1M_0402_1%
2
D
1
1
SUSP# & lt; 30,40,48,49,52 & gt;
IN
EN
BS
GND
LX
ILMT
BYP
PG
LDO
6
@VGA@
PRW4
0_0603_5%
2
BST_VRAMPWR 1
EN_VRAMPWR
VGA@
PCW5
0.1U_0603_25V7K
1
2
BST_VRAMPWRn
10 LX_VRAMPWR
+1.5VDIS
+1.5VS
@
PJW1
JUMP_43X118
1
2
1
2
VGA@
PLW2
1.5UH_PCMC063T-1R5MN_9A_20%
1
2
2
VGA@
PCW13
4.7U_0603_6.3V6K
1
VGA@
PCW10
22U_0805_6.3VAM
2
1
VGA@
PCW9
22U_0805_6.3VAM
2
1
2
1
2
VGA@
PCW8
22U_0805_6.3VAM
VGA@
PCW11
22U_0805_6.3VAM
VGA@
PCW12
4.7U_0603_6.3V6K
1
5
SY8206DQNC_QFN10_3X3
VGA@
PCW7
330P_0402_50V7K
2
+3VALW
2
VGA@
PRW5
30.1K_0402_1%
FB_VRAMPWR
1
2
4
7
2
FB
3
1
1
9
1
1
1
2
VGA@ PCW6
4.7U_0805_25V6-K
1
2
VGA@ PCW4
4.7U_0805_25V6-K
1
2
@EMIVGA@
@EMIVGA@
PRW3
PCW2
4.7_1206_5%
680P_0603_50V7K
1
2 SNB_VRAMPWR 1
2
VGA@
PUW1
B+_VRAMPWR 8
EMIVGA@ PCW3
2200P_0402_50V7K
B+
EMIVGA@
PLW1
HCB2012KF-121T50_0805
1
2
VGA@
PRW6
19.6K_0402_1%
C
2
C
continuous 6A
peak 12A
B
B
A
A
Compal Secret Data
Security Classification
Issued Date
2013/08/07
Deciphered Date
2016/08/06
Title
Compal Electronics, Inc.
VRAM Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Thursday, March 20, 2014
Date:
Rev
0.4
LA-A992P
5
4
3
2
Sheet
1
55
of
55