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SHARI=

TECHNICAL MANUAL
T09P3VC-A6 15X

(PkiL SYSTEM)
MODEL NO.

SERIES
VC-Al03

Series VC-A103R(BK),

VIDEO HEAD

Q(BK), GV(BK), VC-A106GVM(BK)

VC-A 116 Series

VC-Al 1 GS(BK), B, K, E, W, VC-B322N

VC-A 125 Series

VC-A 125X

VC-A215

Series

VCtA215SfBK)

VC-A118

Series VCLAI 18D

VC-A508

Series

VC-A615

VC-A615G(BK), S(BK), GMtBK), SM(BK), YM(BK), HM, X,
Series WT, NZ, VC-B377N, NT

VC-T620

Series

VC-TN623QMiBK)

VC-A215

Series

VC-A215H

2-head
system

VCLA508DT

Double
azimuth
4-head
system
2-head
LP systen

CONTENTS

f
1.
2.
3.
4.
5.
6.
7.
8.

MECHANISM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SERVO CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .._..........
SYSTEM CONTROLLER LSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMING CHART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMER CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AUTOMATIC VOLTAGE SYNTHESIZER CIRCUIT . . . . . . . . . . . . . . . . . . . . . .
Y/C CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SHARP CORPORATION

-Y
2
20
25
49
56
67
74
79

1. MECHANISM
OUTLINE
This VTR is a low-profile, shelf-mount type working on the VHS system. Many newly developed
mechanisms have been adopted to make this model thinner, more reliable and power-saving compared to the conventional models.
Main features include:
1) Use of a single-cam system which can cope with various modes
2) A newly developed thin capstan DD (Direct Drive) motor
3) Appropriate torques achieved by a geared reel drive system
4) Newly developed loading system fpr systemization of the cassette control and loading
mechanisms
CONFIGURATION
The mechanism of this model can be roughly divided into the following sections.
System sections
1) Tape drive train system
2) Loading mechanism
3) Cassette tape take-up mechanism
4) PAD (Power Assist Drive) mechanism
5) Cam switch
6) Cassette control mechanism
These sections are discussed one by one as follows.

1-1. Tape Drive Train System

Guide roller

Slant pole
Slant

p\

/-

Half-loading

Full erase
(FE1 head

lever

Si

Fixed guide
'--sion arm

Reverse guide

Capstan shaft
In-cassette ouide

In-cassette

guide

,'

,'

/'

#'

II
:
:
:

---______---

Figure l-l. Tape Travel System

Features
1) Miniaturized Si (Supply impedance) roller from 16 mm to 7. rr.3-n dia.; much smaller mechanism
realized.
2) Fixed erasing head; simple design.
3) Enlarged guide roller from 6 mm to 7 mm dia.; reduces the number of revolutions in highspeed video search operation.
4) Miniaturized pinch roller from 18 mm to 14 mm dia.; subcompact mechanism accomplished.
5) The reverse guide works in Video search O/S) and rewind (REW) modes only, reducing the
risk of tape damage.

l-2. Loading Mechanism

Loading motor

\Haster
cam
Figure l-7.. Loading Mechamism (Upper stage)

Features
1) The mechanism is driven by the loading motor.
2) The loading motor is intended to drive the mechanism and the cassette housing.
(Refer to the description on the clutch shifting mechanism on page 17.)
3) The four-cam system which used to control the operation of the whole transport mechanism
has been combined into a single master cam.

l-3. Cassette Tape Take-up Mechanism

Capstan DO motor

,/Fast forward (FF) rotation Y

\s"
pp,y
k!["

reel

disk

Reel pulley
-Figure 1-3. Cassette Tape Take-up Mechanism 1 (Lower stage)

Features
1) The reel disk to be driven by the idler assembly is switched by changing the rotational direction of the capstan DD motor.
2) The reel pulley and the idler assembly are always engaged with each other, and the rotation
of the capstan DD motor is transmitted through the reel belt to the supply or take-up reel
disk.
3) The idler assembly consists of a large and a small gear in a monoblock construction and
mounted in the mechanism to allow vertical slide operation.
4) Each reel disk incorporates a slip mechanism to take up the tape without any slack and at an
appropriate take-up torque in recording, playback and trick play operations. (large gear)

5

Switching
jever

Switching
lever

Idler gear

Reel
disk
---/

/

/---

Figure l-4. Gear Engagement in Fast
Foward and Rewind
Operations

disk

/
Idler

arm/

1
Reel pulley

Figure 1-5. Gear Engagement in Recording,
Playback and Trick Play
Operations

5) In the fast forward and rewind modes, the large idler gear engages with the small gear of the
reel disk, not through the torque limiter built in the reel disk. They work as a simple gear
mechanism to transfer the revolving motion to the reel disk. (Figure I-4.)
61 In the recording, playback and trick play modes, the idler arm moves to the lower position so
that the small idler gear engages with the large gear of the reel disk. In this case, the rotation
of the idler assembly is transmitted through the torque limiter built in the reel disk to the reel
disk. (Figure I-5.)

Half-loadino lever

In-cassette guide
guide

Video search brake

\Take-up reel disk

Supply main brake
Figure 1-6. Cassette Tape Take-up Mechanism 2 (Upper stage1
Fast forward operation

6

7) In fast forward and rewind operations, a back tension is provided by the fast forward brake
and video search brakes. (Figures 1-6. and l-7.)
8) The idler gear is positioned as shown in Figure 1-5. when tape loading is completed. The
limiter gear of the take-up reel disk then goes into an operating condition, and its sliding motion absorbs the change in tape diameter while the tape is being wound in order to compensate the reel' revolving speed. (Figures 1-5. and 1-8.)
s
9) In playback and recording operations, a back tension is provided by a combined force of the
tension band, tension arm and tension spring at the supply reel disk. (Figure l-8.!
IO) The back tension in the VS and REW modes is given by the video search brake for the take-up
reel disk. (Figure l-9.)

Half-loading lever
/

Video search brake

4\Take-up
- 1 /

\ & lt;

reel

disk

Figure 1-7. Cassette Tape Take-up Mechanism 3 (Upper stage)
Rewind operation

.11) In the VS and REW modes, the tension release lever slackens the tension band so that only
the brake of the back tension lever acts on the supply reel disk. (Figure l-9.)
12) The reverse guide works in the VS and REW modes in order to stabilize tape drive train during reverse running. (Figure I-9.)

~everre guide

Take-uD
supply reel

disk

Figure I-8. Cassette Tape Take-up Mechanism 4 (Upper stage)
Recording and playback opertions

Figure 1-9. Cassette Tape Take-up Mechanism 5 (Upper stage)
VS and REW operations

reel

disk

1-4. PAD (Power Assist Drive) Mechanism

1)

Master cam grooves
As shown in Figure '
I-IO., the single master cam has some grooves on its both sides to bring
the mechanism in various modes. The control levers are guided along these grooves. Precise
switching is also guaranteed with the interlocking of this cam and the cam switch.

Shifter PAD cam

Pinch PAD cam

Top view

Loading PAD cam

Bottom view

Figue l-10.

2)

Positional relation and
operation of loading gears
The loading gear S is aligned
with the loading gear T so that
the locating mark 1 (round
projection) of the former gear
engages with the notch on the
circumference of the latter gear.
See Fig. l-l 1.

Figure 1-I 1

Loading PAD (bottom view)
in Stop Mode
Loading gear S

Next, the locating mark 2 of the small gear of the loading gear T is aligned with the locating
mark 3 of the loading relay gear.
Figure 1-l 1. and Figure I-1 2. show the positional relation in Stop and Play mode, respectively.
Note the difference in the position of the relay gear drive lever with respect to the master cam
groove between two modes.
.-

Figure I-12. Loading PAD (bottom view1
in Play Mode
Loading gear S

9

3) Positional relation and operation of pinch roller lever
(other than in eject operation)

Pinch roller lever

Figure 1-13. Stop Mode (FF/REW)

Master cam

Master cam

Pinch roller
Forward rota

shaft7
Capstan

Pinch roller lever

Capstan shaft

Figure 1-14. Playback Mode

\Pinch roller lever

Figure l-15. Positioning in Pause Mode

When the pinch roller has been pressed against the capstan shaft the master cam rotates to the
position shown in Figure l-l 4. Then, the pinch pressure spring gives a necessary pressure (I ,000
- 1,200 g) to feed the tape.
Just before going to the video search rewind mode or at short rewind operation in the
RECIPAUSE mode, the master cam once rotates to the position shown in Figure 1-I 5. to slightly
release the pinch roller pressure; this is just to allow the capstan to feed the tape while the idler
assembly is shifting toward the supply reel disk. Then, it reverts to the position shown in Figure
l-l 4. and feeds the tape in the reverse direction to ensure stable tape reversing.

10

4) Operation of half-loading
lever
l

l

Half-loading
spr7ng

Half-loaidng
ieVer

reciprocating

The cassette is loaded in
the normal position only in
the FF and REW modes by the
master cam and released in
the other modes.
The half-loading lever is
always kept at a fixed
position by the half_
loading reciprocating
lever, half-loading
reciprocating spring and
half-loading drive lever.

!\,

reciprocating

Half-loading

lever spring

\\c/

la
Figure 1-16. Eject Mode

Half-loading
Half-loading

Half-loading

reciprocating

reciprocating

drive lever

Half-loading

lever spring

\'d
i

Figure 1-17. Stop Mode (FF/REW)

Half-loading

reciprocating

Half-loadlna

Half-loading
lever

reciprocating

drive leve

oading

Half-loading

lever

Figure I-18. Recording and Playback Modes

11

5) Operation of brake shifter
Master cam
The relay shifter transfers
the driving force of the
master cam to the brake
shifter to cause a linear
motion of the brake shifter as
shown in Figure l-l 9.
The brake shifter performs
the following operations:
l
Activation and Releasing of
the main brake
l
Vertical movement of the
idler lever
l
Activation and Releasing of
the fast forward brake
l
Activation and Releasing of
the back tension brake
l
Switching of the driving
force of the video search
brake
l
Releasing of the tension arm

Relay

shifter

Further, the relay shifter
performs activation and
releasing of the reverse
guide.

Brake

Overrun for attraction
of solenoid
I I I
Brake standby 1 Loading
pogtion
STOP
Loading

Figure l-l 9

12

position

1-5. Cam Switch

D-shaped cut
,

Figure I-20. Cam Switch Alignment

The cam switch is installed with its D-shaped cut aligned with the D-shaped cut of the master
cam. (The specially devised cam switch allows its alignment irrespective of the angle of rotation.)

Figure l-21 Structure of Cam Switch

The cam switch has an internal pattern as shown in Figure 1-21. and turns on the circuit at the
shaded sectors. The system controller determines the mode of the mechanism by detecting turning
on and off of the electric signal as the six shaded sectors make and break the circuit.

13

Released
Cassette controller
activated
/
/

Distance
traveled 0'
each lever

Released

Slow brake

I
I

T
- -:
:T'
---.A -----I:
\

/ Main brake attracted

---

\
-7%
\

Loadinq

\
t
\
w--y-.--- --;-,
\\,---- - ---_ -,I ____\
\----- --)
'
!
,
\
/'
,
\
J-/*(:;
\
L-J' \
\
\
r-I.
\
I
\
I
'
1
::
/
\
I

t
I
,

Clutch switched
ompleted

Ejectio

_1

Al/Half-loading
I
I
,
1

lever

Brake shifter

\-

Pinch roller pressurized

STOP (FF/REW & gt;

PLAY

VS-REW
360'

0'

Revolving angle of
master cam

Figure l-22. Relation between Cam Switch and Mechanism

Figure l-22. shows the relation between the cam switch position and the actions of the individual
components.

.-

14

1-6. Cassette Control Mechanism
1) Cassette controller drive mechanism

Figure l-23. Cassette Controller Drive Mechanism

Feature
The driving force of the loading motor is always transmitted to the pulley of the cassette controller by the cassette loading belt as shown in Figure l-23.

2) Configuration of cassette control mechanism

Elaster cam
Pinch reciprocating
lever

Pinch rol
Clutch
Clutch lever

,.

I

C,"tch ,ock ,e"er

II

Pinch roller lever

Figure

l-24. Relation between Pinch Roller Lever and
Cassette Controller

The master cam acts on the pinch roller while the latter is positioned within the range where the
pressurization of the pinch roller is not affected. The driving fclvce of the loading motor is transmitted to the worm through the pulley.

16

I-7. Clutch Shifting Mechamism

Coupling

Clutch

Worm shaft.

Worm
-

\

/

c
Cassette
unloading

0

lever

(Drive gear I R /

1 S,i,,, lever /
\c,utc,,

,ock\E:::'
h

re'ease

-13

Drive LlearR/

Coupling

Worm shaft

Norm
-

/

(2)

Switch lever/

Clutch

Worm shaft

Drive gear R

lever-1
Switch

Clutch lock lever

(31

\ Clutch lock lever

Figure l-25. Cluch Shifting Sequence during Cassette Unloading

17

lever

Worm

Worm shaft

/

Coupling

~$Pulley
Cassette
loading

Clutch lever
Pinch roller lever

Clutch release lever
Drive gear R/

Switch lever

ock lever

Worm shaft

roller lever

Drive near R J/
.

Wo t-m

(31
\L/

Switch lever /

\ Clutch lock lever

Coupling

Worm shaft

/

Pinch roller lever

Figure l-26. ( Xutch Shifting Seauence durina Cassette Loadina

18

1) Clutch Shifting Sequence during Cassette Unloading
The clutch is located as shown in Figure l-25.(1) when the cassette has been loaded. In this
condition the driving force of the pulley is not transmitted to the worm. As the pinch roller
lever moves in the direction of arrow (a), the clutch, clutch lock lever and clutch release lever
move in the directions (b), (c) and (d), respectively, bringing the positional relation in Figure
l-25.(2).
Now the driving force of the pulley is transmitted through the clutch and the coupling to the
worm, which starts the drive gear R to unload the cassette.
At this time, the clutch lock lever is released from the switch lever and then fixed to the
projection on the frame. By this the clutch is kept at a position even when the pinch roller
lever comes to the position shown in Figure l-25.13).
When the drive gear R roiXes to the position shown in Figure l-25.(3), the switch lever turns
on the switch and the motor stops. Now the cassette has been completely unloaded.
2) Clutch Shifting Sequence during Cassette Loading
Before a cassette is inserted, the clutch is positioned as shown in Figure l-26.(1 I, where \he
driving force of the pulley is transmitted to the worm through the coupling.
When the cassette is inserted in this condition, the drive gear R starts turning by the
reciprocating mechanism. Then the switch is released from the switch lever and the pulley
starts turning to move the cassette in the loading direction. When the mechanism reaches a
position just before completion of loading as shown in Figure l-26.(2), the drive gear R forces
the switch lever to rotate. Consequently, the clutch lock lever moves in the direction of arrow
(e), releasing the clutch and turning on the switch at a time. Now the mechanism has loaded
the cassette in position (Figure l-26.(3)). The pulley remains running idle, and even when the
loading motor is running, its force is not transmitted to the cassette controller.

19

2. SERVO CIRCUIT
Digital servo LSI (RH-IX0431GEZZ)
The digital servo LSI is of single-chip type and has the following functions.
l
Drum speed and phase control.
l
Capstan speed and phase control.
l
Gain control for recording speeds (SP/LP).
l
Automatic tape speed detection in playback mode.
* Head switching pulse generation in 1 PG system.
l
X-value compensation in double-azimuth 4-head fine slow motion.
l
Drum compensation and tracking shift in trick play mode (slow, still, frame advance, etc.).
l
Amplification of record control signaT
l Others.
Below discussed are the names and functions of the pins of RH-IX0431GEZZ.

Pin No.
1

Name

Input/Output

Function

vcc

Power input terminal for analog amplifier
(5 + 0.5V).

(for Analog circuit)
2

Bias (+I
WREF (+I)

Input

3

Bias (-1
WREF (-1)

output

Voltage follower output of the reference
voltage fed at bias ( + 1 (pin 0).
Bias voltage of each amplifier inside the
IC also connected to this pin.

4

Drum PG

Input

Negative drum phase generator pulse
input. Threshold voltage is -70 mVp-p
(TYP). Hysteresis is 60 mVp-p (TYP).
(Positive square wave generated by the
internal Schmitt amplifier)

Drum FG AMP

input

Inverted input for inversion C-MOS
amplifier of drum frequency generator.
Bias preset at pin @ connected to this
pin.

Drum FG AMP
output

output

Output termdnal for inversion C-MOS
amplifier of drum frequency generator.

Drum FG input

Input

Drum additional
AMP output

output

6

8

Drum additional
AMP negative input

Reference bias voltage (2.5 VI settomg
for analog amplifier and analog switch.
Internally connected to the voltage
follower input composed of C-MOS
amplifier. 2.5 V reference voltage fed.

Drum frequency generator Schmitt
amplifier input terminal. Threshold
voltage is 80 mVp-p (TYP).
Hysteresis is 80 mVp-p (TYP).
Additional amplifier output terminal for
drum rotational control (CMOS).

Input

Additional amplifier negative input
terminal for drum rotational control
(C-MOS).

20

Pin No.

Name

Input/Output

Function

10

Drum additional
AMP positive input

Input

Addtional amplifier positive input terminal
for drum rotational control (C-MOS).

11

Capstan FG input

input

Capstan frequency generator Schmitt
amplifier input terminal. Both thresho!d
voltage and hysteresis are 80 mVp-p
(TYP).

12

Capstan additional
AMP output -

output

Additional amplifier output terminal for
capstan rotational control (C-MOS).

13

Analog SW2

14

Capstan additional
AMP negative input

Input

Additional amplifier negative input
terminalfor capstan rotational control
(C-MOS).

15

Capstan additional
AMP positive input

input

Additional amplifier positive input terminal
for capstan rotational control (C-MOS).
(capstan speed and phase error voltages
fed in)

16

GND (for Digital
Circuit)

17

Drum phase error
output (drum AFC)

output

Drum phase error pulse width modulation
(PWM) output terminal. Output at PWM
repeated frequency fsc/26+ 69 kHz. PWM
duty stretched toward "
H" due to phase
delay.
l
Drum phase PWM output fixed at 50%
duty if the drum frequency generator
input frequency comes without about
2 5% of the specified frequency.

18

Drum speed error
output (drum AFC)

output

Drum speed error PWM output terminal.
O & put at PWM repeated frequency
fsc126+69 kHz. PWM duty stretched
toward "
H" due to speed (rpm) delay.

19

Capstan phase error
output (capstan APC)

output

Capstan phase error PWM output
terminal. Output at PWM repeated
frequency fsc/26 + 69 kHz.
PWM duty stretched toward "
H" due to
phase delay.

Built-in analog switch turns on at the
servo serial data D 18 = " 1" and off at
D18 = " . Internally connected with
0"
capstan additional amplifier output.td
control the additional amplifier gain and
to short-circuit the phase compensating
capacitor. Slow, still, FF/REW and capstan
stop modes brought on at D18 = " .
I"

Ground for digital signal processing.

Each capstan phase PWM output fixed at
50% duty in the following cases:
1) Drum frequency generator frequency
out of about 2 10% of the specified
frequency.

21

Pin No.

Name

Function

Input/Output

2) Capstan frequency generator
frequency out of about 2 5% of the
specified frequency.
3) No control pulse.
4) In serial data input mode for FFiREW,
slow, short rewind (ASB*REV).
20

Analog SW 1

output

Built-in analog switch turns on at the
servo serial data D 18 = " I"and off at
D18 = " . Bias voltage fed out of pin
0"
@ when the switch turns on. Slow, still,
FFiREW and capstan stop modes brought
on at D18 = " .
1"

21

Capstan spped error
output (capstan AFC)

output

Capstan speed error PWM output
terminal. Output at PWM repeated
frequency fsc/26+ 69 kHz., PWM duty
stretched toward "
H" due to speed dowr

22

fsc (4.43 MHz) input

Input

23

LP mode (H)

output

24

SP mode (HI

output

4.43 MHz sub-carrier input terminal
(C-MOS). Minimum operating
compensation level at over 200 mVp-p,
Inverting amplifier built-in.
Tape speed detection logic output
terminals for LP and SP modes
(C-MCS output).

LP (H) : PIN @

Servo serial data
input
Servo serial clock
input

Input

PG mono-multi

Input

27

L

H

Servo LSI operation mode is set by
these input terminals. 21-bit serial clock
provided. Internal mode is set by identifying data bit " 1 " or " ; data bit " " an
0"
1
"
0" at serial data with " and ' ,
H"
IL"
respectively, at rising edge of serial clock
Serial transfer made with shift register.
Internal transJer of 21.bit data made at
serial data "
H" at falling edge of serial
clock. (See Servo Process Block Diagram
(Fig. 3-l 91.)

Input

'
26

L

SP (H) : PIN @I
25

H

Mono-multi terminal for video/audio
head switching pulse output timing.
(Drum frequency generator and phase
generator input signals, internally
shaped into square wave, are used to
generate phase generator mono-multi
trigger pulse. By this pulse, the time
constant of resistor and capacitor
externally added is activated for time
adjustment.)
22

n No.

Name

Input/Output

28

Video H-SW-P output

output

Video head switching pulse output
terminal.
I. Double-azimuth 4-head switching:
Video head switching pulse output
timing in SP mode delayed by 2H
(+ 128 psec.) compared to that in
LP mode. (Actual video heads are
set up by 2H difference.)

29

Hi-Fi H-SW-P & tput

output

Hi-Fi head switching pulse output.
terminal.
1. 2-head switching: Head switching
pulse output 90' behind the video
,
head switching pulse.
2. Double-azimuth 4-head switching:
Head switching pulse 60" behind the
video head switching pulse.
(Not used on the models of this series.)

30

Vertical sync. input

Input

31

Tracking monitor
output

output

Internal tracking delay time point
monitored for digital tracking.
l
Monitor output stretched toward "
H"
duty when tracking data (servo serial
data DO thru D5 - 6 bits - used) is
raised. (The center value is 20.0 msec.
inside the IC; 14.78 msec. at this pin,
however.)

32

Control pulse duty
detection output

output

Control pulse duty identify output
L" level when control pulse
terminal. "
"
H" duty (time from positive pulse to
negative pulse) is long (about 60%).
"
H" level when it is short (about 27.5%).
Control pu!se identify duty fixed at
40% (TYP) in the IC.

33

Control pulse
Schmitt output

output

34

Vcc (for Digital
Circuit)

35

TEST

Function

Composite sync. input detected for
vertical sync. by the internal logic.
Vertical sync. is distinguished from
horizontal sync. by the pulse width.

Output terminal of the control signal
*at has been fed through Schmitt
amplifier and converted into square
H" level square wave made
wave. "
with positive pulse and "
L" one with
negative pulse. Internal control pulse
square wave inverted and put out when
tape travel is reversed.
Supply voltage input terminal for
digital circuit (5 t 0.5 VI.
"
H" input to make the servo IC in TEST
mode. Usually at "
H" level.

Input

23

Pin No.

Name

Input/Output

Function

36

Record control (- )

output

Terminal to apply voltage to negative
pole of control head in record mode.
(High impedance in playback mode)
l
" level duty 27.5% at servo serial
L"
data D17="
1" and 60% at D17=" .
0"

37

Record control (+ )

output

Terminal to apply voltage to positive
pole of control head in playback mode.
(High impedance in playback mode)
l
"
H" level duty 27.5% at servo serial
data D17="
1" and 60% at D17=" .
0"

a

38

GND (for Analog
Circuit)

Ground terminal for analog amplifier.
-

39

AMP (+)

Input

C-MOS amplifier positive input terminal.
Pulled with 37 kfi (TYP) up to bias
voltage at pin @ inside the IC.

40

AMP (-)

Input

C-MOS amplifier negative input terminal.

41

AMP output

42

Control pulse
Schmitt input

output

C-MOS amplifier output terminal.
C-MOS amplifier composed at pins @
and @.
(Not used)

Input

Control pulse Schmitt amplifier input.
Threshold voltage of Schmitt amplifier
system is controlled by the servo serial
data D 19 " , " 1" and slow/still mode
0"
as shown below, and control pulse is
given out from Schmitt output (pin 0).

D19 "
0" D19 "
1" Slow/still
Hysteresis 330mVp-p 650mVp-p 45mVp-p
Center level 0 mV

0 mV

110 mV

Notes:
1) The hysteresis of both the positive
and negative pulses of control pulse
are used at D19="
0" or " , in any
I"
other modes than slow/still.
In slow/still mode, only the positive
pulse peak is detected.
2) D19 = " is in FFiREW and video
I"
search modes.
3) D 19 ="
O" is in the other modes than
above.

24

3. SYSTEM CONTROLLER LSI
l
l

2-head s s em: RH-iX057 1 GEZZ, RH-iX0577GEZZ
y t
4-head system: RH-iX0572GEZZ, RH-iX0574GEZZ

3-l. System Controller Terminal Allocation.
Terminal Name

l/O

No.

Name

No.

Name

O(C-MOSI GND CTL

P20

64

I

O(3S)

P21

63

I 2 / AVss 1

FV

1 I

vcc

Terminal Name

l/O

I
I

I 5v
GND

O(C-MOS) FV CTL

P22

62

3

Vref

A/D REF. VOLTAGE

O(C-MOS) X 2

P23

61

4

D-A

COUNTER F/R

P24

/ 60 /

I
I

IOlC-MOS)/ CTL GAIN SW (L)

j

/ 5 1 PWM /

OK-MOS)

/O(N-CH)

BEEPER

6

P63

AL PB (L)

7

P62

BIAS CTL (H)

O(N;CH)

8

PI2

46

PI3

45

O(N-CH)

PB AUDIO (HI

PI4

44

O(N-CH)

HiFi CTL

PI5

43

O(N-CH)

AUDIO MUTE (L)

PI6

42
41

O(N-CH)

EE U-i

P17

SYNC DET (HI

P50

40

REEL SENSOR

P51

z
'
z
.
:
z
:
8
y
:+

39

I (A/D)

AUTO FUNCTION

I (A/D)

AN4

NC

I (A/D)

AN3

FV M.M.

I (A/D)

AN2

SLOW/STILL TRK

I

P41

SPEED DET

I

17

SLOW/STILL (H)

CASSETTE SW

AN5

16

CHROMA ROTARY

AN6

15

O(N-CH)

I (A/D)

14

O(N-CH)

CAM SW

13

i
6

O(N-CH)

AN7

12

47

O(N-CH)

VCR (L)

11

PI1

POWER CTL (L)

P60

10

H. AMP SW

P61

9

O(N-CH)

P40

NC

/ 18 1 SRDY / S.T
CLK

T.S CLOCK
S.T DATA

O(N-CH)

SIN

T.S DATA

21
22

II

CNTR SEARCH (L)

23

INT2

1 24 1 P31 /

O(N-CH)

ENVELOPE DET (L)
ENVELOPE

DET

I
II

25

P30

H.SW.P

INTI

H.SW.P (L)

I

II

I

1I

1 INDEX IN

/ P54 /

II

1DEW SENSOR

/ ~55 /

II

/ NC

/

P56

/

II

/ PB CTL

1

P57

/

33 I

32 -- vss

38 1

/ 27 I CNVss 1

37 I

28

ACL

36

1

29

XIN

35

j

30

XOUT

34 I

31

0

GND

I

I

ACL (L)

I

CLOCK IN

I

CLOCK OUT
NC

p

jo

GND

Figure 3-1. Bottom View

Note: On RH-iX0571GEZZ (for 2-head models) and RH-iX0577GEZZ
46 and 47 are not connected.

25

I

I

I

I

I

I

SOUT

I END SENSOR

P53

lO(N-CHI

19

1START SENSOR

1

(L)

20

II

P52

(A/D) 1

O(N-CH)

READY

26

is

1

O(N-CH)

(for 2-head LP models), pins 23, 24,

3-2. TERMINAL DESCRIPTION (2-/4-HEAD SYSTEM)
?n

Specifications

Control Signal

W.

1

5v

Vdd terminal

2

GND

AVss terminal (GND)
To be connected to GND

3

A/D REF VOLTAGE

Reference voltage for A/D converting

4

COUNTER F/R

5

BEEPER

It is a control signal offering the tape running direction to the timer
JC.
(1) Counter CTL = "
H" : Reverse turn
Counter CTL = " : Positive turn
L"
(2) Other than the model below should be identical to the capstan motor direction. Namely, in case of capstan reverse turn" , counter CTL="
H"
H" is applied.
l
Cue sound countermeasures for FF/REW-Stop, etc. (Idler neck '
swing)
* Idler neck swing
l
Inversion brake time for VS release
(3) In the mode below, the following are to be taken to adjust
to the tape running direction. (For use of real time counter)
l
At loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Counter CTL ="
L"
L"
l
Eject position/Stop position . . . . . . Counter CTL = "
This output shows the time of confirmation sound output when the
operating key is pressed.
l
Confirmation sound "
ON time" = "
H"
l
Confirmation sound "
OFF time" = "
L"
(System controller1
(I) The time of outputting a confirmation sound is 47 msec.
(2) The timing of outputting a confirmation sound is to be at
receiving of keys below.
l REC key
l Power key
0 Pause key
l TVIVCR key
. REW key
l Eject key
l Slow key
l Stop key
* Double speed key
l FF key
l
At INDEX writing (optional writing)
l PB key

,
[Timer]
(However, the confirmation sound output is only when the timer
serial data takes buzzer request.!
(1) The time of outputting a anfirmation sound is 47 msec. and
1 sec.
(2) To output the 47 msec. confirmation sound, it is done when
47 msec. short sound buzzer 1 is present with the timer serial data.
(Refer to the timer ref. material for the operating key outputting a short sound buzzer request.)
l
For the time of confirmation sound, it is shorter than the
above value at Slow/Still.
6

AL PB (L)

A signal to select REC mode with PB mode
(1) In case of PB-system mode (PB, Still, Slow, VS-F/R, double
speed) at PB. REC position, AL PB (L) = "
L" is applied.
(2) When the PB-system mode is released, it should be AL PB
(L) = " .
H"

26

Pin
No.

Specifications

Control Signal

7

BIAS CTL (H)

A signal to control start/end of recording of video/audio signal

8

POWER CTL (L)

A signal to control the power (supply) (controlling a driving-system
power)
(1) When the Power key is pressed at Power "
OFF" it should be
,
PCON (L) =' .
I"
However, in case of timer stand-by, the Power key should be ineffective.
(2) When the Power key is pressed in ON mode, it should be PCON
(L) =" .
H"
However, during mecha-operation, PCON (L) =' is continued,
I"
and PCON (L)="
H" is applied at the next mecha-position.
l Stop position
l
Slider Up position
(3) At timer stand-by, if the timer start data of timer serial data is
detected, it should be PCON (L) =' , making REC display. (Timer
I"
recording start)
(4) At timer stand-by, it should be PCON (L)=" . However, in VPS
H"
Interrupt mode, PCON (L)=" is applied.
L"
(5) For driving of loading motor, cassette motor or capstan motor,
if PCON (L)="
H" is present, it should be made PCON (L)=" ,
L"
and after driving, it is made PCON (L)=" .
H"
(6) In case of EE (L)=" and PCON (L)=" , if weak electric field
C'
L"
(L) input="
L" continues for 30 min., it is automatically to be
PCON (L)=" , allowing the mis-power-OFF preventive function
H"
to be effected.

a

9

VCR (L)

Control signal to switch on and off the signal to come to the RF
converter.
(1) Signal from the video tuner or playback signal from the video
tape fed in with VCR (L) signal at " .
C'
1 (2) Antenna input (VHF) signal fed through in with VCR (L) signal
at " .
H"
(3) VCR (L) signal at "
H" with power control (L) signal at " .
H"
(4) With power control (L) signal at ' , the TV/VCR selector key
I"
switches VCR (L) signal:
* From "
H" to ' .
I!'
l
From ' to " .
I"
H"
(5) When the Stop key is pressed during playback mode, the following are obtained.
i) If the VTR mode (L)="
L" at output of playback screen, VTR
mode (L)="
C' is continued.
ii) If the VTR mode. (U="
H" at output of playback screen, VTR
mode (L)="
H" is continued.

10

CAM SW

11

CASSETTE SWiREC TIP

12

AUTO FUNCTION

13

NC

To be connected to Vdd or GND

14

FV M.M

It is intended to adjust the delay amount from the edge of H.SW.P
to the generation of false vertical synchronous signal.

This terminal has the A/D converting function of 6-resolution for
analog voltage by the comparator (IC built-in) and D/A converter.
(5 to 8)

27

--

f'
in
rI\lO.

Control Signal

Specifications
(1) Normally, " is outputted.
L"
(2) After detection of H.SW.P edge, the terminal is made to be "
Z"
(High impedance) and the mono-multi input taken. When recognized as " , the mono-multi input is stopped and the terminal
H"
to be ' .
I"

H.SW.P

a
FV M.M.

"
H"

I
I

"M "
"L"

I
I

"
H"

1

False V

Ternary out~"t at SP

"L" B i n a r y o u t p u t a t L P

4
8

Figure 3-2.

15

SLOW/STILL TRK

It is intended to adjust the reverse torque generating timing at
Slow/Frame advance.
The preset is inputted to this terminal.
(I) Normally, " is outputted.
C'
(2) At frame advance, when it detects the rising edge of PBCTL signal, it allows the delay time preset by user to pass by. Then, the
terminal is selected to " (High impedance) and such a monoZ"
multi input started. When recognized as " , the mono-multi inH"
put is stopped and the terminal to be ' .
I"
I

I

I

I

I Slow TRK mono-multi
I- -;
time
I
/
I
I
/

PB C T L
/\

I
!
I
,
I
,
lc Delay time preset

I
/
I

/
1
- Reverse torque
generation

Slow TRK M.M.
1
I

I
I

I
I

I

Figure 3-3.

16

SPEED DET

Switches shown corresponding to A-F keys of D/A converting circuil
Speed
detection
input
A

CA SW

Function selection input
Variable speed VSiAuto OFF

SP mode
B

HF SW

Vanable speed VSiAuto Repeat

C

FF SW

Fixed VsiAuto OFF

D

LD SW

Fixed VSiAuto Repeat

E

PB SW

F

PU SW

LP mode

Not used
Not used

ALL SW "
OFF" SW OFF mode

Not used

Auto Power OFF: Auto power OFF function
Auto Repeat:
Auto repeat playback function
Tabie 3-l.

28

Pin
No.

Control Signal

Specifications
[Cassette cantroller SW1
Refer to cassette controller circuit. (Fig. 3-4)
he

I

SW
A

/

Cassette controller/Auto
cassette controller

Specifications
ON: Cassette insertion start
OFF: Other than above

Cassette controller SW
(Insertion start detection)

I

0

ON: Cassette fit-in state
Auto load SW
OFF: Non-auto load cassette con(Cassette fit-in state detection)
troller or cassette not fitted in

C

REC. Tip SW
(Mis-erasing preventive tab
detection)

D

(CAS. Unit fit-in state
detection)

ON: Preventive tab broken
OFF: Preventive tab present
D-SW to be always "
ON" at unit
fit-in state
All SWs to be "
OFF" without unit

l

l
I

L

Table 3-2.

D/A Converting circuit (Main body SW/CAM. SW/Function selecting SW/Cassette controller SW)

74

Figure 3-4 (a).

r - - - - - --___---__ (Note: & gt; )

-q 5v

._---- - ---- ----?

(Note:

11

/

L---------------------~----~-~

Casserte control circuit

Note 1: The D swtch is kept on all the time.
Note 2: The block framed with broken line is
the cassette controller unit.

Figure 3-4 (b).
Reference voltage
Input voltage Vln (V)

Vref IV1

5.ov
i
4.21v

4.53v
--_---_---_

- - - - - - -

F key indent. range

I
E key indent. range

3.45v

3.91 v

, 2.97v
2.5OV

c D key Indent. range
/

- - - - - - - - - - -

2.04V

1.54v
1.09v
0.77v
A k e y Indent. range (

o.ov

I

I

I

0.47v
I

I

I
'
'
, A key' key' keyiD keyiE k e y F keyi No key bnpur
6
C
I
I
I
(Volrage se? value A-11
Input vohage (",n) "s. reference voltage (Vrefl with each swtch

Fiaure 3-4 Cc).

29

Pin
No.

Control Signal

Specifications

Figure 3-4 Idl.

(CAM SW input)
l
Refer to Fig. 3-4 for L-mecha. mecha-posi. and mode.
(Cassette control SW/REC Tip input)
. Timing of cassette insertion/Detection of REC. Tip state
(Cassette controller SW)
(1) SW A detects start of cassette insertion in slider UP condition.
(2) SW B is intended for Auto load cassette controller and "
ON"
when the cassette is fitted in slider UP condition.
For normal-type cassette controller, it is always "
OFF"
.
(3) SW D is conceptual and always "
ON" when the CAS. unit is fitted in.
(REC Tip SW)
(1) It is "
ON" at REC Tip broken and "
OFF" at REC Tip present.
(2) It takes Eject immediately, if the "
REC/timer REC" mode is to
be started at REC Tip broken. (Tab-broken cassette/Auto-Eject
function)
(Speed detection input)
Input to detect a tape speed data of 4Hi2H
(1) Refer to the preceding para. of "
A/D terminal description" for
the relation between the recording mode and the voltage level
to be inputted.
12) The data inputted is transferred to the timer IC as below.
i) In Stop/REC mode, the data of speed detection input is made
ineffective, and the data of recording mode selected by timer
is made to be a serial signal, transferred and displayed.
ii) At replay by PAL 2HEAD, the following codes are trasferred to
the servo IC, instructed by "
Audio 8CH spec. treatment" from
the timer.
l SP mode (Speed identification permitted) at Audio 8CH spec.
treatment
l
SP fixed (Speed identification prohibited) at Audio 8CH spec.
no-treatment
17

NC

NC Terminal: Terminal should to be open.

18

S.T READY (L)

Refer to Page 43.

19

T.S CLOCK

20

S.T DATA

21

T.S DATA

It is a control signal intended for serial transfer between the timer
IC and the system controller IC.
(1) It should be timer READY (L)=" every 23.4 msec., and 8 bit
L"
x 5 byte transferring is taken.
(2) For serial transfer, after timer READY (L)=" has been made,
L"
the system controller serial data is set by trailing edge of serial
clock from timer IC, and the timer serial data is inputted by rising edge of serial clock. And then, after input of 8 bit data, it
should be timer READY (L)=" .
H"
(3) The time of timer READY (L)="
H" is 1.3 msec. min.
(4) For serial data, refer to page 42.

30

Pin
No.

Specifications

Control Signal

22

SEARCH (L)

It is a control signal for selecting the gain of PB CTL signal.
(1) In Video-Search F/R mode, it should be Search (L)=" .
L"

23

ENVELOPE DET (L)
(4-head only)

24

ENVELOPE DET
(4-head only)

Reference signal for head amplifier/chroma rotary switching output.
To be given out of the head amplifier module.
(I) Used to control the head amplifierichroma rotary switching output with the envelope comparison signal input as reference in
each mode.

25

H.SW.P.

26

H.SW.P.(L)

a

Sensor input intended to detect the state of the drum to be rotated.
(1) Head switching pulse to detect if the drum is running.
(2) Drum remains running with drum speed-up at "
Z" (high impedance) from loading start to unloading end.
(3) If head switching pulse input stays in the state (2) above for 1.6
& lt;
seconds, the head is stopped.
It is the reference signal of FV output in trick mode (VSFiR, x 2,
STILL/SLOW).
(I) In trick mode, FV output is taken at the rising and trailing edges
of HSW.P input (HSW.P).
(2)A signal allowing start of frame advance.

27

GND

CNVss terminal (GND)
To be connected to GND

28

ACL (L)

It is an initial resetting terminal of microcomputer, and allows the
microcomputer to be initial-reset by applying the low voltage.
In addition, with system controller reset signal, initial resetting is
possible by connecting such a signal to the ACL terminal by the
timer microcomputer. The timing of system controller reset signal
on timer microcomputer is shown Fig. 3-5.
I
I
I
/
I
,
t
/
/
I
I
I
I
!
I
7

Supply voltage

/
/
I
I
I
I
I

A C L pulse of Timer

I

Reset signal of
system controller

I
I

I
I
I
+
System controller ACL

F i g u r e 3-5.

29 / CLOCK IN
30
CLOCK OUT

The system clock generating circuit of microcomputer is built in,
and the clock signal (4Jv'
lHz) is obtained by connecting the ceramic resonator shown Fig. 3-6.
C L 1 ( N o . 4 6 pm1

0

C L 2 (No 47 p~nl

4MHz
II

Cl

iiF

T"
Figure 3-6.

31

NC

NC terminal: Terminal should to be open.

31

:

Pin
No.

Control Signal

Specifications

32

GND

Vss terminal (GND)
To be connected to GND

33

PB CTL

34

NC

To be connected to Vdd or GND.

35

DEW SENSOR

An input terminal to detect any dew situation
(I) When the dew sensor is equal to " , it identifies as dew situaH"
tion and prohibits any mecha. actuation. However, the following keys should be effective regardless of dew situation.
l Power
. Eject/Insertion
l TVIVTR
(2) When the dew sensor is equal to " , the mecha. position is
H"
moved to Eject position and done as follows:
H"
L" . . . . . . . . . . . . . . . . . . . . . . . . . . Drum mute (L) ="
PCON (L)="
(L)="
L"
H" . . . . . . . . . . . . . . . . . . . . . . . . . . Drum mute
PCON (L)="
(3) When the dew sensor is equal to " , the mecha. position is
C'
moved to Stop position.

36

INDEX IN

This input is to detect cue signal in INDEX mode.
(I) " is inputted on cue recording section. (H to be 20 msec. min.)
H"
(2) By timer operation, Intro search (Interval search) and Index
search are set.
i) Setting of Intro search (Interval search)
When the FFIREW key is pressed, it is shifted to Intro search.
When the cue signal input "
H" is detected during FF/REW
mode, it comes to be PB mode during 7 sec. and is re-shifted
to the FF/REW mode, continuing the cue signal input.
ii) Release of Intro search (Interval search)
When the mode is cleared by the timer, Intro search is released
at once, continuing the current mode.
When the mode key (STOP/FF/REW/PB/REC/SLOW/doubIe
speed key) is pressed during Intro search, the intro search
mode is released, allowing mode shifting.
_iii) index search
When the number of skips is set by Index search, the INDEX
signal is detected, and then it is transmitted to the timer IC
by the system controller SIO.

37

END SENSOR

A signal to detect a tape end
(I) For detection of rising edge of end sensor input:
i) In case of ON mode with cassette IN, auto-rewinding is taken.
ii) During timer REC, Eject is taken after leader tape winding.

Reference signal taking playback blue mute
(I) Unless PB CTL rising edge can be detected during 120 msec.
in PB mode, a blue mute request is taken to the timer IC.
(2) Ref. signal for determining a time (61 i 2 pulses) of "
INDEX signal writing"
(3) Detection signal for identifying a recorded tape (tab broken cas3
sette) in Full Auto function
l
A signal causing reverse torque generation at frame advance

(2) If in Stop mode, the tape is rewound and the leader tape wound
until the end sensor input is ' . However, unless the end senI"
sor input is " even after continuous rewinding for 5 sec., stop
C'
processing is taken.

32

Pin
No.

Specifications

Control Signal

(3) Cassette-down is judged by the end sensor input and the next
start sensor input as follows:
(Cassette controller down). ((End sensor) + (Start sensor))="
H"
In such a case, cassette-down is recognized.
38

START SENSOR

A signal to detect a tape start
(1) For detection of rising edge of start sensor input:
i) In case of REW mode, stop processing is taken.
ii) If during RECIPAUSE short rewinding, short rewinding is interrupted.
:
(2) If is Stop mode, the tape is rapidly advanced and the leader tape
wound until '
the start sensor input is ' . However, unless the
I"
start sensor Iinput is ' regardless of continous rapid-advance
I"
for 5 sec., stop processing is taken.
(3) The start sensor input is utilized for cassette-down recognition.
Refer to the paragraph of end sensor input.

39

REEL SENSOR

It is a sensor inp.ut intended to detect the reel stand situation when
it is to be turned.
(I) The situation subject to a reel stand turn is as follows:
i) For loading completion:
l PB
l REC
l
VSF
l VSR
l Double-speed
ii) For unloading completion:
l FF
l REW
(2) In such conditions, unless the reel sensor input changes within
the time of each mode shown below, stop processing is taken.
1
Shut-Off lime

Mode

SP-PBISP-RECIFFIREWiDouble-speedil.5~time speed
LP-PB/LP-REC

5.0 sec.
10.0 sec.

i

Video Search Rewind/Video Search Reverse

1.2 sec.

Table 3-3.

(3) For processing of tape slack detection, the edge of reel pulse
to be inputted utilizing the reel sensor is to be counted.
40

SYNC DET (H)

It is an identifying terminal for weak electric field, being a signal
to be outputted from the external Sync Det circuit for Hsync existence of input video signal.
(I) For Hsync presence, it is weak electric field (L)=" .
L"
For Hsync not present, it is weak electric field (L)=" .
H"
(2) Input of weak electric field (L) is effective in case of EE (L) =" .
H"
(3) In case of EE (L)="
C' (EE screen), if the weak electric field
(L)="
H" continues for 120 ms., it is to be a blue screen applied.
(The timer IC takes OSD for application. However, that is only
when the blue back ON/OFF SW is "
ON"
.)
(4) In Stop condition with PCON (L)=" , if the weak electric field
L"
(L) ="
H" continues for about 30 min., PCON (L) =" is applied.
H"
(However, unless any execution instruction (T361 from timer IC
is done, it is ineffective. At selection of Full Auto, T36=" .)
1"

33

Pin
No.

Specifications

Control Signal

41

EE (L)

A signal of selecting between EE screen and playback screen
(I) The EE signal is intended to select the signal, i.e. the videoiaudio output is to be EE or PB, and thus in case of EE (L)=" it
C'
selects to the signal (EE screen) to be transmitted from the tuner,
and also at EE (L)=" it selects to the signal (PB screen) to be
L"
transmitted from the video head.
(2) At PB. REC position, if it is PB-system mode and EE (L)=" , EE
C'
(L)="
H" is applied about 1 sec. after positive turn of capstan
motor.
13) If the PB-system mode is released, it should be EE (L)=" .
L"

42

AUDIO MUTE (L)

A signal to stop any audio output
(I) At Power CTL (L)=" , it should be Audio mute (L)=" at any
H"
C'
time.
I
(2) For Power "
ON"
:
;-1,l

set---g

/
f

Power CTL (L)

/
1
I

(H)

I
I

IH)
1

Audm Mute (L)

Figure 3-7.

(3) After PB loading end:
F Durtng Loading A
Loading

,

Cassette Motor CTL
A L PB (L)

1

1

Motor (+I

I

(Ll
(L)
5 0 0 mr +

Audio Mute (L)

(L)
(H)

Figure 3-8.

(4) In PB mode, when the trick playback (Still, Slow, VSF, VSR &
double speed) key is turned "
ON" A mute (L)=" is applied im,
L"
mediately, shifting to trick playback.
(5) When trick playback is released, it is moved to the mecha-posi.
of PB mode, and then after about 1,000 ms, A mute (L)="
H"
is applied.
(6) When the PB mode is released with EE (L)="
H" condition, A
mute (L) should be =" for 500 msec.
L"
.w

43

HiFi CTL

Not used.

44

PB AUDIO (H)

Audio muting at PB Audio (H) -I "
H"
At EE (L) + "
L"
Pin @ SYNC DET (H)

PB AUDIO iH)

H

H

L

L
Table 3-4.

At EE (L) --t "
H"
Pin @) FV CTL

PB AUDIO (Hi

H

H

L

L
Table 3-5.

34

Pin
No.

Specifications

Control Signal

45

SLOW/STILL (H)

"
H" at Slow/Still
Not used

46

CHROMA ROTARY
(4-head only)

Terminal to select chroma.
(1) Right channel: "
H" (6" azimuth head side).
(2) EXOR logic for head switching pulse and head amplifier swkching signal.

47

H.AMP SW
(4-head only)

Output to select between SP and LP heads.
(I) SP mode: "
H"
LP mode: "
C'
(2) Head amplifier switching control signal at " in LP mode.
C'
(3) Inverted envelope comparison input signal (pin @I) to be outputted at VS-F/R in SP mode.
(4) Signal to be outputted according to record mode of each step
during slow/frame advance.
(SP mode)
l
This signal remains in phase with head switching pulse during
frame advance.
Head SW Pulse

mrlqq

Head Amp SW

Chroma Rorat~on

Figure 3-9.
l

This signal remains in anti-phase with envelope comparison signal at the start of slow/still mode.
,- S l o w / S t i l l start fine -1

Head SW Pulse

mmm

Head Amp SW

Chroma Rorat~on
Note: The envelope comparison signal here is typical one.

Figure 3-10.
l

The envelope comparison signal is inverted after the slow/still
mode is cleared. Release
Processing
+--Phase

Head SW Pulse

m a t c h i n g tgme

~~~~~ii'
il

Envelope Comparison Tmm
:
/
Head Amp SW

_;u;: & J
:
:
:
/

Chroma Rotar~on

;mvu-I.

/

rLuL-u-u-tll

Nore: T h e envelope comparison signal here 1s Q'
Picaf one.

Figure 3-11.

Pin
No.

Control Signal

Specifications
(LP mode)
l
This signal remains in anti-phase with head switching pulse during frame advance.
Head SW Pulse

m'
imm

Head Amp SW

Figure 3-12.

0

The following timing is set up at the start of siow/still mode.
i- Slow/Still sfart time ---A

Head SW Pulse

Head Amp SW

Chrama

I
/

Rotation

I

Figure 3-13.
l

The envelope comparison signal is inverted after the slow/still
mode is cleared.
ReleasP

Processing
-Phase matching time
I
f
Head SW Pulse
,
1
Envelope Comparison
1

I
/
u

bite: The envelope comparison signal here i6 typic.3 one.

Figure 3-14.

48

~ TRANSIT (HI

49

SERVO S. CLOCK

50

SERVO s. DATA

51

BRAKE SOLENOID

When transferring from VS FWD and VS RVS modes to PB mode,
it continues to be "
H" for approx. 1,400 ms.
Used to cope with colour dislocation
(I) The following are the method of data transfer to servo IC.
The servo IC outputs thedata of 21 bits to latch the servoidisplay serial data at rising edge of servo/display serial clock. Then,
the serial output is completed by making servo/display serial
data="
H" at the final clock trailing edge.
(2) For mode and data, refer to page 41.
It is a signal for controlling the brake solenoid ON/OFF.
(I) This signal is intended to control the brake solenoid ON/OFF, and
in case of brake solenoid=" , the brake solenoid is made to
H"
be attracted.
(2) When the REW key is pressed at FF.REW position, REW display
is made, and it makes loading motor positive-turn CTL=" and
L"
loading motor reverseturn=" , and after movement to brake
H"
release posi., brake solenoid ="
H" is applied.

36

Pin
No.

Control Signal

Specifications
(3) When the FF key is pressed at FF.REW position, FF display is
made and then the same brake release processing as (2) is taken.
(4) If the cassette is already inserted and end sensor="
H" or start
sensor="
H" is present, the same brake release processing as
(2) is taken.
(5) In tape slack detection, it takes such a brake release processing
identical to (2).
(6) When the REW key is pressed in case of EE (L) ="
H" at PB.REC
posi., VSR display is made and brake solenoid ="
H" made, shifting to the VSR position. After shifting, brake solenoid=" is
L"
applied.
Then, when the VSR mode is released, it makes brake
solenoid="
H" after stopping of tape running, and then upon
shifting to PB.REC position, brake solenoid="
H" is ma,de.
(7) In the item of (2), (3) and (4) of capstan UL, brake solenoid ='
I"
is made immediately before capstan UL (L)=" .
H"
(8) It makes brake solenoid="
L" immediately before release of
FFIR EW.

52

LOADING RVS CTL

(I) It is an output terminal for controlling the rotating direction of
loading motor.

53

LOADING FWD CTL

Given below is the relevant combination.
Control Signal

Loading motor
positive-turn CTL

Loading motor
reverse-turn CTL

Loading motor Stop

L

L

Loading motor positive-turn

H

L

Loading motor reverse-tur

H

H

Table 3-6.

(2) For stopping condition of mecha. actuation:
l
Loading motor positive-turn CTL ="
L"
* Loading motor reverse-turn CTL="
L"
(3) The following functions are provided so as to prevent any overcurrent to the loading motor.
l
2.0 sec. shut-off at cassette controller actuation
* 7.0 sec. shut-off at loading arm actuation
(4) For shut-off, there should be loading motor positive-turn CTL="
C'
and loading motor reverse-turn CTL =" , and the loading motor
L"
is stopped, and then stoppage is continued at that position until the operating keg input has any change.
However, if during positive-turn of cassette controller, the motor is reversely turned and the cassette is ejected at once.
(5) Actuation of cassette controller
i) In cassette insertion, unless the cassette controller moves to the
cassette controller down-posi. within 2 sec., it is actuated in
Eject direction immediately, and further if not moved to the cassette controller up-posi. within 2 sec., it takes shut-off.
ii) For cassette controller Eject, unless the cassette controller
moves to the cassette controller up-posi. within 2 sec., it is actuated in the cassette inserting direction, and if not moved to
the cassette controller down-posi. within 2 sec., it takes shut-off.

37

'
in

Control Signal

UO.

Specifications

54

CAPSTAN UL (L)

A signal to control a reel rotating torque
(1) The capstan UL is a torque control voltage to be applied to the
capstan motor, and to be " during unloading, at start of FFiREW
C'
or at tape-winding at Eject.
i) If the Stop/FF/REW mode is obtained at PB. REC position, the
loading motor is reversely turned, and after about 500 msec.,
capstan UL (L)=" is made, and the capstan motor is reversely
L"
turned, stopping the capstan motor and capstan UL (L) ="
H" at
brake release position.
ii) When the FF key is pressed at FF. REW position, FF display is
C'
a made, and after brake release, capstan UL (L)=" is made, and
the capstan motor is positive-turned and about 500 msec. later,
capstan UL (L)="
H" is applied.
iii) When the REW key is pressed at FF. REC position, REW display
is made, and after brake release, capstan UL (L)="
H" is made,
and the capstan motor is reversely turned and about 500 msec. '
later, capstan UL (L)="
H" is applied.
(2) In tape slack detection or leader tape-winding processing, for
start of tape running, about 500 msec. capstan UL (L)=" is
L
to be applied. However, if the above processing is completed within 500 ms., capstan UL (L)="
H" is made immediately.
(3) Idler move at start of loading action.
(4) Loose-tape winding processing upon cassette insertion (300
msec.)
(5) Loose-tape winding processing during Eject actuation.
(6) Countermeasure for tape slack at FF+Stop

55

CAPSTAN PU (L)

A signal to control a reel rotating torque
(1) The capstan PU is a signal for controlling the torque control voltage of capstan motor, and outputs at the following timing.
i) At transfer from PB. REC posi. to VSR posi.
ii) At return from VSR posi. to PBiREC posi.
iii) At idler move (Neck swing processing)
iv) Idler move from tape-winding upon cassette insertion
v) Idler move at REC-REC. Pause

56

CAPSTAN RVS (H)

It is a control signal for determining the rotating direction of capstan motor.
(I) The mode is made by combining the terminal @ with forced acceleration.

,

Forced acceleration

Capstan motor
reverse turn

L

L

H

L

H

H

Capstan motor stop
Capstan motor positive
turn
Capstan motor reverse turn

w

Table 3-7.

57

CAPSTAN CTL
(Forced acceleration)

It is an output accelerating (stopping) the rotation speed to the capStan motor.
(1) For Slow/Still:
i) At Still (still image) replay-tforced acceleration ="
H"
ii) At Slow/Frame advance-Refer to a frame advance timing chart.
2) Other than Slow/Still
i) Capstan motor rotation: Forced acceleration ="
Z"
ii) Capstan motor stop: Forced acceleration ="
C'

38

Pin
No.

1

Specifications

Control Signal

58

CURRENT LMT

It is an output offering a torque (current) limit to the capstan motor.
(1) In case of Power CTL (L)=" , current limit=" is outputted.
L"
L'
(2) For Power CTL (L)=" :
L"
i) At Still (still image) replay+Current limit="
Z"
ii) At Slow/Frame advance+Refer to frame advance timing chart.
iii) For other than above, current limit="
H" is outputted.

59

DRUM CTL

This signal is to control the drum motor rotation, and stops the drum
motor in oase of drum mute (L)=" .
L"
(1) If PB, VSR, VSF, Still, Slow, double speed or REC display is obtained at FF/REW position, drum mute (L)="
Z" is applied, and
after 500 ms, loading is started.
(2) If Stop, FF or REW is obtained at PB/REC position, unloading is
started, and after completion, drum mute (L)="
C' is applied.
(3) Lateral swing acceleration at Slow/Still-+Refer to a frame advance timing chart.

a

60

CTL GAIN SW (L)

It is a gain selecting output of PB-CTL amp. at FF/REW.
(I) At FF/REW-tCTL gain selecting
CTL ="
H" output
Other than above-+CTL gain selecting
CTL =" output
L"

61

X2 (H)

At double speed -I "
H"
Not used

62

FV CTL

It is a control signal for APC correction of drum in trick mode.
(1) In case of trick=" , drum correction is done.
H"
(2) At VS-F/R, double speed, slow & Still mode, trick="
H" is made.
(3) The timing of trick='
%" is to be 1 sec. after phasing term after
PB mode shifting.

63

FV

In trick mode (VS-F/R), it generates FV/FH and applies the synchronization.
(1) Such a FV is generated in VS-FIR mode, mecha. shift time of
PB--tVS-R, mecha. shift time at VS-R release, mode holding time
of VS-FIR release Slow/Still, and in the case of Head 2 giving
no double speed.
(2) The generation timing waveform is as shown below. (Note:
H.SW.P applies to both rising and trailing.)
i3 made (Fixed-FV Ternary output)

A mode (Variable-FV Ternary output)
H.SW.P

D mode (FIxed-FV Binary output)

C mode (Variable-FV Binary output)
H.SW.P

H.SW.P

39

Pin
No.

Control Signal

Specifications
(3) Modes and output waveforms are listed below

VS-Forward/Reverse

Table 3-8.
& lt;

64

GND CTL

It controls the (-- 1 terminal of CTL head.
(1) 100 ms after bias CTL (L)=" , it should be GND CTL=" . (At
C'
L"
REC)
(2) It should be bias CTL (H)=" , together with GND CTL=" .
H"
H"
(3) Normally, it should be " .
H"

40

3-3. Data Transmission Specification of Mechanism Controller Corresponding to Serial Mode Servo
l

Data is transmitted with the following format.

Servo data

0

1

2

3

4

5

6

7

8

9

10

1

Sen/o

Output end

Figure 3-16.

(I) 21 bit data is outputted to t%e servo IC through the 2-line system consisting of servo clock (SCK) and
servo data (Sl).
(2) The servo data latches at the tail edge of servo clock. Servo SIO ends when the servo data is set to
"
H" at the servo clock tail.
*
1. Relation between Modes and Service Data
(The servo IC corresponds to RH-IX0431GEZZ)
Serial Data
Mode
POWER OFF

O-5

6

7

8

9

10

11

12

13

14

_-

-

-

-

-

-

-

-

-

1

0

1

1

0

0

1

0

1

1

0

0

0

POWER ON STOP

*1)

For 2.0s after FF start

*11

F F subsequent

Xl)

1

For 2.05 afrer REW start

x-1)

1

REW subsequent

*l)

1

PB SP mode

Xl)1

1
1

1
1

15

16

17

18

19

20

- -

-

-

-

Serial transmission stop

1

0

1

0

0

(FF2)

1

0

0

1

0

(FFl)
(FF21

-

*a
*21

0

1

0

0

1

1

0

0

1

0

1

1

0

0

0

*21

1

0

0

1

0

(REWl)

1

1

1

1

*

*

2)

1

1

0

0

1

*2j

1

0

0

1

0

(REW2I

10

0

0

0

0

0

10

10

0

0

0

(P8)

0

0

0

0

0

0

0

110

0

0

0

(PB)

*11110

0

0

0

0

10

0

0

0

(PB)

V S F (M)

*1)

1

1

0

1

0

0

0

0

* 2)

1

0

0

1

0

(SER2) SP: *

5,

(H)

*l)

1

1

0

1

0

0

1

:o

* 2)

1

0

0

1

0

(SERB) SP: *

7,

(M)

*11

1

1

1

1

0

0

0

0

* 2)

1

0

0

1

0

(SER2/RI SP: * 5 , L P :

(t-l)

1

0

0

1

0

(SER3/R) S P : * 7 , L P : *7

1

0

1

0

0

(SLOW)

1

0

1

0

0

(SLOWI

LP mode

x1)1 1

SP fixed mode

VSR

0

*1)

1

1

1

1

0

0

1

Xl)

1

1

0

1

1

1

0

0

STILL

Xl)

1

1

0

0

0

0

0

,o

1

0

* 2)

0

SLOW

0

1

1

1

1

* 21

*11

1

0

0

1

1

0

x110

0

0

0

0

0

0

LP mode

*1)0

0

0

0

0

0

0

0

SP fixed mode

*110

0

0

0

0

0

0

0

0

0

0

0

0

0

0

* 2)

REC/pause

xl)0 1

0

1

High speed
R E C SP m o d e

0

10

0

0

0
0

(REC)

1

0

0

7
5

(REC)

0

(REC. ASB)

Loading

x1)0 1

0

0

0

0

0

0

*2)

0

1

0

0

(REC. ASB)

Unloading

*l)

1

1

0

1

1

0

0

1

* 2)

1

0

0

0

0

(FF2)

Short loading

*1)

1

1

0

1

0

0

0

0

*

a

1

0

0

1

0

(SERll I ( + 2 1

Short unloading

l

0

0

0

0

0

0

1

0

0

(PB)

Trick cancel

Xl)1 1

0

0

0

0

0

0

1

(PE31

Short rewlnd,ng

xl)0 1

0

0

0

0

0

0

*

Phase matching

Xl)

0

0

0

0

0

0

l)

0

1

1

1

N o t e 11 : Tracking delay time

*

0

Note

1
*

D O io D5 = "1 0 0 0 0 0" only in R E C mode
In other modes the preceding data remains.

t:

0

0

l

(REC)

0

*5
*

(*2)

0

0

1

0

0

13)

1

0

0

*3)

11
0

0

*3)

1

LP:
LP:

2)
1

SP

SP :

1

0

0

0

0

0

0

0

(REC. ASB)

1

0

0

0

0

(REC. ASB)

1

0

LP
: 0 1
fixed : 0 0

Holding

41

0

1

2)
1

2:

Table 3-9.

1

: 1 1

Note x 3 : Only when writing the VISS
I n o t h e r cases: "0"

signal:

"1"

2. Serial data DO to D5

3. Serial data D14 to D 15

1

Holding

Table 3-11.

N o t e : T h e output

from pin @ of the servo IC

(RH-IX0431GEZZI

is delayed by 5.22 msec

Table 3-10.

4. Serial data D16 to D20
D16

I

0

Head

I

D/A 4 Head

1

1

D17

D19

)

Hysteresis

I

Width

0

REC. CTL 60 %

D20

I

600mVDp

1

REC I CTL Selection

0

I

300mVpp

1

REC. C T L 2 7 . 5 %

1

I

2 Head

R E C / DUTY Selection

0

Selection

I

High-Z

1

i

I

GND

Table 3-12.

3-4. Serial Transmission Format between System Controller and Timer
1. Format of Data Transmitted from System Controller to Timer
S 1

S 0 byte
s
06

L

s
05

s
s
04 03

SVStem c~ntrollt?r

s
02

s
01

I
mode (8 bits)

S 2 byte

byte

s
00

L
System controller

____status

S3 b y t e

S4 b y t e

System controller status (8 b!t x 4)

Figure 3-l 7.

(1)
(2)
(3)
(4)
(5)
(6)

_-

5-byte data is transmitted by one transmission sequence.
The SO byte is arranged so that 8 bits compose one system controller mode data.
The system controller mode is the system controller operation modes.
The S 1, S2, S3 and S4 bytes are 8 bite data which are used as system controlier status data.
The content of system controller status is represented the status of pertinent sensor by each bit.
The timer makes the data valid when the same data is received twice successively (for SO, S I, S2, S3, S4).

42

2. Format of Data Transmitted from Timer to System Controller
T 1 byte

T 0 byte

Remote control data (8 bit x 2)

T 2 byte

T 4 byte

T 3 byte

Timer status (8 bit x 31

Figure 3-18.

(1) 5-byte data is transmitted by one transmission sequence.
12)TO byte and Tl byte are 8 bit data which are used as remote control data.
(3) The remote control data and they are determined by the content of control signals from the optical remote control and timer.
(4)The TO byte and Tl byte have always the same data content.
(5) The system controller makes the remote control data valid if the TO byte and Tl byte match with each
other.
(6) The T2, T3 and T4 bytes are time master status data. The timer status consists of 8-bit flag it represents
the timer status.
(7) The system controller makes the timer status data valid when the same timer status data is received
twice successively.

r

43

44

Servo Process Block Diagram

40mVp.p

ciii3 C708

PG: M.M.

+

R706

T

T

PCSV

I

I

R704
tl

r-

1

I c7z7z

TP701 (HEAD SWITCHING

~-/--zr

PULSE)

'
lAiOGUJ & DIGEAL
vcc
vcc
DRUM FG
COUNTER
,

(TIT@

PG SCHMITT
I\nMP.
A
DRUM
FG
AMP.

I

II!zl

DRUM FG
SCHMITTAMP.
k

DRUM SPEED
COMPARISON
COUNTER

-

1

I

*
REC IASW

-

(

K

DRUM
COMPENSATION
RDM

DRUM
REFERENCE
COUNTER

1
/+

2H
DELAY]

AFC,
J
DRUM PHASE
DETECTOR

APC

*
I

CTL HEAD @

O)ii'
i
c7b4
-

CTL HEAD -

L
l-

j+

R745

TRACKING M.M.

ANALDGUE

DIGITAL

SERIAL DATA
MODE
DECODER

RH-IX0431 G
(Digital Serw

CTL GAIN SW
(FF I REW MODE)
CTL GAIN SW
(SEARCH MODE)
Q705

CTL GAIN SW

Figure 3-19.

45

2.w
SERVO
REFERENCE
VOLTAGE
GENERATOR

iING

_

R767
-PC 5v
R766

I

DRUM MOTOR
UNIT

CLOCK 4.43 MHz

(RMbTP1096GEZZ)

-I
I/ I

R709

QiR AMP.

AFC,

+++-lzB
M51721ATL

iAlN
TION

CAPSTAN MOTOR UN11
(AM~TNZOlSGEZZ)

COMPARATOR

;AlN
TION

-4

LP IHI

IAL DATA
IE
:ODER

RH-IX0431GEZZ
(Digital Servo LSI)
\
\ C702
H

J

\,

1-19.

46

-1 AT 5V
iOSE SIGNALS DEFINE
IAOING MOTOR ROTARY DIRECTION

I--

9

P60

-]GND

M 12")

"
CR ,L,

I

0 INCH)

, -,
l----

42lH + I T.S

I

11
I I

DATA

-+ 1 COUNTER PULSE

. / I nmb.R,I" ,.,.,d.
U

+- COUNTER RESET

L---*---J
FL801
4MHZ Al
.- 1 ENVELOPE DET
+ H. SW. P

+
Figure 3-20.

- .-_ - . _

48

_-_- -__ - _- .- -"- - -I.-. ._ -_-_ - L-._._- L

-..-,

:.

.
:

.r.i

- -bi

--f,
I-LF

--t--

l_c _I_
f

--

I & lt;

-L

f T-J-" '1 --

)

r-

-L.---+--

------t-t-.c
Y
"
I
I.u
s
L & gt;
;2
.%a
wn

49

i

--T---.
--Ii-*

I
LL
---Ii-f-I
c"
------

Shift to RECKTOP mode when the Slow/Still mode is cleared
(2-head system)
(Release
Processing)
(Slow/Still) __c__t/
1 (T81 1
17----b

- (Ret or stopi

Drur Sensor
IH.SW.P.1
i
Forced
Acceleration
(Ternary)

"l-l"
" L"

"(+" /
Current Limit
(Ternary)

"2"
I
I
I

I
I

I

"L"
Capstan Reverse

I

i

"L"
Capstan Stop (Ll

i
I

Lateral Swing
Acceleration (H)

Figure 4-2.

Shift to PB mode when the Slow/Still mode is cleared
(2-head system)
iSiow/Stlll)

(Release Processing)

----+I

& gt; I + iPB)
iT8i

,
I

;
-

Drum Sensor
IH.SW.P.1
fForced
Acceleration
f
"H"
(Ternary)
"L"
/
I

Current Limit
(Ternary)

"Z"

I
I

"L"

/

I

Capstan Reverse 5

/
,

I
I
1
I

-

"H"

/
I

I
I

3

"H" /
i

Capstan Stop
Lateral Swing
Acceleration (H)

1
I
I
I

I
I
/

I

"Z"

I

Figure 4-3.

50

Preset Value
Item

Symbol

SP

LP

To

Start M/M

13.8 ms

-

Tl

Forced acceleration M/M

16.6 ms

-

T2

Lateral swing acceleration
start time

18.7 ms

-

45.8 ms

-

-

T3

Lateral swing acceleration
M/M

-

T-4

Speed reduction M/M

12.0 ms

T5

Brake M/M

I

13.6 ms
I
-

T6

-

I

T8

Forced acceleration
release

/

I

T7

I

I

/

23.0 ms

-

-

Ts

Note: Head 2 is special for SP; therefore, Slow/Still M/M, etc. of LP is under study.
Table 4-1.

51

----I.?
-7
-----

I

T
n
I

5

I

I-i---

1

--f*)

7

i-L I

---

I-"
_----t

T

-

f
.f

-_
/
----

-

'
i

r

--f-r
n

..-_

-

i-i-L
--'
-;---

-r
i,
5
- ._ ------

a

52

--- _

J

i
*
_---- 2
5
ii

--I

Shift to PB mode when the SP Slow/Still mode is cleared
(4-head system)

Shift to PB mode when the LP Slow/Stiil mode is cleared
(4-head system)
(Release
Processing)

(Release Processing)
I

fSlow/.Still) I

--IPBI

(Slow/Still) -

I

I

Drum Sensor
(Head SW Pulse)

Drum Sensor
(Head SW Pulse)

I

I
I
I

I
I

Forced
Acceleration
(Ternary)

Forced
Acceleration
(Ternary)

I
I
I
I
I

"H"
8
," L"
I
I
I
I

I
Current Limit
(Ternary)

E

Current Limit
(Ternary)
I
I
I
I
I
I

"L"
Capstan Reverse

Capstan Stop IL)

"L"
#

I

t
I
I
I
I
I
I
I
I
I
I
I

"L"
5

"H"

I

I
I
I
I
I
I
I

Capstan Reverse

I

I
I
!
I
"H" /

"H"

Lateral Swing
Acceleration(H)

Lateral Swing
Acceleration(H)
i
I

(SP: H

AMP

I
= HSW) ;

{

I
I
I

"High-speed Switching"

Head Amp. Switching
WI

(LP: H A M P = m)

I
I
I
,

I
I
I

"High-speed Switching"

Head Amp SW

(LP)

(SP: CHROMA = L)
Chroma Rotary
Switching (SP)

- IPB)

"L"

I
I
I
I
I
I
I
I
I
I

Figure 4-5.

Chroma Rotation
^.., I. ..,

I
I
I

"Ii"
(LP: CHROMA = H)

I
I
1 (Shift to PB mode when the
' SP slow/still mode is clearea)

I
I

"High-speed Switching"

I\

;
l

(Shift to P8 mode when the
LP slow/still mode is cleared)
Figure 4-6.

Shift to REC/STOP mode when the SP Slow/Still mode is cleared
(4-head system)

Shift to REC/STOP mode when the SP Slow/Still mode is cleared
(4-head system)

(Release Processing)

(Release Prgcessing)
(Slow/Still) ____ +--*e (Ret or Stop)

(Slow/Still) _/_I (Ret or Stop)
I
gTa)

i _ (TWA

Drum Sensor
(Head SW Pulse)

I
I
I

Forced
Acceleration
( 1 ernaryj

"H"

I
I
I
I
I
I

Drum Sensor
(Head SW Pulse)

I
I

I
I
I
I
I

"H"

I
I
I
I

I
I
I

z
$j "L"

i

I
I
I
I
I
I
I
I
I
I

I

capstan stop IL)

Lateral Swing
AccelerationlH)

"L"

Capstan Reverse

I

"L"
i

I

" L"

"H"

I
I
I
I
I
I
I
I
I
I
I
I

!

i

Lateral Swing
Acceleration (H)

I
(SP: H A M P = HSW)
I
I
Head Amp SW
(SP)

Chroma Rotation
SW (SP)

54
"Z"

I

I

capstan stop (L)

I
Current Limit
(Ternary 1

I
I

" L"

Capstan Reverse

"H"

I

I
I
0
I

Forced
Acceleration
(Ternary 1

" L"

I
Current Limit
(Ternary)

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

i

;

I

I
I
I

I
I
I
I
I -

(SP: CHROMA = L)

I
I
I
I
I
I
I
Figure 4-7.

(LP: H A M P = m)

(Ii A M P = L)

" L"

Head Amp SW
(LP)

(CHROMA = HSW)

;

" L"

E-E (L)

I
1

I

I
I
I
I
"L"
I
I
I
(Shift to RECiSTOP mode when the
SP slow/still mode is cleared)

Chroma Rotation
SW (LPI

(
) "H"

I
I
I
I
I
I
I
I

(LP: CHROMA = H)
,~

I
I
I
I
I
I
I
I
I
I
I
I
I
I

I

E-E iL)

:
I

(CHROMA = HSW)

I
I
I

I

Figure 4-8.

"L"

/

I

I
I

(H A M P = L)

I

(Shift to REClSTOP mode when the
LP slow/still mode is cleared)

c
J

~
I

!

Preset Value
Item

Symbol

SP
14.08 ms

To

TI

Forced acceleration

03
._c
c"
,"

9.73 ms

18.94 ms

11.01 ms

23.04 ms

19.46 ms

23.81 ms

33.28 ms

' 1 1 . 7 8 ms

5.12 ms

12.29 ms

3.58 ms

Start M/M

T2

T3

M/M

Lateral swing acceleration
start time
Lateral swing acceleration
M/M

LP

-

2
T4

LL

Speed reduction M/M

T5

$

Brake M/M

-

T6

Speed reduction M/M

11.78ms

7.94 ms

1 2 . 2 9 ms

3.58 ms

2 3 . 0 4 ms

9.22 ms

(At Still On)

TJ

z
tz
;i,
CT

T8

Ts

Brake M/M
(At Still On)
Forced acceleration
release

:

-

-

Note: Head 2 is speciei for SP; therefore, Slow/Still M/M, etc. of LP is under study.
Table 4-2

55

5. TIMER CIRCUIT
5-l. The RH-lXO581GEZZ is a timer microcomputer LSI featuring the channel

SekCtiOn function

synthesizer tuner.
(VC-A103, Al 16, A125, Al 18, A508, A615, T620 Series and VC-A215H)
l

'
Terminal Allocation (RH-ix058 1 GEZZ)
Terminal Name

No.

Name

Name

No.

Terminal Name

vcc

1

P65

2 AUDIO OUTPUT CTL

P64

3 I EZ PROM CS

P63

/ 4 1E2

+5v

PROM

CLK

P 2 2 / 13 1 C T L FREQ. D I V . IC RESET]
P21

14

SECAM OSD PROHIBIT
INPUT

sin

/ 19 / SYSCON SERIAL DATA

P33

/ 20 1 CTL PULSE (1125)

I

tP30

23

AUDIO TUNER (H)

INTl

24

A/C PULSE

INT2

25 .-R/C PULSE INPUT

CNVss 2 6

GND

RESET 27

RESET -(L)

Xln

28

CLOCK INPUT

Xout

29

CLOCK OUTPUT

Vss 1 32 /
Figure 5-l.

56

GND

I

by a voltage

5-2. TERMINAL DESCRIPTION (RH-iX0455GEZZ: Voltage synthesizer tuner)
Pin No.

Description

Name

I/O (Type)

1

VCC

2

AUDIO OUTPUT CTL Control signal to switch the audio output between (L +R),
L, R and NORMAL.

3

E2PROM CS

4

E2PROM CLK

5

OSD
SK30

6

PWM OUTPUT

Tuning voltage PWM output. 14-bit resolution.

0 (C-MOS)

7

AFT MUTE

Output when the volsyn is in preset mode or when tuning
is being done.

0 (C-MOS)

8

BO

Band switching output for tuning

0 (N-CH)

9

81

10

OSD MUTEI
BLUE BACK

At 5V to be connected.

SO/E2PROM

Used for serial transfer between Timer and E2PROM.
Note that pin No. 5 (E2PROM SI/SO/OSD SO) is commonly
used as the OSD Control serial port.

0 (C-MOS)

0 (C-MOS)
0 (C-MOS)
I/O (C-MOS)

*

0 (N-CH)
0 (N-CH)
0 (N-CH)

OSD control serial terminal.

0 (N-CH)
0 (N-CH)

12

OSD CS-(L)

13

CTL FREQ. DIV. IC
RESET

Control signal to reset the CTL frequency dividing IC.

0 (N-CH)

14

SECAM OSD
PROHIBIT INPUT

Control signal,to prohibit the superimpose
receiving SECAM signal.

I

15

NORMAL (L)

Terminal commonly used for forced normal fL) output and
LR display mute (L) input.
(A mute signal is supplied via the N-CH open drain circuit.
On Hi-Fi models.)

' 16

function while

17

SYSCON READY-(L) Control signal for serial transfer between timer and systern controller.
SYSCON/TIMER CLK

18

TIMER SERIAL DATA

19

SYSCON SERIAL
DATA

20

CTL PULSE (1125)

21

INTERNAL COUNTER Clock count input for the timer. Connected to Pin No. 31.
Shortest pattern possible to be taken for connection.
CLK INPUT

22

VIDEO TUNER (H)

23

AUDIO TUNER (H)

.-

0 (N-CH)

I
0 (N-CH)
0 (N-CH)
I

l-second count source input for the real time counter.

Input switching control terminal.

I
I

0 (N-CH)
0 (N-CH)

57

Description

Name

' No.
in

I/O (Type)

24

A/C PULSE

A/C-shaped signal input for power failure detection. Power failure is identitied if there is no change in A/C pulse
for 35 msec. External interrupt at the rising edge.

25

R/C PULSE INPUT

Rising edge of R/C pulse is detected. External interrupt at the
rising edge to measure the interval between two rising edges
of R/C pulse.

26

CNVss

Connected to GND (OV).

27

RESET-(L)

All Clear i"s made when a voltage lower than 0.6V has
been put in for 2 psec or more after the supply voltage
reached the microcomputer' operating voltage (5V 2 10%).
s

I

28
29

CLOCK INPUT
CLOCK OUTPUT

System clock generating circuit built-in. System clock is
obtained by adding a ceramic resonance circuit as shown
below.

I
0

Xout

Xin

33 pF

33 pF

Figure 5-2.

30

CLOCK INPUT
FOR TIMER

31

CLOCK OUTPUT
FOR TIMER

Timer count clock generating circuit built-in. Timer count
clock is obtained by adding a.crystal resonance circuit as
shown below.

0

Xcout

Xcin

220kSl

22 pF

Figure 5-3.

32

vss

I

Connected

to GND (OV).

58

' No.
in

r

Description

Name

33

& lt; EY
& lt; EY
CEY
& lt; EY

Crystal adjustment output. Adjustment is made when the
microcomputer is reset. Half the crystal output (32.768
/b, "
-.,q;
KHZ) is given out with jumper provided.

C' ADJ.
tal

34
35
36
37

INPUT
INPUT
INPUT
INPUT

I/O (Type)

4
3
2
1

4 x 13 matrix is formed by Pin Nos. 41 thru 53 (S 1 thru
52). Jumper input or key input is made.

T
GFJ
Gil
Sl
s2

/

I
:

n

: :
s3
^.

-

s5
S6

Figure 5-4.

G10
Gil
Sl

T
I I,
1
I
!

s2

I
/

s4
s5
S6

I I
: ;
: ;
/

S?
S8
s9

/
/
I 1

n

n

Figure 5-5

38

VP

- 30V to be connected

-L
59

3

Name

' No.
in
39

'
AY (H)

40

VC

41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

S8
Sl
32
36
37
53
55
54
s9
SIO
Sll
512
s13
Gl
G2
G3
G4
G5
G6
G7
G8
G9
GIO
Gil

c

Description

110 (Type)

Output at "
H" while the PAY position is selected.

3 (P-CH)

Output terminals for fluorescent display tube drive segment signal and key scan strobe signal.

3 (P-CH)
Hi,gh withstand voltage

(Segment signal)
Segment signal output is timed with digit signal output at
Pins 54 thru 64.
a
510 j
;11
jl

u

r-7
1:

"
--i----

j2
j3

u

24

u

I'

1:

j5-lI-T
$6

n

n

r-l

l--l

I

uu

n

n

7,

r-i

j7

/

3

n

j9
I'
510 II)

n

511 -J----t

n

i:

n
n

j12

r-l:
l----i

S13

n
n
n
n

n

Figure 5-6.

Output terminals for digit signals to drive the fluorescent
display tube.

G7
G8
G9
GlO
Gil

1 1.72ms

GlIT

26.9w
Blanking time

Display duty =

96011s
1
11.72ms = 12.21-

Figure 5-7.

60

0 (P-CH)
High withstand voltage

5-3. The RH-lXO58OGEZZ and RH-lX0584GEZZ are a timer microcomputer LSI featuring the channel selection
function by a frequency synthesizer tuner.
WC-A61 5G(BK), GM(BK), YMIBK), VC-A215S(BK), VC-AlOBGV(BK1, VC-AlOGGVM(BK))
l

Terminal Allocation (RH-iX0580GEZZ, RH-iX0584GEZZl
Terminal Name

No.

Name

No.

Name

Terminal Name

Sl

3

Sl

s5

61

S6

SO

4

S8

54

60

S7

INT4

5

AC PULSE

s9

59

S8

SCK

6

SYSCONITIMER-CLK

SIO

58

S9

Iso

I

-4v

57

VPRE

1 SI

1 8 1 SYSCON SERIAL DATA

1 INT2 1

71 TIMER SERIAL DATA

11

j CTL PULSE (l/25)

Sll

53

s12

P13

12

SECAM OSD
PROHIBIT INPUT

s12

52

513

P20

13

CTL FREQ. DIV. IC RESE

s13

51

s14

P21

14

VCR (L)

Gil

50

110

P22

15

TUNER (H)

GlO

49

T9

G9

48

T8

G8

47

T7

G7

46

T6

G6

45

T5

1 P31 j 18 j

G5

1

44

1

43

I

42

/ P62 j

/ T2 /

j SCL

/ T3 /

G3

iH)

1 T4 /

G4

MIX

23

/ P63 ( 24 (
/ P40 / 25 /
RESET

j 39 j kEsET/

OSD MUTE

I

35

I P50 I

F i g u r e 5-8.

61

SDA
KEY

1

5-4. TERMINAL DESCRIPTION (RH-iX0580GEZZ, RH-iX0584GEZZ)

Name

' No.
in
1
2
3
4
51
52
53
58
59
60
61
62
63

S6
s2
Sl
S8
s13
s12
Sll
SIO
s9
S4
S5
S3
S7

Description

I/O

Output terminals for segment signals to drive the fluorescent display
tube.
-II'
6rs

0

q

5

nT,

j

~16~~

,I

I

I

241~s

:

I

P.
+-f+7rrs

I

((

I

I,

*

_! 7ps

se,_. j255~s
P

h

Figure 5-9.

5

AC PULSE

Used to detect service interruption. It detects service interruption when
there is no change in leading or trailing edge for more than 35 ms, and
the microcomputer goes into service interruption mode.
DUTY is 25% - 75%.
Vcc and this terminal are connected with diode.

I

VOD
RESET
Figure 5-l 0.

6

SYSCONITIMER CLK Used for serial transferring with the system controller.
Connected to the CLK terminal of system controller.
N-ch open

0

7

TIMER SERIAL DATA Used for serial transferring with the system controller.
Connected to the timer serial data terminal of system controller.
N-ch open

0

8

SYSCON SERIAL
DATA

Used for serial transferring with the system controller.
Connected to the syscon serial data terminal of system controller.
Schmidt trigger input with hysteresis characteristic.

I

9

R/C PULSE

Terminals to input pulses from optical remote control light receiving position.
Receive criterion of leading interval (T) of pulses is as follows:
T & lt; 0.4 ms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulse invaiid
0"
0.4 ms 5 T & lt; 1 .6 ms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic "
1.6 ms 2 T & lt; 3.2 ms .,........,............................ Logic " 1"
Pulse end
............................................
3.2 ms 2 T

I

10

SYSCON READY (L)

Used for serial transferring with the system controller.
Connected to the READY-L terminal of system controller.
Schmidt trigger input with hysteresis characteristic.

I

62

Pin No.

Name

Description

11

CTL PULSE (1125)

Signal to control real time counter.
When leading or trailing edge input of CTL pulse is performed with PCON
bit = "
1" and cassette-in bit = " , it makes internal counter UP for
I"
0.5 set with counter inversion bit = "
0" and DOWN for 0.5 set with
counter inversion bit = ' 1"
I
.
Counter inversion bit - Syscon serial data (S34) to show Normal rotation/inversion of the drum.

12

SECAM OSD
PROHIBIT INPUT

In case of SECAM input terminal = " , SECAM bit is " ; in case
H"
1"
ofSECAM input terminal = " , SECAM bit is " .
L"
0"

13

CTL FREQ. DIV. IC
RESET

Signal to reset l/25 dividing IC.
Reset terminal turns "
H" for 1 ms when zero reset of counter value or
dividing IC is performed.
4

0

14

VCR (L)

Syscon data VCR mode bit (S2s) = "
0" -t VCR(L) = "
H"
Syscon data VCR mode bit (S2s) = "
1" -+ VCR(L) = "
L"

0

15

TUNER (H)

0

.Inpunt switching control output terminal
TUNER mode

SIMUL mode

AUXI mode

AUXZ mode

H

H

L

L

Table 5-1.

16

PAY (H)/
TUNER-PCON

It corresponds to PAY when PAY jumper is present, and becomes tunerPCON output function when PAY jumper.is not present.
PAY(H) Displaying "+ 3" when selecting CH3 with AUS jumper present.
Displaying ' + 4" when selecting CH4 with AUS jumI
per not present.
Tuner PCON - Signal to control the tuner power supply for receiving
VHS code even if in "
POWER OFF" state during timer
stund-by.
Tuner PCON = "
H" when detecting VPS timer value
and performing VPS timer picture recording.

17
19

A-AUX (H)
A-AUX2 iH)

Input switching control output terminal.

0

0

TUNER mode

SIMUL mode

AUXI mode

AUX2 mode

A-AUX (H)

L

H

H

H

A-AUX2 (H)

L

L

L

H

Table 5-2.

18

MIX (H)

When EE bit = "
1" or EE bit = " , and SO byte = insert, this termi0"
nal is inverted regarding MIX KEY as valid.
When EE bit = "1" and SO byte = insert, this terminal turns " regardL"
ing MIX KEY as invalid.

0

20

21 PIN CTL (H)

Conditions for terminal = "
H"
I) EE bit = "
0"
2) During programmed OSD display
3)TSE bit = "
1"
In conditions other than the above ones, this terminal turns " .
L"

0

F' No.
in

Name

21

AUDIO-OUTPUT-CTL

Description

I/O

Audio output switching control signal

0

MODE

AUDIO-OUTPUT-CTL

Stereo (Main + Sub)

L

Left (Main)

High impedance

Right (Sub)

H

Forced NOR

L
Table 5-3.

It is in stereo mode when the microcomputer is reset.
22

NORMAL (L)

"
L.R.HiFi" display is put out when this terminal is ' .
IL"
Normal L terminal
L+R

H-L, R ON
L-L, R OFF

Input

L

H-L ON
L-L OFF

Input

R

H-R ON
L-R OFF

Input

NORMAL

L output

output

Table 5-4.

23

24

Used for serial communication with the VPS decoder. By converting L
to H at the ninth bit (ACK), it transfers "
H" or " from the receiving
L"
side to sending side.
"
H" is selected when the 1% bus is not used.

SCL

SDA
"
H" is selected when the 12C bus is not used.
With SCL being " , when the terminal experiences "
H"
H" + " conL"
version, data transferring starts; when the terminal experience " +
L"
"
H" conversion, data transferring ends.
1
2
3
4

Input terminals for jumper and key, which compose 4X matris.

25
26 '
27
28

KEY
KEY
KEY
KEY

29

NC

Open

30
31

MAIN SYSTEM
CLOCK

Main system clock is obtained.

4MHz
7gj
iI

ili30P
Figure 5-l I.

64

z30P

I/O

' No.
in

Name

Description

32

GND

GND (OV)

33
34

SUB SYSTEM
CLOCK

Sub system clock is obtained.

I
0

XT, /32.768k;r

22P

Figure 5-l 2.

35

OSD MUTE

Outputting "
H" when controlling OSD IC.
Displaying blue mute and emblem for OSD IC.
OSD mute terminal turns "
H" when displaying programmed content.

0

36

OSD CS (L)

Used for serialtransferring with OSD.
Connected to CS terminal of OSD IC.
Being "
L" only when accessing OSD IC.

0

37

OSD DATA

Used for serial transferring with OSD.
Connected to the SO terminal of OSD IC.

0

38

OSD CLK

Used for serial transferring with OSD.
Connected to serial CLK terminal of OSD IC.

0

39

RESET

The microcomputer is reset when RESET= " .
L"

40
41
42
43
44
45
46
47
48
49
50

Gil
GIO
G9
G8
G7
G6
G5
G4
G3
G2
Gl

Output terminals for digit signals to drive the fluorescent display tube.
P-ch open. Pull-down resistance built-in.,
I
4

3.06 ms

8th digit

,

digit

3rd digit
2nd
1 st digit
Key
timing

,

I

5th digit
4th

,

I
I

,

1 I
I)
II
, ,

I

I I
II

'
,

/
I

f

scan
I

I

I I
i ] , ,

digit
I
I

,

I
I

11
II

I

1 1 1 '
II
Figure 5-I 2.

T+
!/
= 24ops -w & 4-- 15ps
TOSP
= 255~s

Display cycle

= 3.06 ms

DUTY

= 1112.75

Digit signal cutting amplitude = l/16

65

0

Name

' No.
in

Description

I/O

54

NC

Open

55

MODE OSD (H)

This terminal turns "
H" during OSD output in OSD mode.

56
57

- 3ov
-4v

- 3ov
-4v
0

+

0

VDO

0

5v

- 3 o v

RDS. 1 EL
VFW
68kll
VLOAD
VSS

n7
Figure 5-l 3.

64

+ 5v

v,,( + 5v)

66

,

6. AUTOMATIC VOLTAGE SYNTHESIZER CIRCUIT
6-l. Terminal Description of Automatic Voltage Synthesizer IC. RH-iX0600GEZZ
WC-A615G(BK), GM(BK), YM(BK), VC-A215S(BK), VC-A103GV(BK), VC-AlOGGVM(BK))
l

Terminal Allocation (RH-iX0600GEZZ)
Terminal Name

No. Name

AT 5V

48 ADO

AFT-S CURVE IN

47

PlCl

NC

46

PlC2

NC

45

PlC3

T.A DATA

44

POAO

T.A CLOCK

43

POA 1

CS

42

POA2

CLOCK

41

POA3

DATA 110

40

Name No.

POBO

H SYNC

I 35 I HsvNcl

NC

MG

AFT MUTE

2

V-MUTE

28

PWMl

NC

27

PWM2

NC (AT 5V)

2

NC (AT 5V)

25

I

9 PWMO

6 PIBO
PlBl
Figure 6-l

67

Terminal Name

JUMPER INPUT

Not corresponding = 0
Corresponding = 1
AV 1 system = 0
Table 6-1.

Terminal to perform A/D conversion of pin @ input voltage
(analog data) and convert it into digital data.

VC-A61 5G . . . . . . . . D,
VC-A615GM, YM

VC-AlQ3GV
VC-A2155

......A

VHF f- Normal --+UHF

Figure 6-3.

Tuning (UHF, VHF) and Normal modes are identified with
pin @ input voltage.

68

' No.
in
7
8

Name
KEY-l
KEY-2

Terminal

Description

I/O

POD1
PoDo

Tr & 5va

Auto

Figure 6-4. KEY-l

'

TRI-)/
MT(-)

TR(+l/
WI-1

9
ee

'
T5"
@

4
Figure 6-5. KEY-2

With three pieces of SW, this terminal identifies MT (+ j and
(- 1 and makes VT up and down in Tuning mode; it identifies TR (+ 1 and (- 1 and changes tracking in Normal mode.
4

9
10
11
12

NC

PlD3
PlD2
PIDI
PIDO

13

AT 5V

VDD

Power supply input. 5+0.5V.

14

AT 5V

CE

Selector signal input terminal.
it is made High (5V) in normal operation.

15

NC (GND)

INT

16

GND

GND

17
18
19
20

NC

PlA3
PlA2
PIAI
PIAO

21
22

8MHz
8MHz

x0
Xi

23
24

NC

PlB3
PlB2

25

Bilingual IN (L)

PIBI

In case of " , bilingual display is lit.
L"
Connected to AT 5V because of no display.

I

26

Stereo IN (L)

PIBO

In case of " , stereo display is lit.
L"
Connected to AT !i.V because of no display.

I

27

NC

PWM2

28

V-MUTE

PWMI

Conditions for Video Mute.
l
When EE bit = "I"and there is no video signal, V-Mute
= "
H" is made.
l
When EE bit = " , V-Mute = "
0"
L" is made.
l When EE bit is changed from "1" to "
O" V-Mute = "
,
L"
is continued for 015 sec.
EE bit (" :PB, " :EE)
O"
1"
Mute when V-Mute = " .
H"

0

29

AFT MUTE

PWMO

"
H" is putted at PCON rising and Ch position changing.

0

I

GND

Terminal for system clock.
Oscillator of 8 MHz is connected to this terminal.

69

Pin No.

Name

Terminal

Description

i/O

30

PWM rmp

31
32
33
34

NC

R
G
B
BLANK

35

HSYNC

HYSNC

36

t-

VT. PULSE

VSYNC

VSYNC

37

SYNC DET

POB3

Terminal to input sync DET IC output and detect video signai. "
L" when H sync is present.

38

Bl

POB2

Band switching control output terminal.

39

BO

POBI

-

m

Waveform having experienced pulse width modulation
(PWM) according to 14 bit tuning data is outputted.

Input terminal for data to specify display point of character data.
Connected to GND as not used.

0

I
I
I

;

Table 6-2.

i/O

40

DATA i/O

POBO

41

CLOCK

POA3

42

CS

POA2

43
44

T.A CLOCK
T.A DATA

POA 1
POAO

45
46

NC

PlC3
PlC2

47

AFT-S CURVE IN

PICI

Terminal to input AFT voltage (tuning error voltage) from
IF pack.
it detects tuning point with AFT voltage.

I

AT 5V

ADO

A/D converter input terminal.

I

& lt;
4%

Terminal for serial transfer between the automatic voltage
synthesizer IC and E2PROM.
(CS turns "
H" only when accessing E2PROM.)

0
0

Used for serial communication
microcomputer.
Terminal for 12C bus control.

70

with

the

timer

6-2. ICI401 Automatic Voltage Synthesizer IC Functions
(I) Manual tuning function
l
Selection between UHF, Normal and VHF ca' be made with pin @ input voltage.
n
Switching is made with 3-position slide switch.
l
Manual tuning can be made by continuously pressing MT( +) and I-1 key. Fine tuning can be made
by pressing momentarily.
l
Data can be stored in E2PROM after tuning.
l
AFT mute is outputted when PCON is ON and at channel switching.
(2) Auto search tuning function
l
Tuning is made with sync DET IC output and AFT voltage.
l
Tuning is automatically made by pressing Auto KEY.
(3) FTZ specification correspon & nce
l
Detecting no sync, and outputting V-mute.
(4) Title OSD function
(5) DATE REC function
(6) Sound multiplex circuit control
Description of (4) - (6) is omitted as they are: not used in this model.

6-3. Description of tuning unit operation
(1) Auto search tuning operation
a) Start
When "
AT" key is pressed with CH Set SW being at VHF or UHF position, auto search tuning is started.
Tuning direction is restricted to up direction only.
b) Search route and search time
(When CH Set SW is at VHF)

BAND HYPER

Switching jumper A, 0

Switching jumper C, D

Figure 6-6.

(When CH Set is at UHF)
NOTE: Search time means the time
taken when there is no
station.

Figure 6-7.

71

c) Auto search

Stop point

- - A F T - H ( 0 . 8 4 V,,)

_

I
I
I

+a
k
I

_

_

I

_

_

_ AFL-L (0.4X/,,)

Range regarded as center of station

I

SYNC DET
Figure 6-8. AFT-S curve at searching

Fig. 6-8 shows AFT curve and the timing of synchronizing identification signal at searching.
AFT-S curve is fed into A/D input terminal pin @ of IC 1401. Higher section than (AFT-H), lower section than (AFT-L) and middle section in between are detected, and the range regarded as the center
of station is searched.
d) Automatic detection of station
@VT (IC 1401 pin @I) voltage is raised at fast speed until it is detected that synchronizing detecting
= "
L" (ICI404 pin @ SYNC DET) and AFT-S curve level (ICI401 pin @I) is higher than AFT-H
(0.84 Vdd).
@ VT is raised at slow speed until it is detected that AFT-S curve level (IC 1401 pin @) is lower than
AFT-L.
@With VT being lowered by minimal step, AFT-S curve level is detected becoming higher than AFTL. VT data at this time is " .
A"
@With VT being lowered by minimal step, AFT-S curve level is detected becoming higher than AFTLH. VT data at this time is " .
B"
(If no sync is detected during search of 1 - 4, it is switched to fast search.)
@The value of VT data (PWM) between "
A" and " is determined through operation, and outputted.
B"
(Middle value is employed to eliminate the error caused by other signals on AFT-S curve.)
PWM data of (A) +

PWM of (B) - PWM of (A)

2

= PWM of station center

@VT data and band data are stored in E2PROM (IC1402) at stoppage, thus completing tuning
operation.

0 _--------0 0
_-- - - A

8

VT

AFT-S CURVE

* AFT-H and AFT-L are identified by feeding ATF voltage
into pin @ of IC1401.

/

v,,=5.ov

SYNC DET
(IC 1404 pin @,I
Figure 6-9.

72

(2) Manual tuning operation
a) Start
l
When MT ( + ) or MT (- ) is pressed in preset mode, shifting to manual search mode is performed.
l
Change of constant value (AVT) is made during the first 300 msec, and in case of continuous pressing, continuous sweeping is performed.
b) Direction
Sweeping is made in the direction to raise VT with MT (+ ) being pressed; in the direction to lower
VT with MT (- ) being pressed.
c) Stoppage
l
Sweeping is stopped when MT (+ ) or MT (- ) is released, and VT data and band data at this time
are written into E2PROM. (Storing is made when KEY is released.)
l
If MT ( + ) and MT (- ) keJ are pressed together with other keys, VT data is not written. If other
keys are released and either of MT ( + ) and MT (- ) key remains pressed, and the other MT key
is released, VT data is written.

73

7. Y/C CIRCUIT
7-l. DESCRIPTION OF AN3248K OPERATION (IC201: Luminance Signal Processor)
7-1-l. Main functions
(I) FM modulation/demodulation
(2) Preemphasis/Deemphasis
(3) White Clip/Dark Clip
(4) Base Band Drop Out Compensater (With CCD 1 H Delay Line IC202)
(5) 1/2fH Carrier Interleave
(6) Noise Canceller
(7) Nonlinear EmphasislDeemphasis
(8) Detail Enhancer
(9) Line Correlation Noise Cancelltr,(With CCD 1 H Delay Line IC202)
(IO) Picture-Tone Control
(1 l)Y/C Mix
(12) FV Insert
(13) Edit
7-l -2. Description of function
(IC pin NO. whose IC REF NO. is not specified means pin NO. of IC201.)
(I) Base band drop out compensater
Base band (video signal) compensation after FM demodulation is made using CCD" (IC202) as IH
delay line. 2fsc outputted from IC501 pin @ is used as CCD clock.
As transmission throughout all bands of playback luminance signal is possible with CCD, it can make
more precise compensation than the system using glass delay line. While the glass delay line causes
switching noise when switching FM wave, CCD causes no such noise.
While the glass delay line needs two pieces of FM demodulator, CCD needs only one demodulator.
* CCD: Charge Coupled Device
(2) REC/PB switching
Switching to REC mode is performed with EE(L) signal at pin @ via D202.
wee= 5.OV)
Pin @ DC potential

Operation mode

O V - 1.25V

REC

2.25v - 5.ov

PB
Table 7-1.

(3) SP/LP switching
Controlled by DC potential of pin 0. At SP, 0204 is set to ON by SP (HI signal and pin @ is made
OV, thus performing switching to SP mode. In 2-head model (except VC-A215H), pin @I is directly
(Vcc = 5.OV)
connected to GND.
t

Pin @ DC potential

Operation mode

o v - 1.25v

SP

2.25V - 5.OV

LP
Table 7-2.

(4) 112 fH carrier interleave
In order to minimize crosstalk from the adjacent track at LP Flayback, carriers of CHI and CH2 are
recorded being shifted from each other by 112 fH (% 7.5 kHz) at LP recording. This conversion is performed by H.SW.P. fed into pin @I via R222. At SP, pin @ is made OV and carrier interleave is not
performed.
(5) FV insert
FV Insert at trick playback is.controlled by FV signal fed into pin @ as shown in the table below.
PB mode

(Vcc = 5.OV)

Pin @ DC potential

Pin @ Video output

4v - 5v

Sync tip level

2v - 3v

Gray level

o v - 1v

Through
Tabie 7-3.

74

(6) Line correlation noise canceller
CCD (IC201) is used as 1 H delay line. Line correlation noise canceller ON/OFF is controlled by pin
@ DC potential. It is set to OFF when this potential is lower than 1.25 V. Only at SP playback, 0206
is set to ON and pin @ is made OV, thus setting the line correlation noise canceller to OFF.
(7) Picture-Tone control
Controlled by DC potential applied to pin 0. At OPEN, it is fixed to the center, with the potential being
approx. 2.5 V.
(8) Edit (used only in some models)
To prevent deterioration of picture quality at dubbing, the detail enhancer is set to OFF at recording
and the function of the noise canceller is lowered and Picture-Tone control is negated (fixed to the
center) at PB.
At recording, it is set to ON. when pin @ potential is made lower than 1.25 V. At playback, it is set
to ON when pin @ potezial is made lower than 1.25 V.
7-l-3. Signal flow
(1) At recording
The video signal (IVp-p) fed from connector CD @ passes through the AGC AMP and SUB CLAMP
circuits after entering via pin 0, being sent to pin 0 and the ON SCREEN MUTE circuit. The ON SCREEN
MUTE circuit is controlled by DC voltage applied to pin 0. It exerts the function of character insertion
as an ON SCREEN circuit at REC, but this function is not used in the present model, and the signal
is sent through to pin @ with 2.0 Vp-p. This signal level is adjusted by R203 (EE LEV ADJ) externally
attached to pin 0. At PB, the ON SCREEN MUTE circuit exerts the function of FV insertion as a MUTE
circuit, controlled as described in 7-l-2(5).
The signal goes out of pin @ and passes through 3 MHz L.P.F. of FL201, where only luminance signal
is taken out, being fed into pin @. The signal fed into pin @ is mixed with the signal passed through
PRE AMP and H.P.F. and experiences detail enhance at the DE (Detail Enhancer) MIX section. The
characteristic of detail enhancer is determined inside the IC. The signal having experienced detail enhance goes out of pin @ and enters pin 0, experiencing sync tip clamping at the CLAMP circuit, after
which it is sent to the NL (NON Linear) MIX section. It is mixed with the signal passed through the
H.P.F. + LIM -+ FM Cl section, experiening non linear emphasis, then entering the main emphasis
circuit. The characteristic of non linear emphasis is determined inside the IC. At the FM Cl section,
signal DC voltages of CHI and CH2 are so controlled that they are shifted from each other by approx.
2.3 mV for l/Z fH carrier interlieve in LP mode. After entering the main emphasis circuit, the signal
experiences preemphasis and undergoes white clip and dark Clip, then going out of pin @ and passing
through R204 to enter pin @. White clip level is adjusted by R206 so that overshoot of white peak
is 80 ? 4%. Dark clip level is of no adjustment and so controlled that 50 f 10% level is achieved.
The characteristic of preemphasis is determined by the values of R228, C222 and C259 externally
attached to pin @, and of R229 and C223 between pin @I and pin 0.
The signal fed into pin @$ is subject to FM modulation and then sent to pin @ with 1 Vp-p. Carrier
frequency (3.8 MHz) is adjusted by R2051 deviation adjusted by R204. After going out of pin @, the
FM signal passes through REC EQ (H.P.F.) and experiences level adjustment at R208, after which
it is mixed with low frequency converted chrominance signal at 0209 and sent to the HEAD AMP
via 0210 (emitter follower).
(2) At playback
The PB FM signal (4-head models: CE@, 2-head models: CEO) outputted from the HEAD AMP enters
pin @ via PB EQ. Then, after passing through D.O.C.Bnvelop detector and double limiter, it enters
the demodulator, experiencing demodulation to video signal, then entering pin @ via SUB L.P.F. D.0.C
detection level is determined inside the IC. D.0.C period is determined by C225 externally attached
to pin @I,.
The video signal comes from pin @ passes through 3 MHz L.P.F of FL201, FM carrier component
being eliminated, and enters pin @I, after which it passes through Pre Amp and enters the main deemphasis circuit, undergoing deemphasis, and then goes out of pin 0 and enters pin @I,. The characteristic of deemphasis is determined by the constant of the component externally attached to pins @ and 0.
The signal fed via pin @I is sent to the subtracter and usually to pin @ and LNC (Line Correlation Noise
Canceller) MIX and NL (Non Linear) Pre Amp. The signal fed into pin @ passes through IC202 CCD
IH delay line, clock component being eliminated at L.P.F., and then enters pin @ after experiencing
level adjustment at R202. When drop out is detected, the delayed signal supplied via pin @ is sent

75

to pin @ and LNC MIX NL Pre Amp. Usually, the signal supplied via pin @ and the 1 H delayed signal
supplied via pin @ enter the subtractor, where difference component is extracted. The extracted component enters the LNC MIX section, where it is mixed with the main signal from pin @,.thus line correlation noise cancel being performed (in LP mode only). In case of drop out being detected, the line
correlation noise canceller does not function. The signal passed through LNC MIX NL Pre Amp goes
out of pin @ and enters pin @I, then being clamped. The clamped signal enters the NC (Noise Canteller) MIX section, and at the same time a portion of the signal is fed back to LNC MIX NL Pre Amp
via H.P.F --I Limiter + FM Cl, where it is subject to non linear deemphasis. At the NC MIX section,
the signal passed through H.P.F -I Limiter -+ L.P.F. experiences MIX and Noise Cancel. Then it goes
into PB C-MIX via the APT (Aperture) CTL section, where it is mixed with playback chrominance signal, and sent to pin @ via AMP -I SUB CLAMP -I MUTE -I AMP.
The output level of pin @ is adjusted to 2.0 Vp-p by R201 externally attached to pin 0. At the MUTE
section, FV insertion at trick pla$ack is performed.
7-2. DESCRIPTION OF TA8644N OPERATION (IC501: Chrominance Signal Processor)
7-2-1. Description of function
I
(IC pin NO. whose IC REF NO. is not specified means pin NO. of IC501.)
(1) REC/PB mode switching is controlled by DC potential applied to pin @. PB mode is selected by applying ALPB 5V via D502. Switching to PB mode is performed with the maximum of more than 4.0 V.
(2) PAL/MESECAM switching is controlled by DC potential applied to pin @ as shown in the table below.
(Vcc = 5.OVI
Pin @ DC potential

Operation mode

3.3v - v c c

MESECAM

ov - 0.9v

Not used

NTSC *

1.5V - 2.7V

l

PAL
Table 7-4.

(3) SP/LP switching is controlled by DC potential applied to pin @ as shown in the table below.
(Vcc = 5.OV)

(4) CH switching (CHROMA ROTATION switching) is controlled by CHROMA ROTARY signal DC potential applied to pin @ as shown in the table below.
WCC = 5.OV)

-1

,
Pin @ DC potential

CH

Chroma rotation (at recording)
MESECAM

PAL

NTSC *

2.w -vcc

CHl

Shift stop

Shift stop

Advanced 90" per 1H

OV -1.6V

CH2

Delayed 90° per 1H

Shift stop
II
Not used

Delayed 90" per 1H

l

Table 7-6.

(5) Composite synchronizing signal is fed into pin @ with positive approx. 4.7 Vp-p. Threshold values
are shown in the table below.
WCC = 5.OV)
Input level

Threshold value

H

2.7V

L

1.7v

Table 7-7.

76

n

7.7

"P-P

7-2-2. Signal flow
(I) At recording
The video signal (I .O Vp-p) applied to pin @ goes out of pin @ after passing through the switch, after
which it passes through 4.43 MHz B.P.F. (FL502), only chrominance signal band being taken out,
then entering pin 0. The chrominance signal fed into pin @ is amplified at ACC AMP so that burst
signal level is constant. Then the signal enters the main converter, where it experiences low frequency conversion to 627 kHz, and enters pin @ via the colour killer. The low frequency converted chrominance signal fed to pin @ passes through 1.4 MHz L.P.F (FL501 1, undergoing level adjustment at
R504, and then enters the emitter of Q209 via Q503 (emitter follower), where it is mixed with recording luminance signal.
(2) At playback
The PB CHROMA signal (4Jread models: Connector CE@, 2-head models: Connecter CEO) outputted from the head amp is amplified at 0507. Then it passes through L.P.F., low frequency converted
chrominance signal being taken out, and then enters pin @. The signal fed into pin @I is amplified
to a constant level at the ACC amp, sent to the main converter, where it experiences frequency conversion to 4.43 MHz, and then fed into pin @. The signal fed to pin @J passes through 4.43 MHz
B.P.F. (FL502), being amplified at 0504, and then enters the emitter follower of Q505. In the case
of 2-head models, the output of this emitter follower enters the 2H comb filter via C534. In the case
of 4-head models, this output is sent to Q5551 and DL5551 (1 H glass delay line) and the output of
DL5551 (1 H delayed signal) is supplied to the base of 05553. Only when LP(H) signal from connector
CC@, H.AMP.SW signal from connector CA@ and FV CTL signal from connecter CA@ are all " ,
H"
that is, when the output of head amp is switched to SP HEAD side in LP trick mode, 05555 and Q5554
simultaneously turn on and Q5553 functions, by which the 1 H delayed signal outputted from DL5551
is amplified to the same level as at entering DL5551.
In this case, Q5552 turns on and Q5551 off, and the amplified IH delayed signal is sent to the 2H
comb filter of DL501. In other cases, 05552 turns off and Q5551 on, and the signal before being
1 H delayed enters DL501. This switching is performed to prevent colour disappearance caused by
discontinuous phase of burst signal at Still, Slow and Double Speed Playback of LP. In 2-head models,
therefore, this circuit is not used and the output of 0505 enters DL501 via C534. In 4-head models,
C534 is not used. The signal fed to DL501, with luminance signal interleaved in the chrominance signal band and crosstalk from the adjacent track being eliminated, enters pin @J, after which it is sent
to pin @ via amp and the colour killer. The playback chrominance signal outputted from pin @ is applied to pin @ of IC201 after passing through the emitter follower of 0506, and mixed with playback
luminance signal.

77

OVERALL BLOCK DIAGRAM
(FOR 2-HEAD MODELS)

AUDIO
IN
(2. 6PINI

VIDEO
IN
(20PINl

SYSTEM
CONTROL

TIMER

DEMODULATED
LIN
UHF/VHF
TUNER
6
Z~ODULATOR
YIXER

I-

(DIN TYPE1

RF
CONVERTER

1

REF 50Hz

VIDEO OUT
flOPIN

AUDIO OUT
(1. 3PIN)

*
A.HlP. 81

SIGNAL

1

PATH REC MODE

79
.

.I-

., __--__--.- _.- _^

f

PLAYBACK

H.SW.P

PHASE
COWPARATOR
ORUN CTL

MOTOR DRIVE

;
HEAD

MECHANISH

'
TCHINI

MOTOR

IP. SYNI

DRIVE

CAPSTAN F6

CTL SIGNAL t-PPB

---+ REC

80
-

I.

". - ^.__.__

OVERALL BLOCK DIAGRAM
(FOR 4-HEAD MODELS)

ANT

-

9

AUDIO
IN
(RCA TYPE1

VHF/UHF IN
(DIN TYPE)

I

VIDEO
IN
(RCA TYPE1

OEH~OULATOR

J=8--/

I

I

LUMINANCE
PLAYBACK PROCESS

VIDEO OUT

VIDEO OUT
[RCA TYPE)

REF 50Hz

LINE
A,UOIO OUT
[RCA TYPE1

K602

*SIGNAL PATH REC MODE

81

I

SIGNAL

CAPSTAN
0.0 MOTOR

MOTOR

- i
1-l

DRIVE

I
CAPSTAN
NOTOR DRIVE

CTL HEAD(t)

PB

KZCHA..A.,.T
CONTROL
SIGNAL

AU
9

CAPSTAN

F6

SYSTEH
CONTROL

CONTROL
SIGNAL

II

I'
1

CAPSTAN F6

I

/

I
CTL SIGNAL -Pi3

---+ REC

a2

AUDIO BLOCK DIAGRAM

TP601

TPSOP

C626

ICBOi 6A7765AS
[Audio Signal Processor1
R605

HH
AUDIO
ERASE
HEAO

7

*
6NO

5

R630
BIAS
CURRENT
AOJ

_ _ _ _ _ _ ~I

I

V

REC H SW

FULLL
ERASE
HEAO

R620

i

21 PIN JACK
AUDIO

IN

$ R6607

KS02

AR
10

TUNER-H

KS02

ICBOl
EE-L

41

EE-L

1

1614

A

A

K602

ICE01
/,
'441 PB AUOIO-H

K602

R620
z

BIAS CTL-H

KS01
PC 9v

PC 9v

BIAS CTL
9v SW

K601
AEC-H

6

BIAS

1

cc
CTL 9V 15

oa80 i
8809

1-r

84
-- -. .- _.

_

-'

HEAD AMP BLOCK DIAGRAM
(FOR 2-HEAD MODELS)

IC301
VHIBA?252S/-1
HEAD AMP

Jr-

V.HEAD

TP302

TPJOi

m
R306

R305
+

c307

T

85

C3lQ

I

A
17

d.

I

I

I

CE

TO
CHAOHA
BLOCK

XR

CE
BIAS

CTL

9V

2

HEAD AMP BLOCK DIAGRAM
(FOR 4-HEAD MODELS)

LP

C316
-

S
H
4

2'

-

rtr

m

13305

(1306
AEC

SIGNAL

SW

PATH REC MODE

87

/I

I

C323

-

-

C324

CHROHA AMP

-k

R319

II

XA

TO
CHAOWA
BLOCK

XA

IC301
(VHIAN33llK/-11
HEAO AMP.

CE

SYSTEM CONTROL BLOCK DIAGRAM
ICBOl SYSTEH CONTROL

TO AUOIO.HEAO
Y/C CIRCUIT

AHP

BIAS
CTLIHI

LOM7IN6
FM0 CTL
AUDIO WTE
0602

TO AUDIO CIRCUIT

VCR 5%
6EN.
08804

TO RF
CONVERTER
a

LOADING
RVS CTL

AUDIO
MUTE
IL)
4

I

I--

+

VCRILl

I
PB
AUDIO
IH)

TO AUDIO CIRCUIT

'

POWER
CTL(L1
SERVO
S.CLOCK

0953 0954
0955 0966
TO AUDIO.
Y/C CIRCUIT

FROW

EE IL1

SYNC.

Y/C CIRCUIT

TO HEAD ALIP
Y/C CIRCUIT

TO SERVO

SERVO
S.DATA

OET(Hl

AL PB 5V

CAPSTAN
ULILI

AL PB SV
EN.
RI3805

1

4

I

AL PB IL1
CAPSTAN
PU CL1

I

CIRCUIT

SEARCH
(Ll

CAPSTAN
CTL

CAPSTAN
RVS IHI

OAUM
CTL

TE

AS
I

I

I
,.T REAOYILI
FV
i.T DATA

.S DATA

BLOCK DIA6RAM.

10

T.S CLOCK

10

r.s CLOCK

BRAKE
SOLENOID

/

ICE02
LOADIN
DRIVER

LOADIHG
FWO CTL

" OTOR

03

10

2

LOAOING
HOTOA

LOIOING
UQ

LOADING
RYS CTL

CAPSTAN
MOTOR

SERVO
S.CLOCK

_I

AU
CAPSTAN MOTOR

SERVO
S.DATA

CAPSTAN
UOTOR
DRIVE

H
I

CAPSTAN
UL(L1

CAPSTIN/
DRUM
SERVO
CIRCUIT

b

mu!4
HOTOR

CAPSTAI
PUlLI
I

AN
CAPSTAI
CTL

l

CAPSTAI
RVS IHI

DRUU
UOTOR
DRIVE

ORUW UOTOR

l

mwl
CTL

TO Y/C CIACUIl
AT 172

YF
BRAKE
SOLENOI

BRAKE
SOLENOID
DRIVE

BRAKE
SOLENOID

1
Y

SAFETY DEVICE BLOCK DIAGRAM

SYSTEM

CONTROL

IC

START
SENSOR

EN0
SENSOA

CAM SW

*

REEL
SENSOR

CASSETTE SW
H.SW.P

RBOOB
22K

DEW DET
0006
atlo

DEW SENSOR

EXCEPT VC-A215S ~BKl.A103SVlBK~.Aii6s/S
(EKl.Al030 (EK) /R (BK).
A6156 IBKI /6H (BKI /S IBKI /SMlBK) /YM lBKl.TN6230H IOKI

91

I
I
1
I
I
I
I
,
1
1
I
I
I
I
I

IEW
SENSOR

5V

START

ART
NSOR

START
SENSOR

*

SENSOR

3

END SENSOR

d,.
MA
IO
.NSOF

EL
NSOR

END
SENSOR

4

f
'

TU REEL PULSE
WAVE FORM
AMP
0808

*

SW.P

DRUM SERVO
CONTROLLER

dT

7

DRUM
P6

92
,__ "
^---

DRUM SERVO BLOCK DIAGRAM

PC 5v
FROH
Y,c SLOCK

COMPOSITE

SYNC
IC701
DRUM/CAPSTAN
SERVO CONTROL

/

-T
TRK.M.W

PHASE

01

-

c71t I

.L;F;

'
P701
I.SW.

fH REVISION

P6 W.H
R740

PCSV

-

0

:

* '
I

A'71t
L
-

I

r
r-

FROM
Y/C BLOCK
R717
vvb
.

r

4
4

AN
R711

TO CAPSTAN MOTOR

R7iD

I
XC702 2.SV SEN

R767

L

L--

93

r - -- - - - -

t __--

N.F.B

TWO DIFFERENTIAL
16.
ND

ANL6.
SND

r---- -----___--~_ -.A
DRUM MOTOR DRIVE CIRCUIT

POSITION
/

HALL 1
I

6
1
\

x 5"

DAUU MOTOR
2 PHASE DC BRUSHLESS YOTOR

P

MAIN COIL B-2 ]

1

I

IC701
DRUM/CAPSTAN
SERVO CONTROL

r!T
MODE
RET.

SP

TO SYSTERCONTROL.Y/C.AlJOIO
BLOCK

LP

17'1
l/N

------c

PC 5v

PB CTL

CTL DUTY
DET.

CTL DUTY OET.
TO
INDEX/
.
LINEAR COUNTER
BLOCK

_ _ &
~
I- - - -

1-1

16

15
14

I
I
I
1
I
I

I

L__-__-------_--...

96

TIMER BLOCK DIAGRAM
(VC-A103GV(BK), A215S(BK), AGISG(BK)/GM(BK))

(9. IV)
'
PRE

2T

/LOAD

INTTPG
NTSIO
I

F
c

1
I

INTERFASE

INTERRUPT

P

i!

TB
9 COUNTE RESET ] 9

TO MAIN
CIRCUIT
COUNTER 113)

*05002 ~05001 f 05003

I

ROM
PROGRAM
MEMORY
6016XEBit

'
50
'
43

r
S & gt; W50 3 1
-cli,
OSD
IS41

R5001

SW5002

VPS
05009

& gt;

05006

iwa101

SW8107

05019

swaio3
PLAY
TO
KEY

- E

KEY

2

7

1 a

97

R5002

'4 2

-

'4 1
'4 0
1

PORT4

/
PPO
TIMER/PULSE
GENERATOR

INTTC
FIP
CONTROLLER/DRIVER

TIMER/EVENT C O U N T E R

/

/

j-----,TI3/PHO,

I

A
RAM
TER (13)
I

1

I

AT
8'
1 INTW

AC PULSE

jFX/2"

S.T OATA

ATSV

'
a

TO SYST E M
- CONTROL
CIRCUIT

TIMER BLOCK DIAGRAM
(FOR 4-HEAD MODELS)

TO
SYSTEM
CONTROLLER

-?

ul

P

G

P
1

REH
SW8104

SW8108

"
1

REC

CLOCK
SW5003

OCH
05014

/o-l

CH-DOWN
SW5002
/

moo4
47K
!

A500
47K
OS0
D5Oil

12H
II5013

LP
05017

R'
5002
4 7K

CH-UP
SH500 1

YHF - - - + - - - U H F
NORMAL

R5001
47K

ACL
SW5020

VLOAO Vnn
--

I

4

-___
:MER
1ntmt

vss W'ISS

RESE
-

AS'

P5

P2

P3

25

TO MAIN
CIRCUIT

95002
17K
TA
3

AT
OS0 cs IL)

3

REMOTE
CTL
RECEIVER

100

INFRARED
RAY
SIGNAL

AN3248KINK PB LUMINANCE SIGNAL LINE BLOCK DIAGRAM
LNC OPEi3ATION(on at Lp pa)
BY DC VOLTAGE AT PIN @

L

FAOH
SYSYEH CTL

Ll

l3oomvP-Pl

_
,.
9

,n
x-

CB *
IRHAL

I
L

I

(ON THE OPERATION

,,,I~

(300mVp-PI

1

I
APT
CTL

NC
HIX

1

,

i-1
L.P.F

IlVp-PI

PB CHROMA
iPOP 0506

$4

I & ;;~~;;~;::

BURST BOOmVp-p
)

SP

SW

r----------------___---------------~
I
I
I
I

ONYL
VC-A615!4T/E.
Ali6E/W.
AiiBD.A5OBDT.
8322N.B377N

AX
19

nn

SP (HI

* CCO : Charge

Coupled

Device

PE FM

L

1350mVp-pi

1260aVp-p)

/

i

OOUBLE
LIH
i

.

OEM

i
SUB
L.P.F

_

*

T

,
R201
PB LEV AOJ.

Xote:ALL
YODELS

terminal

Signal levels

we typical

values

LEAD TO 6ND

LY 4-HEAD MOOELS 6 VC-A215H
--__---------------____

17% INTERLEAVE

102
_.-.

.-____.-_._-,- I_--- l_l_

AN3248K/NK REC LUMINANCE SIGNAL LINE BLOCK DIAGRAM

CARRIER I

h

l'
\l

I
I

REC

.----I=
iL)

R203
EE LEV AOJ

n

ONLY VC-A6i5UT/E.AlI6E/X,
Ali6D.A506DT.
8322N.Fl377N

LP

ON

(H.S.Pl

,
ONLY 4-HEAD MODE
--------;---------EN CTL w
L------____--__________
AY
30

AY
27

27

SYNC

OUT

SO

To
SEAVO BLOCK

FL201

CD
SIDE0 IN

COMPOSITE

E
I
I

Q
H.P.F

3.6V--------

2.sv-----

(l.OVp-PI
3.7v -------_

(IVp-P)

*

103
._. __

.~.^

-

.~~.

.~ .- . . . . - _. _-__ - .._-. -.-----

;-.

LNC OPERATIONion at LP P91
BY DC VOLTAGE AT PIN @
CARRiER INTERLEAVE

I

/

cc

AX

REC

PB

FROM
SERVO BLOCK
rlO:4-HEAO
i:Z-HEAD

MODELS
MODELS

.;:I:
ONLY 4-HEAO MODELS 6 VC-A215H
-------------------------~
3

SP IHI
------- ---- -----__,

0
ERVO BLOCK

CLAMP

;
,

H.P.F

8204
SP sn

PB sn

/

R206
.IP ADJ.

,---_A
I
t
;
,

*

AL

PB

5V

'--------7
FROM
SYSTEM CTL

i

I

I
ONLY 4-HEAD MODELS
6 VC-A215H .------- -.AI
L_-_---_______-------------

FM C.I.
IS?/LPl

NL
MIX

MAIN
EHPH
R204
DEV.ADJ.

t

I

I

L
/ x

---GJ

/

(lVP-PI

2,3v ------ -_

FROM
SYSTEM CT!.

14

I

I

2.0v ----- iij

+A-

-T

I

\

IlVP-PI

,A;, I~ -------fl
l-J--h-

2.3v

-wf

-----

NotcALL

terminal

signal

2.OV

levels we tYPiCa values.

TA8644N PB (PAL SYSTEM) CHROMA SIGNAL LINE BLOCK DIAGRAM

BURST 3BmVp-p
G506

ToZ$++

,

FL502

,

ICE01

BURST SOOmVp-p

KILLER
DET

/

/

I

I

4

+
B-ID
DET

1'

:

S-IO
LOGIC

SW
t

To bring the forced calaur mode.
place the slide switch
Ian the operation PHI31
at the PAL 10~ COLOURI position:
now pin @becomes 'H'level.

f

$
AI'C
DET

1

/r;\

-

COUNT
DOWN
A

PULSE
GENE

*

TO PINQof
IC202lCCD~

8509
APC SW
RF!01

APC ADJ.

m
c-------

Cl3
1441

AW
7

CB
COHPOSITE

SYNC IN

7

105

AH
*

I9MHZ

I II T " ccnvn

PI " I-Y

i

T

I

H/A SY

AX
LP IH1

BURST BGODVD-p

FL502

16

FAOH
SYSTEM

CTL
I
I
L---_____-__L____-_-_____________L______-----------~

I
,
I
I
I

b
'-------1-

XA

MAIN
CONY

PB

CHROHA

6

FROM
H/A BLOCK

\

L.P.F
-

\
BURST lSOmVp-p

NotcALL

terminal signal levele are typical values.

U:NTSC

106

e

TA8644N REC (PAL SYSTEM) CHROMA SIGNAL LINE BLOCK DIAGRAM

I* Pin @ is used 3s an E

CARR
BAL

AV
5

VIDEO IN(C)

AMP

-

MAIN
CONY

-

KILLER

*

SW

-

FL502
t

.

To bring the forced
colour mode. place
the slide switch

I

c
SUB

CDNV.

Note:ALL

terminal

signal levels

are typical

$ +
90'
ROTATION

values.

FROM
SYSTEM

CTL

'

CHROMA.AOT

CTL

I4

9
P

AM
FROM
SYSTEM

A

CB

AU

Cl?
AL PB 5V

14

/

c
\

is used as an EEIRECl/PB

selector

terminal

too.)

I

II

R504
REC.C.LEV
ADJ.

f
B-ID
LO6IC

EXCEPT
VC-ASlSX/NZ/K,
ABlSWT/HH.

sn-A

,------_-___-_,
I
xc5501
(8170071
:
I
I
I
I

i

A

f
COUNT
DOWN

-

rh

FL5501
----------------~~~

I(
-

0
TO PIN@of
IC202(CCD)

0509
CB
7

AH.
COMPOSITE SYNC IN

5v -t
L
3-f-i

108

TO SERVO BLOCK

7

--____A

AUTO VOLTAGE SYNTHESIZER BLOCK DIAGRAM

r

I

109

_ -_. . ..__ - .--l_l ____.__

----. . . . . .

I

I

.-

,-

Printed in Japan

_

___)_-._
.

..


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