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STC90C51RC/RD+ series MCU
STC90LE51RC/RD+ series MCU
Data Sheet
Update date: 2011-7-26
STC MCU Limited
STC MCU Limited.
CONTENTS
Chapter 1. Introduction ................................................................ 6
1.1 Features ..................................................................................................6
1.2 Block diagram ........................................................................................7
1.3 Pin Configurations of STC90C51RC/RD+ series MCU ........................8
1.4 STC90C51RC/RD+ series Selection Table ............................................9
1.5 STC90C51RC/RD+ series Minimum Application System ..................10
1.6 STC90C51RC/RD+ series Application Circuit for ISP........................11
1.7 Pin Descriptions ...................................................................................13
1.8 Package Dimension Drawings..............................................................15
1.9 STC90C51RC/RD+ series MCU naming rules ....................................19
1.10 Reduce the Electromagnetic Radiation of MCU Clock (EMI) ..........20
-- Three Measures
.................................................................................................. 20
1.11 Super Low Power Consumption -- STC90Cxx Series MCU ............21
Chapter 2. Power Management and Reset ............................... 22
2.1 Power Management Modes ..................................................................22
2.1.1 Idle Mode .............................................................................................................23
2.1.2 Stop / Power Down (PD) Mode ...........................................................................24
2.2 RESET Sources ....................................................................................30
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
Reset pin ..............................................................................................................30
Software RESET..................................................................................................30
Power-On Reset (POR)........................................................................................31
Watch-Dog-Timer ................................................................................................31
Warm Boot and Cold Boot Reset .........................................................................35
Chapter 3. Memory Organization ............................................. 36
3.1 Program Memory .................................................................................36
3.2 Data Memory ........................................................................................37
3.2.1 On-chip Scratch-Pad RAM ..................................................................................37
3.2.2 Auxiliary RAM ....................................................................................................39
3.2.3 External Expandable 64KB RAM (Off-Chip RAM) ...........................................46
3.3 Special Function Registers ...................................................................47
3.3.1 Special Function Registers Address Map ............................................................47
3.3.2 Special Function Registers Bits Description .......................................................48
3.3.3 Dual Data Pointer Register (DPTR) ....................................................................51
Chapter 4. Configurable I/O Ports of STC90xx series ............ 53
4.1 I/O Ports Configurations ......................................................................53
4.2 I/O ports Modes ....................................................................................54
4.2.1 Quasi-bidirectional I/O ........................................................................................54
4.2.2 Open-drain Output (P0 ports are defaut to this mode after reset)........................55
4.3
4.4
4.5
4.6
4.7
4.8
4.9
I/O port application notes .....................................................................55
Head File/New SFRs Declarations, P4 of STC90C51RC/RD+ series .56
P4.5/ALE pin of STC90C51RC/RD+ series 90C version ....................58
Typical transistor control circuit ...........................................................59
3V/5V hybrid system ............................................................................59
I/O drive LED application circuit .........................................................60
I/O immediately drive LCD application circuit....................................61
Chapter 5. Instruction System ................................................... 62
5.1 Addressing Modes ................................................................................62
5.2 Instruction Set Summary ......................................................................63
5.3 Instruction Definitions ..........................................................................67
Chapter 6. Interrupt System .................................................... 104
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Interrupt Structure ..............................................................................106
Interrupt Register ................................................................................108
Interrupt Priorities ..............................................................................115
How Interrupts Are Handled ..............................................................116
External Interrupts .............................................................................117
Response Time ..................................................................................121
Demo Programs about Interrupts (C and Assembly Programs) .........122
6.7.1
6.7.2
6.7.2
6.7.2
External
External
External
External
Interrupt 0 (INT0) Demo Programs (C and ASM) .............................122
Interrupt 1 (INT1) Demo Programs (C and ASM) .............................126
Interrupt 2 (INT2) Demo Programs (C and ASM) .............................130
Interrupt 3 (INT3) Demo Programs (C and ASM) .............................135
Chapter 7. Timer/Counter........................................................ 140
7.1 Timer/Counter 0/1 ..............................................................................140
7.1.1 Special Function Registers about Timer/Counter 0/1 ........................................141
7.1.2 Timer/Counter 0 Operational Mode (Compatible with traditional 8051 MCU) ........ 143
7.1.2.1
7.1.2.2
7.1.2.3
7.1.2.4
Mode 0 (13-bit Timer/Counter) .......................................................................................143
Mode 1 (16-bit Timer/Counter) and Demo Programs (C and ASM) ...............................144
Mode 2 (8-bit Auto-Reload Mode) and Demo Programs (C and Assembly Program) ...148
Mode 3 (Two 8-bit Timers/Couters) ................................................................................150
7.1.3 Timer/Counter 1 Operational Mode...................................................................151
7.1.3.1 Mode 0 (13-bit Timer/Counter) .......................................................................................151
7.1.3.2 Mode 1 (16-bit Timer/Counter) and Demo Programs (C and ASM) ...............................152
7.1.3.3 Mode 2 (8-bit Auto-Reload Mode) and Demo Programs (C and ASM) .........................156
7.2 Application Notes for Timer 0/1 in practice.......................................158
7.3 Timer/Counter 2 .................................................................................159
7.3.1 Special Function Registers about Timer/Counter 2 ...........................................159
7.3.2 Timer / Counter 2 Operational Mode.................................................................161
7.3.2.1 Capture Mode ..................................................................................................................161
7.3.2.2 Auto-Reload Mode ..........................................................................................................162
7.3.2.3 Buad-Rate Generator Mode and Demo Program ( C and ASM).....................................163
7.3.2.4 Timer 2 as Programmable Clock Output and Demo Program (C and ASM)..................170
7.3.2.5 Demo Program of Timer 2 as Timer mode (C and ASM) ...............................................173
Chapter 8. UART with Enhance Function ............................. 177
8.1 Special Function Registers about UART............................................177
8.2 UART Operational Modes .................................................................180
8.2.1
8.2.2
8.2.3
8.2.4
8.3
8.4
8.5
8.6
8.7
Mode 0: 8-Bit Shift Register..............................................................................180
Mode 1: 8-Bit UART with Variable Baud Rate .................................................182
Mode 2: 9-Bit UART with Fixed Baud Rate .....................................................184
Mode3: 9-Bit UART with Variable Baud Rate ..................................................186
Frame Error Detection ........................................................................188
Multiprocessor Communications .......................................................188
Automatic Address Recognition .........................................................189
Buad Rates and Demo Program .........................................................191
Demo Program for UART (C and ASM) ...........................................193
Chapter 9. IAP / EEPROM ...................................................... 199
9.1
9.2
9.3
9.4
IAP / EEPROM Special Function Registers.......................................200
STC90C51RC/RD+ series Internal EEPROM Allocation Table........202
IAP/EEPROM Assembly Language Program Introduction ...............204
EEPROM Demo Program (C and ASM) ............................................207
Chapter 10. STC90 series programming tools usage ............. 215
10.1
10.2
10.3
10.4
10.5
In-System-Programming (ISP) principle..........................................215
STC90C51RC/RD+ series application circuit for ISP .....................216
PC side application usage .................................................................218
Compiler / Assembler Programmer and Emulator ...........................220
Self-Defined ISP download Demo ..................................................220
Appendix A:
Appendix B:
Appendix C:
Appendix D:
Assembly Language Programming ................... 224
8051 C Programming ......................................... 246
STC90xx series Electrical Characteristics ....... 256
Program for indirect addressing inner 256B RAM
.............................................................................. 258
Appendix E: Using Serial port expand I/O interface ............ 259
Appendix F: Use STC MCU common I/O driving LCD Display
.............................................................................. 261
Appendix G: LED driven by an I/O port and Key Scan ........ 268
Appendix H: How to reduce the Length of Code using Keil C ...
.............................................................................. 269
Chapter 1. Introduction
STC90C51RC/RD+ series, which is produced by STC MCU Limited, is a 8-bit single-chip microcontroller
with a fully compatible instruction set with industrial-standard 8051 series microcontroller. There is 64K bytes
flash memory embeded for appliaction program, which is shared with In-System-Programming code.In-SystemProgramming (ISP) and In-Application-Programming (IAP) support the users to upgrade the program and data
in system. ISP allows the user to download new code without removing the microcontroller from the actual end
product; IAP means that the device can write non-valatile data in Flash memory while the application program
is running. There are 1280 bytes or 512 bytes on-chip RAM embedded that provides requirement from wide
field application. The user can configure the device to run in 12 clocks per machine cycle, and to get the same
performance just as he uses another standard 80C51 device that is provided by other vendor, or 6 clocks per
machine cycle to achieve twice performance. The STC90C51RC/RD+ series retain all features of the standard
80C51. In addition, the STC90xx series have a extra I/O port (P4 ), Timer 2, a 8-sources, 4-priority-level interrupt
structure, on-chip crystal oscillator,and a one-time enabled Watchdog Timer.
1.1 Features
o Enhanced 80C51 Central Processing Unit ,6T or 12T per machine cycle
o Operation voltage range: 5.5V~3.3V (STC90C51RC/RD+ series) or 2.0V~ 3.6V (STC90LE51RC/RD+ series)
o Operation frequency range: 0-40MHz @ 6T, or 0- 80MHz @12T, the actual operation frequency can up to
48MHz
o On-chip 4K/8K/13K/16K/32K/40K/48K/56K/61K FLASH program memory with flexible ISP/IAP capability
o On-chip 1280 byte / 512 byte / 256 byte RAM
o Be capable of addressing up to 64K byte of external RAM
o Be capable of addressing up to 64K bytes external memory
o Dual Data Pointer (DPTR) to speed up data movement
o Three 16-bit timer/counter, Timer 2 is an up/down counter with programmable clcok output on P1.0
o 8 vector-address, 4 level priority interrupt capability
o One enhanced UART with hardware address-recognition, frame-error detection function, and with self baudrate generator.
o One 15 bits Watch-Dog-Timer with 8-bit pre-scaler (one-time-enabled)
o integrate MAX810 -- specialized reset circuit
o Two power management modes: idle mode and power-down mode
o Low EMI: inhibit ALE emission
o Power down mode can be woken-up by INT0/P3.2 pin, INT1/P3.3 pin, T0/P3.4, T1/P3.5, RXD/P3.0 pin,
INT2/P4.3, INT3/P4.2
o 39 or 35 programmable I/O ports are available
o Four 8-bit bi-directonal ports; extra four-bit additional P4 are available for PLCC-44 and LQFP-44
o Operating temperature: -40 ~ +85oC (industrial) / 0~75oC (commercial)
o package type : LQFP-44, PDIP-40, PLCC-44
STC MCU Limited.
1.2 Block diagram
The CPU kernel of STC90C51RC/RD+ is fully compatible to the standard 8051 microcontroller, maintains all
instruction mnemonics and binary compatibility. STC90C51RC/RD+ series can execute the fastest instructions
per 6 clock cycles or 12 clock cycles(as the same as the standard 80C51). Improvement of individual programs
depends on the actual instructions used.
RAM ADDR
Register
AUX-RAM
1024 Byte
B Register
256 Byte
RAM
Dual Data
Poniter
ACC
TMP2
TMP1
Stack
Poniter
Timer 0/1
Timer 2
UART
ALU
EEPROM
PSEN
ALE
EA
RESET
PSW
Port 0,1,2,3,4
Latch
Control
Unit
XTAL1
WDT
XTAL2
Port 0,1,2,3,4
Driver
P0, P1,P2,P3,P4
STC90C51RC/RD+ Block Diagram
STC MCU Limited.
FLASH
64K
ISP/IAP
Address
Generator
Program
Counter
P1.4
P1.3
P1.2
P1.1/T2EX
P1.0/T2
P4.2/INT3
Vcc
P0.0
P0.1
P0.2
P0.3
P2.4
P2.3
P2.2
P2.1
P2.0
P4.0
Gnd
XTAL1
XTAL2
P3.7/RD
P3.6/WR
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Vcc
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P4.6
ALE/P4.5
P4.4
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
6
5
4
3
2
1
44
43
42
41
40
P1.5
P1.6
P1.7
RST
RxD/P3.0
INT2/P4.3
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
1
2
3
4
5
6
7
8
9
10
11
LQFP-44
PQFP-44
39 I/O Ports
22
21
20
19
18
17
16
15
14
13
12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
35 I/O Ports
34
35
36
37
38
39
40
41
42
43
44
T2/P1.0
T2EX/P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
RxD/P3.0
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
WR/P3.6
RD/P3.7
XTAL2
XTAL1
Gnd
PDIP-40
P0.3
P0.2
P0.1
P0.0
Vcc
INT3/P4.2
T2/P1.0
T2EX/P1.1
P1.2
P1.3
P1.4
33
32
31
30
29
28
27
26
25
24
23
P0.4
P0.5
P0.6
P0.7
P4.6
P4.1
ALE/P4.5
/P4.4
P2.7
P2.6
P2.5
1.3 Pin Configurations of STC90C51RC/RD+ series MCU
PLCC-44
39 I/O Ports
39
38
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
7
8
9
10
11
12
13
14
15
16
17
P0.4
P0.5
P0.6
P0.7
P4.6
P4.1
ALE/P4.5
P4.4
P2.7
P2.6
P2.5
WR/P3.6
RD/P3.7
XTAL2
XTAL1
Gnd
P4.0
P2.0
P2.1
P2.2
P2.3
P2.4
P1.5
P1.6
P1.7
RST
RxD/P3.0
INT2P4.3
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
About operation voltage/clock frequency: RC/RD+ series MCU are real 6T MCU, which are full compatible
with traditonal 12 clocks per machine cycle
6T core
actually
If MCU don't double speed, its external clock will divide by 2 in order to lower the frequency
Operation
Voltage
External
Clock
5.5V - 4.5V
5.5V - 3.8V
5.5V - 3.6V
5.5V - 3.4V
0 - 44MHz
0 - 33MHz
0 - 24MHz
0 - 20MHz
Single speed
Correspond to
common 8052
0 - 44MHz
0 - 33MHz
0 - 24MHz
0 - 20MHz
Operation Double speed Operation
Clock in Correspond to Clock in
actual core common 8052 actual core
0 - 20MHz
0 - 80MHz 0 - 40MHz
0 - 16.5MHz 0 - 66MHz 0 - 33MHz
0 - 12MHz
0 - 48MHz 0 - 24MHz
0 - 10MHz
0 - 40MHz 0 - 20MHz
IAP/ISP
read program erase
read program erase
read program erase
read(not program/erase)
3V MCU Operation Voltage range:3.6~2.0V. When operation voltage is 2.3V ~ 1.9V, ISP/IAP do not
be ereased and programmed.
STC MCU Limited.
1.4 STC90C51RC/RD+ series Selection Table
Type
12T/6T 8051
MCU
Maximun Clock
Operating Frequency
voltage
(Hz)
(V)
5V
3V
F S T
l
A I
a R M
s
h M E
(B) (B) R
U
A
R
T
D
P
T
R
E
External
E
interrupts Package
Package of
P W
Interrupt which
of
Interrupt
44-pin
R D
Priority can wake 40-pin
(39 I/O
Sources
O T
Level up power (35 I/O
ports)
down
ports)
M
mode
(B)
STC90C/LE51 series Selection Table
STC90C51
5.5~3.3 0 ~ 80M
4K 256 3 1 2
-
Y
8
4
4
PDIP LQFP/PLCC
STC90C52
5.5~3.3 0 ~ 80M
8K 256 3 1 2
-
Y
8
4
4
PDIP LQFP/PLCC
STC90LE51
3.6~2.0
0 ~ 80M 4K 256 3 1 2
-
Y
8
4
4
PDIP LQFP/PLCC
STC90LE52
3.6~2.0
0 ~ 80M 8K 256 3 1 2
-
Y
8
4
4
PDIP LQFP/PLCC
STC90C/LE51RC series Selection Table
STC90C51RC
5.5~3.3 0 ~ 80M
4K 512 3 1 2 4K Y
8
4
4
PDIP LQFP/PLCC
STC90C52RC
5.5~3.3 0 ~ 80M
8K 512 3 1 2 4K Y
8
4
4
PDIP LQFP/PLCC
STC90C53RC
5.5~3.3 0 ~ 80M
13K 512 3 1 2
Y
8
4
4
PDIP LQFP/PLCC
STC90C12RC
5.5~3.3 0 ~ 80M
12K 512 3 1 2 1K Y
8
4
4
PDIP LQFP/PLCC
STC90LE51RC
3.6~2.0
0 ~ 80M 4K 512 3 1 2 4K Y
8
4
4
PDIP LQFP/PLCC
STC90LE52RC
3.6~2.0
0 ~ 80M 8K 512 3 1 2 4K Y
8
4
4
PDIP LQFP/PLCC
STC90LE53RC
3.6~2.0
0 ~ 80M 13K 512 3 1 2
Y
8
4
4
PDIP LQFP/PLCC
STC90LE12RC
3.6~2.0
0 ~ 80M 12K 512 3 1 2 1K Y
8
4
4
PDIP LQFP/PLCC
STC90C54RD+
5.5~3.3 0 ~ 80M
16K 1280 3 1 2 45K Y
8
4
4
PDIP LQFP/PLCC
STC90C58RD+
5.5~3.3 0 ~ 80M
32K 1280 3 1 2 29K Y
8
4
4
PDIP LQFP/PLCC
STC90C510RD+
5.5~3.3 0 ~ 80M
40K 1280 3 1 2 21K Y
8
4
4
PDIP LQFP/PLCC
STC90C512RD+
5.5~3.3 0 ~ 80M
48K 1280 3 1 2 13K Y
8
4
4
PDIP LQFP/PLCC
STC90C514RD+
5.5~3.3 0 ~ 80M
56K 1280 3 1 2 5K Y
8
4
4
PDIP LQFP/PLCC
-
-
STC90C/LE51RD+ series Selection Table
STC90C516RD+
5.5~3.3 0 ~ 80M
Y
8
4
4
PDIP LQFP/PLCC
STC90LE54RD+
3.6~2.0
0 ~ 80M 16K 1280 3 1 2 45K Y
61K 1280 3 1 2
-
8
4
4
PDIP LQFP/PLCC
STC90LE58RD+
3.6~2.0
0 ~ 80M 32K 1280 3 1 2 29K Y
8
4
4
PDIP LQFP/PLCC
STC90LE510RD+ 3.6~2.0
0 ~ 80M 40K 1280 3 1 2 21K Y
8
4
4
PDIP LQFP/PLCC
STC90LE512RD+ 3.6~2.0
0 ~ 80M 48K 1280 3 1 2 13K Y
8
4
4
PDIP LQFP/PLCC
STC90LE514RD+ 3.6~2.0
0 ~ 80M 56K 1280 3 1 2 5K Y
8
4
4
PDIP LQFP/PLCC
STC90LE516RD+ 3.6~2.0
0 ~ 80M 61K 1280 3 1 2
8
4
4
PDIP LQFP/PLCC
-
Y
Besides LQFP-44 and PLCC-44, the packages of STC90C51RC/RD+ series 44-pin MCU also have PQFP, in
which the PLCC-44 and PQFP-44 do not be recommended for users. So we recommend to select the LQFP-44
package as possible.
The reasons to select STC MCU : lower cost and boost performance. All the original programs can be used
directly without any change of hardware. Users can download their bin or hex code to STC MCU by the Writer /
Programmer tool -- STC-ISP.exe.
Internal Flash can be rewritable repeately more than 100 thousands times
STC MCU Limited.
1.5 STC90C51RC/RD+ series Minimum Application System
Vin
1
P1.2
P0.1 38
4
P1.3
P0.2 37
5
P1.4
P0.3 36
6
P1.5
P0.4 35
7
P1.6
P0.5 34
8
P1.7
P0.6 33
9
C1
P0.0 39
3
+
T2EX/P1.1
RST
PSEN/P4.4
C6
104
+
C5
10?F
28
P2.6/A14
27
P2.5/A13
26
16 WR/P3.6
P2.4/A12
25
17 RD/P3.7
P2.3/A11
24
18 XTAL2
P2.2/A10
23
19 XTAL1
P2.1/A9
22
20 Gnd
P2.0/A8
STC90xx Series can directly substitute
STC89xx Series
29
P2.7/A15
15 T1/P3.5
C3 & lt; 47pF
30
14 T0/P3.4
X1
31
ALE/P4.5
13 INT1/P3.3
C2 & lt; 47pF
Power On SW1
P0.7 32
EA/P4.6
12 INT0/P3.2
R1
10 RxD/P3.0
11 TxD/P3.1
10K
System power/5V/3V
Vcc 40
2
10?F
T2/P1.0
21
About reset circuit:
When the crystal frequency X1 is 4MHz, capacitors C2 and C3 should all be 100pF.
When the crystal frequency X1 is 6MHz, capacitors C2 and C3 should all be 47pF ~ 100pF.
When the crystal frequency X1 is 12~25MHz, capacitors C2 and C3 should all be 47pF.
1. When R/C reset, capacitor C1 is 10uF and resistor R1 isto 10K
2.RC/RD+ series HD version MCU, RESET pin is connected to internal pull-down resistor 45K-100K
A b o u t P4.6/EA : T h i s p i n i s d e f a u t t o I / O
port(P4.6), floating when not to be used.
About P4.5/ALE : This pin is defaut to ALE pin
(Address Latch Enable), which can be set to I/O
port( P4.5) in STC-ISP.exe.
About P4.4/PSEN : This pin is defaut to I/O
port(P4.4), floating when not to be used.
STC MCU Limited.
1.6 STC90C51RC/RD+ series Application Circuit for ISP
Vcc
STC3232,STC232,MAX232,SP232
Vcc 16
1 C1+
0.1?F
T1OUT 14
4 C2+
R1IN 13
5 C2-
Gnd
Gnd 15
3 C1-
Vcc
System Power/USB +5V
2
3
R1OUT 12
5
PC_TxD(COM Pin3)
SW1
T1IN 11
6 V-
T2IN 10
7 T2OUT
8 R2IN
PC_RxD(COM Pin2)
Vin
2 V+
+
PC COM
R2OUT 9
This part of the circuit
has nothing to do
with the downloads
Power On
STC90xx Series can directly
substitute STC89xx Series
Vcc
U1-P1.0
U1-P1.1
MCU-VCC
U1-P3.0
U1-P3.1
Gnd
1K
P1.2
P0.1 38
C6
P1.3
P0.2 37
104
5
P1.4
P0.3 36
6
P1.5
P0.4 35
7
P1.6
P0.5 34
8
P1.7
P0.6 33
9
MCU_RxD(P3.0)
P0.0 39
4
C1
Vcc 40
T2EX/P1.1
3
+
T2/P1.0
2
10?F
1
RST
P0.7 32
MCU_TxD(P3.1)
If the frequency of external clock is higher
than 33MHz, external active crystal
oscillator is recommended to use directly.
C2 & lt; 47pF
USB+5V T1OUT R1IN GND
X1
USB1
C1 & lt; 47pF
10 RxD/P3.0
EA/P4.6
31
11 TxD/P3.1
ALE/P4.5
30
12 INT0/P3.2
10K
R1
1K
PSEN/P4.4
29
13 INT1/P3.3
P2.7/A15
28
14 T0/P3.4
P2.6/A14
27
15 T1/P3.5
P2.5/A13
26
16 WR/P3.6
P2.4/A12
25
17 RD/P3.7
P2.3/A11
24
18 XTAL2
P2.2/A10
23
19 XTAL1
P2.1/A9
22
20 Gnd
P2.0/A8
21
1K
About reset circuit:
When the crystal frequency X1 is 4MHz, capacitors C2 and C3 should all be 100pF.
When the crystal frequency X1 is 6MHz, capacitors C2 and C3 should all be 47pF ~ 100pF.
When the crystal frequency X1 is 12~25MHz, capacitors C2 and C3 should all be 47pF.
1. When R/C reset, capacitor C1 is 10uF and resistor R1 isto 10K
2.RC/RD+ series HD version MCU, RESET pin is connected to internal pull-down resistor 45K-100K
STC MCU Limited.
+
C5
10?F
Users in their target system, such as the P3.0/P3.1 through the RS-232 level shifter connected to the computer
after the conversion of ordinary RS-232 serial port to connect the system programming / upgrading client
software. If the user panel recommended no RS-232 level converter, should lead to a socket, with Gnd/P3.1/
P3.0/Vcc four signal lines, so that the user system can be programmed directly. Of course, if the six signal lines
can lead to Gnd/P3.1/P3.0/Vcc/P1.1/P1.0 as well, because you can download the program by P1.0/P1.1 ISP ban.
If you can Gnd/P3.1/P3.0/Vcc/P1.1/P1.0/Reset seven signal lines leads to better, so you can easily use " offline
download board (no computer) " .
ISP programming on the Theory and Application Guide to see " STC90 Series MCU Development / Programming
Tools Help " section. In addition, we have standardized programming download tool, the user can then program
into the goal in the above systems, you can borrow on top of it RS-232 level shifter connected to the computer
to download the program used to do. Programming a chip roughly be a few seconds, faster than the ordinary
universal programmer much faster, there is no need to buy expensive third-party programmer?.
PC STC-ISP software downloaded from the website
STC MCU Limited.
1.7 Pin Descriptions
MNEMONIC
P0.0 ~ P0.7
P1.0/T2
Pin Number
LQFP44 PDIP40 PLCC44
37-30
39-32
40
1
DESCRIPTION
Port0 :Port0 is an 8-bit bi-directional I/O port without pull-up
resistance. Except being as GPIO, Port 0 is also the multiplexed
low-order address and data bus during accesses to external program
43~36 and data memory. When P0 ports are as GPIO, they should be
connected to 10K~4.7K pull-up resistors. When P0 ports are used
as low 8-bit address bus [A0~A7] or data bus [D0~D7], they need
not connect pull-up resistor.
2
P1.0
common I/O port PORT1[0]
T2
Timer/Counter 2 external input pin
P1.1
common I/O PORT1[1]
T2EX
Timer/Counter 2 trigger control of Capture/Reload mode
P1.1/T2EX
41
2
3
P1.2
42
3
4
common I/O PORT1[2]
P1.3
43
4
5
common I/O PORT1[3]
P1.4
44
5
6
common I/O PORT1[4]
P1.5
1
6
7
common I/O PORT1[5]
P1.6
2
7
8
common I/O PORT1[6]
P1.7
3
8
9
common I/O PORT1[7]
18-25
21-28
5
10
P2.0 ~ P2.7
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
7
8
9
11
12
13
Port2 is an 8-bit bi-directional I/O port with pull-up resistance. Except
24~31 being as GPIO, Port2 emits the high 8-bit address bus (A8~A15) during
accessing to external program and data memory.
11
13
14
15
P3.4/T0
10
14
16
P3.5/T1
11
15
17
P3.6/WR
P3.7/RD
STC MCU Limited.
12
13
16
17
18
19
P3.0
common I/O PORT3[0]
RxD
Serial recive port
P3.1
common I/O PORT3[1]
TxD
Serial transmit port
P3.2
common I/O PORT3[2]
INT0
External interrupt 0
P3.3
common I/O PORT3[3]
INT1
External interrupt 1
P3.4
common I/O PORT3[4]
T0
\Timer/Counter 0 external input pin
P3.5
common I/O PORT3[5]
T1
\Timer/Counter 1 external input pin
P3.6
common I/O PORT3[6]
WR
P3.7
RD
common I/O PORT3[7]
MNEMONIC
Pin Number
Description
LQFP44 PDIP40 PLCC44
P4.0
17
23
P4.0
common I/O PORT4[0]
P4.1
28
34
P4.1
common I/O PORT4[1]
P4.2
common I/O PORT4[2]
INT3
External interrupt 3
P4.3
common I/O PORT4[3]
INT3
External interrupt 4
P4.4
common I/O PORT4[4]
PSEN
Program Store Enable is the read strobe to external
program memory.
P4.5
common I/O PORT4[5]
P4.2/INT3
39
1
P4.3/INT2
6
12
P4.4/PSEN
26
29
32
P4.5/ALE
27
30
33
ALE
Address Latch Enable input pin
P4.6
common I/O PORT4[6]
EA
External Access Enable.
P4.6/EA
29
31
35
RST
4
9
10
RST
XTAL1
15
19
21
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
XTAL2
14
18
20
Output from the inverting oscillator amplifier.
VCC
38
40
44
Power
Gnd
16
20
22
circuit ground potential
STC MCU Limited.
1.8 Package Dimension Drawings
LQFP-44 OUTLINE PACKAGE
D (12mm)
D1 (10mm)
VARIATIONS (ALL DIMENSIONS SHOWN IN MM
34
44
E1
E
33
1
23
22
b
TC
S
c1
e
0.80mm
CU
M
A1
0.25
0.05MAX
GATE PLANE
SEATING PLANE
?0
L
L1
STC MCU Limited.
A
12
A2
11
1
SYMBOLS
A
A1
A2
c1
D
D1
E
E1
e
b(w/o
plating)
L
L1
?0
MIN.
0.05
1.35
0.09
NOM
1.40
12.00
10.00
12.00
10.00
0.80
MAX.
1.60
0.15
1.45
0.16
0.25
0.30
0.35
0.45
0.60
1.00REF
3.50
0.75
ed.
mit
Li
00
70
NOTES:
1.JEDEC OUTLINE:MS-026 BSB
2.DIMENSIONS D1 AND E1 D0 NOT
INCLUDE MOLD PROTRUSION.
ALLOWBLE PROTRUSION IS
0.25mm PER SIDE. D1 AND E1 ARE
MAXIMUM PLASTIC BODY SIZE
DIMENSIONS IMCLUDING MOLD
MISMATCH.
3.DIMENSION b DOES NOT INCLUDE
DAMBAR PROTRUSION.ALLOWBLE
DAMBAR PROTRUSION SHALL NOT
CAUSE THE LEAD WIDTH TO EXCEED
THE MAXIMUN b DIMNSION BY MORE
THAN 0.08mm.
PDIP-40 OUTLINE PACKAGE
0
?
D (2060mil)
1
20
A
SEATING
PLANE
A1
L
H
A2
C
E
e?
21
E1
40
b1
100mil
b
SYMBOLS
DIMENSIONS IN INCH
MIN
NOR
A
-
-
0.190
A1
0.015
-
0.020
A2
0.15
0.155
0.160
C
0.008
-
0.015
D
2.025
2.060
2.070
E
MAX
0.600 BSC
E1
0.540
0.545
L
0.120
0.130
0.140
b1
0.015
-
0.021
b
0.045
-
0.067
e?
0.630
0.650
0.690
0
7
15
0
UNIT: INCH
1 inch = 1000mil
NOTE:
1.JEDEC OUTLINE :MS-011 AC
STC MCU Limited.
0.550
PLCC-44 OUTLINE PACKAGE
He
A
E
A2
A1
7
18
b
17
Gd
e
1
Hd
D
b1
6
28
29
39
L
?0
40
c
H
Ge
Seating Plane
Y
SYMBOLS
A
A1
A2
b1
b
c
D
E
e
NOTE:
Gd
Ge
Hd
He
L
Y
1.JEDEC OUTLINE :M0-047 AC
2.DATUM PLANE H IS LACATED AT THE
BOTTOM OF THE MOLD PARTING LINE
COINCIDENT WITH WHERE THE LEAD
EXITS THE BODY.
MIN
0.165
0.020
0.147
0.026
0.013
0.007
0.650
0.650
0.590
0.590
0.685
0.685
0.100
-
1 inch = 1000 mil
3.DIMENSIONS E AND D D0 NOT INCLUDE MODE
PROTRUSION. ALLOWABLE PROTRUSION IS 10
MIL PRE SIDE.DIMENSIONS E AND D D0 INCLUDE
MOLD MISMATCH AND ARE DETERMINED
AT DATUM PLANE H .
4.DIMENSION b1 DOES NOT INCLUDE DAMBAR
PROTRUSION.
STC MCU Limited.
DIMENSIONS IN INCH
NOM
0.028
0.017
0.010
0.653
0.653
0.050BSC
0.610
0.610
0.690
0.690
-
MAX
0.180
0.158
0.032
0.021
0.0013
0.656
0.656
0.630
0.630
0.695
0.695
0.112
0.004
DIMENSIONS IN
MILLMETERS
MIN
NOM
MAX
4.191
4.572
0.508
3.734
4.013
0.660
0.711
0.813
0.330
0.432
0.533
0.178
0.254
0.330
16.510 16.586 16.662
16.510 16.586 16.662
1.270BSC
14.986 15.494 16.002
14.986 15.494 16.002
17.399 17.526 17.653
17.399 17.526 17.653
2.540
2.845
0.102
PQFP-44 OUTLINE PACKAGE
D(13.2mm)
" A "
D1
44
34
11
23
E(13.2mm)
33
E1
1
22
12
H
A
A2
00MIN
GATE PLANE
SEATING PLANE
b
e(0.8mm)
0.01
L
1.6
1
2
0.25
C
0.20MIN
SYMBOLS
A
A1
A2
b(w/o plating)
D
D1
E
E1
L
e
MIN.
0.25
1.80
0.25
13.00
9.9
13.00
9.9
0.73
NOM MAX.
2.70
0.50
2.00
2.20
0.30
0.35
13.20 13.40
10.00 10.10
13.20 13.40
10.00 10.10
0.88
0.93
0.80 BSC.
0
-
7
C
0.1
0.15
0.2
UNIT:mm
STC MCU Limited.
?0
DETAIL A
NOTES:
1.JEDEC OUTLINE:M0-108 AA-1
2.DATUM PLANE H IS LOCATED AT THE BOTTOM
OF THE MOLD PARTING LINE COINCIDENT WITH
WHERE THE LAED EXITS THE BODY.
3.DIMENSIONS D1 AND E1 D0 NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25mm
PER SIDE. DIMENSIONS D1 AND E1 D0 INCLUDE
MOLD MISMATCH AND ARE DETRMINED AT DATUM
PLANE H .
4.DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION.
1.9 STC90C51RC/RD+ series MCU naming rules
STC90 xx
xx
xx
--
40
x
-
xxxx
Package type
e.g. LQFP,PDIP, PLCC
Temperature range
I : Industrial, -40 -80
C : Commercial, 0 -70
Operating frequency
40 : Up to 40MHz
RAM space
RC : RAM is 512 Byte.
RD+ : RAM is 1280 Byte
No RC and RD+ : RAM is 256 Byte
Program space
51:4KB 52:8KB 54:16KB 58:32KB 516:64KB etc.
Operating Voltage
C : 5.5V~3.3V
L E: 3.8V~2.0V
STC 12T/6T Series 8051 MCU
STC MCU Limited.
1.10 Reduce the Electromagnetic Radiation of MCU Clock (EMI)
-- Three Measures
1. Prohibit ALE signal outputting, which apply to models:
The special function register of RC/RD + series 8051 MCU, which extend RAM and manage and prohibit ALE
output, is AUXR (write only)
AUXR: Auxiliary Register (write only)
Mnemonic
Add
bit
B7
B6
B5
B4
B3
B2
B1
B0
Reset Value
AUXR
8EH
name
-
-
-
-
-
-
EXTRAM
ALEOFF
xxxx,xx00
Prohibited ALE signal output (application examples for reference, C language):
sfr AUXR = 0x8e;
/* Declare the address of AUXR register */
AUXR = 0x01;
/* If ALEOFF is set to 1,prohibit ALE singal outputting */
/* and boost performance of system EMI. */
/* If ALEOFF is reset to 0,output ALE singnal normally */
Prohibited ALE signal output (application examples for reference, Assembly language):
AUXR
EQU
MOV
AUXR, #00000001B
8Eh
;or AUXR
DATA
8Eh
;If ALEOFF is set to 1,prohibit ALE singal outputting
; and boost system EMI performance
2. External clock frequency is reduced by half in 6T mode: the traditional 8051 MCU is 12 clock per machine
cycle. If STC enhanced 8051 MCU is set to double the speed (6T mode, 6 clocks per machine cycle) in the STCISP Writter/Programer when burning program, the MCU external clock frequency can be reduced by half, so to
effectively low the MCU clock interference on the outside.
3. MCU internal clock oscillator gain is reduced by half :
If Oscillator Gain is set " low " (1/2 gain) when burning program in STC-ISP Writter/Programmer (see the
following figure), the radiation of MCU clock high-frequency part to outside world can effectively reduce. But
at this time, the external crystal frequency do not higher than16MHz if possible. So when MCU external crystal
frequency & lt; 16MHz, OSCDN can be set 1/2 gain (low), which can help to lower EMI. When MCU external
crystal frequency is 16MHz or more, please set the Oscillator Gain for " high " (full gain).
STC MCU Limited.
1.11 Super Low Power Consumption -- STC90C51RC/RD+ Series MCU
1. Power-down mode:
Typical power consumption & lt; 0.1uA, which can be waked up by external interrupt. it will continue to implement
the original program after the interrupt is returned
2. Idle mode (not recommended):
Typical power consumption 2mA
3. Normal operation mode:
Typical power consumption 4mA - 7mA
4. Power-down mode:
which can be wakeed up by external interrupt and apply for water, gas and other battery-powered systems and
portable devices
STC MCU Limited.
Chapter 2. Power Management and Reset
2.1 Power Management Modes
The STC90C51RC/RD+ core has two software programmable power management mode: idle and stop/
power-down mode. The power consumption of STC90C51RC/RD+ series is about 4mA~7mA in normal
operation, while it is lower than 0.1uA in stop/power-down mode and 2mA in idle mode.
Idle and stop/power-down is managed by the corresponding bit in Power control (PCON) register which is
shown in below.
PCON register (Power Control Register)
SFR name Address
PCON
87H
bit
B7
B6
B5
B4
B3
B2
B1
B0
name
SMOD
SMOD0
-
POF
GF1
GF0
PD
IDL
SMOD : Double baud rate of UART interface
0
Keep normal baud rate when the UART is used in mode 1,2 or 3.
1
Double baud rate bit when the UART is used in mode 1,2 or 3.
SMOD0 : SM0/FE bit select for SCON.7; setting this bit will set SCON.7 as Frame Error function. Clearing it to
set SCON.7 as one bit of UART mode selection bits.
POF
: Power-On flag. It is set by power-off-on action and can only cleared by software.
Practical application: if it is wanted to know which reset the MCU is used, see the following figure.
In initializtion program,
judge whether POF/PCON.4
have been set or not
POF=1,
cold boot
Yes Power-On Reset
Clear POF/PCON.4
POF=0, No
external manual reset
or WDT reset
or software reset
or others
GF1,GF0: General-purposed flag 1 and 0
PD
: Stop Mode/Power-Down Select bit..
Setting this bit will place the STC90C51RC/RD+ MCU in Stop/Power-Down mode. Stop/PowerDown mode can be waked up by external interrupt. Because the MCU' s internal oscillator stopped in
Stop/Power-Down mode, CPU, Timers, UARTs and so on stop to run, only external interrupt go on to
work. The following pins can wake up MCU from Stop/Power-Down mode: INT0/P3.2, INT1/P3.3,
INT2/P4.3, INT3/P4.2
IDL
: Idle mode select bit.
Setting this bit will place the STC90C51RC/RD+ in Idle mode. only CPU goes into Idle mode. (Shuts off clock to
CPU, but clock to Timers, Interrupts, Serial Ports, and Analog Peripherals are still active.) The following pins can
wake up MCU from Idle mode: INT0/P3.2, INT1/P3.3, INT2/P4.3, INT3/P4.2. Besides, Timer0 and Timer1 and
Timer2 and UARTs interrupt also can wake up MCU from idle mode
STC MCU Limited.
2.1.1 Idle Mode
An instruction that sets IDL/PCON.0 causes that to be the last instruction executed before going into the idle
mode, the internal clock is gated off to the CPU but not to the interrupts, timers, WDT and serial port functions.
The CPU status is preserved in its entirety: the RAM, Stack Pointer, Program Counter, Program Status Word, Accumulator, and all other registers maintain their data during Idle. The port pins hold the logical states they had at
the time Idle was activated. ALE and PSEN hold at logic high levels. Idle mode leaves the peripherals running
in order to allow them to wake up the CPU when an interrupt is generated. Timer 0, Timer 1, Timer 2 and UART
will continue to function during Idle mode.
There are two ways to terminate the idle. Activation of any enabled interrupt will cause IDL/PCON.0 to be
cleared by hardware, terminating the idle mode. The interrupt will be serviced, and following RETI, the next
instruction to be executed will be the one following the instruction that put the device into idle.
The flag bits (GFO and GF1) can be used to give art indication if an interrupt occurred during normal operation
or during Idle. For example, an instruction that activates Idle can also set one or both flag bits. When Idle is
terminated by an interrupt, the interrupt service routine can examine the flag bits.
The other way to wake-up from idle is to pull RESET high to generate internal hardware reset.Since the clock
oscillator is still running, the hardware reset neeeds to be held active for only two machine cycles to complete the
reset.
STC MCU Limited.
2.1.2 Stop / Power Down (PD) Mode
An instruction that sets PD/PCON.1 cause that to be the last instruction executed before going into the PowerDown mode. In the Power-Down mode, the on-chip oscillator and the Flash memory are stopped in order to
minimize power consumption. Only the power-on circuitry will continue to draw power during Power-Down.
The contents of on-chip RAM and SFRs are maintained. The power-down mode can be woken-up by RESET
pin, external interrupt INT0 ~ INT3, RXD pin, T0 pin, T1 pin and T2 pin. When it is woken-up by RESET, the
program will execute from the address 0x0000. Be carefully to keep RESET pin active for at least 10ms in order
for a stable clock. If it is woken-up from I/O, the CPU will rework through jumping to related interrupt service
routine. Before the CPU rework, the clock is blocked and counted until 32768(90C version MCU) or 2048 (HD
version MCU) in order for denouncing the unstable clock. To use I/O wake-up, interrupt-related registers have to
be enabled and programmed accurately before power-down is entered. Pay attention to have at least one "NOP"
instruction subsequent to the power-down instruction if I/O wake-up is used. When terminating Power-down
by an interrupt, the wake up period is internally timed. At the negative edge on the interrupt pin, Power-Down
is exited, the oscillator is restarted, and an internal timer begins counting. The internal clock will be allowed to
propagate and the CPU will not resume execution until after the timer has reached internal counter full. After the
timeout period, the interrupt service routine will begin. To prevent the interrupt from re-triggering, the interrupt
service routine should disable the interrupt before returning. The interrupt pin should be held low until the device
has timed out and begun executing. The user should not attempt to enter (or re-enter) the power-down mode for a
minimum of 4 us until after one of the following conditions has occured: Start of code execution(after any type of
reset), or Exit from power-down mode.
The following circuit can timing wake up MCU from power down mode when external interrupt sources do not
exist
I/O
I
300?
0.1uF
I
C1
INTx
5M?
R1
Operation step:
1. I/O ports are first configured to push-pull output(strong pull-up) mode
2. Writen 1s into ports I/O ports
3. the above circuit will charge the capacitor C1
4. Writen 0s into ports I/O ports, MCU will go into power-down mode
5. The above circuit will discharge. When the electricity of capacitor C1 has been discharged less than
0.8V, external interrupt INTx pin will generate a falling edge and wake up MCU from power-down
mode automatically.
STC MCU Limited.
The following example C program demostrates that power-down mode be woken-up by external interrupt .
/*--------------------------------------------------------------------------------*/
/* --- STC MCU International Limited -----------------------------------*/
/* --- STC90xx Series MCU wake up Power-Down mode Demo ------*/
/* If you want to use the program or the program referenced in the */
/* article, please specify in which data and procedures from STC */
/*-------------------------------------------------------------------------------*/
#include & lt; reg51.h & gt;
#include & lt; intrins.h & gt;
sbit
Begin_LED = P1^2;
//Begin-LED indicator indicates system start-up
unsigned char
Is_Power_Down = 0;
//Set this bit before go into Power-down mode
sbit
Is_Power_Down_LED_INT0
= P1^7; //Power-Down wake-up LED indicator on INT0
sbit
Not_Power_Down_LED_INT0
= P1^6; //Not Power-Down wake-up LED indicator on INT0
sbit
Is_Power_Down_LED_INT1
= P1^5; //Power-Down wake-up LED indicator on INT1
sbit
Not_Power_Down_LED_INT1
= P1^4; //Not Power-Down wake-up LED indicator on INT1
sbit
Power_Down_Wakeup_Pin_INT0
= P3^2; //Power-Down wake-up pin on INT0
sbit
Power_Down_Wakeup_Pin_INT1
= P3^3; //Power-Down wake-up pin on INT1
sbit
Normal_Work_Flashing_LED
= P1^3; //Normal work LED indicator
void Normal_Work_Flashing (void);
void INT_System_init (void);
void INT0_Routine (void);
void INT1_Routine (void);
void main (void)
{
unsigned char
unsigned char
j = 0;
wakeup_counter = 0;
//clear interrupt wakeup counter variable wakeup_counter
Begin_LED = 0;
//system start-up LED
INT_System_init ( );
//Interrupt system initialization
while(1)
{
P2 = wakeup_counter;
wakeup_counter++;
for(j=0; j & lt; 2; j++)
{
Normal_Work_Flashing( ); //System normal work
}
STC MCU Limited.
Is_Power_Down = 1;
PCON = 0x02;
//Set this bit before go into Power-down mode
//after this instruction, MCU will be in power-down mode
//external clock stop
_nop_( );
_nop_( );
_nop_( );
_nop_( );
}
}
void INT_System_init (void)
{
IT0
= 0;
/* External interrupt 0, low electrical level triggered */
//
IT0
= 1;
/* External interrupt 0, negative edge triggered */
EX0
= 1;
/* Enable external interrupt 0
IT1
= 0;
/* External interrupt 1, low electrical level triggered */
//
IT1
= 1;
/* External interrupt 1, negative edge triggered */
EX1
= 1;
/* Enable external interrupt 1
EA
= 1;
/* Set Global Enable bit
}
void INT0_Routine (void) interrupt 0
{
if (Is_Power_Down)
{
//Is_Power_Down ==1;
/* Power-Down wakeup on INT0 */
Is_Power_Down = 0;
Is_Power_Down_LED_INT0 = 0;
/*open external interrupt 0 Power-Down wake-up LED indicator */
while (Power_Down_Wakeup_Pin_INT0 == 0)
{
/* wait higher */
}
Is_Power_Down_LED_INT0 = 1;
/* close external interrupt 0 Power-Down wake-up LED indicator */
}
else
{
Not_Power_Down_LED_INT0 = 0;
/* open external interrupt 0 normal work LED */
while (Power_Down_Wakeup_Pin_INT0 ==0)
{
/* wait higher */
}
Not_Power_Down_LED_INT0 = 1;
/* close external interrupt 0 normal work LED */
}
}
STC MCU Limited.
void INT1_Routine (void) interrupt 2
{
if (Is_Power_Down)
{
//Is_Power_Down ==1;
/* Power-Down wakeup on INT1 */
Is_Power_Down = 0;
Is_Power_Down_LED_INT1= 0;
/*open external interrupt 1 Power-Down wake-up LED indicator */
while (Power_Down_Wakeup_Pin_INT1 == 0)
{
/* wait higher */
}
Is_Power_Down_LED_INT1 = 1;
/* close external interrupt 1 Power-Down wake-up LED indicator */
}
else
{
Not_Power_Down_LED_INT1 = 0;
/* open external interrupt 1 normal work LED */
while (Power_Down_Wakeup_Pin_INT1 ==0)
{
/* wait higher */
}
Not_Power_Down_LED_INT1 = 1;
/* close external interrupt 1 normal work LED */
}
}
void delay (void)
{
unsigned int
j = 0x00;
unsigned int
k = 0x00;
for (k=0; k & lt; 2; ++k)
{
for (j=0; j & lt; =30000; ++j)
{
_nop_( );
_nop_( );
_nop_( );
_nop_( );
_nop_( );
_nop_( );
_nop_( );
_nop_( );
}
}
}
STC MCU Limited.
void Normal_Work_Flashing (void)
{
Normal_Work_Flashing_LED = 0;
delay ( );
Normal_Work_Flashing_LED = 1;
delay ( );
}
The following program also demostrates that power-down mode or idle mode be woken-up by external
interrupt, but is written in assembly language rather than C languge.
/*--------------------------------------------------------------------------------*/
/* --- STC MCU International Limited -----------------------------------*/
/* --- STC90xx Series MCU wake up Power-Down mode Demo ------*/
/* If you want to use the program or the program referenced in the */
/* article, please specify in which data and procedures from STC */
/*-------------------------------------------------------------------------------*/
;**************************************************************
;Wake Up Idle and Wake Up Power Down
;**************************************************************
ORG
0000H
AJMP MAIN
ORG
0003H
int0_interrupt:
CLR
P1.7
;open P1.7 LED indicator
ACALL delay
;delay in order to observe
CLR
EA
;clear global enable bit, stop all interrupts
RETI
ORG
0013H
CLR
ACALL
CLR
RETI
ORG
P1.6
delay
EA
0100H
CLR
MOV
MOV
MOV
A
R0,
R1,
R2,
int1_interrupt:
;open P1.6 LED indicator
;;delay in order to observe
;clear global enable bit, stop all interrupts
delay:
STC MCU Limited.
A
A
#02
delay_loop:
DJNZ
DJNZ
DJNZ
RET
R0,
R1,
R2,
delay_loop
delay_loop
delay_loop
MOV
R3,
#0
MOV
CPL
MOV
ACALL
INC
MOV
SUBB
JC
MOV
CLR
SETB
SETB
CLR
SETB
SETB
SETB
A,
R3
A
P1,
A
delay
R3
A,
R3
A,
#18H
main_loop
P1,
#0FFH
IT0
IT0
EX0
IT1
IT1
EX1
EA
main:
;P1 LED increment mode changed
;start to run program
main_loop:
;
;
;close all LED, MCU go into power-down mode
;low electrical level trigger external interrupt 0
;negative edge trigger external interrupt 0
;enable external interrupt 0
;low electrical level trigger external interrupt 1
;negative edge trigger external interrupt 1
;enable external interrupt 1
;set the global enable
;if don't so, power-down mode cannot be wake up
;MCU will go into idle mode or power-down mode after the following instructions
MOV
PCON, #00000010B
;Set PD bit, power-down mode (PD = PCON.1)
;
NOP
;
NOP
;
NOP
;
MOV
PCON, #00000001B
;Set IDL bit, idle mode (IDL = PCON.0)
MOV
P1,
#0DFH
;1101,1111
NOP
NOP
NOP
WAIT1:
SJMP
WAIT1
;dynamically stop
END
STC MCU Limited.
2.2 RESET Sources
In STC90C51RC/RD+, there are 4 sources to generate internal reset. They are RST pin reset, software reset, Onchip power-on-reset and Watch-Dog-Timer reset.
2.2.1 Reset pin
External RST pin reset accomplishes the MCU reset by forcing a reset pulse to RST pin from external.
If RST pin is the input to Schmitt Trigger and input pin for chip reset. Asserting an active-high signal
and keeping at least 24 cycles plus 10us on the RST pin generates a reset. If the signal on RST pin
changed active-low level, MCU will end the reset state and start to run from the 0000H of user procedures.
2.2.2 Software RESET
Writing an "1" to SWRST bit in ISP_CONTR register will generate a internal reset.
ISP_CONTR: ISP/IAP Control Register
SFR Name
SFR Address
bit
B7
B6
B5
B4
B3
B2
B1
B0
ISP_CONTR
E7H
name
ISPEN
SWBS
SWRST
-
-
WT2
WT1
WT0
ISPEN : ISP/IAP operation enable.
0 : Global disable all ISP/IAP program/erase/read function.
1 : Enable ISP/IAP program/erase/read function.
SWBS: software boot selection control bit
0 : Boot from main-memory after reset.
1 : Boot from ISP memory after reset.
SWRST: software reset trigger control.
0 : No operation
1 : Generate software system reset. It will be cleared by hardware automatically.
;Software reset from user appliction program area (AP area) and switch to AP area to run program
MOV ISP_CONTR, #00100000B ;SWBS = 0(Select AP area), SWRST = 1(Software reset)
;Software reset from system ISP monitor program area (ISP area) and switch to AP area to run program
MOV ISP_CONTR, #00100000B ;SWBS = 0(Select AP area), SWRST = 1(Software reset)
;Software reset from user appliction program area (AP area) and switch to ISP area to run program
MOV ISP_CONTR, #01100000B ;SWBS = 1(Select ISP area), SWRST = 1(Software reset)
;Software reset from system ISP monitor program area (ISP area) and switch to ISP area to run program
MOV ISP_CONTR, #01100000B ;SWBS = 1(Select ISP area), SWRST = 1(Software reset)
This reset is to reset the whole system, all special function registers and I/O prots will be reset to the initial value
STC MCU Limited.
2.2.3 Power-On Reset (POR)
When VCC drops below the detection threshold of POR circuit, all of the logic circuits are reset.
When VCC goes back up again, an internal reset is released automatically after a delay of 2048 clocks (HD
version) or 32768 clocks (90C verison).
The Power-On flag, POF/PCON.4, is set by hardware to denote the VCC power has ever been less than the POR
voltage. And, it helps users to check if the start of running of the CPU is from power-on or from hardware reset
(RST-pin reset), software reset or Watchdog Timer reset. The POF bit should be cleared by software.
2.2.4 Watch-Dog-Timer
The watch dog timer in STC90C51RC/RD+ consists of an 8-bit pre-scaler timer and an 15-bit timer. The timer
is one-time enabled by setting EN_WDT(WDT_CONTR.5). Clearing EN_WDT can stop WDT counting. When
the WDT is enabled, software should always reset the timer by writing 1 to CLR_WDT bit before the WDT
overflows. If STC90C51RC/RD+ series MCU is out of control by any disturbance, that means the CPU can
not run the software normally, then WDT may miss the " writting 1 to CLR_WDT " and overflow will come. An
overflow of Watch-Dog-Timer will generate a internal reset.
1/256
1/128
1/64
1/32
15-bit timer
1/16
WDT Reset
1/8
1/4
1/2
8-bit prescalar
SYSclk/12
IDL/PCON.0
-
-
EN_WDT CLR_WDT IDLE_WDT PS2 PS1 PS0
WDT_CONTR
WDT Structure
WDT_CONTR: Watch-Dog-Timer Control Register
SFR name
Address
WDT_CONTR 0E1H
EN_WDT
bit
B7
B6
name
-
-
B5
B4
B3
B2
B1
B0
EN_WDT CLR_WDT IDLE_WDT PS2
PS1
PS0
: Enable WDT bit. When set, WDT is started.
CLR_WDT : WDT clear bit. When set, WDT will recount. Hardware will automatically clear this bit.
IDLE_WDT : WDT IDLE mode bit. When set, WDT is enabled in IDLE mode. When clear, WDT is disabled in
IDLE.
STC MCU Limited.
PS2, PS1, PS0 : WDT Pre-scale value set bit.
Pre-scale value of Watchdog timer is shown as the bellowed table :
PS2
0
0
0
0
1
1
1
1
PS1
0
0
1
1
0
0
1
1
PS0
0
1
0
1
0
1
0
1
Pre-scale
2
4
8
16
32
64
128
256
WDT overflow Time @20MHz
39.3 mS
78.6 mS
157.3 mS
314.6 mS
629.1 mS
1.25 S
2.5 S
5S
The WDT overflow time is determined by the following equation:
WDT overflow time = (12 × Pre-scale × 32768) / Oscillator frequency
The SYSclk is 20MHz in the table above.
If SYSclk is 12MHz, The WDT overflow time is :
WDT overflow time = (12 × Pre-scale × 32768) / 12000000 = Pre-scale× 393216 / 12000000
WDT overflow time is shown as the bellowed table when SYSclk is 12MHz:
PS2
0
0
0
0
1
1
1
1
PS1
0
0
1
1
0
0
1
1
PS0
0
1
0
1
0
1
0
1
Pre-scale
2
4
8
16
32
64
128
256
WDT overflow Time @12MHz
65.5 mS
131.0 mS
262.1 mS
524.2 mS
1.0485 S
2.0971 S
4.1943 S
8.3886 S
WDT overflow time is shown as the bellowed table when SYSclk is 11.0592MHz:
PS2
0
0
0
0
1
1
1
1
PS1
0
0
1
1
0
0
1
1
PS0
0
1
0
1
0
1
0
1
Pre-scale
2
4
8
16
32
64
128
256
STC MCU Limited.
WDT overflow Time @11.0592MHz
71.1 mS
142.2 mS
284.4 mS
568.8 mS
1.1377 S
2.2755 S
4.5511 S
9.1022 S
Options related with WDT in STC-ISP Writter/Programmer is shown in the following figure
The following example is a assembly language program that demostrates STC90xx Series MCU WDT.
;/*-------------------------------------------------------------------------------*/
;/* --- STC MCU International Limited ----------------------------------*/
;/* --- STC90xx Series MCU WDT Demo ------------------------------*/
;/* If you want to use the program or the program referenced in the */
;/* article, please specify in which data and procedures from STC */
;/*-------------------------------------------------------------------------------*/
; WDT overflow time = (12 × Pre-scale × 32768) / SYSclk
WDT_CONTR
EQU
0E1H
;WDT address
WDT_TIME_LED
EQU
P1.5
;WDT overflow time LED on P1.5
;The WDT overflow time may be measured by the LED light time
WDT_FLAG_LED
EQU
P1.7
;WDT overflow reset flag LED indicator on P1.7
Last_WDT_Time_LED_Status
EQU
00H
;bit variable used to save the last stauts of WDT overflow time LED indicator
;WDT reset time , the SYSclk is 18.432MHz
;Pre_scale_Word
EQU
00111100 B
;open WDT, Pre-scale value is 32, WDT overflow time=0.68S
;Pre_scale_Word
EQU
00111101 B
;open WDT, Pre-scale value is 64, WDT overflow time=1.36S
;Pre_scale_Word
EQU
00111110 B
;open WDT, Pre-scale value is 128, WDT overflow time=2.72S
;Pre_scale_Word
EQU
00111111 B
;open WDT, Pre-scale value is 256, WDT overflow time=5.44S
STC MCU Limited.
ORG
0000H
AJMP
MAIN
ORG
0100H
MAIN:
MOV
A,
WDT_CONTR
ANL
A,
#10000000B
JNZ
;detection if WDT reset
WDT_Reset
;WDT_CONTR.7=1, WDT reset, jump WDT reset subroutine
;WDT_CONTR.7=0, Power-On reset, cold start-up, the content of RAM is random
SETB
Last_WDT_Time_LED_Status
CLR
WDT_TIME_LED
MOV
WDT_CONTR,
SJMP
WAIT1
;Power-On reset
;Power-On reset,open WDT overflow time LED
#Pre_scale_Word
;open WDT
WAIT1:
;wait WDT overflow reset
;WDT_CONTR.7=1, WDT reset, hot strart-up, the content of RAM is constant and just like before reset
WDT_Reset:
CLR
WDT_FLAG_LED
;WDT reset,open WDT overflow reset flag LED indicator
JB
Last_WDT_Time_LED_Status,
Power_Off_WDT_TIME_LED
;when set Last_WDT_Time_LED_Status, close the corresponding LED indicator
;clear, open the corresponding LED indicator
;set WDT_TIME_LED according to the last status of WDT overflow time LED indicator
CLR
WDT_TIME_LED
;close the WDT overflow time LED indicator
CPL
Last_WDT_Time_LED_Statu
;reverse the last status of WDT overflow time LED indicator
WAIT2:
SJMP
WAIT2
;wait WDT overflow reset
Power_Off_WDT_TIME_LED:
SETB
WDT_TIME_LED
;close the WDT overflow time LED indicator
CPL
Last_WDT_Time_LED_Status
;reverse the last status of WDT overflow time LED indicator
WAIT3:
SJMP
WAIT3
;wait WDT overflow reset
END
STC MCU Limited.
2.2.5 Warm Boot and Cold Boot Reset
Reset type
Result
WatchDog
Warm boot
Reset source
System will reset to AP address 0000H
and begin running user application
program
Reset Pin
STC MCU Limited.
ISP_CONTR
60H
Cold boot
20H
ISP_CONTR
Power-on
System will reset to ISP address 0000H
and begin running ISP monitor program,
if not detected legitimate ISP command,
system will software reset to the user
program area automatically.
Chapter 3. Memory Organization
The STC90C51RC/RD+ series MCU has separate address space for Program Memory and Data Memory. The
logical separation of program and data memory allows the data memory to be accessed by 8-bit addresses, which
can be quickly stored and manipulated by the CPU.
Program memory (ROM) can only be read, not written to. In the STC90C51RC/RD+ series, all the program
memory are on-chip Flash memory. Besides, STC90C51RC/RD+ series also have the capability of accessing external 64K bytes program memory.
Data memory occupies a separate address space from program memory. In the STC90C54RD+ series, there
are 256 bytes of internal scratch-pad RAM and 1024 bytes of on-chip expanded RAM(XRAM). While in the
STC90C51RC series, there are 256 bytes of internal scratch-pad RAM and 256 bytes of on-chip expanded
RAM(XRAM). While in the STC90C51 series, there are only 256 bytes of internal scratch-pad RAM. Besides,
for STC90C51RC/RD+ series 64K bytes external expanded RAM also can be accessed.
3.1 Program Memory
Program memory is the memory which stores the program codes for the CPU to execute. There is 4/8/13/16/32/4
0/48/56/62K-bytes of flash memory embedded for program and data storage. The design allows users to configure
it as like there are three individual partition banks inside. They are called AP(application program) region, IAP
(In-Application-Program) region and ISP (In-System-Program) boot region. AP region is the space that user
program is resided. IAP(In-Application-Program) region is the nonvolatile data storage space that may be used
to save important parameters by AP program. In other words, the IAP capability of STC90C51RC/RD+ provides
the user to read/write the user-defined on-chip data flash region to save the needing in use of external EEPROM
device. ISP boot region is the space that allows a specific program we calls "ISP program" is resided. Inside the
ISP region, the user can also enable read/write access to a small memory space to store parameters for specific
purposes. Generally, the purpose of ISP program is to fulfill AP program upgrade without the need to remove the
device from system. STC90C51RC/RD+ hardware catches the configuration information since power-up duration
and performs out-of-space hardware-protection depending on pre-determined criteria. The criteria is AP region
can be accessed by ISP program only, IAP region can be accessed by ISP program and AP program, and ISP
region is prohibited access from AP program and ISP program itself. But if the "ISP data flash is enabled", ISP
program can read/write this space. When wrong settings on ISP-IAP SFRs are done, The "out-of-space" happens
and STC90C51RC/RD+ follows the criteria above, ignore the trigger command.
After reset, the CPU begins execution from the location 0000H of Program Memory, where should be the starting
of the user's application code. To service the interrupts, the interrupt service locations (called interrupt vectors)
should be located in the program memory. Each interrupt is assigned a fixed location in the program memory. The
interrupt causes the CPU to jump to that location, where it commences execution of the service routine. External
Interrupt 0, for example, is assigned to location 0003H. If External Interrupt 0 is going to be used, its service
routine must begin at location 0003H. If the interrupt is not going to be used, its service location is available as
general purpose program memory.
The interrupt service locations are spaced at an interval of 8 bytes: 0003H for External Interrupt 0, 000BH for
Timer 0, 0013H for External Interrupt 1, 001BH for Timer 1, etc. If an interrupt service routine is short enough (as
is often the case in control applications), it can reside entirely within that 8-byte interval. Longer service routines
can use a jump instruction to skip over subsequent interrupt locations, if other interrupts are in use.
STC MCU Limited.
3FFFH
16K
Program Flash
Memory
(4 ~ 64K)
0000H
STC90C54RD+ Program Memory
Type
STC90C/LE51
STC90C/LE52
STC90C/LE51RC
STC90C/LE52RC
STC90C/LE53RC
STC90C/LE12RC
STC90C/LE54RD+
STC90C/LE58RD+
STC90C/LE510RD+
STC90C/LE512RD+
STC90C/LE514RD+
STC90C/LE516RD+
Program Memory
0000H~0FFFH(4K)
0000H~1FFFH(8K)
0000H~0FFFH(4K)
0000H~1FFFH(8K)
0000H~33FFH(13K)
0000H~2FFFH(12K)
0000H~3FFFH (16K)
0000H~7FFFH (32K)
0000H~9FFFH(40K)
0000H~BFFFH(48K)
0000H~DFFFH(56K)
0000H~FFFFH (64K)
3.2 Data Memory
3.2.1 On-chip Scratch-Pad RAM
Just the same as the conventional 8051 micro-controller, there are 256 bytes of SRAM data memory plus 128
bytes of SFR space available on the STC90C51RC/RD+. The lower 128 bytes of data memory may be accessed
through both direct and indirect addressing. The upper 128 bytes of data memory and the 128 bytes of SFR
space share the same address space. The upper 128 bytes of data memory may only be accessed using indirect
addressing. The 128 bytes of SFR can only be accessed through direct addressing. The lowest 32 bytes of data
memory are grouped into 4 banks of 8 registers each. Program instructions call out these registers as R0 through
R7. The RS0 and RS1 bits in PSW register select which register bank is in use. Instructions using register
addressing will only access the currently specified bank. This allows more efficient use of code space, since
register instructions are shorter than instructions that use direct addressing. The next 16 bytes (20H~2FH) above
the register banks form a block of bit-addressable memory space. The 80C51 instruction set includes a wide
selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these instructions.
The bit addresses in this area are 00H through 7FH.
All of the bytes in the Lower 128 can be accessed by either direct or indirect addressing while the Upper 128
can only be accessed by indirect addressing. SFRs include the Port latches, timers, peripheral controls, etc.
These registers can only be accessed by direct addressing. Sixteen addresses in SFR space are both byte- and bitaddressable. The bit-addressable SFRs are those whose address ends in 0H or 8H.
FF
7FH
High 128 Bytes
Internal RAM
80
7F
Special Function
Registers (SFRs)
Low 128 Bytes
Internal RAM
00
On-chip Scratch-Pad RAM
30H
20H
18H
10H
08H
00H
bit Addressable
Bank 3
Bank 2
Bank 1
Bank 0
2FH
1FH
17H
0FH
07H
Lower 128 Bytes of internal SRAM
STC MCU Limited.
PSW register
SFR name Address
PSW
D0H
bit
B7
B6
B5
B4
B3
B2
B1
B0
name
CY
AC
F0
RS1
RS0
OV
F1
P
CY : Carry flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow
(subtrac-tion). It is cleared to logic 0 by all other arithmetic operations.
AC : Auxilliary Carry Flag.(For BCD operations)
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow
from (subtraction) the high order nibble. It is cleared to logic 0 by all other arithmetic operations
F0 : Flag 0.(Available to the user for general purposes)
RS1: Register bank select control bit 1.
RS0: Register bank select control bit 0.
[RS1 RS0] select which register bank is used during register accesses
Working Register Bank(R0~R7) and Address
RS1
RS0
0
0
Bank 0(00H~07H)
0
1
Bank 1(08H~0FH)
1
0
Bank 2(10H~17H)
1
1
Bank 3(18H~1FH)
OV : Overflow flag.
This bit is set to 1 under the following circumstances:
o An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
o A MUL instruction results in an overflow (result is greater than 255).
o A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other
cases.
F1 : Flag 1. User-defined flag.
P
: Parity flag.
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the
sum is even.
SP : Stack Pointer.
The Stsek Pointer Register is 8 bits wide. It is incremented before data is stored during PUSH and CALL
executions. The stack may reside anywhere in on-chip RAM.On reset, the Stack Pointer is initialized to
07H causing the stack to begin at location 08H, which is also the first register (R0) of register bank
1. Thus, if more than one register bank is to be used, the SP should be initialized to a location in
the data memory not being used for data storage. The stack depth can extend up to 256 bytes.
STC MCU Limited.
3.2.2 Auxiliary RAM
There are 1024 bytes of additional data RAM available on STC90C54RD+ while 256 bytes XRAM on
STC90C51RC. They may be accessed by the instructions MOVX @Ri or MOVX @DPTR. A control bit -
EXTRAM located in AUXR.1 register is to control access of auxiliary RAM. When set, disable the access of
auxiliary RAM. When clear (EXTRAM=0), this auxiliary RAM is the default target for the address range from
0x0000 to 0x03FF (or from 0x0000 to 0x00FF for STC90C51RC series) and can be indirectly accessed by
move external instruction, "MOVX @Ri" and "MOVX @DPTR". If EXTRAM=0 and the target address is over
0x03FF, switches to access external RAM automatically. When EXTRAM=0, the content in DPH is ignored
when the instruction MOVX @Ri is executed.
For KEIL-C51 compiler, to assign the variables to be located at Auxiliary RAM, the "pdata" or "xdata" definition
should be used. After being compiled, the variables declared by "pdata" and "xdata" will become the memories
accessed by "MOVX @Ri" and "MOVX @DPTR", respectively. Thus the STC90C51RC/RD+ hardware can
access them correctly.
FFFF
00FF
03FF
256 Bytes
expanded RAM
1024 Bytes
expanded RAM
64K Bytes
off-chip
Expanded RAM
0000
0000
Auxiliary RAM of STC90C54RD+
Auxiliary RAM of STC90C51RC
0000
External RAM
AUXR register
Mnemonic Add
AUXR
Name
8EH Auxiliary Register
7
6
5
4
3
2
-
-
-
-
-
-
1
0
EXTRAM ALEOFF
Reset Value
xxxx,xx00
EXTRAM : Internal / external RAM access control bit.
0
1
: On-chip auxiliary RAM is enabled and located at the address 0x0000 to 0x03FF (for STC90C51RD+
series) or 0x00FF (for STC90C51RC series).
When address over 0x03FF or 0x00FF, off-chip expanded RAM becomes the target automatically.
: On-chip auxiliary RAM is always disabled.
STC MCU Limited.
0xFFFF
FFFFH
off-chip
expanded RAM
63KB
off-chip
expanded RAM
64KB
0x0400
0x03FF
Auxiliary RAM 1KB
0x0000
0000H
EXTRAM=0
EXTRAM=1
For STC90C54RD+ series
0xFFFF
FFFFH
off-chip
expanded RAM
63KB
off-chip
expanded RAM
64KB
0x0100
0x00FF
Auxiliary RAM 256B
0x0000
0000H
EXTRAM=0
For STC90C51RC series
STC MCU Limited.
EXTRAM=1
ALEOFF: Disable/enable ALE.
0 : ALE is emitted at a constant rate of 1/3 the oscillator frequency in 6 clock mode, 1/6 fosc in 12 clock
mode
1 : ALE is active only during a MOVX or MOVC instruction.
ALE pin only output signal after a MOVX or MOVC instruction, which benifit is to lower the EMI.
If auxiliary RAM need to be accessed, the corresponding option related AUXR-RAMM should be enabled
in STC-ISP Writter/Programmer.
The option related with WDT in STC-ISP Writter/Programmer is shown in the following figure
STC MCU Limited.
An example program for internal expanded RAM demo of STC90C51RC/RD+:
;/*--------------------------------------------------------------------------------*/
;/* --- STC MCU International Limited -----------------------------------*/
;/* --- STC90xx Series MCU internal expanded RAM Demo -----------*/
;/* If you want to use the program or the program referenced in the */
;/* article, please specify in which data and procedures from STC */
;/*-------------------------------------------------------------------------------*/
#include & lt; reg52.h & gt;
#include & lt; intrins.h & gt;
/* use _nop_() function */
sfr AUXR = 0x8e;
sfr AUXR1 = 0xa2;
sfr P4 = 0xe8;
sfr XICON = 0xc0;
sfr IPH = 0xb7;
sfr WDT_CONTR
sfr ISP_DATA
sfr ISP_ADDRH
sfr ISP_ADDRL
sfr ISP_CMD
sfr ISP_TRIG
sfr ISP_CONTR
= 0xe1;
= 0xe2;
= 0xe3;
= 0xe4;
= 0xe5;
= 0xe6;
= 0xe7;
sbit ERROR_LED = P1^5;
sbit OK_LED = P1^7;
void main ( )
{
unsigned int array_point = 0;
/*Test-array: Test_array_one[512], Test_array_two[512] */
unsigned char xdata Test_array_one[512] =
{
0x00,
0x01
0x02,
0x03,
0x04
0x08,
0x09,
0x0a,
0x0b,
0x0c,
0x10,
0x11,
0x12,
0x13,
0x14,
0x18,
0x19,
0x1a,
0x1b,
0x1c,
0x20,
0x21,
0x22,
0x23,
0x24,
0x28,
0x29,
0x2a,
0x2b,
0x2c,
0x30,
0x31,
0x32,
0x33,
0x34,
0x38,
0x39,
0x3a,
0x3b,
0x3c,
STC MCU Limited.
0x05,
0x0d,
0x15,
0x1d,
0x25,
0x2d,
0x35,
0x3d,
0x06,
0x0e,
0x16,
0x1e,
0x26,
0x2e,
0x36,
0x3e,
0x07,
0x0f,
0x17,
0x1f,
0x27,
0x2f,
0x37,
0x3f
0x40,
0x48,
0x50,
0x58,
0x60,
0x68,
0x70,
0x78,
0x80,
0x88,
0x90,
0x98,
0xa0,
0xa8,
0xb0,
0xb8,
0xc0,
0xc8,
0xd0,
0xd8,
0xe0,
0xe8,
0xf0,
0xf8,
0xff,
0xf7,
0xef,
0xe7,
0xdf,
0xd7,
0xcf,
0xc7,
0xbf,
0xb7,
0xaf,
0xa7,
0x9f,
0x97,
0x8f,
0x87,
0x7f,
0x77,
0x6f,
0x67,
0x5f,
0x57,
0x4f,
0x47,
0x3f,
STC MCU Limited.
0x41,
0x49,
0x51,
0x59,
0x61,
0x69,
0x71,
0x79,
0x81,
0x89,
0x91,
0x99,
0xa1,
0xa9,
0xb1,
0xb9,
0xc1,
0xc9,
0xd1,
0xd9,
0xe1,
0xe9,
0xf1,
0xf9,
0xfe,
0xf6,
0xee,
0xe6,
0xde,
0xd6,
0xce,
0xc6,
0xbe,
0xb6,
0xae,
0xa6,
0x9e,
0x96,
0x8e,
0x86,
0x7e,
0x76,
0x6e,
0x66,
0x5e,
0x56,
0x4e,
0x46,
0x3e,
0x42,
0x4a,
0x52,
0x5a,
0x62,
0x6a,
0x72,
0x7a,
0x82,
0x8a,
0x92,
0x9a,
0xa2,
0xaa,
0xb2,
0xba,
0xc2,
0xca,
0xd2,
0xda,
0xe2,
0xea,
0xf2,
0xfa,
0xfd,
0xf5,
0xed,
0xe5,
0xdd,
0xd5,
0xcd,
0xc5,
0xbd,
0xb5,
0xad,
0xa5,
0x9d,
0x95,
0x8d,
0x85,
0x7d,
0x75,
0x6d,
0x65,
0x5d,
0x55,
0x4d,
0x45,
0x3d,
0x43,
0x4b,
0x53,
0x5b,
0x63,
0x6b,
0x73,
0x7b,
0x83,
0x8b,
0x93,
0x9b,
0xa3,
0xab,
0xb3,
0xbb,
0xc3,
0xcb
0xd3,
0xdb,
0xe3,
0xeb,
0xf3,
0xfb,
0xfc,
0xf4,
0xec,
0xe4,
0xdc,
0xd4,
0xcc,
0xc4,
0xbc,
0xb4,
0xac,
0xa4,
0x9c,
0x94,
0x8c,
0x84,
0x7c,
0x74,
0x6c,
0x64,
0x5c,
0x54,
0x4c,
0x44,
0x3c,
0x44,
0x4c,
0x54,
0x5c,
0x64,
0x6c,
0x74,
0x7c,
0x84,
0x8c,
0x94,
0x9c,
0xa4,
0xac,
0xb4,
0xbc,
0xc4,
,0xcc,
0xd4,
0xdc,
0xe4,
0xec,
0xf4,
0xfc,
0xfb,
0xf3,
0xeb,
0xe3,
0xdb,
0xd3,
0xcb,
0xc3,
0xbb,
0xb3,
0xab,
0xa3,
0x9b,
0x93,
0x8b,
0x83,
0x7b,
0x73,
0x6b,
0x63,
0x5b,
0x53,
0x4b,
0x43,
0x3b,
0x45,
0x4d,
0x55,
0x5d,
0x65,
0x6d,
0x75,
0x7d,
0x85,
0x8d,
0x95,
0x9d,
0xa5,
0xad,
0xb5,
0xbd,
0xc5,
0xcd,
0xd5,
0xdd,
0xe5,
0xed,
0xf5,
0xfd,
0xfa,
0xf2,
0xea,
0xe2,
0xda,
0xd2,
0xca,
0xc2,
0xba,
0xb2,
0xaa,
0xa2,
0x9a,
0x92,
0x8a,
0x82,
0x7a,
0x72,
0x6a,
0x62,
0x5a,
0x52,
0x4a,
0x42,
0x3a,
0x46,
0x4e,
0x56,
0x5e,
0x66,
0x6e,
0x76,
0x7e,
0x86,
0x8e,
0x96,
0x9e,
0xa6,
0xae,
0xb6,
0xbe,
0xc6,
0xce,
0xd6,
0xde,
0xe6,
0xee,
0xf6,
0xfe,
0xf9,
0xf1,
0xe9,
0xe1,
0xd9,
0xd1,
0xc9,
0xc1,
0xb9,
0xb1,
0xa9,
0xa1,
0x99,
0x91,
0x89,
0x81,
0x79,
0x71,
0x69,
0x61,
0x59,
0x51,
0x49,
0x41,
0x39,
0x47,
0x4f,
0x57,
0x5f,
0x67,
0x6f,
0x77,
0x7f,
0x87,
0x8f,
0x97,
0x9f,
0xa7,
0xaf,
0xb7,
0xbf,
0xc7,
0xcf,
0xd7
0xdf,
0xe7,
0xef,
0xf7,
0xff,
0xf8,
0xf0,
0xe8,
0xe0,
0xd8,
0xd0,
0xc8,
0xc0,
0xb8,
0xb0,
0xa8,
0xa0,
0x98,
0x90,
0x88,
0x80,
0x78,
0x70,
0x68,
0x60,
0x58,
0x50,
0x48,
0x40,
0x38,
0x37,
0x2f,
0x27,
0x1f,
0x17,
0x0f,
0x07,
0x36,
0x2e,
0x26,
0x1e,
0x16,
0x0e,
0x06,
0x35,
0x2d,
0x25,
0x1d,
0x15,
0x0d,
0x05,
0x34,
0x2c,
0x24,
0x1c,
0x14,
0x0c,
0x04,
0x33,
0x2b,
0x23,
0x1b,
0x13,
0x0b,
0x03,
0x32,
0x2a,
0x22,
0x1a,
0x12,
0x0a,
0x02,
0x31,
0x29,
0x21,
0x19,
0x11,
0x09,
0x01,
0x30,
0x28,
0x20,
0x18,
0x10,
0x08,
0x00
unsigned char xdata Test_array_two[512] =
{
0x00,
0x01
0x02,
0x03,
0x08,
0x09,
0x0a,
0x0b,
0x10,
0x11,
0x12,
0x13,
0x18,
0x19,
0x1a,
0x1b,
0x20,
0x21,
0x22,
0x23,
0x28,
0x29,
0x2a,
0x2b,
0x30,
0x31,
0x32,
0x33,
0x38,
0x39,
0x3a,
0x3b,
0x40,
0x41,
0x42,
0x43,
0x48,
0x49,
0x4a,
0x4b,
0x50,
0x51,
0x52,
0x53,
0x58,
0x59,
0x5a,
0x5b,
0x60,
0x61,
0x62,
0x63,
0x68,
0x69,
0x6a,
0x6b,
0x70,
0x71,
0x72,
0x73,
0x78,
0x79,
0x7a,
0x7b,
0x80,
0x81,
0x82,
0x83,
0x88,
0x89,
0x8a,
0x8b,
0x90,
0x91,
0x92,
0x93,
0x98,
0x99,
0x9a,
0x9b,
0xa0,
0xa1,
0xa2,
0xa3,
0xa8,
0xa9,
0xaa,
0xab,
0xb0,
0xb1,
0xb2,
0xb3,
0xb8,
0xb9,
0xba,
0xbb,
0xc0,
0xc1,
0xc2,
0xc3,
0xc8,
0xc9,
0xca,
0xcb
0xd0,
0xd1,
0xd2,
0xd3,
0xd8,
0xd9,
0xda,
0xdb,
0xe0,
0xe1,
0xe2,
0xe3,
0xe8,
0xe9,
0xea,
0xeb,
0xf0,
0xf1,
0xf2,
0xf3,
0xf8,
0xf9,
0xfa,
0xfb,
0xff,
0xfe,
0xfd,
0xfc,
0xf7,
0xf6,
0xf5,
0xf4,
0xef,
0xee,
0xed,
0xec,
0xe7,
0xe6,
0xe5,
0xe4,
0xdf,
0xde,
0xdd,
0xdc,
0xd7,
0xd6,
0xd5,
0xd4,
0x04
0x0c,
0x14,
0x1c,
0x24,
0x2c,
0x34,
0x3c,
0x44,
0x4c,
0x54,
0x5c,
0x64,
0x6c,
0x74,
0x7c,
0x84,
0x8c,
0x94,
0x9c,
0xa4,
0xac,
0xb4,
0xbc,
0xc4,
,0xcc,
0xd4,
0xdc,
0xe4,
0xec,
0xf4,
0xfc,
0xfb,
0xf3,
0xeb,
0xe3,
0xdb,
0xd3,
0x05,
0x0d,
0x15,
0x1d,
0x25,
0x2d,
0x35,
0x3d,
0x45,
0x4d,
0x55,
0x5d,
0x65,
0x6d,
0x75,
0x7d,
0x85,
0x8d,
0x95,
0x9d,
0xa5,
0xad,
0xb5,
0xbd,
0xc5,
0xcd,
0xd5,
0xdd,
0xe5,
0xed,
0xf5,
0xfd,
0xfa,
0xf2,
0xea,
0xe2,
0xda,
0xd2,
0x06,
0x0e,
0x16,
0x1e,
0x26,
0x2e,
0x36,
0x3e,
0x46,
0x4e,
0x56,
0x5e,
0x66,
0x6e,
0x76,
0x7e,
0x86,
0x8e,
0x96,
0x9e,
0xa6,
0xae,
0xb6,
0xbe,
0xc6,
0xce,
0xd6,
0xde,
0xe6,
0xee,
0xf6,
0xfe,
0xf9,
0xf1,
0xe9,
0xe1,
0xd9,
0xd1,
0x07,
0x0f,
0x17,
0x1f,
0x27,
0x2f,
0x37,
0x3f
0x47,
0x4f,
0x57,
0x5f,
0x67,
0x6f,
0x77,
0x7f,
0x87,
0x8f,
0x97,
0x9f,
0xa7,
0xaf,
0xb7,
0xbf,
0xc7,
0xcf,
0xd7
0xdf,
0xe7,
0xef,
0xf7,
0xff,
0xf8,
0xf0,
0xe8,
0xe0,
0xd8,
0xd0,
};
STC MCU Limited.
0xcf,
0xc7,
0xbf,
0xb7,
0xaf,
0xa7,
0x9f,
0x97,
0x8f,
0x87,
0x7f,
0x77,
0x6f,
0x67,
0x5f,
0x57,
0x4f,
0x47,
0x3f,
0x37,
0x2f,
0x27,
0x1f,
0x17,
0x0f,
0x07,
0xce,
0xc6,
0xbe,
0xb6,
0xae,
0xa6,
0x9e,
0x96,
0x8e,
0x86,
0x7e,
0x76,
0x6e,
0x66,
0x5e,
0x56,
0x4e,
0x46,
0x3e,
0x36,
0x2e,
0x26,
0x1e,
0x16,
0x0e,
0x06,
0xcd,
0xc5,
0xbd,
0xb5,
0xad,
0xa5,
0x9d,
0x95,
0x8d,
0x85,
0x7d,
0x75,
0x6d,
0x65,
0x5d,
0x55,
0x4d,
0x45,
0x3d,
0x35,
0x2d,
0x25,
0x1d,
0x15,
0x0d,
0x05,
0xcc,
0xc4,
0xbc,
0xb4,
0xac,
0xa4,
0x9c,
0x94,
0x8c,
0x84,
0x7c,
0x74,
0x6c,
0x64,
0x5c,
0x54,
0x4c,
0x44,
0x3c,
0x34,
0x2c,
0x24,
0x1c,
0x14,
0x0c,
0x04,
0xcb,
0xc3,
0xbb,
0xb3,
0xab,
0xa3,
0x9b,
0x93,
0x8b,
0x83,
0x7b,
0x73,
0x6b,
0x63,
0x5b,
0x53,
0x4b,
0x43,
0x3b,
0x33,
0x2b,
0x23,
0x1b,
0x13,
0x0b,
0x03,
0xca,
0xc2,
0xba,
0xb2,
0xaa,
0xa2,
0x9a,
0x92,
0x8a,
0x82,
0x7a,
0x72,
0x6a,
0x62,
0x5a,
0x52,
0x4a,
0x42,
0x3a,
0x32,
0x2a,
0x22,
0x1a,
0x12,
0x0a,
0x02,
0xc9,
0xc1,
0xb9,
0xb1,
0xa9,
0xa1,
0x99,
0x91,
0x89,
0x81,
0x79,
0x71,
0x69,
0x61,
0x59,
0x51,
0x49,
0x41,
0x39,
0x31,
0x29,
0x21,
0x19,
0x11,
0x09,
0x01,
};
ERROR_LED = 1;
OK_LED = 1;
for (array_point = 0; array_point & lt; 512; array_point++)
{
if (Test_array_one[array_point] != Test_array_two [array_point])
{
ERROR_LED = 0;
OK_LED = 1;
break;
}
else{
OK_LED = 0;
ERROR_LED = 1;
}
}
while (1);
}
STC MCU Limited.
0xc8,
0xc0,
0xb8,
0xb0,
0xa8,
0xa0,
0x98,
0x90,
0x88,
0x80,
0x78,
0x70,
0x68,
0x60,
0x58,
0x50,
0x48,
0x40,
0x38,
0x30,
0x28,
0x20,
0x18,
0x10,
0x08,
0x00
3.2.3 External Expandable 64KB RAM (Off-Chip RAM)
There is 64K-byte addressing space available for STC90C51RC/RD+ series MCU to access external data RAM.
The WR and RD signal should be enabled during accessing the external expandable RAM.
Mnemonic
MOVX
MOVX
MOVX
MOVX
Description
A, @Ri
@Ri, A
A, @DPTR
@DPTR, A
Move External RAM(8-bit addr) to Acc
Move Acc to External RAM(8-bit addr)
Move External RAM(16-bit addr) to Acc
Move Acc to External RAM (16-bit addr)
STC MCU Limited.
Execution clocks of
Byte STC90C51RC/RD+ series
1
1
1
1
12
12
12
12
3.3 Special Function Registers
3.3.1 Special Function Registers Address Map
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
0F8H
0FFH
B
0F7H
0000,0000
P4
0E8H
0EFH
xxxx,1111
ACC
WDT_CONR ISP_DATA ISP_ADDRH ISP_ADDRL ISP_CMD ISP_TRIG ISP_CONTR 0E7H
0E0H
0000,0000 xx00,0000
1111,1111
0000,0000
0000,0000
1111,1000 xxxx,xxxx 000x,x000
0F0H
0D8H
0D0H
0C8H
0C0H
0B8H
0B0H
0A8H
0A0H
098H
090H
088H
080H
0DFH
PSW
0000,0000
T2CON
0000,0000
XICON
0000,0000
IP
xx00,0000
P3
1111,1111
IE
0x00,0000
P2
1111,1111
SCON
0000,0000
P1
1111,1111
TCON
0000,0000
P0
1111,1111
0/8
0D7H
T2MOD
xxxx,xx00
RCAP2L
0000,0000
RCAP2H
0000,0000
TL2
0000,0000
0C7H
0BFH
SADEN
0000,0000
IPH
0000,0000
0B7H
0AFH
SADDR
0000,0000
AUXR1
xxxx,0xx0
Don't use
0A7H
09FH
SBUF
xxxx,xxxx
097H
TMOD
0000,0000
SP
0000,0111
1/9
TL0
0000,0000
DPL
0000,0000
2/A
TL1
0000,0000
DPH
0000,0000
3/B
TH0
0000,0000
4/C
Bit Addressable
08FH
TH1
AUXR
0000,0000 xxxx,xx00
5/D
Non Bit Addressable
STC MCU Limited.
0CFH
TH2
0000,0000
6/E
PCON
00x1,0000
7/F
087H
3.3.2 Special Function Registers Bits Description
Symbol
Description
Bit Address and Symbol
Address
MSB
P0
SP
Port 0
Stack Pointer
DPL Data Pointer Low
DPTR
DPH Data Pointer High
80H
81H
82H
83H
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
Value after
Power-on or
LSB
Reset
P0.0
1111 1111B
0000 0111B
0000 0000B
0000 0000B
PCON
Power Control
87H
GF1
GF0
IDL
00x1 0000B
TCON
Timer Control
88H
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
0000 0000B
TMOD
TL0
TL1
TH0
TH1
AUXR
P1
SCON
SBUF
P2
AUXR1
IE
SADDR
P3
Timer Mode
Timer Low 0
Timer Low 1
Timer High 0
Timer High 1
Auxiliary register
Port 1
Serial Control
Serial Buffer
Port 2
Auxiliary register1
Interrupt Enable
Slave Address
Port 3
Interrupt Priority
High
Interrupt Priority
Low
Slave Address
Mask
Auxiliary Interrupt
Control
Timer/Counter 2
Control
Timer/Counter 2
Mode
Timer/Counter 2
Reload/Capture
Low Byte
Timer/Counter 2
Reload/Capture
High Byte
89H
8AH
8BH
8CH
8DH
8EH
90H
98H
99H
A0H
A2H
A8H
A9H
B0H
GATE
C/T
M1
M0
GATE
C/T
M1
M0
0000 0000B
0000 0000B
0000 0000B
0000 0000B
0000 0000B
xxxx xx00B
1111 1111B
0000 0000B
xxxx xxxxB
1111 1111B
xxxx 0xx0B
0x00 0000B
0000 0000B
1111 1111B
IPH
IP
SADEN
XICON
T2CON
T2MOD
RCAP2L
RCAP2H
SMOD SMOD0
-
-
-
-
POF
-
-
PD
EXTRAM ALEOFF
-
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
-
-
-
-
DPS
-
-
GF2
EA
-
ET2
ES
ET1
EX1
ET0
EX0
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1
P3.0
B7H
PX3H
PX2H
PT2H
PSH PT1H PX1H PT0H
PX0H
0000 0000B
B8H
-
-
PT2
PS
PX0
xx00 0000B
PT1
PX1
PT0
B9H
C0H
C8H
C9H
0000 0000B
PX3
EX3
IE3
IT3
PX2
EX2
IE2
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2
-
-
-
-
-
-
T2OE
IT2
0000,0000B
CP/RL2
0000 0000B
DCEN
xxxx xx00B
CAH
0000 0000B
CBH
0000 0000B
STC MCU Limited.
Symbol
Description
Value after
Power-on or
LSB
Reset
Bit Address and Symbol
Address
MSB
TL2
TH2
PSW
ACC
WDT_CONTR
ISP_DATA
ISP_ADDRH
ISP_ADDRL
ISP_CMD
ISP_TRIG
ISP_CONTR
P4
B
Timer/Counter Low
Byte
Timer/Counter High
Byte
Program Status
Word
Accumulator
Watch-Dog-Timer
Control Register
ISP/IAP Flash Data
Register
ISP/IAP Flash
Address High
ISP/IAP Flash
Address Low
ISP/IAP Flash
Command Register
ISP/IAP Flash
Command Trigger
ISP/IAP Control
Register
Port 4
B Register
CCH
0000 0000B
CDH
0000 0000B
D0H
CY
AC
F0
RS1
RS0
OV
F1
P
E0H
E1H
0000 0000B
0000 0000B
-
-
EN_WDT CLR_WDT
IDLE_WDT
PS2
PS1
PS0
xx00 0000B
E2H
1111 1111B
E3H
0000 0000B
E4H
0000 0000B
E5H
-
-
-
-
-
MS2
MS1
MS0
E6H
E7H
E8H
F0H
xxxx x000B
xxxx xxxxB
ISPEN SWBS SWRST
-
-
-
-
P4.3
WT2 WT1
P4.2
P4.1
WT0
P4.0
000x x000B
xxxx 1111B
0000 0000B
Some common SFRs of standard 8051 are shown as below.
Accumulator
ACC is the Accumulator register. The mnemonics for accumulator-specific instructions, however, refer to the
accumulator simply as A.
B-Register
The B register is used during multiply and divide operations. For other instructions it can be treated as another
scratch pad register.
Stack Pointer
The Stack Pointer register is 8 bits wide. It is incrementde before data is stored during PUSH and CALL
executions. While the stack may reside anywhee in on-chip RAM, the Stack Pointer is initialized to 07H after a
reset. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the first
register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be
initialized to a location in the data memory not being used for data storage. The stack depth can extend
up to 256 bytes.
STC MCU Limited.
Program Status Word(PSW)
The program status word(PSW) contains several status bits that reflect the current state of the CPU. The PSW,
shown below, resides in the SFR space. It contains the Carry bit, the Auxiliary Carry(for BCD operation), the two
register bank select bits, the Overflow flag, a Parity bit and two user-definable status flags.
The Carry bit, other than serving the function of a Carry bit in arithmetic operations, also serves as the
"Accumulator" for a number of Boolean operations.
The bits RS0 and RS1 are used to select one of the four register banks shown in the previous page. A number of
instructions refer to these RAM locations as R0 through R7.
The Parity bit reflects the number of 1s in the Accumulator. P=1 if the Accumulator contains an odd number of 1s
and otherwise P=0.
PSW register
SFR name Address
PSW
D0H
bit
B7
B6
B5
B4
B3
B2
B1
B0
name
CY
AC
F0
RS1
RS0
OV
F1
P
CY : Carry flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow
(subtrac-tion). It is cleared to logic 0 by all other arithmetic operations.
AC : Auxilliary Carry Flag.(For BCD operations)
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow
from (subtraction) the high order nibble. It is cleared to logic 0 by all other arithmetic operations
F0 : Flag 0.(Available to the user for general purposes)
RS1: Register bank select control bit 1.
RS0: Register bank select control bit 0.
[RS1 RS0] select which register bank is used during register accesses
Working Register Bank(R0~R7) and Address
RS1
RS0
0
0
Bank 0(00H~07H)
0
1
Bank 1(08H~0FH)
1
0
Bank 2(10H~17H)
1
1
Bank 3(18H~1FH)
OV : Overflow flag.
This bit is set to 1 under the following circumstances:
o An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
o A MUL instruction results in an overflow (result is greater than 255).
o A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other
cases.
F1 : Flag 1. User-defined flag.
P
: Parity flag.
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the
sum is even.
STC MCU Limited.
3.3.3 Dual Data Pointer Register (DPTR)
The Data Pointer (DPTR) consists of a high byte (DPH) and a low byte (DPL). Its intended function is to hold a
16-bit address. It may be manipulated as a 16-bit register or as two independent 8-bit registers.
For fast data movement, STC90C51RC/RD+ supports two data pointers. They share the same SFR address and
are switched by the register bit - DPS/AUXR.0.
AUXR1 register
Mnemonic Add
Name
AUXR1 A2H Auxiliary Register 1
7
-
6
-
5
-
4
-
3
GF2
2
-
1
-
0
Reset Value
DPS xxxx,0xx0
GF2 : General Flag. It can be used by software.
DPS
0 : Default. DPTR0 is selected as Data pointer.
1 : The secondary DPTR is switched to use.
The following program is an assembly program that demostrates how the dual data pointer be used.
;/*--------------------------------------------------------------------------------*/
;/* --- STC MCU International Limited -----------------------------------*/
;/* --- STC90xx Series MCU Dual Data Pointer Demo -------------------*/
;/* If you want to use the program or the program referenced in the */
;/* article, please specify in which data and procedures from STC */
;/*-------------------------------------------------------------------------------*/
AUXR1
MOV
DATA 0A2H
AUXR1, #0
;Define special function register AUXR1
;DPS=0, select DPTR0
MOV
MOV
MOVX
DPTR, #1FFH
A,
#55H
@DPTR, A
;Set DPTR0 for 1FFH
MOV
MOV
MOVX
DPTR, #2FFH
A,
#0AAH
@DPTR, A
;Set DPTR0 for 2FFH
INC
MOV
AUXR1
DPTR, #1FFH
;DPS=1, DPTR1 is selected
;Set DPTR1 for 1FFH
STC MCU Limited.
;load the value 55H in the 1FFH unit
;load the value 0AAH in the 2FFH unit
MOVX
A,
INC
MOVX
AUXR1
A,
@DPTR
INC
MOVX
AUXR1
A,
@DPTR
INC
MOVX
AUXR1
A,
@DPTR
STC MCU Limited.
@DPTR
;Get the content of 1FFH unit
;which is pointed by DPTR1,
;the content of Accumulator has changed for 55H
;DPS=0, DPTR0 is selected
;Get the content of 2FFH unit
;which is pointed by DPTR0,
;the content of Accumulator has changed for 0AAH
;DPS=1, DPTR1 is selected
;Get the content of 1FFH unit
;which is pointed by DPTR1,
;the content of Accumulator has changed for 55H
;DPS=0, DPTR0 is selected
;Get the content of 2FFH unit
;which is pointed by DPTR0,
;the content of Accumulator has changed for 0AAH
Chapter 4. Configurable I/O Ports of STC90C51RC/RD+ series
4.1 I/O Ports Configurations
All I/O ports (including P4) of STC90C51RC/RD+ may be independently configured to one of three modes. The
three modes are quasi-bidirectional (standard 8051 port output mode), input-only (high-impedance) or open-drain
output. P1, P2, P3 and P4 are default to quasi-bidirectional (just as the same as standard 8051) after reset. While
P0 is default to open-drain output mode. When P0 ports are used as bus expansion, pullup resistors need not to be
added. But when P0 ports are used as I/O ports, 10K ~ 4.7K pullup resistors should be added.
Maximum output current sunk by P0 ports pins of STC90C51RC/RD+ series 5V MCU is 12mA, and the other
ports pins' is 6mA.
Maximum output current sunk by P0 ports pins of STC90LE51RC/RD+ series 3V MCU is 8mA, and the other
ports pins' is 4mA.
Some SFRs related with I/O ports are listed below.
P4 register (bit addressable
SFR name Address
P4
E8H
bit
B7
B6
B5
B4
B3
B2
B1
B0
name
-
P4.6
P4.5
P4.4
P4.3
P4.2
P4.1
P4.0
P4 register could be bit-addressable and set/cleared by CPU. And P4.3~P1.0 coulde be set/cleared by CPU.
P3 register (bit addressable
SFR name Address
P3
B0H
bit
B7
B6
B5
B4
B3
B2
B1
B0
name
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1
P3.0
P3 register could be bit-addressable and set/cleared by CPU. And P3.7~P3.0 coulde be set/cleared by CPU.
P2 register (bit addressable
SFR name Address
P2
A0H
bit
B7
B6
B5
B4
B3
B2
B1
B0
name
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
P2 register could be bit-addressable and set/cleared by CPU. And P2.7~P2.0 coulde be set/cleared by CPU.
P1 register (bit addressable
SFR name
Address
bit
B7
B6
B5
B4
B3
B2
B1
B0
P1
90H
name
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
P1 register could be bit-addressable and set/cleared by CPU. And P1.7~P1.0 coulde be set/cleared by CPU.
P0 register (bit addressable
SFR name Address
bit
B7
B6
B5
B4
B3
B2
B1
P0
80H
name P0.7 P0.6 P0.5 P0.4 P0.3 P0.2
P0.1
P0 register could be bit-addressable. And P0.7~P0.0 coulde be set/cleared by CPU.
STC MCU Limited.
B0
P0.0
4.2 I/O ports Modes
4.2.1 Quasi-bidirectional I/O
Port pins in quasi-bidirectional output mode function similar to the standard 8051 port pins. A quasi-bidirectional
port can be used as an input and output without the need to reconfigure the port. This is possible because when
the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. When the pin
outputs low, it is driven strongly and able to sink a large current. There are three pull-up transistors in the quasibidirectional output that serve different purposes.
One of these pull-ups, called the "very weak" pull-up, is turned on whenever the port register for the pin contains
a logic "1". This very weak pull-up sources a very small current that will pull the pin high if it is left floating.
A second pull-up, called the "weak" pull-up, is turned on when the port register for the pin contains a logic
"1" and the pin itself is also at a logic "1" level. This pull-up provides the primary source current for a quasibidirectional pin that is outputting a 1. If this pin is pulled low by the external device, this weak pull-up turns off,
and only the very weak pull-up remains on. In order to pull the pin low under these conditions, the external device
has to sink enough current to over-power the weak pull-up and pull the port pin below its input threshold voltage.
The third pull-up is referred to as the "strong" pull-up. This pull-up is used to speed up low-to-high transitions on
a quasi-bidirectional port pin when the port register changes from a logic "0" to a logic "1". When this occurs, the
strong pull-up turns on for two CPU clocks, quickly pulling the port pin high.
Vcc
2 clock
delay
Strong
Vcc
Weak
Very weak
PORT
PIN
PORT
LATCH DATA
INPUT
DATA
Quasi-bidirectional output
STC MCU Limited.
Vcc
4.2.2 Open-drain Output (P0 ports are defaut to this mode after reset)
P0 is default to open-drain output mode. When P0 ports are used as bus expansion, pullup resistors need not to be
added. But when P0 ports are used as I/O ports, 10K ~ 4.7K pullup resistors should be added.
The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor
of the port pin when the port register contains a logic "0". To use this configuration in application, a
port pin must have an external pull-up, typically tied to VCC. The input path of the port pin in this
configuration is the same as quasi-bidirection mode.
PORT
PIN
PORT
LATCH DATA
INPUT
DATA
Open-drain output
4.3 I/O port application notes
When MCU is connected to a SPI or I2C or other open-drain peripherals circuit, you need add a
10K pull-up resistor.
Some IO port connected to a PNP transistor, but no pul-up resistor. The correct access method
is IO port pull-up resistor and transistor base resistor should be consistent, or IO port is set to a
strongly push-pull output mode.
Using IO port drive LED directly or matrix key scan, needs add a 470ohm to 1Kohm resistor to
limit current.
STC MCU Limited.
4.4 Head File/New SFRs Declarations, P4 of STC90C51RC/RD+ series
The processes accessing P4 are same with common P1, P2 and P3 which all are bit addressable. The address of
P4 is E8H.
The address of P4 port is E8h. Every bit in P4 all can be bit-addressable, bit address of P4 are shown below
bit
P4.6
P4.5
P4.4
P4.3
P4.2
P4.1
P4.0
bit address
EFh
EEh
EDh
ECh
EBh
EAh
E9h
E8h
The P4.4, P4.5 and P4.6 ports are respectively located at the pins - PSEN, ALE and EA of conventional 80C51.
So the STC90C51RC/RD+ series have P4.4, P4.5 and P4.6 ports with as well as the PSEN, ALE and EA pins
New Special Registers about I/O ports declarations:
C language:
#include & lt; reg51.h & gt;
/*The above head file could be included in all STC programs*/
/*New SFRs may be declared as the following statements*/
sfr
P4 = 0xe8;
/*Declare the P4 port SFR address in C language*/
sbit
P40 = 0xe8;
/*Declare the P4.0 port bit address in C language*/
sbit
P41 = 0xe9;
/*Declare the P4.1 port bit address in C language*/
sbit
P42 = 0xea;
sbit
P43 = 0xeb;
sbit
P44 = 0xec;
sbit
P45 = 0xed;
sbit
P46 = 0xee;
/*The above is the SFR address satements of P4 ports in C language
language*/
void main()
{
unsigned char idata temp = 0;
P4 = 0xff;
temp = P4;
P1 = temp;
P40 = 1;
P41 = 0;
P42 = 1;
P43 = 0;
P44 = 1;
P45 = 0;
P46 = 1;
while(1);
}
STC MCU Limited.
Assembly language:
P4
EQU
0E8H
; or P4 DATA 0E8H
P40
EQU
0E8H
; or P40 BIT
0E8H
P41
EQU
0E9H
; or P41 BIT
0E9H
P42
EQU
0EAH
P43
EQU
0EBH
P44
EQU
0ECH
P45
EQU
0EDH
P46
EQU
0EEH
;The above is the SFR address satements of P4 ports in Assembly language
P26
EQU
0A6H
ORG
0000H
LJMP
MAIN
ORG
0100H
MAIN:
MOV
MAIN_LOOP:
MOV
MOV
MOV
SETB
CLR
SETB
CLR
SETB
CLR
SETB
NOP
MOV
MOV
SJMP
END
SP,
#0C0H
A,
P1,
P4,
P40
P41
P42
P43
P44
P45
P46
P4
A
#0AH
; Read P4 status to Accumulator.
; Output data "A"through P4.0 - P4.3
; P4.0 = 1
; P4.1 = 0
; P4.2 = 1
; P4.3 = 0
; P4.4 = 1
; P4.5 = 0
; P4.6 = 1
C,
P46
P26,
C
MAIN_LOOP
Attention : The address of STC90C58AD/STC90LE58AD series P4 port is C0h.
STC MCU Limited.
4.5 P4.5/ALE pin of STC90C51RC/RD+ series
The STC90C51RC/RD+ series have ALE pin as well as P4.5 port. ALE/P4.5 pin in STC90xx series is default to
ALE pin. If users want to use it as P4.5 port, the corresponding option also should be enabled in STC-ISP Writter/
programmer. See the following figure.
STC MCU Limited.
4.6 Typical transistor control circuit
Vcc
Vcc
R1
10K(3.3K~10K)
R3
common I/O port
R2
15K(3.3K~15K)
If I/O is configed as "weak" pull-up, you should add a external pull-up resistor R1(3.3K~10K ohm). If no pull-up
resistor R1, proposal to add a 15K ohm series resistor R2 at least or config I/O as "push-pull" mode.
4.7 3V/5V hybrid system
When STC90LE51RC/RD+ series 3V MCU connect to 5V peripherals. To prevent the 3V MCU can not afford
to 5V voltage, if the corresponding I/O port as input port, the port may be in an isolation diode in series, isolated
high-voltage part. When the external signal is higher than MCU operating voltage, the diode cut-off, I/O have
been pulled high by the internal pull-up resistor; when the external signal is low, the diode conduction, I/O port
voltage is limited to 0.7V, it's low signal to MCU.
MCU common I/O
external input signal
When STC90LE51RC/RD+ series 3V MCU connect to 5V peripherals. To prevent the 3V MCU can not afford to
5V voltage, if the corresponding I/O port as output port, the port may be connect a NPN transistor to isolate highvoltage part. The circuit is shown as below.
5V
common I/O port
1
0
10K
1
0
5V device I/O port
2K
When STC90C51RC/RD+ series 5V MCU connect to 3.3V peripherals. To prevent the 3.3V device can not afford
to 5V voltage, the 5V MCU corresponding I/O should first add a 330 ohm current limiting resistor to 3.3 device
I/O ports. And in intialization of procedures the 5V MCU corresponding I/O is set to open drain mode, disconnect
the internal pull-up resistor, the corresponding 3.3V device I/O port add 10K ohm external pull-up resistor to the
3.3V device VCC, so high level to 3.3V and low to 0V, which can proper functioning
3.3V
10K
5V MCU I/O port
STC MCU Limited.
0~330?
3.3V device I/O port
4.8 I/O drive LED application circuit
1
T2/P1.0
2
P1.1/T2EX
P0.0/AD0 39
3
P1.2
P0.1/AD1 38
4
P1.3
P0.2/AD2 37
5
P1.4
P0.3/AD3 36
6
P1.5
P0.4/AD4 35
7
P1.6
P0.5/AD5 34
8
P1.7
P0.6/AD6 33
9
RST
P0.7/AD7 32
Vcc 40
10 RxD/P3.0
EA/P4.6
ALE/P4.5
PSEN/P4.4
P2.7/AD15
28
14 T0/P3.4
P2.6/AD14
27
15 T1/P3.5
P2.5/AD13
P2.4/AD12
25
17 RD/P3.7
P2.3/AD11
24
18 XTAL2
P2.2/AD10
23
19 XTAL1
P2.1/AD9
22
20 Gnd
P2.0/AD8
b
26
16 WR/P3.6
a
d
c
e
f
g
470ohm*8
dp
29
13 INT1/P3.3
R1 R2 R3 R4 R5 R6 R7 R8
30
12 INT0/P3.2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
31
11 TxD/P3.1
I/O
21
COM1 COM2 COM3 COM4
R1
471
I/O
R2
471
I/O
R3
471
I/O
R4
471
I/O
I/O dynamic scan driver 4 groups of
digital tube Cathode circuit
Maximum output current sunk by P0 ports pins
of STC90C51RC/RD+ series 5V MCU is 12mA,
and the other ports pins' is 6mA.
VCC
LED1 R1
4K7
LED4 R4
LED1
LED2
LED3
LED4
I/O
I/O
I/O
I/O
4K7
LED2 R2
LED3 R3
Maximum output current sunk by P0 ports pins
of STC90LE51RC/RD+ series 5V MCU is 8mA,
and the other ports pins' is 4mA.
4K7
4K7
COM1 COM2 COM3 COM4
a
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
STC MCU Limited.
R5
R6
R7
R8
R9
R10
R11
R12
b c
d
e
f
g dp
a
b
c
d
e
f
g
dp
1Kohm*8
I/O dynamic scan driver 4 groups of
digital tube anode circuit
4.9 I/O immediately drive LCD application circuit
VCC
R1
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
COM1
COM2
SEG1
COM1
R2
R3
R4
100K?
100K?
100K?
100K?
COM2
SEG2
COM3
SEG3
COM4
SEG4
SEG5
SEG6
SEG7
SEG8
COM1
COM2
COM3
COM3
COM4
COM4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
R5
R6
R7
R8
100K?
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
COM1
COM2
COM3
COM4
100K?
100K?
100K?
LCD4X8 1/2 BIAS
How to light on the LCD pixels:
When the pixels corresponding COM-side and SEG-side voltage difference is greater than 1/2VCC, this
pixel is lit, otherwise off
Contrl SEG-side (Segment) :
I/O direct drive Segment lines, control Segment output high-level (VCC) or low-level (0V).
Contrl COM-side (Common) :
I/O port and two 100K dividing resistors jointly controlled Common line, when the IO output " 0 " , the
Common-line is low level (0V), when the IO push-pull output " 1 " , the Common line is high level (VCC),
when IO as high-impedance input, the Common line is 1/2VCC.
VCC
R1
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
COM1
COM2
COM3
COM4
LCD4X8 1/2 BIAS
STC MCU Limited.
SEG1
COM1
R2
R3
R4
100K?
100K?
100K?
100K?
COM2
SEG2
COM3
SEG3
COM4
SEG4
SEG5
SEG6
SEG7
SEG8
COM1
COM2
COM3
COM4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
COM1
COM2
COM3
COM4
R5
R6
R7
R8
100K?
100K?
100K?
100K?
I/O control
Before MCU enter Power_Down
mode, the I/O output high level,
then Common side will have no
leakage current
Chapter 5. Instruction System
5.1 Addressing Modes
Addressing modes are an integral part of each computer's instruction set. They allow specifyng the source or
destination of data in different ways, depending on the programming situation. There are five modes available:
o Immediate
o Direct
o Indirect
o Register
o Indexed
Immediate Constant(IMM)
The value of a constant can follow the opcode in the program memory. For example,
MOV A, #70H
loads the Accumulator with the hex digits 70. The same number could be specified in decimal number as 112.
Direct Addressing(DIR)
In direct addressing the operand is specified by an 8-bit address field in the instruction. Only 128 lowest bytes of
internal data RAM and SFRs can be direct addressed.
Indirect Addressing(IND)
In indirect addressing the instruction specified a register which contains the address of the operand. Both internal
and external RAM can be indirectly addressed.
The address register for 8-bit addresses can be R0 or R1 of the selected bank, or the Stack Pointer.
The address register for 16-bit addresses can only be the 16-bit data pointer register - DPTR.
Register Instruction(REG)
The register banks, containing registers R0 through R7, can be accessed by certain instructions which carry a 3-bit
register specification within the opcode of the instruction. Instructions that access the registers this way are code
efficient because this mode eliminates the need of an extra address byte. When such instruction is executed, one
of the eight registers in the selected bank is accessed.
Register-Specific Instruction
Some instructions are specific to a certain register. For example, some instructions always operate on the
accumulator or data pointer,etc. No address byte is needed for such instructions. The opcode itself does it.
Index Addressing
Only program memory can be accessed with indexed addressing and it can only be read. This addressing mode is
intended for reading look-up tables in program memory. A 16-bit base register(either DPTR or PC) points to the
base of the table, and the accumulator is set up with the table entry number. Another type of indexed
addressing is used in the conditional jump instruction.
In conditional jump, the destination address is computed as the sum of the base pointer and the
accumulator.
STC MCU Limited.
5.2 Instruction Set Summary
The STC MCU instructions are fully compatible with the standard 8051's,which are divided among five functional
groups:
o Arithmetic
o Logical
o Data transfer
o Boolean variable
o Program branching
The following tables provides a quick reference chart showing all the 8051 and STC90xx 6T MCU instructions.
Once you are familiar with the instruction set, this chart should prove a handy and quick source of reference.
Execution Clocks of
Conventional 12T 8051
Mnemonic
Description
Execution Clocks of
STC90xx series in 6T mode
Byte
Execution clocks
of 12T MCU
Execution clocks
Efficiency
of STC90xx
improved
series in 6T mode
ARITHMETIC OPERATIONS
ADD
A, Rn
Add register to Accumulator
1
12
6
ADD
A, direct
Add ditect byte to Accumulator
2
12
6
2x
2x
ADD
A, @Ri
Add indirect RAM to Accumulator
1
12
6
2x
ADD
A, #data
Add immediate data to Accumulator
2
12
6
2x
ADDC
A, Rn
Add register to Accumulator with Carry
1
12
6
2x
ADDC
A, direct
Add direct byte to Accumulator with Carry
2
12
6
2x
ADDC
A, @Ri
Add indirect RAM to Accumulator with Carry
1
12
6
2x
ADDC
A, #data
Add immediate data to Acc with Carry
2
12
6
2x
SUBB
A, Rn
Subtract Register from Acc wih borrow
1
12
6
2x
SUBB
A, direct
Subtract direct byte from Acc with borrow
2
12
6
2x
SUBB
A, @Ri
Subtract indirect RAM from ACC with borrow
1
12
6
2x
SUBB
A, #data
Substract immediate data from ACC with borrow
2
12
6
2x
INC
A
Increment Accumulator
1
12
6
2x
INC
Rn
Increment register
1
12
6
2x
INC
direct
Increment direct byte
2
12
6
2x
INC
@Ri
Increment direct RAM
1
12
6
2x
DEC
A
Decrement Accumulator
1
12
6
2x
DEC
Rn
Decrement Register
1
12
6
2x
DEC
direct
Decrement direct byte
2
12
6
2x
DEC
@Ri
Decrement indirect RAM
1
12
6
2x
INC
DPTR
Increment Data Pointer
1
24
12
2x
MUL
AB
Multiply A & B
1
48
24
2x
DIV
AB
Divde A by B
1
48
24
2x
DA
A
Decimal Adjust Accumulator
1
12
6
2x
STC MCU Limited.
Execution clocks
Efficiency
of STC90xx
improved
series in 6T mode
Byte
Execution clocks
of 12T MCU
LOGICAL OPERATIONS
ANL
A, Rn
AND Register to Accumulator
ANL
A, direct
AND direct btye to Accumulator
ANL
A, @Ri
AND indirect RAM to Accumulator
ANL
A, #data
AND immediate data to Accumulator
ANL
direct, A
AND Accumulator to direct byte
ANL
direct, #data
AND immediate data to direct byte
ORL
A, Rn
OR register to Accumulator
ORL
A,direct
OR direct byte to Accumulator
1
2
1
2
2
3
1
2
12
12
12
12
12
24
12
12
6
6
6
6
6
12
6
6
2x
2x
2x
2x
2x
2x
2x
2x
ORL
ORL
A,@Ri
A, #data
OR indirect RAM to Accumulator
OR immediate data to Accumulator
1
2
12
12
6
6
2x
2x
ORL
direct, A
OR Accumulator to direct byte
2
12
6
2x
ORL
direct,#data
OR immediate data to direct byte
3
24
12
2x
XRL
A, Rn
Exclusive-OR register to Accumulator
1
12
6
2x
XRL
A, direct
Exclusive-OR direct byte to Accumulator
2
12
6
2x
1
12
6
2x
2
12
6
2x
Mnemonic
Description
Exclusive-OR indirect RAM to
Accumulator
Exclusive-OR immediate data to
Accumulator
XRL
A, @Ri
XRL
A, #data
XRL
direct, A
Exclusive-OR Accumulator to direct byte
2
12
6
2x
XRL
direct,#data
Exclusive-OR immediate data to direct
byte
3
24
12
2x
CLR
A
Clear Accumulator
1
12
6
2x
CPL
A
Complement Accumulator
1
12
6
2x
RL
RLC
RR
A
A
A
1
1
1
12
12
12
6
6
6
2x
2x
2x
RRC
A
1
12
6
2x
SWAP
A
Rotate Accumulator Left
Rotate Accumulator Left through the Carry
Rotate Accumulator Right
Rotate Accumulator Right through the
Carry
Swap nibbles within the Accumulator
1
12
6
2x
STC MCU Limited.
Mnemonic
DATA TRANSFER
MOV
A, Rn
MOV
A, direct
MOV
A,@Ri
MOV
A, #data
MOV
Rn, A
MOV
Rn, direct
MOV
Rn, #data
MOV
direct, A
MOV
direct, Rn
MOV
direct,direct
MOV
direct, @Ri
MOV
direct, #data
MOV
@Ri, A
MOV
@Ri, direct
MOV
@Ri, #data
MOV
DPTR, #data16
MOVC A, @A+DPTR
MOVC A, @A+PC
MOVX A, @Ri
MOVX @Ri, A
MOVX A, @DPTR
MOVX @DPTR, A
PUSH
direct
POP
direct
XCH
A, Rn
XCH
A, direct
XCH
A, @Ri
XCHD
A, @Ri
STC MCU Limited.
Execution clocks
Efficiency
of STC90xx
improved
series in 6T mode
Byte
Execution clocks
of 12T MCU
Move register to Accumulator
Move direct byte to Accumulator
Move indirect RAM to
Move immediate data to Accumulator
Move Accumulator to register
Move direct byte to register
Move immediate data to register
Move Accumulator to direct byte
Move register to direct byte
Move direct byte to direct
Move indirect RAM to direct byte
Move immediate data to direct byte
Move Accumulator to indirect RAM
Move direct byte to indirect RAM
Move immediate data to indirect RAM
Move immdiate data to indirect RAM
Move Code byte relative to DPTR to Acc
Move Code byte relative to PC to Acc
Move External RAM(8-bit addr) to Acc
Move Acc to External RAM(8-bit addr)
Move External RAM(16-bit addr) to Acc
Move Acc to External RAM (16-bit addr)
Push direct byte onto stack
POP direct byte from stack
Exchange register with Accumulator
Exchange direct byte with Accumulator
Exchange indirect RAM with Accumulator
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
2
1
1
1
1
1
1
2
2
1
2
1
12
12
12
12
12
24
12
12
24
24
24
24
12
24
12
24
24
24
24
24
24
24
24
24
12
12
12
6
6
6
6
6
12
6
6
12
12
12
12
6
12
6
12
12
12
12
12
12
12
12
12
6
6
6
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
Exchange low-order Digit indirect RAM
with Acc
1
12
6
2x
Description
Mnemonic
BOOLEAN VARIABLE
CLR
C
CLR
bit
SETB
C
SETB
bit
CPL
C
CPL
bit
ANL
C, bit
ANL
C, /bit
ORL
C, bit
ORL
C, /bit
MOV
C, bit
MOV
bit, C
JC
rel
JNC
rel
JB
bit, rel
JNB
bit,rel
JBC
bit, rel
Description
MANIPULATION
Clear Carry
Clear direct bit
Set Carry
Set direct bit
Complement Carry
Complement direct bit
AND direct bit to Carry
AND complement of direct bit to Carry
OR direct bit to Carry
OR complement of direct bit to Carry
Move direct bit to Carry
Move Carry to direct bit
Jump if Carry is set
Jump if Carry not set
Jump if direct bit is set
Jump if direct bit is not set
Jump if direct bit is set & clear bit
Byte
Execution clocks
Execution clocks
Efficiency
of STC90xx series
of 12T MCU
improved
in 6T mode
1
2
1
2
1
2
2
2
2
2
2
2
2
2
3
3
3
12
12
12
12
12
12
24
24
24
24
12
24
24
24
24
24
24
6
6
6
6
6
6
12
12
12
12
6
12
12
12
12
12
12
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2
3
1
1
2
3
2
1
2
2
24
24
24
24
24
24
24
24
24
24
12
12
12
12
12
12
12
12
12
12
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
3
24
12
2x
3
24
12
2x
3
24
12
2x
3
24
12
2x
2
24
12
2x
3
24
12
2x
1
12
6
2x
PROGRAM BRANCHING
ACALL
LCALL
RET
RETI
AJMP
LJMP
SJMP
JMP
JZ
JNZ
addr11
addr16
CJNE
A,direct,rel
CJNE
A,#data,rel
CJNE
Rn,#data,rel
CJNE
@Ri,#data,rel
DJNZ
Rn, rel
DJNZ
direct, rel
NOP
addr11
addr16
rel
@A+DPTR
rel
rel
Absolute Subroutine Call
Long Subroutine Call
Return from Subroutine
Return from interrupt
Absolute Jump
Long Jump
Short Jump (relative addr)
Jump indirect relative to the DPTR
Jump if Accumulator is Zero
Jump if Accumulator is not Zero
Compare direct byte to Acc and jump if
not equal
Compare immediate to Acc and Jump if
not equal
Compare immediate to register and Jump
if not equal
Compare immediate to indirect and jump
if not equal
Decrement register and jump if not Zero
Decrement direct byte and Jump if not
Zero
No Operation
STC MCU Limited.
5.3 Instruction Definitions
ACALL addr 11
Function:
Description:
Absolute Call
ACALL unconditionally calls a subroutine located at the indicated address.The instruction
increments the PC twice to obtain the address of the following instruction, then pushes the
16-bit result onto the stack (low-order byte first) and increments the Stack Pointer twice.
The destination address is obtained by suceesively concatenating the five high-order bits of
the incremented PC opcode bits 7-5,and the second byte of the instruction. The subroutine
called must therefore start within the same 2K block of the program memory as the first
byte of the instruction following ACALL. No flags are affected.
Example:
Initially SP equals 07H. The label "SUBRTN" is at program memory location 0345H. After
executingthe instruction,
ACALL SUBRTN
at location 0123H, SP will contain 09H, internal RAM locations 08H and 09H will contain
25H and 01H, respectively, and the PC will contain 0345H.
Bytes:
Cycles:
Encoding:
Operation:
2
2
a10 a9 a8 1
0 0 1 0
a7 a6 a5 a4
a3 a2 a1 a0
ACALL
(PC)<- (PC)+ 2
<-
(SP)<-(SP) + 1
<-(SP)
(SP)
((sP)) <- (PC7-0)
(SP)<-(SP) + 1
<-(SP)
(SP)
((SP))<-(PC15-8)
<-(PC
(PC
<-
(PC10-0)<- page address
ADD A, & lt; src-byte & gt;
Function:
Description:
Add
ADD adds the byte variable indicated to the Accumulator, leaving the result in the
Accumulator. The carry and auxiliary-carry flags are set, respectively, if there is a carryout from bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag
indicates an overflow occured.
OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not bit
6; otherwise OV is cleared. When adding signed integers, OV indicates a negative number
produced as the sum of two positive operands, or a positive sum from two negative operands.
Example:
Four source operand addressing modes are allowed: register,direct register-indirect, or
immediate.
The Accumulator holds 0C3H(11000011B) and register 0 holds 0AAH (10101010B). The
instruction,
ADD A,R0
will leave 6DH (01101101B) in the Accumulator with the AC flag cleared and both the carry
flag and OV set to 1.
STC MCU Limited.
ADD A,Rn
Bytes:
Cycles:
1
1
0 0
Encoding:
Operation:
1
0
1 r r r
ADD
(A)<-(A) + (Rn)
<-(A)
(A)
ADD A,direct
Bytes:
2
Cycles:
1
0 0 1 0
Encoding:
Operation:
0 1 0 1
direct address
ADD
(A)<-(A) + (direct)
<-(A)
(A)
ADD A,@Ri
Bytes:
1
Cycles:
1
0 0
Encoding:
Operation:
1
0
0 1 1 i
ADD
(A)<-(A) + ((Ri))
<-(A)
(A)
ADD A,#data
Bytes:
Cycles:
Encoding:
Operation:
2
1
0 0 1 0
0 1 0 0
immediate data
ADD
(A)<-(A) + #data
<-(A)
(A)
ADDC A, & lt; src-byte & gt;
Function:
Description:
Example:
Add with Carry
ADDC simultaneously adds the byte variable indicated, the Carry flag and the Accumulator,
leaving the result in the Accumulator. The carry and auxiliary-carry flags are set, respectively,
if there is a carry-out from bit 7 or bit 3, and cleared otherwise. When adding unsigned
integers, the carry flag indicates an overflow occured.
OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not
out of bit 6; otherwise OV is cleared. When adding signed integers, OV indicates a negative
number produced as the sum of two positive operands or a positive sum from two negative
operands.
Four source operand addressing modes are allowed: register, direct, register-indirect, or
immediate.
The Accumulator holds 0C3H(11000011B) and register 0 holds 0AAH (10101010B) with the
Carry. The instruction,
ADDC A,R0
will leave 6EH (01101101B) in the Accumulator with the AC flag cleared and both the carry
flag and OV set to 1.
STC MCU Limited.
ADDC A,Rn
Bytes:
Cycles:
1
1
0 0
Encoding:
Operation:
1
1
1 r r r
ADDC
(A)<-(A) + (C) + (Rn)
<-(A)
(A)
ADDC A,direct
Bytes:
2
Cycles:
1
0 0 1 1
Encoding:
Operation:
0 1 0 1
direct address
ADDC
(A)<-(A) + (C) + (direct)
<-(A)
(A)
ADDC A,@Ri
Bytes:
1
Cycles:
1
0 0
Encoding:
Operation:
1
1
0 1 1 i
ADDC
(A)<-(A) + (C) + ((Ri))
<-(A)
(A)
ADDC A,#data
Bytes:
2
Cycles:
1
0 0 1 1
Encoding:
Operation:
0 1 0 0
immediate data
ADDC
(A)<-(A) + (C) + #data
<-(A)
(A)
AJMP addr 11
Function:
Description:
Example:
Bytes:
Cycles:
Encoding:
Operation:
STC MCU Limited.
Absolute Jump
AJMP transfers program execution to the indicated address, which is formed at run-time by
concatenating the high-order five bits of the PC (after incrementing the PC twice), opcode
bits 7-5, and the second byte of the instruction. The destination must therefore be within the
same 2K block of program memory as the first byte of the instruction following AJMP.
The label "JMPADR" is at program memory location 0123H. The instruction,
AJMP JMPADR
is at location 0345H and will load the PC with 0123H.
2
2
a10 a9 a8 0
0 0 0 1
AJMP
(PC)<- (PC)+ 2
<-
(PC10-0)<- page address
<-
a7 a6 a5 a4
a3 a2 a1 a0
ANL & lt; dest-byte & gt; , & lt; src-byte & gt;
Function:
Description:
Logical-AND for byte variables
ANL performs the bitwise logical-AND operation between the variables indicated and stores
the results in the destination variable. No flags are affected.
The two operands allow six addressing mode combinations. When the destination is the
Accumulator, the source can use register, direct, register-indirect, or immediate addressing;
when the destination is a direct address, the source can be the Accumulator or immediate
data.
Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch not the input pins.
Example:
If the Accumulator holds 0C3H(11000011B) and register 0 holds 55H (01010101B) then the
instruction,
ANL A,R0
will leave 41H (01000001B) in the Accumulator.
When the destination is a directly addressed byte, this instruction will clear combinations of
bits in any RAM location or hardware register. The mask byte determining the pattern of bits
to be cleared would either be a constant contained in the instruction or a value computed in
the Accumulator at run-time. The instruction,
ANL Pl, #01110011B
will clear bits 7, 3, and 2 of output port 1.
ANL A,Rn
Bytes:
Cycles:
1
1
Encoding:
0 1
0
Operation:
1
ANL
(A)<-(A)
<-(A)
(A)
1 r r r
(Rn)
ANL A,direct
Bytes:
2
Cycles:
1
0 1 0 1
Encoding:
Operation:
ANL
(A)<-(A)
<-(A)
(A)
0 1 0 1
(direct)
ANL A,@Ri
Bytes:
1
Cycles:
1
Encoding:
0 1
0
Operation:
ANL
(A)<-(A)
<-(A)
(A)
1
0 1 1 i
((Ri))
STC MCU Limited.
direct address
ANL A,#data
Bytes:
2
Cycles:
1
0 1 0 1
Encoding:
Operation:
ANL
(A)<-(A)
<-(A)
(A)
0 1 0 0
immediate data
#data
ANL direct,A
Bytes:
2
Cycles:
1
Encoding:
0 1 0 1
0 0 1 0
Operation:
ANL
(direct)<-(direct)
<-(direct)
(direct)
direct address
(A)
ANL direct,#data
Bytes:
3
Cycles:
2
Encoding:
0 1 0 1
0 0 1 1
Operation:
ANL
(direct)<-(direct)
<-(direct)
(direct)
direct address
immediate data
#data
ANL C , & lt; src-bit & gt;
Function:
Description:
Logical-AND for bit variables
If the Boolean value of the source bit is a logical 0 then clear the carry flag; otherwise
leave the carry flag in its current state. A slash (" / ") preceding the operand in the assembly
language indicates that the logical complement of the addressed bit is used as the source
value, but the source bit itself is not affceted. No other flsgs are affected.
Only direct addressing is allowed for the source operand.
Example:
Set the carry flag if, and only if, P1.0 = 1, ACC. 7 = 1, and OV = 0:
MOV C, P1.0
;LOAD CARRY WITH INPUT PIN STATE
ANL C, ACC.7
;AND CARRY WITH ACCUM. BIT.7
ANL C, /OV
;AND WITH INVERSE OF OVERFLOW FLAG
ANL C,bit
Bytes:
2
Cycles:
2
Encoding:
Operation:
STC MCU Limited.
1 0 0 0
ANL
(C) <- (C)
0 0 1 0
(bit)
bit address
ANL C, /bit
Bytes:
2
Cycles:
2
1 0 1 1
Encoding:
Operation:
ADD
(C)<-(C)
<-(C)
(C)
0 0 0 0
bit address
(bit)
CJNE & lt; dest-byte & gt; , & lt; src-byte & gt; , rel
Function:
Description:
Compare and Jump if Not Equal
CJNE compares the magnitudes of the first two operands, and branches if their values are not
equal. The branch destination is computed by adding the signed relative-displacement in the
last instruction byte to the PC, after incrementing the PC to the start of the next instruction.
The carry flag is set if the unsigned integer value of & lt; dest-byte & gt; is less than the unsigned
integer value of & lt; src-byte & gt; ; otherwise, the carry is cleared. Neither operand is affected.
The first two operands allow four addressing mode combinations: the Accumulator may
be compared with any directly addressed byte or immediate data, and any indirect RAM
location or working register can be compared with an immediate constant.
Example:
The Accumulator contains 34H. Register 7 contains 56H. The first instruction in the sequence
;
NOT_EQ:
;
CJNE
...
JC
...
R7,#60H, NOT-EQ
......
REQ_LOW
.....
; R7 = 60H.
; IF R7 & lt; 60H.
; R7 & gt; 60H.
sets the carry flag and branches to the instruction at label NOT-EQ. By testing the carry flag,
this instruction determines whether R7 is greater or less than 60H.
If the data being presented to Port 1 is also 34H, then the instruction,
WAIT: CJNE A,P1,WAIT
clears the carry flag and continues with the next instruction in sequence, since the
Accumulator does equal the data read from P1. (If some other value was being input on Pl,
the program will loop at this point until the P1 data changes to 34H.)
CJNE A,direct,rel
Bytes: 3
Cycles: 2
Encoding:
Operation:
1 0 1 1
0 1 0 1
direct address
(PC) <- (PC) + 3
IF (A) & lt; & gt; (direct)
THEN
(PC) <- (PC) + relative offset
IF (A) & lt; (direct)
THEN
(C) <- 1
ELSE
(C) <- 0
STC MCU Limited.
rel. address
CJNE A,#data,rel
Bytes:
3
Cycles:
2
1 0 1 1
Encoding:
Operation:
0 1 0 1
immediata data
rel. address
(PC) <- (PC) + 3
IF (A) & lt; & gt; (data)
THEN
(PC) <- (PC) + relative offset
IF (A) & lt; (data)
THEN
(C) <- 1
ELSE
(C) <- 0
CJNE Rn,#data,rel
Bytes:
3
Cycles:
2
1 0 1 1
Encoding:
Operation:
1 r r r
immediata data
rel. address
(PC) <- (PC) + 3
IF (Rn) & lt; & gt; (data)
THEN
(PC) <- (PC) + relative offset
IF (Rn) & lt; (data)
THEN
(C) <- 1
ELSE
(C) <- 0
CJNE @Ri,#data,rel
Bytes:
3
Cycles:
2
Encoding:
Operation:
STC MCU Limited.
1 0 1 1
0 1 1 i
immediate data
(PC) <- (PC) + 3
IF ((Ri)) & lt; & gt; (data)
THEN
(PC) <- (PC) + relative offset
IF ((Ri)) & lt; (data)
THEN
(C) <- 1
ELSE
(C) <- 0
rel. address
CLR A
Function:
Description:
Example:
Clear Accumulator
The Aecunmlator is cleared (all bits set on zero). No flags are affected.
The Accumulator contains 5CH (01011100B). The instruction,
CLR A
will leave the Accumulator set to 00H (00000000B).
Bytes:
Cycles:
1
1
1 1 1 0
Encoding:
Operation:
0 1 0 0
CLR
(A)<- 0
<-
CLR bit
Function:
Description:
Example:
Clear bit
The indicated bit is cleared (reset to zero). No other flags are affected. CLR can operate on
the carry flag or any directly addressable bit.
Port 1 has previously been written with 5DH (01011101B). The instruction,
CLR
P1.2
will leave the port set to 59H (01011001B).
CLR C
Bytes:
Cycles:
1
1
Encoding:
1 1
0
Operation:
0
0 0 1 1
CLR
(C) <- 0
CLR bit
Bytes:
2
Cycles:
1
Encoding:
Operation:
1 1 0 0
CLR
(bit) <- 0
STC MCU Limited.
0 0 1 0
bit address
CPL A
Function:
Description:
Example:
Complement Accumulator
Each bit of the Accumulator is logically complemented (one's complement). Bits which
previously contained a one are changed to a zero and vice-versa. No flags are affected.
The Accumulator contains 5CH(01011100B). The instruction,
CPL
A
will leave the Accumulator set to 0A3H (101000011B).
Bytes:
Cycles:
1
1
1 1 1 1
Encoding:
Operation:
0 1 0 0
CPL
(A)<- (A)
<-
CPL bit
Function:
Description:
Example:
Complement bit
The bit variable specified is complemented. A bit which had been a one is changed to zero
and vice-versa. No other flags are affected. CLR can operate on the carry or any directly
addressable bit.
Note:When this instruction is used to modify an output pin, the value used as the original
data will be read from the output data latch, not the input pin.
Port 1 has previously been written with 5DH (01011101B). The instruction,
CLR
P1.1
CLR
P1.2
will leave the port set to 59H (01011001B).
CPL C
Bytes:
Cycles:
1
1
1 0
Encoding:
Operation:
1
1
0 0 1 1
CPL
(C) <- (C)
CPL bit
Bytes:
2
Cycles:
1
Encoding:
Operation:
1 0 1 1
CPL
(bit) <- (bit)
STC MCU Limited.
0 0 1 0
bit address
DA
A
Function:
Description:
Decimal-adjust Accumulator for Addition
DA A adjusts the eight-bit value in the Accumulator resulting from the earlier addition of
two variables (each in packed-BCD format), producing two four-bit digits.Any ADD or
ADDC instruction may have been used to perform the addition.
If Accumulator bits 3-0 are greater than nine (xxxx1010-xxxx1111), or if the AC flag is one,
six is added to the Accumulator producing the proper BCD digit in the low-order nibble.
This internal addition would set the carry flag if a carry-out of the low-order four-bit field
propagated through all high-order bits, but it would not clear the carry flag otherwise.
If the carry flag is now set or if the four high-order bits now exceed nine(1010xxxx111xxxx), these high-order bits are incremented by six, producing the proper BCD digit
in the high-order nibble. Again, this would set the carry flag if there was a carry-out of the
high-order bits, but wouldn't clear the carry. The carry flag thus indicates if the sum of
the original two BCD variables is greater than 100, allowing multiple precision decimal
addition. OV is not affected.
All of this occurs during the one instruction cycle. Essentially, this instruction performs the
decimal conversion by adding 00H, 06H, 60H, or 66H to the Accumulator, depending on
initial Accumulator and PSW conditions.
Note: DA A cannot simply convert a hexadecimal number in the Accumulator to BCD
notation, nor does DA A apply to decimal subtraction.
Example:
The Accumulator holds the value 56H(01010110B) representing the packed BCD digits of
the decimal number 56. Register 3 contains the value 67H (01100111B) representing the
packed BCD digits of the decimal number 67.The carry flag is set. The instruction sequence.
ADDC A,R3
DA
A
will first perform a standard twos-complement binary addition, resulting in the value 0BEH
(10111110) in the Accumulator. The carry and auxiliary carry flags will be cleared.
The Decimal Adjust instruction will then alter the Accumulator to the value 24H
(00100100B), indicating the packed BCD digits of the decimal number 24, the low-order
two digits of the decimal sum of 56,67, and the carry-in. The carry flag will be set by the
Decimal Adjust instruction, indicating that a decimal overflow occurred. The true sum 56,
67, and 1 is 124.
BCD variables can be incremented or decremented by adding 01H or 99H. If the Accumulator initially holds 30H (representing the digits of 30 decimal), then the instruction sequence,
ADD
DA
A,#99H
A
will leave the carry set and 29H in the Accumulator, since 30+99=129. The low-order byte
of the sum can be interpreted to mean 30 - 1 = 29.
STC MCU Limited.
Bytes: 1
Cycles: 1
1 1
Encoding:
0 1
0 1 0
0
Operation: DA
-contents of Accumulator are BCD
IF [[(A3-0) & gt; 9] V [(AC) = 1]]
THEN(A3-0) <- (A3-0) + 6
AND
IF [[(A7-4) & gt; 9] V [(C) = 1]]
THEN (A7-4) <- (A7-4) + 6
DEC byte
Function:
Description:
Decrement
The variable indicated is decremented by 1. An original value of 00H will underflow to
0FFH.
No flags are affected. Four operand addressing modes are allowed: accumulator, register,
direct, or register-indirect.
Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
Example:
Register 0 contains 7FH (01111111B). Internal RAM locations 7EH and 7FH contain 00H
and 40H, respectively. The instruction sequence,
DEC
@R0
DEC
R0
DEC
@R0
will leave register 0 set to 7EH and internal RAM locations 7EH and 7FH set to 0FFH and
3FH.
DEC A
Bytes:
Cycles:
1
1
Encoding:
0 0
0
1
0 1 0 0
Operation:
DEC
(A)<-(A)
<-(A)
(A)
Encoding:
0 0 0 1
1 r r r
Operation:
DEC
(Rn)<-(Rn) - 1
<-(Rn)
(Rn)
DEC Rn
Bytes:
1
Cycles:
1
STC MCU Limited.
DEC
direct
Bytes:
Cycles:
2
1
Encoding:
0 0 0 1
0 1 0 1
Operation:
direct address
DEC
(direct)<-(direct)
<-(direct)
(direct)
DEC @Ri
Bytes:
1
Cycles:
1
Encoding:
0 0 0 1
0 1 1 i
Operation:
DEC
((Ri))<-((Ri)) - 1
<-((Ri))
((Ri))
DIV AB
Function:
Description:
Divide
DIV AB divides the unsigned eight-bit integer in the Accumulator by the unsigned eight-bit
integer in register B. The Accumulator receives the integer part of the quotient; register B
receives the integer remainder. The carry and OV flags will be cleared.
Exception: if B had originally contained 00H, the values returned in the Accumulator and
B-register will be undefined and the overflow flag will be set. The carry flag is cleared in any
case.
Example:
The Accumulator contains 251(OFBH or 11111011B) and B contains 18(12H or 00010010B).
The instruction,
DIV
Bytes:
Cycles:
Encoding:
Operation:
AB
will leave 13 in the Accumulator (0DH or 00001101B) and the value 17 (11H or 00010010B)
in B, since 251 = (13×18) + 17. Carry and OV will both be cleared.
1
4
1 0
0
0
0 1 0 0
DIV
(A)15-8
(B)7-0 <- (A)/(B)
STC MCU Limited.
DJNZ & lt; byte & gt; , & lt; rel-addr & gt;
Function:
Description:
Decrement and Jump if Not Zero
DJNZ decrements the location indicated by 1, and branches to the address indicated by the
second operand if the resulting value is not zero. An original value of 00H will underflow to
0FFH. No flags are afected. The branch destination would be computed by adding the signed
relative-displacement value in the last instruction byte to the PC, after incrementing the PC
to the first byte of the following instruction.
The location decremented may be a register or directly addressed byte.
Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
Example:
Internal RAM locations 40H, 50H, and 60H contain the values 01H, 70H, and 15H,
respectively. The instruction sequence,
DJNZ
DJNZ
DJNZ
40H, LABEL_1
50H, LABEL_2
60H, LABEL_3
will cause a jump to the instruction at label LABEL_2 with the values 00H, 6FH, and 15H in
the three RAM locations. The first jump was not taken because the result was zero.
This instruction provides a simple way of executing a program loop a given number of times,
or for adding a moderate time delay (from 2 to 512 machine cycles) with a single instruction
The instruction sequence,
TOOOLE:
MOV
CPL
DJNZ
R2,#8
P1.7
R2, TOOGLE
will toggle P1.7 eight times, causing four output pulses to appear at bit 7 of output Port 1.
Each pulse will last three machine cycles; two for DJNZ and one to alter the pin.
DJNZ Rn,rel
Bytes:
Cycles:
2
2
1 1 0 1
Encoding:
Operation:
DJNZ
1 r r r
rel. address
DJNZ
(PC) <- (PC) + 2
(Rn) <- (Rn) - 1
IF (Rn) & gt; 0 or (Rn) & lt; 0
THEN
(PC) <- (PC)+ rel
direct, rel
Bytes: 3
Cycles: 2
Encoding:
STC MCU Limited.
1 1 0 1
0 1 0 1
direct address
rel. address
Operation:
DJNZ
(PC) <- (PC) + 2
(direct) <- (direct) - 1
IF (direct) & gt; 0 or (direct) & lt; 0
THEN
(PC) <- (PC) + rel
INC & lt; byte & gt;
Function:
Description:
Increment
INC increments the indicated variable by 1. An original value of 0FFH will overflow to
00H.No flags are affected. Three addressing modes are allowed: register, direct, or registerindirect.
Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
Example:
Register 0 contains 7EH (011111110B). Internal RAM locations 7EH and 7FH contain 0FFH
and 40H, respectively. The instruction sequence,
INC
INC
INC
@R0
R0
@R0
will leave register 0 set to 7FH and internal RAM locations 7EH and 7FH holding
(respectively) 00H and 41H.
INC
A
Bytes:
Cycles:
1
1
0 0
Encoding:
Operation:
INC
0
0 1 0 0
INC
(A) <- (A)+1
Rn
Bytes:
1
Cycles:
1
0 0
Encoding:
Operation:
INC
0
direct
Bytes:
Cycles:
0
0
1 r r r
INC
(Rn) <- (Rn)+1
2
1
Encoding:
0 0 0 0
Operation:
INC
(direct)<-(direct)
<-(direct)
(direct)
STC MCU Limited.
0 1 0 1
direct address
INC @Ri
Bytes:
1
Cycles:
1
0 0 0 0
Encoding:
Operation:
0 1 1 i
INC
((Ri))<-((Ri)) + 1
<-((Ri))
((Ri))
INC DPTR
Function:
Description:
Example:
Bytes:
Cycles:
Increment Data Pointer
Increment the 16-bit data pointer by 1. A 16-bit increment (modulo 216) is performed; an
overflow of the low-order byte of the data pointer (DPL) from 0FFH to 00H will increment
the high-order-byte (DPH). No flags are affected.
This is the only 16-bit register which can be incremented.
Register DPH and DPL contains 12H and 0FEH,respectively. The instruction sequence,
INC DPTR
INC DPTR
INC DPTR
will change DPH and DPL to 13H and 01H.
1
2
1 0
Encoding:
Operation:
JB
1
0
0 0 1 1
INC
(DPTR) <- (DPTR)+1
bit, rel
Function:
Description:
Example:
Bytes:
Cycles:
Encoding:
Operation:
STC MCU Limited.
Jump if Bit set
If the indicated bit is a one, jump to the address indicated; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative-displacement
in the third instruction byte to the PC, after incrementing the PC to the first byte of the next
instruction. The bit tested is not modified. No flags are affected.
The data present at input port 1 is 11001010B. The Accumulator holds 56 (01010110B). The
instruction sequence,
JB
P1.2, LABEL1
JB ACC.2, LABEL2
will cause program execution to branch to the instruction at label LABEL2.
3
2
0 0 1 0
0 0 0 0
JB
(PC) <- (PC)+ 3
IF (bit) = 1
THEN
(PC) <- (PC) + rel
bit address
rel. address
JBC
bit, rel
Function:
Description:
Example:
Jump if Bit is set and Clear bit
If the indicated bit is one,branch to the address indicated;otherwise proceed with the next
instruction.The bit wili not be cleared if it is already a zero. The branch destination is
computed by adding the signed relative-displacement in the third instruction byte to the PC,
after incrementing the PC to the first byte of the next instruction. No flags are affected.
Note: When this instruction is used to test an output pin, the value used as the original data
will be read from the output data latch, not the input pin.
The Accumulator holds 56H (01010110B). The instruction sequence,
JBC
JBC
Bytes:
Cycles:
Encoding:
Operation:
JC
ACC.3, LABEL1
ACC.2, LABEL2
will cause program execution to continue at the instruction identified by the label LABEL2,
with the Accumulator modified to 52H (01010010B).
3
2
0 0 0 1
0 0 0 0
bit address
rel. address
JBC
(PC) <- (PC)+ 3
IF (bit) = 1
THEN
(bit) <- 0
(PC) <- (PC) + rel
rel
Function:
Description:
Example:
Jump if Carry is set
If the carry flag is set, branch to the address indicated; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative-displacement in
the second instruction byte to the PC, after incrementing the PC twice.No flags are affected.
The carry flag is cleared. The instruction sequence,
JC
CPL
JC
Bytes:
Cycles:
Encoding:
Operation:
LABEL1
C
LABEL2s
will set the carry and cause program execution to continue at the instruction identified by the
label LABEL2.
2
2
0 1 0 0
0 0 0 0
JC
(PC) <- (PC)+ 2
IF (C) = 1
THEN
(PC) <- (PC) + rel
STC MCU Limited.
rel. address
JMP @A+DPTR
Function:
Description:
Example:
Jump indirect
Add the eight-bit unsigned contents of the Accumulator with the sixteen-bit data pointer,
and load the resulting sum to the program counter. This will be the address for subsequent
instruction fetches. Sixteen-bit addition is performed (modulo 216): a carry-out from the loworder eight bits propagates through the higher-order bits. Neither the Accumulator nor the
Data Pointer is altered. No flags are affected.
An even number from 0 to 6 is in the Accumulator. The following sequence of instructions
will branch to one of four AJMP instructions in a jump table starting at JMP_TBL:
JMP-TBL:
MOV
JMP
AJMP
AJMP
AJMP
AJMP
DPTR, #JMP_TBL
@A+DPTR
LABEL0
LABEL1
LABEL2
LABEL3
If the Accumulator equals 04H when starting this sequence, execution will jump to label
LABEL2. Remember that AJMP is a two-byte instruction, so the jump instructions start at
every other address.
Bytes:
Cycles:
1
2
0 1 1 1
Encoding:
Operation:
0 0 1 1
JMP
(PC) <- (A) + (DPTR)
JNB bit, rel
Function:
Description:
Example:
Jump if Bit is not set
If the indicated bit is a zero, branch to the indicated address; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative-displacement
in the third instruction byte to the PC, after incrementing the PC to the first byte of the next
instruction. The bit tested is not modified. No flags are affected.
The data present at input port 1 is 11001010B. The Accumulator holds 56H (01010110B).
The instruction sequence,
JNB
JNB
P1.3, LABEL1
ACC.3, LABEL2
will cause program execution to continue at the instruction at label LABEL2
Bytes:
Cycles:
Encoding:
Operation:
STC MCU Limited.
3
2
0 0 1 1
0 0 0 0
JNB
(PC) <- (PC)+ 3
IF (bit) = 0
THEN (PC) <- (PC) + rel
bit address
rel. address
JNC rel
Function:
Description:
Example:
Jump if Carry not set
If the carry flag is a zero, branch to the address indicated; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative-displacement
in the second instruction byte to the PC, after incrementing the PC twice to point to the next
instruction. The carry flag is not modified
The carry flag is set. The instruction sequence,
JNC LABEL1
CPL C
JNC LABEL2
will clear the carry and cause program execution to continue at the instruction identified by
the label LABEL2.
Bytes:
Cycles:
2
2
0 1 0 1
Encoding:
Operation:
JNZ
0 0 0 0
rel. address
JNC
(PC) <- (PC)+ 2
IF (C) = 0
THEN (PC) <- (PC) + rel
rel
Function:
Description:
Example:
Jump if Accumulator Not Zero
If any bit of the Accumulator is a one, branch to the indicated address; otherwise proceed
with the next instruction. The branch destination is computed by adding the signed relativedisplacement in the second instruction byte to the PC, after incrementing the PC twice. The
Accumulator is not modified. No flags are affected.
The Accumulator originally holds 00H. The instruction sequence,
JNZ
INC
JNZ
LABEL1
A
LAEEL2
will set the Accumulator to 01H and continue at label LABEL2.
Bytes:
Cycles:
Encoding:
Operation:
2
2
0 1 1 1
0 0 0 0
JNZ
(PC) <- (PC)+ 2
IF (A) ? 0
THEN (PC) <- (PC) + rel
STC MCU Limited.
rel. address
JZ
rel
Function:
Description:
Example:
Bytes:
Cycles:
Jump if Accumulator Zero
If all bits of the Accumulator are zero, branch to the address indicated; otherwise proceed
with the next instruction. The branch destination is computed by adding the signed relativedisplacement in the second instruction byte to the PC, after incrementing the PC twice. The
Accumulator is not modified. No flags are affected.
The Accumulator originally contains 01H. The instruction sequence,
JZ LABEL1
DEC A
JZ LAEEL2
will change the Accumulator to 00H and cause program execution to continue at the
instruction identified by the label LABEL2.
2
2
0 1 1 0
Encoding:
Operation:
0 0 0 0
rel. address
JZ
(PC) <- (PC)+ 2
IF (A) = 0
THEN (PC) <- (PC) + rel
LCALL addr16
Function:
Description:
Long call
LCALL calls a subroutine loated at the indicated address. The instruction adds three to the
program counter to generate the address of the next instruction and then pushes the 16-bit
result onto the stack (low byte first), incrementing the Stack Pointer by two. The high-order
and low-order bytes of the PC are then loaded, respectively, with the second and third bytes
of the LCALL instruction. Program execution continues with the instruction at this address.
The subroutine may therefore begin anywhere in the full 64K-byte program memory address
space. No flags are affected.
Example:
Initially the Stack Pointer equals 07H. The label "SUBRTN" is assigned to program memory
location 1234H. After executing the instruction,
LCALL SUBRTN
Bytes:
Cycles:
Encoding:
Operation:
STC MCU Limited.
at location 0123H, the Stack Pointer will contain 09H, internal RAM locations 08H and 09H
will contain 26H and 01H, and the PC will contain 1234H.
3
2
0 0 0 1
LCALL
(PC) <- (PC) + 3
(SP) <- (SP) + 1
((SP)) <- (PC7-0)
(SP) <- (SP) + 1
((SP)) <- (PC15-8)
(PC) <- addr15-0
0 0 1 0
addr15-addr8
addr7-addr0
LJMP addr16
Function:
Description:
Example:
Long Jump
LJMP causes an unconditional branch to the indicated address, by loading the high-order
and low-order bytes of the PC (respectively) with the second and third instruction bytes. The
destination may therefore be anywhere in the full 64K program memory address space. No
flags are affected.
The label "JMPADR" is assigned to the instruction at program memory location 1234H. The
instruction,
LJMP JMPADR
at location 0123H will load the program counter with 1234H.
Bytes:
Cycles:
3
2
Encoding:
0 0 0 0
Operation:
0 0 1 0
addr15-addr8
addr7-addr0
LJMP
(PC) <- addr15-0
MOV & lt; dest-byte & gt; , & lt; src-byte & gt;
Function:
Description:
Move byte variable
The byte variable indicated by the second operand is copied into the location specified by the
first operand. The source byte is not affected. No other register or flag is affected.
This is by far the most flexible operation. Fifteen combinations of source and destination
addressing modes are allowed.
Example:
Internal RAM location 30H holds 40H. The value of RAM location 40H is 10H. The data
present at input port 1 is 11001010B (0CAH).
MOV
R0, #30H ;R0 & lt; = 30H
MOV
A, @R0
;A & lt; = 40H
MOV
R1, A
;R1 & lt; = 40H
MOV
B, @Rl
;B & lt; = 10H
MOV
@Rl, Pl
;RAM (40H) & lt; = 0CAH
MOV
P2, P1
;P2 #0CAH
leaves the value 30H in register 0,40H in both the Accumulator and register 1,10H in register
B, and 0CAH(11001010B) both in RAM location 40H and output on port 2.
MOV A,Rn
Bytes:
Cycles:
Encoding:
Operation:
1
1
1 1
1
0
MOV
(A) <- (Rn)
STC MCU Limited.
1 r r r
*MOV A,direct
Bytes:
2
Cycles:
1
1 1 1 0
Encoding:
Operation:
0 1 0 1
direct address
MOV
(A)<- (direct)
<-
*MOV A, ACC is not a valid instruction
MOV A,@Ri
Bytes:
1
Cycles:
1
1 1
Encoding:
Operation:
1
0
0 1 1 i
MOV
(A) <- ((Ri))
MOV A,#data
Bytes:
2
Cycles:
1
Encoding:
0 1 1 1
Operation:
0 1 0 0
immediate data
MOV
(A)<- #data
<-
MOV Rn, A
Bytes:
1
Cycles:
1
1 1 1 1
Encoding:
Operation:
1 r r r
MOV
(Rn)<-(A)
<-(A)
(A)
MOV Rn,direct
Bytes:
2
Cycles:
2
1 0 1 0
Encoding:
Operation:
1 r r r
direct addr.
1 r r r
immediate data
MOV
(Rn)<-(direct)
<-(direct)
(direct)
MOV Rn,#data
Bytes:
2
Cycles:
1
Encoding:
Operation:
STC MCU Limited.
0 1 1 1
MOV
(Rn) <- #data
MOV direct, A
Bytes:
2
Cycles:
1
Encoding:
1 1 1 1
Operation:
0 1 0 1
direct address
MOV
(direct) <- (A)
1 r r r
direct address
0 1 0 1
dir.addr. (src)
MOV direct, Rn
Bytes:
2
Cycles:
2
Encoding:
1 0 0 0
Operation:
MOV
(direct) <- (Rn)
MOV direct, direct
Bytes:
3
Cycles:
2
1 0 0 0
Encoding:
Operation:
MOV
(direct)<- (direct)
<-
MOV direct, @Ri
Bytes:
2
Cycles:
2
Encoding:
1 0 0 0
Operation:
0 1 1 i
direct addr.
MOV
(direct)<-((Ri))
<-((Ri))
((Ri))
MOV direct,#data
Bytes:
3
Cycles:
2
0 1 1 1
Encoding:
Operation:
0 1 0 1
MOV
(direct) <- #data
MOV @Ri, A
Bytes:
1
Cycles:
1
Encoding:
1 1 1 1
Operation:
MOV
((Ri)) <- (A)
STC MCU Limited.
0 1 1 i
direct address
MOV @Ri, direct
Bytes:
2
Cycles:
2
1 0 1 0
Encoding:
0 1 1 i
direct addr.
0 1 1 i
immediate data
MOV
((Ri)) <- (direct)
MOV @Ri, #data
Operation:
Bytes:
2
Cycles:
1
Encoding:
0 1 1 1
Operation:
MOV
((Ri)) <- #data
MOV & lt; dest-bit & gt; , & lt; src-bit & gt;
Function:
Description:
Example:
Move bit data
The Boolean variable indicated by the second operand is copied into the location specified by
the first operand. One of the operands must be the carry flag; the other may be any directly
addressable bit. No other register or flag is affected.
The carry flag is originally set. The data present at input Port 3 is 11000101B. The data
previously written to output Port 1 is 35H (00110101B).
MOV
MOV
MOV
P1.3, C
C, P3.3
P1.2, C
will leave the carry cleared and change Port 1 to 39H (00111001B).
MOV C,bit
Bytes:
Cycles:
2
1
1
Encoding:
Operation:
0
1
0
0
0
1
1
bit address
1
0
0
1
0
bit address
MOV
(C) <- (bit)
MOV bit,C
Bytes:
2
Cycles:
2
Encoding:
Operation:
STC MCU Limited.
1
0
0
MOV
(bit)<- (C)
<-
MOV DPTR , #data 16
Function:
Description:
Example:
Bytes:
Cycles:
Encoding:
Operation:
Load Data Pointer with a 16-bit constant
The Data Pointer is loaded with the 16-bit constant indicated.The 16-bit constant is loaded
into the second and third bytes of the instruction. The second byte (DPH) is the high-order
byte, while the third byte (DPL) holds the low-order byte. No flags are affected.
This is the only instruction which moves 16 bits of data at once.
The instruction,
MOV DPTR, #1234H
will load the value 1234H into the Data Pointer: DPH will hold 12H and DPL will hold 34H.
3
2
1
0
0
1
0
0
0
0
immediate data 15-8
MOV
(DPTR) <- #data15-0
DPH DPL <- #data15-8 #data7-0
MOVC A , @A+ & lt; base-reg & gt;
Function:
Description:
Move Code byte
The MOVC instructions load the Accumulator with a code byte, or constant from program
memory. The address of the byte fetched is the sum of the original unsigned eight-bit.
Accumulator contents and the contents of a sixteen-bit base register, which may be either
the Data Pointer or the PC. In the latter case, the PC is incremented to the address of the
following instruction before being added with the Accumulator; otherwise the base register
is not altered. Sixteen-bit addition is performed so a carry-out from the low-order eight bits
may propagate through higher-order bits. No flags are affected.
Example:
A value between 0 and 3 is in the Accumulator. The following instructions will translate the
value in the Accumulator to one of four values defimed by the DB (define byte) directive.
REL-PC: INC
A
MOVC A, @A+PC
RET
DB
66H
DB
77H
DB
88H
DB
99H
If the subroutine is called with the Accumulator equal to 01H, it will return with 77H in the
Accumulator. The INC A before the MOVC instruction is needed to "get around" the RET
instruction above the table. If several bytes of code separated the MOVC from the table, the
corresponding number would be added to the Accumulator instead.
MOVC A,@A+DPTR
Bytes: 1
Cycles: 2
Encoding:
Operation:
1 0
0
1
0 0 1 1
MOVC
(A) <- ((A)+(DPTR))
STC MCU Limited.
MOVC A,@A+PC
Bytes:
1
Cycles:
2
1 0 0 0
Encoding:
Operation:
MOVX
0 0 1 1
MOVC
(PC) <- (PC)+1
(A) <- ((A)+(PC))
& lt; dest-byte & gt; , & lt; src-byte & gt;
Function:
Description:
Move External
The MOVX instructions transfer data between the Accumulator and a byte of external data
memory, hence the "X" appended to MOV. There are two types of instructions, differing in
whether they provide an eight-bit or sixteen-bit indirect address to the external data RAM.
In the first type, the contents of R0 or R1 in the current register bank provide an eight-bit
address multiplexed with data on P0. Eight bits are sufficient for external I/O expansion
decoding or for a relatively small RAM array. For somewhat larger arrays, any output port
pins can be used to output higher-order address bits. These pins would be controlled by an
output instruction preceding the MOVX.
In the second type of MOVX instruction, the Data Pointer generates a sixteen-bit address.
P2 outputs the high-order eight address bits (the contents of DPH) while P0 multiplexes the
low-order eight bits (DPL) with data. The P2 Special Function Register retains its previous
contents while the P2 output buffers are emitting the contents of DPH. This form is faster and
more efficient when accessing very large data arrays (up to 64K bytes), since no additional
instructions are needed to set up the output ports.
It is possible in some situations to mix the two MOVX types. A large RAM array with its
high-order address lines driven by P2 can be addressed via the Data Pointer, or with code to
output high-order address bits to P2 followed by a MOVX instruction using R0 or R1.
Example:
An external 256 byte RAM using multiplexed address/data lines (e.g., an Intel 8155 RAM/
I/O/Timer) is connected to the 8051 Port 0. Port 3 provides control lines for the external
RAM. Ports 1 and 2 are used for normal I/O. Registers 0 and 1 contain 12H and 34H.
Location 34H of the external RAM holds the value 56H. The instruction sequence,
MOVX
MOVX
A, @R1
@R0, A
copies the value 56H into both the Accumulator and external RAM location 12H.
MOVX A,@Ri
Bytes:
Cycles:
Encoding:
Operation:
STC MCU Limited.
1
2
1 1
1
0
MOVX
(A) <- ((Ri))
0 0 1 i
MOVX A,@DPTR
Bytes:
1
Cycles:
2
Encoding:
1 1 1 0
Operation:
MOVX
(A) <- ((DPTR))
MOVX
0 0 0 0
@Ri, A
Bytes:
1
Cycles:
2
Encoding:
1 1 1 1
Operation:
MOVX
((Ri))<- (A)
<-
MOVX
0 0 1 i
@DPTR, A
Bytes:
1
Cycles:
2
1 1 1 1
Encoding:
Operation:
0 0 0 0
MOVX
(DPTR)<-(A)
<-(A)
(A)
MUL AB
Function:
Description:
Example:
Multiply
MUL AB multiplies the unsigned eight-bit integers in the Accumulator and register B. The
low-order byte of the sixteen-bit product is left in the Accumulator, and the high-order byte
in B. If the product is greater than 255 (0FFH) the overflow flag is set; otherwise it is cleared.
The carry flag is always cleared
Originally the Accumulator holds the value 80 (50H). Register B holds the value 160
(0A0H). The instruction,
MUL AB
will give the product 12,800 (3200H), so B is changed to 32H (00110010B) and the
Accumulator is cleared. The overflow flag is set, carry is cleared.
Bytes:
Cycles:
Encoding:
Operation:
1
4
1
0
1
0
0
MUL
(A)7-0 <- (A)×(B)
(B)15-8
STC MCU Limited.
1
0
0
NOP
Function:
Description:
Example:
No Operation
Execution continues at the following instruction. Other than the PC, no registers or flags are
affected.
It is desired to produce a low-going output pulse on bit 7 of Port 2 lasting exactly 5 cycles. A
simple SETB/CLR sequence would generate a one-cycle pulse, so four additional cycles
must be inserted. This may be done (assuming no interrupts are enabled) with the instruction
sequence.
CLR
NOP
NOP
NOP
NOP
SETB
Bytes:
Cycles:
Encoding:
Operation:
P2.7
P2.7
1
1
0
0
0
0
0
0
0
0
NOP
(PC) <- (PC)+1
ORL & lt; dest-byte & gt; , & lt; src-byte & gt;
Function:
Description:
Logical-OR for byte variables
ORL performs the bitwise logical-OR operation between the indicated variables, storing the
results in the destination byte. No flags are affected.
The two operands allow six addressing mode combinations. When the destination is the
Accumulator, the source can use register, direct, register-indirect, or immediate addressing;
when the destination is a direct address, the source can be the Accumulator or immediate
data.
Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
Example:
If the Accumulator holds 0C3H (11000011B) and R0 holds 55H (01010101B) then the
instruction,
ORL
A, R0
will leave the Accumulator holding the value 0D7H (11010111B).
When the destination is a directly addressed byte, the instruction can set combinations of bits
in any RAM location or hardware register. The pattern of bits to be set is determined by a
mask byte, which may be either a constant data value in the instruction or a variable
computed in the Accumulator at run-time.The instruction,
ORL
P1, #00110010B
will set bits 5,4, and 1of output Port 1.
STC MCU Limited.
ORL A,Rn
Bytes:
Cycles:
1
1
0
Encoding:
Operation:
1
0
ORL
(A) <- (A)
0
1
r
r
r
1
0
1
(Rn)
ORL A,direct
Bytes:
2
Cycles:
1
0
Encoding:
Operation:
1
0
ORL
(A)<- (A)
<-
0
0
direct address
(direct)
ORL A,@Ri
Bytes:
Cycles:
1
1
0
Encoding:
Operation:
1
0
ORL
(A)<- (A)
<-
0
0
1
1
i
1
0
0
((Ri))
ORL A,#data
Bytes:
2
Cycles:
1
0
Encoding:
Operation:
1
0
ORL
(A)<- (A)
<-
0
0
immediate data
#data
ORL direct, A
Bytes:
2
Cycles:
1
0
Encoding:
Operation:
1
0
0
0
0
1
0
direct address
1
direct address
ORL
(direct)<- (direct) (A)
<-
ORL direct, #data
Bytes:
3
Cycles:
2
Encoding:
Operation:
0
1
0
0
0
0
1
ORL
(direct) <- (direct) #data
STC MCU Limited.
immediate data
ORL
C, & lt; src-bit & gt;
Function:
Description:
Example:
ORL C, bit
Bytes:
Cycles:
Logical-OR for bit variables
Set the carry flag if the Boolean value is a logical 1; leave the carry in its current state
otherwise. A slash (" / ") preceding the operand in the assembly language indicates that the
logical complement of the addressed bit is used as the source value, but the source bit itself is
not affected. No other flags are affected.
Set the carry flag if and only if P1.0 = 1, ACC. 7 = 1, or OV = 0:
MOV
C, P1.0
;LOAD CARRY WITH INPUT PIN P10
ORL
C, ACC.7
;OR CARRY WITH THE ACC.BIT 7
ORL
C, /OV
;OR CARRY WITH THE INVERSE OF OV
2
2
0
Encoding:
Operation:
1
1
1
0
0
1
0
bit address
0
0
0
bit address
ORL
(C) <- (C) (bit)
ORL C, /bit
Bytes:
2
Cycles:
2
Encoding:
Operation:
1
0
1
0
0
ORL
(C) <- (C) (bit)
POP direct
Function:
Description:
Example:
Bytes:
Cycles:
Encoding:
Operation:
STC MCU Limited.
Pop from stack
The contents of the internal RAM location addressed by the Stack Pointer is read, and the
Stack Pointer is decremented by one. The value read is then transferred to the directly
addressed byte indicated. No flags are affected.
The Stack Pointer originally contains the value 32H, and internal RAM locations 30H
through 32H contain the values 20H, 23H, and 01H, respectively. The instruction sequence,
POP DPH
POP DPL
will leave the Stack Pointer equal to the value 30H and the Data Pointer set to 0123H. At this
point the instruction,
POP SP
will leave the Stack Pointer set to 20H. Note that in this special case the Stack Pointer was
decremented to 2FH before being loaded with the value popped (20H).
2
2
1
1
0 1
POP
(diect) <- ((SP))
(SP) <- (SP) - 1
0
0
0
0
direct address
PUSH direct
Function:
Description:
Example:
Push onto stack
The Stack Pointer is incremented by one. The contents of the indicated variableis then copied
into the internal RAM location addressed by the Stack Pointer. Otherwise no flags are
affected.
On entering interrupt routine the Stack Pointer contains 09H. The Data Pointer holds the
value 0123H. The instruction sequence,
PUSH
PUSH
DPL
DPH
will leave the Stack Pointer set to 0BH and store 23H and 01H in internal RAM locations
0AH and 0BH, respectively.
Bytes:
2
Cycles:
Encoding:
2
Operation:
1
1
0 0
0
0
0
0
direct address
PUSH
(SP) <- (SP) + 1
((SP)) <- (direct)
RET
Function:
Return from subroutine
Description:
RET pops the high-and low-order bytes of the PC successively from the stack, decrementing
the Stack Pointer by two. Program execution continues at the resulting address, generally the
instruction immediately following an ACALL or LCALL. No flags are affected.
Example:
The Stack Pointer originally contains the value 0BH. Internal RAM locations 0AH and 0BH
contain the values 23H and 01H, respectively. The instruction,
RET
will leave the Stack Pointer equal to the value 09H. Program execution will continue at
location 0123H.
Bytes:
Cycles:
Encoding:
Operation:
1
2
0
0
1 0
0
RET
(PC15-8) <- ((SP))
(SP) <- (SP) -1
(PC7-0) <- ((SP))
(SP) <- (SP) -1
STC MCU Limited.
0
1
0
RETI
Function:
Description:
Example:
Return from interrupt
RETI pops the high- and low-order bytes of the PC successively from the stack, and restores
the interrupt logic to accept additional interrupts at the same priority level as the one just
processed. The Stack Pointer is left decremented by two. No other registers are affected; the
PSW is not automatically restored to its pre-interrupt status. Program execution continues at
the resulting address, which is generally the instruction immediately after the point at which
the interrupt request was detected. If a lower- or same-level interrupt had been pending when
the RETI instruction is executed, that one instruction will be executed before the pending
interrupt is processed.
The Stack Pointer originally contains the value 0BH. An interrupt was detected during the
instruction ending at location 0122H. Internal RAM locations 0AH and 0BH contain the
values 23H and 01H, respectively. The instruction,
RETI
will leave the Stack Pointer equal to 09H and return program execution to location 0123H.
Bytes:
Cycles:
Encoding:
Operation:
1
2
0
0
1 1
0
0
1
0
RETI
(PC15-8) <- ((SP))
(SP) <- (SP) -1
(PC7-0) <- ((SP))
(SP) <- (SP) -1
RL A
Function:
Description:
Example:
Rotate Accumulator Left
The eight bits in the Accumulator are rotated one bit to the left. Bit 7 is rotated into the bit 0
position. No flags are affected.
The Accumulator holds the value 0C5H (11000101B). The instruction,
RL
A
leaves the Accumulator holding the value 8BH (10001011B) with the carry unaffected.
Bytes:
Cycles:
Encoding:
Operation:
STC MCU Limited.
1
1
0
0
1 0
RL
(An+1) <- (An)
(A0) <- (A7)
0
0
1
n = 0-6
1
RLC A
Function:
Description:
Example:
Bytes:
Cycles:
Rotate Accumulator Left through the Carry flag
The eight bits in the Accumulator and the carry flag are together rotated one bit to the left. Bit
7 moves into the carry flag; the original state of the carry flag moves into the bit 0 position.
No other flags are affected.
The Accumulator holds the value 0C5H (11000101B), and the carry is zero. The instruction,
RLC A
leaves the Accumulator holding the value 8BH (10001011B) with the carry set.
1
1
0
Encoding:
Operation:
0
1 1
RLC
(An+1) <- (An)
(A0) <- (C)
(C) <- (A7)
0
0
1
1
n = 0-6
RR A
Function:
Description:
Example:
Bytes:
Cycles:
Encoding:
Operation:
Rotate Accumulator Right
The eight bits in the Accumulator are rotated one bit to the right. Bit 0 is rotated into the bit 7
position. No flags are affected.
The Accumulator holds the value 0C5H (11000101B). The instruction,
RR A
leaves the Accumulator holding the value 0E2H (11100010B) with the carry unaffected.
1
1
0
0
0 0
RR
(An) <- (An+1)
(A7) <- (A0)
0
0
1
1
n=0-6
RRC A
Function:
Description:
Example:
Bytes:
Cycles:
Encoding:
Operation:
Rotate Accumulator Right through the Carry flag
The eight bits in the Accumulator and the carry flag are together rotated one bit to the right.
Bit 0 moves into the carry flag; the original value of the carry flag moves into the bit 7
position.No other flags are affected.
The Accumulator holds the value 0C5H (11000101B), and the carry is zero. The instruction,
RRC A
leaves the Accumulator holding the value 62H (01100010B) with the carry set.
1
1
0
0
0 1
RRC
(An+1) <- (An)
(A7) <- (C)
(C) <- (A0)
STC MCU Limited.
0
0
1
n = 0-6
1
SETB
& lt; bit & gt;
Function:
Description:
Example:
SETB
C
Bytes:
Cycles:
Set bit
SETB sets the indicated bit to one. SETB can operate on the carry flag or any directly
addressable bit. No other flags are affected
The carry flag is cleared. Output Port 1 has been written with the value 34H (00110100B).
The instructions,
SETB
C
SETB
P1.0
will leave the carry flag set to 1 and change the data output on Port 1 to 35H (00110101B).
1
1
1
Encoding:
Operation:
SETB
1
0 1
0
0
1
1
0
0
0
1
0
SETB
(C) <- 1
bit
Bytes:
2
Cycles:
1
1
Encoding:
Operation:
1
1
bit address
SETB
(bit) <- 1
SJMP rel
Function:
Short Jump
Description:
Program control branches unconditionally to the address indicated. The branch destination is
computed by adding the signed displacement in the second instruction byte to the PC, after
incrementing the PC twice. Therefore, the range of destinations allowed is from 128bytes
preceding this instruction to 127 bytes following it.
Example:
The label "RELADR" is assigned to an instruction at program memory location 0123H. The
instruction,
SJMP RELADR
will assemble into location 0100H. After the instruction is executed, the PC will contain the
value 0123H.
(Note: Under the above conditions the instruction following SJMP will be at 102H.Therefore,
the displacement byte of the instruction will be the relative offset (0123H - 0102H) = 21H.
Put another way, an SJMP with a displacement of 0FEH would be an one-instruction infinite
loop).
Bytes:
2
Cycles:
2
Encoding:
Operation:
STC MCU Limited.
1
0
0 0
0
SJMP
(PC) <- (PC)+2
(PC) <- (PC)+rel
0
0
0
rel. address
SUBB A, & lt; src-byte & gt;
Function:
Description:
Subtract with borrow
SUBB subtracts the indicated variable and the carry flag together from the Accumulator,
leaving the result in the Accumulator. SUBB sets the carry (borrow)flag if a borrow is needed
for bit 7, and clears C otherwise.(If C was set before executing a SUBB instruction, this
indicates that a borrow was needed for the previous step in a multiple precision subtraction,
so the carry is subtracted from the Accumulator along with the source operand).AC is set if a
borrow is needed for bit 3, and cleared otherwise. OV is set if a borrow is needed into bit 6,
but not into bit 7, or into bit 7, but not bit 6.
When subtracting signed integers OV indicates a negative number produced when a negative
value is subtracted from a positive value, or a positive result when a positive number is
subtracted from a negative number.
The source operand allows four addressing modes: register, direct, register-indirect, or
immediate.
Example:
The Accumulator holds 0C9H (11001001B), register 2 holds 54H (01010100B), and the
carry flag is set. The instruction,
SUBB
A, R2
will leave the value 74H (01110100B) in the accumulator, with the carry flag and AC cleared
but OV set.
Notice that 0C9H minus 54H is 75H. The difference between this and the above result is due
to the carry (borrow) flag being set before the operation. If the state of the carry is not known
before starting a single or multiple-precision subtraction, it should be explicitly cleared by a
CLR C instruction.
SUBB A, Rn
Bytes:
Cycles:
Encoding:
Operation:
1
1
1 0
0
1
1 r r r
SUBB
(A) <- (A) - (C) - (Rn)
SUBB A, direct
Bytes: 2
Cycles: 1
Encoding:
1 0 0 1 0 1 0 1
Operation: SUBB
(A) <- (A) - (C) - (direct)
SUBB A, @Ri
Bytes:
Cycles:
Encoding:
Operation:
1
1
1
0
0
1
0
1
1
SUBB
(A) <- (A) - (C) - ((Ri))
STC MCU Limited.
i
direct address
SUBB A, #data
Bytes:
Cycles:
Encoding:
Operation:
2
1
1
0
0
1
0
1
0
0
immediate data
SUBB
(A) <- (A) - (C) - #data
SWAP A
Function:
Description:
Example:
Swap nibbles within the Accumulator
SWAP A interchanges the low- and high-order nibbles (four-bit fields) of the Accumulator
(bits 3-0 and bits 7-4). The operation can also be thought of as a four-bit rotate instruction.
No flags are affected.
The Accumulator holds the value 0C5H (11000101B). The instruction,
SWAP
Bytes:
Cycles:
A
leaves the Accumulator holding the value 5CH (01011100B).
1
1
Encoding:
1
Operation:
SWAP
(A3-0)
1
0 0
0
1
0
0
(A7-4)
XCH A, & lt; byte & gt;
Function:
Description:
Exchange Accumulator with byte variable
XCH loads the Accumulator with the contents of the indicated variable, at the same time
writing the original Accumulator contents to the indicated variable. The source/destination
operand can use register, direct, or register-indirect addressing.
Example:
R0 contains the address 20H. The Accumulator holds the value 3FH (00111111B). Internal
RAM location 20H holds the value 75H (01110101B). The instruction,
XCH
A, @R0
will leave RAM location 20H holding the values 3FH (00111111B) and 75H (01110101B) in
the accumulator.
XCH A, Rn
Bytes:
Cycles:
Encoding:
Operation:
XCH A, direct
Bytes:
Cycles:
Encoding:
Operation:
STC MCU Limited.
1
1
1 1
XCH
(A)
0
0
1 r r r
(Rn)
2
1
1 1 0 0
XCH
(A)
0 1 0 1
(direct)
direct address
XCH A, @Ri
1
1
Bytes:
Cycles:
Encoding:
1 1 0 0
XCH
(A)
Operation:
0 1 1
i
((Ri))
XCHD A, @Ri
Function:
Description:
Example:
Exchange Digit
XCHD exchanges the low-order nibble of the Accumulator (bits 3-0), generally representing
a hexadecimal or BCD digit, with that of the internal RAM location indirectly addressed by
the specified register. The high-order nibbles (bits 7-4) of each register are not affected. No
flags are affected.
R0 contains the address 20H. The Accumulator holds the value 36H (00110110B). Internal
RAM location 20H holds the value 75H (01110101B). The instruction,
XCHD
Bytes:
Cycles:
Encoding:
Operation:
A, @R0
will leave RAM location 20H holding the value 76H (01110110B) and 35H (00110101B) in
the accumulator.
1
1
1 1 0 1
XCHD
(A3-0)
0 1 1 i
(Ri3-0)
XRL & lt; dest-byte & gt; , & lt; src-byte & gt;
Function:
Description:
Logical Exclusive-OR for byte variables
XRL performs the bitwise logical Exclusive-OR operation between the indicated variables,
storing the results in the destination. No flags are affected.
The two operands allow six addressing mode combinations.When the destination is the
Accumulator, the source can use register, direct, register-indirect, or immediate addressing;
when the destination is a direct address,the source can be the Accumulator or immediate data.
(Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.)
Example:
If the Accumulator holds 0C3H (11000011B) and register 0 holds 0AAH (10101010B) then
the instruction,
XRL
A, R0
will leave the Accumulator holding the vatue 69H (01101001B).
When the destination is a directly addressed byte, this instruction can complement combinnation of bits in any RAM location or hardware register. The pattern of bits to be complemented
is then determined by a mask byte, either a constant contained in the instruction or a variable
computed in the Accumulator at run-time. The instruction,
XRL
P1, #00110001B
will complement bits 5,4 and 0 of outpue Port 1.
STC MCU Limited.
XRL A, Rn
Bytes:
Cycles:
Encoding:
Operation:
1
1
0 1
1
0
XRL
(A) <- (A)
1 r r r
(Rn)
XRL A, direct
Bytes:
2
Cycles:
1
0 1 1 0
Encoding:
Operation:
0 1 0 1
XRL
(A) <- (A)
direct address
(direct)
XRL A, @Ri
Bytes:
1
Cycles:
1
0 1
Encoding:
Operation:
1
0
XRL
(A) <- (A)
0 1 1 i
((Ri))
XRL A, #data
Bytes:
2
Cycles:
1
0 1
Encoding:
Operation:
1
0
XRL
(A) <- (A)
0 1 0 0
immediate data
#data
XRL direct, A
Bytes:
2
Cycles:
1
0 1
Encoding:
Operation:
1
0
0 0 1 0
XRL
(direct) <- (direct)
direct address
(A)
XRL direct, #dataw
Bytes:
3
Cycles:
2
Encoding:
Operation:
STC MCU Limited.
0 1
1
0
0 0 1 1
XRL
(direct) <- (direct)
# data
direct address
immediate data
Chapter 6. Interrupt System
STC90C51RC/RD+ series support 8 interrupt sources with four priority levels. The 8 interrupt sources are
external interrupt 0(INT0), Timer 0 interrrupt, external interrupt 1(INT1), Timer 1 interrrupt, serial port (UART)
interrupt, Timer 2 interrupt, external interrupt 2(INT2) and external interrupt 3(INT3). Each interrupt source has
one or more associated interrupt-request flag(s) in SFRs. Associating with each interrupt vector, the interrupt
sources can be individually enabled or disabled by setting or clearing a bit (interrupt enalbe control bit) in the
SFRs IE and XICON. However, interrupts must first be globally enabled by setting the EA bit (IE.7) to
logic 1 before the individual interrupt enables are recognized. Setting the EA bit to logic 0 disables all
interrupt sources regardless of the individual interrupt-enable settings.
If interrupts are enabled for the source, an interrupt request is generated when the interrupt-request
flag is set. As soon as execution of the current instruction is complete, the CPU generates an LCALL
to a predetermined address to begin execution of an interrupt service routine (ISR). Each ISR must
end with an RETI instruction, which returns program execution to the next instruction that would have
been executed if the interrupt request had not occurred. If interrupts are not enabled, the interruptpending flag is ignored by the hardware and program execution continues as normal. (The interruptpending flag is set to logic 1 regardless of the interrupt's enable/disable state.)
Each interrupt source has two corresponding bits to represent its priority. One is located in SFR named IPH and
other in IP register. Higher-priority interrupt will be not interrupted by lower-priority interrupt request. If two
interrupt requests of different priority levels are received simultaneously, the request of higher priority is serviced.
If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determine
which request is serviced. The following table shows the internal polling sequence in the same priority level and
the interrupt vector address.
Interrupt Sources, vector address, priority and polling sequence Table
Interrupt Priority
Interrupt
Interrupt Priority Priority 0
Priority Priority 3 Interrupt
Vector within
Priority 1
2
(highest) Request
Source
setting(IPH, IP) (lowest)
address
level
External
interrupt 0
(INT0)
Interrupt
Enable
Control Bit
0003H
0(highest)
PX0H,PX0
0,0
0,1
1,0
1,1
IE0
EX0/EA
Timer 0
External
interrupt 1
(INT1)
000BH
1
PT0H,PT0
0,0
0,1
1,0
1,1
TF0
ET0/EA
0013H
2
PX1H,PX1
0,0
0,1
1,0
1,1
IE1
EX1/EA
Timer1
Serial Port
(UART)
Timer2
External
interrupt 2
( INT2 )
External
interrupt 3
( INT3 )
001BH
3
PT1H,PT1
0,0
0,1
1,0
1,1
TF1
ET1/EA
0023H
4
PSH,PS
0,0
0,1
1,0
1,1
RI+TI
ES/EA
002BH
5
PT2H, PT2
0, 0
0, 1
1, 0
1, 1
TF2 + EXF2
ET2/EA
0033H
6
PX2H, PX2
0, 0
0, 1
1, 0
1, 1
IE2
EX2/EA
PX3H, PX3
0, 0
0, 1
1, 0
1, 1
IE3
EX3/EA
003BH 7(lowest)
STC MCU Limited.
In C language program. the interrupt polling sequence number is equal to interrupt number, for example:
void
Int0_Routine(void)
interrupt 0;
void
Timer0_Rountine(void)
interrupt 1;
void
Int1_Routine(void)
interrupt 2;
void
Timer1_Rountine(void)
interrupt 3;
void
UART_Routine(void)
interrupt 4;
void
Timer2_Routine(void)
interrupt 5;
void
Int2_Routine(void)
interrupt 6;
void
Int3_Routine(void)
interrupt 7;
STC MCU Limited.
6.1 Interrupt Structure
The interrupt structure of STC90C51RC/RD+ series is shown as below.
Interrupt Enable
Conterol Registers
IE, XICON Register
TCON.0/IT0=0
IE0
INT0
EX0
EA
TCON.0/IT0=1
TCON.2/IT1=0
IE1
INT1
TCON.2/IT1=1
PT1H, PT1
CU
M
ET1
Timer1 / TF1
PSH, PS
ES
UART RI
TI
Timer2 TF2
EXF2
TC
S
XICON.0/IT2=0
IE2
INT2
PX0H, PX0
PX1H, PX1
EX1
PT2H, PT2
ET2
PX2H, PX2
EX2
lowest Priority
Level Interrupt
Highest Priority
Level Interrupt
IP, XICON ,IPH
Registers
PT0H, PT0
ET0
Timer0 / TF0
Interrupt Priority
Conterol Registers
0,0
0,1
0,1
Li
0,0
0,0
0,0
0,0
1,1
ed.
it
m
0,0
0,0
1,0
0,1
0,1
0,1
0,1
0,1
1,0
1,0
1,0
1,0
1,0
1,0
high
1,1
1,1
1,1
1,1
Interrupt
Polling
Sequence
1,1
1,1
XICON.0/IT2=1
XICON.4/IT3=0
IE3
INT3
PX3H, PX3
EX3
0,0
0,1
1,0
1,1
XICON.4/IT3=1
low
EA
Global Enable
EA
Figure STC90C51RC/RD+ series Interrupt Structure diagram
STC MCU Limited.
The External Interrupts INT0 , INT1 , INT2 and INT3 can each be either level-activated or transition-activated,
depending on bits IT0/TCON.0, IT1/TCON.2, IT2/XICON.0 and IT3/XICON.4. The flags that actually generate
these interrupts are bits IE0/TCON.1, IE1/TCON.3, IE2/XICON.2 and IE3/XICON.5. When an external interrupt
is generated, the flag that generated it is cleared by the hardware when the service routine is vectored to if and
only if the interrupt was transition -activated, otherwise the external requesting source is what controls the
request flag, rather than the on-chip hardware.
The Timer 0 and Timer1 Interrupts are generated by TF0 and TF1, which are set by a rollover in their respective
Timer/Counter registers in most cases. When a timer interrupt is generated, the flag that generated it is cleared by
the on-chip hardware when the service routine is vectored to.
The Serial Port Interrupt is generated by the logical OR of RI and TI. Neither of these flags is cleared by
hardware when the service routine is vectored to. In fact, the service routine will normally have to determine
whether it was RI and TI that generated the interrupt, and the bit will have to be cleared by software.
Timer2 interrupt is generated by the logical OR of TF2 and EXF2. TF2 is set by a rollover in Timer/Counter 2
registers --TL2 and TH2 in most cases. Just the same as serial port, neither of these flags is cleared by hardware
when the service routine is vectored to.
All of the bits that generate interrupts can be set or cleared by software, with the same result as though it had
been set or cleared by hardware. In other words, interrupts can be generated or pending interrupts can be canceled
in software.
All interrupts trigger behavior are summed up as below.
Interrupt Trigger Behavior
Interrupt Sources
Trigger Behavior
INT0
(IT0/TCON.0 = 1): falling edge
(External interrupt 0)
Timer 0
(IT0/TCON.0 = 0): Active-low level
Timer 0 overflow
INT1
(IT1/TCON.2 = 1): falling edge
(External interrupt 1)
Timer1
Timer 1 overflow
UART
Finish sending or receiving
Timer2
(IT1/TCON.2 = 0): Active-low level
Timer 2 overflow
INT2
(IT2/XICON.0 = 1): falling edge
(External interrupt 2)
(IT2/XICON.0 = 0): Active-low level
INT3
(IT3/XICON.4 = 1): falling edge
(External interrupt 3)
(IT3/XICON.4 = 0): Active-low level
STC MCU Limited.
6.2 Interrupt Register
Value after
Power-on or
Reset
LSB
EX0 0x00 0000B
Bit Address and Symbol
Symbol
Description
Address
IE
Interrupt Enable
Interrupt Priority
Low
Interrupt Priority
High
Timer/Counter 0 and
1 Control
A8H
EA
B8H
-
-
PT2
B7H
PX3H
PX2H
PT2H
88H
TF1
TR1
TF0
TR0
IE1
IT1
Serial Control
98H
SM0/FE
SM1
SM2
REN
TB8
RB8
MSB
IP
IPH
TCON
SCON
T2CON
XICON
Timer/Counter 2
Control
Auxiliary Interupt
Control
C8H
C0H
-
ET2
ES
PS
ET1
EX1
ET0
PT1
PX1
PT0
EX3
IE3
xx00 0000B
PX0H
0000,0000B
IE0
IT0
0000 0000B
TI
RI
0000 0000B
PSH PT1H PX1H PT0H
TF2 EXF2 RCLK TCLK EXEN2
PX3
PX0
IT3
PX2
C/T2 CP/RL2
TR2
EX2
IE2
IT2
0000 0000B
0000 0000B
1. Interrupt Enable control Registers IE and XICON
IE: Interrupt Enable Rsgister (Bit-addressable)
SFR name Address
IE
A8H
bit
B7
B6
B5
B4
B3
B2
B1
B0
name
EA
-
ET2
ES
ET1
EX1
ET0
EX0
Enable Bit = 1 enables the interrupt .
Enable Bit = 0 disables it .
EA (IE.7): disables all interrupts. If EA = 0,no interrupt will be acknowledged. If EA = 1, each interrupt
source is individually enabled or disabled by setting or clearing its enable bit.
ET2 (IE.5): Timer 2 interrupt enable bit. If ET2 = 0, Timer 2 interrupt will be diabled. If ET2 = 1, Timer 2
interrupt is enabled.
ES (IE.4): Serial Port (UART) interrupt enable bit. If ES = 0, UART interrupt will be diabled. If ES = 1,
UART interrupt is enabled.
ET1 (IE.3): Timer 1 interrupt enable bit. If ET1 = 0, Timer 1 interrupt will be diabled. If ET1 = 1, Timer 1
interrupt is enabled.
EX1 (IE.2): External interrupt 1 enable bit. If EX1 = 0, external interrupt 1 will be diabled. If EX1 = 1,
external interrupt 1 is enabled.
ET0 (IE.1): Timer 0 interrupt enable bit. If ET0 = 0, Timer 0 interrupt will be diabled. If ET0 = 1, Timer 0
interrupt is enabled.
EX0 (IE.0): External interrupt 0 enable bit. If EX0 = 0, external interrupt 0 will be diabled. If EX0 = 1,
external interrupt 0 is enabled.
STC MCU Limited.
XICON: Auxiliary Interrupt Control Rsgister ( bit-addressable)
SFR name Address
XICON
C0H
bit
B7
B6
B5
B4
B3
B2
B1
B0
name
PX3
EX3
IE3
IT3
PX2
EX2
IE2
IT2
PX3 and PX3H/IPH.7 together control the external interrupt 3 priority. See the descriptions of IPH register.
EX3 : External interrupt 3 enable bit.
If EX3 = 0, external interrupt 3 will be diabled.
If EX3 = 1, external interrupt 3 is enabled.
IE3 : External Interrupt 3 Edge flag. Set by hardware when external interrupt edge/level defined by IT3 is
detected. The flag can be cleared by software but is automatically cleared when the external interrupt 3
service routine has been processed.
IT3 : External Intenupt 3 Type Select bit. Set/cleared by software to specify falling edge/low level triggered
external interrupt 3.
If IT3 = 0, INT3 is low level triggered.
If IT3 = 1, INT3 is edge triggered.
PX2 and PX2H/IPH.6 together control the external interrupt 2 priority. See the descriptions of IPH register.
EX2 : External interrupt 2 enable bit.
If EX2 = 0, external interrupt 2 will be diabled.
If EX2 = 1, external interrupt 2 is enabled.
IE2 : External Interrupt 2 Edge flag. Set by hardware when external interrupt edge/level defined by IT2 is
detected. The flag can be cleared by software but is automatically cleared when the external interrupt 2
service routine has been processed.
IT2 : External Intenupt 2 Type Select bit. Set/cleared by software to specify falling edge/low level triggered
external interrupt 2.
If IT2 = 0, INT2 is low level triggered.
If IT2 = 1, INT2 is edge triggered.
STC MCU Limited.
2. Interrupt Priority control Registers IP, XICON and IPH
Each interrupt source of STC90C51RC/RD+ all can be individually programmed to one of four priority levels by
setting or clearing the bits in Special Function Registers IP/XICON or IPH. A low-priority interrupt can itself be
interrupted by a high-pority interrupt, but not by another low-priority interrupt. A high-priority interrupt can't be
interrupted by any other interrupt source.
IPH: Interrupt Priority High Register (Non bit-addressable)
SFR name Address
IPH
B7H
bit
B7
B6
B5
B4
name
PX3H
PX2H
PT2H
PSH
B3
B2
B1
PT1H PX1H PT0H
B0
PX0H
XICON: Auxiliary Interrupt Control Rsgister ( bit-addressable)
SFR name Address
XICON
C0H
bit
B7
B6
B5
B4
B3
B2
B1
B0
name
PX3
EX3
IE3
IT3
PX2
EX2
IE2
IT2
IP: Interrupt Priority Register (Bit-addressable)
SFR name Address
IP
B8H
bit
B7
B6
B5
B4
B3
B2
B1
B0
name
-
-
PT2
PS
PT1
PX1
PT0
PX0
PX3H, PX3: External interrupt 3 priority control bits.
if PX3H=0 and PX3=0, External interrupt 3 is assigned lowest priority (priority 0).
if PX3H=0 and PX3=1, External interrupt 3 is assigned lower priority (priority 1).
if PX3H=1 and PX3=0, External interrupt 3 is assigned higher priority (priority 2).
if PX3H=1 and PX3=1, External interrupt 3 is assigned highest priority (priority 3).
PX2H, PX2: External interrupt 2 priority control bits.
if PX2H=0 and PX2=0, External interrupt 2 is assigned lowest priority (priority 0).
if PX2H=0 and PX2=1, External interrupt 2 is assigned lower priority (priority 1).
if PX2H=1 and PX2=0, External interrupt 2 is assigned higher priority (priority 2).
if PX2H=1 and PX2=1, External interrupt 2 is assigned highest priority (priority 3).
PT2H, PT2: Timer 2 interrupt priority control bits.
if PT2H=0 and PT2=0, Timer 2 interrupt is assigned lowest priority (priority 0).
if PT2H=0 and PT2=1, Timer 2 interrupt is assigned lower priority (priority 1).
if PT2H=1 and PT2=0, Timer 2 interrupt is assigned higher priority (priority 2).
if PT2H=1 and PT2=1, Timer 2 interrupt is assigned highest priority (priority 3).
PSH, PS: Serial Port (UART) interrupt priority control bits.
if PSH=0 and PS=0, UART interrupt is assigned lowest priority (priority 0).
if PSH=0 and PS=1, UART interrupt is assigned lower priority (priority 1).
if PSH=1 and PS=0, UART interrupt is assigned higher priority (priority 2).
if PSH=1 and PS=1, UART interrupt is assigned highest priority (priority 3).
PT1H, PT1: Timer 1 interrupt priority control bits.
if PT1H=0 and PT1=0, Timer 1 interrupt is assigned lowest priority (priority 0).
if PT1H=0 and PT1=1, Timer 1 interrupt is assigned lower priority (priority 1).
if PT1H=1 and PT1=0, Timer 1 interrupt is assigned higher priority (priority 2).
if PT1H=1 and PT1=1, Timer 1 interrupt is assigned highest priority (priority 3).
STC MCU Limited.
PX1H, PX1: External interrupt 1 priority control bits.
if PX1H=0 and PX1=0, External interrupt 1 is assigned lowest priority (priority 0).
if PX1H=0 and PX1=1, External interrupt 1 is assigned lower priority (priority 1).
if PX1H=1 and PX1=0, External interrupt 1 is assigned higher priority (priority 2).
if PX1H=1 and PX1=1, External interrupt 1 is assigned highest priority (priority 3).
PT0H, PT0: Timer 0 interrupt priority control bits.
if PT0H=0 and PT0=0, Timer 0 interrupt is assigned lowest priority (priority 0).
if PT0H=0 and PT0=1, Timer 0 interrupt is assigned lower priority (priority 1).
if PT0H=1 and PT0=0, Timer 0 interrupt is assigned higher priority (priority 2).
if PT0H=1 and PT0=1, Timer 0 interrupt is assigned highest priority (priority 3).
PX0H, PX0: External interrupt 0 priority control bits.
if PX0H=0 and PX0=0, External interrupt 0 is assigned lowest priority (priority 0).
if PX0H=0 and PX0=1, External interrupt 0 is assigned lower priority (priority 1).
if PX0H=1 and PX0=0, External interrupt 0 is assigned higher priority (priority 2).
if PX0H=1 and PX0=1, External interrupt 0 is assigned highest priority (priority 3).
STC MCU Limited.
3. Timer/Counter Control Registers: TCON and T2CON
TCON: Timer/Counter 0/1 Control register (Bit-Addressable)
SFR name
Address
TCON
88H
bit
B7
name TF1
B6
B5
B4
B3
B2
B1
B0
TR1
TF0
TR0
IE1
IT1
IE0
IT0
TF1: Timer/Counter 1 Overflow Flag. Set by hardware on Timer/Counter 1 overflow. The flag can be cleared by
software but is automatically cleared by hardware when processor vectors to the Timer 1 interrupt routine.
If TF1 = 0, No Timer 1 overflow detected.
If TF1 = 1, Timer 1 has overflowed.
TR1: Timer/Counter 1 Run Control bit. Set/cleared by software to turn Timer/Counter on/off.
If TR1 = 0, Timer 1 disabled.
If TR1 = 1, Timer 1 enabled.
TF0: Timer/Counter 0 Overflow Flag. Set by hardware on Timer/Counter 0 overflow. The flag can be cleared by
software but is automatically cleared by hardware when processor vectors to the Timer 0 interrupt routine.
If TF0 = 0, No Timer 0 overflow detected.
If TF0 = 1, Timer 0 has overflowed.
TR0: Timer/Counter 0 Run Control bit. Set/cleared by software to turn Timer/Counter on/off.
If TR0 = 0, Timer 0 disabled.
If TR0 = 1, Timer 0 enabled.
IE1: External Interrupt 1 Edge flag. Set by hardware when external interrupt edge/level defined by IT1 is
detected. The flag can be cleared by software but is automatically cleared when the external interrupt 1
service routine has been processed.
IT1: External Intenupt 1 Type Select bit. Set/cleared by software to specify falling edge/low level triggered external interrupt 1.
If IT1 = 0, INT1 is low level triggered.
If IT1 = 1, INT1 is edge triggered.
IE0: External Interrupt 0 Edge flag. Set by hardware when external interrupt edge/level defined by IT0 is
detected. The flag can be cleared by software but is automatically cleared when the external interrupt 0
service routine has been processed.
IT0: External Intenupt 0 Type Select bit. Set/cleared by software to specify falling edge/low level triggered external interrupt 0.
If IT0 = 0, INT0 is low level triggered.
If IT0 = 1, INT0 is edge triggered.
STC MCU Limited.
T2CON: Timer/Counter 2 Control register (Bit-Addressable)
SFR name
T2CON
Address bit
B7
C8H name TF2
B6
B5
B4
B3
EXF2 RCLK TCLK EXEN2
B2
TR2
B1
C/T2
B0
CP/RL2
TF2 : Timer 2 overflow flag. TF2 is set by a Timer 2 overflow happens and must be cleared by software. TF2 will
not be set when either RCLK=1 or TCLK=1.
EXF2 : Timer 2 external flag. Timer 2 external flag set when either a capture or reload is caused by a negative
transition on T2EX(P1.1) pin and EXEN2=1. When Timer 2 interrupt is enabled, EXF2=1 will cause the
CPU to vector the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an
interrupt in up/down mode (DCEN=1).
RCLK : Receive clock flag. When set, cause the serial port to use Timer 2 overflow pulses for its receive clock in
modes 1 and 3. When cleared, cause Timer 1 overflow to be used for the receive clock.
TCLK : Transmit clock flag.When set, cause the serial port to use Timer 2 overflow pulses for its transmit clock
in modes 1 and 3. When cleared, cause Timer 1 overflows to be used for the transmit clock.
EXEN2 : Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative
transition on T2EX(P1.1) pin if Timer 2 is not being used to clock the serial port. When cleared, cause
Timer 2 to ignore events at T2EX(P1.1) pin.
TR2 : Timer 2 Run control bit.When set, start the Timer 2. When cleared, stop the Timer 2.
C/T2 : Timer or counter selector.
0: Select Timer 2 as internal timer function.
1: Select Timer 2 as external event counter (falling edge triggered).
CP/RL2: Capture/Reload flag.
0 : Auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX pin when EXEN2=1.
1 : Captures will occur on negative transitions at T2EX pin if EXEN2=1.
STC MCU Limited.
4. SCON register: Serial Port (UART) Control Register (Bit-Addressable)
SFR name
Address
bit
B7
B6
B5
B4
B3
B2
B1
B0
SCON
98H
name
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
FE: Framing Error bit. The SMOD0 bit must be set to enable access to the FE bit
0: The FE bit is not cleared by valid frames but should be cleared by software.
1: This bit set by the receiver when an invalid stop bit id detected.
SM0,SM1 : Serial Port Mode Bit 0/1.
SM0
SM1
Description
0
0
8-bit shift register
0
1
8-bit UART
1
0
9-bit UART
1
1
9-bit UART
Baud rate
SYSclk/12
variable
SYSclk/64 or SYSclk/32(SMOD=1)
variable
SM2 : Enable the automatic address recognition feature in mode 2 and 3. If SM2=1, RI will not be
set unless the received 9th data bit is 1, indicating an address, and the received byte is a
Given or Broadcast address. In mode1, if SM2=1 then RI will not be set unless a valid stop
Bit was received, and the received byte is a Given or Broadcast address. In mode 0, SM2 should be 0.
REN : When set enables serial reception.
TB8 : The 9th data bit which will be transmitted in mode 2 and 3.
RB8 : In mode 2 and 3, the received 9th data bit will go into this bit.
TI : Transmit interrupt flag. Set by hardware when a byte of data has been transmitted by UART0 (after the 8th
bit in 8-bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When the UART0 interrupt is enabled, setting this bit causes the CPU to vector to the UART0 interrupt service routine. This bit
must be cleared manually by software.
RI : Receive interrupt flag. Set to '1' by hardware when a byte of data has been received by UART0 (set at the
STOP bit sam-pling time). When the UART0 interrupt is enabled, setting this bit to '1' causes the CPU to
vector to the UART0 interrupt service routine. This bit must be cleared manually by software.
STC MCU Limited.
6.3 Interrupt Priorities
Each interrupt source can also be individually programmed to one of four priority levels by setting or clearing
the bits in Special Function Registers IP/XICON and IPH. A low-priority interrupt can itself be interrupted by a
high-pority interrupt, but not by another low-priority interrupt. A high-priority interrupt can't be interrupted by
any other interrupt source.
If two requests of different priority levels are received simultaneously, the request of higher priority level
is serviced. If requests of the same priority level are received simultaneously, an internal polling sequence
determines which request is serviced. Thus within each priority level there is a second priority structure
determined by the polling sequence,as follows:
0.
1.
2.
3.
4.
5.
6.
7.
Source
INT0
Timer 0
INT1
Timer 1
UART
Timer 1
INT2
INT3
Priority Within Level
(highest)
(lowest)
Note that the "priority within level" structure is only used to resolve simultaneous requests of the same prionty
level.
In C language program. the interrupt polling sequence number is equal to interrupt number, for example,
void
Int0_Routine(void)
interrupt 0;
void
Timer0_Rountine(void)
interrupt 1;
void
Int1_Routine(void)
interrupt 2;
void
Timer1_Rountine(void)
interrupt 3;
void
UART_Routine(void)
interrupt 4;
void
Timer2_Routine(void)
interrupt 5;
void
Int2_Routine(void)
interrupt 6;
void
Int3_Routine(void)
interrupt 7;
STC MCU Limited.
6.4 How Interrupts Are Handled
External interrupt pins and other interrupt sources are sampled at the rising edge of each instruction OPcode
fetch cycle. The samples are polled during the next instruction OPcode fetch cycle. If one of the flags was in a set
condition of the first cycle, the second cycle of polling cycles will find it and the interrupt system will generate an
hardware LCALL to the appropriate service routine as long as it is not blocked by any of the following conditions.
Block conditions :
o
An interrupt of equal or higher priority level is already in progress.
o
The current cycle(polling cycle) is not the final cycle in the execution of the instruction in progress.
o
The instruction in progress is RETI or any write to the IE, XICON, IP and IPH registers.
o
The ISP/IAP activity is in progress.
Any of these four conditions will block the generation of the hardware LCALL to the interrupt service routine.
Condition 2 ensures that the instruction in progress will be completed before vectoring into any service routine.
Condition 3 ensures that if the instruction in progress is RETI or any access to IE, XICON, IP or IPH, then at least
one or more instruction will be executed before any interrupt is vectored to.
The polling cycle is repeated with the last clock cycle of each instruction cycle. Note that if an interrupt flag is
active but not being responded to for one of the above conditions, if the flag is not still active when the blocking
condition is removed, the denied interrupt will not be serviced. In other words, the fact that the interrupt flag
was once active but not being responded to for one of the above conditions, if the flag is not still active when the
blocking condition is removed, the denied interrupt will not be serviced. The interrupt flag was once active but
not serviced is not kept in memory. Every polling cycle is new.
Note that if an interrupt of higher priority level goes active prior to the rising edge of the third machine cycle,
then in accordance with the above rules it will be vectored to during fifth and sixth machine cycle, without any
instruction of the lower priority routine having been executed.
Thus the processor acknowledges an interrupt request by executing a hardware-generated LCALL to the
appropriate servicing routine. In some cases it also clears the flag that generated the interrupt, and in other cases
it doesn't. It never clears the Serial Port flags. This has to be done in the user's software. It clears an external
interrupt flag (IE0, IE1, IE2 or IE3) only if it was transition-activated. The hardware-generated LCALL pushes
the contents of the Program Counter onto the stack (but it does not save the PSW) and reloads the PC with an
address that depends on the source of the interrupt being vectored to, as shown be low.
STC MCU Limited.
Source
Vector Address
IE0
0003H
TF0
000BH
IE1
0013H
TF1
001BH
RI+TI
0023H
TF2+EXF2
002BH
IE2
0033H
IE3
003BH
Execution proceeds from that location until the RETI instruction is encountered. The RETI instruction informs
the processor that this interrupt routine is no longer in progress, then pops the top two bytes from the stack and
reloads the Program Counter. Execution of the interrupted program continues from where it left off.
Note that a simple RET instruction would also have returned execution to the interrupted program, but it would
have left the interrupt control system thinking an interrupt was still in progress.
6.5 External Interrupts
The external sources can be programmed to be level-activated or transition-activated by clearing or setting bit
IT0/TCON.0 or IT1/TCON.2 or IT2/XICON.0 or IT3/XICON.4. If ITx = 0 (x=0,1,2,3), external interrupt x
is triggered by a detected low at the INTx pin. If ITx=1, external interrupt x is edge-triggered. In this mode if
successive samples of the INTx pin show a high in one cycle and a low in the next cycle, interrupt request flag
IEx in TCON/XICON is set. Flag bit IEx then requests the interrupt.
Since the external interrupt pins are sampled once each machine cycle, an input high or low should hold for at
least 12 system clocks to ensure sampling. If the external interrupt is transition-activated, the external source has
to hold the request pin high for at least one machine cycle, and then hold it low for at least one machine cycle to
ensure that the transition is seen so that interrupt request flag IEx will be set. IEx will be automatically cleared by
the CPU when the service routine is called.
If the external interrupt is level-activated, the external source has to hold the request active until the requested
interrupt is actually generated. Then it has to deactivate the request before the interrupt service routine is
completed, or else another interrupt will be generated.
STC MCU Limited.
Example: Design an intrusion warning system using interrupts that sounds a 400Hz tone for 1 second (using a
loudspeaker connected to P1.7) whenever a door sensor connected to INT0 makes a high-to-low transition.
Assembly Language Solution
ORG
LJMP
LJMP
ORG
LJMP
ORG
LJMP
ORG
0
MAIN
INT0INT
000BH
T0INT
001BH
T1INT
0030H
SETB
MOV
MOV
SJMP
IT0
TMOD, #11H
IE,
#81H
$
;negative edge activated
;16-bit timer mode
;enable EXT 0 only
;now relax
R7,
TF0
TF1
ET0
ET1
;20 ' 5000 us = 1 second
;force timer 0 interrupt
;force timer 1 interrupt
;begin tone for 1 second
;enable timer interrupts
;3-byte instruction
;EXT 0 vector address
;Timer 0 vector
;Timer 1 vector
MAIN:
;
INT0INT:
MOV
SETB
SETB
SETB
SETB
RETI
;
T0INT:
CLR
DJNZ
CLR
CLR
LJMP
SKIP:
MOV
MOV
SETB
EXIT:
RETI
;
T1INT:
CLR
MOV
MOV
CPL
SETB
RETI
END
TR0
R7,
ET0
ET1
EXIT
TH0,
TL0,
TR0
TR1
TH1,
TL1,
P1.7
TR1
#20
SKIP
;stop timer
;if not 20th time, exit
;if 20th, disable tone
;disable itself
#HIGH (-50000)
#LOW (-5000)
;0.05sec. delay
#HIGH (-1250)
#LOW (-1250)
;count for 400Hz
STC MCU Limited.
;music maestro!
C Language Solution
#include & lt; REG51.H & gt;
sbit
outbit = P1^7;
unsigned char
R7;
main( )
{
IT0 = 1;
TMOD = 0x11;
IE = 0x81;
while(1);
}
void INT0INT(void)
{
R7 = 20;
TF0 = 1;
TF1 = 1;
ET0 = 1;
ET1 = 1;
/* SFR declarations */
/* use variable outbit to refer to P1.7 */
/* use 8-bit variable to represent R7 */
/* negative edge activated */
/* 16-bit timer mode */
/* enable EXT 0 only */
interrupt 0
}
void T0INT(void) interrupt 1
{
TR0 = 0;
R7 = R7-1;
if (R7 == 0)
{
ET0 = 0;
ET1 = 0;
}
else
{
TH0 = 0x3C;
TL0 = 0xB0;
}
}
void T1INT (void) interrupt 3
{
TR0 = 0;
TH1 = 0xFB;
TL1 = 0x1E;
outbit = !outbit;
TR1 = 1;
}
STC MCU Limited.
/* 20 x 5000us = 1 second */
/* force timer 0 interrupt */
/* force timer 1 interrupt */
/* begin tone for 1 second */
/* enable timer 1 interrupts */
/* timer interrupts will do the work */
/* stop timer */
/* decrement R7 */
/* if 20th time, */
/* disable itself */
/* 0.05 sec. delay */
/* count for 400Hz */
/* music maestro! */
In the above assembly language solution, five distinct sections are the interrupt vector loactions, the main
program, and the three interrupt service routines. All vector loacations contain LJMP instructions to the respective
routines. The main program, starting at code address 0030H, contains only four instructions. SETB IT0 configures
the door sensing interrupt input as negative-edge triggered. MOV TMOD, #11H configures both timers for mode 1,
16-bit timer mode. Only the external 0 interrupt is enabled initially (MOV IE,#81H), so a " door-open " condition
is needed before any interrupt is accepted. Finally, SJMP $ puts the main program in a do-nothing loop.
When a door-open condition is sensed (by a high-to-low transition of INT0), an external 0 interrupt is
generated, INT0INT begins by putting the constant 20 in R7, then sets the overflow flags for both timers to force
timer interrupts to occur.
Timer interrupt will only occur, however, if the respective bits are enabled in the IE register. The next two
instructions (SETB ET0 and SETB ET1) enable timer interrupts. Finally, INT0INT terminates with a RETI to the
main program.
Timer 0 creates the 1 second timeout, and Timer 1 creates the 400Hz tone. After INT0INT returns to the main
program, timer interrupt are immediately generated (and accepted after one excution of SJMP $). Because of the
fixed polling sequence, the Timer 0 interrupt is serviced first. A 1 second timeout is created by programming 20
repetitions of a 50,000 us timeout. R7 serves as the counter. Nineteen times out of 20, T0INT operates as follows.
First, Timer 0 is turned off and R7 is decremented. Then, TH0/TL is reload with -50,000, the timer is turned back
on, and the interrupt is terminated. On the 20th Timer 0 interrupt, R7 is decremented to 0 (1 second has elapsed).
Both timer interrupts are disabled(CLR ET0, CLR ET1)and the interrupt is terminated. No further timer interrupts
will be generated until the next " door-open " condition is sensed.
The 400Hz tone is programmed using Timer 1 interrupts, 400Hz requires a period of 1/400 = 2,500 us or
1,250 high-time and 1,250 us low-time. Each timer 1 ISR simply puts -1250 in TH1/TL1, complements the port
bit driving the loudspeaker, then terminates.
STC MCU Limited.
6.6 Response Time
The INT0, INT1 , INT2 and INT3 levels are inverted and latched into the interrupt flags IE0, IE1, IE2 and IE3 at
rising edge of every syetem clock cycle.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set after which the timers overflow. The values are then polled
by the circuitry at rising edge of the next system clock cycle.
If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the
requested service routine will be the next instruction to be executed. The call itself takes six system clock cycles.
Thus, a minimum of seven complete system clock cycles elapse between activation of an external interrupt
request and the beginning of execution of the first instruction of the service routine.
A longer response time would result if the request is blocked by one of the four previously listed conditions. If an
interrupt of equal or higher priority level is already in progress, the additional wait time obviously depends on the
nature of the other interrupt's service routine. If the instruction in progress is not in its final cycle, the additional
wait time cannot be more than 3 cycles, since the longest instructions (LCALL) are only 6 cycles long, and if the
instruction in progress is RETI or an access to IE or IP, the additional wait time cannot be more than 5 cycles (a
maximum of one more cycle to complete the instruction in progress, plus 6 cycles to complete the next instruction
if the instruction is LCALL).
Thus, in a single-interrupt system, the response time is always more than 7 cycles and less than 12 cycles.
STC MCU Limited.
6.7 Demo Programs about Interrupts (C and Assembly Programs)
6.7.1 External Interrupt 0 (INT0) Demo Programs (C and ASM)
1. Demostrate External Interrupt 0 triggered by Falling Edge
C program
/*-------------------------------------------------------------------------------*/
/* --- STC MCU International Limited ----------------------------------*/
/* --- STC90xx Series MCU Ext0(Falling edge) Demo -----------------*/
/* If you want to use the program or the program referenced in the */
/* article, please specify in which data and procedures from STC */
/*-------------------------------------------------------------------------------*/
#include " reg51.h "
//External interrupt0 service routine
void exint0() interrupt 0
{
P0++
}
void main()
{
IT0 = 1;
EX0 = 1;
EA = 1;
while (1);
}
STC MCU Limited.
//INT0, interrupt 0 (location at 0003H)
//set INT0 interrupt type (1:Falling 0:Low level)
//enable INT0 interrupt
//open global interrupt switch
Assembly program
;/*-------------------------------------------------------------------------------*/
;/* --- STC MCU International Limited ----------------------------------*/
;/* --- STC90xx Series MCU Ext0(Falling edge) Demo ---------------*/
;/* If you want to use the program or the program referenced in the */
;/* article, please specify in which data and procedures from STC */
;/*-------------------------------------------------------------------------------*/
;----------------------------------------;interrupt vector table
ORG
LJMP
0000H
MAIN
ORG
LJMP
0003H
EXINT0
;INT0, interrupt 0 (location at 0003H)
;----------------------------------------ORG
0100H
MOV
SETB
SETB
SETB
SJMP
SP,
IT0
EX0
EA
$
MAIN:
#7FH
;----------------------------------------;External interrupt0 service routine
EXINT0:
CPL
RETI
P0.0
;----------------------------------------END
STC MCU Limited.
;initial SP
;set INT0 interrupt type (1:Falling 0:Low level)
;enable INT0 interrupt
;open global interrupt switch
2. Demostrate the Power-Down Mode waked up by Falling Edge of External Interrupt 0
C program
/*------------------------------------------------------------------------------------*/
/* --- STC MCU International Limited ---------------------------------------*/
/* --- STC90xx Series MCU Power-Down wakeup by INT0 Demo ------*/
/* If you want to use the program or the program referenced in the ------*/
/* article, please specify in which data and procedures from STC -------*/
/*-------------------------------------------------------------------------------------*/
#include " reg51.h "
#include " intrins.h "
//External interrupt0 service routine
void exint0( )
interrupt 0
{
}
void main()
{
IT0 = 1;
EX0 = 1;
EA = 1;
//INT0, interrupt 0 (location at 0003H)
//set INT0 interrupt type (1:Falling 0:Low level)
//enable INT0 interrupt
//open global interrupt switch
while (1)
{
INT0 = 1;
while (!INT0);
_nop_();
_nop_();
PCON = 0x02;
_nop_();
_nop_();
P1++;
}
}
STC MCU Limited.
//ready read INT0 port
//check INT0
//MCU power down
Assembly program
/*------------------------------------------------------------------------------------*/
/* --- STC MCU International Limited ---------------------------------------*/
/* --- STC90xx Series MCU Power-Down wakeup by INT0 Demo -------*/
/* If you want to use the program or the program referenced in the ------*/
/* article, please specify in which data and procedures from STC -------*/
/*-------------------------------------------------------------------------------------*/
;----------------------------------------;interrupt vector table
ORG
LJMP
0000H
MAIN
ORG
LJMP
0003H
EXINT0
;INT0, interrupt 0 (location at 0003H)
;----------------------------------------ORG
0100H
MOV
SETB
SETB
SETB
SP,
IT0
EX0
EA
SETB
JNB
NOP
NOP
MOV
NOP
NOP
CPL
SJMP
INT0
INT0,
$
;ready read INT0 port
;check INT0
PCON,
#02H
;MCU power down
MAIN:
#7FH
;initial SP
;set INT0 interrupt type (1:Falling 0:Low level)
;enable INT0 interrupt
;open global interrupt switch
LOOP:
P1.0
LOOP
;----------------------------------------;External interrupt0 service routine
EXINT0:
RETI
;----------------------------------------END
STC MCU Limited.
6.7.2 External Interrupt 1 (INT1) Demo Programs (C and ASM)
1. Demostrate External Interrupt 1 triggered by Falling Edge
C program
/*-------------------------------------------------------------------------------*/
/* --- STC MCU International Limited ----------------------------------*/
/* --- STC90xx Series MCU Ext1(Falling edge) Demo ---------------*/
/* If you want to use the program or the program referenced in the */
/* article, please specify in which data and procedures from STC */
/*-------------------------------------------------------------------------------*/
#include " reg51.h "
//External interrupt1 service routine
void exint1() interrupt 2
{
P0++
}
void main()
{
IT1 = 1;
EX1 = 1;
EA = 1;
while (1);
}
STC MCU Limited.
//INT1, interrupt 2 (location at 0013H)
//set INT1 interrupt type (1:Falling only 0:Low level)
//enable INT1 interrupt
//open global interrupt switch
Assembly program
;/*-------------------------------------------------------------------------------*/
;/* --- STC MCU International Limited ----------------------------------*/
;/* --- STC90xx Series MCU Ext1(Falling edge) Demo -----------------*/
;/* If you want to use the program or the program referenced in the */
;/* article, please specify in which data and procedures from STC */
;/*-------------------------------------------------------------------------------*/
;----------------------------------------;interrupt vector table
ORG
LJMP
0000H
MAIN
ORG
LJMP
0013H
EXINT1
;INT1, interrupt 2 (location at 0013H)
;----------------------------------------ORG
0100H
MOV
SETB
SETB
SETB
SJMP
SP,
IT1
EX1
EA
$
MAIN:
#7FH
;----------------------------------------;External interrupt1 service routine
EXINT1:
CPL
RETI
P0.0
;----------------------------------------END
STC MCU Limited.
;initial SP
;set INT1 interrupt type (1:Falling 0:Low level)
;enable INT1 interrupt
;open global interrupt switch
2. Demostrate the Power-Down Mode waked up by Falling Edge of External Interrupt 1
C program
/*------------------------------------------------------------------------------------*/
/* --- STC MCU International Limited ---------------------------------------*/
/* --- STC90xx Series MCU Power-Down wakeup by INT1 Demo -------*/
/* If you want to use the program or the program referenced in the ------*/
/* article, please specify in which data and procedures from STC ------*/
/*-------------------------------------------------------------------------------------*/
#include " reg51.h "
#include " intrins.h "
//External interrupt0 service routine
void exint1( ) interrupt 2
{
}
void main()
{
IT1 = 1;
EX1 = 1;
EA = 1;
//INT1, interrupt 2 (location at 0013H)
//set INT1 interrupt type (1:Falling 0:Low level)
//enable INT1 interrupt
//open global interrupt switch
while (1)
{
INT1 = 1;
while (!INT1);
_nop_();
_nop_();
PCON = 0x02;
_nop_();
_nop_();
P1++;
}
}
STC MCU Limited.
//ready read INT1 port
//check INT1
//MCU power down
Assembly program
/*------------------------------------------------------------------------------------*/
/* --- STC MCU International Limited ---------------------------------------*/
/* --- STC90xx Series MCU Power-Down wakeup by INT1 Demo -------*/
/* If you want to use the program or the program referenced in the ------*/
/* article, please specify in which data and procedures from STC -------*/
/*-------------------------------------------------------------------------------------*/
;----------------------------------------;interrupt vector table
ORG
LJMP
0000H
MAIN
ORG
LJMP
0013H
EXINT1
;INT1, interrupt 2 (location at 0013H)
;----------------------------------------ORG
0100H
MOV
SETB
SETB
SETB
SP,
IT1
EX1
EA
SETB
JNB
NOP
NOP
MOV
NOP
NOP
CPL
SJMP
INT1
INT1,
$
;ready read INT1 port
;check INT1
PCON,
#02H
;MCU power down
MAIN:
#7FH
;initial SP
;set INT1 interrupt type (1:Falling 0:Low level)
;enable INT1 interrupt
;open global interrupt switch
LOOP:
P1.0
LOOP
;----------------------------------------;External interrupt1 service routine
EXINT1:
RETI
;----------------------------------------END
STC MCU Limited.
6.7.2 External Interrupt 2 (INT2) Demo Programs (C and ASM)
1. Demostrate External Interrupt 2 triggered by Falling Edge
C program
/*-------------------------------------------------------------------------------*/
/* --- STC MCU International Limited ----------------------------------*/
/* --- STC90xx Series MCU Ext2(Falling edge) Demo ---------------*/
/* If you want to use the program or the program referenced in the */
/* article, please specify in which data and procedures from STC */
/*-------------------------------------------------------------------------------*/
#include " reg51.h "
sfr P4 = 0xe8;
sbit INT2 = P4^3;
sbit INT3 = P4^2;
//for 90C58AD series, location at 0C0H
sfr XICON = 0xc0;
sbit PX3 = XICON^7;
sbit EX3 = XICON^6;
sbit IE3 = XICON^5;
sbit IT3 = XICON^4;
sbit PX2 = XICON^3;
sbit EX2 = XICON^2;
sbit IE2 = XICON^1;
sbit IT2 = XICON^0;
//for 90C58AD series, location at 0E8H
//External interrupt2 service routine
void exint2() interrupt 6
//INT2, interrupt 6 (location at 0033H)
{
P0++;
}
void main()
{
IT2 = 1;
EX2 = 1;
EA = 1;
//set INT2 interrupt type (1:Falling only 0:Low level)
//enable INT2 interrupt
//open global interrupt switch
while (1);
}
STC MCU Limited.
Assembly program
;/*-------------------------------------------------------------------------------*/
;/* --- STC MCU International Limited ----------------------------------*/
;/* --- STC90xx Series MCU Ext2(Falling edge) Demo -----------------*/
;/* If you want to use the program or the program referenced in the */
;/* article, please specify in which data and procedures from STC */
;/*-------------------------------------------------------------------------------*/
P4
EQU
0E8H
;for 90C58AD series, location at 0C0H
INT2
BIT
P4.3
INT3
BIT
P4.2
XICON EQU
0C0H
PX3
BIT
XICON.7
EX3
BIT
XICON.6
IE3
BIT
XICON.5
IT3
BIT
XICON.4
PX2
BIT
XICON.3
EX2
BIT
XICON.2
IE2
BIT
XICON.1
IT2
BIT
XICON.0
;----------------------------------------;interrupt vector table
ORG
LJMP
0000H
MAIN
ORG
0033H
LJMP
EXINT2
;----------------------------------------ORG
0100H
MAIN:
MOV
SP,
#7FH
SETB
IT2
SETB
EX2
SETB
EA
SJMP
$
;----------------------------------------;External interrupt2 service routine
EXINT2:
CPL
P0.0
RETI
;----------------------------------------END
STC MCU Limited.
;for 90C58AD series, location at 0E8H
;INT2, interrupt 6 (location at 0033H)
;initial SP
;set INT2 interrupt type (1:Falling 0:Low level)
;enable INT2 interrupt
;open global interrupt switch
2. Demostrate the Power-Down Mode waked up by Falling Edge of External Interrupt 2
C program
/*------------------------------------------------------------------------------------*/
/* --- STC MCU International Limited ---------------------------------------*/
/* --- STC90xx Series MCU Power-Down wakeup by INT2 Demo ------*/
/* If you want to use the program or the program referenced in the ------*/
/* article, please specify in which data and procedures from STC ------*/
/*-------------------------------------------------------------------------------------*/
#include " reg51.h "
#include " intrins.h "
sfr P4 = 0xe8;
sbit INT2 = P4^3;
sbit INT3 = P4^2;
//for 90C58AD series, location at 0C0H
sfr XICON
sbit PX3
sbit EX3
sbit IE3
sbit IT3
sbit PX2
sbit EX2
sbit IE2
sbit IT2
= 0xc0;
= XICON^7;
= XICON^6;
= XICON^5;
= XICON^4;
= XICON^3;
= XICON^2;
= XICON^1;
= XICON^0;
//External interrupt2 service routine
void exint2() interrupt 6
{
}
void main()
{
IT2 = 1;
EX2 = 1;
EA = 1;
STC MCU Limited.
//for 90C58AD series, location at 0E8H
//INT2, interrupt 6 (location at 0033H)
//set INT2 interrupt type (1:Falling 0:Low level)
//enable INT2 interrupt
//open global interrupt switch
while (1)
{
INT2 = 1;
while (!INT2);
_nop_();
_nop_();
PCON = 0x02;
_nop_();
_nop_();
P1++;
//ready read INT2 port
//check INT2
//MCU power down
}
}
Assembly program
/*------------------------------------------------------------------------------------*/
/* --- STC MCU International Limited ---------------------------------------*/
/* --- STC90xx Series MCU Power-Down wakeup by INT2 Demo -------*/
/* If you want to use the program or the program referenced in the ------*/
/* article, please specify in which data and procedures from STC -------*/
/*-------------------------------------------------------------------------------------*/
P4
INT2
INT3
EQU
BIT
BIT
0E8H
P4.3
P4.2
;for 90C58AD series, location at 0C0H
XICON
PX3
EX3
IE3
IT3
PX2
EX2
IE2
IT2
EQU
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
0C0H
XICON.7
XICON.6
XICON.5
XICON.4
XICON.3
XICON.2
XICON.1
XICON.0
;for 90C58AD series, location at 0E8H
;----------------------------------------;interrupt vector table
ORG
LJMP
STC MCU Limited.
0000H
MAIN
ORG
0033H
LJMP
EXINT2
;----------------------------------------ORG
0100H
MOV
SETB
SETB
SETB
SP,
IT2
EX2
EA
;INT2, interrupt 6 (location at 0033H)
MAIN:
#7FH
;initial SP
;set INT2 interrupt type (1:Falling 0:Low level)
;enable INT2 interrupt
;open global interrupt switch
LOOP:
SETB
JNB
NOP
NOP
MOV
NOP
NOP
CPL
SJMP
INT2
INT2,
$
;ready read INT2 port
;check INT2
PCON,
#02H
;MCU power down
P1.0
LOOP
;----------------------------------------;External interrupt2 service routine
EXINT2:
RETI
;----------------------------------------END
STC MCU Limited.
6.7.2 External Interrupt 3 (INT3) Demo Programs (C and ASM)
1. Demostrate External Interrupt 3 triggered by Falling Edge
C program
/*-------------------------------------------------------------------------------*/
/* --- STC MCU International Limited ----------------------------------*/
/* --- STC90xx Series MCU Ext3(Falling edge) Demo ---------------*/
/* If you want to use the program or the program referenced in the */
/* article, please specify in which data and procedures from STC */
/*-------------------------------------------------------------------------------*/
#include " reg51.h "
sfr P4
= 0xe8;
sbit INT2 = P4^3;
sbit INT3 = P4^2;
//for 90C58AD series, location at 0C0H
sfr XICON = 0xc0;
sbit PX3 = XICON^7;
sbit EX3 = XICON^6;
sbit IE3 = XICON^5;
sbit IT3 = XICON^4;
sbit PX2 = XICON^3;
sbit EX2 = XICON^2;
sbit IE2 = XICON^1;
sbit IT2 = XICON^0;
//for 90C58AD series, location at 0E8H
//External interrupt3 service routine
void exint3() interrupt 7
//INT3, interrupt 7 (location at 003BH)
{
P0++;
}
void main()
{
IT3
= 1;
EX3 = 1;
EA
= 1;
while (1);
}
STC MCU Limited.
//set INT3 interrupt type (1:Falling only 0:Low level)
//enable INT3 interrupt
//open global interrupt switch
Assembly program
;/*-------------------------------------------------------------------------------*/
;/* --- STC MCU International Limited ----------------------------------*/
;/* --- STC90xx Series MCU Ext3(Falling edge) Demo -----------------*/
;/* If you want to use the program or the program referenced in the */
;/* article, please specify in which data and procedures from STC */
;/*-------------------------------------------------------------------------------*/
P4
EQU
0E8H
;for 90C58AD series, location at 0C0H
INT2
BIT
P4.3
INT3
BIT
P4.2
XICON EQU
0C0H
;for 90C58AD series, location at 0E8H
PX3
BIT
XICON.7
EX3
BIT
XICON.6
IE3
BIT
XICON.5
IT3
BIT
XICON.4
PX2
BIT
XICON.3
EX2
BIT
XICON.2
IE2
BIT
XICON.1
IT2
BIT
XICON.0
;----------------------------------------;interrupt vector table
ORG 0000H
LJMP MAIN
ORG 003BH
LJMP EXINT3
;INT3, interrupt 7 (location at 003BH)
;----------------------------------------ORG
0100H
MAIN:
MOV
SP,#7FH
SETB
IT3
SETB
EX3
SETB
EA
SJMP
$
;----------------------------------------;External interrupt3 service routine
EXINT3:
CPL
P0.0
RETI
;----------------------------------------END
STC MCU Limited.
;initial SP
;set INT3 interrupt type (1:Falling 0:Low level)
;enable INT3 interrupt
;open global interrupt switch
2. Demostrate the Power-Down Mode waked up by Falling Edge of External Interrupt 3
C program
/*------------------------------------------------------------------------------------*/
/* --- STC MCU International Limited ---------------------------------------*/
/* --- STC90xx Series MCU Power-Down wakeup by INT3 Demo ------*/
/* If you want to use the program or the program referenced in the ------*/
/* article, please specify in which data and procedures from STC ------*/
/*-------------------------------------------------------------------------------------*/
#include " reg51.h "
#include " intrins.h "
sfr P4 = 0xe8;
sbit INT2 = P4^3;
sbit INT3 = P4^2;
sfr XICON = 0xc0;
sbit PX3
= XICON^7;
sbit EX3
= XICON^6;
sbit IE3
= XICON^5;
sbit IT3
= XICON^4;
sbit PX2
= XICON^3;
sbit EX2
= XICON^2;
sbit IE2
= XICON^1;
sbit IT2
= XICON^0;
//for 90C58AD series, location at 0C0H
//for 90C58AD series, location at 0E8H
//External interrupt3 service routine
void exint3() interrupt 7
//INT3, interrupt 7 (location at 003BH)
{
}
void main()
{
IT3 = 1;
EX3 = 1;
EA = 1;
STC MCU Limited.
//set INT3 interrupt type (1:Falling 0:Low level)
//enable INT3 interrupt
//open global interrupt switch
while (1)
{
INT3 = 1;
//ready read INT3 port
while (!INT3);
_nop_();
_nop_();
PCON = 0x02;
_nop_();
_nop_();
P1++;
//check INT3
//MCU power down
}
}
Assembly program
/*------------------------------------------------------------------------------------*/
/* --- STC MCU International Limited ---------------------------------------*/
/* --- STC90xx Series MCU Power-Down wakeup by INT3 Demo -------*/
/* If you want to use the program or the program referenced in the ------*/
/* article, please specify in which data and procedures from STC -------*/
/*-------------------------------------------------------------------------------------*/
P4
INT2
INT3
EQU
BIT
BIT
0E8H
P4.3
P4.2
;for 90C58AD series, location at 0C0H
XICON
PX3
EX3
IE3
IT3
PX2
EX2
IE2
IT2
EQU
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
0C0H
XICON.7
XICON.6
XICON.5
XICON.4
XICON.3
XICON.2
XICON.1
XICON.0
;for 90C58AD series, location at 0E8H
;----------------------------------------;interrupt vector table
ORG
LJMP
0000H
MAIN
STC MCU Limited.
ORG
LJMP
003BH
EXINT3
;INT3, interrupt 7 (location at 003BH)
;----------------------------------------ORG
0100H
MOV
SETB
SETB
SETB
SP,
IT3
EX3
EA
SETB
JNB
NOP
NOP
MOV
NOP
NOP
CPL
SJMP
INT3
INT3,
MAIN:
#7FH
;initial SP
;set INT3 interrupt type (1:Falling 0:Low level)
;enable INT3 interrupt
;open global interrupt switch
LOOP:
$
PCON,#02H
P1.0
LOOP
;----------------------------------------;External interrupt3 service routine
EXINT3:
RETI
;----------------------------------------END
STC MCU Limited.
;ready read INT3 port
;check INT3
;MCU power down
Chapter 7. Timer/Counter
There are threee Timers / Counters built in STC90C51RC/RD+ series. They are Timer/Counter 0, Timer/Counter
1 and Timer/Counter 2.
7.1 Timer/Counter 0/1
Timer 0 and timer 1 are like the ones in the conventional 8051, both of them can be individually configured as
timers or event counters.
In the "Timer" function, the register is incremented every 12 system clocks or every 6 system clock depending on
the setting in STC-ISP Writer/Programmer. See the follwing figure. In the default state, it is fully the same as the
conventional 8051. In the 6T mode, the count rate equals to the 6 system clock.
In the "Counter" function, the register is incremented in response to a 1-to-0 transition at its corresponding
external input pin, T0 or T1. In this function, the external input is sampled once at the positive edge of every clock
cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new
count value appears in the register during at the end of the cycle following the one in which the transition was
detected. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is
sampled at least once before it changes, it should be held for at least one full machine cycle.
In addition to the "Timer" or "Counter" selection, Timer 0 and Timer 1 have four operating modes from which
to select. The "Timer" or "Counter" function is selected by control bits C/T in the Special Function Register
TMOD. These two Timer/Counter have four operating modes, which are selected by bit-pairs (M1, M0) in
TMOD. Modes 0, 1, and 2 are the same for both Timer/Counters. Mode 3 is different.The four operating modes
are described in the following text.
STC MCU Limited.
7.1.1 Special Function Registers about Timer/Counter 0/1
Bit Address and Symbol
Symbol
Description
Address
TCON
Timer Control
88H
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
TMOD
TL0
TL1
TH0
TH1
Timer Mode
Timer Low 0
Timer Low 1
Timer High 0
Timer High 1
89H
8AH
8BH
8CH
8DH
GATE
C/T
M1
M0
GATE
C/T
M1
M0
MSB
LSB
Value after
Power-on or
Reset
0000 0000B
0000 0000B
0000 0000B
0000 0000B
0000 0000B
0000 0000B
1. TCON register: Timer/Counter Control Register (Bit-Addressable)
SFR name
Address
TCON
88H
bit
B7
name TF1
B6
B5
B4
B3
B2
B1
B0
TR1
TF0
TR0
IE1
IT1
IE0
IT0
TF1: Timer/Counter 1 Overflow Flag. Set by hardware on Timer/Counter 1 overflow. The flag can be cleared by
software but is automatically cleared by hardware when processor vectors to the Timer 1 interrupt routine.
If TF1 = 0, No Timer 1 overflow detected.
If TF1 = 1, Timer 1 has overflowed.
TR1: Timer/Counter 1 Run Control bit. Set/cleared by software to turn Timer/Counter on/off.
If TR1 = 0, Timer 1 disabled.
If TR1 = 1, Timer 1 enabled.
TF0: Timer/Counter 0 Overflow Flag. Set by hardware on Timer/Counter 0 overflow. The flag can be cleared by
software but is automatically cleared by hardware when processor vectors to the Timer 0 interrupt routine.
If TF0 = 0, No Timer 0 overflow detected.
If TF0 = 1, Timer 0 has overflowed.
TR0: Timer/Counter 0 Run Control bit. Set/cleared by software to turn Timer/Counter on/off.
If TR0 = 0, Timer 0 disabled.
If TR0 = 1, Timer 0 enabled.
IE1: External Interrupt 1 Edge flag. Set by hardware when external interrupt edge/level defined by IT1 is
detected. The flag can be cleared by software but is automatically cleared when the external interrupt 1
service routine has been processed.
IT1: External Intenupt 1 Type Select bit. Set/cleared by software to specify falling edge/low level triggered external interrupt 1.
If IT1 = 0, INT1 is low level triggered.
If IT1 = 1, INT1 is edge triggered.
IE0: External Interrupt 0 Edge flag. Set by hardware when external interrupt edge/level defined by IT0 is
detected. The flag can be cleared by software but is automatically cleared when the external interrupt 0
service routine has been processed.
IT0: External Intenupt 0 Type Select bit. Set/cleared by software to specify falling edge/low level triggered external interrupt 0.
If IT0 = 0, INT0 is low level triggered.
If IT0 = 1, INT0 is edge triggered.
STC MCU Limited.
2. TMOD register: Timer/Counter Mode Register
TMOD
address: 89H (Non bit-addressable)
(MSB)
GATE
C/T
M1
M0
GATE
C/T
M1
(LSB)
M0
}
}
Timer 0
Timer 1
GATR/TMOD.7: Timer/Counter Gate Control.
If GATE/TMOD.7=0,Timer/Counter 1 enabled when TR1 is set irrespective of INT1 logic level;
If GATE/TMOD.7=1, Timer/Counter 1 enabled only when TR1 is set AND INT1 pin is high.
C/T /TMOD.6: Timer/Counter 1 Select bit.
If C/T /TMOD.6=0,Timer/Counter 1 is set for Timer operation (input from internal system clock);
If C/T /TMOD.6=0,Timer/Counter 1 is set for Counter operation (input from external T1 pin).
M1/TMOD.5 ~ M0/TMOD.4: Timer 1 Mode Select bits.
M1
M0
Operating Mode
0
0
Mode 0: 13-bit Timer/Counter for Timer 1
0
1
Mode 1: 16-bit Timer/Counter. TH1and TL1 are cascaded; there is no prescaler.
Mode 2: 8-bit auto-reload Timer/Counter. TH1 holds a value which is to be reloaded into TL1
1
0
each time it overflows.
1
1
Timer/Counter 1 stopped
GATR/TMOD.3: Timer/Counter Gate Control.
If GATE/TMOD.3=0,Timer/Counter 0 enabled when TR0 is set irrespective of INT0 logic level;
If GATE/TMOD.3=1, Timer/Counter 0 enabled only when TR0 is set AND INT0 pin is high.
C/T /TMOD.2: Timer/Counter 0 Select bit.
If C/T /TMOD.2=0,Timer/Counter 0 is set for Timer operation (input from internal system clock);
If C/T /TMOD.2=0,Timer/Counter 0 is set for Counter operation (input from external T0 pin).
M1/TMOD.1 ~ M0/TMOD.0: Timer 0 Mode Select bits.
M1
M0
Operating Mode
0
0
Mode 0: 13-bit Timer/Counter for Timer 0
0
1
Mode 1: 16-bit Timer/Counter. TH0 and TL0 are cascaded; there is no prescaler.
Mode 2: 8-bit auto-reload Timer/Counter. TH0 holds a value which is to be reloaded
1
0
into TL0 each time it overflows.
Mode3: TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits
1
1
TH0 is an 8-bit timer only controlled by Timer 1 control bits.
STC MCU Limited.
7.1.2 Timer/Counter 0 Operational Mode (Compatible with traditional 8051 MCU)
Timer/Counter 0 can be configured for four modes by setting M1(TMOD.1) and M0(TMOD.0) in sepcial function
register TMOD.
7.1.2.1 Mode 0 (13-bit Timer/Counter)
Mode 0
In this mode, the timer 0 is configured as a 13-bit timer/counter. As the count rolls over from all 1s to all 0s, it sets
the timer interrupt flag TF0. The counted input is enabled to the timer when TR0 = 1 and either GATE=0 or INT0
= 1.(Setting GATE = 1 allows the Timer to be controlled by external input INT0 , to facilitate pulse width measurements.) TR0 is a control bit in the Special Function Register TCON. GATE is in TMOD.
The 13-Bit register consists of all 8 bits of TH0 and the lower 5 bits of TL0. The upper 3 bits of TL0 are
indeterminate and should be ignored. Setting the run flag (TR0) does not clear the registers.
There are two different GATE bits. one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).
MCU in 12T mode
÷12
SYSclk
÷6
MCU in 6T mode
C/T=0
TL0
(5 bits)
C/T=1
T0 Pin
TR0
TH0
(8 bits)
control
GATE
INT0
Timer/Counter 0 Mode 0: 13-Bit Timer/Counter
STC MCU Limited.
TF0
Interrupt
7.1.2.2 Mode 1 (16-bit Timer/Counter) and Demo Programs (C and ASM)
In this mode, the timer register is configured as a 16-bit register. As the count rolls over from all 1s to all 0s, it
sets the timer interrupt flag TF0. The counted input is enabled to the timer when TR0 = 1 and either GATE=0 or
INT0 = 1.(Setting GATE = 1 allows the Timer to be controlled by external input INT0 , to facilitate pulse width
measurements.) TR0 is a control bit in the Special Function Register TCON. GATE is in TMOD.
The 16-Bit register consists of all 8 bits of TH0 and the lower 8 bits of TL0. Setting the run flag (TR0) does not
clear the registers.
Mode 1 is the same as Mode 0, except that the timer register is being run with all 16 bits.
MCU in 12T mode
÷12
SYSclk
÷6
MCU in 6T mode
C/T=0
C/T=1
T0 Pin
TR0
TL0
TH0
(8 Bits) (8 bits)
TF0
Interrupt
control
GATE
INT0
Timer/Counter 0 Mode 1 : 16-Bit Timer/Counter
There are two simple programs that demostrates Timer 0 as 16-bit Timer/Counter, one written in C language
while other in Assembly language.
C Program:
/*-------------------------------------------------------------------------------*/
/* --- STC MCU International Limited ----------------------------------*/
/* --- STC90xx Series 16-bit Timer Demo ------------------------------*/
/* If you want to use the program or the program referenced in the */
/* article, please specify in which data and procedures from STC */
/*-------------------------------------------------------------------------------*/
#include " reg51.h "
typedef unsigned char BYTE;
typedef unsigned int WORD;
//----------------------------------------------/* define constants */
#define FOSC 18432000L
STC MCU Limited.
#define
T1MS
(65536-FOSC/12/1000)
//1ms timer calculation method in 12T mode
/* define SFR */
sbit TEST_LED = P1^0;
//work LED, flash once per second
/* define variables */
WORD count;
//1000 times counter
//----------------------------------------------/* Timer0 interrupt routine */
void tm0_isr() interrupt 1 using 1
{
TL0 = T1MS;
TH0 = T1MS & gt; & gt; 8;
if (count-- == 0)
{
count = 1000;
TEST_LED = ! TEST_LED;
}
}
//----------------------------------------------/* main program */
void main()
{
TMOD = 0x01;
TL0 = T1MS;
TH0 = T1MS & gt; & gt; 8;
TR0 = 1;
ET0 = 1;
EA = 1;
count = 0;
while (1);
}
STC MCU Limited.
//reload timer0 low byte
//reload timer0 high byte
//1ms * 1000 - & gt; 1s
//reset counter
//work LED flash
//set timer0 as mode1 (16-bit)
//initial timer0 low byte
//initial timer0 high byte
//timer0 start running
//enable timer0 interrupt
//open global interrupt switch
//initial counter
//loop
Assembly Program:
;/*-------------------------------------------------------------------------------*/
;/* --- STC MCU International Limited ----------------------------------*/
;/* --- STC90xx Series 16-bit Timer Demo ------------------------------*/
;/* If you want to use the program or the program referenced in the */
;/* article, please specify in which data and procedures from STC */
;/*------------------------------------------------------------------------------*/
;/* define constants */
T1MS
EQU 0FA00H
;1ms timer calculation method in 12T mode is (65536-18432000/12/1000)
;/* define SFR */
TEST_LED BIT P1.0
;work LED, flash once per second
;/* define variables */
COUNT DATA 20H
;1000 times counter (2 bytes)
;----------------------------------------------ORG
LJMP
ORG
LJMP
0000H
MAIN
000BH
TM0_ISR
;----------------------------------------------;/* main program */
MAIN:
MOV
TMOD,#01H
MOV
TL0,#LOW T1MS
MOV
TH0,#HIGH T1MS
SETB
TR0
SETB
ET0
SETB
EA
CLR
A
MOV
COUNT,A
MOV
COUNT+1,A
SJMP
$
STC MCU Limited.
;set timer0 as mode1 (16-bit)
;initial timer0 low byte
;initial timer0 high byte
;timer0 start running
;enable timer0 interrupt
;open global interrupt switch
;initial counter
;----------------------------------------------;/* Timer0 interrupt routine */
TM0_ISR:
PUSH ACC
PUSH PSW
MOV
TL0,
#LOW T1MS
MOV
TH0,
#HIGH T1MS
MOV
A,
COUNT
ORL
A,
COUNT+1
JNZ
SKIP
MOV
COUNT, #LOW 1000
MOV
COUNT+1,
#HIGH 1000
CPL
TEST_LED
SKIP:
CLR
C
MOV
A,
COUNT
SUBB A,
#1
MOV
COUNT, A
MOV
A,
COUNT+1
SUBB A,
#0
MOV
COUNT+1,A
POP
PSW
POP
ACC
RETI
;----------------------------------------------END
STC MCU Limited.
;reload timer0 low byte
;reload timer0 high byte
;check whether count(2byte) is equal to 0
;1ms * 1000 - & gt; 1s
;work LED flash
;count--
7.1.2.3 Mode 2 (8-bit Auto-Reload Mode) and Demo Programs (C and Assembly Program)
Mode 2 configures the timer register as an 8-bit counter(TL0) with automatic reload. Overflow from TL0 not
only set TF0, but also reload TL0 with the content of TH0, which is preset by software. The reload leaves TH0
unchanged.
MCU in 12T mode
÷12
SYSclk
÷6
MCU in 6T mode
C/T=0
TL0
(8 Bits)
C/T=1
T0 Pin
TR0
TF0
Interrupt
control
GATE
TH0
(8 Bits)
INT0
Timer/Counter 0 Mode 2: 8-Bit Auto-Reload
;T0 Interrupt (falling edge) Demo programs, where T0 operated in Mode 2 (8-bit auto-relaod mode)
; The Timer Interrupt can not wake up MCU from Power-Down mode in the following programs
1. C program
/*----------------------------------------------------------------------------------*/
/* --- STC MCU International Limited -------------------------------------*/
/* --- STC90xx Series MCU T0 (Falling edge) Demo -------------------*/
/* If you want to use the program or the program referenced in the --*/
/* article, please specify in which data and procedures from STC ---*/
/*---------------------------------------------------------------------------------*/
#include " reg51.h "
//T0 interrupt service routine
void t0int() interrupt 1
//T0 interrupt (location at 000BH)
{
P0++;
}
void main()
{
TMOD = 0x06;
TL0 = TH0 = 0xff;
TR0 = 1;
ET0 = 1;
EA = 1;
while (1);
}
STC MCU Limited.
//set timer0 as counter mode2 (8-bit auto-reload)
//fill with 0xff to count one time
//timer0 start run
//enable T0 interrupt
//open global interrupt switch
2. Assembly program
;/*----------------------------------------------------------------------------------*/
;/* --- STC MCU International Limited -------------------------------------*/
;/* --- STC89-90xx Series MCU T0(Falling edge) Demo -----------------*/
;/* If you want to use the program or the program referenced in the ---*/
;/* article, please specify in which data and procedures from STC ----*/
;/*----------------------------------------------------------------------------------*/
;----------------------------------------;interrupt vector table
ORG 0000H
LJMP MAIN
ORG 000BH
LJMP T0INT
;T0 interrupt (location at 000BH)
;----------------------------------------ORG
0100H
MAIN:
MOV
MOV
MOV
MOV
MOV
SETB
SETB
SETB
SJMP
SP,
TMOD,
A,
TL0,
TH0,
TR0
ET0
EA
$
#7FH
#06H
#0FFH
A
A
;----------------------------------------;T0 interrupt service routine
T0INT:
CPL
RETI
P0.0
;----------------------------------------END
STC MCU Limited.
;initial SP
;set timer0 as counter mode2 (8-bit auto-reload)
;fill with 0xff to count one time
;timer0 start run
;enable T0 interrupt
;open global interrupt switch
7.1.2.4 Mode 3 (Two 8-bit Timers/Couters)
Timer 1 in Mode 3 simply holds its count, the effect is the same as setting TR1 = 0. Timer 0 in Mode 3 established
TL0 and TH0 as two separate 8-bit counters. TL0 use the Timer 0 control bits: C/T,GATE,TR0, INT0 and TF0.
TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 from Tmer 1. Thus,
TH0 now controls the "Timer 1" interrupt.
Mode 3 is provided for applications requiring an extra 8-bit timer or counter. When Timer 0 is in Mode 3, Timer 1
can be turned on and off by switching it out of and into its own Mode 3, or can still be used by the serial port as a
baud rate generator, or in fact, in any application not requiring an interrupt.
MCU in 12T mode
÷12
SYSclk
÷6
MCU in 6T mode
C/T=0
TL0
(8 bit)
C/T=1
T0 Pin
TR0
TF0
Interrupt
control
GATE
INT0
÷12
MCU in 12T mode
SYSclk
÷6
TH0
(8 Bits)
MCU in 6T mode
TR1
TF1
control
Timer/Counter 0 Mode 3: Two 8-Bit Timers/Counters
STC MCU Limited.
Interrupt
7.1.3 Timer/Counter 1 Operational Mode
Timer/Counter 1 can be configured for three modes by setting M1(TMOD.5) and M0(TMOD.4) in sepcial
function register TMOD.
7.1.3.1 Mode 0 (13-bit Timer/Counter)
In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it
sets the timer interrupt flag TF1. The counted input is enabled to the timer when TR1 = 1 and either GATE=0 or
INT1= 1.(Setting GATE = 1 allows the Timer to be controlled by external input INT1, to facilitate pulse width
measurements.) TR0 is a control bit in the Special Function Register TCON. GATE is in TMOD.
The 13-Bit register consists of all 8 bits of TH1 and the lower 5 bits of TL1. The upper 3 bits of TL1 are
indeterminate and should be ignored. Setting the run flag (TR1) does not clear the registers.
MCU in 12T mode
÷12
SYSclk
÷6
MCU in 6T mode
C/T=0
TH1
(8 bits)
C/T=1
T1 Pin
TR1
TL1
(8 bits)
control
GATE
INT1
Timer/Counter 1 Mode 0: 13-Bit Timer/Counter
STC MCU Limited.
TF1
Interrupt
7.1.3.2 Mode 1 (16-bit Timer/Counter) and Demo Programs (C and ASM)
In this mode, the timer register is configured as a 16-bit register. As the count rolls over from all 1s to all 0s, it
sets the timer interrupt flag TF1. The counted input is enabled to the timer when TR1 = 1 and either GATE=0 or
INT1 = 1.(Setting GATE = 1 allows the Timer to be controlled by external input INT1, to facilitate pulse width
measurements.) TRl is a control bit in the Special Function Register TCON. GATE is in TMOD.
The 16-Bit register consists of all 8 bits of THl and the lower 8 bits of TL1. Setting the run flag (TR1) does not
clear the registers.
Mode 1 is the same as Mode 0, except that the timer register is being run with all 16 bits.
÷12
MCU in 12T mode
SYSclk
÷6
MCU in 6T mode
C/T=0
C/T=1
T1 Pin
TR1
TL1
TH1
(8 Bits) (8 bits)
TF1
Interrupt
control
GATE
INT1
Timer/Counter 1 Mode 1 : 16-Bit Timer/Counter
There are another two simple programs that demostrates Timer 1 as 16-bit Timer/Counter, one written in C
language while other in Assembly language.
1. C Program
/*-------------------------------------------------------------------------------*/
/* --- STC MCU International Limited ----------------------------------*/
/* --- STC90xx Series 16-bit Timer Demo --------------------------------*/
/* If you want to use the program or the program referenced in the */
/* article, please specify in which data and procedures from STC */
/*-------------------------------------------------------------------------------*/
#include " reg51.h "
typedef
typedef
unsigned char
unsigned int
BYTE;
WORD;
//----------------------------------------------/* define constants */
#define FOSC 18432000L
STC MCU Limited.
#define
T1MS (65536-FOSC/12/1000)
//1ms timer calculation method in 12T mode
/* define SFR */
sbit
TEST_LED = P1^0;
//work LED, flash once per second
/* define variables */
WORD count;
//1000 times counter
//----------------------------------------------/* Timer0 interrupt routine */
void tm1_isr() interrupt 3 using 1
{
TL1 = T1MS;
TH1 = T1MS & gt; & gt; 8;
if (count-- == 0)
{
count = 1000;
TEST_LED = ! TEST_LED;
}
}
//----------------------------------------------/* main program */
void main()
{
TMOD = 0x10;
TL1 = T1MS;
TH1 = T1MS & gt; & gt; 8;
TR1 = 1;
ET1 = 1;
EA = 1;
count = 0;
while (1);
}
STC MCU Limited.
//reload timer1 low byte
//reload timer1 high byte
//1ms * 1000 - & gt; 1s
//reset counter
//work LED flash
//set timer1 as mode1 (16-bit)
//initial timer1 low byte
//initial timer1 high byte
//timer1 start running
//enable timer1 interrupt
//open global interrupt switch
//initial counter
//loop
2. Assembly Program
;/*---------------------------------------------------------------------------------*/
;/* --- STC MCU International Limited ------------------------------------*/
;/* --- STC90xx Series 16-bit Timer Demo ----------------------------------*/
;/* If you want to use the program or the program referenced in the */
;/* article, please specify in which data and procedures from STC */
;/*------------------------------------------------------------------------------*/
;/* define constants */
T1MS
EQU 0FA00H
;1ms timer calculation method in 12T mode is (65536-18432000/12/1000)
;/* define SFR */
TEST_LED BIT P1.0
;work LED, flash once per second
;/* define variables */
COUNT DATA 20H
;1000 times counter (2 bytes)
;----------------------------------------------ORG
0000H
LJMP
MAIN
ORG
001BH
LJMP
TM1_ISR
;----------------------------------------------;/* main program */
MAIN:
MOV
TMOD, #10H
MOV
TL1,
#LOW T1MS
MOV
TH1
,#HIGH T1MS
SETB
TR1
SETB
ET1
SETB
EA
CLR
A
MOV
COUNT, A
MOV
COUNT+1,
A
SJMP
$
STC MCU Limited.
;set timer1 as mode1 (16-bit)
;initial timer1 low byte
;initial timer1 high byte
;timer1 start running
;enable timer1 interrupt
;open global interrupt switch
;initial counter
;----------------------------------------------;/* Timer1 interrupt routine */
TM1_ISR:
PUSH ACC
PUSH PSW
MOV
TL1,
#LOW T1MS
MOV
TH1,
#HIGH T1MS
MOV
A,
COUNT
ORL
A,
COUNT+1
JNZ
SKIP
MOV
COUNT, #LOW 1000
MOV
COUNT+1,#HIGH 1000
CPL
TEST_LED
SKIP:
CLR
C
MOV
A,
COUNT
SUBB A,
#1
MOV
COUNT,A
MOV
A,COUNT+1
SUBB A,#0
MOV
COUNT+1,A
POP
PSW
POP
ACC
RETI
;----------------------------------------------END
STC MCU Limited.
;reload timer1 low byte
;reload timer1 high byte
;check whether count(2byte) is equal to 0
;1ms * 1000 - & gt; 1s
;work LED flash
;count--
7.1.3.3 Mode 2 (8-bit Auto-Reload Mode) and Demo Programs (C and ASM)
Mode 2 configures the timer register as an 8-bit counter(TL1) with automatic reload. Overflow from TL1 not
only set TFx, but also reload TL1 with the content of TH1, which is preset by software. The reload leaves TH1
unchanged.
MCU in 12T mode
÷12
SYSclk
÷6
MCU in 6T mode
T1 Pin
C/T=0
C/T=1
TL1
(8 Bits)
TF1
Interrupt
control
TR1
GATE
TH1
(8 Bits)
INT1
Timer/Counter 1 Mode 2: 8-Bit Auto-Reload
;T1 Interrupt (falling edge) Demo programs, where T1 operated in Mode 2 (8-bit auto-relaod mode)
; The Timer Interrupt can not wake up MCU from Power-Down mode in the following programs
1. C program
/*-------------------------------------------------------------------------------*/
/* --- STC MCU International Limited ----------------------------------*/
/* --- STC90xx Series MCU T1(Falling edge) Demo -------------------*/
/* If you want to use the program or the program referenced in the */
/* article, please specify in which data and procedures from STC */
/*------------------------------------------------------------------------------*/
#include " reg51.h "
sfr AUXR = 0x8e;
//Auxiliary register
//T1 interrupt service routine
void t1int() interrupt 3
//T1 interrupt (location at 001BH)
{
P0++;
}
void main()
{
TMOD = 0x60;
TL1 = TH1 = 0xff;
TR1 = 1;
ET1 = 1;
EA = 1;
while (1);
}
STC MCU Limited.
//set timer1 as counter mode2 (8-bit auto-reload)
//fill with 0xff to count one time
//timer1 start run
//enable T1 interrupt
//open global interrupt switch
2. Assembly program
/*-------------------------------------------------------------------------------*/
/* --- STC MCU International Limited ----------------------------------*/
/* --- STC90xx Series MCU T1(Falling edge) Demo -------------------*/
/* If you want to use the program or the program referenced in the */
/* article, please specify in which data and procedures from STC */
/*------------------------------------------------------------------------------*/
;----------------------------------------;interrupt vector table
ORG 0000H
LJMP MAIN
ORG 001BH
LJMP T1INT
;T1 interrupt (location at 001BH)
;----------------------------------------ORG
0100H
MOV
MOV
MOV
MOV
MOV
SETB
SETB
SETB
SJMP
SP,
TMOD,
A,
TL1,
TH1,
TR1
ET1
EA
MAIN:
#7FH
#60H
#0FFH
A
A
;----------------------------------------;T1 interrupt service routine
T1INT:
CPL P0.0
RETI
;----------------------------------------END
STC MCU Limited.
;initial SP
;set timer1 as counter mode2 (8-bit auto-reload)
;fill with 0xff to count one time
;timer1 start run
;enable T1 interrupt
;open global interrupt switch
7.2 Application Notes for Timer 0/1 in practice
(1) Real-time Timer
Timer/Counter start running, When the Timer/Counter is overflow, the interrupt request generated, this
action handle by the hardware automatically, however, the process which from propose interrupt request to
respond interrupt request requires a certain amount of time, and that the delay interrupt request on-site with
the environment varies, it normally takes three machine cycles of delay, which will bring real-time processing
bias. In most occasions, this error can be ignored, but for some real-time processing applications, which
require compensation.
Such as the interrupt response delay, for timer mode 0 and mode 1, there are two meanings: the first,
because of the interrupt response time delay of real-time processing error; the second, if you require multiple
consecutive timing, due to interruption response delay, resulting in the interrupt service program once again
sets the count value is delayed by several count cycle.
If you choose to use Timer/Counter mode 1 to set the system clock, these reasons will produce real-time
error for this situation, you should use dynamic compensation approach to reducing error in the system clock,
compensation method can refer to the following example program.
...
CLR
EA
;disable interrupt
MOV
A,
TLx
;read TLx
ADD
A,
#LOW
;LOW is low byte of compensation value
MOV
TLx,
A
;update TLx
MOV
A,
THx
;read THx
ADDC A,
#HIGH
;HIGH is high byte of compensation value
MOV
THx,
A
;update THx
SETB
EA
;enable interrupt
...
(2) Dynamic read counts
When dynamic read running timer count value, if you do not pay attention to could be wrong, this is because it
is not possible at the same time read the value of the TLx and THx. For example the first reading TLx then THx,
because the timer is running, after reading TLx, TLx carry on the THx produced, resulting in error; Similarly,
after the first reading of THx then TLx, also have the same problems.
A kind of way avoid reading wrong is first reading THx then TLx and read THx once more, if the THx twice
to read the same value, then the read value is correct, otherwise repeat the above process. Realization method
reference to the following example code.
...
RDTM: MOV
A,
THx
;save THx to ACC
MOV
R0,
TLx
;save TLx to R0
CJNE
A,
THx,
RDTM
;read THx again and compare with the previous value
MOV
R1,
A
;save THx to R1
...
STC MCU Limited.
7.3 Timer/Counter 2
Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is
selected by bit in the SFR T2CON. In the "Timer" function, the register is incremented every 12 system clocks
or every 6 system clock depending on the setting in STC-ISP Writer/Programmer. See the follwing figure. In the
default state, it is fully the same as the conventional 8052. In the 6T mode, the count rate equals to the 6 system
clock.
Timer 2 has three operating modes: capture, auto-reload (up or dow=n counting), and baud rate generator. The
modes are selected by bits in T2CON. Timer 2 consists of two 8-bit registers, TH2 and TL2.
7.3.1 Special Function Registers about Timer/Counter 2
Symbol
Description
Bit Address and Symbol
Address
MSB
T2CON Timer/Counter 2 control
C8H
T2MOD
C9H
Timer/Counter 2 mode
Timer/Counter 2 Reload/
RCAP2L
Capture High Byte
Timer/Counter 2 Reload/
RCAP2H
Capture High Byte
Timer/Counter 2 Low
TL2
Byte
Timer/Counter 2 High
TH2
Byte
TF2 EXF2 RCLK TCLK
-
-
-
EXEN2
-
-
TR2 C/T2
-
Value after
Power-on or
LSB
Reset
CP/RL2 0000 0000B
T2OE DCEN
xxxx xx00B
CAH
0000 0000B
CBH
0000 0000B
CCH
0000 0000B
CDH
0000 0000B
1. T2CON: Timer/Counter 2 Control register (bit-addressable)
SFR Address bit
T2CON C8H name
B7
TF2
B6
EXF2
B5
RCLK
B4
TCLK
B3
EXEN2
B2
TR2
B1
C/T2
B0
CP/RL2
TF2 : Timer 2 overflow flag. TF2 is set by a Timer 2 overflow happens and must be cleared by software. TF2
will not be set when either RCLK=1 or TCLK=1.
EXF2 : Timer 2 external flag. Timer 2 external flag set when either a capture or reload is caused by a negative
transition on T2EX(P1.1) pin and EXEN2=1. When Timer 2 interrupt is enabled, EXF2=1 will cause the
CPU to vector the Timer 2 interrupt routine. EXF2 must be cleared by software.EXF2 does not cause an
interrupt in up/down mode(DCEN=1).
RCLK : Receive clock flag. When set, cause the serial port to use Timer 2 overflow pulses for its receive clock in
modes 1 and 3. When cleared, cause Timer 1 overflow to be used for the receive clock.
TCLK : Transmit clock flag.When set, cause the serial port to use Timer 2 overflow pulses for its transmit clock
in modes 1 and 3. When cleared, cause Timer 1 overflows to be used for the transmit clock.
EXEN2 : Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative
transition on T2EX(P1.1) pin if Timer 2 is not being used to clock the serial port. When cleared, cause
Timer 2 to ignore events at T2EX(P1.1) pin.
TR2 : Timer 2 Run control bit.When set, start the Timer 2. When cleared, stop the Timer 2.
STC MCU Limited.
C/T2 : Timer or counter selector.
0: Select Timer 2 as internal timer function.
1: Select Timer 2 as external event counter (falling edge triggered).
CP/RL2: Capture/Reload flag.
0 : Auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX pin when EXEN2=1.
1 : Captures will occur on negative transitions at T2EX pin if EXEN2=1.
Timer 2 has three operational modes: Capture Mode, Auto-Reload Mode (up or down counting), Baud-Rate Generator Mode, which are selected by bits T2CON and T2MOD as shown in following table.
Timer 2 Operating Modes Table
RCLK+TCLK CP/RL2 TR2
0
0
1
0
1
1
1
X
1
X
X
0
Mode
16-bit auto-reload
16-bit capture
buad rate generator
(off)
2. T2MOD: Timer/Counter 2 Mode register
bit
name
B7
B6
B5
B4
B3
B2
B1
B0
T20E
DCEN
T2OE : Timer 2 Output Enable bit. It enables Timer 2 overflow rate to toggle P1.0.
DCEN: Down Count Enable bit. When set, this allows Timer 2 to be configured as down counter
STC MCU Limited.
7.3.2 Timer / Counter 2 Operational Mode
Timer 2 is a 16-bit timer/counter which can operate as either an event timer or an event counter as selected by
C/T2 in the special function register T2CON. Timer 2 has four operation modes: Capture Mode, Auto-Reload
Mode (up or down counting), Baud-Rate Generator Mode, which are selected by bits T2CON and T2MOD as
shown in following table. Besides, Timer 2 also can be used as Programable Clock-Output.
Timer 2 Operating Modes Table
RCLK+TCLK CP/RL2 TR2
0
0
1
0
1
1
1
X
1
X
X
0
Mode
16-bit auto-reload
16-bit capture
buad rate generator
(off)
7.3.2.1 Capture Mode
In the capture mode there are two options selected by bit EXEN2 in T2CON. If EXEN2=0, Timer 2 is a 16-bit
timer or counter which upon overflowing sets bit TF2 (Timer 2 overflow flag). This bit can then be used to
generate an interrupt (by enabling the Timer 2 interrupt bit in the IE register). If EXEN2=1, Timer 2 still does the
above, but with the added feature that a 1-to-0 transition at external input T2EX causes the current value in the
Timer 2 registers, TH2 and TL2, to be captured into registers RCAP2H and RCAP2L, respectively. In addition,
the transition at T2EX causes bit EXF2 in T2CON to be set, and the EXF2 bit, like TF2, can generate an interrupt
which vectors to the same location as Timer 2 overflow interrupt. TF2 and EXF2 is ORed to request the interrupt
service. The capture mode is illustrated in following figure.
÷12
MCU in 12T mode
SYSclk
÷6
MCU in 6T mode
T2 Pin
C/T2=0
C/T2=1
Transition
Detector
control
TR2
TL2
(8 Bits)
TH2
(8 Bits)
TF2
capture
Timer 2
Interrupt
RCAP2L RCAP2H
T2EX Pin
EXF2
control
EXEN2
Timer 2 in Capture Mode
STC MCU Limited.
7.3.2.2 Auto-Reload Mode
In 16-bit auto-reload mode, Timer 2 can be configured to count up or down. The counting direction is determined
by DCEN in special function register T2MOD and T2EX pin. If DCEN=0, counting up. If DCEN=1, the counting
direction is determined by T2EX pin. If T2EX=1, counting up, otherwise counting down.
The following figure shows DCEN=0, which enables Timer 2 to count up automatically. In this mode there are
two options selected by bit EXEN2 in T2CON register. If EXEN2=0, then Timer 2 counts up to 0FFFFH and sets
the TF2 (Overflow Flag) bit upon overflow. This causes the Timer 2 registers to be reloaded with the 16-bit value
in RCAP2L and RCAP2H. The values in RCAP2L and RCAP2H are preset by firmware. If EXEN2=1, then a
16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at input T2EX. This transition also
sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be generated when either TF2 or EXF2 are 1.
÷12
MCU in 12T mode
SYSclk
÷6
MCU in 6T mode
T2 Pin
C/T2=0
C/T2=1
TL2
(8 Bits)
control
Transition
Detector
TR2
TH2
(8 Bits)
reload
T2EX Pin
Timer 2
Interrupt
TF2
RCAP2L RCAP2H
EXF2
control
EXEN2
Timer 2 in Auto-Reload Mode (DCEN=0)
The following figure shows DCEN=1, which enables Timer 2 to count up or down. This mode allows pin T2EX
to control the counting direction. When a logic 1 is applied at pin T2EX, Timer 2 will count up. Timer 2 will
overflow at 0FFFFH and set the TF2 flag, which can then generate an interrupt if the interrupt is enabled. This
overflow also causes the 16-bit value in RCAP2L and RCAP2H to be reloaded into the timer registers TL2 and
TH2. A logic 0 applied to pin T2EX causes Timer 2 to count down. The timer will underflow when TL2 and TH2
become equal to the value stored in RCAP2L and RCAP2H. This underflow sets the TF2 flag and causes 0FFFFH
to be reloaded into the timer registers TL2 and TH2.
The external flag EXF2 toggles when Timer 2 underflows or overflows. This EXF2 bit can be used as a 17th bit
of resolution if needed. The EXF2 flag does not generate an interrupt in this mode.
÷12
Down Counting Reload Value
MCU in 12T mode
FFH
Toggle
FFH
EXF2
SYSclk
÷6
MCU in 6T mode
T2 Pin
C/T2=0
C/T2=1
control
TL2
(8 Bits)
Overflow
TH2
(8 Bits)
TF2
Count Direction
1=UP
0=DOWN
TR2
RCAP2L RCAP2H
Up Counting Reload Value
Timer 2 in Auto-Reload Mode (DCEN=1)
STC MCU Limited.
T2EX Pin
Timer 2
Interrupt
7.3.2.3 Buad-Rate Generator Mode and Demo Program ( C and ASM)
Timer2 can be configured to generate various baud-rate. Bit TCLK and/or RCLK in T2CON allow the serial port
transmit and receive baud rates to be derived from either Timer1 or Timer2. When TCLK=0, Timer1 is used as
the serial port transmit baud rate generator. When TCLK=1, Timer2 is used as the serial port transmit baud rate
generator. RCLK has the same effect for the serial port baud rate. With these two bits, the serial port can have different receive and transmit baud rates - one generated from Timer 1 and the other from Timer 2.
In BRG mode, Timers is operated very like auto-reload up-only mode except that the T2EX pin cannot control reload. An overflow on Timer 2 will load RCAP2H, RCAP2L contents onto Timer2, but TF2 will not be set. A 1-to-0
transition on P2EX pin can set EXF2 to request interrupt service if EXEN2=1.
The following figure shows the Timer 2 in baud rate generation mode to generate RX Clock and TX Clock into
UART engine. The baud rate generation mode is like the auto-reload mode, in that a rollover in TH2 causes the
Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by
software.
The baud rate in UART Mode 1 and Mode 3 are determined by Timer2's overflow rate given below:
Timer 2 overflow rate
(counting T2EX)
16
The Timer can be configured for either " timer " or " counter " operation. In the most typical applications, it is
configured for " timer " operation(C/T2=0). " Timer " operation is a little different for Timer 2 when it's being used
as a baud rate generator. Normally, as timer it would increment every machine clcye(thus at 1/6 or 1/12 the
system clock).In that case the baud rate is given bu the formalu :
Baud Rate=
Baud Rate=
(as timer)
SYSclk
n×[65536 - (RCAP2H, RCAP2L)]
when MCU in 12T mode, n=32; When MCU in 6T mode, n=16.
Timer 1
Overflow
÷12
MCU in 12T mode
÷2
SYSclk
'0' '1'
÷6
MCU in 6T mode
T2 Pin
C/T2=0
C/T2=1
Transition
Detector
control
TL2
(8 Bits)
'1'
TH2
(8 Bits)
RCLK
Reload
TR2
RCAP2L RCAP2H
T2EX Pin
EXF2
control
Timer 2
Interrupt
EXEN2
Timer 2 in Baud-Rate Generator Mode
STC MCU Limited.
SMOD
'0'
'1'
'0'
÷16
RX Clock
÷16
TCLK
TX Clock
The Timer 2 as a baud rate generator mode is valid only if RCLK and/or TCLK=1 in T2CON register. Note that
a rollover in TH2 does not set TF2, and will not generate an interrupt. Thus, the Timer 2 interrupt does not have
to be disabled when Timer 2 is in the baud rate generator mode. Also if the EXEN2 (T2 external enable bit) is set,
a 1-to-0 transition in T2EX (Timer/counter 2 trigger input) will set EXF2 (T2 external flag) but will not cause
a reload from (RCAP2H, RCAP2L) to (TH2,TL2). Therefore when Timer 2 is in use as a baud rate generator,
T2EX can be used as an additional external interrupt, if needed.
It should be noted that when Timer 2 is running (TR2=1) in " timer " function in the baud rate generator mode, one
should not try to read or write TH2 and TL2. As a baud rate generator, Timer 2 is incremented at 1/2 the system
clock or asynchronously from pin T2; under these conditions, a read or write of TH2 or TL2 may not be accurate.
The RCAP2 registers may be read, but should not be written to, because a write might overlap a reload and cause
write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2
registers.
The following programs are the codes that domestrate Timer 2 of STC90xx series MCU acted as baud
rate generator of UART.
1. C language code
/*-------------------------------------------------------------------------------*/
/* --- STC MCU International Limited ----------------------------------*/
/* --- STC89-90xx Series MCU UART (8-bit/9-bit)Demo ------------*/
/* If you want to use the program or the program referenced in the */
/* article, please specify in which data and procedures from STC */
/*-------------------------------------------------------------------------------*/
#include " reg51.h "
#include " intrins.h "
sfr T2CON = 0xC8;
sfr RCAP2L = 0xCA;
sfr RCAP2H = 0xCB;
sfr TL2 = 0xCC;
sfr TH2 = 0xCD;
//timer2 control register
typedef unsigned char BYTE;
typedef unsigned int WORD;
#define FOSC 18432000L
#define BAUD 115200
STC MCU Limited.
//System frequency
//UART baudrate
/*Define UART parity mode*/
#define NONE_PARITY 0
#define ODD_PARITY 1
#define EVEN_PARITY 2
#define MARK_PARITY 3
#define SPACE_PARITY 4
//None parity
//Odd parity
//Even parity
//Mark parity
//Space parity
#define PARITYBIT EVEN_PARITY
//Testing even parity
sbit bit9 = P2^2;
bit busy;
//P2.2 show UART data bit9
void SendData(BYTE dat);
void SendString(char *s);
void main()
{
#if (PARITYBIT == NONE_PARITY)
SCON = 0x50;
//8-bit variable UART
#elif (PARITYBIT == ODD_PARITY) || (PARITYBIT == EVEN_PARITY) || (PARITYBIT == MARK_PARITY)
SCON = 0xda;
//9-bit variable UART, parity bit initial to 1
#elif (PARITYBIT == SPACE_PARITY)
SCON = 0xd2;
//9-bit variable UART, parity bit initial to 0
#endif
TL2 = RCAP2L = (65536-(FOSC/32/BAUD)); //Set auto-reload vaule
TH2 = RCAP2H = (65536-(FOSC/32/BAUD)) & gt; & gt; 8;
T2CON = 0x34;
//Timer2 start run
ES = 1;
//Enable UART interrupt
EA = 1;
//Open master interrupt switch
SendString( " STC90-90xx\r\nUart Test !\r\n " );
while(1);
}
/*---------------------------UART interrupt service routine
----------------------------*/
void Uart_Isr() interrupt 4 using 1
{
if (RI)
{
RI = 0;
P0 = SBUF;
bit9 = RB8;
}
if (TI)
{
TI = 0;
busy = 0;
}
}
STC MCU Limited.
//Clear receive interrupt flag
//P0 show UART data
//P2.2 show parity bit
//Clear transmit interrupt flag
//Clear transmit busy flag
/*---------------------------Send a byte data to UART
Input: dat (data to be sent)
Output:None
----------------------------*/
void SendData(BYTE dat)
{
while (busy);
//Wait for the completion of the previous data is sent
ACC = dat;
//Calculate the even parity bit P (PSW.0)
if (P)
//Set the parity bit according to P
{
#if (PARITYBIT == ODD_PARITY)
TB8 = 0;
//Set parity bit to 0
#elif (PARITYBIT == EVEN_PARITY)
TB8 = 1;
//Set parity bit to 1
#endif
}
else
{
#if (PARITYBIT == ODD_PARITY)
TB8 = 1;
//Set parity bit to 1
#elif (PARITYBIT == EVEN_PARITY)
TB8 = 0;
//Set parity bit to 0
#endif
}
busy = 1;
SBUF = ACC;
//Send data to UART buffer
}
/*---------------------------Send a string to UART
Input: s (address of string)
Output:None
----------------------------*/
void SendString(char *s)
{
while (*s)
{
SendData(*s++);
}
}
STC MCU Limited.
//Check the end of the string
//Send current char and increment string ptr
2. Assembly Code
/*-------------------------------------------------------------------------------*/
/* --- STC MCU International Limited ----------------------------------*/
/* --- STC89-90xx Series MCU UART (8-bit/9-bit)Demo ------------*/
/* If you want to use the program or the program referenced in the */
/* article, please specify in which data and procedures from STC */
/*-------------------------------------------------------------------------------*/
T2CON
TR2
EQU
BIT
0C8H
T2CON.2
;timer2 control register
T2MOD
RCAP2L
RCAP2H
TL2
TH2
EQU
EQU
EQU
EQU
EQU
0C9H
0CAH
0CBH
0CCH
0CDH
;timer2 mode register
;/*Define UART parity mode*/
#define NONE_PARITY 0
#define ODD_PARITY 1
#define EVEN_PARITY 2
#define MARK_PARITY 3
#define SPACE_PARITY 4
//None parity
//Odd parity
//Even parity
//Mark parity
//Space parity
#define PARITYBIT EVEN_PARITY //Testing even parity
;----------------------------------------BUSY BIT
20H.0
;transmit busy flag
;----------------------------------------ORG
0000H
LJMP
MAIN
ORG
0023H
LJMP
UART_ISR
;----------------------------------------ORG
0100H
MAIN:
CLR
BUSY
CLR
EA
MOV
SP,
#3FH
STC MCU Limited.
#if (PARITYBIT == NONE_PARITY)
MOV SCON,
#50H
;8-bit variable UART
#elif (PARITYBIT == ODD_PARITY) || (PARITYBIT == EVEN_PARITY) || (PARITYBIT == MARK_PARITY)
MOV SCON,
#0DAH
;9-bit variable UART, parity bit initial to 1
#elif (PARITYBIT == SPACE_PARITY)
MOV SCON,
#0D2H
;9-bit variable UART, parity bit initial to 0
#endif
;------------------------------MOV A,
#0FBH
;65536-18432000/32/115200 = 0xfffb
MOV TL2,
A
MOV RCAP2L, A
MOV A,
#0FFH
MOV TH2,
A
;Set auto-reload vaule
MOV RCAP2H, A
MOV T2CON
,#34H
;Timer2 start run
SETB ES
;Enable UART interrupt
SETB EA
;Open master interrupt switch
;------------------------------MOV DPTR,
#TESTSTR
;Load string address to DPTR
LCALL SENDSTRING
;Send string
;------------------------------SJMP
$
;----------------------------------------TESTSTR:
;Test string
DB " STC90-90xx Uart Test ! " ,0DH,0AH,0
;/*---------------------------;UART2 interrupt service routine
;----------------------------*/
UART_ISR:
PUSH ACC
PUSH PSW
JNB
RI,CHECKTI
CLR
RI
MOV
P0,SBUF
MOV
C,RB8
MOV
P2.2,C
CHECKTI:
JNB
TI,ISR_EXIT
CLR
TI
CLR
BUSY
ISR_EXIT:
POP
PSW
POP
ACC
RETI
STC MCU Limited.
;Check RI bit
;Clear RI bit
;P0 show UART data
;P2.2 show parity bit
;Check S2TI bit
;Clear S2TI bit
;Clear transmit busy flag
;/*---------------------------;Send a byte data to UART
;Input: ACC (data to be sent)
;Output:None
;----------------------------*/
SENDDATA:
JB
BUSY,$
MOV
ACC,A
JNB
P,
EVEN1INACC
ODD1INACC:
#if (PARITYBIT == ODD_PARITY)
CLR
TB8
#elif (PARITYBIT == EVEN_PARITY)
SETB
TB8
#endif
SJMP
PARITYBITOK
EVEN1INACC:
#if (PARITYBIT == ODD_PARITY)
SETB
TB8
#elif (PARITYBIT == EVEN_PARITY)
CLR
TB8
#endif
PARITYBITOK:
;Parity bit set completed
SETB
BUSY
MOV
SBUF, A
RET
;/*---------------------------;Send a string to UART
;Input: DPTR (address of string)
;Output:None
;----------------------------*/
SENDSTRING:
CLR
A
MOVC A,
@A+DPTR
JZ
STRINGEND
INC
DPTR
LCALL SENDDATA
SJMP
SENDSTRING
STRINGEND:
RET
;----------------------------------------END
STC MCU Limited.
;Wait for the completion of the previous data is sent
;Calculate the even parity bit P (PSW.0)
;Set the parity bit according to P
;Set parity bit to 0
;Set parity bit to 1
;Set parity bit to 1
;Set parity bit to 0
;Send data to UART buffer
;Get current char
;Check the end of the string
;increment string ptr
;Send current char
;Check next
7.3.2.4 Timer 2 as Programmable Clock Output and Demo Program (C and ASM)
The STC90xx seires is able to generate a programmable clock output on P1.0. When T2OE bit is set and C//T2
bit is cleared, Timer 2 overflow pulse will generate a 50% duty clock and output that to P1.0. The frequency of
clock-out is calculated according to the following formula.
SYSclk
Baud Rate=
n×[65536 - (RCAP2H, RCAP2L)
when MCU in 12T mode, n=4; when MCU in 6T mode, n=2.
Note Timer 2 overflag, TF2 will always not be set in this mode.
The input clock, SYSclk/2, increments the 16-bit timer (TH2, TL2). The timer repeatedly counts to overflow from
a loaded value. Once overflows occur, the contents of (RCAP2H, RCAP2L) are loaded into (TH2, TL2) for the
consecutive counting. In the clock-out mode, Timer2 rollovers will not generate an interrupt. This is similar to
when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as a baud rate generator and a clock
generator simultaneously. Note, however, that the baud-rate and the clock-out frequency depend on the same
overflow rate of Timer 2.The following figure shows the Timer 2 in programmable clock output mode.
÷12
MCU in 12T mode
SYSclk
÷6
control
MCU in 6T mode
TL2
(8 Bits)
TH2
(8 Bits)
TR2
RCAP2L RCAP2H
C/T2
÷2
T2 Pin (P1.0)
T2OE
Transition
Detector
T2EX Pin (P1.1)
EXF2
Timer 2 Interrupt
control
EXEN2
Timer 2 in Programmable Clock Output Mode
If Timer 2 in Programmabel Clock Out mode, some operations as shown below should be done:
o Set T2OE bit in T2MOD register.
o Clear C/T2 bit in T2CON register.
o Determine the 16-bit reload value from the formula and enter it in the RCAP2H and RCAP2L registers.
o Enter the same reload value as the initial value in the TH2 and TL2 registers.
o Set TR2 bit in T2CON register to start the Timer 2.
STC MCU Limited.
The following programs are the codes that domestrate Timer 2 of STC90xx series MCU acted as
Program Clock Output on P1.0.
1. C language code
/*--------------------------------------------------------------------------------*/
/* --- STC MCU International Limited -----------------------------------*/
/* --- STC89-90xx Series Programmable Clock Output Demo -------*/
/* If you want to use the program or the program referenced in the */
/* article, please specify in which data and procedures from STC */
/*-------------------------------------------------------------------------------*/
#include " reg51.h "
typedef unsigned char BYTE;
typedef unsigned int WORD;
//----------------------------------------------/* define constants */
#define FOSC 18432000L
#define F38_4KHz
(65536-18432000/4/38400)
/* define SFR */
sfr T2CON = 0xc8;
sbit TF2 = T2CON^7;
sbit TR2 = T2CON^2;
//timer2 control register
sfr T2MOD = 0xc9;
sfr RCAP2L = 0xca;
sfr RCAP2H = 0xcb;
sfr TL2 = 0xcc;
sfr TH2 = 0xcd;
//timer2 mode register
sbit T2 = P1^0;
//Clock Output pin
//----------------------------------------------/* main program */
void main()
{
T2MOD = 0x02;
RCAP2L = TL2 = F38_4KHz;
RCAP2H = TH2 = F38_4KHz & gt; & gt; 8;
TR2 = 1;
EA = 1;
while (1);
}
STC MCU Limited.
//enable timer2 output clock
//initial timer2 low byte
//initial timer2 high byte
//timer2 start running
//open global interrupt switch
//loop
2. Assembly Code
/*--------------------------------------------------------------------------------*/
/* --- STC MCU International Limited -----------------------------------*/
/* --- STC89-90xx Series Programmable Clock Output Demo -------*/
/* If you want to use the program or the program referenced in the */
/* article, please specify in which data and procedures from STC */
/*-------------------------------------------------------------------------------*/
;/* define constants */
F38_4KHz EQU 0FF88H
;38.4KHz frequency calculation method of 12T mode (65536-18432000/4/38400)
;/* define SFR */
T2CON EQU
TF2
BIT
TR2
BIT
0C8H
T2CON.7
T2CON.2
T2MOD
RCAP2L
RCAP2H
TL2
TH2
EQU
EQU
EQU
EQU
EQU
;timer2 control register
0C9H
0CAH
0CBH
0CCH
0CDH
;timer2 mode register
T2
BIT P1.0
;Clock Output pin
;----------------------------------------------ORG 0000H
LJMP MAIN
;----------------------------------------------;/* main program */
MAIN:
MOV T2MOD, #02H
;enable timer2 output clock
MOV T2CON, #00H
;timer2 stop
MOV TL2,
#00H
;initial timer2 low byte
MOV TH2,
#00H
;initial timer2 high byte
MOV RCAP2L, #LOW F38_4KHz
;initial timer2 reload low byte
MOV RCAP2H, #HIGH F38_4KHz
;initial timer2 reload high byte
SETB TR2
;timer2 start running
SJMP $
;----------------------------------------------END
STC MCU Limited.
7.3.2.5 Demo Program of Timer 2 as Timer mode (C and ASM)
1. C language code
/*--------------------------------------------------------------------------------*/
/* --- STC MCU International Limited -----------------------------------*/
/* --- STC89-90xx Series 16-bit Timer Demo ---------------------------*/
/* If you want to use the program or the program referenced in the */
/* article, please specify in which data and procedures from STC */
/*-------------------------------------------------------------------------------*/
#include " reg51.h "
typedef unsigned char BYTE;
typedef unsigned int WORD;
//----------------------------------------------/* define constants */
#define FOSC 18432000L
#define T1MS (65536-FOSC/12/1000)
//1ms timer calculation method in 12T mode
/* define SFR */
sbit ET2 = IE^5;
sfr T2CON = 0xc8;
sbit TF2 = T2CON^7;
sbit TR2 = T2CON^2;
//timer2 control register
sfr T2MOD = 0xc9;
sfr RCAP2L = 0xca;
sfr RCAP2H = 0xcb;
sfr TL2 = 0xcc;
sfr TH2 = 0xcd;
//timer2 mode register
sbit TEST_LED = P1^0;
//work LED, flash once per second
/* define variables */
WORD count;
//1000 times counter
//----------------------------------------------STC MCU Limited.
/* Timer2 interrupt routine */
void tm2_isr() interrupt 5 using 1
{
TF2 = 0;
if (count-- == 0)
{
count = 1000;
TEST_LED = ! TEST_LED;
}
}
//----------------------------------------------/* main program */
void main()
{
RCAP2L = TL2 = T1MS;
RCAP2H = TH2 = T1MS & gt; & gt; 8;
TR2 = 1;
ET2 = 1;
EA = 1;
count = 0;
while (1);
//1ms * 1000 - & gt; 1s
//reset counter
//work LED flash
//initial timer2 low byte
//initial timer2 high byte
//timer2 start running
//enable timer2 interrupt
//open global interrupt switch
//initial counter
//loop
}
2. Assembly code
/*--------------------------------------------------------------------------------*/
/* --- STC MCU International Limited -----------------------------------*/
/* --- STC89-90xx Series 16-bit Timer Demo ---------------------------*/
/* If you want to use the program or the program referenced in the */
/* article, please specify in which data and procedures from STC */
/*-------------------------------------------------------------------------------*/
;/* define constants */
T1MS
EQU 0FA00H
;/* define SFR */
ET2
BIT
IE.5
STC MCU Limited.
;1ms(1000Hz) timer (65536-18432000/12/1000)
T2CON EQU
TF2
BIT
TR2
BIT
0C8H
T2CON.7
T2CON.2
;timer2 control register
T2MOD EQU
RCAP2L EQU
RCAP2H EQU
TL2
EQU
TH2
EQU
0C9H
0CAH
0CBH
0CCH
0CDH
;timer2 mode register
TEST_LED
BIT P1.0
;/* define variables */
COUNT DATA 30H
;work LED, flash once per second
;1000 times counter (2 bytes)
;----------------------------------------------ORG
LJMP
ORG
LJMP
0000H
MAIN
002BH
TM2_ISR
;----------------------------------------------;/* main program */
MAIN:
MOV T2MOD,#00H
MOV T2CON,#00H
MOV TL2,#00H
MOV TH2,#00H
MOV RCAP2L,#LOW T1MS
MOV RCAP2H,#HIGH T1MS
SETB TR2
SETB ET2
SETB EA
CLR A
MOV COUNT,A
MOV COUNT+1,A
SJMP $
;-----------------------------------------------
STC MCU Limited.
;initial timer2 mode
;timer2 stop
;initial timer2 low byte
;initial timer2 high byte
;initial timer2 reload low byte
;initial timer2 reload high byte
;timer2 start running
;enable timer2 interrupt
;open global interrupt switch
;initial counter
;/* Timer2 interrupt routine */
TM2_ISR:
PUSH ACC
PUSH PSW
CLR
TF2
MOV
A,
COUNT
ORL
A,
COUNT+1
JNZ
SKIP
MOV
COUNT, #LOW 1000
MOV
COUNT+1,
#HIGH 1000
CPL
TEST_LED
SKIP:
CLR
C
MOV
A,
COUNT
SUBB A,
#1
MOV
COUNT, A
MOV
A,
COUNT+1
SUBB A,
#0
MOV
COUNT+1,A
POP
PSW
POP
ACC
RETI
;----------------------------------------------END
STC MCU Limited.
;check whether count(2byte) is equal to 0
;1ms * 1000 - & gt; 1s
;work LED flash
;count--
Chapter 8. Serial Interface (UART) with Enhance Function
STC90C51RC/RD+ series MCU have one Universal Asychronous Receiver/Transmitter ---- serial port (UART).
The serial port is full duplex,meaning it can transmit and receive simultaneously. It is also receive-buffered,
meaning it can commence reception of a second byte before a previously received byte has been read from the
reeeive register. (However,if the first byte still hasn't been read by the time reception of the second byte is complete, one of the bytes will be lost). The serial port receive and transmit share the same SFR - SBUF, but actually
there is two SBUF in the chip, one is for transmit and the other is for receive.
The serial port(UART) can be operated in 4 different modes: Mode 0 provides synchronous communication
while Modes 1, 2, and 3 provide asynchronous communication. The asynchronous communication operates
as a full-duplex Universal Asynchronous Receiver and Transmitter (UART), which can transmit and receive
simultaneously and at different baud rates.
Serial communiction involves the transimission of bits of data through only one communication line. The data are
transimitted bit by bit in either synchronous or asynchronous format. Synchronous serial communication transmits
ont whole block of characters in syschronization with a reference clock while asynchronous serial communication
randomly transmits one character at any time, independent of any clock.
8.1 Special Function Registers about UART
Symbol
Description
SCON
Serial Control
98H
TI
RI
Value after
Power-on or
Reset
0000 0000B
PD
IDL
00x1 0000B
Bit Address and Symbol
Address
MSB
SBUF
Serial Buffer
Power Control
87H
IE
Interrupt Enable
A8H
LSB
SM1
SM2
REN
TB8
POF
GF1
RB8
99H
PCON
SM0/FE
IPH
IP
SADEN
SADDR
Interrupt Priority
High
Interrupt Priority
Low
Slave Address
Mask
Slave Address
STC MCU Limited.
B7H
B8H
xxxx xxxxB
SMOD SMOD0
EA
-
ET2
ES
ET1
GF0
EX1
ET0
EX0
PX3H PX2H PT2H PSH PT1H PX1H PT0H PX0H
-
-
PT2
PS
PT1
PX1
PT0
PX0
0x00 0000B
0000 0000B
xx00 0000B
B9H
0000 0000B
A9H
0000 0000B
1. Serial Port 1 (UART1) Control Register: SCON and PCON
Serial port 1 of STC90C51RC/RD+ series has two control registers: Serial port control register (SCON) and
PCON which used to select Baud-Rate
SCON: Serial port Control Register (Bit-Addressable)
SFR name
Address
bit
B7
B6
B5
B4
B3
B2
B1
B0
SCON
98H
name
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
FE: Framing Error bit. The SMOD0 bit must be set to enable access to the FE bit
0: The FE bit is not cleared by valid frames but should be cleared by software.
1: This bit set by the receiver when an invalid stop bit id detected.
SM0,SM1 : Serial Port Mode Bit 0/1.
SM0
SM1
Description
0
0
8-bit shift register
0
1
8-bit UART
1
0
9-bit UART
1
1
9-bit UART
Baud rate
SYSclk/12
variable
SYSclk/64 or SYSclk/32(SMOD=1)
variable
SM2 : Enable the automatic address recognition feature in mode 2 and 3. If SM2=1, RI will not be
set unless the received 9th data bit is 1, indicating an address, and the received byte is a
Given or Broadcast address. In mode1, if SM2=1 then RI will not be set unless a valid stop
Bit was received, and the received byte is a Given or Broadcast address. In mode 0, SM2 should be 0.
REN : When set enables serial reception.
TB8 : The 9th data bit which will be transmitted in mode 2 and 3.
RB8 : In mode 2 and 3, the received 9th data bit will go into this bit.
TI : Transmit interrupt flag. Set by hardware when a byte of data has been transmitted by UART0 (after the 8th
bit in 8-bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When the UART0 interrupt is enabled, setting this bit causes the CPU to vector to the UART0 interrupt service routine. This bit
must be cleared manually by software.
RI : Receive interrupt flag. Set to '1' by hardware when a byte of data has been received by UART0 (set at the
STOP bit sam-pling time). When the UART0 interrupt is enabled, setting this bit to '1' causes the CPU to
vector to the UART0 interrupt service routine. This bit must be cleared manually by software.
SMOD/PCON.7 in PCON register can be used to set whether the baud rates of mode 1, mode2 and mode 3
are doubled or not.
PCON: Power Control register (Non bit-addressable)
SFR name
PCON
Address
87H
bit
name
B7
SMOD
B6
SMOD0
B5
-
B4
POF
B3
GF1
B2
GF0
B1
PD
B0
IDL
SMOD : double Baud rate control bit.
0 : Disable double Baud rate of the UART.
1 : Enable double Baud rate of the UART in mode 1,2,or 3.
SMOD0 : Frame Error select.
0 : SCON.7 is SM0 function.
1 : SCON.7 is FE function. Note that FE will be set after a frame error regardless of the state of SMOD0.
STC MCU Limited.
2. SBUF: Serial port Data Buffer register (Non bit-addressable)
SFR name
SBUF
Address
99H
bit
name
B7
B6
B5
B4
B3
B2
B1
B0
It is used as the buffer register in transmission and reception.The serial port buffer register (SBUF) is really two
buffers. Writing to SBUF loads data to be transmitted, and reading SBUF accesses received data. These are two
separate and distinct registers, the transimit write-only register, and the receive read-only register.
3. Slave Address Control registers SADEN and SADDR
SADEN: Slave Address Mask register
SADDR: Slave Address register
SADDR register is combined with SADEN register to form Given/Broadcast Address for automatic address
recognition. In fact, SADEN function as the " mask " register for SADDR register. The following is the example
for it.
SADDR = 1100 0000
SADEN = 1111 1101
Given
= 1100 00x0
The Given slave address will be checked except bit 1 is
treated as " don't care " .
The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zero in this
result is considered as " don't care " and a Broad cast Address of all " don't care " . This disables the automatic
address detection feature.
4. Registers related with UART1 interrupt : IE, IP and IPH
IE: Interrupt Enable Rsgister (Bit-addressable)
SFR name Address
IE
A8H
bit
B7
B6
B5
B4
B3
B2
B1
B0
name
EA
-
ET2
ES
ET1
EX1
ET0
EX0
EA : disables all interrupts.
If EA = 0,no interrupt will be acknowledged.
If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit.
ES :
Serial port 1(UART1) interrupt enable bit.
If ES = 0, Serial port 1(UART1) interrupt will be diabled.
If ES = 1, Serial port 1(UART1) interrupt is enabled.
IPH: Interrupt Priority High Register (Non bit-addressable)
SFR name Address
IPH
B7H
bit
B7
B6
B5
B4
name
PX3H
PX2H
PT2H
PSH
B3
B2
B1
PT1H PX1H PT0H
B0
PX0H
IP: Interrupt Priority Register (Bit-addressable)
SFR name Address
IP
B8H
bit
B7
B6
B5
B4
B3
B2
B1
B0
name
-
-
PT2
PS
PT1
PX1
PT0
PX0
PSH, PS: Serial Port (UART) interrupt priority control bits.
if PSH=0 and PS=0, UART interrupt is assigned lowest priority (priority 0).
if PSH=0 and PS=1, UART interrupt is assigned lower priority (priority 1).
if PSH=1 and PS=0, UART interrupt is assigned higher priority (priority 2).
if PSH=1 and PS=1, UART interrupt is assigned highest priority (priority 3).
STC MCU Limited.
8.2 UART Operational Modes
The serial port (UART) can be operated in 4 different modes which are configured by setting SM0 and SM1 in
SFR SCON. Mode 1, Mode 2 and Mode 3 are asynchronous communication. In Mode 0, UART is used as a
simple shift register.
8.2.1 Mode 0: 8-Bit Shift Register
Mode 0, selected by writing 0s into bits SM1 and SM0 of SCON, puts the serial port into 8-bit shift register mode.
Serial data enters and exits through RXD. TXD outputs the shift clock. Eight data bits are transmitted/received
with the least-significant (LSB) first. The baud rate is fixed at 1/12 the System clock cycle in the default state. If
the corresponding option is set in STC-ISP Writer/Programmer, the baud rate is 1/6 System clock cycle.
Transmission is initiated by any instruction that uses SBUF as a destination register. The "write to SBUF" signal
also loads a "1" into the 9th position of the transmit shift register and tells the TX Control block to commence a
transmission. The internal timing is such that one full system clock cycle will elapse between " write to SBUF, "
and activation of SEND.
SEND transfers the output of the shift register to the alternate output function line of P3.0, and also transfers Shift
Clock to the alternate output function line of P3.1. At the falling edge of the Shift Clock, the contents of the shift
register are shifted one position to the right.
As data bits shift out to the right, "0" come in from the left. When the MSB of the data byte is at the output
position of the shift register, then the "1" that was initially loaded into the 9th position is just to the left of the
MSB, and all positions to the left of that contains zeroes. This condition flags the TX Control block to do one last
shift and then deactivate SEND and set TI. Both of these actions occur after " write to SBUF " .
Reception is initiated by the condition REN=1 and RI=0. After that, the RX Control unit writes the bits 11111110
to the receive shift register, and in the next clock phase activates RECEIVE. RECEIVE enables SHIFT CLOCK
to the alternate output function line of P3.1.At RECEIVE is active, the contents of the receive shift register are
shifted to the left one position. The value that comes in from the right is the value that was sampled at the P3.0
pin the rising edge of Shift clock.
As data bits come in from the right, "1"s shift out to the left. When the "0" that was initially loaded into the rightmost position arrives at the left-most position in the shift register, it flags the RX Control block to do one last shift
and load SBUF. Then RECEIVE is cleared and RI is set.
STC MCU Limited.
INTERNAL BUS
WRITE
TO
SBUF
DS Q
CL
RXD/P3.0
OUTPUT FUNCTION
SBUF
SHIFT
ZERO DETECTOR
SYSclk/12
SYSclk/6
START
0
1
SHIFT
TX CONTROL
Setting in SIC-ISP
Writer/Programmer
REN
RI
TX CLOCK
SEND
TI
RX CLOCK
SERIAL
PORT
INTERRUPT
RI
TXD/P3.1
OUTPUT FUNCTION
SHIFT
CLOCK
RECEIVE
RX CONTROL SHIFT
START
1 1 1 1 1 1 1 0
RXD/P3.0
INPUT FUNCTION
INPUT SHIFT REG.
LOAD
SBUF
SHIFT
SBUF
READ
SBUF
INTERNAL BUS
WRITE TO SBUF
SEND
SHIFT
RXD(DATA OUT)
TRANSMIT
D0
D1
D2
D3
D4
D5
D6
D7
TXD(SHIFT CLOCK)
TI
WRITE TO SCON(CLEAR RI)
RI
RECEIVE
RECEIVE
SHIFT
RXD(DATA IN)
D0
D1
D2
D3
TXD(SHIFT CLOCK)
Serial Port Mode 0
STC MCU Limited.
D4
D5
D6
D7
8.2.2 Mode 1: 8-Bit UART with Variable Baud Rate
In mode 1 the STC90xx serial port operates as an 8-bit UART with variable baud rate. A UART, or " universal
asynchronous receiver/transmitter, " is a device that receives and transmits serial data with each data character
preceded by a start bit(low) and followed by a stop bit(high). A parity bit is sometimes inserted between the last
data bit and the stop bit. The essential operation of a UART is parallel-to-serial conversion of output data and
serial-to-parallel conversion of input data.
In mode 1, 10 bits are transmitted through TXD or received through RXD. The frame data includes a start bit
(always 0), 8 data bits (LSB first) and a stop bit (always 1). For a receive operation, the stop bit goes into RB8 in
SFR - SCON. The baud rate is determined by the overflow rate of Timer 1 or Timer 2 .
Baud rate in mode 1 = (2SMOD /32 ) x timer 1 overflow rate
or = (2SMOD /16 ) x Timer 2 overflow rate
Transmission is initiated by any instruction that uses SBUF as a destination register. The "write to SBUF"
signal also loads a "1" into the 9th bit position of the transmit shift register and flags the TX Control unit that a
transmission is requested. Transmission actually happens at the next rollover of divided-by-16 counter. Thus the
bit times are synchronized to the divided-by-16 counter, not to the "write to SBUF" signal.
The transmission begins with activation of SEND, which puts the start bit at TXD. One bit time later, DATA is
activated, which enables the output bit of the transmit shift register to TXD. The first shift pulse occurs one bit
time after that.
As data bits shift out to the right, zeroes are clocked in from the left. When the MSB of the data byte is at the
output position of the shift register, then the 1 that was initially loaded into the 9th position is just to the left of the
MSB, and all positions to the left of that contain zeroes. This condition flags the TX Control unit to do one last
th
shift and then deactivate SEND and set TI. This occurs at the 10 divide-by-16 rollover after "write to SBUF."
Reception is initiated by a 1-to-0 transition detected at RXD. For this purpose, RXD is sampled at a rate of 16
times the established baud rate. When a transition is detected, the divided-by-16 counter is immediately reset,
and 1FFH is written into the input shift register. Resetting the divided-by-16 counter aligns its roll-overs with the
boundaries of the incoming bit times.
The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th and 9th counter states of each bit time,
the bit detector samples the value of RXD. The value accepted is the value that was seen in at least 2 of the 3
samples. This is done to reject noise. In order to reject false bits, if the value accepted during the first bit time is
not a 0, the receive circuits are reset and the unit continues looking for another 1-to-0 transition. This is to provide
rejection of false start bits. If the start bit is valid, it is shifted into the input shift register, and reception of the rest
of the frame proceeds.
As data bits come in from the right, "1"s shift out to the left. When the start bit arrives at the left most position
in the shift register,(which is a 9-bit register in Mode 1), it flags the RX Control block to do one last shift, load
SBUF and RB8, and set RI. The signal to load SBUF and RB8 and to set RI is generated if, and only if, the
following conditions are met at the time the final shift pulse is generated.
1) RI=0 and
2) Either SM2=0, or SM2=0 and the received stop bit = 1
If either of these two conditions is not met, the received frame is irretrievably lost. If both conditions are met, the
stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated. At this time, whether or not the above
conditions are met, the unit continues looking for a 1-to-0 transition in RXD.
STC MCU Limited.
STC MCU INTERNAL BUS
TIMER 2
OVERFLOW
TIMER 1
OVERFLOW
TB8
WRITE
TO
SBUF
DS Q
CL
÷2
SMOD
=0
SMOD
=1
TXD
SBUF
ZERO DETECTOR
SHIFT
START
" 0 " " 1 "
DATA
TX CONTROL
TCLK
÷16
TX CLOCK
SEND
TI
SERIAL
PORT
INTERRUPT
" 0 " " 1 "
RCLK
SAMPLE
÷16
RX CLOCK
START
RI
LOAD
SBUF
RX CONTROL SHIFT
1FFH
1-TO-0
TRANSITION
DETECTOR
BIT
DETECTOR
INPUT SHIFT REG.
(9 BITS)
RXD
SHIFT
LOAD
SBUF
SBUF
READ
SBUF
STC MCU INTERNAL BUS
TX
CLOCK
WRITE TO SBUF
SEND
TRANSMIT
DATA
SHIFT
D0
TXD
START BIT
TI
D1
D2
RX CLOCK
START BIT
D4
D5
D6
D1
D2
D3
D4
D5
STOP BIT
D7
÷16 RESET
RXD
RECEIVE
D3
D0
BIT DETECTOR SAMPLE TIMES
SHIFT
RI
Serial Port Mode 1
STC MCU Limited.
D6
D7
STOP BIT
8.2.3 Mode 2: 9-Bit UART with Fixed Baud Rate
When SM1=1 and SM0=0, the serial port operates in mode 2 as a 9-bit UART with a fixed baud rate. 11 bits
are transmitted through TXD or received through RXD. The frame data includes a start bit(0), 8 data bits, a
programmable 9th data bit and a stop bit(1). On transmit, the 9th data bit comes from TB8 in SCON. On receive,
the 9th data bit goes into RB8 in SCON. The baud rate is programmable to either 1/32 or 1/64 the System clock
cycle.
Baud rate in mode 2 = (2SMOD/64) x SYSclk
Transmission is initiated by any instruction that uses SBUF as a destination register. The "write to SBUF"
signal also loads TB8 into the 9th bit position of the transmit shift register and flags the TX Control unit that a
transmission is requested. Transmission actually happens at the next rollover of divided-by-16 counter. Thus the
bit times are synchronized to the divided-by-16 counter, not to the "write to SBUF" signal.
The transmission begins when /SEND is activated, which puts the start bit at TXD. One bit time later, DATA is
activated, which enables the output bit of the transmit shift register to TXD. The first shift pulse occurs one bit
time after that. The first shift clocks a "1"(the stop bit) into the 9th bit position on the shift register. Thereafter,
only "0"s are clocked in. As data bits shift out to the right, "0"s are clocked in from the left. When TB8 of the data
byte is at the output position of the shift register, then the stop bit is just to the left of TB8, and all positions to the
left of that contains "0"s. This condition flags the TX Control unit to do one last shift, then deactivate /SEND and
set TI. This occurs at the 11th divided-by-16 rollover after "write to SBUF".
Reception is initiated by a 1-to-0 transition detected at RXD. For this purpose, RXD is sampled at a rate of
16 times whatever baud rate has been estabished. When a transition is detected, the divided-by-16 counter is
immediately reset, and 1FFH is written into the input shift register.
At the 7th, 8th and 9th counter states of each bit time, the bit detector samples the value of RXD. The value accepted
is the value that was seen in at least 2 of the 3 samples. This is done to reject noise. In order to reject false bits, if
the value accepted during the first bit time is not a 0, the receive circuits are reset and the unit continues looking
for another 1-to-0 transition. If the start bit is valid, it is shifted into the input shift register, and reception of the
rest of the frame proceeds.
As data bits come in from the right, "1"s shift out to the left. When the start bit arrives at the leftmost position
in the shift register,(which is a 9-bit register in Mode-2 and 3), it flags the RX Control block to do one last shift,
load SBUF and RB8, and set RI. The signal to load SBUF and RB8 and to set RI is generated if, and only if, the
following conditions are met at the time the final shift pulse is generated.:
1) RI=0 and
2) Either SM2=0, or the received 9th data bit = 1
If either of these two conditions is not met, the received frame is irretrievably lost. If both conditions are met,
the stop bit goes into RB8, the first 8 data bits go into SBUF, and RI is activated. At this time, whether or not the
above conditions are met, the unit continues looking for a 1-to-0 transition at the RXD input.
Note that the value of received stop bit is irrelevant to SBUF, RB8 or RI.
STC MCU Limited.
INTERNAL BUS
TB8
WRITE
TO
SBUF
DS Q
CL
TXD
SBUF
ZERO DETECTOR
SYSclk/2
STOP BIT
START GEN.
MODE 2
SHIFT
DATA
TX CONTROL
÷16
÷2
TX CLOCK
SEND
TI
SERIAL
PORT
INTERRUPT
SMOD=1
SMOD=0
÷16
SAMPLE
(SMOD IS PCON.7)
1-TO-0
TRANSITION
DETECTOR
START
RX
RI
CLOCK
LOAD
SBUF
RX CONTROL SHIFT
1FFH
BIT
DETECTOR
INPUT SHIFT REG.
(9 BITS)
RXD
SHIFT
LOAD
SBUF
SBUF
READ
SBUF
INTERNAL BUS
TX
CLOCK
WRITE TO SBUF
SEND
TRANSMIT
DATA
SHIFT
D0
TXD
START BIT
TI
D1
D2
D3
D4
D5
D6
D7
TB8
STOP BIT
START BIT
D0
D1
D2
D3
D4
D5
D6
D7
STOP BIT GEN
RX CLOCK
RXD
RECEIVE
BIT DETECTOR SAMPLE TIMES
SHIFT
RI
Serial Port Mode 2
STC MCU Limited.
RB8
STOP BIT
8.2.4 Mode3: 9-Bit UART with Variable Baud Rate
Mode 3, 9-bit UART with variable baud rate, is the same as mode 2 except the baud rate is variable.
Baud rate in mode 3 = (2SMOD /32 ) x Timer 1overflow rate
or = (2SMOD /16 ) x Timer 2 overflow rate
In all four modes, transmission is initiated by any instruction that use SBUF as a destination register. Reception
is initiated in mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the
incoming start bit with 1-to-0 transition if REN=1.
STC MCU Limited.
STC MCU INTERNAL BUS
TIMER 2
OVERFLOW
TIMER 1
OVERFLOW
TB8
WRITE
TO
SBUF
DS Q
CL
÷2
SMOD
=1
SMOD
=0
TXD
SBUF
ZERO DETECTOR
SHIFT
START
" 0 " " 1 "
DATA
TX CONTROL
TCLK
÷16
TI
SEND
RI
TX CLOCK
LOAD
SBUF
SERIAL
PORT
INTERRUPT
" 0 " " 1 "
RCLK
÷16
SAMPLE
1-TO-0
TRANSITION
DETECTOR
RX CLOCK
START
RX CONTROL SHIFT
1FFH
BIT
DETECTOR
INPUT SHIFT REG.
(9 BITS)
RXD
SHIFT
LOAD
SBUF
SBUF
READ
SBUF
STC MCU INTERNAL BUS
TX
CLOCK
WRITE TO SBUF
SEND
TRANSMIT
DATA
SHIFT
D0
TXD
START BIT
TI
D1
D2
D3
D4
D5
D6
D7
TB8
STOP BIT
D1
D2
D3
D4
D5
D6
D7
STOP BIT GEN
RX CLOCK
RXD
RECEIVE
÷16 RESET
START BIT
D0
BIT DETECTOR SAMPLE TIMES
SHIFT
RI
Serial Port Mode 3
STC MCU Limited.
RB8
STOP BIT
8.3 Frame Error Detection
When used for frame error detect, the UART looks for missing stop bits in the communication. A missing bit will
set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0 and the function of SCON.7 is
determined by PCON.6(SMOD0). If SMOD0 is set then SCON.7 functions as FE. SCON.7 functions as SM0
when SMOD0 is cleared.When used as FE,SCON.7 can only be cleared by software.Refer to the following figure.
9-bit data
START BIT
D0
D1
D2
D3
D4
D5
D6
D7
D8
STOP BIT
SET FE bit if STOP=0
SM0 to UART mode control
PCON.SMOD0
SCON SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
UART Frame Error Detection
8.4 Multiprocessor Communications
Modes 2 and 3 have a special provision for multiproceasor communications. In these modes 9 data bits are
received.The 9th one goes into RB8. Then comes a stop bit. The port can be programmed such that when the stop
bit is received,the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit
SM2 in SCON. A way to use this feature in multiprocessor systems is as follows.
When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address
byte which identifies the target slave.An address byte differs from a data byte in that the 9th bit is 1 in an address
byte and 0 in a data byte.With SM2 = 1, no slave will be interrupted by a data byte. An address byte, however,will
interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed.The addressed
slave will clear its SM2 bit and prepare to receive the data bytes that will be coming. The slaves that weren't being addressed leave their SM2s set and go on about their business, ignoring the coming data bytes.
SM2 has no effect in Mode 0,and in Mode 1 can be used to check the validity of the stop bit. In a Mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a vatid stop bit is received.
STC MCU Limited.
8.5 Automatic Address Recognition
Automatic Address Recognition is a future which allows the UART to recognize certain addresses in the serial
bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by
eliminating the need for the software to examine every serial address which passes by the serial port. This feature
is enabled by setting the SM2 bit in SCON. In the 9-bit UART modes, Mode 2 and Mode 3, the Receive interrupt
flag(RI) will be automatically set when the received byte contains either the "Given" address or the "Broadcast"
address. The 9-bit mode requires that the 9th information bit is a "1" to indicate that the received information is an
address and not data.
The 8-bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information
received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast
address.
Mode 0 is the Shift Register mode and SM2 is ignored.
Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more
slaves by invoking the given slave address or addresses. All of the slaves may be contacted by using the broadcast
address. Two special function registers are used to define the slave's address, SADDR, and the address mask,
SADEN. SADEN is used to define which bits in the SADDR are to be used and which bits are "don't care". The
SADEN mask can be logically ANDed with the SADDR to create the "Given" address which the master will
use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized which
excluding others. The following examples will help to show the versatility of this scheme :
Slave 0
SADDR = 1100 0000
SADEN = 1111 1101
GIVEN = 1100 00x0
Slave 1
SADDR = 1100 0000
SADEN = 1111 1110
GIVEN = 1100 000x
In the previous example SADDR is the same and the SADEN data is used to differentiate between the two slaves.
Slave 0 requires a "0" in bit 0 and it ignores bit 1. Slave 1 requires a "0" in bit 1 and bit 0 is ignored. A unique
address for slave 0 would be 11000010 since slave 1 requires a "0" in bit 1. A unique address for slave 1 would
be 11000001 since a "1" in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address
which has bit 0=0 (for slave 0) and bit 1 =0 (for salve 1). Thus, both could be addressed with 11000000.
In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0:
Slave 0
SADDR = 1100 0000
SADEN = 1111 1001
GIVEN = 1100 0xx0
Slave 1
SADDR = 1110 0000
SADEN = 1111 1010
GIVEN = 1110 0x0x
Slave 2
SADDR = 1110 0000
SADEN = 1111 1100
GIVEN = 1110 00xx
STC MCU Limited.
In the above example the differentiation among the 3 slaves is in the lower 3 address bits.Slave 0 requires that
bit0 = 0 and it can be uniquely addressed by 11100110. Slave 1 requires that bit 1=0 and it can be uniquely
addressed by 11100101. Slave 2 requires that bit 2=0 and its unique address is 11100011. To select Salve 0 and 1
and exclude Slave 2, use address 11100100, since it is necessary to make bit2=1 to exclude Slave 2.
The Broadcast Address for each slave is created by taking the logic OR of SADDR and SADEN. Zeros in this
result are trended as don't cares. In most cares, interpreting the don't cares as ones, the broadcast address will be
FF hexadecimal.
Upon reset SADDR and SADEN are loaded with "0"s. This produces a given address of all "don't cares as well
as a Broadcast address of all "don't cares". This effectively disables the Automatic Addressing mode and allows
the microcontroller to use standard 80C51-type UART drivers which do not make use of this feature.
Example: write an program that continually transmits characters from a transmit buffer. If incoming characters
are detected on the serial port, store them in the receive buffer starting at internal RAM location 50H. Assume that
the STC90C51RC/RD+ series MCU serial port has already been initialized in mode 1.
Solution:
TX:
RX:
0030H
R0,
R1,
RI,
#30H
#50H
RECEIVE
JB
LOOP:
ORG
MOV
MOV
JB
TI,
TX
SJMP
MOV
MOV
CPL
MOV
CLR
MOV
CLR
INC
CJNE
LOOP
A,
C,
C
ACC.7,
TI
SBUF,
ACC.7
R0
R0,
MOV
SJMP
CLR
MOV
MOV
CPL
CLR
MOV
INC
SJMP
END
R0,
LOOP
RI
A,
C,
C
ACC.7
@R1,
R1
LOOP
STC MCU Limited.
@R0
P
C
A
#50H,
#30H
SBUF
P
A
LOOP
;pointer for tx buffer
;pointer for rx buffer
;character received?
;yes: process it
;previous character transmitted ?
;yes: process it
;no: continue checking
;get character from tx buffer
;put parity bit in C
;change to odd parity
;add to character code
;clear transmit flag
;send character
;strip off parity bit
;point to next character in buffer
;end of buffer?
;no: continue
;yes: recycle
;continue checking
;clear receive flag
;read character into A
;for odd parity in A, P should be set
;complementing correctly indicates " error "
;strip off parity
;store received character in buffer
;point to next location in buffer
;continue checking
8.6 Buad Rates and Demo Program
The baud rate in Mode 0 is fixed:
SYSclk
12
The baud rate in Mode 2 depends on the value of bit SMOD in Special Function Register PCON. If SMOD =0
(which is the value on reset), the baud rate 1/64 the System clock cycle. If SMOD = 1, the baud rate is 1/32 the
System clock cycle .
2SMOD
×(SYSclk)
(SYSclk)
Mode 2 Baud Rate =
64
In the STC90xx series, the baud rates in Modes 1 and 3 are determined by Timer1 or Timer 2 overflow rate.
The baud rate in Mode 1 and 3 are fixed:
Mode 1,3 Baud rate = (2SMOD /32 ) x timer 1 overflow rate
= (2SMOD /32 ) x timer 2 overflow rate
Mode 0 Baud Rate =
Timer 1 overflow rate = (SYSclk/12)/(256 - TH1);
Timer 2 overflow rate = SYSclk/(65536-(RCAP2H,RCAP2L))
When Timer 1 is used as the baud rate generator, the Timer 1 interrupt should be disabled in this application.
The Timer itself can be configured for either "timer" or "cormter" operation, and in any of its 3 running modes.
In the most typcial applications, it is configured for "timer" operation, in the auto-reload mode (high nibble of
TMOD = 0010B).
One can achieve very low baud rate with Timer 1 by leaving the Timer 1 interrupt enabled, and configuring the
Timer to run as a 16-bit timer (high nibble of TMOD = 0001B), and using the Timer 1 interrupt to do a l6-bit
software reload.
The following figure lists various commonly used baud rates and how they can be obtained from Timer 1.
Baud Rate
fOSC
SMOD
Mode 0 MAX:1MHZ
Mode 2 MAX:375K
Mode 1,3:62.5K
19.2K
9.6K
4.8K
2.4K
1.2K
137.5
110
110
12MHZ
12MHZ
12MHZ
11.059MHZ
11.059MHZ
11.059MHZ
11.059MHZ
11.059MHZ
11.986MHZ
6MHZ
12MHZ
X
1
1
1
0
0
0
0
0
0
0
Timer 1
Reload
C/T Mode
Value
X
X
X
X
X
X
2
FFH
0
FDH
0
2
0
2
FDH
2
FAH
0
0
2
F4H
E8H
0
2
0
2
1DH
0
2
72H
0
1 FEEBH
Timer 1 Generated Commonly Used Baud Rates
STC MCU Limited.
When Timer 2 is used as the baud rate generator (either TCLK or RCLK in T2CON is '1'), the baud rate is as
follows,
SYSclk
2SMOD ×SYSclk
Mode 1,3 Baud rate =
32×(65536-(RCAP2H,RCAP2L))
65536-(RCAP2H,RCAP2L))
The following table lists various commonly used baud rates generated by Timer 2.
Baud Rate
12T mode 6T mode
375 000
750 000
9 600
19 200
2 800
9 600
2 400
4 800
1 200
2 400
300
600
110
220
300
600
110
220
STC MCU Limited.
System Clocks
/MHz
12
12
12
12
12
12
12
6
6
Timer 2
RCAP2H RCAP2L
FF
FF
FF
D9
FF
B2
FF
64
FE
C8
FB
1E
F2
AF
FD
8F
F9
57
8.7 Demo Program for UART (C and ASM)
1. C language code
/*-----------------------------------------------------------------------------*/
/* --- STC MCU International Limited ---------------------------------*/
/* --- STC89-90xx Series MCU UART (8-bit/9-bit)Demo ----------*/
/* If you want to use the program or the program referenced in the */
/* article, please specify in which data and procedures from STC */
/*-------------------------------------------------------------------------------*/
#include " reg51.h "
#include " intrins.h "
typedef unsigned char BYTE;
typedef unsigned int WORD;
#define FOSC 18432000L
#define BAUD 9600
//System frequency
//UART baudrate
/*Define UART parity mode*/
#define NONE_PARITY
0
#define ODD_PARITY
1
#define EVEN_PARITY
2
#define MARK_PARITY
3
#define SPACE_PARITY
4
//None parity
//Odd parity
//Even parity
//Mark parity
//Space parity
#define PARITYBIT EVEN_PARITY
//Testing even parity
sbit bit9 = P2^2;
bit busy;
//P2.2 show UART data bit9
void SendData(BYTE dat);
void SendString(char *s);
void main()
{
#if (PARITYBIT == NONE_PARITY)
SCON = 0x50;
//8-bit variable UART
#elif (PARITYBIT == ODD_PARITY) || (PARITYBIT == EVEN_PARITY) || (PARITYBIT == MARK_PARITY)
SCON = 0xda;
//9-bit variable UART, parity bit initial to 1
#elif (PARITYBIT == SPACE_PARITY)
SCON = 0xd2;
//9-bit variable UART, parity bit initial to 0
#endif
STC MCU Limited.
TMOD = 0x20;
TH1 = TL1 = -(FOSC/12/32/BAUD);
TR1 = 1;
ES = 1;
EA = 1;
//Set Timer1 as 8-bit auto reload mode
//Set auto-reload vaule
//Timer1 start run
//Enable UART interrupt
//Open master interrupt switch
SendString( " STC90-90xx\r\nUart Test !\r\n " );
while(1);
}
/*---------------------------UART interrupt service routine
----------------------------*/
void Uart_Isr() interrupt 4 using 1
{
if (RI)
{
RI = 0;
P0 = SBUF;
bit9 = RB8;
}
if (TI)
{
TI = 0;
busy = 0;
}
}
//Clear receive interrupt flag
//P0 show UART data
//P2.2 show parity bit
/*---------------------------Send a byte data to UART
Input: dat (data to be sent)
Output:None
----------------------------*/
void SendData(BYTE dat)
{
while (busy);
ACC = dat;
if (P)
{
#if (PARITYBIT == ODD_PARITY)
TB8 = 0;
#elif (PARITYBIT == EVEN_PARITY)
TB8 = 1;
#endif
}
//Wait for the completion of the previous data is sent
//Calculate the even parity bit P (PSW.0)
//Set the parity bit according to P
STC MCU Limited.
//Clear transmit interrupt flag
//Clear transmit busy flag
//Set parity bit to 0
//Set parity bit to 1
else
{
#if (PARITYBIT == ODD_PARITY)
TB8 = 1;
//Set parity bit to 1
#elif (PARITYBIT == EVEN_PARITY)
TB8 = 0;
//Set parity bit to 0
#endif
}
busy = 1;
SBUF = ACC;
//Send data to UART buffer
}
/*---------------------------Send a string to UART
Input: s (address of string)
Output:None
----------------------------*/
void SendString(char *s)
{
while (*s)
{
SendData(*s++);
}
}
STC MCU Limited.
//Check the end of the string
//Send current char and increment string ptr
2. Assembly program:
/*-------------------------------------------------------------------------------*/
/* --- STC MCU International Limited -----------------------------------*/
/* --- STC90xx Series MCU UART (8-bit/9-bit)Demo ----------------*/
/* If you want to use the program or the program referenced in the */
/* article, please specify in which data and procedures from STC */
/*-------------------------------------------------------------------------------*/
;/*Define UART parity mode*/
#define NONE_PARITY
0
#define ODD_PARITY
1
#define EVEN_PARITY
2
#define MARK_PARITY
3
#define SPACE_PARITY
4
#define PARITYBIT EVEN_PARITY
;----------------------------------------BUSY BIT
20H.0
;----------------------------------------ORG
0000H
LJMP
MAIN
//None parity
//Odd parity
//Even parity
//Mark parity
//Space parity
//Testing even parity
;transmit busy flag
ORG
0023H
LJMP
UART_ISR
;----------------------------------------ORG
0100H
MAIN:
CLR
BUSY
CLR
EA
MOV
SP,
#3FH
#if (PARITYBIT == NONE_PARITY)
MOV
SCON, #50H
;8-bit variable UART
#elif (PARITYBIT == ODD_PARITY) || (PARITYBIT == EVEN_PARITY) || (PARITYBIT == MARK_PARITY)
MOV
SCON, #0DAH
;9-bit variable UART, parity bit initial to 1
#elif (PARITYBIT == SPACE_PARITY)
MOV
SCON, #0D2H
;9-bit variable UART, parity bit initial to 0
#endif
;-------------------------------
STC MCU Limited.
MOV
TMOD, #20H
MOV
A,
#0FBH
MOV
TH1,
A
MOV
TL1,
A
SETB
TR1
SETB
ES
SETB
EA
;------------------------------MOV
DPTR, #TESTSTR
LCALL SENDSTRING
;------------------------------SJMP
$
;----------------------------------------TESTSTR:
DB " STC90-90xx Uart Test ! " ,0DH,0AH,0
;/*---------------------------;UART2 interrupt service routine
;----------------------------*/
UART_ISR:
PUSH ACC
PUSH PSW
JNB
RI,
CHECKTI
CLR
RI
MOV
P0,
SBUF
MOV
C,
RB8
MOV
P2.2,
C
CHECKTI:
JNB
TI,
ISR_EXIT
CLR
TI
CLR
BUSY
ISR_EXIT:
POP
PSW
POP
ACC
RETI
;/*---------------------------;Send a byte data to UART
;Input: ACC (data to be sent)
;Output:None
;----------------------------*/
STC MCU Limited.
;Set Timer1 as 8-bit auto reload mode
;256-18432000/12/32/9600
;Set auto-reload vaule
;Timer1 start run
;Enable UART interrupt
;Open master interrupt switch
;Load string address to DPTR
;Send string
;Test string
;Check RI bit
;Clear RI bit
;P0 show UART data
;P2.2 show parity bit
;Check S2TI bit
;Clear S2TI bit
;Clear transmit busy flag
SENDDATA:
JB
BUSY, $
MOV
ACC,
A
JNB
P,
EVEN1INACC
ODD1INACC:
#if (PARITYBIT == ODD_PARITY)
CLR
TB8
#elif (PARITYBIT == EVEN_PARITY)
SETB
TB8
#endif
SJMP
PARITYBITOK
EVEN1INACC:
#if (PARITYBIT == ODD_PARITY)
SETB
TB8
#elif (PARITYBIT == EVEN_PARITY)
CLR
TB8
#endif
PARITYBITOK:
SETB
BUSY
MOV
SBUF, A
RET
;/*---------------------------;Send a string to UART
;Input: DPTR (address of string)
;Output:None
;----------------------------*/
SENDSTRING:
CLR
A
MOVC A,
@A+DPTR
JZ
STRINGEND
INC
DPTR
LCALL SENDDATA
SJMP
SENDSTRING
STRINGEND:
RET
;----------------------------------------END
STC MCU Limited.
;Wait for the completion of the previous data is sent
;Calculate the even parity bit P (PSW.0)
;Set the parity bit according to P
;Set parity bit to 0
;Set parity bit to 1
;Set parity bit to 1
;Set parity bit to 0
;Parity bit set completed
;Send data to UART buffer
;Get current char
;Check the end of the string
;increment string ptr
;Send current char
;Check next
Chapter 9. IAP / EEPROM
The ISP in STC90xx series makes it possible to update the user's application program and non-volatile application
data (in IAP-memory) without removing the MCU chip from the actual end product. This useful capability makes
a wide range of field-update applications possible. (Note ISP needs the loader program pre-programmed in the
ISP-memory.) In general, the user needn't know how ISP operates because STC has provided the standard ISP
tool and embedded ISP code in STC shipped samples. But, to develop a good program for ISP function, the user
has to understand the architecture of the embedded flash.
The embedded flash consists of 90(max) pages. Each page contains 512 bytes. Dealing with flash, the user must
erase it in page unit before writting (programming) data into it.
Erasing flash means setting the content of that flash as FFH. Two erase modes are available in this chip. One is
mass mode and the other is page mode. The mass mode gets more performance, but it erases the entire flash. The
page mode is something performance less, but it is flexible since it erases flash in page unit. Unlike RAM's realtime operation, to erase flash or to write (program) flash often takes long time so to wait finish.
Furthermore,it is a quite complex timing procedure to erase/program flash. Fortunately, the STC90xx carried
with convenient mechanism to help the user read/change the flash content. Just filling the target address and data
into several SFR, and triggering the built-in ISP automation, the user can easily erase, read, and program the
embedded flash and option registers.
The In-Application Program feature is designed for user to Read/Write nonvolatile data flash. It may bring great
help to store parameters those should be independent of power-up and power-done action. In other words, the user
can store data in data flash memory, and after he shutting down the MCU and rebooting the MCU, he can get the
original value, which he had stored in.
The user can program the data flash according to the same way as ISP program, so he should get deeper understanding related to SFR ISP_DATA, ISP_ADDRL, ISP_ADDRH, ISP_CMD, ISP_TRIG, and ISP_CONTR.
STC MCU Limited.
9.1 IAP / EEPROM Special Function Registers
The following special function registers are related to the IAP/ISP/EEPROM operation. All these
registers can be accessed by software in the user's application program.
Symbol
Description
Value after
Power-on or
LSB
Reset
Bit Address and Symbol
Address
MSB
ISP_DATA
ISP_ADDRH
ISP_ADDRL
ISP_CMD
ISP_TRIG
ISP_CONTR
ISP/IAP Flash Data
Register
ISP/IAP Flash
Address High
ISP/IAP Flash
Address Low
ISP/IAP Flash
Command Register
ISP/IAP Flash
Command Trigger
ISP/IAP Control
Register
E2H
1111 1111B
E3H
0000 0000B
E4H
0000 0000B
E5H
-
-
-
-
-
MS2
MS1
MS0
E6H
E7H
xxxx x000B
xxxx xxxxB
ISPEN
SWBS SWRST
-
-
WT2
WT1
WT0
000x x000B
1. ISP/IAP Flash Data Register : ISP_DATA (Address: E2H, Non bit-addressable)
ISP_DATA is the data port register for ISP/IAP operation. The data in ISP_DATA will be written into
the desired address in operating ISP/IAP write and it is the data window of readout in operating ISP/
IAP read.
2. ISP/IAP Flash Address Registers : ISP_ADDRH and ISP_ADDRL
ISP_ADDRH, which address is E3H, is the high-byte address port for all ISP/IAP modes.
ISP_ADDRH[7:5] must be cleared to 000, if one bit of ISP_ADDRH[7:5] is set, the IAP/ISP write
function must fail.
ISP_ADDRL, which address is E4H, is the low port for all ISP/IAP modes. In page erase operation, it
is ignored.
STC MCU Limited.
3. ISP/IAP Flash Command Register : ISP_CMD (Non bit -addressable)
SFR name
Address
bit
B7
B6
B5
B4
B3
B2
B1
B0
ISP_CMD
E5H
name
-
-
-
-
-
MS2
MS1
MS0
B7~B2: Reserved.
MS2, MS1, MS0 : ISP/IAP operating mode selection. ISP_CMD is used to select the flash mode for
performing numerous ISP/IAP function or used to access protected SFRs.
0, 0, 0 : Standby
0, 0, 1 : Data Flash/EEPROM read.
0, 1, 0 : Data Flash/EEPROM program.
0, 1, 1 : Data Flash/EEPROM page erase.
4. ISP/IAP Flash Command Trigger Register : ISP_TRIG (Address: E6H, Non bit -addressable)
ISP_TRIG is the command port for triggering ISP/IAP activity and protected SFRs access. If ISP_TRIG is filled
with sequential 0x46h, 0xB9h and if ISPEN(ISP_CONTR.7) = 1, ISP/IAP activity or protected SFRs access will
triggered.
5. ISP/IAP Control Register : ISP_CONTR (Non bit-addressable)
SFR name
Address
IAP_CONTR
E7H
bit
B7
B6
B5
name ISPEN SWBS SWRST
B4
B3
B2
B1
B0
-
-
WT2
WT2
WT0
ISPEN : ISP/IAP operation enable.
0 : Global disable all ISP/IAP program/erase/read function.
1 : Enable ISP/IAP program/erase/read function.
SWBS: software boot selection control.
0 : Boot from main-memory after reset.
1 : Boot from ISP memory after reset.
SWRST: software reset trigger control.
0 : No operation
1 : Generate software system reset. It will be cleared by hardware automatically.
B3: Reserved. Software must write "0" on this bit when IAP_CONTR is written.
WT2~WT0 : Waiting time selection while flash is busy.
Setting wait times
WT2 WT1 WT0
0
0
0
0
1
1
0
0
1
0
1
0
Read
6 SYSclks
11 SYSclks
22 SYSclks
43 SYSclks
Program
(=72uS)
30 SYSclks
60 SYSclks
120 SYSclks
240 SYSclks
CPU wait times
Sector Erase
Recommended System
(=13.1304mS) Clock Frequency (MHz)
5471 SYSclks
5MHz
10942 SYSclks
10MHz
21885 SYSclks
20MHz
43769 SYSclks
40MHz
Note: Software reset actions could reset other SFR,but it never influences bits ISPEN and SWBS.The ISPEN and
SWBS. The ISPEN and SWBS only will be reset by power-up action, while not software reset.
STC MCU Limited.
9.2 STC90C51RC/RD+ series Internal EEPROM Allocation Table
STC90C51RC/RD+ series microcontroller's Data Flash (internal available EEPROM) address (and program space
is separate) : if the application area of IAP write Data/erase sector of the action, the statements will be ignore
and continue to the next one. Program in user application area (AP area), only operate IAP/ISP on Data Flash
(EEPROM )
STC90C51RC/RD+/AD/PWM series MCU internal EEPROM Selection Table
EEPROM
(Byte)
Type
STC90C51RC
STC90LE51RC
STC90C52RC
STC90LE52RC
STC90C12RC
STC90LE12RC
STC90C54RD+
STC90LE54RD+
STC90C58RD+
STC90LE58RD+
STC90C510RD+
STC90LE510RD+
STC90C512RD+
STC90LE512RD+
STC90C514RD+
STC90LE514RD+
Sector
Numbers
Begin_Sector
Begin_Address
End_Sector
End_Address
9K
18
1000h
33FFh
5K
10
2000h
33FFh
1K
2
3000h
33FFh
45K
90
4000h
F3FFh
29K
58
8000h
F3FFh
21K
42
A000h
F3FFh
13K
26
C000h
F3FFh
5K
10
E000h
F3FFh
STC MCU Limited.
STC90C58RD+ address reference table in detail (512 bytes per sector)
STC90LE58RD+ address reference table in detail (512 bytes per sector)
Sector 1
Sector 2
Sector 3
Sector 4
Start
End
Start
End
Start
End
Start
End
8000H
81FFH
8200H
83FFH
8400H
85FFH
8600H
87FFH
Sector 5
Sector 6
Sector7
Sector 8
Start
End
Start
End
Start
End
Start
End
8800H
89FFH
8A00H
8BFFH
8C00H
8DFFH
8E00H
8FFFH
Sector 9
Sector 10
Sector 11
Sector 12
Start
End
Start
End
Start
End
Start
End
9000H
91FFH
9200H
93FFH
9400H
95FFH
9600H
97FFH
Sector 13
Sector 14
Sector 15
Sector 16
Start
End
Start
End
Start
End
Start
End
9800H
99FFH
9A00H
9BFFH 9C000H 9DFFH
9E00H
9FFFH
Sector 17
Sector 18
Sector 19
Sector 20
Start
End
Start
End
Start
End
Start
End
A000H
A1FFH
A200H
A3FFH
A400H
A5FFH
A600H
A7FFH
Sector 21
Sector 22
Sector 23
Sector 24
Each sector 512 byte
Start
End
Start
End
Start
End
Start
End
A800H
A9FFH AA00H ABFFH AC00H
ADFFH
AE00H AFFFH
Sector 28
Sector 25
Sector 26
Sector 27
Start
End
Start
End
Start
End
Start
End
B000H
B1FFH
B200H
B3FFH
B400H
B5FFH
B600H
B7FFH
Suggest the same
Sector 29
Sector 30
Sector 31
Sector 32
Start
End
Start
End
Start
End
Start
End times modified data
B800H
B9FFH BA00H BBFFH
BC00H
BDFFH
BE00H
BFFFH in the same sector,
Sector 33
Sector 34
Sector 35
Sector 36
each times modified
Start
End
Start
End
Start
End
Start
End d a t a i n d i ff e r e n t
C000H
C1FFH
C200H
C3FFH
C400H
C5FFH
C600H
C7FFH
sectors, don't have to
Sector 37
Sector 38
Sector 39
Sector 40
Start
End
Start
End
Start
End
Start
End use full, of course, it
C800H
C9FFH CA00H CBFFH
CC00H
CDFFH
CE00H
CFFFH was all to use
Sector 41
Sector 42
Sector 43
Sector 44
Start
End
Start
End
Start
End
Start
End
D000H
D1FFH
D200H
D3FFH
D400H
D5FFH
D600H
D7FFH
Sector 45
Sector 46
Sector 47
Sector 48
Start
End
Start
End
Start
End
Start
End
D800H
D9FFH DA00H DBFFH DC00H
DDFFH
DE00H DFFFH
Sector 49
Sector 50
Sector 51
Sector 52
Start
End
Start
End
Start
End
Start
End
E5FFH
E600H
E7FFH
E000H
E1FFH
E200H
E3FFH
E400H
Sector 53
Sector 54
Sector 55
Sector 56
Start
End
Start
End
Start
End
Start
End
E800H
E9FFH
EA00H EBFFH
EC00H
EDFFH
EE00H
EFFFH
Sector 57
Sector 58
Start
End
Start
End
F000H
F1FFH
F200H
F3FFH
STC MCU Limited.
9.3 IAP/EEPROM Assembly Language Program Introduction
; /*It is decided by the assembler/compiler used by users that whether the SFRs addresses are declared by the
DATA or the EQU directive*/
ISP_DATA
DATA 0E2H
or
ISP_DATA
EQU
0E2H
ISP_ADDRH
DATA 0E3H
or
ISP_ADDRH
EQU
0E3H
ISP_ADDRL
DATA 0E4H
or
ISP_ADDRL
EQU
0E4H
ISP_CMD
DATA 0E5H
or
ISP_CMD
EQU
0E5H
ISP_TRIG
DATA 0E6H
or
ISP_TRIG
EQU
0E6H
ISP_CONTR
DATA 0E7H
or
ISP_CONTR
EQU
0E7H
;/*Define ISP/IAP/EEPROM command and wait time*/
ISP_IAP_BYTE_READ
EQU
ISP_IAP_BYTE_PROGRAM
EQU
ISP_IAP_SECTOR_ERASE
EQU
WAIT_TIME
EQU
;/*Byte-Read*/
MOV
MOV
MOV
ORL
MOV
MOV
MOV
NOP
MOV
1
2
3
0
;Byte-Read
;Byte-Program
;Sector-Erase
;Set wait time
ISP_ADDRH,
ISP_ADDRL,
ISP_CONTR,
ISP_CONTR,
ISP_CMD,
ISP_TRIG,
IsP_TRIG,
A,
#BYTE_ADDR_HIGH
;Set ISP/IAP/EEPROM address high
#BYTE_ADDR_LOW
;Set ISP/IAP/EEPROM address low
#WAIT_TIME
;Set wait time
#10000000B
;Open ISP/IAP function
#ISP_IAP_BYTE_READ
;Set ISP/IAP Byte-Read command
#46H
;Send trigger command1 (0x46)
#0B9H
;Send trigger command2 (0xb9)
;CPU will hold here until ISP/IAP/EEPROM operation complete
ISP_DATA
;Read ISP/IAP/EEPROM data
;/*Disable ISP/IAP/EEPROM function, make MCU in a safe state*/
MOV
ISP_CONTR,
#00000000B
;Close ISP/IAP/EEPROM function
MOV
ISP_CMD,
#00000000B
;Clear ISP/IAP/EEPROM command
;MOV ISP_TRIG,
#00000000B
;Clear trigger register to prevent mistrigger
;MOV ISP_ADDRH,
#0
;Set address high(00h), Data ptr point to non-EEPROM area
;MOV ISP_ADDRL,
#0
;Clear IAP address to prevent misuse
SETB
EA
;Set global enable bit
;/*Byte-Program, if the byte is null(0FFH), it can be programmed; else, MCU must operate Sector-Erase firstly,
and then can operate Byte-Program.*/
MOV
ISP_DATA,
#ONE_DATA
;Write ISP/IAP/EEPROM data
MOV
ISP_ADDRH,
#BYTE_ADDR_HIGH
;Set ISP/IAP/EEPROM address high
MOV
ISP_ADDRL,
#BYTE_ADDR_LOW
;Set ISP/IAP/EEPROM address low
MOV
ISP_CONTR,
#WAIT_TIME
;Set wait time
ORL
ISP_CONTR,
#10000000B
;Open ISP/IAP function
MOV
ISP_CMD,
#ISP_IAP_BYTE_READ
;Set ISP/IAP Byte-Read command
MOV
ISP_TRIG,
#46H
;Send trigger command1 (0x46)
MOV
ISP_TRIG,
#0B9H
;Send trigger command2 (0xb9)
NOP
;CPU will hold here until ISP/IAP/EEPROM operation complete
STC MCU Limited.
;/*Disable ISP/IAP/EEPROM function, make MCU in a safe state*/
MOV
ISP_CONTR,
#00000000B
;Close ISP/IAP/EEPROM function
MOV
ISP_CMD,
#00000000B
;Clear ISP/IAP/EEPROM command
;MOV ISP_TRIG,
#00000000B
;Clear trigger register to prevent mistrigger
;MOV ISP_ADDRH,
#0
;Set address high(00h), Data ptr point to non-EEPROM area
;MOV ISP_ADDRL,
#0
;Clear IAP address to prevent misuse
SETB
EA
;Set global enable bit
;/*Erase one sector area, there is only Sector-Erase instead of Byte-Erase, every sector area account for 512
bytes*/
MOV
ISP_ADDRH,
#SECTOT_FIRST_BYTE_ADDR_HIGH
;Set the sector area starting address high
MOV
ISP_ADDRL,
#SECTOT_FIRST_BYTE_ADDR_LOW
;Set the sector area starting address low
MOV
ISP_CONTR,
#WAIT_TIME
;Set wait time
ORL
ISP_CONTR,
#10000000B
;Open ISP/IAP function
MOV
ISP_CMD,
#ISP_IAP_SECTOR_ERASE
;Set Sectot-Erase command
MOV
ISP_TRIG,
#46H
;Send trigger command1 (0x46)
MOV
ISP_TRIG,
#0B9H
;Send trigger command2 (0xb9)
NOP
;CPU will hold here until ISP/IAP/EEPROM operation complete
;/*Disable ISP/IAP/EEPROM function, make MCU in a safe state*/
MOV
ISP_CONTR,
#00000000B
;Close ISP/IAP/EEPROM function
MOV
ISP_CMD,
#00000000B
;Clear ISP/IAP/EEPROM command
;MOV ISP_TRIG,
#00000000B
;Clear trigger register to prevent mistrigger
;MOV ISP_ADDRH,
#0
;Set address high(00h), Data ptr point to non-EEPROM area
;MOV ISP_ADDRL,
#0
;Clear IAP address to prevent misuse
STC MCU Limited.
Little common sense: (STC MCU Data Flash use as EEPROM function)
Three basic commands -- bytes read, byte programming, the sector erased
Byte programming: " 1 " write " 1 " or " 0 " , will " 0 " write " 0 " .Just FFH can byte programming. If the byte not FFH,
you must erase the sector , because only the " sectors erased " to put " 0 " into " 1 " .
Sector erased: only " sector erased " will also be a " 0 " erased for " 1 " .
Big proposal:
1. The same times modified data in the same sector, not the same times modified data in other sectors, won't have
to read protection.
2. If a sector with only one byte, that's real EEPROM, STC MCU Data Flash faster than external EEPROM, read
a byte/many one byte programming is about 10uS/ 60uS / 10mS.
3. If in a sector of storing a large amounts of data, a only need to modify one part of a byte, or when the other
byte don't need to modify data must first read on STC MCU, then erased RAM the whole sector, again will need
to keep data and need to amend data in bytes written back to this sector section literally only bytes written orders
(without continuous bytes, write command). Then each sector use bytes are using the less the convenient (not
need read a lot of maintained data).
Frequently asked questions:
1. IAP instructions after finishing, address is automatically " add 1 " or " minus 1 " ?
Answer: not
2. Send 46 and B9 after IAP ordered the trigger whether to have sent 46 and B9 trigger?
Answer: yes
STC MCU Limited.
9.4 EEPROM Demo Program (C and ASM)
1. C Code Listing
/*-------------------------------------------------------------------------------*/
/* --- STC MCU International Limited ----------------------------------*/
/* --- STC90xx Series MCU ISP/IAP/EEPROM Demo ----------------*/
/* If you want to use the program or the program referenced in the */
/* article, please specify in which data and procedures from STC */
/*-------------------------------------------------------------------------------*/
#include " reg51.h "
#include " intrins.h "
typedef unsigned char BYTE;
typedef unsigned int WORD;
/*Declare SFR associated with the IAP */
sfr IAP_DATA
= 0xE2;
//Flash data register
sfr IAP_ADDRH = 0xE3;
//Flash address HIGH
sfr IAP_ADDRL = 0xE4;
//Flash address LOW
sfr IAP_CMD
= 0xE5;
//Flash command register
sfr IAP_TRIG
= 0xE6;
//Flash command trigger
sfr IAP_CONTR = 0xE7;
//Flash control register
/*Define ISP/IAP/EEPROM command*/
#define CMD_IDLE 0
//Stand-By
#define CMD_READ 1
//Byte-Read
#define CMD_PROGRAM 2
//Byte-Program
#define CMD_ERASE 3
//Sector-Erase
/*Define ISP/IAP/EEPROM operation const for IAP_CONTR*/
//#define ENABLE_IAP 0x80
//if SYSCLK & lt; 40MHz
#define ENABLE_IAP 0x81
//if SYSCLK & lt; 20MHz
//#define ENABLE_IAP x82
//if SYSCLK & lt; 10MHz
//#define ENABLE_IAP 0x83
//if SYSCLK & lt; 5MHz
//Start address for STC90C58xx EEPROM
#define IAP_ADDRESS 0x08000
void Delay(BYTE n);
void IapIdle();
BYTE IapReadByte(WORD addr);
void IapProgramByte(WORD addr, BYTE dat);
void IapEraseSector(WORD addr);
STC MCU Limited.
void main()
{
WORD i;
P1 = 0xfe;
//1111,1110 System Reset OK
Delay(10);
//Delay
IapEraseSector(IAP_ADDRESS); //Erase current sector
for (i=0; i & lt; 512; i++)
//Check whether all sector data is FF
{
if (IapReadByte(IAP_ADDRESS+i) != 0xff)
goto Error;
//If error, break
}
P1 = 0xfc;
//1111,1100 Erase successful
Delay(10);
//Delay
for (i=0; i & lt; 512; i++)
//Program 512 bytes data into data flash
{
IapProgramByte(IAP_ADDRESS+i, (BYTE)i);
}
P1 = 0xf8;
//1111,1000 Program successful
Delay(10);
//Delay
for (i=0; i & lt; 512; i++)
//Verify 512 bytes data
{
if (IapReadByte(IAP_ADDRESS+i) != (BYTE)i)
goto Error;
//If error, break
}
P1 = 0xf0;
//1111,0000 Verify successful
while (1);
Error:
P1 & = 0x7f;
//0xxx,xxxx IAP operation fail
while (1);
}
/*---------------------------Software delay function
----------------------------*/
void Delay(BYTE n)
{
WORD x;
while (n--)
{
x = 0;
while (++x);
}
}
STC MCU Limited.
/*---------------------------Disable ISP/IAP/EEPROM function
Make MCU in a safe state
----------------------------*/
void IapIdle()
{
IAP_CONTR = 0;
IAP_CMD = 0;
IAP_TRIG = 0;
IAP_ADDRH = 0x80;
IAP_ADDRL = 0;
}
//Close IAP function
//Clear command to standby
//Clear trigger register
//Data ptr point to non-EEPROM area
//Clear IAP address to prevent misuse
/*---------------------------Read one byte from ISP/IAP/EEPROM area
Input: addr (ISP/IAP/EEPROM address)
Output:Flash data
----------------------------*/
BYTE IapReadByte(WORD addr)
{
BYTE dat;
IAP_CONTR = ENABLE_IAP;
IAP_CMD = CMD_READ;
IAP_ADDRL = addr;
IAP_ADDRH = addr & gt; & gt; 8;
IAP_TRIG = 0x46;
IAP_TRIG = 0xb9;
_nop_();
dat = IAP_DATA;
IapIdle();
//Open IAP function, and set wait time
//Set ISP/IAP/EEPROM READ command
//Set ISP/IAP/EEPROM address low
//Set ISP/IAP/EEPROM address high
//Send trigger command1 (0x46)
//Send trigger command2 (0xb9)
//MCU will hold here until ISP/IAP/EEPROM operation complete
//Read ISP/IAP/EEPROM data
//Close ISP/IAP/EEPROM function
return dat;
}
/*---------------------------Program one byte to ISP/IAP/EEPROM area
Input: addr (ISP/IAP/EEPROM address)
dat (ISP/IAP/EEPROM data)
Output:----------------------------*/
STC MCU Limited.
//Data buffer
//Return Flash data
void IapProgramByte(WORD addr, BYTE dat)
{
IAP_CONTR = ENABLE_IAP;
//Open IAP function, and set wait time
IAP_CMD = CMD_PROGRAM;
//Set ISP/IAP/EEPROM PROGRAM command
IAP_ADDRL = addr;
//Set ISP/IAP/EEPROM address low
IAP_ADDRH = addr & gt; & gt; 8;
//Set ISP/IAP/EEPROM address high
IAP_DATA = dat;
//Write ISP/IAP/EEPROM data
IAP_TRIG = 0x46;
//Send trigger command1 (0x46)
IAP_TRIG = 0xb9;
//Send trigger command2 (0xb9)
_nop_();
//MCU will hold here until ISP/IAP/EEPROM operation complete
IapIdle();
}
/*---------------------------Erase one sector area
Input: addr (ISP/IAP/EEPROM address)
Output:----------------------------*/
void IapEraseSector(WORD addr)
{
IAP_CONTR = ENABLE_IAP;
//Open IAP function, and set wait time
IAP_CMD = CMD_ERASE;
//Set ISP/IAP/EEPROM ERASE command
IAP_ADDRL = addr;
//Set ISP/IAP/EEPROM address low
IAP_ADDRH = addr & gt; & gt; 8;
//Set ISP/IAP/EEPROM address high
IAP_TRIG = 0x46;
//Send trigger command1 (0x46)
IAP_TRIG = 0xb9;
//Send trigger command2 (0xb9)
_nop_();
//MCU will hold here until ISP/IAP/EEPROM operation complete
IapIdle();
}
STC MCU Limited.
2. Assembly Code Listing
;/*--------------------------------------------------------------------------------*/
;/* --- STC MCU International Limited -----------------------------------*/
;/* --- STC90xx Series MCU ISP/IAP/EEPROM Demo -----------------*/
;/* If you want to use the program or the program referenced in the */
;/* article, please specify in which data and procedures from STC */
;/*------------------------------------------------------------------------------*/
;/*Declare SFR associated with the IAP */
IAP_DATA EQU 0E2H
;Flash data register
IAP_ADDRH EQU 0E3H
;Flash address HIGH
IAP_ADDRL EQU 0E4H
;Flash address LOW
IAP_CMD EQU 0E5H
;Flash command register
IAP_TRIG EQU 0E6H
;Flash command trigger
IAP_CONTR EQU 0E7H
;Flash control register
;/*Define ISP/IAP/EEPROM command*/
CMD_IDLE EQU 0
;Stand-By
CMD_READ EQU 1
;Byte-Read
CMD_PROGRAM EQU 2
;Byte-Program
CMD_ERASE EQU 3
;Sector-Erase
;/*Define ISP/IAP/EEPROM operation const for IAP_CONTR*/
;ENABLE_IAP EQU 80H
;if SYSCLK & lt; 40MHz
ENABLE_IAP EQU 81H
;if SYSCLK & lt; 20MHz
;ENABLE_IAP EQU 82H
;if SYSCLK & lt; 10MHz
;ENABLE_IAP EQU 83H
;if SYSCLK & lt; 5MHz
;//Start address for STC90C58xx EEPROM
IAP_ADDRESS EQU 08000H
;----------------------------------------ORG 0000H
LJMP MAIN
;----------------------------------------ORG 0100H
MAIN:
MOV P1,#0FEH
LCALL DELAY
STC MCU Limited.
;1111,1110 System Reset OK
;Delay
;------------------------------MOV
DPTR, #IAP_ADDRESS
LCALL IAP_ERASE
;------------------------------MOV
DPTR, #IAP_ADDRESS
MOV
R0,
#0
MOV
R1,
#2
CHECK1:
LCALL IAP_READ
CJNE
A,
#0FFH, ERROR
INC
DPTR
DJNZ
R0,
CHECK1
DJNZ
R1,
CHECK1
;------------------------------MOV
P1,
#0FCH
LCALL DELAY
;------------------------------MOV
DPTR, #IAP_ADDRESS
MOV
R0,
#0
MOV
R1,
#2
MOV
R2,
#0
NEXT:
MOV
A,
R2
LCALL IAP_PROGRAM
INC
DPTR
INC
R2
DJNZ
R0,
NEXT
DJNZ
R1,
NEXT
;------------------------------MOV
P1,
#0F8H
LCALL DELAY
;------------------------------MOV
DPTR, #IAP_ADDRESS
MOV
R0,
#0
MOV
R1,
#2
MOV
R2,
#0
CHECK2:
LCALL IAP_READ
CJNE
A,2,ERROR
INC
DPTR
INC
R2
DJNZ
R0,
CHECK2
DJNZ
R1,
CHECK2
STC MCU Limited.
;Set ISP/IAP/EEPROM address
;Erase current sector
;Set ISP/IAP/EEPROM address
;Set counter (512)
;Check whether all sector data is FF
;Read Flash
;If error, break
;Inc Flash address
;Check next
;Check next
;1111,1100 Erase successful
;Delay
;Set ISP/IAP/EEPROM address
;Set counter (512)
;Initial test data
;Program 512 bytes data into data flash
;Ready IAP data
;Program flash
;Inc Flash address
;Modify test data
;Program next
;Program next
;1111,1000 Program successful
;Delay
;Set ISP/IAP/EEPROM address
;Set counter (512)
;Verify 512 bytes data
;Read Flash
;If error, break
;Inc Flash address
;Modify verify data
;Check next
;Check next
;------------------------------MOV
P1,
SJMP
$
;------------------------------ERROR:
MOV
P0,
MOV
P2,
MOV
P3,
CLR
P1.7
SJMP
$
;/*---------------------------;Software delay function
;----------------------------*/
DELAY:
CLR
A
MOV
R0,
MOV
R1,
MOV
R2,
DELAY1:
DJNZ
R0,
DJNZ
R1,
DJNZ
R2,
RET
#0F0H
;1111,0000 Verify successful
R0
R1
R2
;0xxx,xxxx IAP operation fail
A
A
#20H
DELAY1
DELAY1
DELAY1
;/*---------------------------;Disable ISP/IAP/EEPROM function
;Make MCU in a safe state
;----------------------------*/
IAP_IDLE:
MOV IAP_CONTR,
MOV IAP_CMD, #0
MOV IAP_TRIG, #0
MOV IAP_ADDRH,
MOV IAP_ADDRL,
RET
#0
#80H
#0
;/*---------------------------;Read one byte from ISP/IAP/EEPROM area
;Input: DPTR(ISP/IAP/EEPROM address)
;Output:ACC (Flash data)
;----------------------------*/
STC MCU Limited.
;Close IAP function
;Clear command to standby
;Clear trigger register
;Data ptr point to non-EEPROM area
;Clear IAP address to prevent misuse
IAP_READ:
MOV IAP_CONTR,
#ENABLE_IAP
;Open IAP function, and set wait time
MOV IAP_CMD,
#CMD_READ
;Set ISP/IAP/EEPROM READ command
MOV IAP_ADDRL,
DPL
;Set ISP/IAP/EEPROM address low
MOV IAP_ADDRH,
DPH
;Set ISP/IAP/EEPROM address high
MOV IAP_TRIG,
#46H
;Send trigger command1 (0x46)
MOV IAP_TRIG,
#0B9H
;Send trigger command2 (0xb9)
NOP
;MCU will hold here until ISP/IAP/EEPROM operation complete
MOV A,
IAP_DATA
;Read ISP/IAP/EEPROM data
LCALL IAP_IDLE
;Close ISP/IAP/EEPROM function
RET
;/*---------------------------;Program one byte to ISP/IAP/EEPROM area
;Input: DPAT(ISP/IAP/EEPROM address)
;
ACC (ISP/IAP/EEPROM data)
;Output:;----------------------------*/
IAP_PROGRAM:
MOV IAP_CONTR,
#ENABLE_IAP ;Open IAP function, and set wait time
MOV IAP_CMD, #CMD_PROGRAM
;Set ISP/IAP/EEPROM PROGRAM command
MOV IAP_ADDRL,
DPL
;Set ISP/IAP/EEPROM address low
MOV IAP_ADDRH,
DPH
;Set ISP/IAP/EEPROM address high
MOV IAP_DATA,
A
;Write ISP/IAP/EEPROM data
MOV IAP_TRIG, #46H
;Send trigger command1 (0x46)
MOV IAP_TRIG, #0B9H
;Send trigger command2 (0xb9)
NOP
;MCU will hold here until ISP/IAP/EEPROM operation complete
LCALL IAP_IDLE
;Close ISP/IAP/EEPROM function
RET
;/*---------------------------;Erase one sector area
;Input: DPTR(ISP/IAP/EEPROM address)
;Output:;----------------------------*/
IAP_ERASE:
MOV IAP_CONTR,
#ENABLE_IAP ;Open IAP function, and set wait time
MOV IAP_CMD, #CMD_ERASE
;Set ISP/IAP/EEPROM ERASE command
MOV IAP_ADDRL,
DPL
Set ISP/IAP/EEPROM address low
MOV IAP_ADDRH,
DPH
;Set ISP/IAP/EEPROM address high
MOV IAP_TRIG, #46H
;Send trigger command1 (0x46)
MOV IAP_TRIG, #0B9H
;Send trigger command2 (0xb9)
NOP
;MCU will hold here until ISP/IAP/EEPROM operation complete
LCALL IAP_IDLE
;Close ISP/IAP/EEPROM function
RET
END
STC MCU Limited.
Chapter 10. STC90 series programming tools usage
10.1 In-System-Programming (ISP) principle
If need download code into STC90C51RC/RD+ series, P1.0
and P1.1 pin must be connected to GND
If you chose the " Next program code, P1.0/1.1 need=0/0 "
option, then the next time you need to re-download the
program, first of all must be connected P1.0 and P1.1 to
GND
Power-on,reset
MCU frist running ISP monitor code
Detect whether there ia a
legitimate ISP command
NO
YES
Must be cold-reset (power-on reset),MCU will
run from ISP monitor code, for any warm-reset
(include reset-pin, watchdog), MCU will run user
code directly.
Wait ISP command for tens or hundreds
milliseconds, if no legitimate command, MCU
will reset to AP area.
Download user program to AP area.
Reset to AP area running user code
STC MCU Limited.
PC application must send command at
first then power on MCU
10.2 STC90C51RC/RD+ series application circuit for ISP
Vcc
STC3232,STC232,MAX232,SP232
Vcc 16
1 C1+
0.1?F
T1OUT 14
4 C2+
R1IN 13
5 C2-
Gnd
Gnd 15
3 C1-
Vcc
System Power/USB +5V
2
3
R1OUT 12
PC_RxD(COM Pin2)
5
Vin
2 V+
+
PC COM
PC_TxD(COM Pin3)
SW1
T1IN 11
6 V-
T2IN 10
7 T2OUT
R2OUT 9
8 R2IN
This part of the circuit
has nothing to do
with the downloads
Power On
STC90xx Series can directly
substitute STC89xx Series
Vcc
U1-P1.0
U1-P1.1
MCU-VCC
U1-P3.0
U1-P3.1
Gnd
1K
P1.2
P0.1 38
C6
P1.3
P0.2 37
104
5
P1.4
P0.3 36
6
P1.5
P0.4 35
7
P1.6
P0.5 34
8
P1.7
P0.6 33
9
MCU_RxD(P3.0)
P0.0 39
4
C1
Vcc 40
T2EX/P1.1
3
+
T2/P1.0
2
10?F
1
RST
P0.7 32
MCU_TxD(P3.1)
If the frequency of external clock is higher
than 33MHz, external active crystal
oscillator is recommended to use directly.
C2 & lt; 47pF
USB+5V T1OUT R1IN GND
X1
USB1
C1 & lt; 47pF
10 RxD/P3.0
EA/P4.6
31
11 TxD/P3.1
ALE/P4.5
30
12 INT0/P3.2
10K
R1
1K
PSEN/P4.4
29
13 INT1/P3.3
P2.7/A15
28
14 T0/P3.4
P2.6/A14
27
15 T1/P3.5
P2.5/A13
26
16 WR/P3.6
P2.4/A12
25
17 RD/P3.7
P2.3/A11
24
18 XTAL2
P2.2/A10
23
19 XTAL1
P2.1/A9
22
20 Gnd
P2.0/A8
21
1K
About reset circuit:
When the crystal frequency X1 is 4MHz, capacitors C2 and C3 should all be 100pF.
When the crystal frequency X1 is 6MHz, capacitors C2 and C3 should all be 47pF ~ 100pF.
When the crystal frequency X1 is 12~25MHz, capacitors C2 and C3 should all be 47pF.
1. When R/C reset, capacitor C1 is 10uF and resistor R1 isto 10K
2.RC/RD+ series HD version MCU, RESET pin is connected to internal pull-down resistor 45K-100K
STC MCU Limited.
+
C5
10?F
Users in their target system, such as the P3.0/P3.1 through the RS-232 level shifter connected to the computer
after the conversion of ordinary RS-232 serial port to connect the system programming / upgrading client
software. If the user panel recommended no RS-232 level converter, should lead to a socket, with Gnd/P3.1/
P3.0/Vcc four signal lines, so that the user system can be programmed directly. Of course, if the six signal lines
can lead to Gnd/P3.1/P3.0/Vcc/P1.1/P1.0 as well, because you can download the program by P1.0/P1.1 ISP ban.
If you can Gnd/P3.1/P3.0/Vcc/P1.1/P1.0/Reset seven signal lines leads to better, so you can easily use " offline
download board (no computer) " .
ISP programming on the Theory and Application Guide to see " STC90 Series MCU Development / Programming
Tools Help " section. In addition, we have standardized programming download tool, the user can then program
into the goal in the above systems, you can borrow on top of it RS-232 level shifter connected to the computer
to download the program used to do. Programming a chip roughly be a few seconds, faster than the ordinary
universal programmer much faster, there is no need to buy expensive third-party programmer?.
PC STC-ISP software downloaded from the website
STC MCU Limited.
10.3 PC side application usage
According to
actual situation,
the user selects
the appropriate
maximum baud
rate
In practice, if P3.0/
P3.1 already connected
to a RS232/RS485 or
other equipment, it
is recommended that
selection P1.0 / P1.1
= 0/0 can download
options
Press this button when
mass production
All new settings
are valid in the
next power-on.
Enable the option in
debugging stage
STC MCU Limited.
Step1 : Select MCU type (E.g. STC90C51RC)
Step2 : Load user program code (*.bin or *.hex)
Setp3 : Select the serial port you are using
Setp4 : Config the hardware option
Step5 : Press "ISP programming" or "Re-Programming" button to download user program
NOTE : Must press "ISP programming" or "Re-Programming" button first, then power on MCU, otherwise
will cannot download.
About hardware connection
1. MCU RXD (P3.0) ---- RS232 ---- PC COM port TXD (Pin3)
2. MCU TXD (P3.1) ---- RS232 ---- PC COM port RXD (Pin2)
3. MCU GNG-------PC COM port GND (Pin5)
4. RS232 : You can select STC232 / STC3232 / MAX232 / MAX3232 / ...
Using a demo board as a programmer
STC-ISP ver3.0A PCB can be welded into three kinds of circuits, respectively, support the STC's 16/20/28/32
pins MCU, the back plate of the download boards are affixed with labels,users need to pay special attention
to. All the download board is welded 40-pin socket, the socket's 20-pin is ground line, all types of MCU
should be put on the socket according to the way of alignment with the ground. The method of programming
user code using download board as follow:
1. According to the type of MCU choose supply voltage,
A. For 5V MCU, using jumper JP1 to connect MCU-VCC to +5V pin
B. For 3V MCU, using jumper JP1 to connect MCU-VCC to +3.3V pin
2. Download cable (Provide by STC)
A. Connect DB9 serial connector to the computer's RS-232 serial interface
B. Plug the USB interface at the same side into your computer's USB port for power supply
C. Connect the USB interface at the other side into STC download board
3. Other interfaces do not need to connect.
4. In a non-pressed state to SW1, and MCU-VCC power LED off.
5. For SW3
P1.0/P1.1 = 1/1 when SW3 is non-pressed
P1.0/P1.1 = 0/0 when SW3 is pressed
If you have select the "Next program code, P1.0/P1.1 Need = 0/0" option, then SW3 must be in a pressed
state
6. Put target MCU into the U1 socket, and locking socket
7. Press the "Download" button in the PC side application
8. Press SW1 switch in the download board
9. Close the demo board power supply and remove the MCU after download successfully.
STC MCU Limited.
10.4 Compiler / Assembler Programmer and Emulator
About Compiler/Assembler
Any traditional compiler / assembler and the popular Keil are suitable for STC MCU. For selection MCU
body, the traditional compiler / assembler, you can choose Intel's 8052 / 87C52 / 87C52 / 87C58 or Philips's
P87C52 / P87C54/P87C58 in the traditional environment, in Keil environment, you can choose the types in
front of the proposed or download the STC chips database file (STC.CDB) from the STC official website.
About Programmer
You can use the STC specific ISP programmer. (Can be purchased from the STC or apply for free sample).
Programmer can be used as demo board
About Emulator
We do not provite specific emulator now. If you have a traditional 8051 emulator, you can use it to simulate
STC MCU's some 8052 basic functions.
10.5 Self-Defined ISP download Demo
/*-------------------------------------------------------------------------------------------------------------*/
/* --- STC MCU International Limited ----------------------------------------------------------------*/
/* --- STC90xx Series MCU using software to custom download code Demo---------------------*/
/* If you want to use the program or the program referenced in the ------------------------------*/
/* article, please specify in which data and procedures from STC ------------------------------*/
/*-------------------------------------------------------------------------------------------------------------*/
#include & lt; reg51.h & gt;
#include & lt; instrins.h & gt;
sfr ISP_CONTR = 0xe7;
sbit MCU_Start_Led = P1^7;
#define Self_Define_ISP_Download_Command 0x22
#define RELOAD_COUNT 0xfb
//18.432MHz,12T,SMOD=0,9600bps
//#define RELOAD_COUNT 0xf6
//18.432MHz,12T,SMOD=0,4800bps
//#define RELOAD_COUNT 0xec
//18.432MHz,12T,SMOD=0,2400bps
//#define RELOAD_COUNT 0xd8
//18.432MHz,12T,SMOD=0,1200bps
void serial_port_initial(void);
void send_UART(unsigned char);
void UART_Interrupt_Receive(void);
void soft_reset_to_ISP_Monitor(void);
void delay(void);
void display_MCU_Start_Led(void);
STC MCU Limited.
void main(void)
{
unsigned char i = 0;
serial_port_initial();
//Initial UART
display_MCU_Start_Led(); //Turn on the work LED
send_UART(0x34); //Send UART test data
send_UART(0xa7); // Send UART test data
while (1);
}
void send_UART(unsigned char i)
{
ES = 0; //Disable serial interrupt
TI = 0; //Clear TI flag
SBUF = i;
//send this data
while (!TI);
//wait for the data is sent
TI = 0; //clear TI flag
ES = 1; //enable serial interrupt
}
void UART_Interrupt)Receive(void) interrupt 4 using 1
{
unsigned char k = 0;
if (RI)
{
RI = 0;
k = SBUF;
if (k == Self_Define_ISP_Command) //check the serial data
{
delay(); //delay 1s
delay(); //delay 1s
soft_reset_to_ISP_Monitor();
}
}
if (TI)
{
TI = 0;
}
}
void soft_reset_to_ISP_Monitor(void)
{
ISP_CONTR = 0x60;
//0110,0000 soft reset system to run ISP monitor
}
STC MCU Limited.
void delay(void)
{
unsigned int j = 0;
unsigned int g = 0;
for (j=0; j & lt; 5; j++)
{
for (g=0; g & lt; 60000; g++)
{
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
}
}
}
void display_MCU_Start_Led(void)
{
unsigned char i = 0;
for (i=0; i & lt; 3; i++)
{
MCU_Start_Led = 0;
dejay();
MCU_Start_Led = 1;
dejay();
MCU_Start_Led = 0;
}
}
STC MCU Limited.
//Turn on work LED
//Turn off work LED
//Turn on work LED
In addition, the PC-side application also need to make the following settings
Clicking the " Help " button as show in above figure, we can see the detail explaination as below.
STC MCU Limited.
Appendix A: Assembly Language Programming
INTRODUCTION
Assembly language is a computer language lying between the extremes of machine language and high-level
language like Pascal or C use words and statements that are easily understood by humans, although still a long
way from " natural " language.Machine language is the binary language of computers.A machine language program
is a series of binary bytes representing instructions the computer can execute.
Assembly language replaces the binary codes of machine language with easy to remember " mnemonics " that
facilitate programming.For example, an addition instruction in machine language might be represented by the
code " 10110011 " .It might be represented in assembly language by the mnemonic " ADD " .Programming with
mnemonics is obviously preferable to programming with binary codes.
Of course, this is not the whole story. Instructions operate on data, and the location of the data is specified by
various " addressing modes " emmbeded in the binary code of the machine language instruction. So, there may be
several variations of the ADD instruction, depending on what is added. The rules for specifying these variations
are central to the theme of assembly language programming.
An assembly language program is not executable by a computer. Once written, the program must undergo
translation to machine language. In the example above, the mnemonic " ADD " must be translated to the binary
code " 10110011 " . Depending on the complexity of the programming environment, this translation may involve
one or more steps before an executable machine language program results. As a minimum, a program called an
" assembler " is required to translate the instruction mnemonics to machine language binary codes. Afurther step
may require a " linker " to combine portions of program from separate files and to set the address in memory at
which th program may execute. We begin with a few definitions.
An assembly language program i a program written using labels, mnemonics, and so on, in which each
statement corresponds to a machine instruction. Assembly language programs, often called source code or
symbolic code, cannot be executed by a computer.
A machine language program is a program containing binary codes that represent instructions to a computer.
Machine language programs, often called object code, are executable by a computer.
A assembler is a program that translate an assembly language program into a machine language program.
The machine language program (object code) may be in " absolute " form or in " relocatable " form. In the latter
case, " linking " is required to set the absolute address for execution.
A linker is a program that combines relocatable object programs (modules) and produces an absolute object
program that is executable by a computer. A linker is sometimes called a " linker/locator " to reflect its separate
functions of combining relocatable modules (linking) and setting the address for execution (locating).
A segment is a unit of code or data memory. A segment may be relocatable or absolute. A relocatable
segment has a name, type, and other attributes that allow the linker to combine it with other paritial segments,
if required, and to correctly locate the segment. An absolute segment has no name and cannot be combined with
other segments.
A module contains one or more segments or partial segments. A module has a name assigned by the user. The
module definitions determine the scope of local symbols. An object file contains one or more modules. A module
may be thought of as a " file " in many instances.
A program consists of a single absolute module, merging all absolute and relocatable segments from all input
modules. A program contains only the binary codes for instructions (with address and data constants) that are
understood by a computer.
STC MCU Limited.
ASSEMBLER OPERATION
There are many assembler programs and other support programs available to facilitate the development of
applications for the 8051 microcontroller. Intel's original MCS-51 family assembler, ASM51, is no longer
available commercially. However, it set the standard to which the others are compared.
ASM51 is a powerful assembler with all the bells and whistles. It is available on Intel development systems
and on the IBM PC family of microcomputers. Since these " host " computers contain a CPU chip other than the
8051, ASM51 is called a cross assembler. An 8051 source program may be written on the host computer (using
any text editor) and may be assembled to an object file and listing file (using ASM51), but the program may not
be executed. Since the host system's CPU chip is not an 8051, it does not understand the binary instruction in the
object file. Execution on the host computer requires either hardware emulation or software simulation of the target
CPU. A third possibility is to download the object program to an 8051-based target system for execution.
ASM51 is invoked from the system prompt by
ASM51 source_file [assembler_controls]
The source file is assembled and any assembler controls specified take effect. The assembler receives a source
file as input (e.g., PROGRAM.SRC) and generates an object file (PROGRAM.OBJ) and listing file (PROGRAM.
LST) as output. This is illustrated in Figure 1.
Since most assemblers scan the source program twice in performing the translation to machine language,
they are described as two-pass assemblers. The assembler uses a location counter as the address of instructions
and the values for labels. The action of each pass is described below.
PROGRAM.OBJ
PROGRAM.SRC
Legend
Utility program
User file
ASM51
PROGRAM.LST
Figure 1 Assembling a source program
Pass one
During the first pass, the source file is scanned line-by-line and a symbol table is built. The location counter
defaults to 0 or is set by the ORG (set origin) directive. As the file is scanned, the location counter is incremented
by the length of each instruction. Define data directives (DBs or DWs) increment the location counter by the
number of bytes defined. Reserve memory directives (DSs) increment the location counter by the number of bytes
reserved.
Each time a label is found at the beginning of a line, it is placed in the symbol table along with the current
value of the location counter. Symbols that are defined using equate directives (EQUs) are placed in the symbol
table along with the " equated " value. The symbol table is saved and then used during pass two.
Pass two
During pass two, the object and listing files are created. Mnemonics are converted to opcodes and placed in
the output files. Operands are evaluated and placed after the instruction opcodes. Where symbols appear in the
operand field, their values are retrieved from the symbol table (created during pass one) and used in calculating
the correct data or addresses for the instructions.
Since two passes are performed, the source program may use " forward references " , that is, use a symbol
before it is defined. This would occur, for example, in branching ahead in a program.
STC MCU Limited.
The object file, if it is absolute, contains only the binary bytes (00H-0FH) of the machine language program.
A relocatable object file will also contain a sysmbol table and other information required for linking and locating.
The listing file contains ASCII text codes (02H-7EH) for both the source program and the hexadecimal bytes in
the machine language program.
A good demonstration of the distinction between an object file and a listing file is to display each on the
host computer's CRT display (using, for example, the TYPE command on MS-DOS systems). The listing file
clearly displays, with each line of output containing an address, opcode, and perhaps data, followed by the
program statement from the source file. The listing file displays properly because it contains only ASCII text
codes. Displaying the object file is a problem, however. The output will appear as " garbage " , since the object file
contains binary codes of an 8051 machine language program, rather than ASCII text codes.
ASSEMBLY LANGUAGE PROGRAM FORMAT
Assembly language programs contain the following:
o Machine instructions
o Assembler directives
o Assembler controls
o Comments
Machine instructions are the familiar mnemonics of executable instructions (e.g., ANL). Assembler directives
are instructions to the assembler program that define program structure, symbols, data, constants, and so on (e.g.,
ORG). Assembler controls set assembler modes and direct assembly flow (e.g., $TITLE). Comments enhance the
readability of programs by explaining the purpose and operation of instruction sequences.
Those lines containing machine instructions or assembler directives must be written following specific rules
understood by the assembler. Each line is divided into " fields " separated by space or tab characters. The general
format for each line is as follows:
[label:]
mnemonic [operand]
[, operand]
[...] [;commernt]
Only the mnemonic field is mandatory. Many assemblers require the label field, if present, to begin on the left in
column 1, and subsequent fields to be separated by space or tab charecters. With ASM51, the label field needn't
begin in column 1 and the mnemonic field needn't be on the same line as the label field. The operand field must,
however, begin on the same line as the mnemonic field. The fields are described below.
Label Field
A label represents the address of the instruction (or data) that follows. When branching to this instruction, this
label is usded in the operand field of the branch or jump instruction (e.g., SJMP SKIP).
Whereas the term " label " always represents an address, the term " symbol " is more general. Labels are
one type of symbol and are identified by the requirement that they must terminate with a colon(:). Symbols
are assigned values or attributes, using directives such as EQU, SEGMENT, BIT, DATA, etc. Symbols may be
addresses, data constants, names of segments, or other constructs conceived by the programmer. Symbols do not
terminate with a colon. In the example below, PAR is a symbol and START is a label (which is a type of symbol).
PAR
EQU
500
; " PAR " IS A SYMBOL WHICH
;REPRESENTS THE VALUE 500
START: MOV
A,#0FFH
; " START " IS A LABEL WHICH
;REPRESENTS THE ADDRESS OF
;THE MOV INSTRUCTION
A symbol (or label) must begin with a letter, question mark, or underscore (_); must be followed by letters,
digit, " ? " , or " _ " ; and can contain up to 31 characters. Symbols may use upper- or lowercase characters, but they
are treated the same. Reserved words (mnemonics, operators, predefined symbols, and directives) may not be
used.
STC MCU Limited.
Mnemonic Field
Intruction mnemonics or assembler directives go into mnemonic field, which follows the label field. Examples of
instruction mnemonics are ADD, MOV, DIV, or INC. Examples of assembler directives are ORG, EQU, or DB.
Operand Field
The operand field follows the mnemonic field. This field contains the address or data used by the instruction. A
label may be used to represent the address of the data, or a symbol may be used to represent a data constant. The
possibilities for the operand field are largely dependent on the operation. Some operations have no operand (e.g.,
the RET instruction), while others allow for multiple operands separated by commas. Indeed, the possibilties for
the operand field are numberous, and we shall elaborate on these at length. But first, the comment field.
Comment Field
Remarks to clarify the program go into comment field at the end of each line. Comments must begin with a
semicolon (;). Each lines may be comment lines by beginning them with a semicolon. Subroutines and large
sections of a program generally begin with a comment block--serveral lines of comments that explain the general
properties of the section of software that follows.
Special Assembler Symbols
Special assembler symbols are used for the register-specific addressing modes. These include A, R0 through
R7, DPTR, PC, C and AB. In addition, a dollar sign ($) can be used to refer to the current value of the location
counter. Some examples follow.
SETB
C
INC
DPTR
JNB
TI , $
The last instruction above makes effective use of ASM51's location counter to avoid using a label. It could also be
written as
HERE: JNB
TI , HERE
Indirect Address
For certain instructions, the operand field may specify a register that contains the address of the data. The
commercial " at " sign (@) indicates address indirection and may only be used with R0, R1, the DPTR, or the PC,
depending on the instruction. For example,
ADD
A , @R0
MOVC A , @A+PC
The first instruction above retrieves a byte of data from internal RAM at the address specified in R0. The second
instruction retrieves a byte of data from external code memory at the address formed by adding the contents of
the accumulator to the program counter. Note that the value of the program counter, when the add takes place, is
the address of the instruction following MOVC. For both instruction above, the value retrieved is placed into the
accumulator.
Immediate Data
Instructions using immediate addressing provide data in the operand field that become part of the instruction.
Immediate data are preceded with a pound sign (#). For example,
STC MCU Limited.
CONSTANT
EQU
MOV
ORL
100
A , #0FEH
40H , #CONSTANT
All immediate data operations (except MOV DPTR,#data) require eight bits of data. The immediate data are
evaluated as a 16-bit constant, and then the low-byte is used. All bits in the high-byte must be the same (00H or
FFH) or the error message " value will not fit in a byte " is generated. For example, the following instructions are
syntactically correct:
MOV
A , #0FF00H
MOV
A , #00FFH
But the following two instructions generate error messages:
MOV
A , #0FE00H
MOV
A , #01FFH
If signed decimal notation is used, constants from -256 to +255 may also be used. For example, the following
two instructions are equivalent (and syntactically correct):
MOV
A , #-256
MOV
A , #0FF00H
Both instructions above put 00H into accumulator A.
Data Address
Many instructions access memory locations using direct addressing and require an on-chip data memory address
(00H to 7FH) or an SFR address (80H to 0FFH) in the operand field. Predefined symbols may be used for the
SFR addresses. For example,
MOV
A , 45H
MOV
A , SBUF
;SAME AS MOV A, 99H
Bit Address
One of the most powerful features of the 8051 is the ability to access individual bits without the need for masking
operations on bytes. Instructions accessing bit-addressable locations must provide a bit address in internal data
memory (00h to 7FH) or a bit address in the SFRs (80H to 0FFH).
There are three ways to specify a bit address in an instruction: (a) explicitly by giving the address, (b) using
the dot operator between the byte address and the bit position, and (c) using a predefined assembler symbol. Some
examples follow.
SETB
0E7H
;EXPLICIT BIT ADDRESS
SETB
ACC.7
;DOT OPERATOR (SAME AS ABOVE)
JNB
TI , $
; " TI " IS A PRE-DEFINED SYMBOL
JNB
99H , $
;(SAME AS ABOVE)
Code Address
A code address is used in the operand field for jump instructions, including relative jumps (SJMP and conditional
jumps), absolute jumps and calls (ACALL, AJMP), and long jumps and calls (LJMP, LCALL).
The code address is usually given in the form of a label.
ASM51 will determine the correct code address and insert into the instruction the correct 8-bit signed offset,
11-bit page address, or 16-bit long address, as appropriate.
STC MCU Limited.
Generic Jumps and Calls
ASM51 allows programmers to use a generic JMP or CALL mnemonic. " JMP " can be used instead of SJMP,
AJMP or LJMP; and " CALL " can be used instead of ACALL or LCALL. The assembler converts the generic
mnemonic to a " real " instruction following a few simple rules. The generic mnemonic converts to the short form
(for JMP only) if no forward references are used and the jump destination is within -128 locations, or to the
absolute form if no forward references are used and the instruction following the JMP or CALL instruction is in
the same 2K block as the destination instruction. If short or absolute forms cannot be used, the conversion is to
the long form.
The conversion is not necessarily the best programming choice. For example, if branching ahead a few
instrucions, the generic JMP will always convert to LJMP even though an SJMP is probably better. Consider the
following assembled instructions sequence using three generic jumps.
LOC
1234
1234
1235
12FC
12FC
12FE
1301
OBJ
04
80FD
4134
021301
04
LINE
1
2
3
4
5
6
7
8
SOURCE
START:
FINISH:
ORG
INC
JMP
ORG
JMP
JMP
INC
END
1234H
A
START
START + 200
START
FINISH
A
;ASSEMBLES AS SJMP
;ASSEMBLES AS AJMP
;ASSEMBLES AS LJMP
The first jump (line 3) assembles as SJMP because the destination is before the jump ( i.e., no forward reference)
and the offset is less than -128. The ORG directive in line 4 creates a gap of 200 locations between the label
START and the second jump, so the conversion on line 5 is to AJMP because the offset is too great for SJMP.
Note also that the address following the second jump (12FEH) and the address of START (1234H) are within the
same 2K page, which, for this instruction sequence, is bounded by 1000H and 17FFH. This criterion must be met
for absolute addressing. The third jump assembles as LJMP because the destination (FINISH) is not yet defined
when the jump is assembled (i.e., a forward reference is used). The reader can verify that the conversion is as
stated by examining the object field for each jump instruction.
ASSEMBLE-TIME EXPRESSION EVALUATION
Values and constants in the operand field may be expressed three ways: (a) explicitly (e.g.,0EFH), (b) with a
predefined symbol (e.g., ACC), or (c) with an expression (e.g.,2 + 3). The use of expressions provides a powerful
technique for making assembly language programs more readable and more flexible. When an expression is used,
the assembler calculates a value and inserts it into the instruction.
All expression calculations are performed using 16-bit arithmetic; however, either 8 or 16 bits are inserted
into the instruction as needed. For example, the following two instructions are the same:
MOV
DPTR, #04FFH + 3
MOV
DPTR, #0502H
;ENTIRE 16-BIT RESULT USED
If the same expression is used in a " MOV A,#data " instruction, however, the error message " value will not fit in a
byte " is generated by ASM51. An overview of the rules for evaluateing expressions follows.
STC MCU Limited.
Number Bases
The base for numeric constants is indicated in the usual way for Intel microprocessors. Constants must be
followed with " B " for binary, " O " or " Q " for octal, " D " or nothing for decimal, or " H " for hexadecimal. For
example, the following instructions are the same:
MOV
MOV
MOV
MOV
MOV
A , #15H
A , #1111B
A , #0FH
A , #17Q
A , #15D
Note that a digit must be the first character for hexadecimal constants in order to differentiate them from labels (i.e.,
" 0A5H " not " A5H " ).
Charater Strings
Strings using one or two characters may be used as operands in expressions. The ASCII codes are converted to the
binary equivalent by the assembler. Character constants are enclosed in single quotes ('). Some examples follow.
CJNE
A , # 'Q', AGAIN
SUBB A , # '0'
;CONVERT ASCII DIGIT TO BINARY DIGIT
MOV
DPTR, # 'AB'
MOV
DPTR, #4142H
;SAME AS ABOVE
Arithmetic Operators
The arithmetic operators are
+
addition
subtraction
*
multiplication
/
division
MOD
modulo (remainder after division)
For example, the following two instructions are same:
MOV
A, 10 +10H
MOV
A, #1AH
The following two instructions are also the same:
MOV
A, #25 MOD 7
MOV
A, #4
Since the MOD operator could be confused with a symbol, it must be seperated from its operands by at least one
space or tab character, or the operands must be enclosed in parentheses. The same applies for the other operators
composed of letters.
Logical Operators
The logical operators are
OR
logical
AND
logical
XOR
logical
NOT
logical
OR
AND
Exclusive OR
NOT (complement)
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The operation is applied on the corresponding bits in each operand. The operator must be separated from the
operands by space or tab characters. For example, the following two instructions are the same:
MOV
A, # '9' AND 0FH
MOV
A, #9
The NOT operator only takes one operand. The following three MOV instructions are the same:
THREE
EQU
3
MINUS_THREE EQU
-3
MOV
A, # (NOT THREE) + 1
MOV
A, #MINUS_THREE
MOV
A, #11111101B
Special Operators
The sepcial operators are
SHR
shift right
SHL
shift left
HIGH
high-byte
LOW
low-byte
()
evaluate first
For example, the following two instructions are the same:
MOV
A, #8 SHL 1
MOV
A, #10H
The following two instructions are also the same:
MOV
A, #HIGH 1234H
MOV
A, #12H
Relational Operators
When a relational
The operators are
EQ
NE
LT
LE
GT
GE
operator is used between two operands, the result is alwalys false (0000H) or true (FFFFH).
=
& lt; & gt;
& lt;
& lt; =
& gt;
& gt; =
equals
not equals
less than
less than or equal to
greater than
greater than or equal to
Note that for each operator, two forms are acceptable (e.g., " EQ " or " = " ). In the following examples, all relational
tests are " true " :
MOV
A, #5 = 5
MOV
A,#5 NE 4
MOV
A,# 'X' LT 'Z'
MOV
A,# 'X' & gt; = 'X'
MOV
A,#$ & gt; 0
MOV
A,#100 GE 50
STC MCU Limited.
So, the assembled instructions are equal to
MOV
A, #0FFH
Even though expressions evaluate to 16-bit results (i.e., 0FFFFH), in the examples above only the low-order
eight bits are used, since the instruction is a move byte operation. The result is not considered too big in this case,
because as signed numbers the 16-bit value FFFFH and the 8-bit value FFH are the same (-1).
Expression Examples
The following are examples of expressions and the values that result:
Expression
Result
'B' - 'A'
0001H
8/3
0002H
155 MOD 2
0001H
4*4
0010H
8 AND 7
0000H
NOT 1
FFFEH
'A' SHL 8
4100H
LOW 65535
00FFH
(8 + 1) * 2
0012H
5 EQ 4
0000H
'A' LT 'B'
FFFFH
3 & lt; = 3
FFFFHss
A practical example that illustrates a common operation for timer initialization follows: Put -500 into Timer 1
registers TH1 and TL1. In using the HIGH and LOW operators, a good approach is
VALUE
EQU
-500
MOV
TH1, #HIGH VALUE
MOV
TL1, #LOW VALUE
The assembler converts -500 to the corresponding 16-bit value (FE0CH); then the HIGH and LOW operators
extract the high (FEH) and low (0CH) bytes. as appropriate for each MOV instruction.
Operator Precedence
The precedence of expression operators from highest to lowest is
()
HIGH LOW
* / MOD SHL SHR
+EQ NE LT LE GT GE = & lt; & gt; & lt; & lt; = & gt; & gt; =
NOT
AND
OR XOR
When operators of the same precedence are used, they are evaluated left to right.
Examples:
Expression
Value
HIGH ( 'A' SHL 8)
0041H
HIGH 'A' SHL 8
0000H
NOT 'A' - 1
FFBFH
'A' OR 'A' SHL 8
4141H
STC MCU Limited.
ASSEMBLER DIRECTIVES
Assembler directives are instructions to the assembler program. They are not assembly language instructions
executable by the target microprocessor. However, they are placed in the mnemonic field of the program. With the
exception of DB and DW, they have no direct effect on the contents of memory.
ASM51 provides several catagories of directives:
o
o
o
o
o
Assembler state control (ORG, END, USING)
Symbol definition (SEGMENT, EQU, SET, DATA, IDATA, XDATA, BIT, CODE)
Storage initialization/reservation (DS, DBIT, DB, DW)
Program linkage (PUBLIC, EXTRN,NAME)
Segment selection (RSEG, CSEG, DSEG, ISEG, ESEG, XSEG)
Each assembler directive is presented below, ordered by catagory.
Assembler State Control
ORG (Set Origin)
The format for the ORG (set origin) directive is
ORG
expression
The ORG directive alters the location counter to set a new program origin for statements that follow. A label is
not permitted. Two examples follow.
ORG
ORG
100H
($ + 1000H) AND 0F00H
;SET LOCATION COUNTER TO 100H
;SET TO NEXT 4K BOUNDARY
The ORG directive can be used in any segment type. If the current segment is absolute, the value will be an
absolute address in the current segment. If a relocatable segment is active, the value of the ORG expression is
treated as an offset from the base address of the current instance of the segment.
End
The format of the END directive is
END
END should be the last statement in the source file. No label is permitted and nothing beyond the END statement
is processed by the assembler.
Using
The format of the END directive is
USING expression
This directive informs ASM51 of the currently active register bank. Subsequent uses of the predefined symbolic
register addresses AR0 to AR7 will convert to the appropriate direct address for the active register bank. Consider
the following sequence:
USING
PUSH
USING
PUSH
3
AR7
1
AR7
The first push above assembles to PUSH 1FH (R7 in bank 3), whereas the second push assembles to PUSH 0FH
(R7 in bank 1).
Note that USING does not actually switch register banks; it only informs ASM51 of the active bank.
Executing 8051 instructions is the only way to switch register banks. This is illustrated by modifying the example
above as follows:
STC MCU Limited.
MOV
USING
PUSH
MOV
USING
PUSH
PSW, #00011000B
3
AR7
PSW, #00001000B
1
AR7
;SELECT REGISTER BANK 3
;ASSEMBLE TO PUSH 1FH
;SELECT REGISTER BANK 1
;ASSEMBLE TO PUSH 0FH
Symbol Definition
The symbol definition directives create symbols that represent segment, registers, numbers, and addresses. None
of these directives may be preceded by a label. Symbols defined by these directives may not have been previously
defined and may not be redefined by any means. The SET directive is the only exception. Symbol definiton
directives are described below.
The format for the SEGMENT directive is shown below.
Segment
symbol
SEGMENT
segment_type
The symbol is the name of a relocatable segment. In the use of segments, ASM51 is more complex than
conventional assemblers, which generally support only " code " and " data " segment types. However, ASM51
defines additional segment types to accommodate the diverse memory spaces in the 8051. The following are the
defined 8051 segment types (memory spaces):
o
o
o
o
o
CODE (the code segment)
XDATA (the external data space)
DATA (the internal data space accessible by direct addressing, 00H-07H)
IDATA (the entire internal data space accessible by indirect addressing, 00H-07H)
BIT (the bit space; overlapping byte locations 20H-2FH of the internal data space)
For example, the statement
EPROM
SEGMENT
CODE
declares the symbol EPROM to be a SEGMENT of type CODE. Note that this statement simply declares what
EPROM is. To actually begin using this segment, the RSEG directive is used (see below).
EQU (Equate)
Symbol
The format for the EQU directive is
EQU
expression
The EQU directive assigns a numeric value to a specified symbol name. The symbol must be a valid symbol
name, and the expression must conform to the rules described earlier.
The following are examples of the EQU directive:
N27
HERE
EQU
EQU
27
$
CR
MESSAGE:
LENGTH
EQU
0DH
DB 'This is a message'
EQU
$ - MESSAGE
;SET N27 TO THE VALUE 27
;SET " HERE " TO THE VALUE OF
;THE LOCATION COUNTER
;SET CR (CARRIAGE RETURN) TO 0DH
; " LENGTH " EQUALS LENGTH OF " MESSAGE "
Other Symbol Definition Directives
The SET directive is similar to the EQU directive except the
symbol may be redefined later, using another SET directive.
STC MCU Limited.
The DATA, IDATA, XDATA, BIT, and CODE directives assign addresses of the corresponding segment
type to a symbol. These directives are not essential. A similar effect can be achieved using the EQU directive; if
used, however, they evoke powerful type-checking by ASM51. Consider the following two directives and four
instructions:
FLAG1
FLAG2
EQU
BIT
SETB
SETB
MOV
MOV
05H
05H
FLAG1
FLAG2
FLAG1, #0
FLAG2, #0
The use of FLAG2 in the last instruction in this sequence will generate a " data segment address expected " error
message from ASM51. Since FLAG2 is defined as a bit address (using the BIT directive), it can be used in a set
bit instruction, but it cannot be used in a move byte instruction. Hence, the error. Even though FLAG1 represents
the same value (05H), it was defined using EQU and does not have an associated address space. This is not an
advantage of EQU, but rather, a disadvantage. By properly defining address symbols for use in a specific memory
space (using the directives BIT, DATA, XDATA,ect.), the programmer takes advantage of ASM51's powerful
type-checking and avoids bugs from the misuse of symbols.
Storage Initialization/Reservation
The storage initialization and reservation directives initialize and reserve space in either word, byte, or bit units.
The space reserved starts at the location indicated by the current value of the location counter in the currently
active segment. These directives may be preceded by a label. The storage initialization/reservation directives are
described below.
DS (Define Storage)
[label:]
The format for the DS (define storage) directive is
DS
expression
The DS directive reserves space in byte units. It can be used in any segment type except BIT. The expression
must be a valid assemble-time expression with no forward references and no relocatable or external references.
When a DS statement is encountered in a program, the location counter of the current segment is incremented by
the value of the expression. The sum of the location counter and the specified expression should not exceed the
limitations of the current address space.
The following statement create a 40-byte buffer in the internal data segment:
LENGTH
BUFFER:
DSEG
EQU
DS
AT
30H
40
LENGRH
;PUT IN DATA SEGMENT (ABSOLUTE, INTERNAL)
;40 BYTES RESERVED
The label BUFFER represents the address of the first location of reserved memory. For this example, the buffer
begins at address 30H because " AT 30H " is specified with DSEG. The buffer could be cleared using the following
instruction sequence:
LOOP:
STC MCU Limited.
MOV
R7, #LENGTH
MOV
R0, #BUFFER
MOV
@R0, #0
DJNZ
R7, LOOP
(continue)
To create a 1000-byte buffer in external RAM starting at 4000H, the following directives could be used:
XSTART
XLENGTH
XBUFFER:
EQU
4000H
EQU
1000
XSEG
AT
DS XLENGTH
XSTART
This buffer could be cleared with the following instruction sequence:
MOV
DPTR, #XBUFFER
CLR
A
MOVX @DPTR, A
INC
DPTR
MOV
A, DPL
CJNE
A, #LOW (XBUFFER + XLENGTH + 1), LOOP
MOV
A, DPH
CJNE
A, #HIGH (XBUFFER + XLENGTH + 1), LOOP
(continue)
LOOP:
This is an excellent example of a powerful use of ASM51's operators and assemble-time expressions. Since an
instruction does not exist to compare the data pointer with an immediate value, the operation must be fabricated
from available instructions. Two compares are required, one each for the high- and low-bytes of the DPTR.
Furthermore, the compare-and-jump-if-not-equal instruction works only with the accumulator or a register, so
the data pointer bytes must be moved into the accumulator before the CJNE instruction. The loop terminates only
when the data pointer has reached XBUFFER + LENGTH + 1. (The " +1 " is needed because the data pointer is
incremented after the last MOVX instruction.)
DBIT
The format for the DBIT (define bit) directive is,
[label:]
DBIT
expression
The DBIT directive reserves space in bit units. It can be used only in a BIT segment. The expression must be
a valid assemble-time expression with no forward references. When the DBIT statement is encountered in a
program, the location counter of the current (BIT) segment is incremented by the value of the expression. Note
that in a BIT segment, the basic unit of the location counter is bits rather than bytes. The following directives
creat three flags in a absolute bit segment:
KEFLAG:
PRFLAG:
DKFLAG:
BSEG
DBIT
DBIT
DBIT
1
1
1
;BIT SEGMENT (ABSOLUTE)
;KEYBOARD STATUS
;PRINTER STATUS
;DISK STATUS
Since an address is not specified with BSEG in the example above, the address of the flags defined by DBIT could
be determined (if one wishes to to so) by examining the symbol table in the .LST or .M51 files. If the definitions
above were the first use of BSEG, then KBFLAG would be at bit address 00H (bit 0 of byte address 20H). If other
bits were defined previously using BSEG, then the definitions above would follow the last bit defined.
DB (Define Byte)
[label:]
The format for the DB (define byte) directive is,
DB
expression [, expression] [...]
The DB directive initializes code memory with byte values. Since it is used to actually place data constants in
code memory, a CODE segment must be active. The expression list is a series of one or more byte values (each of
which may be an expression) separated by commas.
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The DB directive permits character strings (enclosed in single quotes) longer than two characters as long as they
are not part of an expression. Each character in the string is converted to the corresponding ASCII code. If a label
is used, it is assigned the address of th first byte. For example, the following statements
CSEG AT
0100H
DB
0, 1, 4, 9, 16, 25
DB
'Login:', 0
SQUARES:
MESSAGE:
;SQUARES OF NUMBERS 0-5
;NULL-TERMINATED CHARACTER STRING
When assembled, result in the following hexadecimal memory assignments for external code memory:
Address
0100
0101
0102
0103
0104
0105
0106
0107
0108
0109
010A
010B
010C
Contents
00
01
04
09
10
19
4C
6F
67
69
6E
3A
00
DW (Define Word)
[label:]
The format for the DW (define word) directive is
DW
expression
[, expression] [...]
The DW directive is the same as the DB directive except two memory locations (16 bits) are assigned for each
data item. For example, the statements
CSEG
DW
AT
200H
$, 'A', 1234H, 2, 'BC'
result in the following hexadecimal memory assignments:
Address
0200
0201
0202
0203
0204
0205
0206
0207
0208
0209
Contents
02
00
00
41
12
34
00
02
42
43
Program Linkage
Program linkage directives allow the separately assembled modules (files) to communicate by permitting
intermodule references and the naming of modules. In the following discussion, a " module " can be considered a
" file. " (In fact, a module may encompass more than one file.)
STC MCU Limited.
The format for the PUBLIC (public symbol) directive is
Public
PUBLIC
symbol
[, symbol] [...]
The PUBLIC directive allows the list of specified symbols to known and used outside the currently assembled
module. A symbol declared PUBLIC must be defined in the current module. Declaring it PUBLIC allows it to be
referenced in another module. For example,
PUBLIC
INCHAR, OUTCHR, INLINE, OUTSTR
The format for the EXTRN (external symbol) directive is
Extrn
EXTRN
segment_type (symbol [, symbol] [...], ...)
The EXTRN directive lists symbols to be referenced in the current module that are defined in other modules. The
list of external symbols must have a segment type associated with each symbol in the list. (The segment types
are CODE, XDATA, DATA, IDATA, BIT, and NUMBER. NUMBER is a type-less symbol defined by EQU.)
The segment type indicates the way a symbol may be used. The information is important at link-time to ensure
symbols are used properly in different modules.
The PUBLIC and EXTRN directives work together. Consider the two files, MAIN.SRC and MESSAGES.
SRC. The subroutines HELLO and GOOD_BYE are defined in the module MESSAGES but are made available
to other modules using the PUBLIC directive. The subroutines are called in the module MAIN even though they
are not defined there. The EXTRN directive declares that these symbols are defined in another module.
MAIN.SRC:
EXTRN
...
CALL
...
CALL
...
END
CODE (HELLO, GOOD_BYE)
HELLO
GOOD_BYE
MESSAGES.SRC:
HELLO:
GOOD_BYE:
PUBLIC
HELLO, GOOD_BYE
...
(begin subroutine)
...
RET
(begin subroutine)
...
RET
...
END
Neither MAIN.SRC nor MESSAGES.SRC is a complete program; they must be assembled separately and
linked together to form an executable program. During linking, the external references are resolved with correct
addresses inserted as the destination for the CALL instructions.
Name
NAME
The format for the NAME directive is
module_name
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All the usual rules for symbol names apply to module names. If a name is not provided, the module takes on
the file name (without a drive or subdirectory specifier and without an extension). In the absence of any use
of the NAME directive, a program will contain one module for each file. The concept of " modules, " therefore,
is somewhat cumbersome, at least for relatively small programming problems. Even programs of moderate
size (encompassing, for example, several files complete with relocatable segments) needn't use the NAME
directive and needn't pay any special attention to the concept of " modules. " For this reason, it was mentioned in
the definition that a module may be considered a " file, " to simplify learning ASM51. However, for very large
programs (several thousand lines of code, or more), it makes sense to partition the problem into modules, where,
for example, each module may encompass several files containing routines having a common purpose.
Segment Selection Directives
When the assembler encounters a segment selection directive, it diverts the following code or data into the
selected segment until another segment is selected by a segment selection directive. The directive may select may
select a previously defined relocatable segment or optionally create and select absolute segments.
RSEG (Relocatable Segment)
RSEG
The format for the RSEG (relocatable segment) directive is
segment_name
Where " segment_name " is the name of a relocatable segment previously defined with the SEGMENT directive.
RSEG is a " segment selection " directive that diverts subsequent code or data into the named segment until another
segment selection directive is encountered.
Selecting Absolute Segments
RSEG selects a relocatable segment. An " absolute " segment, on the other
hand, is selected using one of the directives:
CSEG
DSEG
ISEG
BSEG
XSEG
(AT
(AT
(AT
(AT
(AT
address)
address)
address)
address)
address)
These directives select an absolute segment within the code, internal data, indirect internal data, bit, or external
data address spaces, respectively. If an absolute address is provided (by indicating " AT address " ), the assembler
terminates the last absolute address segment, if any, of the specified segment type and creates a new absolute
segment starting at that address. If an absolute address is not specified, the last absolute segment of the specified
type is continuted. If no absolute segment of this type was previously selected and the absolute address is omitted,
a new segment is created starting at location 0. Forward references are not allowed and start addresses must be
absolute.
Each segment has its own location counter, which is always set to 0 initially. The default segment is an
absolute code segment; therefore, the initial state of the assembler is location 0000H in the absolute code segment.
When another segment is chosen for the first time, the location counter of the former segment retains the last
active value. When that former segment is reselected, the location counter picks up at the last active value. The
ORG directive may be used to change the location counter within the currently selected segment.
ASSEMBLER CONTROLS
Assembler controls establish the format of the listing and object files by regulating the actions of ASM51. For the
most part, assembler controls affect the look of the listing file, without having any affect on the program itself.
They can be entered on the invocation line when a program is assembled, or they can be placed in the source file.
Assembler controls appearing in the source file must be preceded with a dollor sign and must begin in column 1.
STC MCU Limited.
There are two categories of assembler controls: primary and general. Primary controls can be placed in the
invocation line or at the beginnig of the source program. Only other primary controls may precede a primary
control. General controls may be placed anywhere in the source program.
LINKER OPERATION
In developing large application programs, it is common to divide tasks into subprograms or modules containing
sections of code (usually subroutines) that can be written separately from the overall program. The term " modular
programming " refers to this programming strategy. Generally, modules are relocatable, meaning they are not
intended for a specific address in the code or data space. A linking and locating program is needed to combine the
modules into one absolute object module that can be executed.
Intel's RL51 is a typical linker/locator. It processes a series of relocatable object modules as input and creates
an executable machine language program (PROGRAM, perhaps) and a listing file containing a memory map and
symbol table (PROGRAM.M51). This is illustrated in following figure.
PROGRAM.ABS
FILE3.OBJ
FILE2.OBJ
RL51
FILE1.OBJ
PROGRAM.MAP
Legend
Utility program
User file
Linker operation
As relocatable modules are combined, all values for external symbols are resolved with values inserted into
the output file. The linker is invoked from the system prompt by
RL51
input_list
[T0 output_file]
[location_controls]
The input_list is a list of relocatable object modules (files) separated by commas. The output_list is the name
of the output absolute object module. If none is supplied, it defaults to the name of the first input file without any
suffix. The location_controls set start addresses for the named segments.
For example, suppose three modules or files (MAIN.OBJ, MESSAGES.OBJ, and SUBROUTINES.OBJ) are
to be combined into an executable program (EXAMPLE), and that these modules each contain two relocatable
segments, one called EPROM of type CODE, and the other called ONCHIP of type DATA. Suppose further that
the code segment is to be executable at address 4000H and the data segment is to reside starting at address 30H (in
internal RAM). The following linker invocation could be used:
RS51
MAIN.OBJ, MESSAGES.OBJ, SUBROUTINES.OBJ TO EXAMPLE & CODE
(EPROM (4000H) DATA (ONCHIP (30H))
Note that the ampersand character " & " is used as the line continuaton character.
If the program begins at the label START, and this is the first instruction in the MAIN module, then
execution begins at address 4000H. If the MAIN module was not linked first, or if the label START is not at the
beginning of MAIN, then the program's entry point can be determined by examining the symbol table in the
listing file EXAMPLE.M51 created by RL51. By default, EXAMPLE.M51 will contain only the link map. If
a symbol table is desired, then each source program must have used the SDEBUG control. The following table
shows the assembler controls supported by ASM51.
STC MCU Limited.
Assembler controls supported by ASM51
NAME
DATE (date)
DEBUG
EJECT
ERRORPRINT
(file)
NOERRORPRINT
PRIMARY/
GENERAL
GEN
G
GENONLY
INCLUED(file)
LIST
NOLIST
MACRO
(men_precent)
NOMACRO
MOD51
G
G
G
G
P
NOMOD51
P
OBJECT(file)
NOOBJECT
PAGING
P
P
P
NOPAGING
PAGELENGTH
(N)
PAGE WIDTH (N)
P
P
PRINT(file)
NOPRINT
SAVE
RESTORE
REGISTERBANK
(rb,...)
NOREGISTERBANK
SYMBOLS
NOSYMBOLS
TITLE(string)
P
P
G
G
P
MEANING
Place string in header (9 char. max.)
Outputs debug symbol information to object file
Continue listing on next page
Designates a file to receive error messages in addition to the
listing file (defauts to console)
NOERRORPRINT
NOEP Designates that error messages will be printed in listing file
only
GENONLY
GO
List only the fully expanded source as if all lines generated
by a macro call were already in the source file
GENONLY
NOGE List only the original source text in the listing file
not applicable
IC
Designates a file to be included as part of the program
LIST
LI
Print subsequent lines of source code in listing file
LIST
NOLI Do not print subsequent lines of source code in lisitng file
MACRO(50)
MR
Evaluate and expand all macro calls. Allocate percentage of
free memory for macro processing
MACRO(50)
NOMR Do not evalutate macro calls
MOD51
MO
Recognize the 8051-specific predefined special function
registers
MOD51
NOMO Do not recognize the 8051-specific predefined special
function registers
OBJECT(source.OBJ)
OJ
Designates file to receive object code
OBJECT(source.OBJ) NOOJ Designates that no object file will be created
PAGING
PI
Designates that listing file be broken into pages and each
will have a header
PAGING
NOPI Designates that listing file will contain no page breaks
PAGELENGT(60)
PL
Sets maximun number of lines in each page of listing file
(range=10 to 65536)
PAGEWIDTH(120)
PW
Set maximum number of characters in each line of listing
file (range = 72 to 132)
PRINT(source.LST)
PR
Designates file to receive source listing
PRINT(source.LST)
NOPR Designates that no listing file will be created
not applicable
SA
Stores current control settings from SAVE stack
not applicable
RS
Restores control settings from SAVE stack
REGISTERBANK(0)
RB
Indicates one or more banks used in program module
P
REGISTERBANK(0)
NORB
Indicates that no register banks are used
P
P
G
SYMBOLS
SYMBOLS
TITLE( )
SB
NOSB
TT
WORKFILES
(path)
XREF
P
same as source
WF
Creates a formatted table of all symbols used in program
Designates that no symbol table is created
Places a string in all subsequent page headers (max.60
characters)
Designates alternate path for temporay workfiles
P
NOXREF
XR
NOXREF
P
NOXREF
NOXR
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P
P
G
P
P
P
P
P
DEFAULT
DATE( )
NODEBUG
not applicable
NOERRORPRINT
ABBREV.
DA
DB
EJ
EP
Creates a cross reference listing of all symbols used in
program
Designates that no cross reference list is created
MACROS
The macro processing facility (MPL) of ASM51 is a " string replacement " facility. Macros allow frequently used
sections of code be defined once using a simple mnemonic and used anywhere in the program by inserting the
mnemonic. Programming using macros is a powerful extension of the techniques described thus far. Macros can
be defined anywhere in a source program and subsequently used like any other instruction. The syntax for macro
definition is
%*DEFINE
(call_pattern)
(macro_body)
Once defined, the call pattern is like a mnemonic; it may be used like any assembly language instruction by
placing it in the mnemonic field of a program. Macros are made distinct from " real " instructions by preceding
them with a percent sign, " % " . When the source program is assembled, everything within the macro-body, on
a character-by-character basis, is substituted for the call-pattern. The mystique of macros is largely unfounded.
They provide a simple means for replacing cumbersome instruction patterns with primitive, easy-to-remember
mnemonics. The substitution, we reiterate, is on a character-by-character basis--nothing more, nothing less.
For example, if the following macro definition appears at the beginning of a source file,
%*DEFINE
(PUSH_DPTR)
(PUSH
PUSH
)
DPH
DPL
then the statement
%PUSH_DPTR
will appear in the .LST file as
PUSH
PUSH
DPH
DPL
The example above is a typical macro. Since the 8051 stack instructions operate only on direct addresses,
pushing the data pointer requires two PUSH instructions. A similar macro can be created to POP the data pointer.
There are several distinct advantages in using macros:
o A source program using macros is more readable, since the macro mnemonic is generally more indicative
of the intended operation than the equivalent assembler instructions.
o The source program is shorter and requires less typing.
o Using macros reduces bugs
o Using macros frees the programmer from dealing with low-level details.
The last two points above are related. Once a macro is written and debugged, it is used freely without the worry
of bugs. In the PUSH_DPTR example above, if PUSH and POP instructions are used rather than push and pop
macros, the programmer may inadvertently reverse the order of the pushes or pops. (Was it the high-byte or lowbyte that was pushed first?) This would create a bug. Using macros, however, the details are worked out once--
when the macro is written--and the macro is used freely thereafter, without the worry of bugs.
Since the replacement is on a character-by-character basis, the macro definition should be carefully
constructed with carriage returns, tabs, ect., to ensure proper alignment of the macro statements with the rest of
the assembly language program. Some trial and error is required.
There are advanced features of ASM51's macro-processing facility that allow for parameter passing, local
labels, repeat operations, assembly flow control, and so on. These are discussed below.
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Parameter Passing
A macro with parameters passed from the main program has the following modified format:
%*DEFINE
(macro_name (parameter_list))
(macro_body)
For example, if the following macro is defined,
%*DEFINE
(CJNE
)
(CMPA# (VALUE))
A, #%VALUE, $ + 3
then the macro call
%CMPA# (20H)
will expand to the following instruction in the .LST file:
CJNE
A, #20H, $ + 3
Although the 8051 does not have a " compare accumulator " instruction, one is easily created using the CJNE
instruction with " $+3 " (the next instruction) as the destination for the conditional jump. The CMPA# mnemonic
may be easier to remember for many programmers. Besides, use of the macro unburdens the programmer from
remembering notational details, such as " $+3. "
Let's develop another example. It would be nice if the 8051 had instructions such as
JUMP
JUMP
JUMP
JUMP
IF
IF
IF
IF
ACCUMULATOR
ACCUMULATOR
ACCUMULATOR
ACCUMULATOR
GREATER THAN X
GREATER THAN OR EQUAL TO X
LESS THAN X
LESS THAN OR EQUAL TO X
but it does not. These operations can be created using CJNE followed by JC or JNC, but the details are tricky.
Suppose, for example, it is desired to jump to the label GREATER_THAN if the accumulator contains an ASCII
code greater than " Z " (5AH). The following instruction sequence would work:
CJNE
JNC
A, #5BH, $÷3
GREATER_THAN
The CJNE instruction subtracts 5BH (i.e., " Z " + 1) from the content of A and sets or clears the carry flag
accordingly. CJNE leaves C=1 for accumulator values 00H up to and including 5AH. (Note: 5AH-5BH & lt; 0,
therefore C=1; but 5BH-5BH=0, therefore C=0.) Jumping to GREATER_THAN on the condition " not carry "
correctly jumps for accumulator values 5BH, 5CH, 5DH, and so on, up to FFH. Once details such as these are
worked out, they can be simplified by inventing an appropriate mnemonic, defining a macro, and using the macro
instead of the corresponding instruction sequence. Here's the definition for a " jump if greater than " macro:
%*DEFINE
(JGT (VALUE, LABEL))
(CJNE A, #%VALUE+1, $+3
JNC
%LABEL
)
;JGT
To test if the accumulator contains an ASCII code greater than " Z, " as just discussed,the macro would be called as
%JGT
('Z', GREATER_THAN)
ASM51 would expand this into
CJNE
JNC
A, #5BH, $+3
;JGT
GREATER_THAN
The JGT macro is an excellent example of a relevant and powerful use of macros. By using macros, the
programmer benefits by using a meaningful mnemonic and avoiding messy and potentially bug-ridden details.
STC MCU Limited.
Local Labels
Local labels may be used within a macro using the following format:
%*DEFINE
(macro_name [(parameter_list)])
[LOCAL list_of_local_labels]
(macro_body)
For example, the following macro definition
%*DEFINE
%SKIP:
(DEC_DPTR) LOCAL SKIP
(DEC
DPL
;DECREMENT DATA POINTER
MOV A, DPL
CJNE A, #0FFH, %SKIP
DEC DPL
)
would be called as
%DEC_DPTR
and would be expanded by ASM51 into
DEC
MOV
CJNE
DEC
DPL
;DECREMENT DATA POINTER
A, DPL
A, #0FFH, SKIP00
DPH
SKIP00:
Note that a local label generally will not conflict with the same label used elsewhere in the source program, since
ASM51 appends a numeric code to the local label when the macro is expanded. Furthermore, the next use of the
same local label receives the next numeric code, and so on.
The macro above has a potential " side effect. " The accumulator is used as a temporary holding place for
DPL. If the macro is used within a section of code that uses A for another purpose, the value in A would be lost.
This side effect probably represents a bug in the program. The macro definition could guard against this by saving
A on the stack. Here's an alternate definition for the DEC_DPTR macro:
%*DEFINE
%SKIP:
(DEC_DPTR)
LOCAL SKIP
(PUSHACC
DEC
DPL
;DECREMENT DATA POINTER
MOV A, DPL
CJNE A, #0FFH, %SKIP
DEC
DPH
POP
ACC
)
Repeat Operations
This is one of several built-in (predefined) macros. The format is
%REPEAT
(expression)
(text)
For example, to fill a block of memory with 100 NOP instructions,
%REPEAT (100)
(NOP
)
STC MCU Limited.
Control Flow Operations
The conditional assembly of section of code is provided by ASM51's control flow macro definition. The format is
%IF (expression) THEN (balanced_text)
[ELSE (balanced_text)] FI
For example,
INTRENAL
(INCHAR:
OUTCHR:
(INCHAR:
OUTCHR:
EQU
1
;1 = 8051 SERIAL I/O DRIVERS
;0 = 8251 SERIAL I/O DRIVERS
.
.
%IF (INTERNAL) THEN
.
;8051 DRIVERS
.
.
.
) ELSE
.
;8251 DRIVERS
.
.
.
)
In this example, the symbol INTERNAL is given the value 1 to select I/O subroutines for the 8051's serial port,
or the value 0 to select I/O subroutines for an external UART, in this case the 8251. The IF macro causes ASM51
to assemble one set of drivers and skip over the other. Elsewhere in the program, the INCHAR and OUTCHR
subroutines are used without consideration for the particular hardware configuration. As long as the program as
assembled with the correct value for INTERNAL, the correct subroutine is executed.
STC MCU Limited.
Appendix B: 8051 C Programming
ADVANTAGES AND DISADVANTAGES OF 8051 C
The advantages of programming the 8051 in C as compared to assembly are:
o Offers all the benefits of high-level, structured programming languages such as C, including the ease of
writing subroutines
o Often relieves the programmer of the hardware details that the complier handles on behalf of the
programmer
o Easier to write, especially for large and complex programs
o Produces more readable program source codes
Nevertheless, 8051 C, being very similar to the conventional C language, also suffers from the following
disadvantages:
o Processes the disadvantages of high-level, structured programming languages.
o Generally generates larger machine codes
o Programmer has less control and less ability to directly interact with hardware
To compare between 8051 C and assembly language, consider the solutions to the Example--Write a program
using Timer 0 to create a 1KHz square wave on P1.0.
A solution written below in 8051 C language:
sbit portbit = P1^0;
main ( )
{
TMOD = 1;
while (1)
{
TH0 = 0xFE;
TL0 = 0xC;
TR0 = 1;
while (TF0 !=1);
TR0 = 0;
TF0 = 0;
portbit = !(P1.^0);
}
}
/*Use variable portbit to refer to P1.0*/
A solution written below in assembly language:
LOOP:
WAIT:
ORG
MOV
MOV
MOV
SETB
JNB
CLR
CLR
CPL
SJMP
END
8100H
TMOD, #01H
TH0, #0FEH
TL0, #0CH
TR0
TF0, WAIT
TR0
TF0
P1.0
LOOP
STC MCU Limited.
;16-bit timer mode
;-500 (high byte)
;-500 (low byte)
;start timer
;wait for overflow
;stop timer
;clear timer overflow flag
;toggle port bit
;repeat
Notice that both the assembly and C language solutions for the above example require almost the same number
of lines. However, the difference lies in the readability of these programs. The C version seems more human than
assembly, and is hence more readable. This often helps facilitate the human programmer's efforts to write even
very complex programs. The assembly language version is more closely related to the machine code, and though
less readable, often results in more compact machine code. As with this example, the resultant machine code from
the assembly version takes 83 bytes while that of the C version requires 149 bytes, an increase of 79.5%!
The human programmer's choice of either high-level C language or assembly language for talking to the
8051, whose language is machine language, presents an interesting picture, as shown in following figure.
C (high-level) language
Eg. for (x=0; x & lt; 9; x++)...
Human language
Eg. English, Malay, Chinese
Complier
Machine language
Eg. 10011101 0101010101
Assembly language
Eg. MOV, ADD, SUB
Assembler
Conversion between human, high-level, assembly, and machine language
8051 C COMPILERS
We saw in the above figure that a complier is needed to convert programs written in 8051 C language into
machine language, just as an assembler is needed in the case of programs written in assembly language. A
complier basically acts just like an assembler, except that it is more complex since the difference between C and
machine language is far greater than that between assembly and machine language. Hence the complier faces a
greater task to bridge that difference.
Currently, there exist various 8051 C complier, which offer almost similar functions. All our examples
and programs have been compiled and tested with Keil's ? Vision 2 IDE by Keil Software, an integrated 8051
program development envrionment that includes its C51 cross compiler for C. A cross compiler is a compiler that
normally runs on a platform such as IBM compatible PCs but is meant to compile programs into codes to be run
on other platforms such as the 8051.
DATA TYPES
8051 C is very much like the conventional C language, except that several extensions and adaptations have been
made to make it suitable for the 8051 programming environment. The first concern for the 8051 C programmer is
the data types. Recall that a data type is something we use to store data. Readers will be familiar with the basic C
data types such as int, char, and float, which are used to create variables to store integers, characters, or floatingpoints. In 8051 C, all the basic C data types are supported, plus a few additional data types meant to be used
specifically with the 8051.
The following table gives a list of the common data types used in 8051 C. The ones in bold are the specific
8051 extensions. The data type bit can be used to declare variables that reside in the 8051's bit-addressable
locations (namely byte locations 20H to 2FH or bit locations 00H to 7FH). Obviously, these bit variables can only
store bit values of either 0 or 1. As an example, the following C statement:
bit
flag = 0;
declares a bit variable called flag and initializes it to 0.
STC MCU Limited.
Data types used in 8051 C language
Data Type
bit
signed char
unsigned char
enum
signed short
unsigned short
signed int
unsigned int
signed long
unsigned long
float
sbit
sfr
sfr16
Bits
1
8
8
16
16
16
16
16
32
32
32
1
8
16
Bytes Value Range
0 to 1
1
-128 to +127
1
0 to 255
2
-32768 to +32767
2
-32768 to +32767
2
0 to 65535
2
-32768 to +32767
2
0 to 65535
4
-2,147,483,648 to +2,147,483,647
4
0 to 4,294,967,295
4
?1.175494E-38 to ?3.402823E+38
0 to 1
1
0 to 255
2
0 to 65535
The data type sbit is somewhat similar to the bit data type, except that it is normally used to declare 1-bit
variables that reside in special function registes (SFRs). For example:
sbit
P = 0xD0;
declares the sbit variable P and specifies that it refers to bit address D0H, which is really the LSB of the PSW
SFR. Notice the difference here in the usage of the assignment ( " = " ) operator. In the context of sbit declarations,
it indicatess what address the sbit variable resides in, while in bit declarations, it is used to specify the initial
value of the bit variable.
Besides directly assigning a bit address to an sbit variable, we could also use a previously defined sfr
variable as the base address and assign our sbit variable to refer to a certain bit within that sfr. For example:
sfr
sbit
PSW = 0xD0;
P = PSW^0;
This declares an sfr variable called PSW that refers to the byte address D0H and then uses it as the base address
to refer to its LSB (bit 0). This is then assigned to an sbit variable, P. For this purpose, the carat symbol (^) is used
to specify bit position 0 of the PSW.
A third alternative uses a constant byte address as the base address within which a certain bit is referred. As
an illustration, the previous two statements can be replaced with the following:
sbit
P = 0xD0 ^ 0;
Meanwhile, the sfr data type is used to declare byte (8-bit) variables that are associated with SFRs. The
statement:
sfr
IE = 0xA8;
declares an sfr variable IE that resides at byte address A8H. Recall that this address is where the Interrupt Enable
(IE) SFR is located; therefore, the sfr data type is just a means to enable us to assign names for SFRs so that it is
easier to remember.
The sfr16 data type is very similar to sfr but, while the sfr data type is used for 8-bit SFRs, sfr16 is used for
16-bit SFRs. For example, the following statement:
sfr16
DPTR = 0x82;
STC MCU Limited.
declares a 16-bit variable DPTR whose lower-byte address is at 82H. Checking through the 8051 architecture,
we find that this is the address of the DPL SFR, so again, the sfr16 data type makes it easier for us to refer to
the SFRs by name rather than address. There's just one thing left to mention. When declaring sbit, sfr, or sfr16
variables, remember to do so outside main, otherwise you will get an error.
In actual fact though, all the SFRs in the 8051, including the individual flag, status, and control bits in the
bit-addressable SFRs have already been declared in an include file, called reg51.h, which comes packaged with
most 8051 C compilers. By using reg51.h, we can refer for instance to the interrupt enable register as simply IE
rather than having to specify the address A8H, and to the data pointer as DPTR rather than 82H. All this makes
8051 C programs more human-readable and manageable. The contents of reg51.h are listed below.
/*-------------------------------------------------------------------------------------------------------------------REG51.H
Header file for generic 8051 microcontroller.
-----------------------------------------------------------------------------------------------------------------------*/
sbit
IE1
= 0x8B;
/* BYTE Register */
sbit
IT1
= 0x8A;
sfr
P0
= 0x80;
sbit
IE0
= 0x89;
sfr
P1
= 0x90;
sbit
IT0
= 0x88;
sfr
P2
= 0xA0;
/* IE */
sfr
P3
= 0xB0;
sbit
EA
= 0xAF;
sfr
PSW
= 0xD0;
sbit
ES
= 0xAC;
sfr
ACC
= 0xE0;
sbit
ET1
= 0xAB;
sfr
B
= 0xF0;
sbit
EX1
= 0xAA;
sfr
SP
= 0x81;
sbit
ET0
= 0xA9;
sfr
DPL
= 0x82;
sbit
EX0
= 0xA8;
sfr
DPH
= 0x83;
/* IP */
sfr
PCON = 0x87;
sbit
PS
= 0xBC;
sfr
TCON = 0x88;
sbit
PT1
= 0xBB;
sfr
TMOD = 0x89;
sbit
PX1
= 0xBA;
sfr
TL0
= 0x8A;
sbit
PT0
= 0xB9;
sfr
TL1
= 0x8B;
sbit
PX0
= 0xB8;
sfr
TH0
= 0x8C;
/* P3 */
sfr
TH1
= 0x8D;
sbit
RD
= 0xB7;
sfr
IE
= 0xA8;
sbit
WR
= 0xB6;
sfr
IP
= 0xB8;
sbit
T1
= 0xB5;
sfr
SCON = 0x98;
sbit
T0
= 0xB4;
sfr
SBUF = 0x99;
sbit
INT1
= 0xB3;
/* BIT Register */
sbit
INT0
= 0xB2;
/* PSW */
sbit
TXD
= 0xB1;
sbit
CY
= 0xD7;
sbit
RXD
= 0xB0;
sbit
AC
= 0xD6;
/* SCON */
sbit
F0
= 0xD5;
sbit
SM0
= 0x9F;
sbit
RS1
= 0xD4;
sbit
SM1
= 0x9E;
sbit
RS0
= 0xD3;
sbit
SM2
= 0x9D;
sbit
OV
= 0xD2;
sbit
REN
= 0x9C;
sbit
P
= 0xD0;
sbit
TB8
= 0x9B;
/* TCON */
sbit
RB8
= 0x9A;
sbit
TF1
= 0x8F;
sbit
TI
= 0x99;
sbit
TR1
= 0x8E;
sbit
RI
= 0x98;
sbit
TF0
= 0x8D;
sbit
TR0
= 0x8C;
STC MCU Limited.
MEMORY TYPES AND MODELS
The 8051 has various types of memory space, including internal and external code and data memory. When
declaring variables, it is hence reasonable to wonder in which type of memory those variables would reside. For
this purpose, several memory type specifiers are available for use, as shown in following table.
Memory Type
code
data
idata
bdata
xdata
pdata
Memory types used in 8051 C language
Description (Size)
Code memory (64 Kbytes)
Directly addressable internal data memory (128 bytes)
Indirectly addressable internal data memory (256 bytes)
Bit-addressable internal data memory (16 bytes)
External data memory (64 Kbytes)
Paged external data memory (256 bytes)
The first memory type specifier given in above table is code. This is used to specify that a variable is to reside in
code memory, which has a range of up to 64 Kbytes. For example:
char
code
errormsg[ ] = " An error occurred " ;
declares a char array called errormsg that resides in code memory.
If you want to put a variable into data memory, then use either of the remaining five data memory specifiers
in above table. Though the choice rests on you, bear in mind that each type of data memory affect the speed of
access and the size of available data memory. For instance, consider the following declarations:
signed int data num1;
bit bdata numbit;
unsigned int xdata num2;
The first statement creates a signed int variable num1 that resides in inernal data memory (00H to 7FH). The next
line declares a bit variable numbit that is to reside in the bit-addressable memory locations (byte addresses 20H
to 2FH), also known as bdata. Finally, the last line declares an unsigned int variable called num2 that resides in
external data memory, xdata. Having a variable located in the directly addressable internal data memory speeds
up access considerably; hence, for programs that are time-critical, the variables should be of type data. For other
variants such as 8052 with internal data memory up to 256 bytes, the idata specifier may be used. Note however
that this is slower than data since it must use indirect addressing. Meanwhile, if you would rather have your
variables reside in external memory, you have the choice of declaring them as pdata or xdata. A variable declared
to be in pdata resides in the first 256 bytes (a page) of external memory, while if more storage is required, xdata
should be used, which allows for accessing up to 64 Kbytes of external data memory.
What if when declaring a variable you forget to explicitly specify what type of memory it should reside in, or
you wish that all variables are assigned a default memory type without having to specify them one by one? In this
case, we make use of memory models. The following table lists the various memory models that you can use.
Memory Model
Small
Compact
Large
Memory models used in 8051 C language
Description
Variables default to the internal data memory (data)
Variables default to the first 256 bytes of external data memory (pdata)
Variables default to external data memory (xdata)
STC MCU Limited.
A program is explicitly selected to be in a certain memory model by using the C directive, #pragma. Otherwise,
the default memory model is small. It is recommended that programs use the small memory model as it allows for
the fastest possible access by defaulting all variables to reside in internal data memory.
The compact memory model causes all variables to default to the first page of external data memory while
the large memory model causes all variables to default to the full external data memory range of up to 64 Kbytes.
ARRAYS
Often, a group of variables used to store data of the same type need to be grouped together for better readability.
For example, the ASCII table for decimal digits would be as shown below.
Decimal Digit
0
1
2
3
4
5
6
7
8
9
ASCII table for decimal digits
ASCII Code In Hex
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
To store such a table in an 8051 C program, an array could be used. An array is a group of variables of the same
data type, all of which could be accessed by using the name of the arrary along with an appropriate index.
The array to store the decimal ASCII table is:
int
table [10] =
{0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39};
Notice that all the elements of an array are separated by commas. To access an individul element, an index
starting from 0 is used. For instance, table[0] refers to the first element while table[9] refers to the last element in
this ASCII table.
STRUCTURES
Sometime it is also desired that variables of different data types but which are related to each other in some way
be grouped together. For example, the name, age, and date of birth of a person would be stored in different types
of variables, but all refer to the person's personal details. In such a case, a structure can be declared. A structure is
a group of related variables that could be of different data types. Such a structure is declared by:
struct
person {
char name;
int age;
long DOB;
};
Once such a structure has been declared, it can be used like a data type specifier to create structure variables that
have the member's name, age, and DOB. For example:
struct
STC MCU Limited.
person
grace = { " Grace " , 22, 01311980};
would create a structure variable grace to store the name, age, and data of birth of a person called Grace. Then in
order to access the specific members within the person structure variable, use the variable name followed by the
dot operator (.) and the member name. Therefore, grace.name, grace.age, grace.DOB would refer to Grace's name,
age, and data of birth, respectively.
POINTERS
When programming the 8051 in assembly, sometimes register such as R0, R1, and DPTR are used to store
the addresses of some data in a certain memory location. When data is accessed via these registers, indirect
addressing is used. In this case, we say that R0, R1, or DPTR are used to point to the data, so they are essentially
pointers.
Correspondingly in C, indirect access of data can be done through specially defined pointer variables. Pointers are simply just special types of variables, but whereas normal variables are used to directly store data, pointer
variables are used to store the addresses of the data. Just bear in mind that whether you use normal variables or
pointer variables, you still get to access the data in the end. It is just whether you go directly to where it is stored
and get the data, as in the case of normal variables, or first consult a directory to check the location of that data
before going there to get it, as in the case of pointer variables.
Declaring a pointer follows the format:
data_type
where
*pointer_name;
data_type
*
pointer_name
refers to which type of data that the pointer is pointing to
denotes that this is a pointer variable
is the name of the pointer
As an example, the following declarations:
int * numPtr
int num;
numPtr = & num;
first declares a pointer variable called numPtr that will be used to point to data of type int. The second declaration
declares a normal variable and is put there for comparison. The third line assigns the address of the num variable
to the numPtr pointer. The address of any variable can be obtained by using the address operator, & , as is used in
this example. Bear in mind that once assigned, the numPtr pointer contains the address of the num variable, not
the value of its data.
The above example could also be rewritten such that the pointer is straightaway initialized with an address
when it is first declared:
int
int
num;
* numPtr = & num;
In order to further illustrate the difference between normal variables and pointer variables, consider the
following, which is not a full C program but simply a fragment to illustrate our point:
int num = 7;
int * numPtr = & num;
printf ( " %d\n " , num);
printf ( " %d\n " , numPtr);
printf ( " %d\n " , & num);
printf ( " %d\n " , *numPtr);
STC MCU Limited.
The first line declare a normal variable, num, which is initialized to contain the data 7. Next, a pointer variable,
numPtr, is declared, which is initialized to point to the address of num. The next four lines use the printf( )
function, which causes some data to be printed to some display terminal connected to the serial port. The first
such line displays the contents of the num variable, which is in this case the value 7. The next displays the
contents of the numPtr pointer, which is really some weird-looking number that is the address of the num variable.
The third such line also displays the addresss of the num variable because the address operator is used to obtain
num's address. The last line displays the actual data to which the numPtr pointer is pointing, which is 7. The *
symbol is called the indirection operator, and when used with a pointer, indirectly obtains the data whose address
is pointed to by the pointer. Therefore, the output display on the terminal would show:
7
13452 (or some other weird-looking number)
13452 (or some other weird-looking number)
7
A Pointer's Memory Type
Recall that pointers are also variables, so the question arises where they should be stored. When declaring
pointers, we can specify different types of memory areas that these pointers should be in, for example:
int * xdata numPtr = & num;
This is the same as our previous pointer examples. We declare a pointer numPtr, which points to data of type int
stored in the num variable. The difference here is the use of the memory type specifier xdata after the *. This is
specifies that pointer numPtr should reside in external data memory (xdata), and we say that the pointer's memory
type is xdata.
Typed Pointers
We can go even further when declaring pointers. Consider the example:
int data * xdata numPtr = & num;
The above statement declares the same pointer numPtr to reside in external data memory (xdata), and this pointer
points to data of type int that is itself stored in the variable num in internal data memory (data). The memory type
specifier, data, before the * specifies the data memory type while the memory type specifier, xdata, after the *
specifies the pointer memory type.
Pointer declarations where the data memory types are explicitly specified are called typed pointers. Typed
pointers have the property that you specify in your code where the data pointed by pointers should reside. The
size of typed pointers depends on the data memory type and could be one or two bytes.
Untyped Pointers
When we do not explicitly state the data memory type when declaring pointers, we get untyped pointers, which
are generic pointers that can point to data residing in any type of memory. Untyped pointers have the advantage
that they can be used to point to any data independent of the type of memory in which the data is stored. All
untyped pointers consist of 3 bytes, and are hence larger than typed pointers. Untyped pointers are also generally
slower because the data memory type is not determined or known until the complied program is run at runtime.
The first byte of untyped pointers refers to the data memory type, which is simply a number according to the
following table. The second and third bytes are,respectively,the higher-order and lower-order bytes of the address
being pointed to.
An untyped pointer is declared just like normal C, where:
int * xdata numPtr = & num;
does not explicitly specify the memory type of the data pointed to by the pointer. In this case, we are using
untyped pointers.
STC MCU Limited.
Data memory type values stored in first byte of untyped pointers
Value
Data Memory Type
1
idata
2
xdata
3
pdata
4
data/bdata
5
code
FUNCTIONS
In programming the 8051 in assembly, we learnt the advantages of using subroutines to group together common
and frequently used instructions. The same concept appears in 8051 C, but instead of calling them subroutines, we
call them functions. As in conventional C, a function must be declared and defined. A function definition includes
a list of the number and types of inputs, and the type of the output (return type), puls a description of the internal
contents, or what is to be done within that function.
The format of a typical function definition is as follows:
return_type function_name (arguments)
{
...
}
[memory] [reentrant] [interrupt] [using]
where
return_type
function_name
arguments
memory
reentrant
interrupt
using
refers to the data type of the return (output) value
is any name that you wish to call the function as
is the list of the type and number of input (argument) values
refers to an explicit memory model (small, compact or large)
refers to whether the function is reentrant (recursive)
indicates that the function is acctually an ISR
explicitly specifies which register bank to use
Consider a typical example, a function to calculate the sum of two numbers:
int sum (int a, int b)
{
return a + b;
}
This function is called sum and takes in two arguments, both of type int. The return type is also int, meaning that
the output (return value) would be an int. Within the body of the function, delimited by braces, we see that the
return value is basically the sum of the two agruments. In our example above, we omitted explicitly specifying the
options: memory, reentrant, interrupt, and using. This means that the arguments passed to the function would be
using the default small memory model, meaning that they would be stored in internal data memory. This function
is also by default non-recursive and a normal function, not an ISR. Meanwhile, the default register bank is bank 0.
Parameter Passing
In 8051 C, parameters are passed to and from functions and used as function arguments (inputs). Nevertheless, the
technical details of where and how these parameters are stored are transparent to the programmer, who does not
need to worry about these techinalities. In 8051 C, parameters are passed through the register or through memory.
Passing parameters through registers is faster and is the default way in which things are done. The registers used
and their purpose are described in more detail below.
STC MCU Limited.
Registers used in parameter passing
Number of Argument Char / 1-Byte Pointer INT / 2-Byte Pointer Long/Float
1
R7
R6 & R7
R4-R7
2
R5
R4 & R5
R4-R7
3
R3
R2 & R3
Generic Pointer
R1-R3
Since there are only eight registers in the 8051, there may be situations where we do not have enough registers for parameter passing. When this happens, the remaining parameters can be passed through fixed memory
loacations. To specify that all parameters will be passed via memory, the NOREGPARMs control directive is
used. To specify the reverse, use the REGPARMs control directive.
Return Values
Unlike parameters, which can be passed by using either registers or memory locations, output values must be
returned from functions via registers. The following table shows the registers used in returning different types of
values from functions.
Registers used in returning values from functions
Return Type
Register
Description
bit
Carry Flag (C)
char/unsigned char/1-byte pointer R7
int/unsigned int/2-byte pointer
R6 & R7
MSB in R6, LSB in R7
long/unsigned long
R4-R7
MSB in R4, LSB in R7
float
R4-R7
32-bit IEEE format
generic pointer
R1-R3
Memory type in R3, MSB in R2, LSB in R1
STC MCU Limited.
Appendix C: STC90xx series Electrical Characteristics
Absolute Maximum Ratings
Symbol
Min
Max
Srotage temperature
Parameter
TST
-55
+125
Operating temperature (I)
TA
-40
+85
Operating temperature (C)
Unit
TA
0
+70
DC power supply (5V)
VDD - VSS
-0.3
+6.0
V
DC power supply (3V)
VDD - VSS
-0.3
+4.0
V
-
-0.5
+ 5.5
V
Voltage on any pin
DC Specification (5V MCU)
Sym
Parameter
Specification
Min.
Typ
Max.
Unit
Test Condition
VDD
Operating Voltage
3.8
5.0
5.5
V
IPD
Power Down Current
-
& lt; 0.1
-
uA
5V
IIDL
Idle Current
-
2.0
-
mA
5V
ICC
Operating Current
-
4
20
mA
5V
VIL1
Input Low (P0,P1,P2,P3, P4)
-
-
0.8
V
5V
VIL2
Input Low voltage (RESET, XTAL1)
-
-
1.5
V
5V
VIH1
Input High (P0,P1,P2,P3, P4, /EA)
2.0
-
-
V
5V
VIH2
Input High (RESET)
3.0
-
-
V
5V
IOL1
Sinking Current for output low (P1,P2,P3,P4)
4
6
-
mA
5V
IOL2
Sinking Current for output low(P0,ALE,PSEN)
8
12
mA
5V
IOH1
Sourcing Current for output high (P1,P2,P3,P4)
150
220
-
uA
5V
IOH2
Sourcing Current for output high (ALE,PSEN)
14
20
-
mA
5V
IIL
Logic 0 input current (P1,P2,P3,P4)
-
18
50
uA
Vpin=0V
ITL
Logic 1 to 0 transition current (P1,P2,P3,P4)
-
270
600
uA
Vpin=2.0V
STC MCU Limited.
DC Specification (3V MCU)
Sym
Parameter
Specification
Min.
Typ
Max.
Unit
Test Condition
VDD
Operating Voltage
2.4
3.3
3.8
V
IPD
Power Down Current
-
& lt; 0.1
-
uA
3.3V
IIDL
Idle Current
-
2.0
-
mA
3.3V
ICC
Operating Current
-
4
15
mA
3.3V
VIL1
Input Low (P0,P1,P2,P3,P4)
-
-
0.8
V
3.3V
VIL2
Input Low (RESET, XTAL1)
-
-
1.5
V
3.3V
VIH1
Input High (P0,P1,P2,P3)
2.0
-
-
V
3.3V
VIH2
Input High (RESET)
3.0
-
-
V
3.3V
IOL1
Sink Current for output low (P1,P2,P3,P4)
2.5
4
-
mA
3.3V
IOL2
Sink Current for output low (P0,ALE,PSEN)
5
8
-
mA
3.3V
IOH1
Sourcing Current for output high (P1,P2,P3,P4)
40
70
-
uA
3.3V
IOH2
Sourcing Current for output high (ALE,PSEN)
8
13
-
mA
3.3V
IIL
Logic 0 input current (P1,P2,P3,P4)
-
8
50
uA
Vpin=0V
ITL
Logic 1 to 0 transition current (P1,P2,P3,P4)
-
110
600
uA
Vpin=2.0V
STC MCU Limited.
Appendix D: Program for indirect addressing inner 256B RAM
;/*---------------------------------------------------------------------------------------------------------------*/
;/* --- STC MCU International Limited ------------------------------------------------------------------*/
;/* --- STC90xx Series MCU the inner 256B normal RAM (indirect addressing) Demo -----------*/
;/* If you want to use the program or the program referenced in the --------------------------------*/
;/* article, please specify in which data and procedures from STC --------------------------------*/
;/*--------------------------------------------------------------------------------------------------------------*/
TEST_CONST
;TEST_RAM
ORG
LJMP
EQU
5AH
EQU
03H
0000H
INITIAL
ORG
0050H
MOV
R0,
INITIAL:
MOV
R1,
TEST_ALL_RAM:
MOV
R2,
TEST_ONE_RAM:
MOV
A,
MOV
@R1,
CLR
A
MOV
A,
CJNE
DJNZ
INC
DJNZ
OK_DISPLAY:
MOV
Wait1:
SJMP
#253
#3H
#0FFH
R2
A
@R1
A,
R2,
R1
R0,
2H,
ERROR_DISPLAY
TEST_ONE_RAM
P1,
#11111110B
TEST_ALL_RAM
Wait1
ERROR_DISPLAY:
MOV
A,
MOV
P1,
Wait2:
SJMP
Wait2
END
R1
A
STC MCU Limited.
Appendix E: Using Serial port expand I/O interface
STC90C51RC/RD+ series MCU serial port mode0 can be used for expand IO if UART is free in your application.
UART Mode0 is a synchronous shift register, the baudrate is fixed at fosc/12, RXD pin (P3.0) is the data I/O port,
and TXD pin (P3.1) is clock output port, data width is 8 bits, always sent / received the lowest bit at first.
(1) Using 74HC165 expand parallel input ports
Please refer to the following circuit which using 2 pcs 74HC165 to expand 16 input I/Os
89Cxx
6
P3.0
9
P3.1
7
P1.0
5
4
3
14
13
12
11
H G F E D C B A
QH
QH
SIN
74HC165
S/L
1
6
10
7
CP
15
2
9
16
8
104
Vcc
5
4
3
14
13
12
11
H G F E D C B A
QH
QH
SIN
74HC165
S/L
1
10
CP
15
2
8
16
104
Vcc
74HC165 is a 8-bit parallel input shift register, when S/L (Shift/Load) pin is falling to low level, the parallel port
data is read into internal register, and now, if S/L is raising to high and ClockDisable pin (15 pin) is low level,
then clock signal from CP pin is enable. At this time register data will be output from the Dh pin (9 pin) with the
clock input.
...
MOV R7,#05H
;read 5 groups data
MOV R0,#20H
;set buffer address
START: CLR P1.0
;S/L = 0, load port data
SETB P1.0
;S/L = 1, lock data and enable clock
MOV R1,#02H
;2 bytes per group
RXDAT:MOV SCON,#00010000B
;set serial as mode 0 and enable receive data
WAIT: JNB RI,WAIT
;wait for receive complete
CLR RI
;clear receive complete flag
MOV A,SBUF
;read data to ACC
MOV @R0,A
;save data to buffer
INC R0
;modify buffer ptr
DJNZ R1,RXDAT
;read next byte
DJNZ R7,START
;read next group
...
STC MCU Limited.
(2) Using 74HC164 expand parallel output ports
Please refer to the following circuit which using 2 pcs 74HC164 to expand 16 output I/Os
12Cxx
3
P3.0
P3.1
P1.0
4
5
6
10
11
12
13
Q A QB QC QD QE QF QG QH
A,B
74HC164
14
Vcc
104
3
1,2
7 Gnd
CLR
CP
9
4
5
6
10
11
12
13
QA QB Q C QD QE Q F QG QH
A,B
14
74HC164
Vcc
1,2
104
7 Gnd
8
CLR
CP
9
8
When serial port is working in MODE0, the serial data is input/output from RXD(P3.0) pin and serial clock is
output from TXD(P3.1). Serial data is always starting transmission from the lowest bit.
...
START: MOV R7,#02H
MOV R0,#30H
MOV SCON,#00000000B
SEND: MOV A,@R0
MOV SBUF,A
WAIT: JNB TI,WAIT
CLR TI
INC R0
DJNZ R7,SEND
...
STC MCU Limited.
;output 2 bytes data
;set buffer address
;set serial as mode 0
;read data from buffer
;start send data
;wait for send complete
;clear send complete flag
;modify buffer ptr
;send next data
Appendix F: Use STC MCU common I/O driving LCD Display
Vcc
21K
38
37
36
35
VCC
34
P2.6
30
Seg22
P2.5
29
Seg21
& lt; 33pF
27
28
Seg19
Seg20
P2.3
26
Seg18
P2.1
25
P2.1
24
Seg16
P3.7
& lt; 33pF
20
P3.6
19
P2.0
P3.3
P2.4
ALE 33
PSEN 32
P2.7 31
Seg23
Seg7
Seg5
Seg6
Seg4
P0.3
41 Seg2
40
P0.2
43 Seg0
42 Seg1
P0.1
P0.0
3
44
Seg8
VDD
Seg9
3
1
P4.2
39
P4.1
P3.1
P3.2
18
5.6K R6
5.6K R7
Com2
5.6K R5
Com1
5.6K R3
5.6K R4
5.6K R2
Com0
P1.0
Seg10
4
8051
P4.3
P3.4
17 P3.5
STC MCU Limited.
P1.1
Seg11
5
EA
Seg17
16
P3.0
P4.0
15
RST
P0.7
VSS
14
P0.6
23
13
P1.7
22
12
P0.4
P0.5
XTAL1
11
R1
10K
Seg3
P1.6
21
10
P1.2
9
P1.5
XTAL2
8
Seg15
C1
10?F
7
Seg14
P1.3
Seg12
Seg13
VCC
P1.4
6
U2
Com0
Com1
Seg0
Seg1
Seg2
Seg3
Seg4
Seg5
Seg6
Seg7
Seg8
Seg9
Seg10
Seg11
Seg12
Seg13
Seg14
Seg15
Seg16
Seg17
Seg18
Seg19
Seg20
Seg21
Seg22
Seg23
Com2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Com0
Com1
Seg0
Seg1
Seg2
Seg3
Seg4
Seg5
Seg6
Seg7
Seg8
Seg9
Seg10
Seg11
Seg12
Seg13
Seg14
Seg15
Seg16
Seg17
Seg18
Seg19
Seg20
Seg21
Seg22
Seg23
Com2
NAME LcdDriver
#include & lt; reg52.h & gt;
;********************************************************************************
;the LCD is 1/3 duty and 1/3 bias; 3Com*24Seg; 9 display RAM;
;
;
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
;Com0: Com0Data0:
Seg7
Seg6
Seg5
Seg4
Seg3
Seg2
Seg1
Seg0
;
Com0Data1:
Seg15 Seg14 Seg13 Seg12 Seg11 Seg10 Seg9
Seg8
;
Com0Data2:
Seg23 Seg22 Seg21 Seg20 Seg19 Seg18 Seg17 Seg16
;Com1: Com1Data0:
Seg7
Seg6
Seg5
Seg4
Seg3
Seg2
Seg1
Seg0
;
Com1Data1:
Seg15 Seg14 Seg13 Seg12 Seg11 Seg10 Seg9
Seg8
;
Com1Data2:
Seg23 Seg22 Seg21 Seg20 Seg19 Seg18 Seg17 Seg16
;Com2: Com2Data0:
Seg7
Seg6
Seg5
Seg4
Seg3
Seg2
Seg1
Seg0
;
Com2Data1:
Seg15 Seg14 Seg13 Seg12 Seg11 Seg10 Seg9
Seg8
;
Com2Data2:
Seg23 Seg22 Seg21 Seg20 Seg19 Seg18 Seg17 Seg16
;********************************************************************************
;Com0: P3^0,P3^1 when P3^0 = P3^1 = 1
then Com0=VCC(=5V);
;
P3^0 = P3^1 = 0
then Com0=GND(=0V);
;
P3^0 = 1, P3^1=0
then Com0=1/2 VCC;
;Com1: P3^2,P3^3 the same as the Com0
;Com2: P3^4,P3^5 the same as the Com0
;
sbit
sbit
sbit
sbit
sbit
sbit
sbit
sbit
sbit
sbit
sbit
SEG0 =P0^0
SEG1 =P0^1
SEG2 =P0^2
SEG3 =P0^3
SEG4 =P0^4
SEG5 =P0^5
SEG6 =P0^6
SEG7 =P0^7
SEG8 =P1^0
SEG9 =P1^1
SEG10 =P1^2
STC MCU Limited.
sbit
SEG11 =P1^3
sbit
SEG12 =P1^4
sbit
SEG13 =P1^5
sbit
SEG14 =P1^6
sbit
SEG15 =P1^7
sbit
SEG16 =P2^0
sbit
SEG17 =P2^1
sbit
SEG18 =P2^2
sbit
SEG19 =P2^3
sbit
SEG20 =P2^4
sbit
SEG21 =P2^5
sbit
SEG22 =P2^6
sbit
SEG23 =P2^7
;*********************************************************************************
;======Interrupt===============================
CSEG
AT
0000H
LJMP
start
CSEG
LJMP
AT
int_t0
000BH
;======register===============================
lcdd_bit SEGMENT BIT
RSEG lcdd_bit
OutFlag:
DBIT 1
;the output display reverse flag
lcdd_data SEGMENT DATA
RSEG lcdd_data
Com0Data0: DS 1
Com0Data1: DS 1
Com0Data2: DS 1
Com1Data0: DS 1
Com1Data1: DS 1
Com1Data2: DS 1
Com2Data0: DS 1
Com2Data1: DS 1
Com2Data2: DS 1
TimeS:
DS 1
STC MCU Limited.
;======Interrupt Code==========================
t0_int SEGMENT
CODE
RSEG t0_int
USING 1
;*****************************************************************
;Time0 interrupt
;ths system crystalloid is 22.1184MHz
;the time to get the Time0 interrupr is 2.5mS
;the whole duty is 2.5mS*6=15mS, including reverse
;*****************************************************************
int_t0:
ORL
TL0,#00H
MOV TH0,#0EEH
PUSH ACC
PUSH PSW
MOV PSW,#08H
ACALL OutData
POP
PSW
POP
ACC
RETI
;======SUB CODE================================
uart_sub SEGMENT CODE
RSEG uart_sub
USING 0
;******************************************************************
;initial the display RAM data
;if want to display other,then you may add other data to this RAM
;Com0: Com0Data0,Com0Data1,Com0Data2
;Com1: Com1Data0,Com1Data1,Com1Data2
;Com2: Com2Data0,Com0Data1,Com0Data2
;*******************************************************************
InitComData:
;it will display " 11111111 "
MOV Com0Data0,
#24H
MOV Com0Data1,
#49H
MOV Com0Data2,
#92H
STC MCU Limited.
MOV
MOV
MOV
MOV
MOV
MOV
RET
Com1Data0,
Com1Data1,
Com1Data2,
Com2Data0,
Com2Data1,
Com2Data2,
#92H
#24H
#49H
#00H
#00H
#00H
;********************************************************************
;reverse the display data
;********************************************************************
RetComData:
MOV R0,
#Com0Data0
;get the first data address
MOV R7,
#9
RetCom_0:
MOV A,
@R0
CPL
A
MOV @R0, A
INC
R0
DJNZ R7,
RetCom_0
RET
;**********************************************************************
;get the display Data and send to Output register
;**********************************************************************
OutData:
INC
TimeS
MOV A,
TimeS
MOV P3,
#11010101B
;clear display,all Com are 1/2VCC and invalidate
CJNE A,
#01H, OutData_1
;judge the duty
MOV P0,
Com0Data0
MOV P1,
Com0Data1
MOV P2,
Com0Data2
JNB
OutFlag,OutData_00
MOV P3,
#11010111B
;Com0 is work and is VCC
RET
STC MCU Limited.
OutData_00:
MOV P3,
#11010100B
;Com0 is work and is GND
RET
OutData_1:
CJNE A,
#02H,OutData_2
MOV P0,
Com1Data0
MOV P1,
Com1Data1
MOV P2,
Com1Data2
JNB
OutFlag,OutData_10
MOV P3,
#11011101B
;Com1 is work and is VCC
RET
OutData_10:
MOV P3,
#11010001B
;Com1 is work and is GND
RET
OutData_2:
MOV P0,
Com2Data0
MOV P1,
Com2Data1
MOV P2,
Com2Data2
JNB
OutFlag,OutData_20
MOV P3,
#11110101B
;Com2 is work and is VCC
SJMP OutData_21
OutData_20:
MOV P3,#11000101B
;Com2 is work and is GND
OutData_21:
MOV TimeS, #00H
ACALL RetComData
CPL
OutFlag
RET
;======Main Code===============================
uart_main SEGMENT CODE
RSEG uart_main
USING 0
STC MCU Limited.
start:
MOV SP,#40H
CLR OutFlag
MOV TimeS,#00H
MOV TL0,#00H
MOV TH0,#0EEH
MOV TMOD,#01H
MOV IE,#82H
ACALL InitComData
SETB TR0
Main:
NOP
SJMP
END
STC MCU Limited.
Main
Appendix G: LED driven by an I/O port and Key Scan
Vcc
10K
1K
P1.7
1K
Vcc
10K
1K
P1.6
1K
It can save a lot of I/O ports that STC90C51RC/RD+ MCU I/O ports can used as the LED drivers and key
detection concurrently because of their feature which they can be set to the weak pull , the strong pull (push-pull)
output, only input (high impedance), open drain four modes.
When driving the LED, the I/O port should be set as strongly push-pull output, and the LED will be lighted when
the output is high.
When testing the keys, the I/O port should be set as weak pull input, and then reading the status of external ports
can test the keys.
STC MCU Limited.
Appendix H: How to reduce the Length of Code using Keil C
Setting as shown below in Keil C can maximum reduce about 10K to the length of original code
1. Choose the " Options for Target " in " Project " menu
2. Choose the option " C51 " in " Options for Target "
3. Code Optimization, 9 common block subroutines
4. Click " OK " , compile the program once again.
STC MCU Limited.