Taaaa, Pierwsze koty za płoty :-). Na samym początku walki z lf2401 udało mi się skutecznie zablokować procesor hasłem :-) jednak wspomagany radą i doświadczeniem coberr-a i walce do późnych godzin wieczornych udało sie odblokowac procesor. Następny dzień nie był jednak lepszy co zaowocowało wertowaniem not katalogowyxh i kolejnych próbach uwieńczonych uzyskaniem stabilnego przebiegu prostokątnego na pinie XF potwierdzonego w testach !!. Dlaczego tak długo, a dlatego że chłopcy z TI potrafią skutecznie namieszać w rejestrach :D przez o procesor na poczatku staje się "niedostępny". Porównując pracę z '51 i namotanym AVR-em z DSP to czysta przyjeność na korzyść tych pierwszych. Jednak "szybkość pracy" (chodzi mi o MIPS-y) i możliwości jakie daje DSP-ek rekompensuje godziny przeznaczone na testy i wertowanie pdf_ów. Poniżej zamieszczam pliki źródłowe i wszystko co jest potrzebne aby ruszyć ten procesor z poziomu asemblera (oczywiście) i ładowania kodu przez RS-232. Bym zapomniał, Sanjuro dzięki a CC, zassałem ponownie i jest OK.
;************************************************************
; vector.h
; Deklaracja wektorow przerwan
;************************************************************
.sect " .vectors "
RSVECT B START ; Reset Vector
;;INT1 B 00002h ; Interrupt Level 1
INT1 B START ; Interrupt Level 1
INT2 B 00004h ; Interrupt Level 2
INT3 B 00006h ; Interrupt Level 3
INT4 B 00008h ; Interrupt Level 4
INT5 B 0000Ah ; Interrupt Level 5
INT6 B 0000Ch ; Interrupt Level 6
RESERVED B PHANTOM ; Reserved
SW_INT8 B PHANTOM ; Software Interrupt
SW_INT9 B PHANTOM ; Software Interrupt
SW_INT10 B PHANTOM ; Software Interrupt
SW_INT11 B PHANTOM ; Software Interrupt
SW_INT12 B PHANTOM ; Software Interrupt
SW_INT13 B PHANTOM ; Software Interrupt
SW_INT14 B PHANTOM ; Software Interrupt
SW_INT15 B PHANTOM ; Software Interrupt
SW_INT16 B PHANTOM ; Software Interrupt
TRAP B PHANTOM ; Trap vector
NMI B NMI ; Nonmaskable Interrupt
EMU_TRAP B PHANTOM ; Emulator Trap
SW_INT20 B PHANTOM ; Software Interrupt
SW_INT21 B PHANTOM ; Software Interrupt
SW_INT22 B PHANTOM ; Software Interrupt
SW_INT23 B PHANTOM ; Software Interrupt
SW_INT24 B PHANTOM ; Software Interrupt
SW_INT25 B PHANTOM ; Software Interrupt
SW_INT26 B PHANTOM ; Software Interrupt
SW_INT27 B PHANTOM ; Software Interrupt
SW_INT28 B PHANTOM ; Software Interrupt
SW_INT29 B PHANTOM ; Software Interrupt
SW_INT30 B PHANTOM ; Software Interrupt
SW_INT31 B PHANTOM ; Software Interrupt
; Codesecurity passwords are stored from 40h 43h
.word 0000h ; Replace values with
.word 0000h ; codesecurity passwords
.word 0000h
.word 0000h
;************************************************************************
; LF2401.h
;
;************************************************************************
; LF2401 CPU core registers
IMR .set 0004h ; Interrupt Mask Register
IFR .set 0006h ; Interrupt Flag Register
; System configuration and interrupt registers
SCSR1 .set 7018h ; System Control & Status register. 1
SCSR2 .set 7019h ; System Control & Status register. 2
SCSR4 .set 701Bh ; System Control & Status register. 4
DINR .set 701Ch ; Device Identification Number register.
PIVR .set 701Eh ; Peripheral Interrupt Vector register.
PIRQR0 .set 7010h ; Peripheral Interrupt Request register 0
PIRQR1 .set 7011h ; Peripheral Interrupt Request register 1
PIRQR2 .set 7012h ; Peripheral Interrupt Request register 2
PIACKR0 .set 7014h ; Peripheral Interrupt Acknowledge register 0
PIACKR1 .set 7015h ; Peripheral Interrupt Acknowledge register 1
PIACKR2 .set 7016h ; Peripheral Interrupt Acknowledge register 2
; External interrupt configuration registers
XINT1CR .set 7070h ; External interrupt 1 control register
XINT2CR .set 7071h ; External interrupt 2 control register
; Digital I/O registers
MCRA .set 7090h ; I/O Mux Control Register A
MCRB .set 7092h ; I/O Mux Control Register B
MCRC .set 7094h ; I/O Mux Control Register C
PADATDIR .set 7098h ; I/O port A Data & Direction register
PBDATDIR .set 709Ah ; I/O port B Data & Direction register
PCDATDIR .set 709Ch ; I/O port C Data & Direction register
PDDATDIR .set 709Eh ; I/O port D Data & Direction register
PEDATDIR .set 7095h ; I/O port E Data & Direction register
PFDATDIR .set 7096h ; I/O port F Data & Direction register
; Watchdog (WD) registers
WDCNTR .set 7023h ; WD Counter register
WDKEY .set 7025h ; WD Key register
WDCR .set 7029h ; WD Control register
; ADC registers
ADCTRL1 .set 70A0h ; ADC Control register 1
ADCTRL2 .set 70A1h ; ADC Control register 2
MAXCONV .set 70A2h ; Maximum conversion channels register
CHSELSEQ1 .set 70A3h ; Channel select Sequencing control register 1
CHSELSEQ2 .set 70A4h ; Channel select Sequencing control register 2
CHSELSEQ3 .set 70A5h ; Channel select Sequencing control register 3
CHSELSEQ4 .set 70A6h ; Channel select Sequencing control register 4
AUTO_SEQ_SR .set 70A7h ; Autosequence status register
RESULT0 .set 70A8h ; Conversion result register 0
RESULT1 .set 70A9h ; Conversion result register 1
RESULT2 .set 70Aah ; Conversion result register 2
RESULT3 .set 70Abh ; Conversion result register 3
RESULT4 .set 70Ach ; Conversion result register 4
RESULT5 .set 70Adh ; Conversion result register 5
RESULT6 .set 70Aeh ; Conversion result register 6
RESULT7 .set 70Afh ; Conversion result register 7
RESULT8 .set 70B0h ; Conversion result register 8
RESULT9 .set 70B1h ; Conversion result register 9
RESULT10 .set 70B2h ; Conversion result register 10
RESULT11 .set 70B3h ; Conversion result register 11
RESULT12 .set 70B4h ; Conversion result register 12
RESULT13 .set 70B5h ; Conversion result register 13
RESULT14 .set 70B6h ; Conversion result register 14
RESULT15 .set 70B7h ; Conversion result register 15
;;;;CALIBRATION .set 70B8h ; Calibration result, used to correct
; SCI registers
SCICCR .set 7050h ; SCI Communication control register
SCICTL1 .set 7051h ; SCI Control register 1
SCIHBAUD .set 7052h ; SCI Baud Rate MS byte register
SCILBAUD .set 7053h ; SCI Baud Rate LS byte register
SCICTL2 .set 7054h ; SCI Control register 2
SCIRXST .set 7055h ; SCI Receiver Status register
SCIRXEMU .set 7056h ; SCI Emulation Data Buffer register
SCIRXBUF .set 7057h ; SCI Receiver Data buffer register
SCITXBUF .set 7059h ; SCI Transmit Data buffer register
SCIPRI .set 705Fh ; SCI Priority control register
; Event Manager A (EVA) registers
GPTCONA .set 7400h ; GP Timer control register A
T1CNT .set 7401h ; GP Timer 1 counter register
T1CMPR .set 7402h ; GP Timer 1 compare register
T1PR .set 7403h ; GP Timer 1 period register
T1CON .set 7404h ; GP Timer 1 control register
T2CNT .set 7405h ; GP Timer 2 counter register
T2CMPR .set 7406h ; GP Timer 2 compare register
T2PR .set 7407h ; GP Timer 2 period register
T2CON .set 7408h ; GP Timer 2 control register
COMCONA .set 7411h ; Compare control register A
ACTRA .set 7413h ; Full compare Action control register A
DBTCONA .set 7415h ; Dead-band timer control register A
CMPR1 .set 7417h ; Full compare unit compare register1
CMPR2 .set 7418h ; Full compare unit compare register2
CMPR3 .set 7419h ; Full compare unit compare register3
CAPCONA .set 7420h ; Capture control register A
CAPFIFOA .set 7422h ; Capture FIFO status register A
CAP1FIFO .set 7423h ; Capture Channel 1 FIFO Top
CAP2FIFO .set 7424h ; Capture Channel 2 FIFO Top
CAP3FIFO .set 7425h ; Capture Channel 3 FIFO Top
CAP1FBOT .set 7427h ; Bottom reg. of capture FIFO stack 1
CAP2FBOT .set 7428h ; Bottom reg. of capture FIFO stack 2
CAP3FBOT .set 7429h ; Bottom reg. of capture FIFO stack 3
EVAIMRA .set 742Ch ; Group A Interrupt Mask Register
EVAIMRB .set 742Dh ; Group B Interrupt Mask Register
EVAIMRC .set 742Eh ; Group C Interrupt Mask Register
EVAIFRA .set 742Fh ; Group A Interrupt Flag Register
EVAIFRB .set 7430h ; Group B Interrupt Flag Register
EVAIFRC .set 7431h ; Group C Interrupt Flag Register
; Code security module (CSM) registers (Data memory)
KEY3 .set 77F0h ; High word of the 64-bit KEY register
KEY2 .set 77F1h ; Third word of the 64-bit KEY register
KEY1 .set 77F2h ; Second word of the 64-bit KEY register
KEY0 .set 77F3h ; Low word of the 64-bit KEY register
; Code security module (CSM) registers (Program memory)
PWL3 .set 0040h ; High word of the 64bit password
PWL2 .set 0041h ; Third word of the 64bit password
PWL1 .set 0042h ; Second word of the 64bit password
PWL0 .set 0043h ; Low word of the 64bit password
;
; I/O space mapped registers
;
FCMR .set 0FF0Fh ; Flash control mode register
WSGR .set 0FFFFh ; Wait-State Generator Control register
;
; Bit codes for Test bit instruction (BIT) (15 Loads bit 0 into TC)
;
BIT15 .set 0000h ; Bit Code for 15
BIT14 .set 0001h ; Bit Code for 14
BIT13 .set 0002h ; Bit Code for 13
BIT12 .set 0003h ; Bit Code for 12
BIT11 .set 0004h ; Bit Code for 11
BIT10 .set 0005h ; Bit Code for 10
BIT9 .set 0006h ; Bit Code for 9
BIT8 .set 0007h ; Bit Code for 8
BIT7 .set 0008h ; Bit Code for 7
BIT6 .set 0009h ; Bit Code for 6
BIT5 .set 000Ah ; Bit Code for 5
BIT4 .set 000Bh ; Bit Code for 4
BIT3 .set 000Ch ; Bit Code for 3
BIT2 .set 000Dh ; Bit Code for 2
BIT1 .set 000Eh ; Bit Code for 1
BIT0 .set 000Fh ; Bit Code for 0
TMS320F24XX-A DSP Controllers
TMS320LF240x-A Flash Programming
Serial Port Flash Programming Utility
Texas Instruments
TMS320F24XX-A DSP Controllers
Table of Contents
1.
Introduction.......................................................................................................................................... 4
1.1. Overview ............................................................................................................................................... 4
2.
Operation.............................................................................................................................................. 4
2.1. DSP Controller Initialization ................................................................................................................. 4
2.2. Kernel Transfer...................................................................................................................................... 6
2.3. Kernel Operation ................................................................................................................................... 8
2.4. Clear ...................................................................................................................................................... 8
2.5. Erase ...................................................................................................................................................... 8
2.6. Program ................................................................................................................................................. 8
2.7. Repeat program / Exit Programming ..................................................................................................... 9
3.
Working with the Serial Programming Utility................................................................................ 10
3.1. Preparing code for programming into flash. ........................................................................................ 10
3.2. Setting up the programming utilities.................................................................................................... 10
3.3. Invoking the serial loader .................................................................................................................... 10
3.4. Setting up the password for the LF240x-A devices. ............................................................................ 10
4.
Configuring the target clock frequency ........................................................................................... 11
4.1
Adjusting Clock Frequency ............................................................................................................. 11
4.1.1. (NOT) Configuring the PLL Multiplier Ratio ........................................................................ 12
4.1.2. Scaling the Timing Parameters ............................................................................................... 12
4.1.3. Generating a timing set ........................................................................................................... 12
Texas Instruments
TMS320F24XX-A DSP Controllers
Table of Figures
Figure 1. Serial Flash Utility Device Initialization ..........................................................................5
Figure 2. Memory Maps for the LF 24xx Devices in Microcontroller Mode. .................................7
Figure 3. Transfer Packet Formats for the Programming.................................................................9
Figure 4. Flowchart for the ROM Bootloader SCI Protocol ..........................................................13
Figure 5. Flowchart for Serial Flash Programming Utility ............................................................14
Figure 6. Flowchart for Serial Flash Programming Utility ............................................................15
Texas Instruments
TMS320F24XX-A DSP Controllers
1. Introduction
This document describes the Serial Asynchronous Port based Flash Programming Utility for
the TMS320LF240x DSP Controllers. This utility leverages the Boot ROM on these
DSP controllers to provide a stand alone flash programming capability independent on the
previous contents of the flash. The serial port flash programming utility can be applied to
in-system programming for the DSP controller. The Serial Flash Programming Utilities share
the core flash programming algorithms with the JTAG Based Flash Programming Utilities.
Another major difference from the F24x Serial Programming is that the RAM resident kernel
is not fixed, copied from flash. It is downloaded run-time, resulting in added flexibility.
The TMS320LF240x devices have a on-chip asynchronous serial port (SCI - serial
communication interface). This chip communicates with standard RS232 compatible devices,
via external level translation hardware. The programming does not tie up the serial
communication port, this can be used for normal operation at other times.
1.1. Overview
The Boot ROM on the 'LF240x devices has two loaders in it. The serial flash programming
utility requires that upon device reset the Boot_EN / XF and the SPISIMO pins be pulled
low. This vectors the control of the device to the Boot ROM Asynchronous port loader. A
baud rate match protocol is then followed, synchronizing the communications port on the
target and the host. Once the communications are up-and-running , the host downloads a
kernel to the target. This kernel has the sequencing built into it, besides containing the
interface routines to the asynchronous serial port. This kernel will from this point onwards,
be the sole interface between the target flash algorithms and the host, the Boot ROM will not
be accessible during the flash programming process, and the routines in the ROM cannot be
executed. The kernel will be described in Sections 2.2 and 2.3. Once the kernel is initialized
correctly, the Clear, Erase and Program Algorithms are downloaded and executed.
2. Operation
A step by step description of the process appears below.
2.1. DSP Controller Initialization
The device is placed in Microcontroller mode and control transferred to the Boot ROM
(See Figure 1). To do this the following things are required:
Microcontroller Mode The ‘LF24xx device must be placed in microcontroller mode, by
pulling the MP/MC* pin LOW.
Texas Instruments
TMS320F24XX-A DSP Controllers
Boot ROM Loader Invocation The boot loader is invoked by pulling the BOOT_EN* /
XF pin low through a resistor, prior to device reset. This causes the control to transfer to
the boot load program located in the on-chip ROM. At reset time internal logic takes a
‘snapshot’ of this pin and if this pin is a low level then the Boot ROM appears in the
memory map as shown in Figure 2.
Otherwise the on-chip flash memory is enabled and the program counter begins execution
at 0x0000. It is suggested that this pin be driven from a jumper through a resistor, allowing
control whether the processor enters the boot loader or commences normal execution from
SCI Bootload
SPI Bootload
Vdd
LF240x
EEPROM
DIN
DOUT
CLK
SPISIMO
SPISOMI
SPICLK
CS
Boot_EN / XF
Boot_EN
Boot ROM
Flash Execute
Vdd
Host PC
SCITXD
SCIRXD
internal program memory. Alternately this pin may be controlled from a host processor,
allowing it to control the boot sequence of the DSP. The resistor must be present, since the
XF pin is an output at all other times.
SPI or SPI Selection The boot loader code selects the source of the incoming code
depending on the state of the SPISIMO pin, on the device.
Figure 1. Serial Flash Utility Device Initialization
The code takes a snapshot of this code after being invoked, and determines which loader
(SPI or SCI) to invoke based on the status of this pin.
• If SPISIMO/IOPC2 is pulled low, an SCI transfer is commenced, otherwise
• If SPISIMO/IOPC2 is pulled high an SPI transfer is commenced
For the Serial port flash programming the first option, to commence SCI transfer must be
selected.
Texas Instruments
TMS320F24XX-A DSP Controllers
At this point the control is transferred into the Boot ROM SCI control program. This
program resident in the Boot ROM enables the transfer of the kernel into RAM on the
device.
Communications Initialization The baud rate over the communication link is always
38400 bps. The baud rate protocol is necessary because the ‘LF240x device may be
operated at different speeds. The underlying assumption for the baud rate matching is that
the device is clocked at a clock frequency belonging to a given set. This set is determined
by the parameters in ROM. The host is required to send ‘probe’ characters, with the
hexadecimal value 0x0D. The target listens in on the serial port, at the set speeds, in
succession. Every time a character is detected, it is compared to 0x0D. If more than three
characters do not match, the target tries a new baud rate. If the baud rate is correct and the
character matches 0x0D, then the target expects to receive nine correct characters back to
back. If any other character is received the baud match fails. Once the nine chars are
received correctly then the target sends an acknowledge character. Once the acknowledge
character is sent, from this point on each and every character is bounced back to the host
to ensure data transfer integrity. All the communications are with 8 bits/char. 1 stop bit
and no parity. The communications initialization protocol is flowcharted in Figure 4.
Once the communications are locked, the data transfer commences.
2.2. Kernel Transfer
The kernel is transferred over the communications channel split into bytes. The LS Byte
is transferred first, followed by the MS Byte. The data packet format is shown below:
Host sends:
• Start address : One Word (16 bits) , split into bytes, LS Byte first.
• Length (i.e. number of words to transfer): One Word (16 bits) , split into
bytes, LS Byte first.
• Actual kernel code, split into bytes, LS Byte first.
As part of the initialization process, once the kernel is transferred into RAM, the kernel
sends a 'error code' to indicate its initialization status. A 0x0 code indicates success
whereas a failure to return any code or the return of an incorrect code would cause the
host to abandon the transfer.
Note: Once the kernel is initialized it is possible to change the communication
parameters, however the custom kernel must verify that the last transfer on the SCI is
complete before attempting to change the parameters. Additionally the host must take this
change of parameters into account.
Texas Instruments
TMS320F24XX-A DSP Controllers
Flash Block details
0000
003F
0040
Interrupts
0000
4K
00FF
010
FLASH
32 KW
(seg - 4/12/12/4)
Note: External if
MC*/MP=1
0FFF
1000
12K Sector
3FFF
4000
12K Sector
7FFF
8000
SARAM
2KW
87FF
8800
(Note: Double mapped
with Data space
External
(off chip)
FDFF
FE00
DARAM (B0)
256W
(CNF=1)
FEFF
FF00
DARAM (B0)
Double mapped
(CNF=1)
FFFF
4K
Boot ROM (256 W)
Note:
Active only when
BOOT_EN*/XF pin =
Lo at reset.
6FFF
7000
7FFF
0000
00FF
Note:
• Boot ROM & Flash Memory
appear in the same memory space,
and hence are not visible (active) at
the same time. If BOOT_EN*/XF
pin = Low at reset Flash memory is
disabled. See SCSR2 register
description for more explanation.
Figure 2. Memory Maps for the LF 24xx Devices in Microcontroller Mode.
Texas Instruments
TMS320F24XX-A DSP Controllers
2.3. Kernel Operation
Once the kernel is successfully initialized, the kernel controls the sequencing of the
transfer over the link. The TI kernel requires the algorithms to satisfy certain
conditions/guidelines. These are:
a. The algorithm must be less than 0x100 words, and must be assembled/linked
to execute between 0xfe00 and 0xfeff. In addition the entry point must be at
0xfe00.
b. The algorithm must return status in the variable ERROR_FLAG. See
SVAR.H in the algos\include directory for details.
c. The algorithm must return control by means of a return instruction. Also it
should not destroy any variables the kernel uses. The kernel variables are in
the file indicated in (b).
d. The algorithm should also not interfere with the communications port, this
may interrupt the protocol.
e. The kernel expects the algorithms to be Clear, Erase and Program in that
sequence. The clear, erase and program algorithms are described in step
(5),(6) and (7).
f. The kernel must of course be located at an address with valid RAM
available. No check is made to see if there is RAM available, so the kernel
must be assembled and linked to ensure that this happens correctly.
2.4. Clear
The clear algorithm is the first algorithm downloaded to the target. It performs the precondition operation on the flash, clearing(setting to zero) all the bits in the main and
secondary arrays. This readies the flash for erase. Upon a successful clear the algo returns
a zero, otherwise non-zero.
2.5. Erase
Erase is the downloaded next. This erases all four sectors of the flash. The erase
algorithm also performs a compaction check on the flash, compacting any depleted
columns. Upon a successful erase the algo returns a zero, otherwise non-zero.
2.6. Program
Following the erase and clear the programming algorithm is downloaded next. However
the programming algorithm is not executed immediately, instead first block of
programming data is downloaded. Once the programming data is available a call is made
to the programming algorithm, with the destination address and the length are available.
The programming algo reads in data from the data buffer and programs the data into the
flash array. The programming operation puts a pattern of zeros into the flash array.
Texas Instruments
TMS320F24XX-A DSP Controllers
2.7. Repeat program / Exit Programming
Once the programming operation for one block is completed the programming algorithm
returns a status in ERROR_FLAG. Once the kernel regains control, it passes the status to
the host. The host, upon receiving a success status, send a " last block flag " - one word.
The target looks at this and either returns to receive one more program data block, or
terminates in a blind loop.
The TI kernel terminates in a blind loop, however if the system allows, a custom kernel
may allow the control to return to the newly programmed code in the flash. It would also
be possible to extend the kernel to run further algorithms, after programming, performing
other functions.
Start Address
Start Address
Size(number of words)
Size(number of words)
Data block start
Code block start
o
o
o
o
o
o
Data block end
Code block end
Last Block Flag
(a)
Figure 3. Transfer Packet Formats for the Programming
data blocks (a) and the three operational algorithms(b).
Texas Instruments
(b)
TMS320F24XX-A DSP Controllers
Serial Flash Programming Utility Operation
3. Working with the Serial Programming Utility
3.1. Preparing code for programming into flash.
To use the serial port flash programming utility compile, assemble and link your code to
run out of flash. Prepare your COFF file (flashcode.out) for programming the flash. This
COFF file can contain up to 32K words for the ‘F24xx. The only restriction is that the
COFF file must not include anything other then the code to be programmed in the flash.
Never include data sections in the COFF file that will be used to program the flash. For
more information on COFF and working with sections, refer to the
TMS320C1x/C2x/C2xx/C5x Assembly Language Tools User’s Guide.
3.2. Setting up the programming utilities
The programming utilities are distributed as a compressed file. To set up the tool unzip
this file. Ensure that the directory structure is restored. For correct operation this required.
3.3. Invoking the serial loader
Verify that the serial link on your target is functioning by means of echoing characters
back from a terminal program. By connecting RX and TX together on the target side for
example) Once this is done restore the connections.
Choose loader1.bat or loader2.bat depending on whether your serial cable is connected to
COM1 or COM2. Copy this batch file to another batch file say, prog.bat. Edit this file to
point the command line parameter for spf24xb?.exe to your hex file. Once this is done,
run this batch file to invoke the loader
3.4. Setting up the password for the LF240x-A devices.
Locate the password.h file in the ‘algos\include’ directory. Open this file in any ascii
editor. Now edit this file to put in the password you want to use to unlock the flash on a
rev-A device. This password needs to be the same exact password that is present in the
flash so that the flash will unlock. If the flash contains the password that is either all
0x0000 or 0xffff then this password is a don’t care.
Once the password is setup, run MK_ALGOS.BAT to rebuild the kernel so that the
password change takes effect.
For example a sample file is:
; Password section: input the four words of the flash password here
PASSWD1 .set 0000h ; Password at 0040h in flash
PASSWD2 .set 0000h ; Password at 0041h in flash
PASSWD3 .set 0000h ; Password at 0042h in flash
PASSWD4 .set 0000h ; Password at 0043h in flash
NOTE: THIS PASSWORD IS THE UNLOCK PASSWORD. THE COFF FILE BEING
PROGRAMMED INTO THE DSP CONTROLS THE NEW PASSWORD IF ANY
THAT IS PROGRAMMED INTO THE DSP.
Texas Instruments
TMS320F24XX-A DSP Controllers
Also, the password that is placed in the password.h does NOT take effect untill the algos
are rebuilt using the mk_algos.bat batch file. If this password does not match then the
flash loader will try to unlock the flash, and will continue on to clear, and will report that
the clear failed. This will be the main symptom of a locked flash. Check the password
and try again with the correct password.
4. Configuring the target clock frequency
For the utilities as released the target clock frequency MUST be 30MHz.
The serial boot ROM loader will lock at other clock frequencies as well, but the
flash algorithms must be first configured for the NEW frequency first.
Programming the flash using wrongly configured algorithms can cause permanent
damage to the target device and/or undefined operation.
4.1. Adjusting Clock Frequency
The programming algorithms for the ‘F240x on-chip flash include software delays that must be
adjusted according to the instruction rate of the target device. This chapter describes how to
modify the programming utility for use with different clock frequencies.
Texas Instruments
TMS320F24XX-A DSP Controllers
WARNING! If the design will be using a variable CLKOUT, (i.e. CLKOUT will be varied by
the application) then the flash should be erased at the highest possible CLKOUT rate. This is
important to ensure adequate read-back margin throughout the life of the application. If for
instance the CLKOUT may be any of 5,10,20 MHz, then the flash must be erased using the
CLKOUT at 20Mhz.
If the frequency of CLKOUT will be different for some reason, eg. the CLKIN is not 7.5
MHz, then it is necessary to re-configure the flash programming utilities to take this into
account. To do this following things must be accomplished.
a. PLL Multiplier Configuration
b. Scaling the Timing Parameters.
c. Generating a timing set.
d. Re-building the algorithms.
4.1.1. (NOT) Configuring the PLL Multiplier Ratio
The configuration set in the algos\include\var.h is ignored, since the utilities depend on
the Boot ROM loader to configure the PLL.
4.1.2. Scaling the Timing Parameters
Timing parameters are selected based on the clock frequency the CPU is running at. A
few timing sets are distributed with the tools. Each set of timings is contained in a file
called timings.xx. For example the file containing loop timings calibrated at 28MHz is
called timings.28.In STEP 2 in VAR.H choose the appropriate timing set.
4.1.3. Generating a timing set
Lets assume that a system needs timings to be calibrated at 28 MHz. For this purpose the
Excel worksheet timings.xls is provided. To generate a new set of timings open this file
in Microsoft Excel, and see the instructions in the worksheet.
Texas Instruments
TMS320F24XX-A DSP Controllers
A
Initialize Baud Rate Parameters
Clear VBR_COUNTER,
Listen for a character
N
Is the RX
Flag Set?
Y
Fetch Character
Is Char
N
=0x0D?
Y
Increment VBR
Increment VBR
N
Is VBR
& gt; max ?
Y
Send 0xAA to Host
Figure 4. Flowchart for the ROM Bootloader SCI Protocol
Communications Synchronization.
Texas Instruments
TMS320F24XX-A DSP Controllers
B
FETCH_HEADER
Get Kernel from Host (XFER_SCI_2_PROG)
Transfer control to kernel. Return status
FETCH_HEADER
Get Clear from the host (XFER_SCI_2_PROG)
Execute clear algorithm. Return status
FETCH_HEADER
Get Erase from the host (XFER_SCI_2_PROG)
Execute erase algorithm. Return status.
FETCH_HEADER
Get program algorithm from the host
(XFER_SCI_2_PROG)
C
Figure 5. Flowchart for Serial Flash Programming Utility
Algorithm execution sequence.
Texas Instruments
TMS320F24XX-A DSP Controllers
C
FETCH_HEADER
Get data block from host
(XFER_SCI_2_DATA)
Execute program
algorithm. Return status
Get LAST_BLOCK flag
More data
blocks to
program ?
Y
N
End
Figure 6. Flowchart for Serial Flash Programming Utility
Programming Sequence.
Texas Instruments