PDF'a dodaję w załączniku. Z tego, co udało mi się znaleźć na chińskich stronach, sterowanie to "8080 8-bit data bus". Jest to opisane w tym pdf'ie. Podejrzewam, że sterowanie może być podobne do wyświetlacza z tego tematu. http://www.elektroda.pl/rtvforum/topic1344700.html#6669973 A ten lcd wygląda bardzo podobnie (rozdzielczość i sterownil) http://www.module.ro/nokia_3110.html
SPFD54124B
396-channel 6-bit Source Driver with
System-on-chip for Color
Amorphous TFT-LCDs
Preliminary
APR. 26, 2007
Version 0.6
ORISE Technology reserves the right to change this documentation without prior notice. Information provided by ORISE Technology is believed to be
accurate and reliable. However, ORISE Technology makes no warranty for any errors which may appear in this document.
Contact ORISE Technology to
obtain the latest version of device specifications before placing your order. No responsibility is assumed by ORISE Technology for any infringement of patent
or other rights of third parties which may result from its use. In addition, ORISE Technology products are not authorized for use as critical components in life
support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to
the user, without the express written approval of ORISE Technology.
Preliminary
SPFD54124B
Table of Contents
PAGE
1. GENERAL DESCRIPTION .......................................................................................................................................................................... 6
2. FEATURES.................................................................................................................................................................................................. 6
3. ORDERING INFORMATION........................................................................................................................................................................ 6
4. BLOCK DIAGRAM ...................................................................................................................................................................................... 7
5. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 9
6. INSTRUCTIONS ........................................................................................................................................................................................ 14
6.1. OUTLINE .............................................................................................................................................................................................. 14
6.1.1.
System Function Command List and Description ................................................................................................................ 14
6.1.2.
Panel Function Command List and Description ................................................................................................................... 17
6.2. SYSTEM COMMAND DESCRIPTION ........................................................................................................................................................ 20
6.2.1.
NOP (00h) ............................................................................................................................................................................ 20
6.2.2.
SWRESET (01h): Software Reset........................................................................................................................................ 20
6.2.3.
RDDID (04h): Read Display ID............................................................................................................................................. 22
6.2.4.
RDDST (09h): Read Display Status ..................................................................................................................................... 23
6.2.5.
RDDPM (0Ah): Read Display Power Mode.......................................................................................................................... 25
6.2.6.
RDDMADCTR (0Bh): Read Display MADCTR .................................................................................................................... 26
6.2.7.
RDDCOLMOD (0Ch): Read Display Pixel Format ............................................................................................................... 27
6.2.8.
RDDIM (0Dh): Read Display Image Mode ........................................................................................................................... 28
6.2.9.
RDDSM (0Eh): Read Display Signal Mode .......................................................................................................................... 29
6.2.10. RDDSDR (0Fh): Read Display Self-Diagnostic Result ........................................................................................................ 30
6.2.11. SLPIN (10h): Sleep In .......................................................................................................................................................... 31
6.2.12. SLPOUT (11h): Sleep Out.................................................................................................................................................... 33
6.2.13. PTLON (12h): Partial Display Mode On ............................................................................................................................... 35
6.2.14. NORON (13h): Normal Display Mode On ............................................................................................................................ 36
6.2.15. INVOFF (20h): Display Inversion Off.................................................................................................................................... 37
6.2.16. INVON (21h): Display Inversion On ..................................................................................................................................... 38
6.2.17. GAMSET (26h): Gamma Set................................................................................................................................................ 39
6.2.18. DISPOFF (28h): Display Off................................................................................................................................................. 40
6.2.19. DISPON (29h): Display On................................................................................................................................................... 42
6.2.20. CASET (2Ah): Column Address Set..................................................................................................................................... 44
6.2.21. RASET (2Bh): Row Address Set .......................................................................................................................................... 46
6.2.22. RAMWR (2Ch): Memory Write ............................................................................................................................................. 48
6.2.23. RGBSET (2Dh): Colour Setting for 4K, 65K and 262K ........................................................................................................ 50
6.2.24. RAMHD (2Eh): Memory Read.............................................................................................................................................. 51
6.2.25. PTLAR (30h): Partial Area.................................................................................................................................................... 52
6.2.26. SCRLAR (33h): Scroll Area .................................................................................................................................................. 54
6.2.27. TEOFF (34h): Tearing Effect Line OFF ................................................................................................................................ 58
6.2.28. TEON (35h): Tearing Effect Line ON.................................................................................................................................... 59
6.2.29. MADCTR (36h): Memory Data Access Control .................................................................................................................... 60
6.2.30. VSCSAD (37h): Vertical Scroll Start Address of RAM .......................................................................................................... 62
6.2.31. IDMOFF (38h): Idle Mode Off............................................................................................................................................... 64
6.2.32. IDMON (39h): Idle Mode On ................................................................................................................................................ 65
6.2.33. COLMOD (3Ah): Interface Pixel Format............................................................................................................................... 67
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Preliminary
SPFD54124B
6.2.34. RDID1 (DAh): Read ID1 Value ............................................................................................................................................. 68
6.2.35. RDID2 (DBh): Read ID2 Value ............................................................................................................................................. 69
6.2.36. RDID3 (DCh): Read ID3 Value............................................................................................................................................. 70
6.3. PANEL COMMAND DESCRIPTION ........................................................................................................................................................... 71
6.3.1.
RGBCTR (B0h): RGB signal control .................................................................................................................................... 71
6.3.2.
FRMCTR1 (B1h): Frame Rate Control (In normal mode/ Full colors).................................................................................. 73
6.3.3.
FRMCTR2 (B2h): Frame Rate Control (In Idle mode/ 8-colors)........................................................................................... 75
6.3.4.
FRMCTR3 (B3h): Frame Rate Control (In Partial mode/ full colors).................................................................................... 77
6.3.5.
INVCTR (B4h): Display Inversion Control ............................................................................................................................ 79
6.3.6.
RGBBPCTR (B5h): RGB Interface Blanking Porch setting.................................................................................................. 80
6.3.7.
DISSET5 (B6h): Display Function set 5 ............................................................................................................................... 81
6.3.8.
PWCTR1 (C0h): Power Control 1 ........................................................................................................................................ 83
6.3.9.
PWCTR2 (C1h): Power Control 2 ........................................................................................................................................ 85
6.3.10. PWCTR3 (C2h): Power Control 3 (in Normal mode/ Full colors) ......................................................................................... 86
6.3.11. PWCTR4 (C3h): Power Control 4 (in Idle mode/ 8-colors) .................................................................................................. 88
6.3.12. PWCTR5 (C4h): Power Control 5 (in Partial mode/ full-colors) ........................................................................................... 90
6.3.13. VMCTR1 (C5h): VCOM Control 1 ........................................................................................................................................ 92
6.3.14. VMCTR2 (C6h): VCOM Control 2 ........................................................................................................................................ 94
6.3.15. RDVMH (C8h): Read the VCOMH Value NV memory ......................................................................................................... 96
6.3.16. WRID1 (D0h): Write ID1 Value............................................................................................................................................. 97
6.3.17. WRID2 (D1h): Write ID2 Value............................................................................................................................................. 98
6.3.18. WRID3 (D2h): Write ID3 Value............................................................................................................................................. 99
6.3.19. RDID4 (D3h): Read the ID4 value...................................................................................................................................... 100
6.3.20. NVFCTR1 (D9h): NV Memory Function Controller 1 ......................................................................................................... 101
6.3.21. NVFCTR2 (DEh): NV Memory Function Controller 2 ......................................................................................................... 103
6.3.22. NVFCTR3 (DFh): NV Memory Function Controller 3 ......................................................................................................... 104
6.3.23. GMCTRP1 (E0h): Gamma Correction Characteristics Setting .......................................................................................... 105
6.3.24. GMCTRP1 (E1h): Gamma Correction Characteristics Setting .......................................................................................... 107
7. FUNCTION DESCRIPTIONS................................................................................................................................................................... 109
7.1. MCU & RGB INTERFACE ................................................................................................................................................................... 109
7.2. MPU INTERFACE ............................................................................................................................................................................... 109
7.2.1.
Interface Type Selection......................................................................................................................................................110
7.2.2.
8080-Series Parallel interface(P68=’0’)...............................................................................................................................110
7.2.3.
6800-Series Parallel Interface (P68=’1’) .............................................................................................................................113
7.2.4.
Serial Peripheral interface ...................................................................................................................................................116
7.2.5.
Data Transfer Break and Recovery .................................................................................................................................... 120
7.2.6.
Data Transfer Pause .......................................................................................................................................................... 122
7.2.7.
Data Transfer Modes.......................................................................................................................................................... 123
7.3. MCU DATA COLOUR CODING ............................................................................................................................................................. 124
7.3.1.
MCU Data Colour Coding for RAM data Write ................................................................................................................... 124
7.3.2.
MCU Data Colour Coding for RAM data Read................................................................................................................... 135
7.3.3.
Serial Interface (IM2 = ‘0’) .................................................................................................................................................. 140
7.4. RGB INTERFACE ................................................................................................................................................................................ 142
7.4.1.
General Description............................................................................................................................................................ 142
7.4.2.
General Timing Diagram .................................................................................................................................................... 143
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Preliminary
SPFD54124B
7.4.3.
Updating Order on Display Active Area (Normal Display Mode On + Sleep Out) .............................................................. 144
7.4.4.
RGB Interface Bus Width set ............................................................................................................................................. 146
7.4.5.
RGB Interface Mode Set .................................................................................................................................................... 146
7.4.6.
RGB Interface Timing Diagram .......................................................................................................................................... 147
7.4.7.
RGB Data Color Coding ..................................................................................................................................................... 158
7.5. DISPLAY DATA RAM .......................................................................................................................................................................... 161
7.5.1.
Configuration ...................................................................................................................................................................... 161
7.5.2.
Memory to Display Address Mapping................................................................................................................................. 162
7.5.3.
Normal Display On or Partial Mode On, Vertical Scroll Off ................................................................................................ 166
7.5.4.
Vertical Scroll Mode............................................................................................................................................................ 170
7.5.5.
Vertical Scroll Example....................................................................................................................................................... 175
7.6. ADDRESS COUNTER........................................................................................................................................................................... 178
7.7. MEMORY DATA WRITE/ READ DIRECTION ........................................................................................................................................... 179
7.8. TEARING EFFECT OUTPUT LINE .......................................................................................................................................................... 183
7.8.1.
Tearing Effect Line Modes.................................................................................................................................................. 183
7.8.2.
Tearing Effect Line Timings ................................................................................................................................................ 184
7.8.3.
Example 1: MPU Write is faster than panel read. .............................................................................................................. 185
7.8.4.
Example 2: MPU write is slower than panel read............................................................................................................... 186
7.9. PRESET VALUES ................................................................................................................................................................................ 187
7.10. POWER ON/OFF SEQUENCE ............................................................................................................................................................. 187
7.10.1. Case 1 – RESX Line is held High or Unstable by Host at Power On ................................................................................. 187
7.10.2. Case 2 – RESX Line is Held Low by Host at Power On .................................................................................................... 188
7.10.3. Uncontrolled Power Off ...................................................................................................................................................... 188
7.11. POWER LEVEL DEFINITION ................................................................................................................................................................. 189
7.11.1. Power Level........................................................................................................................................................................ 189
7.11.2. Power Flow Chart............................................................................................................................................................... 190
7.12. GAMMA CURVES ................................................................................................................................................................................ 191
7.13. RESET ............................................................................................................................................................................................... 192
7.13.1. Reset Value ........................................................................................................................................................................ 192
7.13.2. Module Input/Output Pins................................................................................................................................................... 196
7.13.3. Reset Timing ...................................................................................................................................................................... 197
7.14. COLOUR DEPTH CONVERSION LOOK UP TABLES................................................................................................................................. 198
7.14.1. 4096 and 65536 Colour to 262,144 Colour ........................................................................................................................ 198
7.15. SLEEP OUT-COMMAND AND SELF-DIAGNOSTIC FUNCTIONS OF THE DISPLAY MODULE ......................................................................... 202
7.15.1. Register Loading Detection ................................................................................................................................................ 202
7.15.2. Functionality Detection ....................................................................................................................................................... 203
7.15.3. Chip Attachment Detection................................................................................................................................................. 204
7.15.4. Display Glass Break Detection........................................................................................................................................... 205
7.16. OSCILLATOR ...................................................................................................................................................................................... 206
7.17. SYSTEM COLCK GENERATOR ............................................................................................................................................................. 206
7.18. INSTRUCTION DECODER AND REGISTER ............................................................................................................................................. 206
7.19. SOURCE DRIVER................................................................................................................................................................................ 206
7.20. GATE DRIVER .................................................................................................................................................................................... 206
7.20.1. Gate Driver ......................................................................................................................................................................... 206
7.21. Γ-CORRECTION FUNCTION .......................................................................................................................................................... 206
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Preliminary
SPFD54124B
8. ELECTRICAL SPECIFICATIONS ........................................................................................................................................................... 207
8.1. DC CHARACTERISTICAC CHARACTERISTIC ......................................................................................................................................... 207
8.2. AC TIMING CHARACTERISTICS ............................................................................................................................................................ 208
8.2.1.
Parallel Interface Characteristics 18, 16 ,9 or 8-bits bus (8080-series MCU) .................................................................... 208
8.3. PARALLEL INTERFACE CHARACTERISTICS 18, 16 ,9 OR 8-BITS BUS (6800-SERIES MCU) ...................................................................... 210
8.4. SERIAL INTERFACE CHARACTERISTICS (3-PIN SERIAL) .........................................................................................................................211
9. CHIP INFORMATION .............................................................................................................................................................................. 212
9.1. PAD ASSIGNMENT ............................................................................................................................................................................. 212
9.2. PAD DIMENSION ................................................................................................................................................................................ 212
9.3. BUMP DIMENSION .............................................................................................................................................................................. 213
9.3.1.
Output Pads ....................................................................................................................................................................... 213
9.3.2.
Input Pads .......................................................................................................................................................................... 213
9.4. BUMP CHARACTERISTICS ................................................................................................................................................................... 213
9.5. PAD LOCATIONS ............................................................................................................................................................................... 214
9.6. ALIGNMENT MARK.............................................................................................................................................................................. 221
9.7. WIRING RESISTANCE ......................................................................................................................................................................... 222
10. DISCLAIMER........................................................................................................................................................................................... 223
11. REVISION HISTORY ............................................................................................................................................................................... 224
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Preliminary Version: 0.6
Preliminary
SPFD54124B
396-CHANNEL DRIVER WITH SYSTEM-ON-CHIP (SOC)
FOR COLOR AMORPHOUS TFT LCD
1. GENERAL DESCRIPTION
2. FEATURES
The SPFD54124B, a 262144-color System-on-Chip (SoC) driver
One-chip solution for amorphous TFT-LCD.
LSI designed for small and medium sizes of TFT LCD display, is
Supports resolution up to 132xRGBx162, incorporating a
capable of supporting up to 132xRGBx162 in resolution which can
396-channel source driver and a 162-channel gate driver
be achieved by the designated RAM for graphic data.
Outputs 64 γ -corrected values using an internal true 6-bit
The
resolution D/A converter to achieve 262K colors
396-channel source driver has true 6-bit resolution, which
generates 64 Gamma-corrected values by an internal D/A
Built-in 48114 bytes internal RAM
converter.
Line Inversion AC drive / frame inversion AC drive
The SPFD54124B is able to operate with low IO interface power
− High-speed interfaces to 8-, 9-, 16-, and 18-bit parallel ports
supply up to 1.6V and incorporate with several charge pumps to
− 3-pin 9 bits or 4-pin 8 bits Serial Peripheral Interface (SPI)
generate various voltage levels that form an on-chip power
Interfaces for moving picture display
management system for gate driver and source driver.
− 6-, 16-, and 18-bit RGB interfaces
System interfaces
Diverse RAM accessing for functional display
− Window address function to display at any area on the
The built-in timing controller in SPFD54124B can support several
interfaces for the diverse request of medium or small size portable
screen via a moving picture display interface
− Window address function to limit the data rewriting area
display. SPFD54124B provides system interfaces, which include
8-/9-/16-/18-bit parallel interfaces and serial interface (SPI), to
and reduce data transfer
configure system. Not only can the system interfaces be used to
− Moving and still picture can display at the same time
configure system, they can also access RAM at high speed for still
− Vertical scrolling function
picture display. In addition, the SPFD54124B incorporates 6, 16,
− Partial screen display
and 18-bit RGB interfaces for picture movement display. The
Power supply
SPFD54124B also supports a function to display eight colors and
− Logic power supply voltage (VDD): 2.6 ~ 3.6 V
a standby mode for power control consideration.
− I/O interface supply voltage (VDDIO): 1.6 ~ 3.6 V
− Analog power supply voltage (VDD): 2.6 ~ 3.6V
On-chip power management system
− Power saving mode (standby / 8-color mode, etc)
− Low power consumption structure for source driver.
Built-in Charge Pump circuits
− Source driver voltage level : 2 times (x2) of Vci1
− Gate driver voltage level (VGH, VGL) up to 6 times (x6) and
minus 5 times (x-5) Vci1
Built-in internal oscillator and hardware reset
Built–in One-Time-Programming (OTP) function for VCOM
amplitude and VcomH voltage adjustment.
3. ORDERING INFORMATION
Product Number
Package Type
SPFD54124B-C
Chip Form With Gold Bump
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Preliminary
SPFD54124B
4. BLOCK DIAGRAM
4.1. Block Function
S1
SPI4
P68
DCX/SCL
SDA
IM[2:0]
CSX
RDX
WRX
OTP
Memory
S2
S395
S396
Source Driver (396 channels)
System
Interface
True 6-bit D/A Converter
6
6
6
6
Level Shifter (396 x 6bits)
LUT
D[17:0]
DE
PCLK
VS
HS
18
RGB
Interface
Graphics
RAM
48114
bytes
6
18
6
6
6
Data Latch (132 x 3 x 6bits x2)
Shift Register (132 bits)
64
FB
TESEL
TE
RESX
EXTC
IDM
GM[1:0]
LCM[1:0]
RCM[1:0]
SRGB
SMX
SMY
SHUT
REV
RL
TB
VREF
VDD
Timing
Signal
Generator
Regulator
VDDI
Clock
CLK
Generator
VGL
VCOM
VCOML
AVDD
Gate
Power
Charge
Pump
GVDD
VCOMH
VCI1
VCOM
VCI1
C11P/N
C12P/N
C21P/N
C22P/N
C23P/N
OSC
AVDD
Gamma
Voltage
Generator
Gate
Driver
G[162:1]
VGH
VCL
DC-DC
Controller
DRV
Note1 : Pwr = VDD, VDDI; Gnd = AGND,DGND;
Pwr/Gnd Output = VDDIO,DGNDO,VCC
Note2 : Glass Broken - PADA0,PADB0; Chip Attachment - PADA[4:1],PADB[4:1];
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SPFD54124B
4.1.1. System Interface
The SPFD54124B supports three high-speed system interfaces:
4.1.5. Grayscale Voltage Generating Circuit
1. 80-system high-speed interfaces with 8-, 9-, 16-, 18-bit parallel
SPFD54124B has true 6-bit resolution D/A converter, which
ports.
generates 64 Gamma-corrected values and cooperates with
2. 68-system high-speed interfaces with 8-, 9-, 16-, 18-bit parallel
OP-AMP structure to enhance display quality. The grayscale
ports.
voltage can be adjusted by grayscale data set in the γ-correction
3. 3-pin 9-bits or 4-pin 8 bits Serial Peripheral Interface (SPI).
register.
The SPFD54124B has a 16-bit index register (IR) and two 18-bit
4.1.6. Timing Controller
data registers, a write-data register (WDR) and a read-data
register (RDR).
SPFD54124B has a timing controller which can generate a timing
The IR register is used to store index information
signal for internal circuit operation such as gate output timing,
from control registers. The WDR register is used to temporarily
RAM accessing timing, etc.
store data to be written for register control and internal GRAM.
The RDR register is used to temporarily store data read from the
4.1.7. Oscillator (OSC)
GRAM. When graphic data is written to the internal GRAM from
The SPFD54124B also features an internal oscillator to generate
MCU/graphic engine, the data is first written to the WDR and then
RC oscillation with an internal resistor. In standby mode, RC
automatically written to the internal GRAM in internal operation.
oscillation is halted to reduce power consumption.
When graphic data read operation is executed, graphic data is
read via the RDR from the internal GRAM. Therefore, invalid data
4.1.8. Source Driver Circuit
is first read out to the data bus when the SPFD54124B executes
st
the 1 read operation.
SPFD54124B consists of a 396-output source driver circuit (S1 ~
Thus, valid data can be read out after the
th
S396).
SPFD54124B executes the 2 read operation.
Data in the GRAM are latched when the 396 bit data is
input.
nd
The latched data controls the source driver and generates
a drive waveform.
4.1.2. External Display Interface
The SPFD54124B supports external RGB interface for picture
4.1.9. Gate Driver Circuit
movement display.
The SPFD54124B allows switching between one of the external
SPFD54124B consists of a 162-output gate driver circuit
display interfaces and the system interface via pin configuration so
(G1~G162). The gate driver circuit outputs gate driver signals at
that the optimum interface is selected for still / moving picture
either VGH or VGL level.
displayed on the screen.
4.1.10. LCD Driving Power Supply Circuit
When the RGB interface is chosen, display operations are
The LCD driving power supply circuit generates the voltage levels
synchronized with external supplied signals, VSYNC, HSYNC, and
AVDD, VGH, VGL and VCOM for driving an LCD. All this voltages
DOTCLK. Moreover, valid display data (DB17-0) is written to
can be adjusted by register setting.
GRAM, which synchronized with signal (DE) enabling.
4.1.3. Address Counter (AC)
SPFD54124B features an Address Counter (AC) giving an
address to the internal GRAM. The address in the AC is
automatically updated plus or minus 1. The window address
function enables writing data only in the rectangular area arbitrarily
set by users on the GRAM.
4.1.4. Graphics RAM (GRAM)
SPFD54124B features a 48114-byte (132 x 162x 18 / 8) Graphic
RAM (GRAM).
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SPFD54124B
5. SIGNAL DESCRIPTIONS
Signal
Pin No.
I/O
Connected with
Function
GND/ VDDIO
Select system interface mode.
System Configuration Input Signal
P68,
5
I
IM2~0,
SPI4
P68
IM2
IM1
IM0
0
SPI4
0
0
-
-
3-Pin Serial interface
-
0
1
0
0
8080 MCU 8-bits Parallel interface
-
0
1
0
1
8080 MCU 16-bits Parallel interface
-
0
1
1
0
8080 MCU 9-bits Parallel interface
-
0
1
1
1
8080 MCU 18-bits Parallel interface
-
1
0
-
-
3-Pin Serial interface
-
1
1
0
0
6800 MCU 8-bits Parallel interface
-
1
1
0
1
6800 MCU 16-bits Parallel interface
-
1
I
MPU or
1
1
0
6800 MCU 9-bits Parallel interface
1
1
1
1
6800 MCU 18-bits Parallel interface
1
RESX
1
-
-
0
-
-
4-Pin Serial interface
Reset pin. This is an active low signal.
external
RC circuit
EXTC
1
1
GND/ VDDIO
Extend command set access
Low: Extend command set is not accessible.
High: Extend command set is accessible.
If this is not used. Open it (This pin is internally pull low).
GAMSEL
1
1
GND/ VDDIO
Gamma Setting selection:
(a) Low: GC0=1.0, GC1=2.5, GC2=2.2, GC3=1.8.
(b) High: GC0=2.2, GC1=1.8, GC2=2.5, GC3=1.0.
GM1~0
2
1
GND/ VDDIO
Resolution selection:
GM1
1
120*RGB*160
0
128*RGB*128
1
GND/ VDDIO
128*RGB*160
1
1
0
0
2
Resolution
0
RCM1~0
GM0
1
132*RGB*162
Interface selection:
RCM1
1
MCU Interface
0
RGB Interface
1
MCU
MCU Interface
1
1
0
0
1
Interface
0
IDM
RCM0
1
RGB Interface
In RGB interface mode:
(a) Low: Normal Display.
(b) High: Idle Mode (8-color mode).
This pin can be only used when RGB mode is selected.
LCM[1:0]
1
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GND/ VDDIO
Liquid Crystal Type selection:
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Preliminary
SPFD54124B
Signal
Pin No.
I/O
Connected with
Function
LCM1
1
TM
0
LV
1
GND/ VDDIO
TR
1
1
0
0
1
LC Type
0
SRGB
LCM0
1
MVA
RGB arrangement selection:
(a) Low: S1, S2, S3 fit ‘R’, ‘G’, ‘B’.
(b) High: S1, S2, S3 fit ‘B’, ‘G’, ‘R’
SHUT
1
1
GND/ VDDIO
Display on/off selection when RGB mode is selected.
(a) Low: Display On.
(b) High: Display Off.
This pin can be only used when RGB mode is selected.
REV
1
1
GND/ VDDIO
Data reverse for source driver selection when RGB mode is selected.
(a) Low: Reverse Off.
(b) High: Reserve On.
This pin can be only used when RGB mode is selected.
SMX
1
1
GND/ VDDIO
Source driver output direction selection:
SMX
1
GND/ VDDIO
GM=”11”
S7 = & gt; S390
S7= & gt; S366
S1= & gt; S396
1
1
GM=”01”
0
SMY
GM=”00” or “10”
S390= & gt; S7
S366= & gt; S7
S396= & gt; S1
Gate driver output direction selection:
SMY
0
1
RL
1
1
GND/ VDDIO
GM=”00” or “01”
GM=”10”
GM=”11”
G2 = & gt; G161
G2= & gt; G129
G1= & gt; G162
G161= & gt; G2
G129= & gt; G2
G162= & gt; G1
Source driver output direction selection:
RL
SMX
GM=”00” or “10”
GM=”01”
GM=”11”
0
0
S7 = & gt; S390
S7= & gt; S366
S1= & gt; S396
0
1
S390= & gt; S7
S366= & gt; S7
S396= & gt; S1
1
0
S390= & gt; S7
S366= & gt; S7
S396= & gt; S1
1
1
S7 = & gt; S390
S7= & gt; S366
S1= & gt; S396
This pin can be only used when RGB mode is selected.
TB
1
1
GND/ VDDIO
Gate driver output direction selection:
TB
SMY
GM=”00” or “01”
GM=”10”
GM=”11”
0
0
G2 = & gt; G161
G2= & gt; G129
G1= & gt; G162
0
1
G161= & gt; G2
G129= & gt; G2
G162= & gt; G1
1
0
G161= & gt; G2
G129= & gt; G2
G162= & gt; G1
1
1
G2 = & gt; G161
G2= & gt; G129
G1= & gt; G162
This pin can be only used when RGB mode is selected.
TESEL
1
I
GND/ VDDIO
The period of TE is equal 162 line
0
Proprietary & Confidential
TE period select
0
© ORISE Technology Co., Ltd.
TESEL
The period of TE is equal 160 line
10
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
Signal
Pin No.
I/O
Connected with
Function
I
MPU
Chip select signal.
Interface input Signals
CSX
1
Low: the SPFD54124B is accessible
High: the SPFD54124B is not accessible
This pin has can be permanently fixed “Low” in MCU interface mode only.
D/CX
1
I
MPU
(SCL)
Display data / Command selection pin in parallel interface
Low: Command data
High: Display data
In SPI I/F, this is used as SCL pin.
Must connect to the GND or VDDIO level when not used.
WRX
1
I
MPU
(R/WX)
(A) In 80-system interface mode, a write strobe signal can be input via this pin
and initializes a write operation when the signal is low.
(B) In 68-system interface mode, a write or read control signal can be input via
this pin and initializes a write or read operation.
Must connect to the GND or VDDIO level when not used.
RDX
1
I
MPU
(E)
In 80-system interface mode, a read strobe signal can be input via this pin and
initializes a read operation when the signal is low.
In 68system interface mode, a strobe signal can be input via this pin and
initializes a write or read operation when the signal is low.
SDA
1
I/O
MPU
Must connect to the GND or VDDIO level when not in use.
(A) When RCM = ‘1’ (RGB I/F),
Serial input/ output signal in serial I/F mode.
The data is input on the rising edge of the SCL signal.
The data is output on the falling edge of the SCL signal.
(B) When RCM = ‘0’ (MCU I/F),
This pin is not used, and fix at VDDIO or DGND level.
If not used, please fix this pin at VDDIO or DGND level.
DB0-DB17
1
I/O
MPU
(A) When RCM = ‘1’ (RGB I/F),
D[17:0] are used for RGB interface data bus
(B) When RCM = ‘0’ (MCU I/F),
D[17:0] are used to MCU parallel interface data bus
(C) In SPI I/F, D0 is used as Serial input/ output signal.
In SPI I/F, D[17:1] not used, please fix this pin at VDDIO or DGND level.
VS
1
I
MPU
In external interface mode, served as a vertical synchronize signal input
Must connect to the VDDIO or DGND level when not in use.
HS
1
I
MPU
In external interface mode, served as a horizontal synchronized signal input
Must connect to the VDDIO or DGND level when not in use.
DE
1
I
MPU
In external interface mode, polarity of DE signal is synchronized with valid
graphic data input.
High: Valid data on DB17-DB0
Low: Invalid data on DB17-DB0
Must connect to the VDDIO or DGND level when not in use.
PCLK
1
I
MPU
In external interface mode, served as a dot clock signal.
Must connect to the VDDIO or DGND level when not in use.
OSC
1
O
MPU
Oscillator frequency output pin for oscillator testing and turn ON/OFF by S/W
command.
Charge Pump and Power Supply Signal
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Preliminary Version: 0.6
Preliminary
SPFD54124B
Signal
C11P/N,
Pin No.
I/O
10
-
Function
Step-up
Connect boost capacitors for the internal DC/DC converter circuit to these
capacitor
C12P/N
Connected with
pins.
C21P/N,
Leave the pins open when DC/DC converter circuits are not used.
C22P/N
C23P/N
VCI1
1
O
Stabilizing
An internal reference voltage level, which is regulated from VDD. The
capacitor
amplitude of VCI1 is from VDD-GND. Place a stabilizing capacitor between
GND.
AVDD
1
O
VGH
1
O
An output voltage from the step-up circuit 2x, 4x ~ 6x of the VCI1 level.
Connect with a stabilizing capacitor.
1
O
An output voltage from the step-up circuit –2x, -3x ~ -5x of the VCI1 level.
Connect with a stabilizing capacitor.
O
Stabilizing
An output voltage from the step-up circuit 2, –1x of the VCI1 level.
capacitor
VDD_18V
1
Stabilizing
capacitor
VCL
O
capacitor between GND. AVDD = 4.5 ~ 5.5V
Stabilizing
capacitor
1
Output 2x VCI1 voltage level from the step-up circuit 1. Place a stabilizing
capacitor
VGL
Stabilizing
Connect with a stabilizing capacitor.
1
O
GVDD
1
I/O
FB
1
I
Reference voltage for Internal logic block
Connect with a stabilizing capacitor
Stabilizing
Reference voltage for power block
capacitor
VREF
Stabilizing
capacitor
Connect with a stabilizing capacitor.
Stabilizing
Output source driver grayscale reference voltage level.
capacitor
Backlight voltage
The feedback voltage from DC-DC
enerator
DRV
1
O
DC-DC
voltage
generator
Source/Gate Driver and VCOM Signals
G1~G162
162
O
LCD
Output gate driver signals, which has the swing from VGH to VGL
S1~S396
396
O
LCD
Output source driver signals. The D/A converted 64-gray-scale analog voltage
VCOM
1
O
TFT panel
Output a square wave signal with the swing from VcomH - VcomL to the
common
common electrode of TFT panel. The alternating cycle can be set to frame
electrode
inversion or 1-line inversion.
Stabilizing
Output the high level of VCOM voltage. Connect with a capacitor to stabilize.
is output.
VcomH
1
O
VcomL
1
O
capacitor
Stabilizing
Output the low level of VCOM voltage. Connect with a capacitor to stabilize.
capacitor
or open
VDDIO
1
I
Stabilizing
VDDIO input voltage for control pins using
capacitor
VDD
1
I
Stabilizing
Power supply Input
capacitor
VSS
Digital ground pin.
VSSA
Analog ground pin.
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Preliminary Version: 0.6
Preliminary
SPFD54124B
Signal
Pin No.
I/O
Connected with
Function
TE
1
O
MPU
Tearing effect output pin to synchronies MCU to frame writing, activated by
S/W command.
When this pin is not activated (TE function OFF), this pin is DGND level.
PADA0
1
I
This pin is used for glass break detection
PADB0
1
O
This pin is used for glass break detection
PADA1/PADB1
8
Misc. Signal
This pin is used for chip attachment detection
PADA2/PADB2
PADA3/PADB3
PADA4/PADB4
TEST
1
T
Test pin. If not used, please open this pin.
D
Dummy pin. If not used, please open this pin.
TRIM0-9
Dummy
© ORISE Technology Co., Ltd.
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Test pin. If not used, please open this pin.
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Preliminary Version: 0.6
Preliminary
SPFD54124B
6. INSTRUCTIONS
6.1. Outline
The SPFD54124B supports 18-bit data bus interface to configure system via accessing command register. When the command register
is executed, sending the command information to specify which index register would be accessed and following the data to that control
register. Moreover, register accessing operation should cooperate with DC/X, WRX, RDX signal for SPFD54124B to recognize the
control instruction. And command instruction can be accomplished using all system interfaces (18-bit, 16-bit, 9-bit, 8-bit 80- or
68-system and SPI)..
6.1.1.
System Function Command List and Description
Table 6.1.1 list all the system function command. After the H/W reset by RESX pin or S/W reset by SWRESET command, each internal
register becomes default state (Refer “RESET TABLE” section). Commands 10h, 12h, 13h, 20h, 21h, 26h, 28h, 29h, 30h, 33h, 36h (ML
parameter only), 37h, 38h and 39h are updated during V-sync when Module is in Sleep Out Mode to avoid abnormal visual effects.
During Sleep In mode, these commands are updated immediately. Read status (09h), Read Display Power Mode (0Ah), Read Display
MADCTR (0Bh), Read Display Pixel Format (0Ch), Read Display Image Mode (0Dh), Read Display Signal Mode (0Eh) and Read
Display Self Diagnostic Result (0Fh) of these commands are updated immediately both in Sleep In mode and Sleep Out mode.
Table 6.1.1 System Function command List (1)
Instruction D/CX WRX RDX D17-8
RDDID
RDDST
RDDPM
RDD
MADCTR
RDD
COLMOD
RDDIM
RDDSM
RDDSDR
0
0
0
1
1
1
1
0
1
1
1
1
1
0
1
↑
↑
↑
1
1
1
1
1
NOP
SWRESET
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
↑
1
1
↑
1
1
1
1
1
↑
1
↑
1
1
↑
1
1
↑
1
1
↑
1
1
1
1
1
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
-
0
0
0
-
0
0
0
-
0
0
0
-
0
0
0
-
0
0
1
-
0
0
0
-
0
1
0
-
D1
D0
1
-
(Hex)
Function
1
-
↑
-
(00h) No Operation
(01h) Software reset
(04h) Read Display ID
Dummy read
ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10
ID1 read
ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20
ID2 read
ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30
ID3 read
0
0
0
0
1
0
0
1
(09h) Read Display Status
Dummy read
BSTON MY
MX
MV
ML
RGB
MH
ST24
ST23 IFPF2 IFPF1 IFPF0 IDMON PTLON SLOUT NORON
VSSON ST14 INVON ST12 ST11 DISON TEON GCS2
GCS1 GCS0 TELOM HSON VSON PCKON DEON ST0
0
0
0
0
1
0
1
0
(0Ah) Read Display Power Mode
Dummy read
↑
-
BSTON IDMON PTLON SLPOUT NORON DISON
1
-
↑
↑
↑
↑
1
↑
↑
↑
↑
↑
1
↑
↑
1
↑
↑
1
↑
↑
1
↑
↑
1
↑
↑
0
-
0
-
0
-
0
-
1
-
0
-
-
(0Bh) Read Display MADCTR
Dummy read
MX
MY
MV
ML
RGB MH
D1
D0
0
0
0
0
1
1
0
0
(0Ch) Read Display Pixel Format
Dummy read
D7
D6
D5
D4
D3
IFPF2 IFPF1 IFPF0
0
0
0
0
1
1
0
1
(0Dh) Read Display Image Mode
Dummy read
VSSON D6
INVON
D4
D3 GCS2 GCS1 GCS0
0
0
0
0
1
1
1
0
(0Eh) Read Display Signal Mode
Dummy read
TEON TELOM HSON VSON PCKON DEON D1
D0
0
0
0
0
1
1
1
1
(0Fh) Read Display Self-diagnostic result
Dummy read
RELD FUND ATTD BRD
D3
D2
D1
D0
-
“-“: Don＇t care, can be set to VDDIO or DGND level
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Preliminary Version: 0.6
Preliminary
SPFD54124B
Table 6.1.1 System Function command List (2)
Instruction D/CX WRX RDX D17-8
SLPIN
SLPOUT
PTLON
NORON
INVOFF
INVON
GAMSET
DISPOFF
DISPON
CASET
RASET
RAMWR
RAMHD
RGBSET
D7
D6
D5
D4
D3
D2
D1
D0
(Hex)
0
0
0
0
0
0
0
GC6
0
0
0
XS14
XS6
XE14
XE6
0
YS14
YS6
YE14
YE6
0
0
0
0
1
1
1
GC5
1
1
1
XS13
XS5
XE13
XE5
1
YS13
YS5
YE13
YE5
1
1
1
1
0
0
0
GC4
0
0
0
XS12
XS4
XE12
XE4
0
YS12
YS4
YE12
YE4
0
0
0
0
0
0
0
GC3
1
1
1
XS11
XS3
XE11
XE3
1
YS11
YS3
YE11
YE3
0
0
0
0
0
0
1
GC2
0
0
0
XS10
XS2
XE10
XE2
0
YS10
YS2
YE10
YE2
0
0
1
1
0
0
1
GC1
0
0
1
XS9
XS1
XE9
XE1
1
YS9
YS1
YE9
YE1
0
1
0
1
0
1
0
GC0
0
1
0
XS8
XS0
XE8
XE0
1
YS8
YS0
YE8
YE0
(10h)
(11h)
(12h)
(13h)
(20h)
(21h)
(26h)
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
1
1
1
1
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
0
0
0
0
0
0
0
GC7
0
0
0
XS15
XS7
XE15
XE7
0
YS15
YS7
YE15
YE7
0
↑
1
-
0
0
1
0
1
1
0
1
0
1
1
0
1
1
1
1
1
1
1
1
1
↑
↑
1
1
1
1
D17-8
D17-8
-
D7
0
D7
0
R007
:
Ra7
G007
:
Gb7
B007
:
Bc7
D6
0
D6
0
R006
:
Ra6
G006
:
Gb6
B006
:
Bc6
D5
1
D5
1
R005
:
Ra5
G005
:
Gb5
B005
:
Bc5
D4
0
D4
0
R004
:
Ra4
G004
:
Gb4
B004
:
Bc4
D3
1
D3
1
R003
:
Ra3
G003
:
Gb3
B003
:
Bc3
D2
1
D2
1
R002
:
Ra2
G002
:
Gb2
B002
:
Bc2
D1
1
D1
0
R001
:
Ra1
G001
:
Gb1
B001
:
Bc1
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
1
1
1
1
1
1
1
1
1
1
Function
Sleep in & booster off
Sleep out & booster on
Partial mode on
Partial off (Normal)
Display inversion off (normal)
Display inversion on
Gamma curve select
(28h) Display off
(29h) Display on
(2Ah) Column address set
X address start: 0 ≤ XS ≤ 0x83
X address end: XS ≤ XE ≤ 0x83
(2Bh) Row address set
Y address start: 0 ≤ YS ≤ 0xA1
Y address end: YS ≤ YE ≤ 0xA1
(2Ch)
Memory write
D0
Write data
0
(2Eh) Memory read
Dummy read
D0
Read data
1 (2Dh) LUT for 4k,65k , 262K color display
R000
Red tone 0
:
: Ra0
Red tone “31”
G000
Green tone 0
:
: Gb0
Green tone “63”
B000
Blue tone 0
:
: Bc0
Blue tone “31”
“-“: Don’t care, can be set to VDDIO or DGND level
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Preliminary Version: 0.6
Preliminary
SPFD54124B
Table 6.1.1 System Function command List (3)
Instruction D/CX WRX RDX D17-8
0
1
1
1
PTLAR
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
1
0
0
0
0
↑
1
-
↑
1
-
PSL15 PSL14 PSL13 PSL12 PSL11 PSL10 PSL9 PSL8
↑
1
-
1
-
PEL15 PEL14 PEL13 PEL12 PEL11 PEL10 PEL9 PEL8
-
PEL7 PEL6 PEL5 PEL4 PEL3 PEL2 PEL1 PEL0
1
↑
1
0
↑
1
-
1
↑
1
-
TFA15 TFA14 TFA13 TFA12 TFA11 TFA10 TFA9 TFA8
1
↑
1
-
1
↑
1
-
VSA15 VSA14 VSA13 VSA12 VSA11 VSA10 VSA9 VSA8
↑
1
-
↑
1
-
BFA15 BFA14 BFA13 BFA12 BFA11 BFA10 BFA9 BFA8
1
↑
1
-
Partial start address (0,1,2, .., 161)
Partial end address (0,1,2, .., 161)
VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0
1
(30h) Partial start/end address set
TFA7 TFA6 TFA5 TFA4 TFA3 TFA2 TFA1 TFA0
1
SCRLAR
Function
PSL7 PSL6 PSL5 PSL4 PSL3 PSL2 PSL1 PSL0
↑
(Hex)
BFA7 BFA6 BFA5 BFA4 BFA3 BFA2 BFA1 BFA0
0
0
1
1
0
0
1
1
(33h) Scroll area set
Top fixed area (0,1,2, .., 161)
Vertical scroll area (0,1,2, .., 161)
Bottom fixed area (0,1,2, .., 161)
TEON
MADCTR
0
↑
1
-
0
0
1
1
0
1
0
0
(34h) Tearing effect line off
0
↑
1
-
0
0
1
1
0
1
0
1
(35h) Tearing effect mode set & on
1
↑
1
-
0
0
0
0
0
0
0
TELOM
0
↑
1
-
0
0
1
1
0
1
1
0
1
↑
1
-
MY
MX
MV
ML
RGB
MH
0
0
0
TEOFF
↑
1
-
0
0
1
1
0
1
1
1
M=”0”: Mode1, M=”1”: Mode2
(36h) Memory data access control
(37h) Scroll start address of RAM
1
↑
1
-
SSA15 SSA14 SSA13 SSA12 SSA11 SSA10 SSA9 SSA8
1
↑
1
-
SSA7 SSA6 SSA5 SSA4 SSA3 SSA2 SSA1 SSA0
IDMOFF
0
↑
1
-
0
0
1
1
1
0
0
0
IDMON
0
↑
1
-
0
0
1
1
1
0
0
1
(39h) Idle mode on
0
↑
1
-
0
0
1
1
1
0
1
0
(3Ah) Interface pixel format
VSCSAD
COLMOD
1
↑
1
-
0
0
0
0
0
IFPF2
IFPF1
IFPF0
0
1
-
1
1
0
1
1
0
1
0
1
↑
1
1
1
0
1
↑
1
1
RDID3
1
0
RDID2
1
1
RDID1
↑
1
1
↑
-
-
-
-
-
-
-
-
-
↑
1
-
ID17
ID16
ID15
ID14
ID13
ID12
ID11
ID10
-
1
1
0
1
1
0
1
1
↑
-
-
-
-
-
-
-
-
-
↑
1
-
ID27
ID26
ID25
ID24
ID23
ID22
ID21
ID20
-
1
1
0
1
1
1
0
0
↑
-
-
-
-
-
-
-
-
-
↑
-
ID37
ID36
ID35
ID34
ID33
ID32
ID31
ID30
SSA = 0, 1, 2, …, 161
(38h) Idle mode off
Interface format
(DAh) Read ID1
Dummy read
Read parameter
(DBh) Read ID2
Dummy read
Read parameter
(DCh) Read ID3
Dummy read
Read parameter
“-“: Don’t care, can be set to VDDIO or DGND level
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Preliminary Version: 0.6
Preliminary
SPFD54124B
6.1.2.
Panel Function Command List and Description
Table 6.1.2 list all the panel function command. Panel function command is only accessible when EXTC is pulled high state (by VDDIO).
Table 6.1.2 Panel Function command List (1)
Instruction D/CX WRX RDX D17-8
D0
1
0
0
0
0
1
↑
1
-
0
0
ICM
DW
DP
EP
↑
1
-
1
0
1
1
↑
1
-
-
-
1
↑
1
-
↑
1
-
↑
1
-
1
0
↑
1
-
1
↑
1
-
↑
1
-
0
↑
1
-
1
↑
1
-
1
↑
1
-
1
↑
1
-
0
1
0
↑
↑
↑
1
1
1
-
1
0
1
0
0
0
1
↑
1
-
-
-
0
1
↑
↑
1
1
-
1
0
0
0
1
DISSET5
D1
1
1
RGB
PRCTR
D2
0
1
INVCTR
D3
1
0
FRMCTR3
D4
-
1
FRMCTR2
D5
1
1
FRMCTR1
D6
↑
0
RGBCTR
D7
0
↑
1
-
0
0
1
0
0
Function
(B0h) Set RGB signal control
ICM: RGB data ascess select
DW: RGB interface bus width set
DP,HSP,VSP:PCLK,HS,VS polarity set
HSP VSP
0
0
0
1
FP0 FP0 FP0 FP0
[3]
[2]
[1]
[0]
BP0 BP0 BP0 BP0
[3]
[2]
[1]
[0]
RTN0 RTN0 RTN0 RTN0
[3]
[2]
[1]
[0]
1
1
0
0
1
0
FP1 FP1 FP1 FP1
[3]
[2]
[1]
[0]
BP1 BP1 BP1 BP1
[3]
[2]
[1]
[0]
RTN1 RTN1 RTN1 RTN1
[3]
[2]
[1]
[0]
1
1
0
0
1
1
FP2 FP2 FP2 FP2
[3]
[2]
[1]
[0]
BP2 BP2 BP2 BP2
[3]
[2]
[1]
[0]
RTN2 RTN2 RTN2 RTN2
[3]
[2]
[1]
[0]
1
1
0
1
0
0
0
0
0
NLA NLB NLC
1
1
0
1
0
1
VBP VBP VBP VBP
[3]
[2]
[1]
[0]
1
1
0
1
1
1
NO1 NO0 SDT1 STD0 EQ1 EQ0
0
(Hex)
PTG1 PTG0 PT1
PT0
(B1h)
In normal mode (Full colors)
FP0: Front porch in normal mode
BP0: Back porch in normal mode
RTN0: Number of clock / one line
(B2h)
In Idle mode (8-colors)
FP1: Front porch in idle mode
BP1: Back porch in idle mode
RTN1: Number of clock / one line
(B3h)
In partial mode + Full colors
FP2: Front porch in partial mode
BP2: Back porch in partial mode
RTN2: Number of clock / one line
(B4h) Display inversion control
NLA, NLB, NLC: set inversion
(B5h)
RGB I/F Blanking porch setting
Vertical back porch in RGB mode
(B6h) Display function setting
NO: the amount of non-overlap
SDT: set amount of source delay
PT: No display area source/ VCOM/
Gate output control
EQ: set EQ period
“-“: Don’t care, can be set to VDDIO or DGND level
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APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
Table 6.1.2 Panel Function Command List (2)
Instruction D/CX WRX RDX D17-8
D7
D6
D5
D4
D3
D2
D1
D0
↑
1
-
1
0
1
1
0
0
0
0
↑
1
-
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
1
0
1
PWCTR2
1
↑
1
0
PWCTR1
↑
1
-
Function
(C0h) Power control setting
VRH: Set the GVDD voltage
VC : Set the VCI1 voltage
Power control setting
VRH4 VRH3 VRH2 VRH1 VRH0
VC2 VC1 VC0
1
↑
1
-
0
0
0
0
0
BT2
BT1
↑
1
-
1
0
1
1
0
0
1
0
1
↑
1
-
0
0
0
0
0
(C1h) BT: set AVDD/VCL/ VGH/ VGL voltage
BT0
0
PWCTR3
(Hex)
APA2 APA1 APA0
DCA2 DCA1 DCA0
(C2h) n normal mode (Full colors)
APA: adjust the operational amplifier
DCA: adjust the booster circuit for Idle
mode
1
0
0
0
0
1
1
0
1
↑
1
-
0
0
0
0
0
↑
1
-
↑
1
-
1
↑
1
-
↑
1
-
↑
1
-
1
↑
1
-
0
↑
1
-
1
0
1
1
0
1
↑
1
-
0
0
1
RVMOF
CTR
0
1
0
VMCTR2
0
-
1
VMCTR1
-
1
0
PWCTR5
1
↑
1
PWCTR4
↑
0
↑
1
1
-
nVM VMF6 VMF5 VMF4 VMF3 VMF2 VMF1 VMF0
0
↑
-
1
1
↑
-
0
1
1
1
0
0
0
(C8h) VCOM control 4
RVMF RVMF RVMF RVMF RVMF RVMF RVMF
Read the VMOF value form NV memory
nVM
6
5
4
3
2
1
0
0
1
1
(C3h) In Idle mode (8-colors)
APB: adjust the operational amplifier
DCB: adjust the booster circuit for Idle
mode
0
0
0
0
0 DCB2 DCB1 DCB0
I
1
0
1
1
0
1
0
0
(C4h) In partial mode + Full colors
APC: adjust the operational amplifier
0
0
0
0
0 APC2 APC1 APC0
DCC: adjust the booster circuit for Idle
mode
0
0
0
0
0 DCC2 DCC1 DCC0
1
0
1
1
0
1
0
1
(C5h) VCOM control 1
nVM: VCOM input select
VMH: VCOMH voltage control
nVM VMH6 VMH 5 VMH4 VMH3 VMH2 VMH1 VMH0
APB2 APB1 APB0
1
1
0
(C6h)
VMA5 VMA4 VMA3 VMA2 VMA1 VMA0
VCOM control 2
VMA: VCOMAC voltage control
1
“-“: Don’t care, can be set to VDDIO or DGND level
Table 6.1.2 Panel Function Command List (3)
Instruction D/CX WRX RDX D17-8
WRID2
WRID3
D6
D5
D4
D3
D2
D1
D0
↑
1
-
1
1
0
1
0
0
0
1
1
↑
1
-
1
0
↑
1
-
1
1
↑
1
-
1
0
WRID1
D7
0
↑
1
-
1
ID16 ID15 ID14 ID13 ID12 ID11 ID10
1
0
1
0
0
0
1
ID26 ID25 ID24 ID23 ID22 ID21 ID20
1
0
1
0
0
1
0
1
-
↑
1
1
-
1
1
0
1
0
0
1
1
↑
-
-
-
-
-
-
-
-
-
1
1
↑
-
ID417 ID416 ID415 ID414 ID413 ID412 ID411 ID410
1
1
↑
-
ID427 ID426 ID425 ID424 ID423 ID422 ID421 ID420
1
1
↑
-
ID437 ID436 ID435 ID434 ID43 ID432 ID431 ID430
1
NVCTR1
↑
1
RDID4
1
0
1
-
↑
-
NVCTR3
ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30
1
1
0
1
1
0
0
1
1
1
0
1
1
1
1
0
1
1
0
1
1
1
1
1
0
NVCTR2
Function
(D0h) Panel ID code
Write ID1 value to NV memory
Set the LCM ID code at ID1
(D1h) Panel version code
Write ID2 value to NV memory
Set the LCM version code at ID2
(D2h) Driver maker Project code
Write ID3 value to NV memory
Set the project code at ID3
ID447 ID446 ID445 ID444 ID443 ID442 ID441 ID440
0
↑
1
(Hex)
↑
1
-
1
↑
1
-
0
↑
1
-
1
↑
1
-
(D3h)
IC Vender Coder
Dummy read
ID41:IC Vender Coder
ID42: IC Part Number Coder
ID43 & ID44: Chip version coder
(D9h) NV memory function controller 1
Please refer to ‘OTP programming
procedure’ for details.
(DEh) NV memory function controller 2
Please refer to ‘OTP programming
procedure’ for details.
(DFh) NV memory function controller 3
Please refer to ‘OTP programming
procedure’ for details.
“-“: Don’t care, can be set to VDDIO or DGND level
© ORISE Technology Co., Ltd.
Proprietary & Confidential
18
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
Table 6.1.2 Panel Function Command List (4)
Instruction D/CX WRX RDX D17-8 D7 D6
D5
D4
D3
D2
D1
D0
1
0
0
0
0
0
(Hex) Function
0
1
1
↑
1
-
-
-
1
↑
1
-
-
-
1
↑
1
-
-
-
PVR1V2[5] PVR1V2[4] PVR1V2[3] PVR1V2[2] PVR1V2[1] PVR1V2[0]
1
↑
1
-
-
-
PVR1V61[5] PVR1V61[4] PVR1V61[3] PVR1V61[2] PVR1V61[1] PVR1V61[0]
1
↑
1
-
-
-
PVR1V62[5] PVR1V62[4] PVR1V62[3] PVR1V62[2] PVR1V62[1] PVR1V62[0]
1
↑
1
-
-
-
-
PVR1V63[4] PVR1V63[3] PVR1V63[2] PVR1V63[1] PVR1V63[0]
1
↑
1
-
-
-
-
PVR2V13[4] PVR2V13[3] PVR2V13[2] PVR2V13[1] PVR2V13[0]
1
↑
1
-
-
-
-
PVR2V50[4] PVR2V50[3] PVR2V50[2] PVR2V50[1] PVR2V50[0] (E0h) adjustment
1
↑
1
-
-
-
-
-
1
↑
1
-
-
-
-
-
PVR3V8[3] PVR3V8[2] PVR3V8[1] PVR3V8[0]
1
↑
1
-
-
-
-
-
PVR3V20[3] PVR3V20[2] PVR3V20[1] PVR3V20[0]
1
↑
1
-
-
-
-
-
PVR3V27[3] PVR3V27[2] PVR3V27[1] PVR3V27[0]
1
↑
1
-
-
-
-
-
PVR3V36[3] PVR3V36[2] PVR3V36[1] PVR3V36[0]
1
↑
1
-
-
-
-
-
PVR3V43[3] PVR3V43[2] PVR3V43[1] PVR3V43[0]
1
↑
1
-
-
-
-
-
PVR3V55[3] PVR3V55[2] PVR3V55[1] PVR3V55[0]
1
GAMCTRP1
↑
↑
1
-
-
-
-
-
PVR3V59[3] PVR3V59[2] PVR3V59[1] PVR3V59[0]
-
1
1
-
PVR1V0[4] PVR1V0[3] PVR1V0[2] PVR1V0[1] PVR1V0[0]
PVR1V1[5] PVR1V1[4] PVR1V1[3] PVR1V1[2] PVR1V1[1] PVR1V1[0]
Gamma
PVR3V4[3] PVR3V4[2] PVR3V4[1] PVR3V4[0]
“-“: Don’t care, can be set to VDDIO or DGND level
Table 6.1.2 Panel Function Command List (5)
Instruction D/CX WRX RDX D17-8 D7 D6
D5
D4
D3
D2
D1
D0
1
0
0
0
0
1
(Hex) Function
0
1
1
↑
1
-
-
-
1
↑
1
-
-
-
1
↑
1
-
-
-
NVR1V2[5] NVR1V2[4] NVR1V2[3] NVR1V2[2] NVR1V2[1] NVR1V2[0]
1
↑
1
-
-
-
NVR1V61[5] NVR1V61[4] NVR1V61[3] NVR1V61[2] NVR1V61[1] NVR1V61[0]
1
↑
1
-
-
-
NVR1V62[5] NVR1V62[4] NVR1V62[3] NVR1V62[2] NVR1V62[1] NVR1V62[0]
1
↑
1
-
-
-
-
NVR1V63[4] NVR1V63[3] NVR1V63[2] NVR1V63[1] NVR1V63[0]
1
↑
1
-
-
-
-
NVR2V13[4] NVR2V13[3] NVR2V13[2] NVR2V13[1] NVR2V13[0]
1
↑
1
-
-
-
-
NVR2V50[4] NVR2V50[3] NVR2V50[2] NVR2V50[1] NVR2V50[0] (E1h) adjustment
1
↑
1
-
-
-
-
-
1
↑
1
-
-
-
-
-
NVR3V8[3] NVR3V8[2] NVR3V8[1] NVR3V8[0]
1
↑
1
-
-
-
-
-
NVR3V20[3] NVR3V20[2] NVR3V20[1] NVR3V20[0]
1
↑
1
-
-
-
-
-
NVR3V27[3] NVR3V27[2] NVR3V27[1] NVR3V27[0]
1
↑
1
-
-
-
-
-
NVR3V36[3] NVR3V36[2] NVR3V36[1] NVR3V36[0]
1
↑
1
-
-
-
-
-
NVR3V43[3] NVR3V43[2] NVR3V43[1] NVR3V43[0]
1
↑
1
-
-
-
-
-
NVR3V55[3] NVR3V55[2] NVR3V55[1] NVR3V55[0]
1
GAMCTRN1
↑
↑
1
-
-
-
-
-
NVR3V59[3] NVR3V59[2] NVR3V59[1] NVR3V59[0]
-
1
1
-
NVR1V0[4] NVR1V0[3] NVR1V0[2] NVR1V0[1] NVR1V0[0]
NVR1V1[5] NVR1V1[4] NVR1V1[3] NVR1V1[2] NVR1V1[1] NVR1V1[0]
Gamma
NVR3V4[3] NVR3V4[2] NVR3V4[1] NVR3V4[0]
“-“: Don’t care, can be set to VDDIO or DGND level
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Preliminary Version: 0.6
Preliminary
SPFD54124B
6.2. System Command Description
6.2.1.
NOP (00h)
00H
NOP (No Operation)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
NOP
0
↑
1
-
0
0
0
0
0
0
0
0
(00h)
Parameter
No Parameter
NOTE: “-” Don’t care, can be set to VDDIO or DGND level, can be set to VDDIO or DGND level
-
-This command is empty command. It does not have effect on the display module.
Description
Restriction
-However it can be used to terminate RAM data write or read as described in RAMWR (Memory Write), RAMHD
(Memory Read) and parameter write commands.
-
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
N/A
N/A
N/A
-
Flow Chart
6.2.2.
SWRESET (01h): Software Reset
01H
SWRESET (Software Reset)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
SWRESET
0
↑
1
-
0
0
0
0
0
0
0
1
(01h)
Parameter
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
Description
No Parameter
-
-When the Software Reset command is written, it causes software reset. It resets the commands and parameters to their
S/W Reset default values and all source outputs are set to DGND (display off). (See default tables in each command
description)
Note: The Frame Memory contents are not affected by this command.
-It will be necessary to wait 5msec before sending new command following software reset.
-The display module loads all display supplier’s factory default values to the registers during 5msec.
Restriction
-If Software Reset is applied during Sleep Out mode, it will be necessary to wait 120msec before sending Sleep Out
command.
-Software Reset command cannot be sent during Sleep Out sequence.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
© ORISE Technology Co., Ltd.
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Availability
Yes
Yes
Yes
Yes
Yes
20
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
N/A
N/A
N/A
SWRESET (01h)
Legend
Command
Display whole blank
screen
Parameter
Display
Flow Chart
Action
Set Commands
to S/W Default
Value
Mode
Sequential
transfer
Sleep In Mode
© ORISE Technology Co., Ltd.
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APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
6.2.3.
RDDID (04h): Read Display ID
04H
RDDID (Read Display ID)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
RDDID
0
↑
1
-
0
0
0
0
0
1
0
0
(04h)
1 Parameter
st
1
1
↑
-
-
-
-
-
-
-
-
-
-
nd
1
1
↑
-
ID17
ID16
ID15
ID14
ID13
ID12
ID11
ID10
rd
1
1
↑
-
ID27
ID26
ID25
ID24
ID23
ID22
ID21
ID20
th
1
1
↑
-
ID37
ID36
ID35
ID34
ID33
ID32
ID31
ID30
2 Parameter
3 Parameter
4 Parameter
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
-This read byte returns 24-bits display identification information.
st
-The 1 parameter is dummy data
nd
Description
-The 2 parameter (ID17 to ID10): LCD module’s manufacturer ID.
rd
-The 3 parameter (ID27 to ID20): LCD module/driver version ID
th
Restriction
Register
Availability
-The 4 parameter (ID37 to UD30): LCD module/driver ID.
NOTE: Commands RDID1/2/3(DAh, DBh, DCh) read data correspond to the parameters 2,3,4 of the command 04h,
respectively.
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Status
Default
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
ID1
38h
38h
38h
Serial I/F Mode
RDDID (04h)
ID3
4Fh
4Fh
4Fh
Parallel I/F M
RDDID (04h)
Default Value
ID2
8xh
8xh
8xh
Legend
Host
Driver
Dummy Clock
Dummy Read
Command
Parameter
Display
Flow Chart
Send ID1[7:0]
Send ID1[7:0]
Send ID2[7:0]
Send ID2[7:0]
Action
Mode
Sequential
transfer
Send ID3[7:0]
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Send ID3[7:0]
22
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
6.2.4.
RDDST (09h): Read Display Status
09H
RDDST (Read Display Status)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
RDDST
0
↑
1
-
0
0
0
0
1
0
0
1
(09h)
1 Parameter
st
1
1
↑
-
-
-
-
-
-
-
-
-
-
nd
1
1
↑
-
BSTON
MY
MX
MV
rd
1
1
↑
-
ST23
IFPF2
IFPF1
IFPF0
th
1
1
↑
-
VSSON
ST14
INVON
ST12
2 Parameter
3 Parameter
4 Parameter
th
5 Parameter
1
1
GCS1
↑
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
GCS0 TELOM HSON
ST24
NORO
IDMON PTLON SLOUT
N
ST11 DISON TEON GCS2
ML
RGB
MH
VSON PCKON DEON
ST0
This command indicates the current status of the display as described in the table below:
Bit
Description
BSTON
Booster Voltage Status
MY
Row Address Order (MY)
MX
Column Address Order (MX)
MV
Row/Column Exchange (MV)
ML
Vertical Refresh Order (ML)
RGB
RGB/ BGR Order (RGB)
MH
Horizontal Order (MH)
ST24
ST23
IFPF2
For Future Use
For Future Use
Interface Color
Definition
Pixel
Format
Idle Mode On/Off
Partial Mode On/Off
Sleep In/Out
NORON
Display Normal Mode On/Off
VSSON
ST14
INVON
ST12
ST11
DISON
TEON
GCSEL2
Vertical Scrolling Status
Horizontal Scroll Status
Inversion Status
All Pixels On (Not Used)
All Pixels Off (Not Used)
Display On/Off
Tearing effect line on/off
GCSEL1
Description
IFPF1
IFCPF0
IDMON
PTLON
SLPOUT
Gamma Curve Selection
GCSEL0
TELOM
HSON
VSON
PCLKON
DEON
ST0
Tearing effect line mode
Horizontal Sync. (HS)
Vertical Sync, (VS, RGB I/F)
Pixel Clock (PCLK, RGB I/F)
Data Enable (DE, RGB I/F)
For Future Use
Value
‘1’ =Booster on,
‘0’ =Booster off
‘1’ =Decrement, (Bottom to Top, when MADCTL (36h) D7=’1’)
‘0’ =Increment, (Top to Bottom, when MADCTL (36h) D7=’0’)
‘1’ =Decrement, (Right to Left, when MADCTL (36h) D6=’1’)
‘0’ =Increment, (Left to Right, when MADCTL (36h) D6=’0’)
‘1’ = Row/column exchange, (when MADCTL (36h) D5=’1’)
‘0’ = Normal, (when MADCTL (36h) D5=’0’)
‘1’ =Decrement, (LCD refresh Bottom to Top, when MADCTL
D4=’1’)
“0”=Increment, (LCD refresh Top to Bottom, when MADCTL
D4=’0’)
‘1’ =BGR, (When MADCTL (36h) D3=’1’)
‘0’ =RGB, (When MADCTL (36h) D3=’0’)
‘1’ =Decrement, (LCD refresh Right to Left, when MADCTL
D2=’1’)
‘0’ =Increment, (LCD refresh Left to Right, when MADCTL
D2=’0’)
‘0’
‘0’
(36h)
(36h)
(36h)
(36h)
“011” = 12-bits / pixel,
“101” = 16-bits / pixel,
“110” = 18-bits / pixel,others are no define
‘1’ = On, “0” = Off
‘1’ = On, “0” = Off
‘1’ = Out, “0” = In
‘1’ = Normal Display,
‘0’ = Partial Display
‘1’ = Scroll on,“0” = Scroll off
‘0’
‘1’ = On, “0” = Off
‘0’
‘0’
‘1’ = On, “0” = Off
‘1’ = On, “0” = Off
“000” = GC0
“001” = GC1
“010” = GC2
“011” = GC3
”100” to “111” = Not defined
‘0’ = mode1, ‘1’ = mode2
‘1’ = On, ‘0’ = Off
‘1’ = On, ‘0’ = Off
‘1’ = On, ‘0’ = Off
‘1’ = On, ‘0’ = Off
‘0’
Note: ST0, ST11-ST12, ST14, ST23, ST24 are set to ‘0’
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APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
Restriction
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Status
Default
Power On Sequence
S/W Reset
H/W Reset
ST[31-24]
0000-0000
0xxx-xx00
0000-0000
Serial I/F Mode
Parallel I/F Mode
RDDST (09h)
Default Value (ST31 to ST0)
ST[23-16]
ST[15-8]
ST[7-0]
0110-0001 0000-0000 0000-0000
0xxx-0001 0000-0000 0000-0000
0110-0001 0000-0000 0000-0000
RDDST (09h)
Host
Driver
Dummy Clock
Dummy Read
Legend
Command
Flow Chart
Send ST[31:24]
Send ST[31:24]
Parameter
Display
Send ST[23:16]
Send ST[23:16]
Send ST[15:8]
Send ST[15:8]
Action
Mode
Sequential
transfer
Send ST[7:0]
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Send ST[7:0]
24
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
6.2.5.
RDDPM (0Ah): Read Display Power Mode
0AH
RDDPM (Read Display Power Mode)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
RDDPM
0
↑
1
-
0
0
0
0
1
0
1
0
(0Ah)
1 Parameter
1
1
↑
-
-
-
-
-
-
-
D1
D0
st
SLPOU NORO
nd
2 Parameter
1
1
BSTON IDMON PTLON
DISON
↑
T
N
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
Description
This command indicates the current status of the display as described in the table below:
Bit
Description
Value
“1”=Booster on,
BSTON
Booster Voltage Status
“0”=Booster off
“1” = Idle Mode On,
IDMON
Idle Mode On/Off
“0” = Idle Mode Off
“1” = Partial Mode On,
PTLON
Partial Mode On/Off
“0” = Partial Mode Off
“1” = Sleep Out,
SLPON
Sleep In/Out
“0” = Sleep In
“1” = Normal Display,
NORON
Display Normal Mode On/Off
“0” = Partial Display
“1” = Display On,
DISON
Display On/Off
“0” = Display Off
D1
Not Used
“0”
D0
Not Used
“0”
Restriction
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value (D7 to D0)
0000_1000 (08h)
0000_1000 (08h)
0000_1000 (08h)
Default
Legend
Serial I/F Mode
Parallel I/F Mode
Command
RDDPM (0Ah)
RDDPM (0Ah)
Parameter
Flow Chart
Host
Driver
Send D[7:0]
Dummy Read
Display
Action
Mode
Send D[7:0]
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Sequential
transfer
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
6.2.6.
RDDMADCTR (0Bh): Read Display MADCTR
0BH
Inst / Para
RDDMADCTR
st
1 Parameter
RDDMADCTR (Read Display MADCTR)
D/CX
0
1
WRX
↑
1
RDX
1
D17-8
-
D7
0
-
↑
nd
2 Parameter
1
1
MX
↑
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
Description
D6
0
-
D5
0
-
D4
0
-
D3
1
-
D2
0
-
D1
1
-
D0
1
-
MY
MV
ML
RGB
MH
D1
(Code)
(0Bh)
-
D0
This command indicates the current status of the display as described in the table below:
Bit
Description
Value
‘1’ = Bottom to Top (When MADCTL B7=’1’)
MX
Row Address Order
‘0’ = Top to Bottom (When MADCTL B7=’0’)
‘1’ = Right to Left (When MADCTL B6=’1’)
MY
Column Address Order
‘0’ = Left to Right (When MADCTL B6=’0’)
‘1’ = Row/column exchange (MV=1)
MV
Row/Column Order (MV)
‘0’ = Normal (MV=0)
‘1’ =LCD Refresh Bottom to Top
ML
Vertical Refresh Order
‘0’ =LCD Refresh Top to Bottom
RGB
RGB/BGR Order
‘1’ =BGR, “0”=RGB
‘1’ =LCD Refresh Right to Left
MH
Horizontal order
‘0’ =LCD Refresh Left to Right
D1
Not Used
‘0’
D0
Not Used
‘0’
Restriction
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value (D7 to D0)
0000_0000 (00h)
No change
0000_0000 (00h)
Serial I/F Mode
RDDMADCTR (0Bh)
Legend
Parallel I/F Mode
RDDMADCTR (0Bh)
Command
Host
Driver
Flow Chart
Send D[7:0]
Dummy Read
Parameter
Display
Action
Mode
Send D[7:0]
Sequential
transfer
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APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
6.2.7.
RDDCOLMOD (0Ch): Read Display Pixel Format
0CH
RDDCOLMOD (Read Display Pixel Format)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
RDDCOLMOD
0
↑
1
-
0
0
0
0
1
1
0
0
(0Ch)
1
1
↑
-
-
-
-
-
-
-
-
-
-
VIPF2
VIPF1
VIPF0
D3
IFPF2
IFPF1
IFPF0
st
1 Parameter
nd
2 Parameter
1
1
VIPF3
↑
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
-This command indicates the current status of the display as described in the table below:
IFPF[2:0]
MCU Interface Color Format
011
3
12-bits/pixel
101
5
16-bits/pixel
110
6
18-bits/pixel
111
7
No used
Others are no define and invalid
Description
VIPF[3:0]
0101
5
0110
6
0111
7
1110
14
Others are no define and invalid
RGB Interface Color Format
16-bits/pixel (1-times data transfer)
18-bits/pixel (1-times data transfer)
No used
18-bits/pixel (3-times data transfer)
Restriction
Availability
Yes
Yes
Yes
Yes
Yes
Status
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Default Value
IFPF[2:0]
VIPF[3:0]
0110 (18-bits/pixel)
0110 (18-bits/pixel)
No Change
No Change
0110 (18-bits/pixel)
0110 (18-bits/pixel)
Default
Power On Sequence
S/W Reset
H/W Reset
Serial I/F Mode
RDDCOLMOD (0Ch)
Legend
Parallel I/F Mode
RDDCOLMOD (0Ch)
Command
Host
Driver
Flow Chart
Send D[7:0]
Dummy Read
Parameter
Display
Action
Mode
Send D[7:0]
Sequential
transfer
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Preliminary Version: 0.6
Preliminary
SPFD54124B
6.2.8.
RDDIM (0Dh): Read Display Image Mode
0DH
RDDIM (0Dh): Read Display Image Mode
Inst / Para
D/CX WRX
RDX D17-8
D7
RDDIM
0
1
0
↑
st
1 Parameter
1
1
↑
nd
2 Parameter
1
1
VSSON
↑
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
Description
D6
0
D6
D5
0
INVON
D4
0
D4
D3
1
D3
D2
1
GCS2
D1
0
GCS1
D0
1
GCS0
(Code)
(0Dh)
-
This command indicates the current status of the display as described in the table below:
Bit
Description
Value
“1” = Vertical scrolling is On,
VSSON Vertical Scrolling On/Off
“0” = Vertical scrolling is Off
D6
Horizontal Scrolling On/Off
“0” (Not used)
“1” = Inversion is On,
INVON Inversion On/Off
“0” = Inversion is Off
D4
All Pixels On
“0” (Not used)
D3
All Pixels Off
“0” (Not used)
“000” = GC0,
GCS2
“001” = GC1,
GCS1
Gamma Curve Selection
“010” = GC2,
GCS0
“011” = GC3, ”100” to “111” = Not defined
Restriction
-
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value (D7 to D0)
0000_0000 (00h)
0000_0000 (00h)
0000_0000 (00h)
Serial I/F Mode
RDDIM (0Dh)
Legend
Parallel I/F Mode
RDDIM (0Dh)
Command
Host
Driver
Flow Chart
Send D[7:0]
Dummy Read
Parameter
Display
Action
Mode
Send D[7:0]
Sequential
transfer
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APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
6.2.9.
RDDSM (0Eh): Read Display Signal Mode
RDDSM (0Eh): Read Display Signal Mode
0EH
Inst / Para
D/CX WRX
RDX D17-8
D7
D6
D5
RDDSM
0
1
0
0
0
↑
st
1 Parameter
1
1
↑
nd
2 Parameter
1
1
TEON TELOM HSON
↑
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
Description
D4
D3
D2
0
1
1
VSON PCKON DEON
D1
1
D1
D0
0
D0
(Code)
(0Eh)
-
This command indicates the current status of the display as described in the table below:
Bit
Description
Value
“1” = On,
TEON
Tearing Effect Line On/Off
“0” = Off
“0” = mode1,
TELOM
Tearing effect line mode
“1” = mode2
“1” = On,
HSON
Horizontal Sync. (RGB I/F) On/Off
“0” = Off
“1” = On,
VSON
Vertical Sync. (RGB I/F) On/Off
“0” = Off
“1” = On,
PCKON
Pixel Clock (PCLK, RGB I/F) On/Off
“0” = Off
“1” = On,
DEON
Data Enable (DE, RGB I/F) On/Off
“0” = Off
“1” = On,
D1
Not Used
“0” = Off
“1” = On,
D0
Not Used
“0” = Off
Restriction
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value (D7 to D0)
0000_0000 (00h)
0000_0000 (00h)
0000_0000 (00h)
Serial I/F Mode
RDDSM (0Eh)
Legend
Parallel I/F Mode
RDDSM (0Eh)
Command
Host
Driver
Flow Chart
Send D[7:0]
Dummy Read
Parameter
Display
Action
Mode
Send D[7:0]
Sequential
transfer
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Preliminary Version: 0.6
Preliminary
SPFD54124B
6.2.10. RDDSDR (0Fh): Read Display Self-Diagnostic Result
0FH
RDDSDR (0Fh): Read Display Self-Diagnostic Result
Inst / Para
D/CX WRX
RDX D17-8
D7
RDDSDR
0
1
0
↑
st
1 Parameter
1
1
↑
nd
2 Parameter
1
1
RELD
↑
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
Description
D6
0
FUND
D5
0
ATTD
D4
0
BRD
D3
1
D3
D2
1
D2
D1
1
D1
D0
1
D0
(Code)
(0Fh)
-
This command indicates the current status of the display as described in the table below:
Bit
Description
Value
RELD
Register Loading Detection
FUND
Functionality Detection
ATTD
Chip Attachment Detection
BRD
Display Glass Break Detection
D3
Not Used
“0”
D2
Not Used
“0”
D1
Not Used
“0”
D0
Not Used
“0”
Restriction
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value (D7 to D0)
0000_0000 (00h)
0000_0000 (00h)
0000_0000 (00h)
Serial I/F Mode
RDDSDR (0Fh)
Legend
Parallel I/F Mode
RDDSTR (0Fh)
Command
Host
Driver
Flow Chart
Send D[7:0]
Dummy Read
Parameter
Display
Action
Mode
Send D[7:0]
Sequential
transfer
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APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
6.2.11. SLPIN (10h): Sleep In
10H
SLPIN (Sleep In)
Inst / Para
D/CX WRX
RDX D17-8
D7
SLPIN
0
1
0
↑
st
1 Parameter
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
D6
D5
0
0
No parameter
D4
1
D3
0
D2
0
D1
0
D0
0
(Code)
(10h)
-
-This command causes the LCD module to enter the minimum power consumption mode.
-In this mode the DC/DC converter is stopped, Internal display oscillator is stopped, and panel scanning is stopped.
Sleep In
VDDIO
1.6V-3.6V
VDD
2.6V-3.6V
Gate Output
STOP
Source Output
0V
VCOM Output
Description
Blanking display (over 1frame display) *
0V
0V
Internal counter
STOP
Internal Oscillator
STOP
DISCHARGE
DC charge in capacitors
0V or VDD
VGH
0V or VDD
VGL
0V
AVDD
0V or VDD
IC Internal reset
0V
* Note: complete 1 frame display (ex: continue 2-falling edges of VS)
-MCU interface and memory are still working and the memory keeps its contents
-This command has no effect when module is already in sleep in mode. Sleep In Mode can only be exit by the Sleep Out
Command (11h).
Restriction
-It will be necessary to wait 5msec before sending next command, this is to allow time for the supply voltages and clock
circuits to stabilize.
-It will be necessary to wait 120msec after sending Sleep Out command (when in Sleep In Mode) before Sleep In
command can be sent.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Sleep in mode
Sleep in mode
Sleep in mode
Default
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APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
-It takes about 120msec to get into Sleep In mode (booster off state) after SLPIN command issued.
-The results of booster off can be check by RDDST (09h) command Bit31.
Legend
SPLIN (10h)
Flow Chart
Display whole blank
screen (Automatic No
effect to DISP
ON/OFF Command)
Drain charge
from LCD
panel
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Stop
DC/DC
Converte
Command
Parameter
Display
Stop
Internal
Oscillator
Sleep In
32
Action
Mode
Sequential
transfer
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
6.2.12. SLPOUT (11h): Sleep Out
11H
SLPOUT (Sleep Out)
Inst / Para
D/CX WRX
RDX D17-8
D7
SLPOUT
0
1
0
↑
st
1 Parameter
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
D6
D5
0
0
No Parameter
D4
1
D3
0
D2
0
D1
0
D0
1
(Code)
(11h)
-
-This command turns off sleep mode.
-In this mode the DC/DC converter is enabled, Internal display oscillator is started, and panel scanning is started.
Sleep Out
VDDIO
1.6V-3.6V
VDD
2.6V-3.6V
Internal Oscillator
STOP
AVDD
0V or VDD
VGL
0V
VGH
0V or VDD
Internal counter
STOP
IC Internal reset
0V
Gate Output
STOP
Source Output
0V
0V
Memory Contents
VCOM Output
0V
0V
Memory Contents
Description
Start
Start
STOP
Blanking display (over 1frame display) *
If DISPON 29h is set
* Note: complete 1 frame display (ex: continue 2-falling edges of VS)
-This command has no effect when module is already in sleep out mode. Sleep Out Mode can only be exit by the Sleep
In Command (10h).
-It will be necessary to wait 5msec before sending next command, this is to allow time for the supply voltages and clock
circuits to stabilize.
Restriction
-DRIVER loads all default values of extended and test command to the registers during this 5msec and there cannot be
any abnormal visual effect on the display image if those default and register values are same when this load is done
and when the DRIVER is already Sleep Out mode.
-DRIVER is doing self-diagnostic functions during this 5msec.
-It will be necessary to wait 120msec after sending Sleep In command (when in Sleep Out mode) before Sleep Out
command can be sent
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Sleep in mode
Sleep in mode
Sleep in mode
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APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
-It takes 120msec to become Sleep Out mode (booster on mode) after SLPOUT command issued.
-The results of booster on can be checked by RDDST (09h) command Bit31.
SLPOUT (11h)
Start Internal
Oscillator
Flow Chart
Start
DC-DC
Converter
Charge Offset
voltage for
LCD Panel
Legend
Display whole blank
screen for 2 frames
(Automatic No effect to
DISP ON/OFF
Display Memory
contents in accordance
with the current command
table settings
Command
Parameter
Display
Action
Mode
Sequential
transfer
Sleep Out
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APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
6.2.13. PTLON (12h): Partial Display Mode On
12H
PTLON (12h): Partial Display Mode On
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
PTLON
0
↑
1
-
0
0
0
1
0
0
1
0
(12h)
st
1 Parameter
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
No Parameter
-
-This command turns on Partial mode. The partial mode window is described by the Partial Area command (30h)
Description
-To leave Partial mode, the Normal Display Mode On command (13H) should be written.
-There is no abnormal visual effect during mode change between Normal mode On & lt; - & gt; Partial mode On.
Restriction
This command has no effect when Partial mode is active.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Normal Mode On
Normal Mode On
Normal Mode On
Flow Chart
See Partial Area (30h)
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6.2.14. NORON (13h): Normal Display Mode On
13H
NORON (Normal Display Mode On)
Inst / Para
D/CX WRX
RDX D17-8
D7
NORON
0
1
0
↑
st
1 Parameter
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
D6
D5
0
0
No Parameter
D4
1
D3
0
D2
0
D1
1
D0
1
(Code)
(13h)
-
-This command returns the display to normal mode.
Description
-Normal display mode on means Partial mode off, Scroll mode Off.
-Exit from NORON by the Partial mode On command (12h)
-There is no abnormal visual effect during mode change from Normal mode On to Partial mode On.
Restriction
-This command has no effect when Normal Display mode is active.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Normal Mode On
Normal Mode On
Normal Mode On
Flow Chart
-See Partial Area and Vertical Scrolling Definition Descriptions for details of when to use this command
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6.2.15. INVOFF (20h): Display Inversion Off
20H
INVOFF (Display Inversion Off)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
INVOFF
0
↑
1
-
0
0
1
0
0
0
0
0
(20h)
st
1 Parameter
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
No Parameter
-
-This command is used to recover from display inversion mode.
-This command makes no change of contents of frame memory.
-This command does not change any other status.
Top-Left (0,0)
Description
Restriction
(Example)
Memory
Display
-This command has no effect when module is already inversion off mode.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Display Inversion off
Display Inversion off
Display Inversion off
Legend
Display Inversion On
Mode
Flow Chart
Command
Parameter
Display
INVOFF (20h)
Action
Mode
Display Inversion OFF
Mode
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6.2.16. INVON (21h): Display Inversion On
21H
INVON (Display Inversion On)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
INVON
0
↑
1
-
0
0
1
0
0
0
0
1
(21h)
st
1 Parameter
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
No Parameter
-
-This command is used to enter into display inversion mode
-This command makes no change of contents of frame memory.
-This command does not change any other status.
-To exit from Display Inversion On, the Display Inversion Off command (20h) should be written.
Description
Restriction
Top-Left (0,0)
(Example)
Memory
Display
-This command has no effect when module is already Inversion On mode.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Display Inversion off
Display Inversion off
Display Inversion off
Legend
Display Inversion OFF
Mode
Flow Chart
Command
Parameter
Display
INVON (21h)
Action
Mode
Display Inversion ON
Mode
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6.2.17. GAMSET (26h): Gamma Set
26H
GAMSET (Gamma Set)
Inst / Para
D/CX WRX
RDX D17-8
D7
GAMSET
0
1
0
↑
st
1 Parameter
1
GC7
1
↑
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
D6
0
GC6
D5
1
GC5
D4
0
GC4
D3
0
GC3
D2
1
GC2
D1
1
GC1
D0
0
GC0
(Code)
(26h)
-This command is used to select the desired Gamma curve for the current display. A maximum of 4 curves can be
selected. The curve is selected by setting the appropriate bit in the parameter as described in the Table.
GC [7:0]
Parameter
Curve Selected
GS=1
Description
GS=0
GC0
Gamma Curve 1 (G2.2)
Gamma Curve 1 (G1.0)
02h
GC1
Gamma Curve 2 (G1.8)
Gamma Curve 2 (G2.5)
04h
GC2
Gamma Curve 3 (G2.5)
Gamma Curve 3 (G2.2)
08h
GC3
Note: All other values are undefined.
Restriction
01h
Gamma Curve 4 (G1.0)
Gamma Curve 4 (G1.8)
-Values of GC [7:0] not shown in table above are invalid and will not change the current selected Gamma curve until valid
is received.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
01h
01h
01h
Legend
----------------
Command
GAMSET (26h)
Parameter
Display
st
Flow Chart
1 Parameter: GC[7:0]
Action
Mode
Sequential
transfer
New Gamma
Curve Loaded
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6.2.18. DISPOFF (28h): Display Off
28H
DISPOFF (Display Off)
Inst / Para
D/CX WRX
RDX D17-8
D7
DISPOFF
0
1
0
↑
st
1 Parameter
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
D6
D5
0
1
No Parameter
D4
0
D3
1
D2
0
D1
0
D0
0
(Code)
(28h)
-
-This command is used to enter into DISPLAY OFF mode. In this mode, the output from Frame Memory is disables and
blank page inserted.
-This command makes no change of contents of frame memory.
-This command does not change any other status.
-There will be no abnormal visible effect on the display.
-Exit from this command by Display On (29h)
Top-Left (0,0)
(Example)
Memory
Display
Display OFF
VDDIO
1.6V-3.6V
VDD
Description
2.6V-3.6V
Gate Output
STOP
Source Output
0V
VCOM Output
Blanking display (over 1 frame display) *
0V
0V
Internal counter
STOP
Internal Oscillator
VGH
VGL
AVDD
IC Internal reset
* Note: complete 1 frame display (ex: continue 2-falling edges of VS)
Restriction
Register
Availability
-This command has no effect when module is already in Display Off mode.
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
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Yes
Yes
Yes
Yes
Yes
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SPFD54124B
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Display off
Display off
Display off
Legend
Display On Mode
Command
Parameter
Flow Chart
Display
DISPOFF (28h)
Action
Mode
Display OFF Mode
Sequential
transfer
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6.2.19. DISPON (29h): Display On
29H
DISPON (Display On)
Inst / Para
D/CX WRX
RDX D17-8
D7
DISPON
0
1
0
↑
st
1 Parameter
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
D6
D5
0
1
No Parameter
D4
0
D3
1
D2
0
D1
0
D0
1
(Code)
(29h)
-
-This command is used to recover from DISPLAY OFF mode. Output from the Frame Memory is enabled.
-This command makes no change of contents of frame memory.
-This command does not change any other status.
Top-Left (0,0)
(Example)
Memory
Display
Display ON
1.6V-3.6V
VDDIO
VDD
Description
2.6V-3.6V
Blanking display (over 1 frame display) *
Gate Output
STOP
Source Output
0V
Memory Contents
VCOM Output
0V
Memory Contents
Internal counter
STOP
Start
Internal Oscillator
VGH
VGL
AVDD
IC Internal reset
* Note: complete 1 frame display (ex: continue 2-falling edges of VS)
Restriction
-This command has no effect when module is already in Display On mode.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Display off
Display off
Display off
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Legend
Display OFF Mode
Command
Parameter
Flow Chart
Display
DISPON (29h)
Action
Mode
Display ON Mode
Sequential
transfer
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6.2.20. CASET (2Ah): Column Address Set
CASET (Column Address Set)
2AH
Inst / Para
D/CX WRX
RDX D17-8
D7
CASET
0
1
0
↑
st
1 Parameter
1
1
XS15
↑
nd
2 Parameter
1
1
XS7
↑
rd
3 Parameter
1
1
XE15
↑
th
4 Parameter
1
1
XE7
↑
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
D6
0
XS14
XS6
XE14
XE6
D5
1
XS13
XS5
XE13
XE5
D4
0
XS12
XS4
XE12
XE4
D3
1
XS11
XS3
XE11
XE3
D2
0
XS10
XS2
XE10
XE2
D1
1
XS9
XS1
XE9
XE1
D0
0
XS8
XS0
XE8
XE0
(Code)
(2Ah)
-This command is used to define area of frame memory where MCU can access.
-This command makes no change on the other driver status.
-The value of XS [15:0] and XE [15:0] are referred when RAMWR command comes.
-Each value represents one column line in the Frame Memory.
(Example)
XS[15:0]
XE[15:0]
Description
XS [15:0] always must be equal to or less than XE [15:0]
When XS [15:0] or XE [15:0] is greater than maximum address like below, data of out of range will be ignored.
1. 128X160 memory base (GM = ’00’)
(Parameter range: 0 ≤ XS [15:0] ≤ XE [15:0] ≤ 127 (007Fh)): MV=”0”
(Parameter range: 0 ≤ XS [15:0] ≤ XE [15:0] ≤ 159 (009Fh)): MV=”1”
2. 120x160 memory base (GM = ‘01’)
Restriction
(Parameter range: 0 ≤ XS [15:0] ≤ XE [15:0] ≤ 119 (0077h)): MV=”0”
(Parameter range: 0 ≤ XS [15:0] ≤ XE [15:0] ≤ 159 (009Fh)): MV=”1”
3. 128x128 memory base (GM = ‘10’)
(Parameter range: 0 ≤ XS [15:0] ≤ XE [15:0] ≤ 127 (007Fh)): MV=”0”
(Parameter range: 0 ≤ XS [15:0] ≤ XE [15:0] ≤ 127 (007Fh)): MV=”1”
4. 132x162 memory base (GM = ‘11’)
(Parameter range: 0 ≤ XS [15:0] ≤ XE [15:0] ≤ 131 (0083h)): MV=”0”
(Parameter range: 0 ≤ XS [15:0] ≤ XE [15:0] ≤ 161 (00A1h)): MV=”1”
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
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Yes
Yes
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Yes
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1. 128x160 memory base (GM = ‘00’)
Status
Power On Sequence
S/W Reset
H/W Reset
XS [15:0]
0000h
0000h
0000h
Default Value
XE [15:0] (MV=’0’)
XE [15:0] (MV=’1’)
007Fh (127)
007Fh (127)
009Fh (159)
007Fh (127)
XS [15:0]
0000h
0000h
0000h
Default Value
XE [15:0] (MV=’0’)
XE [15:0] (MV=’1’)
0077h (119)
0077h (119)
009Fh (159)
0077h (119)
XS [15:0]
0000h
0000h
0000h
Default Value
XE [15:0] (MV=’0’)
XE [15:0] (MV=’1’)
007Fh (127)
007Fh (127)
007Fh (127)
007Fh (127)
XS [15:0]
0000h
0000h
0000h
Default Value
XE [15:0] (MV=’0’)
XE [15:0] (MV=’1’)
0083h (131)
0083h (131)
00A1h (161)
0083h (131)
2. 120x160 memory base (GM = ‘01’)
Status
Default
Power On Sequence
S/W Reset
H/W Reset
3. 128x128 memory base (GM = ‘10’)
Status
Power On Sequence
S/W Reset
H/W Reset
4. 132x162 memory base (GM = ‘11’)
Status
Power On Sequence
S/W Reset
H/W Reset
Partial Mode
CASET (2Ah)
rd
st
nd
1 & 2 Parameter:
XS[15:0]
th
RASET (2Bh)
Flow Chart
rd
1st & 2nd Parameter:
YS[15:0]
th
If Needed
RAMWR (2Ch)
Image Data
D1[17:0],D2[17:0]…Dn[17:0]
Legend
Command
Parameter
Display
Action
Mode
Any Command
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6.2.21. RASET (2Bh): Row Address Set
2BH
RASET (Row Address Set)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
RASET (2Bh)
0
↑
1
-
0
0
1
0
1
0
1
1
(2Bh)
st
1
↑
1
-
YS15
YS14
YS13
YS12
YS11
YS10
YS9
YS8
nd
1
↑
1
-
YS7
YS6
YS5
YS4
YS3
YS2
YS1
YS0
rd
1
↑
1
-
YE15
YE14
YE13
YE12
YE11
YE10
YE9
YE8
4 Parameter
1
1
YE7
↑
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
YE6
YE5
YE4
YE3
YE2
YE1
YE0
1 Parameter
2 Parameter
3 Parameter
th
This command is used to define area of frame memory where MCU can access.
This command makes no change on the other driver status.
The value of YS [15:0] and YE [15:0] are referred when RAMWR command comes.
Each value represents one column line in the Frame Memory.
(Example)
Description
YS[15:0]
YE[15:0]
YS [15:0] always must be equal to or less than YE [15:0]
When YS [15:0] or YE [15:0] are greater than maximum row address like below, data of out of range will be ignored.
1. 128X160 memory base (GM = ’00’)
(Parameter range: 0 ≤ YS [15:0] ≤ YE [15:0] ≤ 159 (009Fh)): MV=”0”
(Parameter range: 0 ≤ YS [15:0] ≤ YE [15:0] ≤ 127 (007Fh)): MV=”1”
2. 120x160 memory base (GM = ‘01’)
Restriction
(Parameter range: 0 ≤ YS [15:0] ≤ YE [15:0] ≤ 159 (009Fh)): MV=”0”
(Parameter range: 0 ≤ YS [15:0] ≤ YE [15:0] ≤ 119 (0077h)): MV=”1”
3. 128x128 memory base (GM = ‘10’)
(Parameter range: 0 ≤ YS [15:0] ≤ YE [15:0] ≤ 127 (007Fh)): MV=”0”
(Parameter range: 0 ≤ YS [15:0] ≤ YE [15:0] ≤ 127 (007Fh)): MV=”1”
4. 132x162 memory base (GM = ‘11’)
(Parameter range: 0 ≤ YS [15:0] ≤ YE [15:0] ≤ 161 (00A1h)): MV=”0”
(Parameter range: 0 ≤ YS [15:0] ≤ YE [15:0] ≤ 131 (0083h)): MV=”1”
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
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Yes
Yes
Yes
Yes
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1. 128x160 memory base (GM = ‘00’)
Status
Power On Sequence
S/W Reset
H/W Reset
YS [15:0]
0000h
0000h
0000h
Default Value
YE [15:0] (MV=’0’)
YE [15:0] (MV=’1’)
009Fh (159)
009Fh (159)
007Fh (127)
009Fh (159)
YS [15:0]
0000h
0000h
0000h
Default Value
YE [15:0] (MV=’0’)
YE [15:0] (MV=’1’)
009Fh (159)
007Fh (159)
0077h (119)
009Fh (159)
YS [15:0]
0000h
0000h
0000h
Default Value
YE [15:0] (MV=’0’)
YE [15:0] (MV=’1’)
007Fh (127)
007Fh (127)
007Fh (127)
007Fh (127)
YS [15:0]
0000h
0000h
0000h
Default Value
YE [15:0] (MV=’0’)
YE [15:0] (MV=’1’)
00A1h (161)
00A1h (161)
0083h (131)
00A1h (161)
2. 120x160 memory base (GM = ‘01’)
Status
Default
Power On Sequence
S/W Reset
H/W Reset
3. 128x128 memory base (GM = ‘10’)
Status
Power On Sequence
S/W Reset
H/W Reset
4. 132x162 memory base (GM = ‘11’)
Status
Power On Sequence
S/W Reset
H/W Reset
Partial Mode
rd
If Needed
CASET (2Ah)
1st & 2nd Parameter:
XS[15:0]
th
RASET (2Bh)
Flow Chart
rd
st
nd
1 & 2 Parameter:
YS[15:0]
th
Legend
RAMWR (2Ch)
Command
Parameter
If Needed
Image Data
D1[17:0],D2[17:0]…Dn[17:0]
Display
Action
Mode
Any Command
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6.2.22. RAMWR (2Ch): Memory Write
2CH
RAMWR (Memory Write)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
RAMWR
0
↑
1
-
0
0
1
0
1
1
0
0
(2Ch)
1 Parameter
1
↑
1
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
-
∣
1
↑
1
∣
∣
∣
∣
∣
∣
∣
∣
∣
∣
N Parameter
1
1
D17-8
D7
↑
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
D6
D5
D4
D3
D2
D1
D0
-
st
th
-This command is used to transfer data from MCU to frame memory.
-This command makes no change to the other driver status.
Description
-When this command is accepted, the column register and the row register are reset to the Start Column/Start Row
positions.
-The Start Column/Start Row positions are different in accordance with MADCTR setting.
-Sending any other command can stop Frame Write.
In all color modes, there is no restriction on length of parameters.
-1. 128X160 memory base (GM = ‘00’)
128x160x18-bit memory can be written by this command
Memory range: (0000h,0000h) - & gt; (007Fh, 09Fh)
Restriction
-2. 120x160 memory base (GM = ‘01’)
120x160x18-bit memory can be written on this command.
Memory range: (0000h,0000h) - & gt; (0077h,09Fh)
-3. 128x128 memory base (GM = ‘10’)
128x128x18-bit memory can be written on this command.
Memory range: (0000h,0000h) - & gt; (007Fh,007Fh)
-4. 132x162 memory base (GM = ‘11’)
132x162x18-bit memory can be written on this command.
Memory range: (0000h,0000h) - & gt; (0083h,00A1h)
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Contents of memory is set randomly
Contents of memory is not cleared
Contents of memory is not cleared
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Legend
RAMWR (2Ch)
Command
Parameter
Flow Chart
Image Data
D1[17:0],D2[17:0]…Dn[17:0]
Display
Action
Mode
Any Command
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6.2.23. RGBSET (2Dh): Colour Setting for 4K, 65K and 262K
2DH
RGBSET (Colour Set for 4K, 65K and 262K)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
RGBSET
0
↑
1
-
0
0
1
0
1
1
0
1
(2Dh)
1 Parameter
1
↑
1
-
-
-
R005
R004
R003
R002
R001
R000
-
∣
1
↑
1
-
-
-
Rnn5
Rnn4
Rnn3
Rnn2
Rnn1
Rnn0
-
∣
1
↑
1
-
-
-
R315
R314
R313
R312
R311
R310
-
∣
1
↑
1
-
-
-
G005
G004
G003
G002
G001
G000
-
∣
1
↑
1
-
-
-
Gnn5
Gnn4
Gnn3
Gnn2
Gnn1
Gnn0
-
∣
1
↑
1
-
-
-
G635
G634
G633
G632
G631
G630
-
∣
1
↑
1
-
-
-
B005
B004
B003
B002
B001
B000
-
∣
1
↑
1
-
-
-
Bnn5
Bnn4
Bnn3
Bnn2
Bnn1
Bnn0
-
128 Parameter
1
1
↑
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
-
B315
B314
B313
B312
B311
B310
-
st
nd
This command is used to define the LUT for 12bits-to-16bits / 16-bits-to-18bits color depth conversations.
128-Bytes must be written to the LUT regardless of the color mode..
Description
In this condition, 4K-color (4-4-4) and 65K-color(5-6-5) data input are transferred 6(R)-6(G)-6(B) through RGB LUT table.
This command has no effect on other commands/parameters and Contents of frame memory.
Visible change takes effect next time the Frame Memory is written to.
Restriction
Do not send any command before the last data is sent or LUT is not defined correctly.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Random
Contents of the look-up table protected
Random
---------------
Legend
RGBSET (2Dh)
Command
Parameter
Display
st
1 Parameter:
Flow Chart
∣
Action
th
64 Parameter:
th
65 Parameter:
Mode
∣
th
128 Parameter:
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Sequential
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Preliminary
SPFD54124B
6.2.24. RAMHD (2Eh): Memory Read
2EH
RAMHD (Memory Read)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
RAMHD
0
↑
1
-
0
0
1
0
1
1
1
0
(2Eh)
1 Parameter
st
1
1
↑
-
-
-
-
-
-
-
-
-
-
2 Parameter
nd
1
1
↑
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
-
∣
1
1
↑
∣
∣
∣
∣
∣
∣
∣
∣
∣
∣
(N+1) Parameter
1
1
D17-8
D7
↑
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
D6
D5
D4
D3
D2
D1
D0
-
th
-This command is used to transfer data from frame memory to MCU.
-This command makes no change to the other driver status.
Description
-When this command is accepted, the column register and the row register are reset to the Start Column/Start Row
positions.
-The Start Column/Start Row positions are different in accordance with MADCTR setting.
-Frame Read can be canceled by sending any other command.
Restriction
-In all color modes, the Frame Read is always 18-bits and there is no restriction on length of parameters.
-Memory read is only possible via the SPI and parallel interface.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Contents of memory is set randomly
Contents of memory is not cleared
Contents of memory is not cleared
RAMRD (2Eh)
Legend
Command
Dummy Read
Parameter
Flow Chart
Display
Image Data
D1[17:0],D2[17:0]…Dn[17:0]
Action
Mode
Sequential
transfer
Any Command
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Preliminary
SPFD54124B
6.2.25. PTLAR (30h): Partial Area
30H
PTLAR (Partial Area)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
PTLAR
0
↑
1
-
0
0
1
1
0
0
0
0
(30h)
1 Parameter
st
1
↑
1
-
PSL15
PSL14
PSL13
PSL12
PSL11
PSL10
PSL9
PSL8
nd
1
↑
1
-
PSL7
PSL6
PSL5
PSL4
PSL3
PSL2
PSL1
PSL0
rd
1
↑
1
-
PEL15
PEL14
PEL13
PEL12
PEL11
PEL10
PEL9
PEL8
4 Parameter
1
1
PEL7
↑
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
PEL6
PEL5
PEL4
PEL3
PEL2
PEL1
PEL0
2 Parameter
3 Parameter
th
-This command defines the partial mode’s display area.
-There are 4 parameters associated with this command, the first defines the Start Row (PSL) and the second the End
Row (PEL), as illustrated in the figures below. PSL and PEL refer to the Frame Memory row address counter.
-If End Row & gt; Start Row, when MADCTL ML=’0’
Start Row
PSL [15:0]
Non-displaying Area
Partial Display Area
PEL [15:0]
End Row
Non-displaying Area
-If End Row & gt; Start Row, when MADCTL ML=’1’
End Row
PEL [15:0]
Non-displaying Area
Description
Partial Display Area
PSL [15:0]
Start Row
Non-displaying Area
-If End Row & lt; Start Row, when MADCTL ML=’0’
End Row
Partial Display Area
PEL [15:0]
Non-displaying Area
PSL [15:0]
Partial Display Area
Start Row
-If End Row = Start Row then the Partial Area will be one row deep.
Restriction
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
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Availability
Yes
Yes
Yes
Yes
Yes
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APR. 26, 2007
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Preliminary
SPFD54124B
Status
Default Value
PEL [15:0]
GM=”00” , “01”
GM=”10”
009Fh
007Fh
009Fh
007Fh
009Fh
007Fh
PSL [15:0]
Default
Power On Sequence
S/W Reset
H/W Reset
0000h
0000h
0000h
1. To Enter Partial Mode
2. To Exit Partial Mode
PTLAR (30h)
Partial Mode
st
DISPOFF (28h)
nd
1 & 2 Parameter:
D
rd
NORON (13h)
th
3 & 4 Parameter:
PEL[15:0]
Partial Mode OFF
Flow Chart
PTLON (12h)
Partial Mode
Image Data
D1[17:0],D2[17:0]…
Dn[17:0]
DISON (29h)
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Optional to
prevent tearing
effect image
display
Legend
Command
Parameter
RAMRW (2Ch)
Proprietary & Confidential
GM=”11”
00A1h
00A1h
00A1h
53
Display
Action
Mode
Sequential
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APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
6.2.26. SCRLAR (33h): Scroll Area
33H
SCRLAR (Scroll Area)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
SCRLAR
0
↑
1
-
0
0
1
1
0
0
1
1
(33h)
st
1
↑
1
-
TFA15
TFA14
TFA13
TFA12
TFA11
TFA10
TFA9
TFA8
nd
1
↑
1
-
TFA7
TFA6
TFA5
TFA4
TFA3
TFA2
TFA1
TFA0
rd
1
↑
1
-
VSA15 VSA14 VSA13 VSA12 VSA11 VSA10
VSA9
VSA8
th
1
↑
1
-
VSA7
VSA6
VSA5
VSA4
VSA3
VSA2
VSA1
VSA0
1
1
BFA15
↑
th
6 Parameter
1
1
BFA7
↑
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
BFA14
BFA13
BFA12
BFA11
BFA10
BFA9
BFA8
BFA6
BFA5
BFA4
BFA3
BFA2
BFA1
BFA0
1 Parameter
2 Parameter
3 Parameter
4 Parameter
th
5 Parameter
This command defines the Vertical Scrolling Area of the display.
When MADCTR ML=0
st
nd
－The 1 & 2 parameter TFA [15:0] describes the Top Fixed Area (in No. of lines from Top of the Frame Memory and
Display).
rd
th
－The 3 & 4 parameter VSA [15:0] describes the height of the Vertical Scrolling Area (in No. of lines of the Frame
Memory [not the display] from the Vertical Scrolling Start Address)
－The first line appears immediately after the bottom most line of the Top Fixed Area.
th
th
－The 5 & 6 parameter BFA [15:0] describes the Bottom Fixed Area (in No. of lines from Bottom of the Frame
Memory and Display).
－TFA, VSA and BFA refer to the Frame Memory row address.
Top-Left (0,0)
Top Fixed Area
TFA [15:0]
First line read from
frame memory
Scroll Fixed Area
VSFA [15:0]
Bottom Fixed Area
BFA [15:0]
Description
When MADCTR ML=1
st
nd
th
th
－The 1 & 2 parameter TFA [15:0] describes the Top Fixed Area (in No. of lines from Bottom of the Frame Memory
and Display).
rd
th
－The 3 & 4 parameter VSA [15:0] describes the height of the Vertical Scrolling Area (in No. of lines of the Frame
Memory [not the display] from the Vertical Scrolling Start Address)
－The first line appears immediately after the top most line of the Top Fixed Area.
－The 5 & 6 parameter BFA [15:0] describes the Bottom Fixed Area (in No. of lines from Top of the Frame Memory
and Display).
Top-Left (0,0)
Bottom Fixed Area
BFA [15:0]
Scroll Fixed Area
VSFA [15:0]
First line read from
frame memory
Top Fixed Area
TFA [15:0]
Restriction
-The condition is 0 ≤ (TFA+VSA+BFA) ≤ 162, otherwise Scrolling mode is undefined.
-In Vertical Scroll Mode, MADCTR parameter MV should be set to ‘0’-this only affects the Frame Memory Write.
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Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Register
Availability
Availability
Yes
Yes
Yes
Yes
Yes
Status
Default
Power On Sequence
S/W Reset
H/W Reset
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TFA [15:0]
0000h
0000h
0000h
Default Value
VSA [15:0]
GM=”00”,”01”
GM=”10”
00A0h
0080h
00A0h
0080h
00A0h
0080h
55
BFA [15:0]
GM=”11”
00A2h
00A2h
00A2h
0000h
0000h
0000h
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
1. To Enter Vertical Scroll Mode
Legend
Normal Mode
Command
SCRLAR (33h)
Parameter
Display
st
nd
1 & 2
Parameter: TFA[15:0]
Action
3rd & 4th Parameter VSA[15:0]
Mode
5th & 6th Parameter BFA[15:0]
Sequential
transfer
CASET (2Ah)
1st & 2nd Parameter XS[15:0]
rd
th
3 & 4 Parameter XE[15:0]
RASET (2Ah)
1st & 2nd Parameter YS[15:0]
Flow Chart
Only required
for non-rolling
scrolling
3rd & 4th Parameter YE[15:0]
MADCTR (36h)
Parameter: MY,MX,MV,ML,RGB
RAMRW (2Ch)
Scroll Image
Data
VSCSAD (37h)
1st & 2nd Parameter SS
Scroll Mode
NOTE: The Frame Memory Window size must be defined correctly otherwise undesirable image will be displayed.
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SPFD54124B
Legend
2. Continuous Scroll
Command
Normal Mode
Parameter
Display
CASET (2Ah)
1st
Action
& 2nd Parameter XS[15:0]
Mode
rd
th
3 & 4 Parameter XE[15:0]
RASET (2Bh)
Sequential
transfer
1st & 2nd Parameter YS[15:0]
3rd & 4th Parameter YE[15:0]
RAMRW (2Ch)
Only required
for non-rolling
scrolling
Scroll Image
Data
VSCSAD (37h)
Flow Chart
1st & 2nd Parameter SSA[15:0]
3. To Exit Vertical Scroll Mode
Scroll Mode
DISOFF (28h)
NORON (13h) / PTLON (12h)
OptionTo prevent
Tearing Effect
Image Display
Scroll Mode OFF
RAMRW (2Ch)
Image Data
D1[17:0],D2[17:0]…
Dn[17:0]
DISON (29h)
NOTE: Scroll Mode can be exit by both the Normal Display Mode On (13h) and Partial Mode On (12h) commands.
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Preliminary
SPFD54124B
6.2.27. TEOFF (34h): Tearing Effect Line OFF
TEOFF (Tearing Effect Line OFF)
34H
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
TEOFF
0
↑
1
-
0
0
1
1
0
1
0
0
(34h)
st
1 Parameter
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
No Parameter
-
Description
-This command is used to turn OFF (Active Low) the Tearing Effect output signal from the TE signal line.
Restriction
-This command has no effect when Tearing Effect output is already OFF.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
OFF
OFF
OFF
Default
Legend
Command
TE Line Output ON
Flow Chart
Parameter
Display
TE
Action
Mo
TE Line Output OFF
Sequential
transfer
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Preliminary
SPFD54124B
6.2.28. TEON (35h): Tearing Effect Line ON
35H
TEON (Tearing Effect Line ON)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
TEON
0
↑
1
-
0
0
1
1
0
1
0
1
(35h)
1 Parameter
1
1
0
↑
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
0
0
0
0
0
0
TELOM
st
-This command is used to turn ON the Tearing Effect output signal from the TE signal line.
-This output is not affected by changing MADCTR bit ML.
-The Tearing Effect Line On has one parameter, which describes the mode of the Tearing Effect Output Line.
(“-“=Don’t Care).
－When M=’0’:
The Tearing Effect Output line consists of V-Blanking information only.
tvdl
tvdh
Vertical
time scale
Description
－When M=’1’:
The Tearing Effect Output line consists of both V-Blanking and H-Blinking information.
tvdl
tvdh
Vertical
time scale
Note: During Sleep In Mode with Tearing Effect Line On, Tearing Effect Output pin will be active Low.
Restriction
-This command has no effect when Tearing Effect output is already OFF.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Tearing effect off & TELOM=0
Tearing effect off & TELOM=0
Tearing effect off & TELOM=0
Legend
Command
TE Line Output OFF
Parameter
Flow Chart
Display
TEON (35h)
Action
1st Parameter: (M)
TE Line Output ON
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transfer
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SPFD54124B
6.2.29. MADCTR (36h): Memory Data Access Control
36H
MADCTR (Memory Data Access Control)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
MADCTR
0
↑
1
-
0
0
1
1
0
1
1
0
(36h)
MX
MV
ML
RGB
0
0
0
st
1 Parameter
1
1
MY
↑
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
-This command defines read/ write scanning direction of frame memory.
-This command makes no change on the other driver status.
-Bit Assignment
Bit
NAME
MY
Row Address Order
MX
Column Address Order
MV
Row/Column Exchange
ML
RGB
DESCRIPTION
These 3bits controls MCU to memory write/read
direction.
LCD vertical refresh direction control
‘0’ = LCD vertical refresh Top to Bottom
‘1’ = LCD vertical refresh Bottom to Top
Color selector switch control
‘0’ =RGB color filter panel,
‘1’ =BGR color filter panel)
Vertical Refresh Order
RGB-BGR ORDER
ML: Vertical Refresh Order
Top-Left (0,0)
Memory
Display
Sent First
Sent 2nd
Sent 3rd
ML=’0’
Sent Last
Top-Left (0,0)
Description
Memory
Display
Sent Last
ML=’1’
Sent 3rd
Sent 2nd
Sent First
RGB: RGB-BGR Order
RGB=”0”
Driver IC
RGB
SIG1
RGB=”1”
Driver IC
RGB
SIG2
RGB
SIG132
RGB
SIG1
RGB
SIG2
RGB
SIG132
SIG1
SIG2
SIG132
SIG1
SIG2
SIG132
RGB
RGB
RGB
BGR
BGR
BGR
RGB
RGB
RGB
BGR
BGR
BGR
LCD Panel
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LCD Panel
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Preliminary
SPFD54124B
st
Restriction
D1 and D0 of the 1 parameter are set to “00” internally.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
MY=0,MX=0,MV=0,ML=0,RGB=0
No Change
MY=0,MX=0,MV=0,ML=0,RGB=0
Default
Legend
Command
Parameter
MADCTR (36h)
Display
Flow Chart
st
Action
1 Parameter:
MY, MX, ML, RGB
Mode
Sequential
transfer
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Preliminary
SPFD54124B
6.2.30. VSCSAD (37h): Vertical Scroll Start Address of RAM
37H
VSCSAD (Vertical Scroll Start Address of RAM)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
VSCSAD
0
↑
1
-
0
0
1
1
0
1
1
1
(37h)
1
↑
1
-
SSA9
SSA8
SSA1
SSA0
st
1 Parameter
SSA15 SSA14 SSA13 SSA12 SSA11 SSA10
nd
1
SSA7
2 Parameter
1
↑
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
SSA6
SSA5
SSA4
SSA3
SSA2
-This command is used together with Vertical Scrolling Definition (33h). These two commands describe the scrolling area
and the scrolling mode.
-The Vertical Scrolling Start Address command has one parameter which describes which line in the Frame Memory will
be written as the first line after the last line of the Top Fixed Area on the display as illustrated below:
-This command Start the scrolling.
-Exit from V-scrolling mode by commands Partial mode On (12h) or Normal mode On (13h).
When MADCTR ML= ‘0’
Example:
－When Top Fixed Area=Bottom Fixed Area=00, Vertical Scrolling Area=160 and Vertical Scrolling Pointer SSA= ’3’.
(Example)
Top-Left (0,0)
Scan address
Memory
Display
0
1
2
3
∣
∣
158
159
SSA[15:0]
Scroll start address
Description
G1
G2
G3
G4
|
|
G159
G160
When MADCTR ML = ‘1’
Example:
－When Top Fixed Area= Bottom Fixed Area=00, Vertical Scrolling Area=160 and SSA= ’3’
(Example)
Top-Left (0,0)
Scan address
Memory
Display
159
158
∣
∣
3
2
1
0
SSA[15:0]
Scroll start address
G1
G2
G3
G4
|
|
G159
G160
NOTE: -When new Pointer position and Picture Data are sent, the result on the display will happen at the next Panel
Scan to avoid tearing effect.
-SSA refers to the Frame Memory scan address.
-Since the value of the Vertical Scrolling Start Address is absolute (with reference to the Frame Memory), it must not enter
the fixed area (defined by Vertical Scrolling Definition (33h)-otherwise undesirable image will be displayed on the Panel.
Restriction
SSA[15:0] is based on 1-line unit.
-SSA[15:0] = 0000h, 0001h, 0002h, 0003h, … , 00A1h
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Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
No
No
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
0000h
0000h
0000h
Flow Chart
See Vertical Scrolling Definition (33h) description.
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Preliminary
SPFD54124B
6.2.31. IDMOFF (38h): Idle Mode Off
38H
IDMOFF (Idle Mode Off)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
IDMOFF
0
↑
1
-
0
0
1
1
1
0
0
0
(38h)
st
1 Parameter
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
No Parameter
-
-This command is used to recover from Idle mode on.
-There will be no abnormal visible effect on the display mode change transition.
Description
-In the idle off mode,
1. LCD can display 4096, 65k or 262k colors.
2. Normal frame frequency is applied.
Restriction
-This command has no effect when module is already in idle off mode.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Idle Mode Off
Idle Mode Off
Idle Mode Off
Legend
Command
Idle mode on
Parameter
Display
Flow Chart
IDMOFF (38h)
Action
Mode
Idle mode off
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SPFD54124B
6.2.32. IDMON (39h): Idle Mode On
39H
IDMON (Idle Mode On)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
IDMON
0
↑
1
-
0
0
1
1
1
0
0
1
(39h)
st
1 Parameter
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
No Parameter
-
-This command is used to enter into Idle mode on.
-There will be no abnormal visible effect on the display mode change transition.
-In the idle on mode,
1. Color expression is reduced. The primary and the secondary colors using MSB of each
R,G and B in the Frame Memory, 8 color depth data is displayed.
2. 8-Color mode frame frequency is applied.
3. Exit from IDMON by Idle Mode Off (38h) command
Top-Left (0,0)
(Example)
Memory
Display
Description
Color
Black
Blue
Red
Magenta
Green
Cyan
Yellow
White
Restriction
R5 R4 R3 R2 R1 R0
0xxxxx
0xxxxx
1xxxxx
1xxxxx
0xxxxx
0xxxxx
1xxxxx
1xxxxx
G5 G4 G3 G2 G1 G0
0xxxxx
0xxxxx
0xxxxx
0xxxxx
1xxxxx
1xxxxx
1xxxxx
1xxxxx
B5 B4 B3 B 4 B1 B0
0xxxxx
1xxxxx
0xxxxx
1xxxxx
0xxxxx
1xxxxx
0xxxxx
1xxxxx
This command has no effect when module is already in idle on mode.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Idle Mode Off
Idle Mode Off
Idle Mode Off
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SPFD54124B
Legend
Command
Idle mode on
Parameter
Display
Flow Chart
IDMOFF (38h)
Action
Mode
Idle mode off
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6.2.33. COLMOD (3Ah): Interface Pixel Format
3AH
COLMOD (3Ah): Interface Pixel Format
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
COLMOD
0
↑
1
-
0
0
1
1
1
0
1
0
(3Ah)
VIPF2
VIPF1
VIPF0
D3
IFPF2
IFPF1
IFPF0
st
1 Parameter
1
1
VIPF3
↑
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
Description
This command is used to define the format of RGB picture data, which is to be transferred via the MCU interface and
RGB interface. The formats are shown in the table:
IFPF[2:0]
MCU Interface Color Format
011
3
12-bits/pixel
101
5
16-bits/pixel
110
6
18-bits/pixel
111
7
No used
Others are no define and invalid
VIPF[3:0]
0101
5
0110
6
0111
7
1110
14
RGB Interface Color Format
16-bits/pixel (1-times data transfer)
18-bits/pixel (1-times data transfer)
No used
18-bits/pixel (3-times data transfer)
Others are no define and invalid
Note1: In 12-bits/Pixel, 16-bits/Pixel or 18-bits/Pixel mode, the LUT is applied to transfer data into the Frame Memory.
Note2: When RGB I/F the 12-bit/pixel don’t care
Note 3: When VIPF[3:0]=”1110”,6-bits data width of 3-times transfer is used to transmit 1 pixel data with the 18-bits color
depth information.
Restriction
There is no visible effect until the Frame Memory is written to.
Availability
Yes
Yes
Yes
Yes
Yes
Status
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Default Value
IFPF[2:0]
VIPF[3:0]
0110 (18-bits/pixel)
0110 (18-bits/pixel)
No Change
No Change
0110 (18-bits/pixel)
0110 (18-bits/pixel)
Default
Power On Sequence
S/W Reset
H/W Reset
Example:
Legend
18-bits/Pixel Mode
Command
Parameter
COLMOD (3Ah)
Display
Flow Chart
Action
1st Parameter
Mode
Sequential
transfer
16-bits/Pixel Mode
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SPFD54124B
6.2.34. RDID1 (DAh): Read ID1 Value
DAH
RDID1 (Read ID1 Value)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
RDID1
0
↑
1
-
1
1
0
1
1
0
1
0
(DAh)
1 Parameter
1
1
↑
-
-
-
-
-
-
-
-
-
-
ID16
ID15
ID14
ID13
ID12
ID11
ID10
st
nd
ID17
2 Parameter
1
1
↑
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
-This read byte returns 8-bits LCD module’s manufacturer ID
Description
st
-The 1 parameter is dummy data
nd
-The 2 parameter (ID17 to ID10): LCD module’s manufacturer ID.
nd
NOTE: See command RDDID (04h), 2 parameter.
Restriction
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
38h
38h
38h
Serial I/F Mode
RDID1 (DAh)
Legend
Partial I/F Mode
RDID1 (DAh)
Command
Host
Driver
Flow Chart
nd
Send 2 parameter:
ID1[7:0]
Dummy Read
Parameter
Display
Action
Mode
nd
Send 2 parameter:
ID1[7:0]
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SPFD54124B
6.2.35. RDID2 (DBh): Read ID2 Value
DBH
RDID2 (Read ID2 Value)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
RDID2
0
↑
1
-
1
1
0
1
1
0
1
1
(DBh)
1 Parameter
1
1
↑
-
-
-
-
-
-
-
-
-
-
ID26
ID25
ID24
ID23
ID22
ID21
ID20
st
nd
ID27
2 Parameter
1
1
↑
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
-This read byte returns 8-bits LCD module/driver version ID
st
-The 1 parameter is dummy data
nd
-The 2 parameter (ID26 to ID20): LCD module/driver version ID
Description
-Parameter Range: ID=80h to FFh
ID26 to ID20
Version
80h
81h
82h
83h
rd
NOTE: See command RDDID (04h), 3 parameter.
Changes
Restriction
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
80h
80h
80h
Serial I/F Mode
RDID2 (DBh)
Legend
Partial I/F Mode
RDID2 (DBh)
Command
Host
Driver
Flow Chart
nd
Send 2 parameter:
ID2[7:0]
Dummy Read
Parameter
Display
Action
Mode
nd
Send 2 parameter:
ID2[7:0]
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SPFD54124B
6.2.36. RDID3 (DCh): Read ID3 Value
DCH
RDID3 (Read ID2 Value)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
RDID3
0
↑
1
-
1
1
0
1
1
1
0
0
(DCh)
1 Parameter
1
1
↑
-
-
-
-
-
-
-
-
-
-
ID36
ID35
ID34
ID33
ID32
ID31
ID30
st
nd
ID37
2 Parameter
1
1
↑
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
-This read byte returns 8-bits LCD module/driver ID.
Description
st
-The 1 parameter is dummy data
nd
-The 2 parameter (ID37 to ID30): LCD module/driver ID.
th
NOTE: See command RDDID (04h), 4 parameter.
Restriction
-
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
4Fh
4Fh
4Fh
Serial I/F Mode
RDID3 (DCh)
Flow Chart
Legend
Part
Command
RDID3 (DCh)
Host
Driver
nd
Send 2 parameter:
ID3[7:0]
Dummy Read
Parameter
Display
Action
Mode
nd
Send 2 p
ram
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SPFD54124B
6.3. Panel Command Description
6.3.1.
RGBCTR (B0h): RGB signal control
B0H
RGBCTR (RGB signal control)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
RGBCTR
0
↑
1
-
1
0
1
1
0
0
0
0
(B0h)
1 Parameter
1
0
1
↑
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
0
0
ICM
DP
EP
HSP
VSP
st
-Set the operation status on the RGB interface. The setting becomes effective as soon as the command is received.
-ICM: GRAM Write/Read frequency and data input select on the RGB interface
ICM
Write/ Read frequency and input data select
Write cycle
Read cycle
Data input
0
PCLK
PCLK
D[17:0]
1
SCL
Internal oscillator
SDA
Description
Symbol
Name
DP
PCLK polarity set
EP
Enable polarity set
HSP
Hsync polarity set
VSP
Vsync polarity set
Clock polarity set for RGB Interface
‘1’ = data fetched at the falling edge
‘0’ = data fetched at the rising edge
‘1’ = Low enable for RGB interface
‘0’ = High enable for RGB interface
‘1’ = High level sync clock
‘0’ = Low level sync clock
‘1’ = High level sync clock
‘0’ = Low level sync clock
Restriction
-If this register not using the register need be reserved.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Status
Default
Power On Sequence
S/W Reset
H/W Reset
© ORISE Technology Co., Ltd.
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Default Value
ICM
0d
0d
0d
71
DP/EP/HSP/VSP
0d/0d/0d/0d
0d/0d/0d/0d
0d/0d/0d/0d
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
------------------
Legend
RGBCTR (B0h)
Command
Parameter
Display
Flow Chart
Action
st
1 Parameter:
ICM, DP,
EP, HSP, VSP
Mode
Sequential
transfer
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6.3.2.
FRMCTR1 (B1h): Frame Rate Control (In normal mode/ Full colors)
B1H
FRMCTR1 (Frame Rate Control)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
FRMCTR1
0
↑
1
-
1
0
1
1
0
0
0
1
(B1h)
st
1
↑
1
-
0
0
0
0
FP0[3]
FP0[2]
FP0[1]
FP0[0]
-
nd
1
↑
1
-
0
0
0
0
1
↑
1
-
0
0
0
0
BP0[2]
RTN0
[2]
BP0[1]
RTN0
[1]
BP0[0]
RTN0
[0]
-
rd
BP0[3]
RTN0
[3]
1 Parameter
2 Parameter
3 Parameter
-
NOTE: “-“ Don’t care
-Set the frame frequency of the full colors normal mode in MPU interface.
--The default vaule of BP0, FP0, and RTN0 can fit the frame frequency to be 65Hz ±5%.
FP0[3:0]
0
1
2
3
4
…
D
E
F
BP0[3:0]
0
1
2
3
4
…
D
E
F
Amount of Back Porch
0
1
2
3
4
…
13
14
15
RTN0[3:0]
0
1
2
3
4
…
D
E
F
Description
Amount of Front Porch
0
1
2
3
4
…
13
14
15
No. of clock in one line
16
17
18
19
20
…
29
30
31
Restriction
-If this register not using the register need be reserved.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Status
Default
Power On Sequence
S/W Reset
H/W Reset
© ORISE Technology Co., Ltd.
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Default Value
BP0
14d
14d
14d
FP0
2d
2d
2d
73
RTN0
0d
0d
0d
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
-------------
Legend
FRMCTR1 (B1h)
Command
Parameter
Display
Flow Chart
st
1 Parameter:
nd
2 Parameter:
3rd Parameter:
th
N Parameter:
Action
Mode
Sequential
transfer
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SPFD54124B
6.3.3.
FRMCTR2 (B2h): Frame Rate Control (In Idle mode/ 8-colors)
B2H
FRMCTR2 (Frame Rate Control)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
FRMCTR2
0
↑
1
-
1
0
1
1
0
0
1
0
(B2h)
st
1
↑
1
-
0
0
0
0
FP1[3]
FP1[2]
FP1[1]
FP1[0]
-
nd
1
↑
1
-
0
0
0
0
1
↑
1
-
0
0
0
0
BP1[2]
RTN1
[2]
BP1[1]
RTN1
[1]
BP1[0]
RTN1
[0]
-
rd
BP1[3]
RTN1
[3]
1 Parameter
2 Parameter
3 Paramete
-
NOTE: “-“ Don’t care
-Set the frame frequency of the Idle mode in MPU interface.
-The default vaule of BP1, FP1, and RTN1 can fit the frame frequency to be 70Hz ±5%.
FP1[3:0]
0
1
2
3
4
…
D
E
F
BP1[3:0]
0
1
2
3
4
…
D
E
F
Amount of Back Porch
0
1
2
3
4
…
13
14
15
RTN1[3:0]
0
1
2
3
4
…
D
E
F
Description
Amount of Front Porch
0
1
2
3
4
…
13
14
15
No. of clock in one line
16
17
18
19
20
…
29
30
31
Restriction
-If this register not using the register need be reserved.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Status
Default
Power On Sequence
S/W Reset
H/W Reset
© ORISE Technology Co., Ltd.
Proprietary & Confidential
Default Value
BP1
14d
14d
14d
FP1
2d
2d
2d
75
RTN1
0d
0d
0d
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
-------------
Legend
FRMCTR2 (B2h)
Command
Parameter
Display
Flow Chart
st
1 Parameter:
nd
2 Parameter:
3rd Parameter:
th
N Parameter:
Action
Mode
Sequential
transfer
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SPFD54124B
6.3.4.
FRMCTR3 (B3h): Frame Rate Control (In Partial mode/ full colors)
B3H
FRMCTR3 (Frame Rate Control)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
FRMCTR3
0
↑
1
-
1
0
1
1
0
0
1
1
(B3h)
st
1
↑
1
-
0
0
0
0
FP2[3]
FP2[2]
FP2[1]
FP2[0]
-
nd
1
↑
1
-
0
0
0
0
1
↑
1
-
0
0
0
0
BP2[2]
RTN2
[2]
BP2[1]
RTN2
[1]
BP2[0]
RTN2
[0]
-
rd
BP2[3]
RTN2
[3]
1 Parameter
2 Parameter
3 Parameter
-
NOTE: “-“ Don’t care
-Set the frame frequency of the Partial mode/ full colors in MPU interface.
-The default vaule of BP2, FP2, and RTN2 can fit the frame frequency to be 70Hz ±5% with frame inversion
and
65Hz ±5% with line inversion in this mode
FP2[3:0]
0
1
2
3
4
…
D
E
F
BP2[3:0]
0
1
2
3
4
…
D
E
F
Amount of Back Porch
0
1
2
3
4
…
13
14
15
RTN2[3:0]
0
1
2
3
4
…
D
E
F
Description
Amount of Front Porch
0
1
2
3
4
…
13
14
15
No. of clock in one line
16
17
18
19
20
…
29
30
31
Restriction
-If this register not using the register need be reserved.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Status
Default
Power On Sequence
S/W Reset
H/W Reset
© ORISE Technology Co., Ltd.
Proprietary & Confidential
Default Value
BP2
14d
14d
14d
FP2
2d
2d
2d
77
RTN2
0d
0d
0d
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
-------------
Legend
FRMCTR3 (B3h)
Command
Parameter
Display
Flow Chart
st
1 Parameter:
nd
2 Parameter:
3rd Parameter:
th
N Parameter:
Action
Mode
Sequential
transfer
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Preliminary
SPFD54124B
6.3.5.
INVCTR (B4h): Display Inversion Control
B4H
INVCTR (Display Inversion Control)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
INVCTR
0
↑
1
-
1
0
1
1
0
1
0
0
(B4h)
1 Parameter
1
0
1
↑
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
0
0
0
0
NLA
NLB
NLC
st
-Display Inversion mode control
-NLA: Inversion setting in full colors normal mode (Normal mode on)
NLA
Inversion setting in full colours normal mode
0
Line Inversion
1
Frame Inversion
Description
-NLB: Inversion setting in Idle mode (Idle mode on)
NLB
Inversion setting in Idle mode
0
Line Inversion
1
Frame Inversion
-NLC: Inversion setting in full colors partial mode (Partial mode on / Idle mode off)
NLC
Inversion setting in full colours partial mode
0
Line Inversion
1
Frame Inversion
Restriction
-If this register not using the register need be reserved.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Status
Default
Default Value
NLA
0d
0d
0d
Power On Sequence
S/W Reset
H/W Reset
NLB
1d
1d
1d
NLC
0d
0d
0d
B4h
02h
02h
02h
-------------
Legend
INVCTR (B4h)
Command
Parameter
Display
Flow Chart
Action
st
1 Parameter:
NLA, NLB, NLC
Mode
Sequential
transfer
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Preliminary Version: 0.6
Preliminary
SPFD54124B
6.3.6.
RGBBPCTR (B5h): RGB Interface Blanking Porch setting
B5H
RGBPSET (RGB Interface Blanking Porch setting)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
RGBBPCTR
0
↑
1
-
1
0
1
1
0
1
0
1
(B5h)
1
↑
1
-
st
1 Parameter
NOTE: “-“ Don’t care
VBP[3] VBP[2] VBP[1] VBP[0]
-
-Set the blanking porch in the RGB interface
Description
VBP[3:0]
0
1
2
3
4
…
D
E
F
Amount of Back Porch in RGB interface
0
1
2
3
4
…
13
14
15
Restriction
-If this register not using the register need be reserved.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Status
Default
Default Value
VBP
3d
3d
3d
Power On Sequence
S/W Reset
H/W Reset
----------------
Legend
RGBBPCTR (B5h)
Command
Parameter
Display
Flow Chart
Action
st
1 Parameter:
nd
2 Parameter:
rd
3 Parameter:
th
N Parameter:
Mode
Sequential
transfer
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Preliminary Version: 0.6
Preliminary
SPFD54124B
6.3.7.
DISSET5 (B6h): Display Function set 5
B6H
DISSET (Display Function set 5)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
DISSET5
0
↑
1
-
1
0
1
1
0
1
1
0
(B6h)
1
1
↑
↑
1
1
-
0
0
0
0
NO1
0
NO0
0
SDT1
PTG1
STD0
PTG0
EQ1
PT1
EQ0
PT0
st
1 Parameter
nd
2 Parameter
NOTE: “-“ Don’t care
st
-1 parameter: Set output waveform relation.
-NO[1:0]: Set the amount of non-overlap of the gate output
NO[1:0]
Amount of non-overlap of the gate output
Refer the Internal oscillator
Refer the PCLK
00
0
1 clock cycle
4 clock cycle
01
1
4 clock cycle
16 clock cycle
10
2
6 clock cycle
24 clock cycle
11
3
8 clock cycle
32 clock cycle
-SDT[1:0]: Set delay amount from gate signal falling edge of the source output.
SDT[1:0]
Amount of non-overlap of the source output
Refer the Internal oscillator
Refer the PCLK
00
0
1 clock cycle
4 clock cycle
01
1
2 clock cycle
8 clock cycle
10
2
3 clock cycle
12 clock cycle
11
3
4 clock cycle
16 clock cycle
-EQ[1:0]: Set the Equalizing period
EQ[1:0]
EQ period
Refer the Internal oscillator
00
0
No EQ
01
1
2 clock cycle
10
2
4 clock cycle
11
3
6 clock cycle
Gn
Description
Refer the PCLK
No EQ
4 clock cycle
16 clock cycle
24 clock cycle
Gate Non-overlap period
Gn+1
Sn
VCOM
Delay time for source output EQ period
nd
-2 parameter: Set the output waveform in non-display area.
-PTG[1:0]: Determine gate output in a non-display area in the partial mode
PTG[1:0]
Gate output in a non-display area
00
0
Normal scan
01
1
Fix on VGL
10
2
Fix on VGL
11
3
Fix on VGL
-PT[1:0]: Determine Source /VCOM output in a non-display area in the partial mode
Source output on non-display
VCOM output on non-display
PT[1:0]
area
area
Positive
Negative
Positive
Negative
00
0
V63
V0
VCOML
VCOMH
01
1
V0
V63
VCOML
VCOMH
10
2
AGND
AGND
AGND
AGND
11
3
Hi-z
Hi-z
AGND
AGND
Restriction
-If this register not using the register need be reserved.
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Preliminary Version: 0.6
Preliminary
SPFD54124B
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Status
Default
NO[1:0]
1d
1d
1d
Power On Sequence
S/W Reset
H/W Reset
STD[1:0]
1d
1d
1d
Default Value
EQ[1:0]
2d
2d
2d
PTG[1:0]
0d
0d
0d
PT[1:0]
2d
2d
2d
------------------
Legend
DISSET5 (B6h)
Command
Parameter
Display
Flow Chart
st
1 Parameter:
NO[1:0], STD[1:0], EQ[1:0]
nd
2 Parameter:
PTG[1:0], PT[1:0]
Action
Mode
Sequential
transfer
© ORISE Technology Co., Ltd.
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82
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
6.3.8.
PWCTR1 (C0h): Power Control 1
C0H
PWCTR1 (Power Control 1)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
PWCTR1
0
↑
1
-
1
1
0
0
0
0
0
0
(C0h)
1
↑
1
-
0
0
0
VRH4
VRH3
VRH2
VRH1
VRH0
2 Parameter
1
0
1
↑
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
0
0
0
0
VCI2
VCI1
VCI0
st
1 Parameter
nd
-Set the GVDD and VCI1 voltage
Description
VRH[4:0]
00000
0
00001
1
00010
2
00011
3
00100
4
00101
5
00110
6
00111
7
01000
8
01001
9
01010
10
01011
11
01100
12
01101
13
01110
14
01111
15
10000
16
10001
17
10010
18
10011
19
10100
20
10101
21
10110
22
10111
23
11000
24
11001
25
11010
26
11011
27
11100
28
11101
29
11110
30
11111
31
GVDD
5.00
4.75
4.70
4.65
4.60
4.55
4.50
4.45
4.40
4.35
4.30
4.25
4.20
4.15
4.10
4.05
4.00
3.95
3.90
3.85
3.80
3.75
3.70
3.65
3.60
3.55
3.50
3.45
3.40
3.35
3.25
3.00
VC[2:0]
000
001
010
011
100
101
110
111
000
VCI1
2.75
2.70
2.65
2.60
2.55
2.50
x
x
0
1
2
3
4
5
6
7
8
-If this register not using the register need be reserved.
Restriction
-The deviation value of GVDD between with Measurement and Specification: Max & lt; =50mV
-The deviation value of VCI1 between with Measurement and Specification: Max & lt; =1% deviation
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
© ORISE Technology Co., Ltd.
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Availability
Yes
Yes
Yes
Yes
Yes
83
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
Status
Default Value
LCM = ‘0’
LCM = ‘1’
TR LC Type
TM LC type
VRH[4:0]
VC[2:0]
VRH[4:0]
VC[2:0]
16d
5d
5d
5d
16d
5d
5d
5d
16d
5d
5d
5d
Default
Power On Sequence
S/W Reset
H/W Reset
--------------
Legend
PWCTR1 (C0h)
Command
Parameter
Display
Flow Chart
1st Parameter:
VRH[4:0]
nd
2
© ORISE Technology Co., Ltd.
Proprietary & Confidential
Action
Mode
Parameter:
VCI[2:0]
Sequential
transfer
84
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
6.3.9.
PWCTR2 (C1h): Power Control 2
C1H
PWCTR2 (Power Control 2)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
PWCTR2
0
↑
1
-
1
1
0
0
0
0
0
1
(C1h)
1 Parameter
1
0
1
↑
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
0
0
0
0
BT2
BT1
BT0
st
-Set the AVDD, VCL, VGH and VGL supply power level
BT[2:0]
000
0
001
1
VCL
-1xVDDIO
-2.45
-1xVDDIO
-2.45
VGH
4*VDDIO
9.80
4*VDDIO
9.80
VGL
-3*VDDIO
-7.35
-4*VDDIO
-9.80
010
011
100
2
3
4
2xVDDIO
2xVDDIO
2xVDDIO
4.75
4.75
4.75
-1xVDDIO
-1xVDDIO
-1xVDDIO
-2.45
-2.45
-2.45
5*VDDIO
5*VDDIO
5*VDDIO
12.25
12.25
12.25
-3*VDDIO
-4*VDDIO
-5*VDDIO
-7.35
-9.80
-12.25
101
110
111
Description
AVDD
2xVDDIO
4.75
2xVDDIO
4.75
5
6
7
2xVDDIO
2xVDDIO
2xVDDIO
4.75
4.75
4.75
-1xVDDIO
-1xVDDIO
-1xVDDIO
-2.45
-2.45
-2.45
6*VDDIO
6*VDDIO
6*VDDIO
14.70
14.70
14.70
-3*VDDIO
-4*VDDIO
-5*VDDIO
-7.35
-9.80
-12.25
Note: When VCI1=2.5V, Set-up cycle 1 effective=95%, Set-up cycle 2 effective=98%,
-If this register not using the register need be reserved.
Restriction
-The deviation value of VGH/ VGL between with Measurement and Specification: Max: VGH-VGL & lt; =1V
-VGH-VGL & lt; = 25V
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Status
Default
Default Value
BT[2:0]
7d
7d
7d
Power On Sequence
S/W Reset
H/W Reset
---------------
Legend
PWCTR2 (C1h)
Command
Parameter
Flow Chart
Display
1st Parameter:
BT[2:0]
Action
nd
2 Parameter:
VGH[2:0], VGL[2:0]
Mode
Sequential
transfer
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Preliminary Version: 0.6
Preliminary
SPFD54124B
6.3.10. PWCTR3 (C2h): Power Control 3 (in Normal mode/ Full colors)
C2H
PWCTR3 (Power Control 3)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
PWCTR3
0
↑
1
-
1
1
0
0
0
0
1
0
(C2h)
1
1
↑
↑
1
1
-
0
0
0
0
0
0
0
0
0
0
APA2
DCA2
APA1
DCA1
APA0
DCA0
st
1 Parameter
nd
2 Parameter
NOTE: “-“ Don’t care
-Set the amount of current in Operational amplifier in normal mode/full colors.
-Adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver.
APA[2:0]
000
001
010
011
100
101
110
111
Description
Amount of Current in Operational Amplifier
Operation of the operational amplifier stops
Small
Medium Low
Medium
Medium High
Large
Reserved
Reserved
0
1
2
3
4
5
6
7
-Set the Booster circuit Step-up cycle in Normal mode/ full colors.
DCA[2:0]
000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
Step-up cycle in Booster circuit 1
BCLK / 1
BCLK / 1
BCLK / 1
BCLK / 2
BCLK / 2
BCLK / 4
BCLK / 4
BCLK / 4
Step-up cycle in Booster circuit 2,3
BCLK / 1
BCLK / 2
BCLK / 4
BCLK / 2
BCLK / 4
BCLK / 4
BCLK / 8
BCLK / 16
Note: BCLK is Clock frequency for Booster circuit
Restriction
Register
Availability
-If some parameter of the register not use the register need to be reserved.
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Status
Default
Power On Sequence
S/W Reset
H/W Reset
© ORISE Technology Co., Ltd.
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Default Value
AP[2:0]
4d
4d
4d
86
DC[2:0]
1d
1d
1d
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
---------------
Legend
PWCTR3 (C2h)
Command
Parameter
Display
Flow Chart
st
1 Parameter:
APA[2:0]
Action
Mode
nd
2
© ORISE Technology Co., Ltd.
Proprietary & Confidential
Parameter:
DCA[2:0]
Sequential
transfer
87
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
6.3.11. PWCTR4 (C3h): Power Control 4 (in Idle mode/ 8-colors)
C3H
PWCTR4 (Power Control 4)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
PWCTR4
0
↑
1
-
1
1
0
0
0
0
1
1
(C3h)
1
1
↑
↑
1
1
-
0
0
0
0
0
0
0
0
0
0
APB2
DCB2
APB1
DCB1
APB0
DCB0
st
1 Parameter
nd
2 Parameter
NOTE: “-“ Don’t care
-Set the amount of current in Operational amplifier in Idle mode/ 8-colors.
-Adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver.
APB[2:0]
000
001
010
011
0
1
2
3
100
4
101
110
111
Amount of Current in Operational Amplifier
Operation of the operational amplifier stops
Small
Medium Low
Medium
5
6
7
Medium High
Description
Large
Reserved
Reserved
-Set the Booster circuit Step-up cycle in Idle mode/ 8-colors.
DCB[2:0]
000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
Step-up cycle in Booster circuit 1
BCLK / 1
BCLK / 1
BCLK / 1
BCLK / 2
BCLK / 2
BCLK / 4
BCLK / 4
BCLK / 4
Step-up cycle in Booster circuit 2,3
BCLK / 1
BCLK / 2
BCLK / 4
BCLK / 2
BCLK / 4
BCLK / 4
BCLK / 8
BCLK / 16
Note: BCLK is Clock frequency for Booster circuit
Restriction
Register
Availability
-If some parameters of the register not use the register need to be reserved.
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Status
Default
Power On Sequence
S/W Reset
H/W Reset
© ORISE Technology Co., Ltd.
Proprietary & Confidential
Default Value
AP[2:0]
2d
2d
2d
88
DC[2:0]
4d
4d
4d
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
---------------
Legend
PWCTR4 (C3h)
Command
Parameter
Display
Flow Chart
st
1 Parameter:
APB[2:0]
Action
Mode
nd
2
© ORISE Technology Co., Ltd.
Proprietary & Confidential
Parameter:
DCB[2:0]
Sequential
transfer
89
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
6.3.12. PWCTR5 (C4h): Power Control 5 (in Partial mode/ full-colors)
C4H
PWCTR5 (Power Control 5)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
PWCTR5
0
↑
1
-
1
1
0
0
0
1
0
0
(C4h)
1
1
↑
↑
1
1
-
0
0
0
0
0
0
0
0
0
0
APC2
DCC2
APC1
DCC1
APC0
DCC0
st
1 Parameter
nd
2 Parameter
NOTE: “-“ Don’t care
-Set the amount of current in Operational amplifier in Partial mode/ full-colors.
-Adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver.
APC[2:0]
000
001
010
011
100
101
110
111
Description
Amount of Current in Operational Amplifier
Operation of the operational amplifier stops
Small
Medium Low
Medium
Medium High
Large
Reserved
Reserved
0
1
2
3
4
5
6
7
-Set the Booster circuit Step-up cycle in Partial mode/ full-colors.
DCC[2:0]
000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
Step-up cycle in Booster circuit 1
BCLK / 1
BCLK / 1
BCLK / 1
BCLK / 2
BCLK / 2
BCLK / 4
BCLK / 4
BCLK / 4
Step-up cycle in Booster circuit 2,3
BCLK / 1
BCLK / 2
BCLK / 4
BCLK / 2
BCLK / 4
BCLK / 4
BCLK / 8
BCLK / 16
Note: BCLK is Clock frequency for Booster circuit
Restriction
Register
Availability
-If some parameters of the register not use the register need to be reserved.
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Status
Default
Power On Sequence
S/W Reset
H/W Reset
© ORISE Technology Co., Ltd.
Proprietary & Confidential
Default Value
APC[2:0]
3d
3d
3d
90
DCC[2:0]
2d
2d
2d
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
---------------
Legend
PWCTR5 (C4h)
Command
Parameter
Display
Flow Chart
st
1 Parameter:
APC[2:0]
Action
Mode
nd
2
© ORISE Technology Co., Ltd.
Proprietary & Confidential
Parameter:
DCC[2:0]
Sequential
transfer
91
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
6.3.13. VMCTR1 (C5h): VCOM Control 1
C5H
VMCTR1 (VCOM Control 1)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
VMCTR1
0
↑
1
-
1
1
0
0
0
1
0
1
(C5h)
VMH6
VMH5
st
1 Parameter
1
nVM *
1
↑
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
VMH 4 VMH 3 VMH 2 VMH 1 VMH 0
-Set VCOMH Voltage
Description
VMH[6:0]
0000000
0
0000001
1
0000010
2
0000011
3
0000100
4
0000101
5
0000110
6
0000111
7
0001000
8
0001001
9
0001010
10
0001011
11
0001100
12
0001101
13
0001110
14
0001111
15
0010000
16
0010001
17
0010010
18
0010011
19
0010100
20
0010101
21
0010110
22
0010111
23
0011000
24
0011001
25
0011010
26
VCOMH
2.500
2.525
2.550
2.575
2.600
2.625
2.650
2.675
2.700
2.725
2.750
2.775
2.800
2.825
2.850
2.875
2.900
2.925
2.950
2.975
3.000
3.025
3.050
3.075
3.100
3.125
3.150
VMH[6:0]
0011011
27
0011100
28
0011101
29
0011110
30
0011111
31
0100000
32
0100001
33
0100010
34
0100011
35
0100100
36
0100101
37
0100110
38
0100111
39
0101000
40
0101001
41
0101010
42
0101011
43
0101100
44
0101101
45
0101110
46
0101111
47
0110000
48
0110001
49
0110010
50
0110011
51
0110100
52
0110101
53
VCOMH
3.175
3.200
3.225
3.250
3.275
3.300
3.325
3.350
3.375
3.400
3.425
3.450
3.475
3.500
3.525
3.550
3.575
3.600
3.625
3.650
3.675
3.700
3.725
3.750
3.775
3.800
3.825
VMH[6:0]
0110110
54
0110111
55
0111000
56
0111001
57
0111010
58
0111011
59
0111100
60
0111101
61
0111110
62
0111111
63
1000000
64
1000001
65
1000010
66
1000011
67
1000100
68
1000101
69
1000110
70
1000111
71
1001000
72
1001001
73
1001010
74
1001011
75
1001100
76
1001101
77
1001110
78
1001111
79
1010000
80
VCOMH
3.850
3.875
3.900
3.925
3.950
3.975
4.000
4.025
4.050
4.075
4.100
4.125
4.150
4.175
4.200
4.225
4.250
4.275
4.300
4.325
4.350
4.375
4.400
4.425
4.450
4.475
4.500
VMH[6:0]
VCOMH
1010001 81
4.525
1010010 82
4.550
1010011 83
4.575
1010100 84
4.600
1010101 85
4.625
1010110 86
4.650
1010111
87
4.675
1011000 88
4.700
1011001 89
4.725
1011010 90
4.750
1011011
91
4.775
1011100
92
4.800
1011101
93
4.825
1011110
94
4.850
1011111
95
4.875
1100000 96
4.900
1100001 97
4.925
1100010 98
4.950
1100011
99
4.975
1100100 100
5.000
1100101 101
Not
|
Permitted
1111111 127
-Select the VCOMH value
nVM *
VCOMH value
0
VCOMH value is from NV memory
1
VCOMH value is from the VCOMH[6:0] setting
st
-The nVM need be used in 1 parameter of VMCTR1 (C5h)
- When nVM=0, the value of VMH[6:0] is from NV memory. So it must program the NV memory first.
- When nVM=1, the vaule of VMH[6:0] is from $C5 register. It can fine-tune the display performance to the best quality
by setting this register, and program this optium value to NV memory.
-If this register not using the register need be reserved.
Restriction
-The deviation value of VCOMH between with Measurement and Specification: Max & lt; =25mV
-The deviation value of VCOMAC between with Measurement and Specification: Max & lt; =50mV
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
© ORISE Technology Co., Ltd.
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Availability
Yes
Yes
Yes
Yes
Yes
92
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
Status
nVM
Default
Power On Sequence
S/W Reset
H/W Reset
0d
0d
0d
Default Value
LCM = ‘0’
TR LC Type
VMH[6:0] / VML[6:0]
40d / 68d
40d / 68d
40d / 68d
LCM = ‘1’
TM LC type
VMH[6:0] / VML[6:0]
26d / 24d
26d / 24d
26d / 24d
---------------
Legend
VMCTR1 (C5h)
Command
Parameter
Display
Flow Chart
1st Parameter: VMH[6:0]
nd
2 Parameter: VML[6:0]
Action
Mode
Sequential
transfer
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Preliminary Version: 0.6
Preliminary
SPFD54124B
6.3.14. VMCTR2 (C6h): VCOM Control 2
C6H
VMCTR2 (VCOM Control 2)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
VMCTR2
0
↑
1
-
1
1
0
0
0
1
1 Parameter
1
0
1
↑
NOTE: “-” Don’t care, can be set to VDDIO or DGND level
0
VMA5
VMA4
VMA3
VMA2
st
D5
D4
D3
D2
D1
D0
(Code)
1
0
(C6h)
VMA1
VMA0
-Set VCOMAC Voltage
Description
Restriction
Register
Availability
VMA[5:0]
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VCOMAC
4.000
4.050
4.100
4.150
4.200
4.250
4.300
4.350
4.400
4.450
4.500
4.550
4.600
4.650
4.700
4.750
VMA[5:0]
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
VCOMAC
4.800
4.850
4.900
4.950
5.000
5.050
5.100
5.150
5.200
5.250
5.300
5.350
5.400
5.450
5.500
5.550
VMA[5:0]
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
111111
32
33
34
35
36
37
38
39
40
41
|
63
VCOMAC
5.600
5.650
5.700
5.750
5.800
5.850
5.900
5.950
6.000
Not
Permitted
-If this register not use the register need be reserved.
-The deviation value of VCOMAC between with Measurement and Specification: Max & lt; =50mV
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Status
Default
Power On Sequence
S/W Reset
H/W Reset
© ORISE Technology Co., Ltd.
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Default Value
LCM = ‘0’
TR LC Type
VMA[5:0]
6d
6d
6d
94
LCM = ‘1’
TM LC type
VMA[5:0]
21d
21d
21d
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
---------------
Legend
VMCTR2 (C6h)
Command
Parameter
Display
Flow Chart
Action
st
1 Parameter: VMA[5:0]
Mode
Sequential
transfer
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Preliminary Version: 0.6
Preliminary
SPFD54124B
6.3.15. RDVMH (C8h): Read the VCOMH Value NV memory
C8H
RDVMH (Read the VCOMH Value NV memory)
Inst / Para
D/CX
WRX
RDVMOF
0
0
1
st
1 Parameter
nd
2 Parameter
NOTE: “-“ Don’t care
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
↑
1
-
1
1
0
0
1
0
0
0
(C8h)
1
1
↑
↑
-
nVM
RVMH6 RVMH5 RVMH4 RVMH3 RVMH2 RVMH1 RVMH0
-
-Read the VCOMH value from NV memory
st
-The 1 parameter is dummy data.
Description
-The 2 parameter is RVMH[6:0] value from NV memory or default value.
Restriction
-If this register not use the register need be reserved.
nd
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value-
Legend
Serial I/F Mode
Parallel I/F Mode
Command
RDVMOF (C8h)
RDVMOF (C8h)
Parameter
Flow Chart
Host
Driver
RVMH[6:0]
Dummy Read
Display
Action
Mode
RVMH[6:0]
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Sequential
transfer
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Preliminary Version: 0.6
Preliminary
SPFD54124B
6.3.16. WRID1 (D0h): Write ID1 Value
WRID2 (Write ID2 Value)
D0H
Inst / Para
D/CX
RDX
D17-8
D7
0
WRID1
st
1 Parameter
NOTE: “-“ Don’t care
WRX
D6
D5
D4
D3
D2
↑
1
-
1
1
0
1
0
0
1
↑
1
-
1
ID16
ID15
ID14
ID13
ID12
D1
D0
(Code)
0
0
(D0h)
ID11
ID10
-
-Write 7-bits data of LCD panel maker ID code to save it to NV memory.
Description
st
-The 1 parameter ID1[6:0] is LCD panel maker ID code.
Restriction
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Not Fixed
Not Fixed
Not Fixed
---------------
Legend
WRID1 (D0h)
Command
Parameter
Display
Flow Chart
Action
st
1 Parameter: ID1[6:0]
Mode
Sequential
transfer
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Preliminary Version: 0.6
Preliminary
SPFD54124B
6.3.17. WRID2 (D1h): Write ID2 Value
WRID2 (Write ID2 Value)
D1H
Inst / Para
D/CX
RDX
D17-8
D7
0
WRID2
st
1 Parameter
NOTE: “-“ Don’t care
WRX
D6
D5
D4
D3
D2
↑
1
-
1
1
0
1
0
0
1
↑
1
-
1
ID26
ID25
ID24
ID23
ID22
D1
D0
(Code)
0
1
(D1h)
ID21
ID20
-
-Write 7-bits data of LCD module version to save it to NV memory.
Description
st
-The 1 parameter ID2[6:0] is LCD Module version ID.
Restriction
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Not Fixed
Not Fixed
Not Fixed
---------------
Legend
WRID2 (D1h)
Command
Parameter
Display
Flow Chart
Action
st
1 Parameter: ID2[6:0]
Mode
Sequential
transfer
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Preliminary
SPFD54124B
6.3.18. WRID3 (D2h): Write ID3 Value
WRID3 (Write ID3 Value)
D2H
Inst / Para
D/CX
RDX
D17-8
0
WRID3
st
1 Parameter
NOTE: “-“ Don’t care
WRX
D7
D6
D5
D4
D3
D2
↑
1
-
1
1
0
1
0
0
1
↑
1
-
ID37
ID36
ID35
ID34
ID33
ID32
D1
D0
(Code)
1
0
(D2h)
ID31
ID30
-Write 8-bits data of project code module to save it to NV memory.
st
-The 1 parameter ID3[7:0] is product project ID.
Description
Restriction
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
00h
00h
00h
---------------
Legend
WRID3 (D2h)
Command
Parameter
Display
Flow Chart
Action
st
1 Parameter: ID3[7:0]
Mode
Sequential
transfer
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Preliminary Version: 0.6
Preliminary
SPFD54124B
6.3.19. RDID4 (D3h): Read the ID4 value
RDID4 (Read the ID4 value)
D3H
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
(D3h)
RDID4
0
↑
1
-
1
1
0
1
0
0
1
1
1 Parameter
st
1
1
↑
-
-
-
-
-
-
-
-
-
nd
1
1
↑
-
ID417
ID416
ID415
ID414
ID413
ID412
ID411
ID410
-
rd
1
1
1
1
1
1
↑
↑
↑
-
ID427
ID437
ID447
ID426
ID436
ID446
ID425
ID435
ID445
ID424
ID434
ID444
ID423
ID433
ID443
ID422
ID432
ID442
ID421
ID431
ID441
ID420
ID430
ID440
-
2 Parameter
3 Parameter
th
4 Parameter
th
5 Parameter
NOTE: “-“ Don’t care
-Read the Driver IC information from mask value.
st
-The 1 parameter is dummy data.
nd
Description
-The 2 parameter ID41[7:0] is Driver IC ID code.
-ID41[7:0] is 06H.
rd
-The 3 parameter ID42[7:0] is Driver IC Part number ID. It is 14H.
th
th
-The 4 & 5 parameter ID43[7:0] & ID44[7:0] are Driver IC version ID.
Restriction
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Status
Default
Power On Sequence
S/W Reset
H/W Reset
Default ValueID42[7:0]
ID43[7:0]
14H
00H
14H
00H
14H
00H
ID41[7:0]
06H
06H
06H
Serial I/F Mode
Partial I/F Mode
RDID4 (D3h)
RDID4 (D3h)
Legend
Command
Host
Driver
Dummy Clock
Flow Chart
Dummy Read
Send ID41[7:0]
Send ID41[7:0]
ID44[7:0]
01H
01H
01H
Parameter
Display
Action
Mode
Send ID42[7:0]
Send ID43[7:0]
© ORISE Technology Co., Ltd.
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Send ID42[7:0]
Send ID43[7:0]
100
Sequential
transfer
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
6.3.20. NVFCTR1 (D9h): NV Memory Function Controller 1
NVFCTR1 (NV Memory Function Controller 1)
D9H
Inst / Para
D/CX
WRX
RDX
D17-8
NVFCTR1
0
↑
1
-
st
1 Parameter
1
↑
1
-
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
1
1
0
1
1
0
0
1
(D9h)
WVMH WVMH WVMH WVMH WVMH WVMH WVMH WVMH
7
6
5
4
3
2
1
0
-
NOTE: “-“ Don’t care1
- Write WVMH[6:0] for VCOMH voltage to $D9 when the value is considered as the optimum for display quality.
- The endurence for SPFD54124B NV memory is 4 times for ID1 ,ID2, ID3, and VCOMH.
START
EXTC=VDDI -- & gt;
Accessing Command2 enable
EXTC=VDDI
SLPOUT($11)
RAMWR($2C)
VMCTR1($C5)
= 8'b1xxx_xxxx
Check the display quality
DISPON($29)
Optimum Display??
No
The Optimum value for
VCOMH = 7'bnnn_nnnn
Yes
VMCTR1($C5)
= 8'b0xxx_xxxx
Description
Prepare the data that will be
written into OTP cell
WRID1($D0)
WRID2($D1)
WRID3($D2)
NVFCTR3($DF)
8'b1nnn_nnnn
SLPIN($10)
Apply 7.5V at VGH pad
OTP programming procedure
NVFCTR1 ($D9)
Wait more than 1.5sec
NVFCTR2 ($DE)
Remove external power
from Reserved pad
SLPOUT($11)
Verify the progamming
procedure by read back the data
through $C8
RDVMH($C8)
END
Restriction
The endurence of ID1, ID2, ID3, and WVMH is 4 times.
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Preliminary
SPFD54124B
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Not Fixed
Not Fixed
Not Fixed
---------------
Legend
NVFCTR1 (D9h)
Command
Parameter
Display
Flow Chart
Action
st
1 Parameter:
Mode
Sequential
transfer
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Preliminary
SPFD54124B
6.3.21. NVFCTR2 (DEh): NV Memory Function Controller 2
NVFCTR2 (NV Memory Function Controller 2)
DEH
Inst / Para
D/CX
WRX
RDX
D17-8
NVFCTR2
0
↑
1
st
1
↑
1
1 Parameter
NOTE: “-“ Don’t care
Description
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
-
1
1
0
1
1
1
1
0
(DEh)
-
1
-
- Please refer to $D9 for details.
Restriction
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Not Fixed
Not Fixed
Not Fixed
---------------
Legend
NVFCTR1 (DEh)
Command
Parameter
Display
Flow Chart
Action
st
1 Parameter:
Mode
Sequential
transfer
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Preliminary Version: 0.6
Preliminary
SPFD54124B
6.3.22. NVFCTR3 (DFh): NV Memory Function Controller 3
NVFCTR3 (NV Memory Function Controller 3)
DEH
Inst / Para
D/CX
WRX
RDX
D17-8
NVFCTR3
0
↑
1
st
1
↑
1
1 Parameter
NOTE: “-“ Don’t care
Description
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
-
1
1
0
1
1
1
1
1
(DFh)
-
1
-
- Please refer to $D9 for details.
Restriction
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Not Fixed
Not Fixed
Not Fixed
---------------
Legend
NVFCTR3 (DFh)
Command
Parameter
Display
Flow Chart
Action
st
1 Parameter:
Mode
Sequential
transfer
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Preliminary Version: 0.6
Preliminary
SPFD54124B
6.3.23. GMCTRP1 (E0h): Gamma Correction Characteristics Setting
E0H
GMCTRP1 (Gamma ‘+’polarity Correction Characteristics Setting)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
GMCTRP1
0
↑
1
-
1
1
D4
1
0
0
PVR1
V0[1]
PVR1
V1[1]
PVR1
V2[1]
PVR1
V61[1]
PVR1
V62[1]
PVR1
V63[1]
PVR2
V13[1]
PVR2
V50[1]
PVR3
V4[1]
PVR3
V8[1]
PVR3
V20[1]
PVR3
V27[1]
PVR3
V36[1]
PVR3
V43[1]
PVR3
V55[1]
PVR3
V59[1]
PVR1
V0[0]
PVR1
V1[0]
PVR1
V2[0]
PVR1
V61[0]
PVR1
V62[0]
PVR1
V63[0]
PVR2
V13[0]
PVR2
V50[0]
PVR3
V4[0]
PVR3
V8[0]
PVR3
V20[0]
PVR3
V27[0]
PVR3
V36[0]
PVR3
V43[0]
PVR3
V55[0]
PVR3
V59[0]
-
-
nd
1
↑
1
-
-
-
rd
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
-
-
th
1
↑
1
-
-
-
-
th
1
↑
1
-
-
-
-
th
1
↑
1
-
-
-
-
-
th
1
↑
1
-
-
-
-
-
th
1
↑
1
-
-
-
-
-
th
1
↑
1
-
-
-
-
-
th
1
↑
1
-
-
-
-
-
th
1
↑
1
-
-
-
-
-
th
1
↑
1
-
-
-
-
-
th
1
↑
1
-
-
-
-
-
6 Parameter
7 Parameter
8 Parameter
9 Parameter
10 Parameter
11 Parameter
12 Parameter
13 Parameter
14 Parameter
15 Parameter
16 Parameter
(E0h)
0
PVR1
V0[2]
PVR1
V1[2]
PVR1
V2[2]
PVR1
V61[2]
PVR1
V62[2]
PVR1
V63[2]
PVR2
V13[2]
PVR2
V50[2]
PVR3
V4[2]
PVR3
V8[2]
PVR3
V20[2]
PVR3
V27[2]
PVR3
V36[2]
PVR3
V43[2]
PVR3
V55[2]
PVR3
V59[2]
-
5 Parameter
(Code)
0
1
4 Parameter
D0
PVR1
V0[3]
PVR1
V1[3]
PVR1
V2[3]
PVR1
V61[3]
PVR1
V62[3]
PVR1
V63[3]
PVR2
V13[3]
PVR2
V50[3]
PVR3
V4[3]
PVR3
V8[3]
PVR3
V20[3]
PVR3
V27[3]
PVR3
V36[3]
PVR3
V43[3]
PVR3
V55[3]
PVR3
V59[3]
↑
3 Parameter
D1
0
1
2 Parameter
D2
PVR1
V0[4]
PVR1
V1[4]
PVR1
V2[4]
PVR1
V61[4]
PVR1
V62[4]
PVR1
V63[4]
PVR2
V13[4]
PVR2
V50[4]
st
1 Parameter
D3
PVR1
V1[5]
PVR1
V2[5]
PVR1
V61[5]
PVR1
V62[5]
NOTE: “-“ Don’t care
-The default vaule for gamma register is for MVA LC type, GAMMA curve 2.2.
-The gamma volatge
Gamma2.2_POS
5.000
Gamma2.2_POS
4.000
Description
3.000
2.000
1.000
0.000
0
10
20
30
40
50
60
Restriction
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SPFD54124B
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Default
VR1_V0_[4:0]
VR1_V1_[5:0]
VR1_V2_[5:0]
VR1_V61_[5:0]
VR1_V62_[5:0]
VR1_V63_[4:0]
VR2_V13_[4:0]
VR2_V50_[4:0]
VR3_V4_[3:0]
VR3_V8_[3:0]
VR3_V20_[3:0]
VR3_V27_[3:0]
VR3_V36_[3:0]
VR3_V43_[3:0]
VR3_V55_[3:0]
VR3_V59_[3:0]
Availability
Yes
Yes
Yes
Yes
Yes
Gamma 1.0 POS
0
5
9
63
63
7
14
7
5
6
13
8
4
4
5
11
Gamma 1.8 POS
0
8
12
60
58
7
23
0
5
3
12
15
0
3
4
10
---------------
Gamma 2.2 POS
0
9
14
58
50
7
24
0
6
4
14
15
0
2
6
12
Gamma 2.5 POS
0
0
15
53
28
7
23
5
6
4
14
14
0
2
6
13
Legend
GMCTRP1 (E0h)
Command
Parameter
Flow Chart
Display
st
1 Parameter:
….
th
16 Parameter:
Action
Mode
Sequential
transfer
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Preliminary
SPFD54124B
6.3.24. GMCTRP1 (E1h): Gamma Correction Characteristics Setting
E1H
GMCTRN1 (Gamma ‘-’polarity Correction Characteristics Setting)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
GMCTRN1
0
↑
1
-
1
1
D4
1
0
1
NVR1
V0[1]
NVR1
V1[1]
NVR1
V2[1]
NVR1
V61[1]
NVR1
V62[1]
NVR1
V63[1]
NVR2
V13[1]
NVR2
V50[1]
NVR3
V4[1]
NVR3
V8[1]
NVR3
V20[1]
NVR3
V27[1]
NVR3
V36[1]
NVR3
V43[1]
NVR3
V55[1]
NVR3
V59[1]
NVR1
V0[0]
NVR1
V1[0]
NVR1
V2[0]
NVR1
V61[0]
NVR1
V62[0]
NVR1
V63[0]
NVR2
V13[0]
NVR2
V50[0]
NVR3
V4[0]
NVR3
V8[0]
NVR3
V20[0]
NVR3
V27[0]
NVR3
V36[0]
NVR3
V43[0]
NVR3
V55[0]
NVR3
V59[0]
-
-
nd
1
↑
1
-
-
-
rd
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
-
-
th
1
↑
1
-
-
-
-
th
1
↑
1
-
-
-
-
th
1
↑
1
-
-
-
-
-
th
1
↑
1
-
-
-
-
-
th
1
↑
1
-
-
-
-
-
th
1
↑
1
-
-
-
-
-
th
1
↑
1
-
-
-
-
-
th
1
↑
1
-
-
-
-
-
th
1
↑
1
-
-
-
-
-
th
1
↑
1
-
-
-
-
-
6 Parameter
7 Parameter
8 Parameter
9 Parameter
10 Parameter
11 Parameter
12 Parameter
13 Parameter
14 Parameter
15 Parameter
16 Parameter
(E1h)
0
NVR1
V0[2]
NVR1
V1[2]
NVR1
V2[2]
NVR1
V61[2]
NVR1
V62[2]
NVR1
V63[2]
NVR2
V13[2]
NVR2
V50[2]
NVR3
V4[2]
NVR3
V8[2]
NVR3
V20[2]
NVR3
V27[2]
NVR3
V36[2]
NVR3
V43[2]
NVR3
V55[2]
NVR3
V59[2]
-
5 Parameter
(Code)
0
1
4 Parameter
D0
NVR1
V0[3]
NVR1
V1[3]
NVR1
V2[3]
NVR1
V61[3]
NVR1
V62[3]
NVR1
V63[3]
NVR2
V13[3]
NVR2
V50[3]
NVR3
V4[3]
NVR3
V8[3]
NVR3
V20[3]
NVR3
V27[3]
NVR3
V36[3]
NVR3
V43[3]
NVR3
V55[3]
NVR3
V59[3]
↑
3 Parameter
D1
0
1
2 Parameter
D2
NVR1
V0[4]
NVR1
V1[4]
NVR1
V2[4]
NVR1
V61[4]
NVR1
V62[4]
NVR1
V63[4]
NVR2
V13[4]
NVR2
V50[4]
st
1 Parameter
D3
NVR1
V1[5]
NVR1
V2[5]
NVR1
V61[5]
NVR1
V62[5]
NOTE: “-“ Don’t care
-The default vaule for gamma register is for MVA LC type, GAMMA curve 2.2.
-The gamma volatge
Gamma2.2_NEG
5.000
Gamma2.2_NEG
4.000
Description
3.000
2.000
1.000
0.000
0
10
20
30
40
50
60
Restriction
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SPFD54124B
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Default
VR1_V0_[4:0]
VR1_V1_[5:0]
VR1_V2_[5:0]
VR1_V61_[5:0]
VR1_V62_[5:0]
VR1_V63_[4:0]
VR2_V13_[4:0]
VR2_V50_[4:0]
VR3_V4_[3:0]
VR3_V8_[3:0]
VR3_V20_[3:0]
VR3_V27_[3:0]
VR3_V36_[3:0]
VR3_V43_[3:0]
VR3_V55_[3:0]
VR3_V59_[3:0]
Availability
Yes
Yes
Yes
Yes
Yes
Gamma 1.0 NEG
0
56
58
18
14
5
5
18
2
1
5
2
10
10
1
2
Gamma 1.8 NEG
3
49
51
21
16
4
1
22
6
5
6
3
13
12
4
5
---------------
Gamma 2.2 NEG
3
42
49
22
17
4
1
24
6
6
3
0
14
14
4
6
Gamma 2.5 NEG
3
19
44
23
18
4
5
23
14
7
2
0
13
14
5
7
Legend
GMCTRP1 (E1h)
Command
Parameter
Flow Chart
Display
st
1 Parameter:
….
th
16 Parameter:
Action
Mode
Sequential
transfer
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SPFD54124B
7. FUNCTION DESCRIPTIONS
7.1. MCU & RGB Interface
The SPFD54124B features System interfaces and RGB interface to satisfy various needs of small or medium size’s LCD panel. Based on
the application requirements, there are two display modes mostly used in the LCD end product.
1. Still picture display mode
2.
Moving picture display mode.
System interface is suitable for still picture display while RGB interface are suitable for moving picture display. Table 7.1 summarizes
different interfaces for various display requirements.
Table 7.1 MCU & RGB Interface Comparisons table
Function
Mode selection 1
Mode selection 2
Motion /Still selection
RCM1, RCM0
" 0x "
8080/ 6800 IF + SPI I/F
MCU Mode
IMx=
IMx= " 00 "
8080/ 6800 IF
SPI I/F
Motion or Still
Still picture
picture
Input data
D[17:0]
D0 = SDA
RCM1, RCM0
" 10 "
" 11 "
RGB I/F + SPI I/F
RGB Mode 1
ICM='0'
ICM='1'
RGB-1 I/F + SPI I/F
Motion or Still
Still picture
picture
SDA H/W pin
D[17:0]
enable
PCLK
D/CX = SCL
CSX
D/CX = SCL
WRX (R/WX),
CSX
VS, HS, DE
CSX
RDX (E)
Refer the
GRAM Write cycle
Refer SCL
Refer PCLK
Refer SCL
WRX cycle
Refer
Refer
Refer
GRAM Read Cycle
Refer PCLK
Internal Oscillator Internal Oscillator
Internal Oscillator
Command setting
D[7:0]
SDA (D0)
SDA
SDA
SMX, SMY, SRGB -When Power On or H/W reset, those function follow H/W pins setting first.
TE
-By command setting
-By command setting
Function
Normal /
-By command setting
-By command setting
Partial mode
Idle Mode
(IDM H/W pin)
RGB Mode 2
ICM='0'
ICM='1'
RGB-2 I/F + SPI I/F
Motion or Still
Still picture
picture
SDA H/W pin
D[17:0]
enable
PCLK
D/CX = SCL
Input signal
Display On/ Off
(SHUT H/W pin)
-By command setting
-Don’t care in this mode, but should be set to VDDIO or DGND
Data inverter setting
(REV H/W pin)
DE H/W pin
RL H/W pin
TB H/W pin
Blanking porch
Colors format
-The data latched by rising edge of
PCLK when DE=’1’
-Don’t care in this mode, but should be -When display data coming the DE
signal should be VDDIO level
set to VDDIO or DGND
-Don’t care in this mode, but should
be set to VDDIO or DGND
VS, HS, DE
CSX
Refer PCLK
Refer SCL
Refer PCLK
SDA
Refer
Internal Oscillator
SDA
-By Command setting
-By Command setting
-By IDM H/W pin
-IDM On/OFF (39h/28h) are disable
-By SHUT H/W pin
-SLPIN(10h), SLPOUT(11h), Display
On/OFF (29h/28h) are disable
-By REV H/W pin
-INVON/OFF (21h/20h) are disable
-When DE='0' area, the data of
GRAM will keep the same status.
-By H/W pin
-No commands conflict
-Don’t care in this mode
-Control by DE signal
-Control by RGBBPCTR (B5h)
-Control by IFPF[2:0] of COLMOD(3A) -Control by VIPF[3:0] of COLMOD(3A)
Note 1: RCM1 and RCM0 are H/W setting pins.
Note 2: In RGB + SPI I/F (RCM= " 1x " ), VS, HS, DE, PCLK and D[17:0] are Hi-Z by Driver and can be stop for Host, when ICM='1'.
Note 3: In RGB + SPI I/F (RCM= " 1x " ), the data deliver via GRAM
Note 4: When Power on Driver IC should be detect SMX, SMY, SRGB H/W setting
Note 5: When Power on Driver IC should be detect RCM1, RCM0 H/W setting and get into the I/F mode.
Note 6: When Power on Driver IC should be detect LCM1, LCM0 H/W setting and get into the setting mode.
Note 7: When Power on Driver IC should be detect GM1, GM0 H/W setting and get into the setting mode.
7.2. MPU Interface
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SPFD54124B
7.2.1.
Interface Type Selection
The MPU interfaces of SPFD54124B support 8-bit, 9-bit, 16-bit, and 18-bit’s 80- or 68-system Interface and Serial Peripheral Interface (SPI),
which can be set by the P68 and IM2/1/0 pins. The MPU interface can set instructions and access RAM. Table 7.2.1 depicts the interface
corresponding to P68and IM2/1/0 settings.
Table 7.2.1
SPI4 P68 IM2 IM1 IM0
Interface
0
0
0
- 3-Pin Serial interface
0
1
0
0 8080 MCU 8-bits Parallel
0
1
0
1 8080 MCU 16-bits Parallel
0
1
1
0 8080 MCU 9-bits Parallel
0
1
1
1 8080 MCU 18-bits Parallel
0
1
0
- 3-Pin Serial interface
1
1
0
0 6800 MCU 8-bits Parallel
1
1
0
1 6800 MCU 16-bits Parallel
1
1
1
0 6800 MCU 9-bits Parallel
1
1
1
1 6800 MCU 18-bits Parallel
1
0
- 4-Pin Serial interface
7.2.2.
Read back selection
Via the read instruction (8-bits, 24-bits and 32-bits read parameter
RDX strobe (8-bits read data and 8-bits read parameter)
RDX strobe (16-bits read data and 8-bits read parameter)
RDX strobe (9-bits read data and 8-bits read parameter)
RDX strobe (18-bits read data and 8-bits read parameter)
Via the read instruction (8-bits, 24-bits and 32-bits read parameter
E strobe (8-bits read data and 8-bits read parameter)
E strobe (16-bits read data and 8-bits read parameter)
E strobe (9-bits read data and 8-bits read parameter)
E strobe (18-bits read data and 8-bits read parameter)
Via the read instruction (8-bits, 24-bits and 32-bits read parameter
8080-Series Parallel interface(P68=’0’)
The MCU uses a 11-wires 8-data parallel interface or 19-wires 16-data parallel interface or 12-wires 9-data parallel interface or 21-wires
18-data parallel interface. The chip-select CSX(active low) enables and disables the parallel interface. RESX (active low) is an external
reset signal. WRX is the parallel data write, RDX is the parallel data read and D[17:0] is parallel data.
The Graphics Controller Chip reads the data at the rising edge of WRX signal. The D/CX is the data/command flag. When D/CX=’1’, D[17:0]
bits are display RAM data or command parameters. When D/C=’0’, D[17:0] bits are commands.
The 8080-series bi-directional interface can be used for communication between the micro controller and LCD driver chip. The selection of
this interface is done when P68 pin is low state (DGND). Interface bus width can be selected with IM2, IM1 and IM0.
The interface function of 8080-series parallel interface are given in Table 7 2.2
Table 7.2.2 The function of 8080-series parallel interface
P68 IM2
0
0
0
0
1
1
1
1
IM1
IM0
Interface
0
0
8-bits
Parallel
1
16-bits
Parallel
0
9-bits
Parallel
1
18-bits
Parallel
0
1
1
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D/CX
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
RDX
1
1
↑
↑
1
1
↑
↑
1
1
↑
↑
1
1
↑
↑
WRX
↑
↑
1
1
↑
↑
1
1
↑
↑
1
1
↑
↑
1
1
Function
Write 8-bits command (D7 to D0)
Write 8-bits display data or 8-bits parameter (D7 to D0)
Read 8-bits command (D7 to D0)
Read 8-bits parameter or status (D7 to D0)
Write 8-bits command (D7 to D0)
Write 16-bits display data (D15 to D0) or 8-bits parameter (D7 to D0)
Read 8-bits command (D7 to D0)
Read 8-bits parameter or status (D7 to D0)
Write 8-bits command (D7 to D0)
Write 9-bits display data (D8 to D0) or 8-bits parameter (D7 to D0)
Read 8-bits command (D7 to D0)
Read 8-bits parameter or status (D7 to D0)
Write 8-bits command (D7 to D0)
Write 18-bits display data (D17 to D0) or 8-bits parameter (D7 to D0)
Read 8-bits command (D7 to D0)
Read 8-bits parameter or status (D7 to D0)
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7.2.2.1 Write cycle sequence
The write cycle means that the host writes information (command or/and data) to the display via the interface. Each write cycle (WRX
high-low-high sequence) consists of 3 control (D/CX, RDX, WRX) and data signals (D[17:0]). D/CX bit is a control signal, which tells if the
data is a command or a data. The data signals are the command if the control signal is low (=’0’) and vice versa it is data (=’1’).
WRX
D[17:0]
The host starts to
control D[17:0] lines
when there is a falling
edge of the WRX
The display writes
D[17:0] lines when
there is a falling edge
of the WRX
The host stops to
control D[17:0] lines
Fig. 7.2.2.1.1 8080-Series WRX Protocol
Note: WRX is an unsynchronized signal (It can be stopped)
1-byte command
D[17:0]
RESX
S
CMD
2-byte command
N-byte command (PA=N-1)
CMD
PA1
CMD
PA1
PAN-2
PAN-1
P
‘1’
CSX
D/CX
‘1’
RDX
WRX
D[17:0]
S
CMD
CMD
PA1
CMD
PA1
PAN-2
PAN-1
P
Host [17:0]
Host to LCD
S
CMD
CMD
PA1
CMD
PA1
PAN-2
PAN-1
P
Driver [17:0]
LCD to Host]
Hi-Z
CMD: Write command code
PA: Parameter or RAM data
Signal on D[17:0], DCX. R/WX, E pins
during CSX=’1’ are ignored
Fig. 7.2.2.1.2 8080-Series parallel bus protocol, Write to register or display RAM
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7.2.2.2 Read Cycle Sequence
The read cycle (RDX high-low-high sequence) means that the host reads information from display via interface. The display sends data
(D[17:0]) to the host when there is a falling edge of RDX and the host reads data when there is a rising edge of RDX.
RDX
D[17:0]
The display starts to
control D[17:0] lines
when there is a falling
edge of the RDX
The host reads
D[17:0] lines when
there is a rising edge
of RDX
The display stops to
control D[17:0]
Fig. 7.2.2.2.1 8080-Series RDX Protocol
Note: RDX is an unsynchronized signal (It can be stopped)
Read Parameter
D[17:0]
Read display RAM data
S
CMD
DM
PA
CMD
DM
data
data
P
D[17:0]
S
CMD
DM
PA
CMD
DM
data
data
P
Host [17:0]
Host to LCD
S
CMD
Driver [17:0]
LCD to Host]
S
RESX
‘1’
CSX
D/CX
RDX
WRX
Hi-Z
Hi-Z
DM
CMD
PA
Hi-Z
CMD: Write command code
PA: Parameter or RAM data
DM: Dummy
Hi-Z
DM
P
data
data
P
Signal on D[17:0], DCX. R/WX, E pins
during CSX=’1’ are ignored
Fig. 7.2.2.2.2 8080-Series parallel bus protocol, Read data from register or display RAM
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7.2.3.
6800-Series Parallel Interface (P68=’1’)
The MCU uses a 11-wires 8-data parallel interface or 19-wires 16-data parallel interface or 12-wires 9-data parallel interface or 21-wires
18-data parallel interface. The chip-select CSX(active low) enables and disables the parallel interface. RESX (active low) is an external
reset signal. The R/WX is the Read/Write flag and D[17:0] is parallel data.
The Graphics Controller Chip reads the data at the falling edge of E signal when R/WX=’1’ and Writes the data at the falling of the E signal
when R/WX=’0’. The D/CX is the data/command flag. When D/CX=’1’, D[17:0] bits are display RAM data or command parameters. When
D/C=’0’, D[17:0] bits are commands.
The 6800-series bi-directional interface can be used for communication between the micro controller and LCD driver chip. The selection of
this interface is done when P68 pin is high state (VDDIO). Interface bus width can be selected with IM2, IM1 and IM0.
The interface functions of 6800-series parallel interface are given in Table 7.2.3.
Table 7.2.3 The function of 6800-series parallel interface
P68 IM2 IM1 IM0
Interface
1
1
0
0
8-bits
Parallel
1
1
0
1
16-bits
Parallel
1
1
1
0
9-bits
Parallel
1
1
1
1
18-bits
Parallel
D/CX
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
R/WX
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
E
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
Function
Write 8-bits command (D7 to D0)
Write 8-bits display data or 8-bits parameter (D7 to D0)
Read 8-bits command (D7 to D0)
Read 8-bits parameter or status (D7 to D0)
Write 8-bits command (D7 to D0)
Write 16-bits display data (D15 to D0) or 8-bits parameter (D7 to D0)
Read 8-bits command (D7 to D0)
Read 8-bits parameter or status (D7 to D0)
Write 8-bits command (D7 to D0)
Write 9-bits display data (D8 to D0) or 8-bits parameter (D7 to D0)
Read 8-bits command (D7 to D0)
Read 8-bits parameter or status (D7 to D0)
Write 8-bits command (D7 to D0)
Write 18-bits display data (D17 to D0) or 8-bits parameter (D7 to D0)
Read 8-bits command (D7 to D0)
Read 8-bits parameter or status (D7 to D0)
7.2.3.1 Write cycle sequence
The write cycle means that the host writes information (command or/and data) to the display via the interface. Each write cycle (E
low-high-low sequence) consists of 3 control (D/CX, E, R/WX) and data signals (D[17:0]). D/CX bit is a control signal, which tells if the data
is a command or a data. The data signals are the command if the control signal is low (=’0’) and vice versa it is data (=’1’).
R/WX
‘0’
E
D[17:0]
The host starts to
control D[17:0] lines
when there is a rising
edge of the E
The display writes
D[17:0] lines when
there is a falling edge
of the E
The host stops to
control D[17:0] lines
Fig. 7.2.3.1.1 6800-Series Write Protocol
Note: E is an unsynchronized signal (It can be stopped)
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1-byte command
D[17:0]
S
2-byte command
N-byte command (PA=N-1)
CMD
CMD
PA1
CMD
PA1
PAN-2
PAN-1
P
‘1’
RESX
CSX
D/CX
R/WX
‘0’
E
D[17:0]
S
CMD
CMD
PA1
CMD
PA1
PAN-2
PAN-1
P
Host [17:0]
Host to LCD
S
CMD
CMD
PA1
CMD
PA1
PAN-2
PAN-1
P
Driver [17:0]
LCD to Host]
Hi-Z
CMD: Write command code
PA: Parameter or RAM data
Signal on D[17:0], DCX. R/WX, E pins
during CSX=’1’ are ignored
Fig. 7.2.3.1.2 6800-Series parallel bus protocol, Write to register or display RAM
7.2.3.2 Read cycle sequence
The read cycle means that the host reads information (command or/and data) to the display via the interface. Each read cycle (E
low-high-low sequence) consists of 3 control (D/CX, E, R/WX) and data signals (D[17:0]). D/CX bit is a control signal, which tells if the data
is a command or a data. The data signals are the command if the control signal is low (=’0’) and vice versa it is data (=’1’).
R/WX
‘1’
E
D[17:0]
The display starts to
control D[17:0] lines
when there is a rising
edge of the E
The host reads
D[17:0] lines when
there is a falling edge
of the E
The display stops to
control D[17:0] lines
Fig. 7.2.3.2.1 6800-Series Read Protocol
Note: E is an unsynchronized signal (It can be stopped)
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Read Parameter
D[17:0]
RESX
S
CMD
DM
Read display RAM data
PA
CMD
DM
data
data
P
PA
CMD
DM
data
data
P
‘1’
CSX
D/CX
R/WX
‘1’
‘0’
E
D[17:0]
S
CMD
Host [17:0]
Host to LCD
S
CMD
Driver [17:0]
LCD to Host]
S
Hi-Z
DM
Hi-Z
DM
Hi-Z
CMD
PA
Hi-Z
DM
CMD: Write command code
PA: Parameter or RAM data
DM: Dummy
P
data
data
P
Signal on D[17:0], DCX. R/WX, E pins
during CSX=’1’ are ignored
Fig. 7.2.3.2.2 6800-Series parallel bus protocol, Read data from register or display RAM
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7.2.4.
Serial Peripheral interface
7.2.4.1 3-pin 9-bits SPI
The selection of this interface is done by IM2 and SPI4. See the Table 7.2.4.1.
The serial interface is a 3-pin 9-bits bi-directional interface for communication between the micro controller and the LCD driver chip. The
3-pin serial use: CSX (chip enable), SCL (serial clock) and SDA (serial data input/output). Serial clock (SCL) is used for interface with MCU
only, so it can be stopped when no communication is necessary.
Table 7.2.4.1 Serial Interface Type Selection
SPI4 P68
0
‘-‘
IM2
0
IM1
‘-‘
IM0
Interface
‘-‘ 3-Pin Serial interface
Read back selection
Via the read instruction (8-bits, 24-bits and 32-bits read parameter
7.2.4.1.1 Command Write Mode
The write mode of the interface means the micro controller writes commands and data to the 3-Pin serial data packet contains a control bit
D/CX and a transmission byte. If D/CX is low, the transmission byte is interpreted as command byte. If D/CX is high, the transmission byte
is stored in the display data RAM (Memory write command), or command register as parameter.
Any instruction can be sent in any order to the DRIVER. The MSB is transmitted first. The serial interface is initialized when CSX is high. In
this state, SCL clock pulse or SDA data have no effect. A falling edge on CSX enables the serial interface and indicates the start of data
transmission.
3-pin Serial Data Stream Format
Transmission byte(TB) may be a command or a data
MSB
LSB
D/CX D7 D6 D5 D4 D3 D2 D1 D0
D/CX
D/CX
D/CX
(TB)
(TB)
(TB)
Fig. 7.2.4.1.1 Serial interface data Stream format
When CSX is high, SCL clock is ignored. During the high time of CSX the serial interface is initialized. At the falling edge of CSX, SCL can
be high or low. SDA is sampled at the rising edge of CSX. D/CX indicates, whether the byte is command code (D/CX=’0’) or parameter/RAM
data (D/CX=’1’). It is sampled when first rising edge of CSX. If CSX stay low after the last bit of command/data byte, the serial interface
expects the D/CX bit of the next byte at the next rising edge of SCL.
S
TB
TB
P
CSX
Host
(MCU to
Driver)
SDA
0
D7
D6
D5
D4
D3
D2
D1
D/C
D0
D7
D6
D5
D4
D3
D2
D1
D0
SCL
Command
Command / Parameter
CSX can be ‘H’ between parameter / command and
parameter/command SCL and SDA during CSX=’H’ is invalid
Fig. 7.2.4.1.2 Serial interface Write protocol (Write to register with control bit in transmission)
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7.2.4.1.2 Read Functions
The read mode of the interface means that the micro controller reads register value from the Driver. To do the micro controller first has to
send a command (Read ID or register command) and then the following byte is transmitted in the opposite direction. After the read status
command has been sent, the SDA lin must be set to tri-state no later than at the falling edge of SCL of the last bit.
3-Pin Serial Protocol (for RDID1/RDID2/RDID3/0Ah/0Bh/0Ch/0Dh/0Eh/0Fh command: 8-bit read)
S
TB
TB
P
S
Host
CSX
SCL
Driver
SDA
(SDI)
D/CX
D7
D6
SDA
(SDO)
D5
D4
D3
D2
D1
High-Z
D0
High-Z
D7
D6
D5
D4
D3
D/CX
D2
D1 D0
3-Pin Serial Protocol (for RDDID command: 24-bit read)
TB
S
TB
P
S
Host
CSX
SCL
Driver
SDA
(SDI)
D/CX D7
D6
D5
D4
D3
D2
D1
High-Z
SDA
(SDO)
High-Z
D0
D23
D22 D21
D/CX
D20 D19
D3
D2
D1 D0
Dummy Clock Cycle
3-Pin Serial Protocol (for RDDST command: 32-bit read)
TB
S
TB
P
S
Host
CSX
SCL
Driver
SDA
(SDI)
D/CX
D7
SDA
(SDO)
D6
D5
D4
High-Z
D3
D2
D1
High-Z
D0
D31 D30 D29
D28 D27
D/CX
D3
D2
D1 D0
Dummy Clock Cycle
Fig. 7.2.4.1.2 3-pin Serial interface Read protocol
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7.2.4.2 4-pin 8-bits SPI
The selection of this interface is done by IM2 and SPI4. See the Table 7.2.4.2.
The serial interface is a 4-pin 8-bits bi-directional interface for communication between the micro controller and the LCD driver chip. The
4-pin serial use: CSX (chip enable), SCL (serial clock), DCX(command or data) and SDA (serial data input/output). Serial clock (SCL) is
used for interface with MCU only, so it can be stopped when no communication is necessary.
Table 7.2.4.2 Serial Interface Type Selection
SPI4 P68
1
‘-‘
IM2
0
IM1
‘-‘
IM0
Interface
‘-‘ 4-Pin Serial interface
Read back selection
Via the read instruction (8-bits, 24-bits and 32-bits read parameter
7.2.4.2.1 Command Write Mode
The write mode of the interface means the micro controller writes commands and data to the 4-Pin serial data packet. If D/CX is low, the
transmission byte is interpreted as command byte. If D/CX is high, the transmission byte is stored in the display data RAM (Memory write
command), or command register as parameter.
Any instruction can be sent in any order to the DRIVER. The MSB is transmitted first. The serial interface is initialized when CSX is high. In
this state, SCL clock pulse or SDA data have no effect. A falling edge on CSX enables the serial interface and indicates the start of data
transmission.
4-pins Serial Data Stream Format
Transmission byte(TB) may be a command or a data
MSB
LSB
D7 D6 D5 D4 D3 D2 D1 D0
(TB)
(TB)
(TB)
Fig. 7.2.4.2.1 Serial interface data Stream format
When CSX is high, SCL clock is ignored. During the high time of CSX the serial interface is initialized. At the falling edge of CSX, SCL can
be high or low. SDA is sampled at the rising edge of CSX. D/CX indicates, whether the byte is command code (D/CX=’0’) or parameter/RAM
data (D/CX=’1’). It is sampled when first rising edge of CSX. If CSX stay low after the last bit of command/data byte, the serial interface
expects the D/CX bit of the next byte at the next rising edge of SCL.
4-pins Serial Interface Protocol
S
TB
TB
P
CSX
Host
(MCU to
Driver)
SDA
D7
D6
D5
D4
D3
D/CX
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D/C
0
SCL
Command
Command / Parameter
CSX can be ‘H’ between parameter / command and
parameter/command SCL and SDA during CSX=’H’ is invalid
Fig. 7.2.4.2.2 4-pins Serial interface Write protocol (Write to register with control bit in
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7.2.4.2.2 Read Functions
The read mode of the interface means that the micro controller reads register value from the Driver. To do the micro controller first has to
send a command (Read ID or register command) and then the following byte is transmitted in the opposite direction. After the read status
command has been sent, the SDA lin must be set to tri-state no later than at the falling edge of SCL of the last bit.
4-pins Serial Protocol (for RDID1/ RDID2/ RDID3/ 0AH/ 0BH/ 0CH/ 0DH/ 0EH/ 0FH command: 8-bits read)
S
TB
TB
P
S
CSX
Host
(MCU to
Driver)
SCL
D/CX
0
SDA
(SDI)
SDA
(SDO)
D7
D6
D5
D4
D3
D2
D1
Hight-Z
D0
Hight-Z
D7
D6
D5
D4
D7
D2
D3
D1
D0
4-pins Serial Protocol (for RDDID command: 24-bits read)
S
TB
TB
P
S
CSX
Host
(MCU to
Driver)
SCL
D/CX
0
SDA
(SDI)
SDA
(SDO)
D7
D6
D5
D4
D3
D2
D1
Hight-Z
D0
Hight-Z
D23 D22 D21
D7
D2
D1
D0
Dummy Clock Cycle = 8 clock
4-pins Serial Protocol (for RDDST command: 32-bits read)
S
TB
TB
P
S
CSX
Host
(MCU to
Driver)
SCL
D/CX
SDA
(SDI)
SDA
(SDO)
0
D7
D6
D5
D4
D3
Hight-Z
D2
D1
Hight-Z
D0
D31 D30 D29 D28 D27 D26
D7
D2
D1
D0
Dummy Clock Cycle = 8 clock
Fig. 7.2.4.2.2 4-pins Serial interface Read protocol
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7.2.5.
Data Transfer Break and Recovery
If there is a break in data transmission by RESX pulse, while transferring a Command or Frame Memory Data or Multiple Parameter
command Data, before Bit D0 of the byte has been completed, then DRIVER will reject the previous bits and have reset the interface such
that it will be ready to receive command data again when the chip select line (CSX) is next activated after RESX have been High state. See
the following example
S
TB
TB
P
CSX
Host
(MPU to
Driver)
RESX
Wait for more than 10µs
SCL
SDA
D7
D/CX
D6
D5
D4
D3
D2
D/CX
D7
D6
D5
Command /
Parameter / Data
D4
D3
D2
D1
D0
Command
SCL and SDA during RESX = “L” is invalid and next
byte becomes command
Fig. 7.2.5.1 Serial bus protocol, write mode – interrupted by RESX
If there is a break in data transmission by CSX pulse, while transferring a Command or Frame Memory Data or Multiple Parameter
command Data, before Bit D0 of the byte has been completed, then DRIVER will reject the previous bits and have reset the interface such
that it will be ready to receive the same byte re-transmitted when the chip select line (CSX) is next activated. See the following example
S
TB
TB
P
CSX
SCL
Host
SDA
D/CX
(MPU to
Driver)
D7
D6
D5
D4
Command /
Parameter /
Data
D/CX
Break
D7
D6
D5
D4
D3
D2
D1
D0
Command /
Parameter /
Data
Fig. 7.2. 5.2 Serial bus protocol, write mode – interrupted by CSX
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If 1, 2 or more parameter command is being sent and a break occurs while sending any parameter before the last one and if the host then
sends a new command rather than re-transmitting the parameter that was interrupted, then the parameters that were successfully sent are
stored and the parameter where the break occurred is rejected. The interface is ready to receive next byte as shown below.
Break
CMD1
PARA11
PARA12
PARA11 is sucessfully sended but PARA12
is breaked and need to be transfered again
CMD2
CMD1
PARA11
PARA12
PARA13
Command1 with 1st parameter (PARA11) should
be executed again to write remained parameter
(PARA12 and PARA13)
Fig.7.2.5.3 Write interrupts recovery (serial interface)
If a 2 or more parameter command is being sent and a break occurs by the other command before the last one is sent, then the parameters
that were successfully sent are stored and the other parameter of that command remains previous value.
Break
CMD1
PARA11
PARA11 is sucessfully sent but the other parameters
are not sent and break happeds by the other
command.
CMD2
CMD1
PARA11
PARA12
PARA13
Command1 with 1st parameter (PARA11) should
be executed again to write remained parameter
(PARA12 and PARA13)
Fig. 7.2.5.4 Write interrupts recovery (both serial and parallel interface)
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7.2.6.
Data Transfer Pause
It will be possible when transferring a Command, Frame Memory Data or Multiple Parameter Data to invoke a pause in the data
transmission. If the Chip Select Line is released after a whole byte of a Frame Memory Data or Multiple Parameter Data has been
completed, then DRIVER will wait and continue the Frame Memory Data or Parameter Data Transmission from the point where it was
paused. If the Chip Select Line is released after a whole byte of a command has been completed, then the Display Module will receive
either the command’s parameters (if appropriate) or a new command when the Chip Select Line is next enabled as shown below.
This applies to the following 4 conditions:
1) Command-Pause-Command
2) Command-Pause-Parameter
3) Parameter-Pause-Command
4) Parameter-Pause-Parameter
7.2.6.1 Serial Interface Pause
S
TB
TB
Pause
CSX
Host
P
SCL
(MPU to
Driver)
SDA
D/CX
D7
D6
D5
D4
D3
D2
D1
D0
D/CX
Command / Parameter / Data
D7
D6
D5
D4
D3
D2
D1
D0
Command / Parameter / Data
SCL and SDA during CSX = “H” is invalid
Fig. 7.2.6.1 Serial interface Pause Protocol (pause by CSX)
7.2.6.2 Parallel Interface Pause
CSX
Pause
D/CX
RDX
WRX
D[17:0]
D17 to D0
D17 to D0
Command /
Parameter
Pause
Command /
Parameter
Fig. 7.2.6.2 Parallel bus Pause Protocol (paused by CSX)
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7.2.7.
Data Transfer Modes
The Module has three kinds colour modes for transferring data to the display RAM. These are 12-bit colour per pixel, 16-bit colour per pixel
and 18-bit colour per pixel. The data format is described for each interface. Data can be downloaded to the Frame Memory by 2 methods.
6.2.7.1 Method 1
The Image data is sent to the Frame Memory in successive Frame writes, each time the Frame Memory is filled, the Frame Memory pointer
is reset to the start point and the next Frame is written.
Start
Start Frame
Memory
Write
Stop
Image
Data
Frame 1
Image
Data
Frame 2
Image
Data
Frame 3
Any
Command
6.2.7.2 Method 2
Image Data is sent and at the end of each Frame Memory download, a command is sent to stop Frame Memory Write. Then Start Memory
Write command is sent, and a new Frame is downloaded.
Start
Start Frame
Memory
Write
Image
Data
Frame 1
Any
Command
Start Frame
Memory
Write
Image
Data
Frame 2
Any
Command
Stop
Any
Command
Note:
1) These apply to all data transfer Colour modes on both serial and parallel interfaces.
2) The frame memory can contain both odd and even number of pixels for both methods. Only complete pixel data will be stored in the
frame memory.
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7.3. MCU Data Colour Coding
7.3.1.
MCU Data Colour Coding for RAM data Write
- Parallel 8-Bits Bus Interface (IM1, IM0= “00”)
Table 7.3.1.1 8-Bits Parallel Interface Set Table
Register
D17 D16 D15 D14 D13 D12 D11 D10
Command
x
x
x
x
x
x
x
x
3AH
D17 D16 D15 D14 D13 D12 D11 D10
x
x
x
x
x
x
x
x
03h
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
05h
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
06h
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
D9
x
D9
x
x
x
x
x
x
x
x
D8
x
D8
x
x
x
x
x
x
x
x
D7
0
D7
R3
B3
G3
R4
G2
R5
G5
B5
D6
0
D6
R2
B2
G2
R3
G1
R4
G4
B4
D5
1
D5
R1
B1
G1
R2
G0
R3
G3
B3
D4
0
D4
R0
B0
G0
R1
B4
R2
G2
B2
D3
1
D3
G3
R3
B3
R0
B3
R1
G1
B1
D2
1
D2
G2
R2
B2
G5
B2
R0
G0
B0
D1
0
D1
G1
R1
B1
G4
B1
x
x
x
D0
Command
0
2CH
D0
Colour
G0
4K-Colour
R0 (2-pixels/ 3-byyes)
B0
G3
65K-Colour
B0 (1-pixels/ 2-byyes)
x
262K-Colour
x (1-pixels/ 3byyes)
x
Table 7.3.1.2 16-Bits Parallel Interface Set Table
Register
D17 D16 D15 D14 D13 D12 D11 D10 D9
Command
x
x
x
x
x
x
x
x
x
3AH
D17 D16 D15 D14 D13 D12 D11 D10 D9
03h
x
x
x
x
x
x
R3 R2 R1
05h
x
x
R4 R3 R2 R1 R0 G5 G4
x
x
R5 R4 R3 R2 R1 R0
x
06h
x
x
B5 B4 B3 B2 B1 B0
x
x
x
G5 G4 G3 G2 G1 G0
x
D8
x
D8
R0
G3
x
x
x
D7
0
D7
G3
G2
G5
R5
B5
D6
0
D6
G2
G1
G4
R4
B4
D5
1
D5
G1
G0
G3
R3
B3
D4
0
D4
G0
B4
G2
R2
B2
D3
1
D3
B3
B3
G1
R1
B1
D2
1
D2
B2
B2
G0
R0
B0
D1
0
D1
B1
B1
x
x
x
D0
0
D0
B0
B0
x
x
x
D9
x
D9
x
x
D8
x
D8
R5
G2
D7
0
D7
R4
G1
D6
0
D6
R3
G0
D5
1
D5
R2
B5
D4
0
D4
R1
B4
D3
1
D3
R0
B3
D2
1
D2
G5
B2
D1
0
D1
G4
B1
D0
0
D0
G3
B0
Register
2CH
Colour
262K-Colour
(1-pixels/ 2bytes)
Table 7.3.1.4 18-Bits Parallel Interface Set Table
Register
D17 D16 D15 D14 D13 D12 D11 D10 D9
Command
x
x
x
x
x
x
x
x
x
3AH
D17 D16 D15 D14 D13 D12 D11 D10 D9
03h
x
x
x
x
x
x
R3 R2 R1
05h
x
x
R4 R3 R2 R1 R0 G5 G4
06h
R5 R4 R3 R2 R1 R0 G5 G4 G3
D8
x
D8
R0
G3
G2
D7
0
D7
G3
G2
G1
D6
0
D6
G2
G1
G0
D5
1
D5
G1
G0
B5
D4
0
D4
G0
B4
B4
D3
1
D3
B3
B3
B3
D2
1
D2
B2
B2
B2
D1
0
D1
B1
B1
B1
D0
0
D0
B0
B0
B0
Register
2CH
Colour
4K-Colour
65K-Colour
262K-Colour
- Parallel 16-Bits Bus Interface (IM1, IM0= “01”)
Command
2CH
Colour
4K-Colour
65K-Colour
262K-Colour
(2-pixels/ 3byyes)
- Parallel 9-Bits Bus Interface (IM1, IM0= “10”)
Table 7.3.1.3 9-Bits Parallel Interface Set Table
Register
D17 D16 D15 D14 D13 D12 D11 D10
Command
x
x
x
x
x
x
x
x
3AH
D17 D16 D15 D14 D13 D12 D11 D10
x
x
x
x
x
x
x
x
06h
x
x
x
x
x
x
x
x
- Parallel 18-Bits Bus Interface (IM1, IM0= “11”)
Note: ‘x’ Don’t care, but need to set VDDIO or DGND level.
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Preliminary
SPFD54124B
7.3.1.1 Parallel 8-Bits Bus Interface for RAM Data Write (IM1, IM0= “00”)
Different display data formats are available for three colours depth supported by listed below.
- 4K-Colours, RGB 4,4,4-bits input data. (3AH=”03h”)
- 65K-Colours, RGB 5,6,5-bits input data. (3AH=”05h”)
- 262K-Colours, RGB 6,6,6-bits input data. (3AH=”06h”)
(1). 8-bits data bus for 12-bits/pixel (RGB 4-4-4-bits input), 4K-colours, 3AH=”03h”
There are 2 pixels (6 sub-pixels) per 3-bytes.
RESX
‘1’
IM1, IM0 = ”00”
IM1/IM0
CSX
D/CX
WRX
RDX
‘1’
8080-Series control pins
R/WX
‘0’
6800-Series control pins
E
D7
0
R1, Bit 3
B1, Bit 3
G2, Bit 3
R3, Bit 3
D6
0
R1, Bit 2
B1, Bit 2
G2, Bit 2
R3, Bit 2
D5
1
R1, Bit 1
B1, Bit 1
G2, Bit 1
R3, Bit 1
D4
0
R1, Bit 0
B1, Bit 0
G2, Bit 0
R3, Bit 0
D3
1
G1, Bit 3
R2, Bit 3
B2, Bit 3
G3, Bit 3
D2
1
G1, Bit 2
R2, Bit 2
B2, Bit 2
G3, Bit 2
D1
0
G1, Bit 1
R2, Bit 1
B2, Bit 1
G3, Bit 1
D0
0
G1, Bit 0
R2, Bit 0
B2, Bit 0
G3, Bit 0
Pixel n
Pixel n+1
12-bits
12-bits
Look-Up Table for 4K-colors or data mapping (12-Bits to 18-Bits)
18-bits
Frame
Memory
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data.
Note 2.3-times transfer is used to transmit 1 pixel data with the 12-bits color depth information.
Note 3. ‘-‘ = Don't care - Can be set to VDDIO or DGND level
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Preliminary
SPFD54124B
(2). 8-bits data bus for 16-bits/pixel (RGB 5-6-5-bits input), 65K-colours, 3AH=”05h”
There are 1 pixels (3 sub-pixels) per 2-bytes.
RESX
‘1’
IM1, IM0 = ”00”
IM1/IM0
CSX
D/CX
WRX
RDX
‘1’
8080-Series control pins
R/WX
‘0’
6800-Series control pins
E
D7
0
R1, Bit 4
G1, Bit 2
R2, Bit 4
G2, Bit 2
D6
0
R1, Bit 3
G1, Bit 1
R2, Bit 3
G2, Bit 1
D5
1
R1, Bit 2
G1, Bit 0
R2, Bit 2
G2, Bit 0
D4
0
R1, Bit 1
B1, Bit 5
R2, Bit 1
B2, Bit 5
D3
1
R1, Bit 0
B1, Bit 3
R2, Bit 0
B2, Bit 3
D2
1
G1, Bit 5
B1, Bit 2
G2, Bit 5
B2, Bit 2
D1
0
G1, Bit 4
B1, Bit 1
G2, Bit 4
B2, Bit 1
D0
0
G1, Bit 3
B1, Bit 0
G2, Bit 3
B2, Bit 0
Pixel n+1
Pixel n
16-bits
16-bits
Look-Up Table for 4K-colors or data mapping (16-Bits to 18-Bits)
18-bits
Frame
Memory
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green and MSB=Bit 4, LSB=Bit 0 for
Red and Blue data.
Note 2.2-times transfer is used to transmit 1 pixel data with the 16-bits color depth information.
Note 3. ‘-‘ = Don't care - Can be set to VDDIO or DGND level
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Preliminary
SPFD54124B
(3). 8-bits data bus for 18-bits/pixel (RGB 6-6-6-bits input), 262K-colours, 3AH=”06h”
There are 1 pixels (3 sub-pixels) per 3-bytes.
RESX
‘1’
IM1, IM0 = ”00”
IM1/IM0
CSX
D/CX
WRX
RDX
‘1’
8080-Series control pins
R/WX
‘0’
6800-Series control pins
E
D7
0
R1, Bit 5
G1, Bit 5
B1, Bit 5
R2, Bit 5
D6
0
R1, Bit 4
G1, Bit 4
B1, Bit 4
R2, Bit 4
D5
1
R1, Bit 3
G1, Bit 3
B1, Bit 3
R2, Bit 3
D4
0
R1, Bit 2
G1, Bit 2
B1, Bit 2
R2, Bit 2
D3
1
R1, Bit 1
G1, Bit 1
B1, Bit 1
R2, Bit 1
D2
1
R1, Bit 0
G1, Bit 0
B1, Bit 0
R2, Bit 0
D1
0
-
-
-
-
D0
0
-
-
-
-
Pixel n+1
Pixel n
18-bits
18-bits
Frame
Memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2.3-times transfer is used to transmit 1 pixel data with the 18-bits color depth information.
Note 3. ‘-‘ = Don't care - Can be set to VDDIO or DGND level
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Preliminary Version: 0.6
Preliminary
SPFD54124B
7.3.1.2 Parallel 16-Bits Bus Interface for RAM Data Write (IM1, IM0=”01”)
Different display data formats are available for three colors depth supported by listed below.
- 4K-Colours, RGB 4,4,4-bits input data. (3AH=”03h”)
- 65K-Colours, RGB 5,6,5-bits input data. (3AH=”05h”)
- 262K-Colours, RGB 6,6,6-bits input data. (3AH=”06h”)
(1). 16-bits data bus for 12-bits/pixel (RGB 4-4-4-bits input), 4K-colours, 3AH=”03h”
There are 1 pixel (3 sub-pixels) per 1 bytes
RESX ‘1’
IM1/IM0 IM1 IM0=”01”
CSX
D/CX
WRX
RDX ‘1’
8080-Series control
R/WX ‘0’
6800-Series control
E
D15
-
-
-
-
-
D14
-
-
-
-
-
D13
-
-
-
-
-
D12
-
-
-
-
-
D11
-
R1 Bit 3
R2 Bit 3
R3 Bit 3
R4 Bit 3
D10
-
R1 Bit 2
R2 Bit 2
R3 Bit 2
R4 Bit 2
D9
-
R1 Bit 1
R2 Bit 1
R3 Bit 1
R4 Bit 1
D8
-
R1 Bit 0
R2 Bit 0
R3 Bit 0
R4 Bit 0
D7
0
G1 Bit 3
G2 Bit 3
G3 Bit 3
G4 Bit 3
D6
0
G1 Bit 2
G2 Bit 2
G3 Bit 2
G4 Bit 2
D5
1
G1 Bit 1
G2 Bit 1
G3 Bit 1
G4 Bit 1
D4
0
G1 Bit 0
G2 Bit 0
G3 Bit 0
G4 Bit 0
D3
1
B1 Bit 3
B2 Bit 3
B3 Bit 3
B4 Bit 3
D2
1
B1 Bit 2
B2 Bit 2
B3 Bit 2
B4 Bit 2
D1
0
B1 Bit 1
B2 Bit 1
B3 Bit 1
B4 Bit 1
D0
0
B1 Bit 0
B2 Bit 0
B3 Bit 0
B4 Bit 0
Pixel n+2
Pixel n+3
Pixel n
Pixel n+1
12-bits
12-bits
Look-Up Table for 4K-colors or data mapping (12-Bits to 18-Bits)
18-bits
Frame
Memory
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data.
Note 2.1-times transfer is used to transmit 1 pixel data with the 12-bits color depth information.
Note 3. ‘-‘ = Don't care - Can be set to VDDIO or DGND level
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Preliminary
SPFD54124B
(2). 16-bits data bus for 16-bits/pixel (RGB 5-6-5-bits input), 65K-colours, 3AH=”05h”
There are 1 pixel (3 sub-pixels) per 1 bytes
RESX
‘1’
IM1, IM0=”01”
IM1/IM0
CSX
D/CX
WRX
RDX
‘1’
8080-Series control pins
R/WX
‘0’
6800-Series control pins
E
D15
-
R1, Bit 4
R2, Bit 4
R3, Bi
R4, Bit 4
D14
-
R1, Bit 3
R2, Bit 3
R3, Bit 3
R4, Bit 3
D13
-
R1, Bit 2
R2, Bit 2
R3, Bit 2
R4, Bit 2
D12
-
R1, Bit 1
R2, Bit 1
R3, Bit 1
R4, Bit 1
D11
-
R1, Bit 0
R2, Bit 0
R3, Bit 0
R4, Bit 0
D10
-
G1, Bit 5
G2, Bit 5
G3, Bit 5
G4, Bit 5
D9
-
G1, Bit 4
G2, Bit 4
G3, Bit 4
G4, Bit 4
D8
-
G1, Bit 3
G2, Bit 3
G3, Bit 3
G4, Bit 3
D7
0
G1, Bit 2
G2, Bit 2
G3, Bit 2
G4, Bit 2
D6
0
G1, Bit 1
G2, Bit 1
G3, Bit 1
G4, Bit 1
D5
1
G1, Bit 0
G2, Bit 0
G3, Bit 0
G4, Bit 0
D4
0
B1, Bit 4
B2, Bit 4
B3, Bit 4
B4, Bit 4
D3
1
B1, Bit 3
B2, Bit 3
B3, Bit 3
B4, Bit 3
D2
1
B1, Bit 2
B2, Bit 2
B3, Bit 2
B4, Bit 2
D1
0
B1, Bit 1
B2, Bit 1
B3, Bit 1
B4, Bit 1
D1
0
B1, Bit 0
Pixel n
B2, Bit 0
Pixel n+1
16-bits
B4, Bit 0
Pixel n+2
Pixel n+3
16-bits
Look-Up Table for 4K-colors or data mapping (16-Bits to 18-Bits)
18-bits
Frame
Memory
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0 for
Red and Blue data.
Note 2.1-times transfer is used to transmit 1 pixel data with the 16-bits color depth information.
Note 3. ‘-‘ = Don't care - Can be set to VDDIO or DGND level
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Preliminary Version: 0.6
Preliminary
SPFD54124B
(3). 16-bits data bus for 18-bits/pixel (RGB 6-6-6-bits input), 262K-colours, 3AH=”06h”
There are 2 pixel (6 sub-pixels) per 3 bytes
RESX
‘1’
IM1, IM0=”01”
IM1/IM0
CSX
D/CX
WRX
RDX
‘1’
8080-Series control pins
R/WX
‘0’
6800-Series control pins
E
D15
-
R1, Bit 5
B1, Bit 5
G2, Bit 5
R3, Bit 5
D14
-
R1, Bit 4
B1, Bit 4
G2, Bit 4
R3, Bit 4
D13
-
R1, Bit 3
B1, Bit 3
G2, Bit 3
R3, Bit 3
D12
-
R1, Bit 2
B1, Bit 2
G2, Bit 2
R3, Bit 2
D11
-
R1, Bit 1
B1, Bit 1
G2, Bit 1
R3, Bit 1
D10
-
R1, Bit 0
B1, Bit 0
G2, Bit 0
R3, Bit 0
D9
-
-
-
-
-
D8
-
-
-
-
-
D7
0
G1, Bit 5
R2, Bit 5
B2, Bit 5
G3, Bit 5
D6
0
G1, Bit 4
R2, Bit 4
B2, Bit 4
G3, Bit 4
D5
1
G1, Bit 3
R2, Bit 3
B2, Bit 3
G3, Bit 3
D4
0
G1, Bit 2
R2, Bit 2
B2, Bit 2
G3, Bit 2
D3
1
G1, Bit 1
R2, Bit 1
B2, Bit 1
G3, Bit 1
D2
1
G1, Bit 0
R2, Bit 0
B2, Bit 0
G3, Bit 0
D1
0
-
-
-
-
D0
0
-
-
-
-
Pixel n
Pixel n+1
18-bits
Frame
Memory
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2.3-times transfer is used to transmit 1 pixel data with the 18-bits color depth information.
Note 3. ‘-‘ = Don't care - Can be set to VDDIO or DGND level
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Preliminary Version: 0.6
Preliminary
SPFD54124B
7.3.1.3 Parallel 9-Bits Bus Interface for RAM Data Write (IM1, IM0=”10”)
Different display data formats are available for three colors depth supported by listed below.
- 262K-Colours, RGB 6,6,6-bits input data. (3AH=”06h”)
(1). 9-bits data bus for 18-bits/pixel (RGB 6-6-6-bits input), 262K-colours, 3AH=”06h”
There is 1 pixel (3 sub-pixels) per 2 bytes
RESX
‘1’
IM1, IM0 = “10”
IM1/IM0
CSX
D/CX
WRX
RDX
‘1’
8080-Series control pins
R/WX
‘0’
6800-Series control pins
E
D8
-
R1, Bit 5
G1, Bit 2
R2, Bit 5
G2, Bit 2
D7
0
R1, Bit 4
G1, Bit 1
R2, Bit 4
G2, Bit 1
D6
0
R1, Bit 3
G1, Bit 0
R2, Bit 3
G2, Bit 0
D5
1
R1, Bit 2
B1, Bit 5
R2, Bit 2
B2, Bit 5
D4
0
R1, Bit 0
B1, Bit 4
R2, Bit 1
B2, Bit 4
D3
1
R1, Bit 0
B1, Bit 3
R2, Bit 0
B2, Bit 3
D2
1
G1, Bit 5
B1, Bit 2
G2, Bit 5
B2, Bit 2
D1
0
G1, Bit 4
B1, Bit 1
G2, Bit 4
B2, Bit 1
D0
0
G1, Bit 3
B1, Bit 0
G2, Bit 3
B2, Bit 0
Pixel n
Pixel n+1
18-bits
Frame
Memory
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D8, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2.3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3. ‘-‘ = Don't care - Can be set to VDDIO or DGND level
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Preliminary Version: 0.6
Preliminary
SPFD54124B
7.3.1.4 Parallel 18-Bits Bus Interface for RAM Data Write (IM1, IM0=”11”)
Different display data formats are available for three colors depth supported by listed below.
- 4K-Colours, RGB 4,4,4-bits input data. (3AH=”03h”)
- 65K-Colours, RGB 5,6,5-bits input data. (3AH=”05h”)
- 262K-Colours, RGB 6,6,6-bits input data. (3AH=”06h”)
(1). 18-bits data bus for 12-bits/pixel (RGB 4-4-4-bits input), 4K-colours, 3AH=”03h”
There is 1 pixel (3 sub-pixels) per 1 bytes
RESX ‘1’
IM1/IM0 IM1 IM0=”11”
CSX
D/CX
WRX
RDX ‘1’
8080-Series control
R/WX ‘0’
6800-Series control
E
D17
-
-
-
-
-
D16
-
-
-
-
-
D12
-
-
-
-
-
D11
-
R1 Bit
R2 Bit
R3 Bit
R4 Bit
D10
-
R1 Bit
R2 Bit
R3 Bit
R4 Bit
D9
-
R1 Bit
R2 Bit
R3 Bit
R4 Bit
D8
-
R1 Bit
R2 Bit
R3 Bit
R4 Bit
D7
0
G1 Bit
G2 Bit
G3 Bit
G4 Bit
D6
0
G1 Bit
G2 Bit
G3 Bit
G4 Bit
D5
1
G1 Bit
G2 Bit
G3 Bit
G4 Bit
D4
0
G1 Bit
G2 Bit
G3 Bit
G4 Bit
D3
1
B1 Bit
B2 Bit
B3 Bit
B4 Bit
D2
1
B1 Bit
B2 Bit
B3 Bit
B4 Bit
D1
0
B1 Bit
B2 Bit
B3 Bit
B4 Bit
D0
0
B1 Bit
Pixel n
12-bits
B2 Bit
Pixel n+1
B3 Bit
Pixel n+2
B4 Bit
Pixel n+3
12-bits
Look-Up Table for 4K-colors or data mapping (12-Bits to 18-Bits)
18-bits
18-bits
Frame
Memory R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D17, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data.
Note 2.1-times transfer is used to transmit 1 pixel data with the 12-bits color depth information.
Note 3. ‘-‘ = Don't care - Can be set to VDDIO or DGND level
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Preliminary Version: 0.6
Preliminary
SPFD54124B
(2). 18-bits data bus for 16-bits/pixel (RGB 5-6-5-bits input), 65K-colours, 3AH=”05h”
There are 1 pixel (3 sub-pixels) per 1 bytes
RESX
‘1’
IM1, IM0=”11”
IM1/IM0
CSX
D/CX
WRX
RDX
‘1’
8080-Series control pins
R/WX
‘0’
6800-Series control pins
E
D17
-
-
-
-
-
D16
-
-
-
-
-
D15
-
R1, Bit 4
R2, Bit 4
R3, Bi
R4, Bit 4
D14
-
R1, Bit 3
R2, Bit 3
R3, Bit 3
R4, Bit 3
D13
-
R1, Bit 2
R2, Bit 2
R3, Bit 2
R4, Bit 2
D12
-
R1, Bit 1
R2, Bit 1
R3, Bit 1
R4, Bit 1
D11
-
R1, Bit 0
R2, Bit 0
R3, Bit 0
R4, Bit 0
D10
-
G1, Bit 5
G2, Bit 5
G3, Bit 5
G4, Bit 5
D9
-
G1, Bit 4
G2, Bit 4
G3, Bit 4
G4, Bit 4
D8
-
G1, Bit 3
G2, Bit 3
G3, Bit 3
G4, Bit 3
D7
0
G1, Bit 2
G2, Bit 2
G3, Bit 2
G4, Bit 2
D6
0
G1, Bit 1
G2, Bit 1
G3, Bit 1
G4, Bit 1
D5
1
G1, Bit 0
G2, Bit 0
G3, Bit 0
G4, Bit 0
D4
0
B1, Bit 4
B2, Bit 4
B3, Bit 4
B4, Bit 4
D3
1
B1, Bit 3
B2, Bit 3
B3, Bit 3
B4, Bit 3
D2
1
B1, Bit 2
B2, Bit 2
B3, Bit 2
B4, Bit 2
D1
0
B1, Bit 1
B2, Bit 1
B3, Bit 1
B4, Bit 1
D0
0
B1, Bit 0
B2, Bit 0
Pixel n
Pixel n
16-bits
B1, Bit 0
Pixel n
B4, Bit 0
Pixel n
16-bits
Look-Up Table for 65K-colors or data mapping (16-Bits to 18-Bits)
18-bits
Frame
Memory
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D17, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0 for
Red and Blue data.
Note 2.1-times transfer is used to transmit 1 pixel data with the 16-bits color depth information.
Note 3. ‘-‘ = Don't care - Can be set to VDDIO or DGND level
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Preliminary Version: 0.6
Preliminary
SPFD54124B
(3). 18-bits data bus for 18-bits/pixel (RGB 6-6-6-bits input), 262K-colours, 3AH=”06h”
There are 1 pixel (6 sub-pixels) per 1 bytes
RESX
‘1’
IM1, IM0=”11”
IM1/IM0
CSX
D/CX
WRX
RDX
‘1’
8080-Series control pins
R/WX
‘0’
6800-Series control pins
E
D17
-
R1, Bit 5
R2, Bit 5
R3, Bit5
R4, Bit 5
D16
-
R1, Bit 4
R2, Bit 4
R3, Bit5
R4, Bit 4
D15
-
R1, Bit 3
R2, Bit 3
R3, Bit 3
R4, Bit 3
D14
-
R1, Bit 2
R2, Bit 2
R3, Bit 2
R4, Bit 2
D13
-
R1, Bit 1
R2, Bit 1
R3, Bit 1
R4, Bit 1
D12
-
R1, Bit 0
R2, Bit 0
R3, Bit 0
R4, Bit 0
D11
-
G1, Bit 5
G2, Bit 5
G3, Bit 5
G4, Bit 5
D10
-
G1, Bit 4
G2, Bit 4
G3, Bit 4
G4, Bit 4
D9
-
G1, Bit 3
G2, Bit 3
G3, Bit 3
G4, Bit 3
D8
-
G1, Bit 2
G2, Bit 2
G3, Bit 2
G4, Bit 2
D7
0
G1, Bit 1
G2, Bit 1
G3, Bit 1
G4, Bit 1
D6
0
G1, Bit 0
G2, Bit 0
G3, Bit 0
G4, Bit 0
D5
1
B1, Bit 5
B2, Bit 5
B3, Bit 5
B4, Bit 5
D4
0
B1, Bit 4
B2, Bit 4
B3, Bit 4
B4, Bit 4
D3
1
B1, Bit 3
B2, Bit 3
B3, Bit 3
B4, Bit 3
D2
1
B1, Bit 2
B2, Bit 2
B3, Bit 2
B4, Bit 2
D1
0
B1,
PixelBit 1
n
B2, Bit
Pixel n+11
B3, Bit
Pixel n+21
B4, Bit
Pixel n+31
D0
0
B1, Bit 0
B2, Bit 0
B1, Bit 0
B4, Bit 0
18-bits
Frame
Memory
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D17, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2.1-times transfer is used to transmit 1 pixel data with the 18-bits color depth information.
Note 3. ‘-‘ = Don't care - Can be set to VDDIO or DGND level
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7.3.2.
MCU Data Colour Coding for RAM data Read
- Parallel 8-Bits Bus Interface (IM1, IM0= “00”)
Table 7.3.2.1 8-Bits Parallel Interface Set Table
Register
D17 D16 D15 D14 D13 D12 D11 D10
Command
x
x
x
x
x
x
x
x
D17 D16 D15 D14 D13 D12 D11 D10
x
x
x
x
x
x
x
x
Read
Data Format
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
D9
x
D9
x
x
x
D8
x
D8
x
x
x
D7
0
D7
R5
G5
B5
D6
0
D6
R4
G4
B4
D5
1
D5
R3
G3
B3
D4
0
D4
R2
G2
B2
D3
1
D3
R1
G1
B1
D2
1
D2
R0
G0
B0
D1
1
D1
x
x
x
D0
0
D0
x
x
x
Command
2EH
Colour
D9
x
D9
x
x
x
D8
x
D8
x
x
x
D7
0
D7
G5
R5
B5
D6
0
D6
G4
R4
B4
D5
1
D5
G3
R3
B3
D4
0
D4
G2
R2
B2
D3
1
D3
G1
R1
B1
D2
1
D2
G0
R0
B0
D1
1
D1
x
x
x
D0
0
D0
x
x
x
D9
x
D9
x
x
D8
x
D8
R5
G2
D7
0
D7
R4
G1
D6
0
D6
R3
G0
D5
1
D5
R2
B5
D4
0
D4
R1
B4
D3
1
D3
R0
B3
D2
1
D2
G5
B2
D1
1
D1
G4
B1
D0
0
D0
G3
B0
Register
2EH
Colour
262K-Colour
(1-pixels/ 2bytes)
D8
x
D7
0
D6
0
D5
1
D4
0
D3
1
D2
1
D1
1
D0
0
Register
2EH
G2
G1
G0
B5
B4
B3
B2
B1
B0
262K-Colour
262K-Colour
(1-pixels/ 3byyes)
- Parallel 16-Bits Bus Interface (IM1, IM0= “01”)
Table 7.3.2.2 16-Bits Parallel Interface Set Table
Register
D17 D16 D15 D14 D13 D12 D11 D10
Command
x
x
x
x
x
x
x
x
D17 D16 D15 D14 D13 D12 D11 D10
x
x
R5 R4 R3 R2 R1 R0
Read
Data Format
x
x
B5 B4 B3 B2 B1 B0
x
x
G5 G4 G3 G2 G1 G0
Command
2EH
Colour
262K-Colour
(2-pixels/ 3byyes)
- Parallel 9-Bits Parallel Interface (IM1, IM0= “10”)
Table 7.3.2.3 9-Bits Parallel Interface Set Table
Register
D17 D16 D15 D14 D13 D12 D11 D10
Command
x
x
x
x
x
x
x
x
D17 D16 D15 D14 D13 D12 D11 D10
Read
x
x
x
x
x
x
x
x
Data Format
x
x
x
x
x
x
x
x
- Parallel 18-Bits Parallel Interface (IM1, IM0= “11”)
Table 7.3.2.4 18-Bits Parallel Interface Set Table
Register
D17 D16 D15 D14 D13 D12 D11 D10 D9
Command
x
x
x
x
x
x
x
x
x
Read
R5 R4 R3 R2 R1 R0 G5 G4 G3
Data Format
Note . ‘x’ Don’t care, but need to set VDDIO or DGND level.
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7.3.2.1 Parallel 8-Bits Bus Interface for RAM Data Read (IM1, IM0= “00”)
There are 1 pixels (3 sub-pixels) per 3-bytes. (RGB 6-6-6-bits output)
RESX
‘1’
IM1, IM0 = ”00”
IM1/IM0
CSX
D/CX
RDX
WRX
R/WX
‘1’
‘0’
8080-Series control pins
6800-Series control pins
‘1’
E
D7
0
---
R1, Bit 5
G1, Bit 5
B1, Bit 5
D6
0
---
R1, Bit 4
G1, Bit 4
B1, Bit 4
D5
1
---
R1, Bit 3
G1, Bit 3
B1, Bit 3
D4
0
---
R1, Bit 2
G1, Bit 2
B1, Bit 2
D3
1
---
R1, Bit 1
G1, Bit 1
B1, Bit 1
D2
1
---
R1, Bit 0
G1, Bit 0
B1, Bit 0
D1
1
---
-
-
-
D0
0
---
-
-
-
Dummy Pixel
Pixel n
18-bits
Frame
Memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2.3-times transfer is used to transmit 1 pixel data with the 18-bits color depth information.
Note 3. ‘-‘ = Don't care - Can be set to VDDIO or DGND level
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7.3.2.2 Parallel 16-Bits Bus Interface for RAM Data Read (IM1, IM0= “01”)
There are 2 pixel (6 sub-pixels) per 3 bytes (RGB 6-6-6-bits output)
RESX
‘1’
IM1, IM0 = ”01”
IM1/IM0
CSX
D/CX
RDX
WRX
R/WX
‘1’
‘0’
8080-Series control pins
6800-Series control pins
‘1’
E
D15
-
---
R1, Bit 5
B1, Bit 5
G2, Bit 5
D14
-
---
R1, Bit 4
B1, Bit 4
G2, Bit 4
D13
-
---
R1, Bit 3
B1, Bit 3
G2, Bit 3
D12
-
---
R1, Bit 2
B1, Bit 2
G2, Bit 2
D11
-
---
R1, Bit 1
B1, Bit 1
G2, Bit 1
D10
-
---
R1, Bit 0
B1, Bit 0
G2, Bit 0
D9
-
---
-
-
-
D8
-
---
-
-
-
D7
0
---
G1, Bit 5
R2, Bit 5
B2, Bit 5
D6
0
---
G1, Bit 4
R2, Bit 4
B2, Bit 4
D5
1
---
G1, Bit 3
R2, Bit 3
B2, Bit 3
D4
0
---
G1, Bit 2
R2, Bit 2
B2, Bit 2
D3
1
---
G1, Bit 1
R2, Bit 1
B2, Bit 1
D2
1
---
G1, Bit 0
R2, Bit 0
B2, Bit 0
D1
1
---
-
-
-
D0
0
---
-
-
-
Dummy Pixel
Pixel n
Pixel n+1
18-bits
Frame
Memory
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2.3-times transfer is used to transmit 1 pixel data with the 18-bits color depth information.
Note 3. ‘-‘ = Don't care - Can be set to VDDIO or DGND level
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7.3.2.3 Parallel 9-Bits Bus Interface for RAM Data Read (IM1, IM0= “10”)
There are 1 pixel (3 sub-pixels) per 2 bytes (RGB 6-6-6-bits output)
RESX
‘1’
IM1, IM0 = ”10”
IM1/IM0
CSX
D/CX
RDX
WRX
R/WX
‘1’
‘0’
8080-Series control pins
6800-Series control pins
‘1’
E
D8
-
---
R1, Bit 5
G1, Bit 2
R2, Bit 5
D7
0
---
R1, Bit 4
G1, Bit 1
R2, Bit 4
D6
0
---
R1, Bit 3
G1, Bit 0
R2, Bit 3
D5
1
---
R1, Bit 2
B1, Bit 5
R2, Bit 2
D4
0
---
R1, Bit 0
B1, Bit 4
R2, Bit 1
D3
1
---
R1, Bit 0
B1, Bit 3
R2, Bit 0
D2
1
---
G1, Bit 5
B1, Bit 2
G2, Bit 5
D1
1
---
G1, Bit 4
B1, Bit 1
G2, Bit 4
D0
0
---
G1, Bit 3
B1, Bit 0
G2, Bit 3
Dummy Pixel
Pixel n
Pixel n+1
18-bits
Frame
Memory
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D8, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2.3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3. ‘-‘ = Don't care - Can be set to VDDIO or DGND level
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7.3.2.4 Parallel 18-Bits Bus Interface for RAM Data Read (IM1, IM0= “11”)
There are 1 pixel (3 sub-pixels) per 1 bytes (RGB 6-6-6-bits output)
RESX
‘1’
IM1, IM0 = ”11”
IM1/IM0
CSX
D/CX
RDX
WRX
R/WX
‘1’
‘0’
8080-Series control pins
6800-Series control pins
‘1’
E
D17
-
---
R1, Bit 5
R2, Bit 5
R3, Bit5
D16
-
---
R1, Bit 4
R2, Bit 4
R3, Bit5
D15
-
---
R1, Bit 3
R2, Bit 3
R3, Bit 3
D14
-
---
R1, Bit 2
R2, Bit 2
R3, Bit 2
D13
-
---
R1, Bit 1
R2, Bit 1
R3, Bit 1
D12
-
---
R1, Bit 0
R2, Bit 0
R3, Bit 0
D11
-
--
G1, Bit 5
G2, Bit 5
G3, Bit 5
D10
-
---
G1, Bit 4
G2, Bit 4
G3, Bit 4
D9
-
---
G1, Bit 3
G2, Bit 3
G3, Bit 3
D8
-
---
G1, Bit 2
G2, Bit 2
G3, Bit 2
D7
0
---
G1, Bit 1
G2, Bit 1
G3, Bit 1
D6
0
--
G1, Bit 0
G2, Bit 0
G3, Bit 0
D5
1
---
B1, Bit 5
B2, Bit 5
B3, Bit 5
D4
0
---
B1, Bit 4
B2, Bit 4
B3, Bit 4
D3
1
---
B1, Bit 3
B2, Bit 3
B3, Bit 3
D2
1
---
B1, Bit 2
B2, Bit 2
B3, Bit 2
D1
1
---
B1, Bit 1
B2, Bit 1
B3, Bit 1
D0
0
---
B1, Bit 0
Dummy Pixel
Pixel n
B2, Bit 0
Pixel n+1
18-bits
Frame
Memory
B1, Bit 0
Pixel n+2
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D17, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2.1-times transfer is used to transmit 1 pixel data with the 18-bits color depth information.
Note 3. ‘-‘ = Don't care - Can be set to VDDIO or DGND level
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SPFD54124B
7.3.3.
Serial Interface (IM2 = ‘0’)
Different display data formats are available for three colors depth supported by the LCM listed below.
- 4K-Colours, RGB 4,4,4-bits input data. (3AH=”03h”)
- 65K-Colours, RGB 5,6,5-bits input data. (3AH=”05h”)
- 262K-Colours, RGB 6,6,6-bits input data. (3AH=”06h”)
7.3.3.1 Write data for 12-bits/pixel (RGB 4-4-4-bits input), 4K-colours, 3AH=”03h”
RESX
‘1’
IM2
‘0’
IM1,IM0= “xx”
CSX
Pixel n
D8
SDA
1
D7
D6
D5
D4
D3
D2
Pixel n+1
D1
D0
D8
R13 R12 R11 R10 G13 G12 G11 G10
1
D7
D6
D5
D4
D3
D2
D1
D0
D8
B13 B12 B11 B10 R23 R22 R21 R20
1
D7
D6
D5
D4
D3
D2
D1
D0
G23 G22 G21 G20 B23 B22 B21 B20
SCL
12-bits
12-bits
Look-Up Table for 4K-colors mapping (12-Bits to 18-Bits)
18-bits
Frame
Memory
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1. pixel data with the 12-bits color depth information
Note 2. The most significant bits are: Rx3, Gx3 and Bx3
Note 3. The least significant bits are: Rx0, Gx0 and Bx0
Note 4. ‘-‘ = Don't care - Can be set to VDDIO or DGND level
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7.3.3.2 Write data for 16-bits/pixel (RGB 5-6-5-bits input), 65K-colours, 3AH=”05h”
RESX
‘1’
IM2
‘0’
IM1,IM0= “xx”
CSX
Pixel n
D8
SDA
1
D7
D6
D5
D4
D3
D2
D1
D0
R14 R13 R12 R11 R10 G15 G14 G13
1
Pixel n+1
D8
D7
D6
D5
D4
D3
D2
D1
D0
D8
G12 G11 G10 B14 B13 B12 B11 B10
1
D7
D6
D5
D4
D3
D2
D1
D0
R24 R23 R22 R21 R20 G25 G24 G23
SCL
16-bits
Look-Up Table for 65k-colors mapping (16-Bits to 18-Bits)
18-bits
Frame
Memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1. pixel data with the 16-bits color depth information
Note 2. The most significant bits are: Rx4, Gx5 and Bx4
Note 3. The least significant bits are: Rx0, Gx0 and Bx0
Note 4. ‘-‘ = Don't care - Can be set to VDDIO or DGND level
7.3.3.3 Write data for 18-bits/pixel (RGB 6-6-6-bits input), 262K-colours, 3AH=”06h”
RESX
‘1’
IM2
‘0’
IM1,IM0= “xx”
CSX
Pixel n
D8
SDA
1
D7
D6
D5
D4
D3
D2
R15 R14 R13 R12 R11 R10
D1
D0
D8
-
-
1
D7
D6
D5
D4
D3
D2
G15 G14 G13 G12 G11 G10
D1
D0
D8
-
-
1
D7
D6
D5
D4
D3
D2
B15 B14 B13 B12 B11 B10
D1
D0
-
-
SCL
18-bits
Frame
Memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1. pixel data with the 18-bits color depth information
Note 2. The most significant bits are: Rx5, Gx5 and Bx5
Note 3. The least significant bits are: Rx0, Gx0 and Bx0
Note 4. ‘-‘ = Don't care - Can be set to VDDIO or DGND level
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SPFD54124B
7.4. RGB interface
7.4.1.
General Description
The module uses 6, 16 and 18-bits parallel RGB interface which includes: VS, HS, DE, PCLK, D[17:0]. The interface is activated after
Power On sequence.
Pixel clock (PCLK) is running all the time without stoping and it is used to entering VS, HS, DE and D[17:0] states when there is a rising
edge of the PCLK. The PCLK cannot be used as continues internal clock for other functions of the display module e.g. Sleep In –mode etc.
Vertical synchronization (VS) is used to tell when there is received a new frame of the display. This is negative (‘0’, low) active and its state
is read to the display module by a rising edge of he PCLK signal.
Horizontal synchronization (HS) is used to tell when there is received a new line of the frame. This is negative (‘0’, low) active and its state
is read to the display module by a rising edge of the PCLK signal.
Data Enable (DE) is used to tell when there is received a RGB information that should be transferred on the display. This is a positive (‘1’,
high) active and its state is read to the display module by a rising edge of the PCLK signal.
D[17:0] (18-bit: R5-R0, G5-G0 and B5-B0; 16-bit: R4-R0, G5-G0 and B4-B0) are used to tell what is the information of the image that is
transferred on the display (When DE=’1’ and there is a rising edge of PCLK). D[17:0] can be ‘0’ (low) or ‘1’ (high). These lines are read by a
rising edge of the PCLK signal.
The PCLK cycle is described in the following figure.
PCLK
VS, HS, DE
D[17:0]
The host changes D[17:0], VS,
HS and DE lines when there is a
falling edge of the PCLK
The driver read the D[17:0], VS,
HS and DE lines when there is a
falling edge of the PCLK
Fig. 7.4.1 PCLK cycle
Note: PCLK is an unsynchronized signal (It can be stopped).
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7.4.2.
General Timing Diagram
Vertical Sync.
0 1
VS
Invisible Image
= Timing information what is not possible to see on the display
= Blanking Time
VBP
DE = ‘0’ (Low)
Visible Image
= Image which can see on the display
= Active
VP
DE = ‘1’ (high)
HDISP
VFP
Horizontal Sync.
1
0
HPW
HBP
HDISP
HFP
HP
Fig. 7.4.2 RGB General Timing diagram
The image information must be correct on the display, when the timings are in range on the interface.
However, the image information can be incorrect on the display, when timings are not out of range on the interface (Out of the range timings
cannot on the host side). The correct image information must be displayed automatically (by the display module) on the next frame (vertical
sync.) when there is returned from out of the range to in range interface timing.
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SPFD54124B
7.4.3.
Updating Order on Display Active Area (Normal Display Mode On + Sleep Out)
There is defined different kind of updating orders for display. These updating orders are controlled by H/W (SMX, SMY) and S/W (MX, MY,)
bits.
Physical
(0,0)
Point
Physical
(0,0)
Point
Start Point
(0,0)
Active areaa on the LCD
Active area on the LCD
Vertical
Active counter (0-161)
Vertical
Active counter (0-161)
End Point
(131,161)
Horizontal
Active counter (0-131)
End Point
(131,161)
Horizontal
Active counter (0-131)
Fig. 7.4.3.1 Updating order when MADCTL’s
MX=’0’ and MY = ‘0’
Fig. 7.4.3.2 Updating order when MADCTL’s
MX=’1’ and MY = ‘0’
Physical
(0,0)
Point
Physical
(0,0)
Point
Active area on the LCD
End Point
(131,161)
End Point
(0,0)
Active area on the LCD
Vertical
Active counter (0-161)
Vertical
Active counter (0-161)
Start Point
(0,0)
Start Point
(0,0)
Start Point
(131,161)
Horizontal
Active counter (0-131)
Horizontal
Active counter (0-131)
Fig. 7.4.3.3 Updating order when MADCTL’s
MX=’0’ and MY = ‘1’
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MX=’1’ and MY = ‘1’
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Table 7.4.3.1 Rules for Updating Order
Condition
An active VS signal is received
Signal Pixel information of the active area is received
An active HS signal between two active area lines
The Horizontal counter is larger than 127 and the Vertical counter is larger than 159
Note 1. Pixel order is RGB on the display.
Horizontal
Counter
Return to 0
Increment by 1
Return to 0
Return to 0
Vertical
Counter
Return to 0
No change
Increment by 1
Return to 0
Note 2. Data streaming direction from the host to the display is described in the following figure.
B
Data Stream from RGB I/F is like in this figure
Orisetech
E
Fig. 7.4.3.5 Data streaming order from RGB I/F
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SPFD54124B
7.4.4.
RGB Interface Bus Width set
All 4-kinds of bus width can be available during RGB interface mode (selected by COLMOD (3Ah) command for 8-bits, 16-bits and 18-bits
data width)
Table 7.4.4.1 RGB interface Bus Width Set Table
VIPF[3:0] D17 D16 D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Bus width
16-bits
data
18-bits
data
Bus width
0101
R4
R3
R2
R1
R0
x
G5
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
x
0110
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
D17 D16 D15 D14 D13 D12 D11 D10
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
D9
x
x
x
D8
x
x
x
D7
R5
G5
B5
D6
R4
G4
B4
D5
R3
G3
B3
D4
R2
G2
B2
D3
R1
G1
B1
D2
R0
G0
B0
D1
x
x
x
D0
x
x 6-bits data
x
VIPF[3:0]
1110
Note 1: When VIPF[3:0]=”1110”, 6-bits data width of 3-times transfer is used to transmit 1 pixel data with the 18-bits color depth information.
Note 2: Only VIPF[3:0]= ”0101”,”0110” and “1110” are valid on RGB I/F, Others are invalid.
Note 3. ‘x’ Don’t care, but need to set VDDIO or DGND level.
7.4.5.
RGB Interface Mode Set
Table 7.4.5.1 RGB Interface Mode Set
RGB I/F Mode
PCLK
DE
VS
HS
RGB Mode 1
RGB Mode 2
Used
Used
Used
Used
Used
Used
Used
Used
Video Data bus
D[17:0]
Used
Used
Register for Blanking
Porch setting
Not Used
Used
Reference clock for
Display
Internal Oscillator
Internal Oscillator
There are 2-kinds of RGB mode which is selected by RCM1 & RCM0 hardware pins.
In RGB Mode 1 (RCM1, RCM0 = “10”), writing data to frame memory is done by PCLK and Video Data Bus (D[17:0]), when DE is high
state. The external synchronization signals (PCLK, VS and HS) are used for internal display signals. So, controller (host) must always
transfer PCLK, VS, HS and DE signals to SPFD54124B.
In RGB Mode 2 (RCM1, RCM0 = “11”), blanking porch setting of VS and HS signals are defined by RGBBPCTR (B5h) command. When DE
pin is high, valid data is directly stored to frame memory.
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7.4.6.
RGB Interface Timing Diagram
7.4.6.1 General Timings for RGB I/F
TVSST
TVSST
VIH
VS
VIL
THSST
VIH
HS
THSHT
VIL
TPCLKCYC
PCLK
TVSHT
TPCLKHT
TPCLKLT
VIH
VIL
TDST/TDEST
D[17:0]
DE
TDHT/TDEHT
VIH
VIL
Fig. 7.4.6.1.1 General Timing for RGB I/F
Table 7.4.6.1.1 General Timing for RGB I/F
Item
Pixel low pulse width
Pixel high pulse width
Vertical Sync. set-up time
Vertical Sync. hold time
Horizontal Sync. set-up time
Horizontal Sync. hold time
Data Enable set-up time
Data Enable hold time
Data set-up time
Data hold time
Symbol
Condition
TPCLKLT
TPCLKHT
TVSST
TVSSHT
THSST
TVSSHT
TDEST
TDEHT
TDST
TDHT
Min
Specification
Type.
15
15
15
15
15
15
15
15
15
15
Max
Unit
ns
ns
ns
ns
Note 1: VDDIO=1.6 to 3.6V, VDD=2.6 to 3.6V, AGND=DGND=0V, Ta=-30 to 70℃ (to +85℃ no damage)
Note 2: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
Note 3. Data lines can be set to “High” or “Low” during blanking time – Don’t care.
Note 4. Logic high and low levels are specified as 30% and 70% of VDDIO for Input signals.
Note 5. HP is multiples of eight PCLK.
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N Frame
VS
N+1 Frame
N+2 Frame
HS
PCLK
DE *
DE **
Don’t care
Data Bus
Frame data
Frame data
Updating from
Data bus
Frame data
Updating from
SDA
Data transfer (ICM=’0’)
RAM write command (2Ch)
DE* : RGB Mode 1
DE** : RGB Mode 2
Address set command (2Ah), (2Bh)
Data transfer (ICM=’1’)
Fig. 7.4.6.1.2 RAM Access via SPI Interface in RGB Mode
Note: DP=’0’, EP=’0’, HSP=’0’ and VSP=’0’ of RGBCTR (B0h) command.
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7.4.6.2 RGB Interface Mode 1 Timing Diagram
1-Frame (TVP)
V Back Porch (TVS+TVBP)
VS
V Front Porch (TVFP)
HS
DE
1-Line (THP)
H Back Porch (THS+THBP)
HS
Valid data area (THDISP)
H Front Porch (THFP)
PCLK
DE
Data Bus
Latch data
In-Valid
In-Valid
D1 D2 D3 D4 D5
In-Valid
Dn
Dn
D1 D2 D3 D4 D5
RAM WEN
Fig. 7.4.6.2.1 RGB Mode 1 Timing Diagram
Note: DP=’0’, EP=’0’, HSP=’0’ and VSP=’0’ of RGBCTR (B0h) command.
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Vertical Timing for RGB I/F
VS
TVFP
D
[17:0]
TVS
TVBP
TVFP
Note 3
Note 3
TVBL
TDSIP
DE
TVP
HS
Horizontal Timing for RGB I/F
HS
THFP
THS
THBP
THDSIP
THFP
DE
THBL
D
[17:0]
Note 3
TPCLK
Note 3
THP
PCLK
Fig. 7.4.6.2.2 Vertical and Horizontal timing for RGB I/F
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Table 7.4.6.2.1 Vertical and Horizontal Timing for RGB I/F
Item
Symbol
Condition
Vertical cycle period
TVP
GM=”00” & “01”
GM=”10”
Vertical low pulse width
Vertical front porch
Vertical back porch
Vertical data start line
Vertical blanking period
TVS
TVFP
TVBP
Min
Specification
Type.
Max
Unit
Vertical Timing
TVBL
Vertical active area
TVDISP
Vertical refresh rate
Horizontal Timing
TVRR
Horizontal cycle period
THP
Horizontal low pulse width
Horizontal front porch
Horizontal back porch
TVS + TVBP
TVS + TVBP + TVFP
GM=”00” & “01”
GM=”10”
Frame rate
GM=”00” & “10”
GM=”01”
THS
THFP
THBP
THS + THBP
ffHS + fHBP
Horizontal data start point
Horizontal blanking period
Horizontal active area
Pixel clock cycle
THBL
THDISP
TPCLKCYC
fPCLKCYC
TPCLKCYC
fPCLKCYC
TPCLKCYC
fPCLKCYC
GM=”00” & “10”
GM=”01”
GM=”00”
TVRR=65Hz
GM=”01”
TVRR=65Hz
GM=”10”
TVRR=65Hz
166
134
2
2
2
4
6
61.75
172
140
4
4
4
8
12
160
152
2
2
2
30
1.0
32
68.25
Hz
745
745
256
256
256
766
160
128
65
HS
HS
HS
HS
HS
HS
HS
HS
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
µs
PCLK
PCLK
PCLK
ns
MHz
ns
MHz
ns
MHz
768
128
120
100
1.7
100
1.6
100
1.4
579
10
610
10
718
10
Note 1. VDDIO=1.6 to 3.6V, VDD=2.6 to 3.6V, AGND=DGND=0V, Ta=-30 to 70℃ (to +85℃ no damage)
Note 2. Data lines can be set to “High” or “Low” during blanking time – Don’t care.
Note 3. HP is multiples of eight PCLK.
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7.4.6.3 RGB Interface Mode 2 Timing Diagram
1-Frame (TVP)
V Back Porch (TVS+TVBP)
VS
V Front Porch (TVFP)
HS
DE
1-Line (THP)
H Back Porch (THS+THBP)
HS
Valid data area (THDISP)
H Front Porch (THFP)
PCLK
DE
Data Bus
Latch data
In-Valid
D1 D2 D3 D4 D5
In-Valid
In-Valid
Dn
Dn
D1 D2 D3 D4 D5
RAM WEN
Fig. 7.4.6.3.1 RGB Mode 2 Timing Diagram
1-Frame (TVP = 164Hs)
TVS+TVBP = 3Hs
VS
TVDISP= 160Hs
TVFP = 1Hs
HS
Line 1
Line 320
DE
Fig. 7.4.6.3.2 RGB Mode 2 Vertical Timing Diagram
Note: DP=’0’, EP=’0’, HSP=’0’ and VSP=’0’ of RGBCTR (B0h) command.
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-128xRGBx160
THP = 148 PCLK
THS+THBP = 10PCLK
HS
THDISP = 128PCLK
THFP = 10PCLK
PCLK
DE
Data Bus
In-Valid
D1 D2 D3 D4 D5
Dn
In-Valid
Fig. 7.4.6.3.3 RGB Mode 2 Horizontal Timing Diagram
Note: DP=’0’, EP=’0’, HSP=’0’ and VSP=’0’ of RGBCTR (B0h) command.
IDM
VS
Data Bus
Full-color mode
Idle mode
Full-color mode
Fig. 7.4.6.3.4 RGB Mode 2 Idle mode Timing Diagram
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Vertical Timing for RGB I/F
VS
TVFP
D
[17:0]
TVS
TVBP
TVFP
Note 3
Note 3
TVBL
TDSIP
DE
TVP
HS
Horizontal Timing for RGB I/F
HS
THFP
THS
THBP
THDSIP
THFP
DE
THBL
D
[17:0]
Note 3
TPCLK
Note 3
THP
PCLK
Fig. 7.4.6.3.5 Vertical and Horizontal timing for RGB I/F
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Table 7.4.6.3.1 Vertical and Horizontal Timing for RGB I/F
Item
Symbol
Min
Specification
Type.
GM=”00” & “01”
163
164
GM=”10”
131
132
Condition
Max
Unit
Vertical Timing
Vertical cycle period
TVP
Vertical low pulse width
Vertical front porch
Vertical back porch
Vertical data start line
Vertical blanking period
TVS
TVFP
TVBP
TVBL
Vertical active area
TVDISP
Vertical refresh rate
Horizontal Timing
TVRR
Horizontal cycle period
THP
Horizontal low pulse width
Horizontal front porch
Horizontal back porch
TVS + TVBP
TVS + TVBP + TVFP
GM=”00” & “01”
GM=”10”
Frame rate
GM=”00” & “10”
GM=”01”
THS
THFP
THBP
Horizontal data start point
Horizontal blanking period
Horizontal active area
Pixel clock cycle
THBL
THDISP
TPCLKCYC
fPCLKCYC
TPCLKCYC
fPCLKCYC
TPCLKCYC
fPCLKCYC
THS + THBP
ffHS + fHBP
THS + THBP + THFP
GM=”00” & “10”
GM=”01”
(GM=’0’)
(GM=’1’)
1
1
1
2
3
61.75
131
123
1
1
1
1
TBD
3
100
1.39
100
1.30
100
1.12
1
3
4
160
128
65
148
140
10
20
128
120
634
1.58
670
1.49
788
1.27
HS
HS
4
1023
1022
1023
1023
68.25
511
511
63
63
62
63
256
720
10
767
10
896
10
HS
HS
HS
HS
HS
HS
HS
Hz
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
µs
PCLK
PCLK
PCLK
Ns
MHz
Ns
MHz
Ns
MHz
Note 1. VDDIO=1.6 to 3.6V, VDD=2.6 to 3.6V, AGND=DGND=0V, Ta=-30 to 70℃ (to +85℃ no damage)
Note 2. Data lines can be set to “High” or “Low” during blanking time – Don’t care.
Note 3. HP is multiples of eight PCLK.
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SPFD54124B
7.4.6.4 Power On Sequence on RGB Mode 2
The Driver operates power up and display ON by VDD, VDDIO, SHUT, VS, HS, DE, PCLK on RGB mode 2 as show as following figure.
VDDIO
TVDD-VDDIO
VDD
RESX
SHUT
PCLK
TRS-SH
TVDD-SH
TPCLK -SH
HS
DE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VS
Host
Driver IC
Display High
Voltage
TSH-LCD
Display ON
Display OFF
Display
TSH-ON
Normal Display
Normal Display
Source Output
Blanking Display (Over 1 frame display)
VCOM Output
Normal Display
Gate Output
Internal Counter
Internal oscillator
Fig. 7.4.6.4.1 Power On Sequence on RGB Mode 2
Table 7.4.6.4.1 Power ON AC Characteristics
Characteristics
Symbol
Min
Typ
Max
Unit
Remark
VDDIO On to VDD On
TVDDIO-VDD
0
ns
Note1
VDDIO/VDD on to falling edge of SHUT
TVDD-SH
1
ms
RESX to falling of SHUT
TRS-SH
10
us
Signals input to falling edge of SHUT *
TCLK-SH
1
PCLK
Note2
Falling edge of SHUT to LCD power ON
TSH-LCD
120
ms
Falling edge of SHUT to Display start
TSH-ON
10
VS
Note 1: TVDDIO-VDD can be & lt; =0ns, & gt; 0ns. In any case, VDDIO and VDD power up sequence should not have any impact on the driver / display
functionalities / performance.
Note 2: Signals mean VS, HS, DE and PCLK signal.
Note 3: DP=’0’, EP=’0’, HSP=’0’ and VSP=’0’ of RGBCTR (B0h) command.
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SPFD54124B
7.4.6.5 Power OFF Sequence on RGB Mode 2
The Driver operates power off and display OFF by VDD, VDDIO, SHUT, VS, HS and DE on RGB mode 2 as show as following figure.
VDDIO
TVDD-VDDIO
VDD
RESX
SHUT
TOFF-VDD
PCLK
HS
TSH-OFF
DE
VS
Host
Driver IC
Display High
Voltage
Display ON
Display OFF
Display
Normal Display
Source Output
Normal Display
0V
VCOM Output
Normal Display
0V
Blanking Display (Over 1 frame display)
Gate Output
Internal Counter
Internal oscillator
Fig. 7.4.6.5.1 Power OFF Sequence on RGB Mode 2
Table 7.4.6.5.1 Power OFF AC Characteristics
Characteristics
Symbol
Min
Typ
Max
Unit
Remark
VDDIO On to VDD On
TVDDIO-VDD
0
ns
Note1
Signals input to VDDIO/VDD off
TSH-OFF
1
us
Note2
Rising edge of SHUT to Display off
TSH-OFF
2
VS
Note 1: TVDDIO-VDD can be & lt; =0ns, & gt; 0ns. In any case, VDDIO and VDD power up sequence should not have any impact on the driver / display
functionalities / performance.
Note 2: Signals mean VS, HS, DE and PCLK signal.
Note 3: DP=’0’, EP=’0’, HSP=’0’ and VSP=’0’ of RGBCTR (B0h) command.
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7.4.7.
RGB Data Color Coding
7.4.7.1 16-bits/pixel Colour Order on the RGB Interface
RESX
‘1’
RCM = ‘1’
RCMx
VS
‘1’
HS
‘1’
DE
‘1’
PCLK
D17, R4
R1, Bit 4
R2, Bit 4
R3, Bit 4
R4, Bit 4
R5, Bit 4
D16, R3
R1, Bit 3
R2, Bit 3
R3, Bit 3
R4, Bit 3
R5, Bit 3
D15, R2
R1, Bit 2
R2, Bit 2
R3, Bit 2
R4, Bit 2
R5, Bit 2
D14, R1
R1, Bit 1
R2, Bit 1
R3, Bit 1
R4, Bit 1
R5, Bit 1
D13, R0
R1, Bit 0
R2, Bit 0
R3, Bit 0
R4, Bit 0
R5, Bit 0
D12
-
-
-
-
-
D11, G5
G1, Bit 5
G2, Bit 5
G3, Bit 5
G4, Bit 5
G5, Bit 5
D10, G4
G1, Bit 4
G2, Bit 4
G3, Bit 4
G4, Bit 4
G5, Bit 4
D9, G3
G1, Bit 3
G2, Bit 3
G3, Bit 3
G4, Bit 3
G5, Bit 3
D8, G2
G1, Bit 2
G2, Bit 2
G3, Bit 2
G4, Bit 2
G5, Bit 2
D7, G1
G1, Bit 1
G2, Bit 1
G3, Bit 1
G4, Bit 1
G5, Bit 1
D6, G0
G1, Bit 0
G2, Bit 0
G3, Bit 0
G4, Bit 0
G5, Bit 0
D5, B4
B1, Bit 4
B2, Bit 4
B3, Bit 4
B4, Bit 4
B5, Bit 4
D4, B3
B1, Bit 3
B2, Bit 3
B3, Bit 3
B4, Bit 3
B5, Bit 3
D3, B2
B1, Bit 2
B2, Bit 2
B3, Bit 2
B4, Bit 2
B5, Bit 2
D2, B1
B1, Bit 1
B2, Bit 1
B3, Bit 1
B4, Bit 1
B5, Bit 1
D1, B0
B1, Bit 0
B2, Bit 0
B3, Bit 0
B4, Bit 0
B5, Bit 0
D0
-
-
-
-
-
Pixel n
Pixel n+1
Pixel n+2
Pixel n+3
Pixel n+4
16-bits
16-bits
16-bits
Look-Up Table for 65K-colors or data mapping (16-Bits to 18-Bits)
Frame
Memory
18-bits
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D23, LSB=D0 and picture data is MSB=Bit5, LSB=Bit0 for Green data and MSB=Bit4, LSB=Bit0
for Red and Blue data.
Note 2. ‘-’ Don’t care, but need set to VDDIO or DGND level.
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7.4.7.2 18-bits/pixel Colour Order on the RGB Interface
RESX
RCM
‘1’
IM1=’0’ / IM0=’0’
VS
‘1’
HS
‘1’
DE
‘1’
WRX
D17, R6
R1, Bit 5
R2, Bit 5
R3, Bit 5
R4, Bit 5
R5, Bit 5
D16, R5
R1, Bit 4
R2, Bit 4
R3, Bit 4
R4, Bit 4
R5, Bit 4
D15, R4
R1, Bit 3
R2, Bit 3
R3, Bit 3
R4, Bit 3
R5, Bit 3
D14, R3
R1, Bit 2
R2, Bit 2
R3, Bit 2
R4, Bit 2
R5, Bit 2
D13, R2
R1, Bit 1
R2, Bit 1
R3, Bit 1
R4, Bit 1
R5, Bit 1
D12, R1
R1, Bit 0
R2, Bit 0
R3, Bit 0
R4, Bit 0
R5, Bit 0
D11, G5
G1, Bit 5
G2, Bit 5
G3, Bit 5
G4, Bit 5
G5, Bit 5
D10, G4
G1, Bit 4
G2, Bit 4
G3, Bit 4
G4, Bit 4
G5, Bit 4
D9, G3
G1, Bit 3
G2, Bit 3
G3, Bit 3
G4, Bit 3
G5, Bit 3
D8, G2
G1, Bit 2
G2, Bit 2
G3, Bit 2
G4, Bit 2
G5, Bit 2
D7, G1
G1, Bit 1
G2, Bit 1
G3, Bit 1
G4, Bit 1
G5, Bit 1
D6, G0
G1, Bit 0
G2, Bit 0
G3, Bit 0
G4, Bit 0
G5, Bit 0
D5, B5
B1, Bit 5
B2, Bit 5
B3, Bit 5
B4, Bit 5
B5, Bit 5
D4, B4
B1, Bit 4
B2, Bit 4
B3, Bit 4
B4, Bit 4
B5, Bit 4
D3, B3
B1, Bit 3
B2, Bit 3
B3, Bit 3
B4, Bit 3
B5, Bit 3
D2, B2
B1, Bit 2
B2, Bit 2
B3, Bit 2
B4, Bit 2
B5, Bit 2
D1, B1
B1, Bit 1
B2, Bit 1
B3, Bit 1
B4, Bit 1
B5, Bit 1
D0, B0
B1, Bit 0
B2, Bit 0
B3, Bit 0
B4, Bit 0
B5, Bit 0
Pixel n
Frame
Memory
18-bit
Pixel n+1
18-bit
Pixel n+2
Pixel n+3
Pixel n+4
18-bit
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D23, LSB=D0 and picture data is MSB=Bit5, LSB=Bit0 for Red, Green and Blue data.
Note 2. ‘-’ Don’t care, but need set to VDDIO or DGND level.
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7.4.7.3 6-bits/pixel Colour Order on the RGB Interface
RESX
RCM
‘1’
IM1=’0’ / IM0=’0’
VS
‘1’
HS
‘1’
DE
‘1’
WRX
D17
-
-
-
-
-
D16
-
-
-
-
-
D9
-
-
-
-
-
D8
-
-
-
-
-
D7
R1, Bit 5
G1, Bit 5
B1, Bit 5
R2, Bit 5
G2, Bit 5
D6
R1, Bit 4
G1, Bit 4
B1, Bit 4
R2, Bit 4
G2, Bit 4
D5
R1, Bit 3
G1, Bit 3
B1, Bit 3
R2, Bit 3
G2, Bit 3
D4
R1, Bit 2
G1, Bit 2
B1, Bit 2
R1, Bit 2
G2, Bit 2
D3
R1, Bit 1
G1, Bit 1
B1, Bit 1
R2, Bit 1
G2, Bit 1
D2
R1, Bit 0
G1, Bit 0
B1, Bit 0
R2, Bit 0
G2, Bit 0
D1
-
-
-
-
-
D0
-
-
-
-
-
Pixel n
Pixel n+1
8-bit
Frame
Memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D17, LSB=D0 and picture data is MSB=Bit5, LSB=Bit0 for Red, Green and Blue data.
Note 2. ‘-’ Don’t care, but need set to VDDIO or DGND level.
© ORISE Technology Co., Ltd.
Proprietary & Confidential
160
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
7.5. Display Data RAM
7.5.1.
Configuration
The display module has an integrated 132x162x18-bit graphic type static RAM. This 384,912-bits memory allows to store on-chip a
132xRGBx162 image with an 18-bpp resolution (262K-color).
There will be no abnormal visible effect on the display when there is a simultaneous Panel Read
and interface Read or Write to the same location of the Frame Memory.
Display Data RAM Organization (GM=’00’)
LCD Glass
(128 x RGB x 160)
Latch
Look-up table
MPU
I/F
Display Data RAM
(128 x 160 x 18-bit)
Row
Address
Counter
Line
Address
Counter
Scan
Address
Counter
Column
Address
Counter
Host Interface
Fig. 7.5.1.1 Display Date RAM Organization
© ORISE Technology Co., Ltd.
Proprietary & Confidential
161
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
7.5.2.
Memory to Display Address Mapping
7.5.2.1 When using 128RGB x 160 resolution (GM1, GM0 = “00”, SMX=SMY=SRGB=’0’)
--------
S385 S386 S387 S388 S389 S390
RGB
Order
RGB=1
S12
Pixel 128
RGB=0
S11
Pixel 127
RGB=1
S10
--------
RGB=0
RA
S9
RGB=0
S8
RGB=1
S7
RGB=0
Gate Out Source Out
Pixel 2
RGB=1
Pixel 1
SA
MY=’0’ MY=’1’
ML=’0’ ML=’1’
2
0
159
0
159
3
1
158
--------
1
158
4
2
157
--------
2
157
5
3
156
--------
3
156
6
4
155
--------
4
155
7
5
154
--------
5
154
8
6
153
--------
6
153
9
7
152
--------
7
152
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
154
152
7
--------
152
7
155
153
6
--------
153
6
156
154
5
--------
154
5
157
155
4
--------
155
4
158
156
3
--------
156
3
159
157
2
--------
157
2
160
158
1
--------
158
1
161
159
0
--------
159
0
CA
R0
|
|
|
|
|
G0
|
|
|
|
|
B0
|
|
|
|
|
R1
|
|
|
|
|
G1
|
|
|
|
|
B1
|
|
|
|
|
--------
|
|
|
|
|
R126 G126 B126 R127 G127 B127
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
MX=’0’
0
1
--------
126
127
MX=’1’
127
126
--------
1
|
|
|
|
|
0
Note
RA = Row Address,
CA = Column Address
SA = Scan Address
MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command
MY = Mirror Y-axis (Column address direction parameter), D7 parameter of MADCTL command
MX =Scan direction parameter, D4 parameter of MADCTL command
RGB = Red, Green and Blue pixel position change, D3 parameter of MADCTL command
© ORISE Technology Co., Ltd.
Proprietary & Confidential
162
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
7.5.2.2 When using 120RGB x 160 resolution (GM1, GM0 = “01”, SMX=SMY=SRGB=’0’)
--------
S361 S362 S363 S364 S365 S366
RGB
Order
RGB=1
S12
Pixel 120
RGB=0
S11
Pixel 119
RGB=1
S10
--------
RGB=0
RA
S9
RGB=0
S8
RGB=1
S7
RGB=0
Gate Out Source Out
Pixel 2
RGB=1
Pixel 1
SA
MY=’0’ MY=’1’
ML=’0’ ML=’1’
2
0
159
0
159
3
1
158
--------
1
158
4
2
157
--------
2
157
5
3
156
--------
3
156
6
4
155
--------
4
155
7
5
154
--------
5
154
8
6
153
--------
6
153
9
7
152
--------
7
152
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
154
152
7
--------
152
7
155
153
6
--------
153
6
156
154
5
--------
154
5
157
155
4
--------
155
4
158
156
3
--------
156
3
159
157
2
--------
157
2
160
158
1
--------
158
1
161
159
0
--------
159
0
CA
R0
|
|
|
|
|
G0
|
|
|
|
|
B0
|
|
|
|
|
R1
|
|
|
|
|
G1
|
|
|
|
|
B1
|
|
|
|
|
--------
|
|
|
|
|
R118 G118 B118 R119 G119 B119
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
MX=’0’
0
1
--------
118
119
MX=’1’
119
118
--------
1
|
|
|
|
|
0
Note
RA = Row Address,
CA = Column Address
SA = Scan Address
MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command
MY = Mirror Y-axis (Column address direction parameter), D7 parameter of MADCTL command
MX =Scan direction parameter, D4 parameter of MADCTL command
RGB = Red, Green and Blue pixel position change, D3 parameter of MADCTL command
© ORISE Technology Co., Ltd.
Proprietary & Confidential
163
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
7.5.2.3 When using 128RGB x 128 resolution (GM1, GM0 = “10”, SMX=SMY=SRGB=’0’)
--------
S385 S386 S387 S388 S389 S390
RGB
Order
RGB=1
S12
Pixel 128
RGB=0
S11
Pixel 127
RGB=1
S10
--------
RGB=0
RA
S9
RGB=0
S8
RGB=1
S7
RGB=0
Gate Out Source Out
Pixel 2
RGB=1
Pixel 1
SA
MY=’0’ MY=’1’
ML=’0’ ML=’1’
2
0
127
0
127
3
1
126
--------
1
126
4
2
125
--------
2
125
5
3
124
--------
3
124
6
4
123
--------
4
123
7
5
122
--------
5
122
8
6
121
--------
6
121
9
7
120
--------
7
120
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
122
120
7
--------
120
7
123
121
6
--------
121
6
124
122
5
--------
122
5
125
123
4
--------
123
4
126
124
3
--------
124
3
127
125
2
--------
125
2
128
126
1
--------
126
1
129
127
0
--------
127
0
CA
R0
|
|
|
|
|
G0
|
|
|
|
|
B0
|
|
|
|
|
R1
|
|
|
|
|
G1
|
|
|
|
|
B1
|
|
|
|
|
--------
|
|
|
|
|
R126 G126 B126 R127 G127 B127
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
MX=’0’
0
1
--------
126
127
MX=’1’
127
126
--------
1
|
|
|
|
|
0
Note
RA = Row Address,
CA = Column Address
SA = Scan Address
MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command
MY = Mirror Y-axis (Column address direction parameter), D7 parameter of MADCTL command
MX =Scan direction parameter, D4 parameter of MADCTL command
RGB = Red, Green and Blue pixel position change, D3 parameter of MADCTL command
© ORISE Technology Co., Ltd.
Proprietary & Confidential
164
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
7.5.2.4 When using 132RGB x 162 resolution (GM1, GM0 = “11”, SMX=SMY=SRGB=’0’)
--------
S391 S392 S393 S394 S395 S396
RGB
Order
RGB=1
S6
Pixel 132
RGB=0
S5
Pixel 131
RGB=1
S4
--------
RGB=0
RA
S3
RGB=0
S2
RGB=1
S1
RGB=0
Gate Out Source Out
Pixel 2
RGB=1
Pixel 1
SA
MY=’0’ MY=’1’
ML=’0’ ML=’1’
1
0
161
0
161
2
1
160
--------
1
160
3
2
159
--------
2
159
4
3
158
--------
3
158
5
4
157
--------
4
157
6
5
156
--------
5
156
7
6
155
--------
6
155
8
7
154
--------
7
154
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
155
154
7
--------
154
7
156
155
6
--------
155
6
157
156
5
--------
156
5
158
157
4
--------
157
4
159
158
3
--------
158
3
160
159
2
--------
159
2
161
160
1
--------
160
1
162
161
0
--------
161
0
CA
R0
|
|
|
|
|
G0
|
|
|
|
|
B0
|
|
|
|
|
R1
|
|
|
|
|
G1
|
|
|
|
|
B1
|
|
|
|
|
--------
|
|
|
|
|
R130 G130 B130 R131 G131 B131
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
MX=’0’
0
1
--------
130
131
MX=’1’
131
130
--------
1
|
|
|
|
|
0
Note
RA = Row Address,
CA = Column Address
SA = Scan Address
MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command
MY = Mirror Y-axis (Column address direction parameter), D7 parameter of MADCTL command
MX =Scan direction parameter, D4 parameter of MADCTL command
RGB = Red, Green and Blue pixel position change, D3 parameter of MADCTL command
© ORISE Technology Co., Ltd.
Proprietary & Confidential
165
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
7.5.3.
Normal Display On or Partial Mode On, Vertical Scroll Off
7.5.3.1 When using 128RGB x 160 resolution (GM1, GM0 = “00”)
In this mode, contents of the frame memory within an area where column pointer is 00h to 7Fh and page pointer is 00h to 9Fh is displayed.
To display a dot on leftmost top corner, store the dot data at (column pointer, row pointer) = (0, 0).
(1) Example for Normal Display On (MX=MY=ML=’0’ ,SMX=SMY=’0’)
128 Columns
128 Columns
Scan
Order
160 Lines
00h 01h ---- ---- 76h 77h ---- 7Fh 83h
00h
01h
02h
|
|
|
|
|
|
|
|
|
|
|
9Eh
9Fh
A0h
A1h
00
10
20
30
40
50
60
01
11
21
31
41
51
0Y
0Y
2Y
3Y
4Y
5Y
0Z
0Z
2Z
3Z
4Z
4Z
6Z
128 x 160 x18 bit
Frame RAM
X0 X1 X2
XX XY XZ
Y0 Y1 Y2 Y3 YW YX YY YZ
Z0 Z1 Z2 Z3 ZW ZX ZY ZZ
1
2
3
|
|
|
|
|
|
|
|
|
|
158
159
160
00
10
20
30
40
50
60
01
11
21
31
41
51
02 03
12 13
22
32
42
0W 0X 0Y
1W 0X 0Y
2X 2Y
3X 3Y
4X 4Y
5Y
0Z G2
0Z G3
2Z G4
3Z |
4Z |
4Z |
6Z |
128 RGB x 160
LCD Panel
S0
U0 U1
V0 V1
W0 W1
X0 X1
Y0 Y1
Z0 Z1
V2
W2
X2
Y2 Y3
Z2 Z3
SZ
UY UZ
VX VY VZ
WX WY WZ
XX XY XZ
YW YX YY YZ
ZW ZX ZY ZZ
|
|
|
|
|
|
|
|
G159
G160
G161
Display area
=160 lines
(2). Example for Partial Display On (PSL[7:0]=04h,PEL[7:0]=9Bh, MX=MV=ML=’0’ ,SMX=SMY=’0’)
128 Columns
128 Columns
Scan
Order
160 Lines
00h 01h ---- ---- 76h 77h ---- 7Fh 83h
00h
01h
02h
|
|
|
|
|
|
|
|
|
|
|
9Eh
9Fh
A0h
A1h
00
10
20
30
40
50
60
01
11
21
31
41
51
0Y
0Y
2Y
3Y
4Y
5Y
0Z
0Z
2Z
3Z
4Z
4Z
6Z
128 x 160 x18 bit
Frame RAM
U0 U1
UY UZ
V0 V1 V2
VX VY VZ
W0 W1 W2
WX WY WZ
X0 X1 X2
XX XY XZ
Y0 Y1 Y2 Y3
YX YY YZ
Z0 Z1 Z2 Z3
ZX ZY ZZ
© ORISE Technology Co., Ltd.
Proprietary & Confidential
1
2
3
|
|
|
|
|
|
|
|
|
|
158
159
160
00
10
20
30
40
50
60
01
11
21
31
41
51
02 03
12 13
22
32
42
0W 0X 0Y
1W 0X 0Y
2X 2Y
3X 3Y
4X 4Y
5Y
0Z G2
0Z G3
2Z G4
3Z |
4Z |
4Z |
6Z |
128 RGB x 160
LCD Panel
S0
U0 U1
V0 V1
W0 W1
X0 X1
Y0 Y1
Z0 Z1
166
V2
W2
X2
Y2 Y3
Z2 Z3
SZ
UY UZ
VX VY VZ
WX WY WZ
XX XY XZ
YW YX YY YZ
ZW ZX ZY ZZ
|
|
|
|
|
|
|
|
G159
G160
G161
Non-Display
area =4 lines
Display area
=152 lines
Non-Display
area =4 lines
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
7.5.3.2 When using 120RGB x 160 resolution (GM1, GM0 = “01”)
In this mode, contents of the frame memory within an area where column pointer is 00h to 77h and page pointer is 00h to 9Fh is displayed.
To display a dot on leftmost top corner, store the dot data at (column pointer, row pointer) = (0, 0).
(1) Example for Normal Display On (MX=MY=ML=’0’, SMX=SMY=’0’)
120 Columns
120 Columns
Scan
Order
160 Lines
00h 01h ---- ---- 76h 77h ---- 81h 83h
00h
01h
02h
|
|
|
|
|
|
|
|
|
|
|
9Eh
9Fh
A0h
A1h
00
10
20
30
40
50
60
01 02
11 12
21 22
31
41
51
0Y 0Z
0Y 0Z
2Y 2Z
3Z
4Z
4Z
6Z
120 x 160 x18 bit
Frame RAM
W0 W1
X0 X1 X2
Y0 Y1 Y2
Z0 Z1 Z2
WZ
XY XZ
YY YZ
ZY ZZ
Unused
area
1
2
3
|
|
|
|
|
|
|
|
|
|
158
159
160
00
10
20
30
40
50
60
01 02
11 12
21 22
31
41
51
0Y 0Z
0Y 0Z
2Y 2Z
3Z
4Z
4Z
6Z
G2
G3
G4
|
|
|
|
|
120 RGB x 160
LCD Panel
Display area
=160 lines
|
S0
U0 U1
V0 V1
W0 W1
X0 X1 X2
Y0 Y1 Y2
Z0 Z1 Z2
SZ |
UZ |
VZ |
WZ |
XY XZ G159
YY YZ G160
ZY ZZ G161
(2) Example for Partial Display On (PSL[7:0]=04h,PEL[7:0]=9Bh, MX=MV=ML=’0’, SMX=SMY=’0’)
120 Columns
120 Columns
Scan
Order
160 Lines
00h 01h ---- ---- 76h 77h ---- 81h 83h
00h
01h
02h
|
|
|
|
|
|
|
|
|
|
|
9Eh
9Fh
A0h
A1h
00
10
20
30
40
50
60
01 02
11 12
21 22
31
41
51
0Y 0Z
0Y 0Z
2Y 2Z
3Z
4Z
4Z
6Z
120 x 160 x18 bit
Frame RAM
U0 U1
UZ
V0 V1
VZ
W0 W1
WZ
X0 X1 X2
XY XZ
Y0 Y1 Y2
YY YZ
Z0 Z1 Z2
ZY ZZ
© ORISE Technology Co., Ltd.
Proprietary & Confidential
Unused
area
1
2
3
|
|
|
|
|
|
|
|
|
|
158
159
160
00
10
20
30
40
50
60
01 02
11 12
21 22
31
41
51
0Y 0Z
0Y 0Z
2Y 2Z
3Z
4Z
4Z
6Z
G2
G3
G4
|
|
|
|
|
120 RGB x 160
LCD Panel
Non-Display
area =4 lines
Display area
=152 lines
|
S0
U0 U1
V0 V1
W0 W1
X0 X1 X2
Y0 Y1 Y2
Z0 Z1 Z2
167
SZ |
UZ |
VZ |
WZ |
XY XZ G159
YY YZ G160
ZY ZZ G161
Non-Display
area =4 lines
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
7.5.3.3 When using 128RGB x 128 resolution (GM1, GM0 = “10”)
In this mode, contents of the frame memory within an area where column pointer is 00h to 7Fh and page pointer is 000h to 07Fh is
displayed.
To display a dot on leftmost top corner, store the dot data at (column pointer, row pointer) = (0, 0).
(1) Example for Normal Display On (MX=MY=ML=’0’ ,SMX=SMY=’0’)
128 Columns
128 Columns
Scan
Order
Scan
Order
128 Lines
00h 01h ---- ---- ---- ---- 7Eh 7Fh 83h
000h
001h
002h
|
|
|
|
7Dh
7Eh
7Fh
00
10
20
30
01 02
0Y 0Z
11 12
1Y 1Z
21
2Z
31
128 x 128 x18 bit
Frame RAM
W0
X0 X1
Y0 Y1 Y2
Z0 Z1 Z2
XZ
YY YZ
ZY ZZ
00 01 02
10 11 12
30 31
40
128 RGB x 128
LCD Panel
X0 X1
20 21
Y0 Y1 Y2
Z0 Z1 Z2
1
2
3
|
|
|
|
126
127
128
0Y 0Z
1Y 1Z
2Z
3Z
WZ
XZ
YY YZ
ZY ZZ
G2
G3
G4
|
|
|
|
G127
G128
G129
Display area
=128 lines
Unused area
A1h
(2) Example for Partial Display On (PSL[7:0]=03h,PEL[7:0]=7Ah, MX=MV=ML=’0’ ,SMX=SMY=’0’)
128 Columns
128 Columns
Scan
Order
Scan
Order
128 Lines
00h 01h ---- ---- ---- ---- 7Eh 7Fh 83h
00h
01h
02h
|
|
|
|
7Dh
7Eh
7Fh
00
10
20
30
01 02
0Y
11 12
1Y
21
31
128 x 128 x18 bit
Frame RAM
W0
X0 X1
Y0 Y1 Y2
Z0 Z1 Z2
0Z
1Z
2Z
3Z
WZ
XZ
YY YZ
ZY ZZ
00 01 02
10 11 12
30 31
40
128 RGB x 128
LCD Panel
X0 X1
20 21
Y0 Y1 Y2
Z0 Z1 Z2
1
2
3
|
|
|
|
126
127
128
0Y 0Z
1Y 1Z
2Z
3Z
WZ
XZ
YY YZ
ZY ZZ
G2
G3
G4
|
|
|
|
G127
G128
G129
Non-Display
area =3 lines
Display area
=122 lines
Non-Display
area =3 lines
Unused area
A1h
© ORISE Technology Co., Ltd.
Proprietary & Confidential
168
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
7.5.3.4 When using 132RGB x 162 resolution (GM1, GM0 = “11”)
In this mode, contents of the frame memory within an area where column pointer is 00h to 83h and page pointer is 00h to A1h is displayed.
To display a dot on leftmost top corner, store the dot data at (column pointer, row pointer) = (0, 0).
(1) Example for Normal Display On (MX=MY=ML=’0’ ,SMX=SMY=’0’)
132 Columns
132 Columns
Scan
Order
162 Lines
00h 02h ---- ---- ---- ---- 79h 81h 83h
00h
01h
02h
|
|
|
|
|
|
|
|
|
|
|
|
9Fh
A0h
A1h
00
10
20
30
40
50
60
01
11
21
31
41
51
02 03
12 13
22
32
42
0W 0X 0Y
1W 0X 0Y
2X 2Y
3X 3Y
4X 4Y
5Y
0Z
0Z
2Z
3Z
4Z
4Z
6Z
132 x 162 x18 bit
Frame RAM
S0
U0 U1
V0 V1
W0 W1
X0 X1
Y0 Y1
Z0 Z1
V2
W2
X2
Y2 Y3
Z2 Z3
SZ
UY UZ
VX VY VZ
WX WY WZ
XX XY XZ
YW YX YY YZ
ZW ZX ZY ZZ
00
10
20
30
40
50
60
1
2
3
|
|
|
|
|
|
|
|
|
|
|
|
160
161
162
01
11
21
31
41
51
02 03
12 13
22
32
42
0W 0X 0Y
1W 0X 0Y
2X 2Y
3X 3Y
4X 4Y
5Y
0Z G1
0Z G2
2Z G3
3Z |
4Z |
4Z |
6Z |
132 RGB x 162
LCD Panel
S0
U0 U1
V0 V1
W0 W1
X0 X1
Y0 Y1
Z0 Z1
V2
W2
X2
Y2 Y3
Z2 Z3
SZ
UY UZ
VX VY VZ
WX WY WZ
XX XY XZ
YW YX YY YZ
ZW ZX ZY ZZ
|
|
|
|
|
|
|
|
G160
G161
G162
Display area
=162 lines
(2) Example for Partial Display On (PSL[7:0]=04h,PEL[7:0]=9Dh, MX=MV=ML=’0’ ,SMX=SMY=’0’)
132 Columns
132 Columns
Scan
Order
162 Lines
00h 02h ---- ---- ---- ---- 79h 81h 83h
00h
01h
02h
|
|
|
|
|
|
|
|
|
|
|
|
9Fh
A0h
A1h
00
10
20
30
40
50
60
01
11
21
31
41
51
02 03
12 13
22
32
42
0W 0X 0Y
1W 0X 0Y
2X 2Y
3X 3Y
4X 4Y
5Y
0Z
0Z
2Z
3Z
4Z
4Z
6Z
132 x 162 x18 bit
Frame RAM
S0
U0 U1
V0 V1
W0 W1
X0 X1
Y0 Y1
Z0 Z1
V2
W2
X2
Y2 Y3
Z2 Z3
© ORISE Technology Co., Ltd.
Proprietary & Confidential
SZ
UY UZ
VX VY VZ
WX WY WZ
XX XY XZ
YW YX YY YZ
ZW ZX ZY ZZ
00
10
20
30
40
50
60
1
2
3
|
|
|
|
|
|
|
|
|
|
|
|
160
161
162
01
11
21
31
41
51
02 03
12 13
22
32
42
0W 0X 0Y
1W 0X 0Y
2X 2Y
3X 3Y
4X 4Y
5Y
0Z G1
0Z G2
2Z G3
3Z |
4Z |
4Z |
6Z |
132 RGB x 162
LCD Panel
S0
U0 U1
V0 V1
W0 W1
X0 X1
Y0 Y1
Z0 Z1
169
V2
W2
X2
Y2 Y3
Z2 Z3
SZ
UY UZ
VX VY VZ
WX WY WZ
XX XY XZ
YW YX YY YZ
ZW ZX ZY ZZ
|
|
|
|
|
|
|
|
G160
G161
G162
Non-Display
area =4 lines
Display area
=154 lines
Non-Display
area =4 lines
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
7.5.4.
Vertical Scroll Mode
There is vertical scrolling, which are determined by the commands “Vertical Scrolling Definition” (33h) and “Vertical Scrolling Start Address”
(37h).
T FA
T FA
V SA
V SA
B FA
B FA
O riginal
Scrolling
Fig. 7.5.4.1 Difference between Scrolling and original
© ORISE Technology Co., Ltd.
Proprietary & Confidential
170
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
7.5.4.1 When using 128RGB x 160 resolution (GM1, GM0 = “00”)
When Vertical Scrolling Definition Parameters (TFA+VSA+BFA)=160. In this case, scrolling is applied as shown below.
(1) Example for TFA =3, VSA=155, BFA=2, SSA=4, ML=0: Scrolling
128 Columns
128 Columns
Scan
Order
160 Lines
00h 01h ---- ---- 76h 77h ---- 7Fh 83h
00h
01h
02h
|
|
|
|
|
|
|
|
|
|
|
9Eh
9Fh
A0h
A1h
00
10
20
30
40
50
60
01
11
21
31
41
51
0Y
0Y
2Y
3Y
4Y
5Y
0Z
0Z
2Z
3Z
4Z
4Z
6Z
128 x 160 x18 bit
Frame RAM
X0 X1 X2
XX XY XZ
Y0 Y1 Y2 Y3 YW YX YY YZ
Z0 Z1 Z2 Z3 ZW ZX ZY ZZ
1
2
3
|
|
|
|
|
|
|
|
|
|
158
159
160
00
10
20
40
50
60
01
11
21
41
51
02 03
12 13
22
42
0W 0X 0Y
1W 0X 0Y
2X 2Y
4X 4Y
5Y
0Z G2
0Z G3
2Z G4
4Z |
4Z |
6Z |
128 RGB x 160
LCD Panel
S0
U0 U1
V0 V1
W0 W1
X0 X1
30 31
Y0 Y1
Z0 Z1
V2
W2
X2
32
Y2 Y3
Z2 Z3
SZ
UY UZ
VX VY VZ
WX WY WZ
XX XY XZ
3X 3Y 3Z
YW YX YY YZ
ZW ZX ZY ZZ
|
|
|
|
|
|
|
|
|
G159
G160
G161
TFA
VSA
BFA
(2) Example for TFA =3, VSA=155, BFA=2, SSA=4, ML=1: Scrolling: TFA and BFT are exchanged
128 Columns
128 Columns
Scan
Order
160 Lines
00h 01h ---- ---- 76h 77h ---- 7Fh 83h
00h
01h
02h
|
|
|
|
|
|
|
|
|
|
|
9Eh
9Fh
A0h
A1h
00
10
20
30
40
50
60
01
11
21
31
41
51
0Y
0Y
2Y
3Y
4Y
5Y
0Z
0Z
2Z
3Z
4Z
4Z
6Z
128 x 160 x18 bit
Frame RAM
V0
VZ
W0 W1
WY WZ
X0 X1 X2
XX XY XZ
Y0 Y1 Y2 Y3 YW YX YY YZ
Z0 Z1 Z2 Z3 ZW ZX ZY ZZ
© ORISE Technology Co., Ltd.
Proprietary & Confidential
160
159
158
|
|
|
|
|
|
|
|
|
|
3
2
1
00 01 02 03
0W 0X
10 11 12 13
1W 0X
W0 W1
20 21
30 31
40 41
50 51
60
128 RGB x 160
LCD Panel
S0
U0
V0
X0
Y0
Z0
171
U1
X1 X2
Y1 Y2 Y3
Z1 Z2 Z3
0Y 0Z G2
0Y 0Z G3
WY WZ G4
2Y 2Z |
3Y 3Z |
4Y 4Z |
5Y 4Z |
6Z |
SZ
UY UZ
VZ
XX XY XZ
YW YX YY YZ
ZW ZX ZY ZZ
|
|
|
|
|
|
|
G159
G160
G161
BFA
VSA
TFA
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
7.5.4.2 When using 120RGB x 160 resolution (GM1, GM0 = “01”)
When Vertical Scrolling Definition Parameters (TFA+VSA+BFA)=160. In this case, scrolling is applied as shown below.
(1) Example for TFA =3, VSA=155, BFA=2, SSA=4, ML=0: Scrolling
120 Columns
120 Columns
Scan
Order
160 Lines
00h 01h ---- ---- 76h 77h ---- 81h 83h
00h
01h
02h
|
|
|
|
|
|
|
|
|
|
|
9Eh
9Fh
A0h
A1h
00
10
20
30
40
50
60
01 02
11 12
21 22
31
41
51
0Y 0Z
0Y 0Z
2Y 2Z
3Z
4Z
4Z
6Z
120 x 160 x18 bit
Frame RAM
W0 W1
X0 X1 X2
Y0 Y1 Y2
Z0 Z1 Z2
WZ
XY XZ
YY YZ
ZY ZZ
Unused
area
1
2
3
|
|
|
|
|
|
|
|
|
|
158
159
160
00
10
20
40
50
60
01 02
11 12
21 22
41
51
0Y 0Z
0Y 0Z
2Y 2Z
4Z
4Z
6Z
G2
G3
G4
|
|
|
|
|
120 RGB x 160
LCD Panel
S0
U0 U1
V0 V1
W0 W1
X0 X1 X2
30 31
Y0 Y1 Y2
Z0 Z1 Z2
SZ |
UZ |
VZ |
WZ |
XY XZ |
3Z G159
YY YZ G160
ZY ZZ G161
TFA
VSA
BFA
(2) Example for TFA =2, VSA=155, BFA=3, SSA=4, ML=1: Scrolling: TFA and BFT are exchanged
120 Columns
120 Columns
Scan
Order
160 Lines
00h 01h ---- ---- 76h 77h ---- 81h 83h
00h
01h
02h
|
|
|
|
|
|
|
|
|
|
|
9Eh
9Fh
A0h
A1h
00
10
20
30
40
50
60
01 02
11 12
21 22
31
41
51
0Y 0Z
0Y 0Z
2Y 2Z
3Z
4Z
4Z
6Z
120 x 160 x18 bit
Frame RAM
V0 V1
W0 W1
X0 X1 X2
Y0 Y1 Y2
Z0 Z1 Z2
© ORISE Technology Co., Ltd.
Proprietary & Confidential
VY VZ
WZ
XY XZ
YY YZ
ZY ZZ
Unused
area
160
159
158
|
|
|
|
|
|
|
|
|
|
3
2
1
00 01 02
0Y 0Z G2
10 11 12
0Y 0Z G3
W0 W1
WZ G4
20 21 22
2Y 2Z |
30 31
3Z |
40 41
4Z |
50 51
4Z |
60
6Z |
120 RGB x 160
LCD Panel
S0
U0
V0
X0
Y0
Z0
172
U1
V1
X1 X2
Y1 Y2
Z1 Z2
VY
XY
YY
ZY
SZ
UZ
VZ
XZ
YZ
ZZ
|
|
|
|
|
G159
G160
G161
TFA
VSA
BFA
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
7.5.4.3 When using 128RGB x 128 resolution (GM1, GM0 = “10”)
When Vertical Scrolling Definition Parameters (TFA+VSA+BFA)=128. In this case, scrolling is applied as shown below.
(1) Example for TFA =2, VSA=124, BFA=2, SSA=3, ML=0: Scrolling
128 Columns
128 Columns
Scan
Order
128 Lines
00h 01h ---- ---- ---- ---- 7Eh 7Fh 83h
000h
001h
002h
|
|
|
|
7Dh
7Eh
7Fh
00
10
20
30
01 02
0Y 0Z
11 12
1Y 1Z
21
2Z
31
128 x 128 x18 bit
Frame RAM
W0
X0 X1
Y0 Y1 Y2
Z0 Z1 Z2
XZ
YY YZ
ZY ZZ
00 01 02
10 11 12
30 31
40
128 RGB x 128
LCD Panel
X0 X1
20 21
Y0 Y1 Y2
Z0 Z1 Z2
1
2
3
|
|
|
|
126
127
128
0Y 0Z
1Y 1Z
3Z
4Z
XZ
2Z
YY YZ
ZY ZZ
G2
G3
G4
|
|
|
|
G127
G128
G129
TFA
VSA
BFA
Unused area
A1h
(2) Example for TFA =2, VSA=124, BFA=2, SSA=4, ML=1: Scrolling: TFA and BFT are exchanged
128 Columns
128 Columns
Scan
Order
128 Lines
00h 01h ---- ---- ---- ---- 7Eh 7Fh 83h
000h
001h
002h
|
|
|
|
7Dh
7Eh
7Fh
00
10
20
30
W0
X0
Y0
Z0
01 02
0Y 0Z
11 12
1Y 1Z
21
2Z
31
128 x 128 x18 bit
Frame RAM
WZ
X1
XZ
Y1 Y2
YY YZ
Z1 Z2
ZY ZZ
00
10
X0
20
01 02
0Y 0Z
11 12
1Y 1Z
X1
XZ
21
2Z
128 RGB x 128
LCD Panel
V0 V1
VZ
W0
WZ
Y0 Y1 Y2
YY YZ
Z0 Z1 Z2
ZY ZZ
128
127
126
|
|
|
|
3
2
1
G2
G3
G4
|
|
|
|
G127
G128
G129
BFA
VSA
TFA
Unused area
A1h
© ORISE Technology Co., Ltd.
Proprietary & Confidential
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APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
7.5.4.4 When using 132RGB x 162 resolution (GM1, GM0 = “11”)
When Vertical Scrolling Definition Parameters (TFA+VSA+BFA)=162. In this case, scrolling is applied as shown below.
(1) Example for TFA =3, VSA=157, BFA=2, SSA=4, ML=0: Scrolling
132 Columns
132 Columns
Scan
Order
162 Lines
00h 02h ---- ---- ---- ---- 79h 81h 83h
00h
01h
02h
|
|
|
|
|
|
|
|
|
|
|
|
9Fh
A0h
A1h
00
10
20
30
40
50
60
01
11
21
31
41
51
02 03
12 13
22
32
42
0W 0X 0Y
1W 0X 0Y
2X 2Y
3X 3Y
4X 4Y
5Y
0Z
0Z
2Z
3Z
4Z
4Z
6Z
132 x 162 x18 bit
Frame RAM
S0
U0 U1
V0 V1
W0 W1
X0 X1
Y0 Y1
Z0 Z1
V2
W2
X2
Y2 Y3
Z2 Z3
SZ
UY UZ
VX VY VZ
WX WY WZ
XX XY XZ
YW YX YY YZ
ZW ZX ZY ZZ
1
2
3
|
|
|
|
|
|
|
|
|
|
|
|
160
161
162
00
10
20
40
50
60
70
SSA
01
11
21
41
51
02 03
12 13
22
42
0W 0X 0Y
1W 0X 0Y
2X 2Y
4X 4Y
5Y
0Z G1
0Z G2
2Z G3
4Z |
4Z |
6Z |
7Z |
132 RGB x 162
LCD Panel
S0
U0 U1
V0 V1 V2
W0 W1 W2
X0 X1 X2
30 31 32
Y0 Y1 Y2 Y3
Z0 Z1 Z2 Z3
SZ
UY UZ
VX VY VZ
WX WY WZ
XX XY XZ
3X 3Y 3Z
YW YX YY YZ
ZW ZX ZY ZZ
|
|
|
|
|
|
|
|
G160
G161
G162
TFA
VSA
BFA
(2) Example for TFA =3, VSA=157, BFA=2, SSA=4, ML=1: Scrolling: TFA and BFT are exchanged
132 Columns
132 Columns
Scan
Order
162 Lines
00h 02h ---- ---- ---- ---- 79h 81h 83h
00h
01h
02h
|
|
|
|
|
|
|
|
|
|
|
|
9Fh
A0h
A1h
00
10
20
30
40
50
60
01
11
21
31
41
51
02 03
12 13
22
32
42
0W 0X 0Y
1W 0X 0Y
2X 2Y
3X 3Y
4X 4Y
5Y
0Z 162
0Z 161
2Z 160
3Z |
4Z |
4Z |
6Z |
132 x 162 x18 bit
Frame RAM
S0
U0 U1
V0 V1
W0 W1
X0 X1
Y0 Y1
Z0 Z1
V2
W2
X2
Y2 Y3
Z2 Z3
© ORISE Technology Co., Ltd.
Proprietary & Confidential
SZ
UY UZ
VX VY VZ
WX WY WZ
XX XY XZ
YW YX YY YZ
ZW ZX ZY ZZ
|
|
|
|
|
|
|
|
3
2
1
00 01 02 03
0W 0X 0Y 0Z G1
10 11 12 13
1W 0X 0Y 0Z G2
W0 W1 W2
WX WY WZ G3
20 21 22
2X 2Y 2Z |
30 31 32
3X 3Y 3Z |
40 41 42
4X 4Y 4Z |
50 51
5Y 4Z |
60
6Z |
|
132 RGB x 162
LCD Panel
|
S0
U0
V0
X0
Y0
Z0
SSA
174
U1
V1
X1
Y1
Z1
V2
X2
Y2 Y3
Z2 Z3
VX
XX
YW YX
ZW ZX
UY
VY
XY
YY
ZY
SZ
UZ
VZ
XZ
YZ
ZZ
|
|
|
|
|
G160
G161
G162
BFA
VSA
TFA
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
7.5.5.
Vertical Scroll Example
7.5.5.1 Vertical Scroll Example (GM1, GM0 = “00” & GM1, GM0=”01”)
There are 2 types of vertical scrolling, which are determined by the commands “ Vertical Scrolling Definition” (33h) and “Vertical Scrolling
Start Address” (37h).
Case 1: TFA + VSA + BFA≠160
N/A. Do not set TFA + VSA + BFA≠160. In that case, unexpected picture will be shown.
Case 2: TFA + VSA + BFA=160 (Scrolling)
Example1) When MADCTR parameter ML=”0”, TFA=0, VSA=160, BFA=0 and VSCSAD=80.
Physical Line
Pointer
Memory Physical Axis
(0,0)
Display
Axis (0,0)
2
1
VSCSAD
1
2
Display
Frame
Memory
Increment
Physical Line
Pointer
Display
Axis (0,0)
2
1
1
2
VSCSAD
Display
Frame
Memory
Example2) When MADCTR parameter ML=”1”, TFA=30, VSA=130, BFA=0 and VSCSAD=80.
Physical Line
Memory Physical Axis
(0,0)
Display
Axis (0,0)
Pointer
2
3
3
2
VSCSAD
TFA
1
1
TFA
Frame
Memory
Display
Increment
Physical Line
Memory Physical Axis
(0,0)
Pointer
Display
Axis (0,0)
2
3
VSCSAD
3
Frame
Memory
© ORISE Technology Co., Ltd.
Proprietary & Confidential
2 1
1
TFA
TFA
Display
175
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
7.5.5.2 Vertical Scroll Example (GM1, GM0 = “10”)
There are 2 types of vertical scrolling, which are determined by the commands “ Vertical Scrolling Definition” (33h) and “Vertical Scrolling
Start Address” (37h).
Case 1: TFA + VSA + BFA≠128
N/A. Do not set TFA + VSA + BFA≠128. In that case, unexpected picture will be shown.
Case 2: TFA + VSA + BFA=128 (Scrolling)
Example1) When MADCTR parameter ML=”0”, TFA=0, VSA=128, BFA=0 and VSCSAD=40.
Physical Line
Pointer
Memory Physical Axis
(0,0)
Display
Axis (0,0)
2
1
VSCSAD
1
2
Display
Frame
Memory
Increment
Physical Line
Pointer
Display
Axis (0,0)
2
1
1
2
VSCSAD
Display
Frame
Memory
Example2) When MADCTR parameter ML=”1”, TFA=30, VSA=98, BFA=0 and VSCSAD=40.
Physical Line
Memory Physical Axis
(0,0)
Display
Axis (0,0)
Pointer
2
3
3
2
VSCSAD
TFA
1
1
TFA
Frame
Memory
Display
Increment
Physical Line
Memory Physical Axis
(0,0)
Pointer
Display
Axis (0,0)
2
3
VSCSAD
3
Frame
Memory
© ORISE Technology Co., Ltd.
Proprietary & Confidential
2 1
1
TFA
TFA
Display
176
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
7.5.5.3 Vertical Scroll Example (GM1, GM0 = “11”)
There are 2 types of vertical scrolling, which are determined by the commands “ Vertical Scrolling Definition” (33h) and “Vertical Scrolling
Start Address” (37h).
Case 1: TFA + VSA + BFA≠162
N/A. Do not set TFA + VSA + BFA≠162. In that case, unexpected picture will be shown.
Case 2: TFA + VSA + BFA=162 (Scrolling)
Example1) When MADCTR parameter ML=”0”, TFA=0, VSA=162, BFA=0 and VSCSAD=40.
Physical Line
Pointer
Memory Physical Axis
(0,0)
Display
Axis (0,0)
2
1
VSCSAD
1
2
Display
Frame
Memory
Increment
Physical Line
Pointer
Display
Axis (0,0)
2
1
1
2
VSCSAD
Display
Frame
Memory
Example2) When MADCTR parameter ML=”1”, TFA=30, VSA=132, BFA=0 and VSCSAD=40.
Physical Line
Memory Physical Axis
(0,0)
Display
Axis (0,0)
Pointer
2
3
3
2
VSCSAD
TFA
1
1
TFA
Frame
Memory
Display
Increment
Physical Line
Memory Physical Axis
(0,0)
Pointer
Display
Axis (0,0)
2
3
VSCSAD
3
Frame
Memory
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1
TFA
TFA
Display
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7.6. Address Counter
The address counter sets the addresses of the display data RAM for writing and reading.
Data is written pixel-wise into the RAM matrix of DRIVER. The data for one pixel or two pixels is collected (RGB 8-8-8-bit), according to the
data formats. As soon as this pixel-data information is complete the “Write access” is activated on the RAM. The locations of RAM are
addressed by the address pointers. The address ranges are X=0 to X=128 (7Fh) and Y=0 to Y=160 (9Fh). Addresses outside these ranges
are not allowed. Before writing to the RAM a window must be defined into which will be written. The window is programmable via the
command registers XS, YS designating the start address and XE, YE designating the end address.
For example the whole display contents will be written, the window is defined by the following values: XS=0 (0h) YS=0 (0h) and XE=128
(7Fh), YE=160 (9Fh).
In vertical addressing mode (MV=1), the Y-address increments after each byte, after the last Y-address (Y=YE), Y wraps around to YS and
X increments to address the next column. In horizontal addressing mode (V=0), the X-address increments after each byte, after the last
X-address (X=XE), X wraps around to XS and Y increments to address the next row. After the every last address (X=XE and Y=YE) the
address pointers wrap around to address (X=XS and Y=YS).
For flexibility in handling a wide variety of display architectures, the commands “CASET, RASET” and “MADCTR” , define flags MX and MY,
which allows mirroring of the X-address and Y-address. All combinations of flags are allowed. Fig. 8.2.3 show the available combinations of
writing to the display RAM. When MX, MY and MV will be changed the data bust be rewritten to the display RAM.
For each image condition, the controls for the column and row counters apply as Fig. 7.6.1 below:
Condition
Column Counter
Complete Pixel Read / Write action
The Column counter value is larger than “End Column (XE)”
The Column counter value is larger than “End Column (XE)” and the Row
counter value is larger than “End Row (YE)”
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Return to “Start Row
(YS)”
Increment by 1
When RAMWR/RAMRD command is accepted
Row Counter
Return to “Start
Column (XS)”
No change
Return to “Start
Column (XS)”
Return to “Start
Column (XS)”
Increment by 1
Return to “Start Row
(YS)”
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Preliminary Version: 0.6
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7.7. Memory Data Write/ Read Direction
The data is written in the order illustrated above. The Counter which dictates where in the physical memory the data is to be written is
controlled by “Memory Data Access Control” Command, bits B5 (MV), B6 (MX), B7 (MY) as described below.
B
Data Stream order is like in this figure
Orisetech
E
Fig. 7.7.1 Data streaming order
-When 128RGBx160 (GM=’00’)
MADCTR
(36h)
MV
MX
Virtual to Physical Pointer translator
RASET (2Bh)
Physical Row
Pointer
MY
CASET (2Ah)
Physical Column
Pointer
Virtual (0,0) when
MV=don’t care,
MX=’0’, MY=’0’
(0,0)
(127,0)
Physical
axes
(0,159)
(127,159)
Virtual (0,0)
when MV=don’t care,
MX=’0’, MY=’1’
MV
0
0
0
0
1
1
1
1
MX
0
0
1
1
0
0
1
1
MV
0
1
0
1
0
1
0
1
CASET
Direct to Physical Column Pointer
Direct to Physical Column Pointer
Direct to (127-Physical Column Pointer)
Direct to (127-Physical Column Pointer)
Direct to Physical Row Pointer
Direct to (159-Physical Row Pointer)
Direct to Physical Row Pointer
Direct to (159-Physical Row Pointer)
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Virtual (0,0)
when MV=don’t care,
MX=’1’, MY=’0’
Virtual (0,0)
when MV=don’t care,
MX=’1’, MY=’1’
RASET
Direct to Physical Row Pointer
Direct to (159-Physical Row Pointer)
Direct to Physical Row Pointer
Direct to (159-Physical Row Pointer)
Direct to Physical Column Pointer
Direct to Physical Column Pointer
Direct to (127-Physical Column Pointer)
Direct to (127-Physical Column Pointer)
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-When 120RGBx160 (GM=’01’)
MADCTR
(36h)
MV
MX
Virtual to Physical Pointer translator
RASET (2Bh)
Physical Row
Pointer
MY
CASET (2Ah)
Physical Column
Pointer
Virtual (0,0) when
MV=don’t care,
MX=’0’, MY=’0’
(0,0)
(119,0)
Physical
axes
(0,159)
(119,159)
Virtual (0,0)
when MV=don’t care,
MX=’0’, MY=’1’
MV
0
0
0
0
1
1
1
1
MX
0
0
1
1
0
0
1
1
MV
0
1
0
1
0
1
0
1
Virtual (0,0)
when MV=don’t care,
MX=’1’, MY=’0’
CASET
Direct to Physical Column Pointer
Direct to Physical Column Pointer
Direct to (119-Physical Column Pointer)
Direct to (119-Physical Column Pointer)
Direct to Physical Row Pointer
Direct to (159-Physical Row Pointer)
Direct to Physical Row Pointer
Direct to (159-Physical Row Pointer)
Virtual (0,0)
when MV=don’t care,
MX=’1’, MY=’1’
RASET
Direct to Physical Row Pointer
Direct to (159-Physical Row Pointer)
Direct to Physical Row Pointer
Direct to (159-Physical Row Pointer)
Direct to Physical Column Pointer
Direct to Physical Column Pointer
Direct to (119-Physical Column Pointer)
Direct to (119-Physical Column Pointer)
-When 128RGBx128 (GM=’10’)
MADCTR
(36h)
MV
MX
Virtual to Physical Pointer translator
RASET (2Bh)
Physical Row
Pointer
MY
CASET (2Ah)
Physical Column
Pointer
Virtual (0,0) when
MV=don’t care,
MX=’0’, MY=’0’
(0,0)
(127,0)
Physical
axes
(0,127)
(127,127)
Virtual (0,0)
when MV=don’t care,
MX=’0’, MY=’1’
MV
0
0
0
0
1
1
1
1
MX
0
0
1
1
0
0
1
1
MV
0
1
0
1
0
1
0
1
CASET
Direct to Physical Column Pointer
Direct to Physical Column Pointer
Direct to (127-Physical Column Pointer)
Direct to (127-Physical Column Pointer)
Direct to Physical Row Pointer
Direct to (127-Physical Row Pointer)
Direct to Physical Row Pointer
Direct to (127-Physical Row Pointer)
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Virtual (0,0)
when MV=don’t care,
MX=’1’, MY=’0’
Virtual (0,0)
when MV=don’t care,
MX=’1’, MY=’1’
RASET
Direct to Physical Row Pointer
Direct to (127-Physical Row Pointer)
Direct to Physical Row Pointer
Direct to (127-Physical Row Pointer)
Direct to Physical Column Pointer
Direct to Physical Column Pointer
Direct to (127-Physical Column Pointer)
Direct to (127-Physical Column Pointer)
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-When 132RGBx162 (GM=’11’)
MADCTR
(36h)
MV
MX
Virtual to Physical Pointer translator
RASET (2Bh)
Physical Row
Pointer
MY
CASET (2Ah)
Physical Column
Pointer
Virtual (0,0) when
MV=don’t care,
MX=’0’, MY=’0’
(0,0)
(131,0)
Physical
axes
(0,161)
(131,161)
Virtual (0,0)
when MV=don’t care,
MX=’0’, MY=’1’
MV
0
0
0
0
1
1
1
1
MX
0
0
1
1
0
0
1
1
MV
0
1
0
1
0
1
0
1
Virtual (0,0)
when MV=don’t care,
MX=’1’, MY=’0’
CASET
Direct to Physical Column Pointer
Direct to Physical Column Pointer
Direct to (131-Physical Column Pointer)
Direct to (131-Physical Column Pointer)
Direct to Physical Row Pointer
Direct to (161-Physical Row Pointer)
Direct to Physical Row Pointer
Direct to (161-Physical Row Pointer)
Virtual (0,0)
when MV=don’t care,
MX=’1’, MY=’1’
RASET
Direct to Physical Row Pointer
Direct to (161-Physical Row Pointer)
Direct to Physical Row Pointer
Direct to (161-Physical Row Pointer)
Direct to Physical Column Pointer
Direct to Physical Column Pointer
Direct to (131-Physical Column Pointer)
Direct to (131-Physical Column Pointer)
Note: Data is always written to the Frame Memory in the same order, regardless of the Memory Write Direction set by MADCTL bits B7
(MY), B6 (MX), B5 (MV). The write order for each pixel unit is
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
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Frame Data Write Direction According to the MADCTR parameters (MV, MX and MY)
Display Data
Direction
Normal
MADCTR
Parameter
Image in the Driver
(DDRAM)
Image in the Host
(MPU)
MV MX MY
0
0
0
H/W position (0,0)
B
B
F
Y-Mirror
0
0
1
0
1
0
H/W position (0,0)
X-Y Exchange
0
1
1
0
0
X-Y Exchange
X-Mirror
X-Y Exchange
X-Mirror
Y-Mirror
1
0
1
1
0
1
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1
B
E
E
E
H/W position (0,0)
E
B
X-Y address (0,0)
X: RASET
Y: CASET
B
B
H/W position (0,0)
H/W position (0,0)
F
X-Y address (0,0)
X: RASET
Y: CASET
E
E
B
X-Y address (0,0)
X: CASET
Y: RASET
B
X-Y address (0,0)
X: RASET
Y: CASET
B
X-Y address (0,0)
X: CASET
Y: RASET
E
B
H/W position (0,0)
F
1
B
E
B
E
E
E
H/W position (0,0)
F
1
E
B
F
X-Y Exchange
Y-Mirror
X-Y address (0,0)
X: CASET
Y: RASET
H/W position (0,0)
F
1
E
B
F
X-Mirror
Y-Mirror
E
B
F
X-Mirror
F
X-Y address (0,0)
X: CASET
Y: RASET
E
E
B
182
X-Y address (0,0)
X: RASET
Y: CASET
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7.8. Tearing Effect Output Line
The Tearing Effect output line supplies to the MPU a Panel synchronization signal. This signal can be enabled or disabled by the Tearing
Effect Line Off & On commands. The mode of the Tearing Effect signal is defined by the parameter of the Tearing Effect Line On command.
The signal can be used by the MPU to synchronize Frame Memory Writing when displaying video images.
7.8.1.
Tearing Effect Line Modes
Mode 1, the Tearing Effect Output signal consists of V-Blanking Information only:
t vdl
t vdh
tvdl
tvdh
Vertical T im e Scale
tvdh= The LCD display is not updated from the Frame Memory
tvdl= The LCD display is updated from the Frame Memory (except Invisible Line – see below)
Mode 2, the Tearing Effect Output signal consists of V-Blanking and H-Blanking Information, there is one V-sync and 162 H-sync pulses per
field.
t hd l
t h dh
thdl
thdh
V-Sync
V-Sync
Invisible
Line
1 st Line
2 nd Line
161 st Line
162 nd Line
thdh= The LCD display is not updated from the Frame Memory
thdl= The LCD display is updated from the Frame Memory (except Invisible Line – see above)
Bottom Line
T op Line
2
nd
Line
T E (M ode2)
T E (M ode1)
t vdh
tvdh
Note: During Sleep In Mode, the Tearing Output Pin is active Low.
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7.8.2.
Tearing Effect Line Timings
The Tearing Effect signal is described below:
t vdl
tvdl
tvdh
t vdh
Vertical T im ing
H orizontal T im ing
t hd l
thdl
thdh
t hd h
Table 7.8.1 AC characteristics of Tearing Effect Signal Idle Mode Off (Frame Rate = 60 Hz)
Symbol
Parameter
min
max
unit
tvdl
Vertical Timing Low Duration
13
-
ms
tvdh
Vertical Timing High Duration
1000
-
μs
thdl
Horizontal Timing Low Duration
33
-
μs
thdh
Horizontal Timing High Duration
25
500
description
μs
NOTE: The timings in Table 7.8.1 apply when MADCTR ML=0 and ML=1
The signal’s rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns.
Input Signal Slope
Output Signal Slope
TR
TF
TR
VIH=0.7*VDDIO
VIL=0.3*VDDIO
TF
VOH=0.8*VDDIO
VOL=0.2*VDDIO
TR=TF & lt; = 15ns
TR=TF & lt; = 15ns
Fig. 7.1.2 Rising and Falling timing for Input and Output signal
The Tearing Effect Output Line is fed back to the MPU and should be used as shown below to avoid Tearing Effect:
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7.8.3.
Example 1: MPU Write is faster than panel read.
M CU to
M em ory
1
st
162
tim e
nd
TE Output
Signal
tim e
M em ory to
LCD
Im age on LCD
1
st
162
a
b
c
nd
tim e
d
Data write to Frame Memory is now synchronized to the Panel Scan. It should be written during the vertical sync pulse of the Tearing Effect
Output Line. This ensures that data is always written ahead of the panel scan and each Panel Frame refresh has a complete new image:
Data to be sent
B
a
Im age on LCD
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b
c
d
A A B B
B
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7.8.4.
Example 2: MPU write is slower than panel read.
M CU to
M em ory
1
st
16 2
tim e
nd
TE Output
Signal
tim e
M em ory to
LCD
Im age on LCD
1
a
st
16 2
b
nd
c
tim e
d
f
e
The MPU to Frame Memory write begins just after Panel Read has commenced i.e. after one horizontal sync pulse of the Tearing Effect
Output Line. This allows time for the image to download behind the Panel Read pointer and finishing download during the subsequent
Frame before the Read Pointer “catches” the MPU to Frame memory write position.
Data to be sent
B
a
Im age on LCD
b
c
d
e
f
AA A A AB
B
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7.9. Preset Values
ORISETECH has already set all preset values in SPFD54124B. Any of these preset values do not need customer’s SW support.
7.10. Power ON/OFF Sequence
VDDIO and VDD can be applied in any order.
VDDIO and VDD can be powered down in any order.
During power off, if LCD is in the Sleep Out mode, VDD and VDDIO must be powered down minimum 120msec after RESX has been
released.
During power off, if LCD is in the Sleep In mode, VDDIO or VDD can be powered down minimum 0msec after RESX has been released.
CSX can be applied at any timing or can be permanently grounded. RESX has priority over CSX.
Note 1: There will be no damage to the display module if the power sequences are not met.
Note 2: There will be no abnormal visible effects on the display panel during the Power On/Off Sequences.
Note 3: There will be no abnormal visible effects on the display between end of Power On Sequence and before receiving Sleep Out
command. Also between receiving Sleep In command and Power Off Sequence.
If RESX line is not held stable by host during Power On Sequence, then it will be necessary to apply a Hardware Reset (RESX) after Host
Power On Sequence is complete to ensure correct operation. Otherwise function is not guaranteed.
The power on/off sequence is illustrated below:
7.10.1. Case 1 – RESX Line is held High or Unstable by Host at Power On
If RESX line is held High or unstable by the host during Power On, then a Hardware Reset must be applied after both VDD and VDDIO
have been applied – otherwise correct functionality is not guaranteed. There is no timing restriction upon this hardware reset.
TrPW = +/- no limit
tfPW
=
+/- no limit
VDD1
VDDIO
VDD2
VDD
Time when the latter signal rises up to 90% of its Typical Value.
e.g. When VDD2 comes later, This time is defined at the cross point
of 90% of 2.5V/2.75V, not 90% of 2.3V.
2.75V,not 90% of
Time when the former signal falls down to 90% of its Typical Value.
e.g. When VDD2 falls earlier, This time is defined at the cross point
of 90% of 2.5V/2.75V, not 90% of 2.3V.
2.75V,not 90% of
tfPW!CS = +/- no limit
CSX
trPW!CS = +/- no limit
CSX
CSX
!CS
H or L
trPW!RES = + no limit
RESX
RESX
!RES
(Power down in
Sleep Out mode)
RESX
!RES
30%
tfPW!RES1 = min.120ms
RESX1
trPW!RES = + no limit
RES
30%
tfPW!RES2 = min.0ns
RESX2
(Power down in
Sleep In mode)
tfPW!RES1
RESX
TfpwRESX1 is applied to !RES falling in the Sleep Out Mode.
tfPW!RES2
TfpwRESX2 is applied to !RES falling in the Sleep In Mode.
RESX
Note: Unless otherwise specified, timings herein show cross point at 50% of signal/power level.
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7.10.2. Case 2 – RESX Line is Held Low by Host at Power On
If RESX line is held Low (and stable) by the host during Power On, then the RESX must be held low for minimum 10µsec after both VDD
and VDDIO have been applied.
TrPW = +/- no limit
tfPW
=
+/- no limit
VDD1
VDDIO
VDD2
VDD
Time when the latter signal rises up to 90% of its Typical Value.
e.g. When VDD2 comes later, This time is defined at the cross point
of 90% of 2.5V/2.75V, not 90% of 2.3V.
2.75V,not 90% of
Time when the former signal falls down to 90% of its Typical Value.
e.g. When VDD2 falls earlier, This time is defined at the cross point
2.75V,not 90% 90% of 2.3V.
of 90% of 2.5V/2.75V, notof
CSX
tfPW!CS = +/- no limit
trPW!CS = +/- no limit
CSX
CSX
!CS
H or L
RESX
trPW!RES = min.10µs
!RES
RESX
(Power down in
Sleep Out mode)
RESX1
tfPW!RES1 = min.120ms
RESX
trPW!RES = min.10µs
!RES
RESX
RESX2
tfPW!RES2 = min.0ns
(Power down in
Sleep In mode)
tfPW!RES1
!RES
TfpwRESX1 is applied to RESX falling in the Sleep Out Mode.
TfpwRESX2 is applied to RESX falling in the Sleep In Mode.
tfPW!RES2
!RES
Note: Unless otherwise specified, timings herein show cross point at 50% of signal/power level.
7.10.3. Uncontrolled Power Off
The uncontrolled power off means a situation when e.g. there is removed a battery without the controlled power off sequence. There will not
be any damages for the display module or the display module will not cause any damages for the host or lines of the interface.
At an uncontrolled power off the display will go blank and there will not be any visible effects within (TBD) second on the display (blank
display) and remains blank until “Power On Sequence” powers it up.
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7.11. Power Level Definition
7.11.1. Power Level
6 level modes are defined they are in order of Maximum Power consumption to Minimum Power Consumption:
1. Normal Mode On (full display), Idle Mode Off, Sleep Out.
In this mode, the display is able to show maximum 262,144 colors.
2. Partial Mode On, Idle Mode Off, Sleep Out.
In this mode part of the display is used with maximum 262,144 colors.
3. Normal Mode On (full display), Idle Mode On, Sleep Out.
In this mode, the full display area is used but with 8 colors.
4. Partial Mode On, Idle Mode On, Sleep Out.
In this mode, part of the display is used but with 8 colors.
5. Sleep In Mode
In this mode, the DC: DC converter, Internal oscillator and panel driver circuit are stopped. Only the MCU interface and memory works
with VDDIO power supply. Contents of the memory are safe.
6. Power Off Mode
In this mode, both VDD and VDDIO are removed.
Note: Transition between modes 1-5 is controllable by MCU commands. Mode 6 is entered only
when both Power supplies are removed.
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7.11.2. Power Flow Chart
Normal display mode on = NORON
Partial mode on = PTLON
Idle mode off = IDMOFF
Power on sequence
HW reset
SW reset
Idle mode on = IDMON
Sleep out = SLPOUT
Sleep in = SLPIN
NORON
NORON
SLPIN
Sleep out
Normal display mode on
Idle mode off
PTLON
IDMON
SLPOUT
IDMOFF
Sleep in
Normal display mode on
Idle mode off
IDMON
PTLON
IDMOFF
SLPIN
Sleep out
Normal display mode on
Idle mode on
SLPOUT
Sleep in
Normal display mode on
Idle mode on
SLPIN
Sleep out
Partial mode on
Idle mode off
IDMON
IDMOFF
PTLON
NORON
Sleep in
Partial mode on
Idle mode off
SLPOUT
IDMON
IDMOFF
PTLON
SLPIN
Sleep out
Partial mode on
Idle mode on
SLPOUT
Sleep out
Sleep in
Partial mode on
Idle mode on
NORON
Sleep in
Note 1: There is not any abnormal visual effect when there is changing from one power mode to another power mode.
Note 2: There is not any limitation, which is not specified by this spec, when there is changing from one power mode to another power
mode.
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7.12. Gamma Curves
Gamma Curve
1.0
0.9
0.8
Gamma = 1.0
0.7
Gamma = 2.5
0.6
Gamma = 2.2
Y 0.5
Gamma = 1.8
0.4
0.3
0.2
Optical Gamma Curve according to the GC0 to GC3 bit
0.1
0.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
X
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7.13. Reset
7.13.1. Reset Value
7.13.1.1 Reset Table (Default Value, GM=00, 128RGB x 160)
Item
Frame memory
Sleep In/Out
Display On/Off
Display mode (normal/partial)
Display Inversion On/Off
Display Idle Mode On/Off
Column: Start Address (XS)
Row: Start Address (YS)
0000h
0000h
Row: End Address (YE)
009Fh
009Fh
GC0
See Section 6.14
0000h
009Fh
Off
0000h
00A0h
0000h
0000h
Off
0 (Mode1)
GC0
See Section 6.14
0000h
009Fh
Off
0000h
00A0h
0000h
0000h
Off
0 (Mode1)
After Software Reset
No Change
In
Off
Normal
Off
Off
0000h
007Fh (127d) (when MV=0)
009Fh (159d) (when MV=1)
0000h
009Fh (159d) (when MV=0)
007Fh (127d) (when MV=1)
GC0
No Change
0000h
009Fh
Off
0000h
00A0h
0000h
0000h
Off
0 (Mode1)
0/0/0/0/0
0/0/0/0/0
No Change
6 (18-Bit/Pixel)
08h
00h
6 (18-Bit/Pixel)
00h
00h
00h
38h
NV Value
NV Value
6 (18-Bit/Pixel)
08h
00h
6 (18-Bit/Pixel)
00h
00h
00h
38h
NV Value
NV Value
No Change
08h
No Change
No Change
00h
00h
00h
38h
NV Value
NV Value
Column: End Address (XE)
Gamma setting
RGB for 256, 4k and 65k Color Mode
Partial: Start Address (PSL)
Partial: End Address (PEL)
Scroll: Vertical scrolling
Scroll: Top Fixed Area (TFA)
Scroll: Scroll Area (VSA)
Scroll: Bottom Fixed Area (BFA)
Scroll Start Address (SSA)
Tearing: On/Off
Tearing Effect Mode *3)
Memory Data Access Control
(MY/MX/MV/ML/RGB)
Interface Pixel Color Format
RDDPM
RDDMADCTR
RDDCOLMOD
RDDIM
RDDSM
RDDSDR
ID1
ID2
ID3
After Power On
Random
In
Off
Normal
Off
Off
0000h
After Hardware Reset
No Change
In
Off
Normal
Off
Off
0000h
007Fh
007Fh
Notes 1. There will be no abnormal visible effects on the display when S/W or H/W Reset is applied.
Notes:2. Powered-On Reset finishes within 10µs after both VDD & VDDIO are applied.
Notes:3. TE Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only.
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Preliminary Version: 0.6
Preliminary
SPFD54124B
7.13.1.2 Reset Table (GM=01, 120RGB x 160)
Item
Frame memory
Sleep In/Out
Display On/Off
Display mode (normal/partial)
Display Inversion On/Off
Display Idle Mode On/Off
Column: Start Address (XS)
Column: End Address (XE)
0077h
0077h
Row: Start Address (YS)
0000h
0000h
Row: End Address (YE)
009Fh
009Fh
GC0
See Section 6.14
0000h
009Fh
Off
0000h
00A0h
0000h
0000h
Off
0 (Mode1)
GC0
See Section 6.14
0000h
009Fh
Off
0000h
00A0h
0000h
0000h
Off
0 (Mode1)
After Software Reset
No Change
In
Off
Normal
Off
Off
0000h
0077h (119d) (when MV=0)
009Fh (159d) (when MV=1)
0000h
009Fh (159d) (when MV=0)
0077h (119d) (when MV=1)
GC0
No Change
0000h
009Fh
Off
0000h
00A0h
0000h
0000h
Off
0 (Mode1)
0/0/0/0/0
0/0/0/0/0
No Change
6 (18-Bit/Pixel)
08h
00h
6 (18-Bit/Pixel)
00h
00h
00h
NV Value
NV Value
NV Value
6 (18-Bit/Pixel)
08h
00h
6 (18-Bit/Pixel)
00h
00h
00h
NV Value
NV Value
NV Value
No Change
08h
No Change
No Change
00h
00h
00h
NV Value
NV Value
NV Value
Gamma setting
RGB for 256, 4k and 65k Color Mode
Partial: Start Address (PSL)
Partial: End Address (PEL)
Scroll: Vertical scrolling
Scroll: Top Fixed Area (TFA)
Scroll: Scroll Area (VSA)
Scroll: Bottom Fixed Area (BFA)
Scroll Start Address (SSA)
Tearing: On/Off
Tearing Effect Mode *3)
Memory Data Access Control
(MY/MX/MV/ML/RGB)
Interface Pixel Color Format
RDDPM
RDDMADCTR
RDDCOLMOD
RDDIM
RDDSM
RDDSDR
ID1
ID2
ID3
After Power On
Random
In
Off
Normal
Off
Off
0000h
After Hardware Reset
No Change
In
Off
Normal
Off
Off
0000h
Notes 1. There will be no abnormal visible effects on the display when S/W or H/W Reset is applied.
Notes:2. Powered-On Reset finishes within 10µs after both VDD & VDDIO are applied.
Notes:3. TE Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only.
© ORISE Technology Co., Ltd.
Proprietary & Confidential
193
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Preliminary Version: 0.6
Preliminary
SPFD54124B
7.13.1.3 Reset Table (GM=10, 128RGB x 128)
Item
Frame memory
Sleep In/Out
Display On/Off
Display mode (normal/partial)
Display Inversion On/Off
Display Idle Mode On/Off
Column: Start Address (XS)
After Power On
Random
In
Off
Normal
Off
Off
0000h
After Hardware Reset
No Change
In
Off
Normal
Off
Off
0000h
Column: End Address (XE)
007Fh
007Fh
Row: Start Address (YS)
0000h
0000h
Row: End Address (YE)
007Fh
007Fh
GC0
See Section 6.14
0000h
007Fh
Off
0000h
0080h
0000h
0000h
Off
0 (Mode1)
GC0
See Section 6.14
0000h
007Fh
Off
0000h
0080h
0000h
0000h
Off
0 (Mode1)
After Software Reset
No Change
In
Off
Normal
Off
Off
0000h
007Fh (127d) (when MV=0)
007Fh (127d) (when MV=1)
0000h
007Fh (127d) (when MV=0)
007Fh (127d) (when MV=1)
GC0
No Change
0000h
007Fh
Off
0000h
0080h
0000h
0000h
Off
0 (Mode1)
0/0/0/0/0
0/0/0/0/0
No Change
6 (18-Bit/Pixel)
08h
00h
6 (18-Bit/Pixel)
00h
00h
00h
38h
NV Value
NV Value
6 (18-Bit/Pixel)
08h
00h
6 (18-Bit/Pixel)
00h
00h
00h
38h
NV Value
NV Value
No Change
08h
No Change
No Change
00h
00h
00h
38h
NV Value
NV Value
Gamma setting
RGB for 256, 4k and 65k Color Mode
Partial: Start Address (PSL)
Partial: End Address (PEL)
Scroll: Vertical scrolling
Scroll: Top Fixed Area (TFA)
Scroll: Scroll Area (VSA)
Scroll: Bottom Fixed Area (BFA)
Scroll Start Address (SSA)
Tearing: On/Off
Tearing Effect Mode *3)
Memory Data Access Control
(MY/MX/MV/ML/RGB)
Interface Pixel Color Format
RDDPM
RDDMADCTR
RDDCOLMOD
RDDIM
RDDSM
RDDSDR
ID1
ID2
ID3
Notes 1. There will be no abnormal visible effects on the display when S/W or H/W Reset is applied.
Notes:2. Powered-On Reset finishes within 10µs after both VDD & VDDIO are applied.
Notes:3. TE Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only.
© ORISE Technology Co., Ltd.
Proprietary & Confidential
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Preliminary Version: 0.6
Preliminary
SPFD54124B
7.13.1.4 Reset Table (GM=11, 132RGB x 162)
Item
Frame memory
Sleep In/Out
Display On/Off
Display mode (normal/partial)
Display Inversion On/Off
Display Idle Mode On/Off
Column: Start Address (XS)
Column: End Address (XE)
0083h
0083h
Row: Start Address (YS)
0000h
0000h
Row: End Address (YE)
00A1h
00A1h
GC0
See Section 6.14
0000h
00A1h
Off
0000h
00A2h
0000h
0000h
Off
0 (Mode1)
GC0
See Section 6.14
0000h
00A1h
Off
0000h
00A2h
0000h
0000h
Off
0 (Mode1)
After Software Reset
No Change
In
Off
Normal
Off
Off
0000h
0083h (131d) (when MV=0)
00A1h (161d) (when MV=1)
0000h
00A1h (161d) (when MV=0)
0083h (131d) (when MV=1)
GC0
No Change
0000h
00A1h
Off
0000h
00A2h
0000h
0000h
Off
0 (Mode1)
0/0/0/0/0
0/0/0/0/0
No Change
6 (18-Bit/Pixel)
08h
00h
6 (18-Bit/Pixel)
00h
00h
00h
38h
NV Value
NV Value
6 (18-Bit/Pixel)
08h
00h
6 (18-Bit/Pixel)
00h
00h
00h
38h
NV Value
NV Value
No Change
08h
No Change
No Change
00h
00h
00h
38h
NV Value
NV Value
Gamma setting
RGB for 256, 4k and 65k Color Mode
Partial: Start Address (PSL)
Partial: End Address (PEL)
Scroll: Vertical scrolling
Scroll: Top Fixed Area (TFA)
Scroll: Scroll Area (VSA)
Scroll: Bottom Fixed Area (BFA)
Scroll Start Address (SSA)
Tearing: On/Off
Tearing Effect Mode *3)
Memory Data Access Control
(MY/MX/MV/ML/RGB)
Interface Pixel Color Format
RDDPM
RDDMADCTR
RDDCOLMOD
RDDIM
RDDSM
RDDSDR
ID1
ID2
ID3
After Power On
Random
In
Off
Normal
Off
Off
0000h
After Hardware Reset
No Change
In
Off
Normal
Off
Off
0000h
Notes 1. There will be no abnormal visible effects on the display when S/W or H/W Reset is applied.
Notes:2. Powered-On Reset finishes within 10µs after both VDD & VDDIO are applied.
Notes:3. TE Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only.
© ORISE Technology Co., Ltd.
Proprietary & Confidential
195
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
7.13.2. Module Input/Output Pins
7.13.2.1 Output or Bi-directional (I/O) Pins
Output or Bi-directional pins
After Power On
After Hardware Reset
After Software Reset
TE
Low
Low
Low
D7 to D0 (Output driver)
High-Z (Inactive)
High-Z (Inactive)
High-Z (Inactive)
Note: There will be no output from D7-D0 during Power On/Off sequence, Hardware Reset and Software Reset.
7.13.2.2 Input Pins
Input pins
During Power On
Process
After Power On
After Hardware
Reset
After Software
Reset
During Power Off
Process
RESX
See 6.10
Input valid
Input valid
Input valid
See 6.10
CSX
Input invalid
Input valid
Input valid
Input valid
Input invalid
D/CX
Input invalid
Input valid
Input valid
Input valid
Input invalid
WRX
Input invalid
Input valid
Input valid
Input valid
Input invalid
RDX
Input invalid
Input valid
Input valid
Input valid
Input invalid
D7 to D0
Input invalid
Input valid
Input valid
Input valid
Input invalid
P/SX
Input invalid
Input valid
Input valid
Input valid
Input invalid
© ORISE Technology Co., Ltd.
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Preliminary Version: 0.6
Preliminary
SPFD54124B
7.13.3. Reset Timing
Shorter than 5µs
tRESW
!RES
RESX
tREST
Internal Status
Initial Condition
(Default for H/W reset)
Resetting
Normal Operation
Table 7.13.3.1 Reset input timing
VSS=0V, VDDIO=1.6V to 3.6V, VDD=2.6V to 3.6V,Ta = -30 to 70°C)
Symbol
Parameter
Related Pins
MIN
TYP
MAX
tRESW
*1) Reset low pulse width
RESX
10
-
-
tREST
-
-
5
-
120
*2) Reset complete time
-
Note
Unit
-
µs
When reset applied during
Sleep in mode
When reset applied during
Sleep out mode
ms
ms
Note 1) Spike due to an electrostatic discharge on RESX line does not cause irregular system reset according to the table below.
RESX Pulse
Action
Shorter than 5µs
Reset Rejected
Longer than 10µs
Reset
Between 5µs and 10µs
Reset starts
(It depends on voltage and temperature condition.)
Note 2. During the resetting period, the display will be blanked (The display is entering blanking sequence, which maximum time is 120 ms,
when Reset Starts in Sleep Out –mode. The display remains the blank state in Sleep In –mode) and then return to Default condition
for H/W reset.
Note 3. During Reset Complete Time, ID2 and VCOMOF value in OTP will be latched to internal register during this period. This loading is
done every time when there is H/W reset complete time (tREST) within 5ms after a rising edge of RESX.
Note 4. Spike Rejection also applies during a valid reset pulse as shown below:
10µs
Reset is accepted
10µs
Note 5. It is necessary to wait 5msec after releasing RESX before sending commands. Also Sleep Out command cannot be sent for
120msec.
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Preliminary Version: 0.6
Preliminary
SPFD54124B
7.14. Colour Depth Conversion Look Up Tables
7.14.1. 4096 and 65536 Colour to 262,144 Colour
Colour
Look Up Table Outputs
Frame Memory Data (6-bit)
RED
R005R004 R003 R002 R001 R000
R015R014 R013 R012 R011 R010
R025R024 R023 R022 R021 R020
R035R034 R033 R032 R031 R030
R045R044 R043 R042 R041 R040
R055R054 R053 R052 R051 R050
R065R064 R063 R062 R061 R060
R075R074 R073 R072 R071 R070
R085R084 R083 R082 R081 R080
R095R094 R093 R092 R091 R090
R105R104 R103 R102 R101 R100
R115R114 R113 R112 R111 R110
R125R124 R123 R122 R121 R120
R135R134 R133 R132 R131 R130
R145R144 R143 R142 R141 R140
R155R154 R153 R152 R151 R150
R165R164 R163 R162 R161 R160
R175R174 R173 R172 R171 R170
R185R184 R183 R182 R181 R180
R195R194 R193 R192 R191 R190
R205R204 R203 R202 R201 R200
R215R214 R213 R212 R211 R210
R225R224 R223 R222 R221 R220
R235R234 R233 R232 R231 R230
R245R244 R243 R242 R241 R240
R255R254 R253 R252 R251 R250
R265R264 R263 R262 R261 R260
R275R274 R273 R272 R271 R270
R285R284 R283 R282 R281 R280
R295R294 R293 R292 R291 R290
R305R304 R303 R302 R301 R300
R315R314 R313 R312 R311 R310
© ORISE Technology Co., Ltd.
Proprietary & Confidential
Default value after H/W Reset
4k Colour
000000
000100
001000
001100
010001
010101
011001
011101
100010
100110
101010
101110
110011
110111
111011
111111
Not Used
65k Colour
000000
000010
000100
000110
001000
001010
001100
001110
010000
010010
010100
010110
011000
011010
011100
011110
100001
100011
100101
100111
101001
101011
101101
101111
110001
110011
110101
110111
111001
111011
111101
111111
198
RGBSET
Parameter
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Look Up Table Input Data
4k Colour
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Not Used
65k Colour
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
Colour
Look Up Table Outputs
Frame Memory Data (6-bit)
GREEN
G005 G004 G003 G002 G001 G000
G015 G014 G013 G012 G011 G010
G025 G024 G023 G022 G021 G020
G035 G034 G033 G032 G031 G030
G045 G044 G043 G042 G041 G040
G055 G054 G053 G052 G051 G050
G065 G064 G063 G062 G061 G060
G075 G074 G073 G072 G071 G070
G085 G084 G083 G082 G081 G080
G095 G094 G093 G092 G091 G090
G105 G104 G103 G102 G101 G100
G115 G114 G113 G112 G111 G110
G125 G124 G123 G122 G121 G120
G135 G134 G133 G132 G131 G130
G145 G144 G143 G142 G141 G140
G155 G154 G153 G152 G151 G150
G165 G164 G163 G162 G161 G160
G175 G174 G173 G172 G171 G170
G185 G184 G183 G182 G181 G180
G195 G194 G193 G192 G191 G190
G205 G204 G203 G202 G201 G200
G215 G214 G213 G212 G211 G210
G225 G224 G223 G222 G221 G220
G235 G234 G233 G232 G231 G230
G245 G244 G243 G242 G241 G240
G255 G254 G253 G252 G251 G250
G265 G264 G263 G262 G261 G260
G275 G 274 G273 G272 G271 G270
G285 G 284 G283 G282 G281 G280
G295 G 294 G293 G292 G291 G290
G305 G 304 G303 G302 G301 G300
G315 G 314 G313 G312 G311 G310
© ORISE Technology Co., Ltd.
Proprietary & Confidential
Default value after H/W Reset
4k Colour
000000
000100
001000
001100
010001
010101
011001
011101
100010
100110
101010
101110
110011
110111
111011
111111
Not Used
65k Colour
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
199
RGBSET
Parameter
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Look Up Table Input Data
4k Colour
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Not Used
65k Colour
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
Colour
Look Up Table Outputs
Frame Memory Data (6-bit)
GREEN
G325 G324 G323 G322 G321 G320
G335 G334 G333 G332 G331 G330
G345 G344 G343 G342 G341 G340
G355 G354 G353 G352 G351 G350
G365 G364 G363 G362 G361 G360
G375 G374 G373 G372 G371 G370
G385 G384 G383 G382 G381 G380
G395 G394 G393 G392 G391 G390
G405 G404 G403 G402 G401 G400
G415 G414 G413 G412 G411 G410
G425 G424 G423 G422 G421 G420
G435 G434 G433 G432 G431 G430
G445 G444 G443 G442 G441 G440
G455 G454 G453 G452 G451 G450
G465 G464 G463 G462 G461 G460
G475 G474 G473 G472 G471 G470
G485 G484 G483 G482 G481 G480
G495 G494 G493 G492 G491 G490
G505 G504 G503 G502 G501 G500
G515 G514 G513 G512 G511 G510
G525 G524 G523 G522 G521 G520
G535 G534 G533 G532 G531 G530
G545 G544 G543 G542 G541 G540
G555 G554 G553 G552 G551 G550
G565 G564 G563 G562 G561 G560
G575 G574 G573 G572 G571 G570
G585 G584 G583 G582 G581 G580
G595 G594 G593 G592 G591 G590
G605 G604 G603 G602 G601 G600
G615 G614 G613 G612 G611 G610
G625 G624 G623 G622 G621 G620
G635 G634 G633 G632 G631 G630
© ORISE Technology Co., Ltd.
Proprietary & Confidential
Default value after H/W Reset
4k Colour
Not Used
65k Colour
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
200
RGBSET
parameter
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
Look Up Table Input Data
4k Colour
Not Used
65k Colour
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
Colour
Look Up Table Outputs
Frame Memory Data (6-bit)
BLUE
B005B004 B003 B002 B001 B000
B015B014 B013 B012 B011 B010
B025B024 B023 B022 B021 B020
B035B034 B033 B032 B031 B030
B045B044 B043 B042 B041 B040
B055B054 B053 B052 B051 B050
B065B064 B063 B062 B061 B060
B075B074 B073 B072 B071 B070
B085B084 B083 B082 B081 B080
B095B094 B093 B092 B091 B090
B105B104 B103 B102 B101 B100
B115B114 B113 B112 B111 B110
B125B124 B123 B122 B121 B120
B135B134 B133 B132 B131 B130
B145B144 B143 B142 B141 B140
B155B154 B153 B152 B151 B150
B165B164 B163 B162 B161 B160
B175B174 B173 B172 B171 B170
B185B184 B183 B182 B181 B180
B195B194 B193 B192 B191 B190
B205B204 B203 B202 B201 B200
B215B214 B213 B212 B211 B210
B225B224 B223 B222 B221 B220
B235B234 B233 B232 B231 B230
B245B244 B243 B242 B241 B240
B255B254 B253 B252 B251 B250
B265B264 B263 B262 B261 B260
B275B274 B273 B272 B271 B270
B285B284 B283 B282 B281 B280
B295B294 B293 B292 B291 B290
B305B304 B303 B302 B301 B300
B315B314 B313 B312 B311 B310
© ORISE Technology Co., Ltd.
Proprietary & Confidential
Default value after H/W Reset
4k Colour
000000
000100
001000
001100
010001
010101
011001
011101
100010
100110
101010
101110
110011
110111
111011
111111
Not Used
65k Colour
000000
000011
000101
000111
001001
001011
001101
001111
010001
010011
010101
010111
011001
011011
011101
011111
100001
100011
100101
100111
101001
101011
101101
101111
110001
110011
110101
110111
111001
111011
111101
111111
201
RGBSET
parameter
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Look Up Table Input Data
4k Colour
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Not Used
65k Colour
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
7.15. Sleep Out-Command and Self-Diagnostic Functions of the Display Module
7.15.1. Register Loading Detection
Sleep Out-command is a trigger for an internal function of the display module, which indicates, if the display module loading function of
factory default values from OTP (one-time programming memory) to registers of the display controller is working properly.
There are compared factory values of the OTP and register values of the display controller by the display controller. If those both values
(OTP and register values) are same, there is inverted (=increased by 1) a bit in “Read Display Self-Diagnostic Result (0Fh)” (=RDDSDR)
(The used bit of this command is D7). If those both values are not same, this bit (D7) is not inverted (= increased by 1).
The flow chart for this internal function is following:
Power on sequence
HW reset
SW reset
Sleep In (10h)
Sleep Out Mode
Sleep In Mode
RDDSDR’s D7=0
Sleep Out (11h)
Loads values from
OTP to registers
No
Compares OTP and
register values
Are OTP and register
values same ?
Yes
D7 inverted
Note: There is not compared and loaded register values, which can be changed by user (00h to AFh and DAh to DDh), by the display
module.
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7.15.2. Functionality Detection
Sleep Out-command is a trigger for an internal function of the display module, which indicates, if the display module is still running and
meets functionality requirements.
The internal function (= the display controller) is comparing, if the display module is still meeting functionality requirements (only Booster
voltage level). If functionality requirement is met, there is inverted (= increased by 1) a bit in “Read Display Self- Diagnostic Result (0Fh)” (=
RDDSDR) (The used bit of this command is D6). If functionality requirement is not same, this bit (D6) is not inverted (= increased by 1).
The flow chart for this internal function is following:
Sleep In (10h)
Sleep Out Mode
Sleep In Mode
Power on sequence
HW reset
SW reset
RDDSDR’s D6=0
Sleep Out (11h)
Checks Booster voltage levels
and other functionalities
No
Is functionality
requirement met ?
Yes
D6 inverted
Note: There is needed 120msec after Sleep Out -command, when there is changing from Sleep In –mode to Sleep Out -mode, before there
is possible to check if functionality requirements are met and a value of RDDSDR’s D6 is valid. Otherwise, there is 5msec delay for
D6’s value, when Sleep Out –command is sent in Sleep Out -mode.
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7.15.3. Chip Attachment Detection
Sleep Out-command is a trigger for an internal function of the display module, which indicates, if a chip or chips (e.g. driver, etc.) of the
display module is/are attached to the circuit route of a flex foil or display glass ITO.
There is inverted (= increased by 1) a bit in command “Read Display Self- Diagnostic Result (0Fh)” (= RDDSDR) (The used bit of this
command is D5), if the chip or chips is/are attached to the circuit route of the flex or display glass. If this chip is or those chips are not
attached to the circuit route of the flex or display glass, this bit (D5) is not inverted (= increased by 1).
The following figure is for reference purposes; how this chip attachment can be implemented e.g. there are connected together 2 bumps via
route of ITO or the flex foil on 4 corners of the driver (chip).
Bump
Routing
between
bumps
Through view of driver to
Routing
between
bumps
Substrate of display glass
The flow chart for this internal function is following:
Sleep In (10h)
Sleep Out Mode
Sleep In Mode
Power on sequence
HW reset
SW reset
RDDSDR’s D5=0
Sleep Out (11h)
Checks, if chip is attached to
route
No
Is chip attached to
routes?
Yes
D5 inverted
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7.15.4. Display Glass Break Detection
Sleep Out-command is a trigger for an internal function of the display module, which indicates, if the display glass of the display module is
broken or not.
There is inverted (= increased by 1) a bit in “Read Display Self-Diagnostic Result (0Fh)” (= RDDSDR) (The used bit of this command is D4),
if the display glass is not broken. If this display glass is broken, this bit (D4) is not inverted (= increased by 1).
The following figure is a reference, how this glass break detection can be implemented e.g. there is connected together 2 bumps via route
of ITO. This route of ITO is the nearest route of the edge of the display glass.
Active area of the display glass
Through view of driver to
Substrate of display glass
The flow chart for this internal function is following:
Sleep In (10h)
Sleep Out Mode
Sleep In Mode
Power on sequence
HW reset
SW reset
RDDSDR’s D4=0
Sleep Out (11h)
Checks, if display glass is broken
Yes
Is the display glass
broken?
No
D4 inverted
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7.16. Oscillator
The chip has on-chip oscillator that does not require external components. This oscillator output signal is used for system clock generation
for internal display operation.
7.17. System Colck Generator
The timing generator produces the various signals to dirver the internal circuitty. Internal chip operation is not affected by operations on the
data bus.
7.18. Instruction Decoder and Register
The instruction decoder indentifies command words arriving at the interface and routes the following data bytes to their destination. The
command set can be found in “ Command” section.
7.19. Source Driver
The source driver block includes 132x3 source outputs (S1 to S396), which should be connected directly to the TFT-LCD. The source
output signals are generated in the data processing block after the data is read out of the RAM and latched, which represent the
simulatance selected rows.
7.20. Gate Driver
The gate dirver block include 160 chanel gate output (G1 to G162) which should be connected directly to the TFT-LCD.
7.20.1. Gate Driver
S1-S396
1
2
3
4
5
6
7
8
9
10
11
12
G1
G2
G3
G4
G5
G6
G7
VGH
G8
VGL
G9
G10
G11
G12
Fig. 7.20.1 Gate Driver Output Option 1
7.21. γ-CORRECTION FUNCTION
The SPFD54124B adopts true 6-bit OP-AMP with adjustable γ -correction function to display in 262,144 colors. The adjustable γ
-correction can be set by 14 groups of registers to determine eight reference grayscale levels, which are gradient adjustment, amplitude
adjustment and fine-adjustment registers. Each register group can be set independently to other register groups.
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8. ELECTRICAL SPECIFICATIONS
8.1. DC CharacteristicAC Characteristic
(VDD=2.6V~3.6V, VDDIO = 1.6V~3.6V, Ta = -40℃ ~ 85℃)
Parameter
Power & Operation Voltage
Analog Operating voltage
Logic Operating voltage
Digital Operating voltage
Gate Driver High voltage
Gate Driver Low voltage
Driver Supply voltage
Input / Output
Logic High level input voltage
Logic Low level input voltage
Logic High level output
voltage
Logic Low level output voltage
Logic High level input current
Logic Low level input current
Logic Input leakage current
VCOM Operation
VCOM High voltage
VCOM Low voltage
VCOM Amplitude voltage
Source Driver
Source output range
Gamma reference voltage
Source output settling time
Output deviation voltage
(Source output channel)
Output offset voltage
Booster Operation
Internal reference voltage
1st Booster (VDDx2) voltage
1st Booster (VDDx2) Drop
voltage
Linear range
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Symbol
Conditions
VDD
VDDIO
VCC
VGH
VGL
Operating Voltage
I/O supply voltageDigital supply voltage
MIN
Specification
TYP
MAX
Unit
2.78
1.8/2.78
|VGH-VGL|
2.6
1.6
2.6
10.0
-11.5
19
3.6
3.6
3.6
13.5
-9.0
30
V
V
V
V
V
V
VIH
VIL
-
0.7VDDIO
VSS
-
VDDIO
0.3VDDIO
V
V
VOH
IOH = -1.0mA
0.8VDDIO
-
VDDIO
V
VOL
IIH
IIL
IIL
IOL = +1.0mA
VSS
-
0.2VDDIO
1
VIN = VDDIO or VSS
-1
-0.1
-
+0.1
V
µA
µA
µA
VCOMH
VCOML
VCOMA
Ccom=12nF
Ccom=12nF
|VCOMH-VCOML|
2.5
-2.5
4.0
5.0
0.0
6.0
V
V
V
0.1
3.0
AVDD-0.1
5.0
V
V
20
µs
20
15
35
mV
mV
mv
1
6.0 *7)
%
V
5%
%
AVDD-0.2
Notes
V
VSout
GVDD
Tr
V,dev
Below with 99%
precision
15
Sout & gt; =4.2V, Sout & lt; =0.8V
4.2V & gt; Sout & gt; 0.8V
VOFSET
VREF
AVDD
VDDx2,d
rop
4.95 *6)
I AVDD = 1mA
(include Panel loading)
VLinear
0.2
207
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
8.2. AC timing Characteristics
8.2.1.
Parallel Interface Characteristics 18, 16 ,9 or 8-bits bus (8080-series MCU)
TCHW
TCHW
CSX
VIH
TCSF
VIL
TCSH
TCS
D/CX
VIH
VIL
TAST
TAHT
TWC
WRX
TCSF
VIH
TWRL
TWRH
VIL
TDST
D[17:0]
Write
TDHT
VIH
VIL
TRCS/TRCSFM
TAST
VIH
RDX
TAHT
TRC/TRCFM
TRDL/TRDLFM
TRDH/ TRDHFM
VIL
TODH
TRAT/ TRATFM
D[17:0]
Read
VIH
VIL
Fig. 8.2.1.1 Parallel Interface characteristics (8080-Series MCU)
Table 8.2.1.1: AC Characteristics for Parallel Interface18, 16, 9, 8-bits bus (8080-series MCU)
Signal
D/CX
CSX
WRX
RDX (ID)
RDX (FM)
D[17:0]
Symbol
TAST
TAHT
TCHW
TCS
TRCS
TRCSFM
TCSF
TCSH
TWC
TWRH
TWRL
TRC
TRDH
TRDL
TRCFM
TRDHFM
TRDLFM
TDST
TDHT
TRAT
TRATFM
TODH
Parameter
MIN
Address setup time
Address hold time (Write/Read)
Chip select “H” pulse width
Chip select setup time (Write)
Chip select setup time (Read ID)
Chip select setup time (Read FM)
Chip select wait time (Write/Read)
Chip select hold time
Write cycle
Control pulse “H” duration
Control pulse “L” duration
Read cycle (ID)
Control pulse “H” duration (ID)
Control pulse “L” duration (ID)
Read cycle (FM)
Control pulse “H” duration (FM)
Control pulse “L” duration (FM)
Data setup time
Data hold time
Read access time (ID)
Read access time (FM)
Output disable time
MAX
Unit
40
340
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
0
35
45
355
10
10
100
35
35
160
90
45
450
90
355
10
10
20
Description
-
-(3-transfer for one pixel)
When read ID data
When read from frame memory
For maximum CL=30pF
For minimum CL=8pF
Note 1: VDDIO=1.6 to 3.6V, VDD=2.6 to 3.6V, AGND=DGND=0V, Ta=-30 to 70℃ (to +85℃ no damage)
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Input Signal Slope
Output Signal Slope
TR
TF
TR
TF
VIH=0.7*VDDIO
VIL=0.3*VDDIO
VOH=0.8*VDDIO
VOL=0.2*VDDIO
TR=TF & lt; = 15ns
TR=TF & lt; = 15ns
Fig. 8.2.1.2 Rising and Falling timing for Input and Output signal
VIH
CSX
VIL
TCHW
VIH
WRX
RDX
VIL
TCSF
Min. 5ns
Fig.8.2.1.3 Chip selection (CSX) timing
CSX
WRX
VIH
VIH
VIL
VIL
VIH
RDX
TWRH
VIL
TWRH /TRDHFM
Fig. 8.2.1.4 Write to read and Read to write timing
NOTE: The input signal rise time and fall time (Tr, Tf) is specified at 15 ns or less.
Logic high and low levels are specified as 30% and 70% of VDDIO for Input signals.
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8.3. Parallel Interface Characteristics 18, 16 ,9 or 8-bits bus (6800-series MCU)
TCHW
CSX
TCS
TRCS/TRCSFM
VIH
VIL
TCSH
TCSF
VIH
D/CX
VIL
TAHT
TAST
/WX
VIH
TWC
VIL
TWRH
VIL
VIH
D[17:0]
Write
RX
TWRL
VIH
E
VIL
TDHT
TDST
VIH
TRC/TRCFM
VIL
VIH
E
TRDH/ TRDHFM
VIL
TRDL/TRDLFM
TRAT/ TRATFM
D[17:0]
Read
VIH
TODH
VIL
Fig. 8.3.1 Parallel Interface characteristics (6800-Series MCU)
Table 8.3.1: AC Characteristics for Parallel Interface 18, 16, 9, 8-bits bus (6800-series MCU)
Signal
D/CX
CSX
WRX
RDX (ID)
RDX (FM)
D[17:0]
Symbol
TAST
TAHT
TCHW
TCS
TRCS
TRCSFM
TCSF
TCSH
TWC
TWRH
TWRL
TRC
TRDH
TRDL
TRCFM
TRDHFM
TRDLFM
TDST
TDHT
TRAT
TRATFM
TODH
Parameter
MIN
Address setup time
Address hold time (Write/Read)
Chip select “H” pulse width
Chip select setup time (Write)
Chip select setup time (Read ID)
Chip select setup time (Read FM)
Chip select wait time (Write/Read)
Chip select hold time
Write cycle
Control pulse “H” duration
Control pulse “L” duration
Read cycle (ID)
Control pulse “H” duration (ID)
Control pulse “L” duration (ID)
Read cycle (FM)
Control pulse “H” duration (FM)
Control pulse “L” duration (FM)
Data setup time
Data hold time
Read access time (ID)
Read access time (FM)
Output disable time
MAX
Unit
40
340
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
0
35
45
355
10
10
100
35
35
160
90
45
450
90
355
10
10
20
Description
-
-
When read ID data
When read from frame
memory
For maximum CL=30pF
For minimum CL=8pF
Note 1: VDDIO=1.6 to 3.6V, VDD=2.6 to 3.6V, AGND=DGND=0V, Ta=-30 to 70℃ (to +85℃ no damage)
Note 2: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
Logic high and low levels are specified as 30% and 70% of VDDIO for Input signals.
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SPFD54124B
8.4. Serial Interface Characteristics (3-pin Serial)
CSX
VIH
TCHW
VIL
TCSS
SCL
TSCYCW /TSCYCR
VIH
VIL
TSDS
SDA
(DIN)
TCSH
TSCC
TSLW /TSLR
TSHW /TSHR
TSDH
VIH
VIL
TACC
SDA
(DOUT)
TOH
VIH
VIL
Fig. 8.4.1 3-pin Serial Interface Characteristics
Table 8.4.1: 3-pin Serial Interface Characteristics
Signal
CSX
SCL
SDA
(DIN)
(DOUT)
Symbol
TCSS
TCSH
TSCC
TCHW
TSCYCW
TSHW
TSLW
TSCYCR
TSHR
TSLR
TSDS
TSDH
TACC
TOH
Parameter
MIN
Chip select setup time
Chip select hold time
Chip select setup time
Chip select setup time
Serial clock cycle (Write)
SCL “H” pulse width (Write)
SCL “L” pulse width (Write)
Serial clock cycle (Read)
SCL “H” pulse width (Read)
SCL “L” pulse width (Read)
Data setup time
Data hold time
Access time
Output disable time
MAX
60
65
20
40
100
35
35
150
60
60
30
30
10
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
-
For maximum CL=30pF
For minimum CL=8pF
Note 1: VDDIO=1.6 to 3.6V, VDD=2.6 to 3.6V, AGND=DGND=0V, Ta=-30 to 70℃ (to +85℃ no damage)
Note 2: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
Logic high and low levels are specified as 30% and 70% of VDDIO for Input signals.
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PADA1
PADB1
PADA0
EXTC
VSS
IM0
VDDIO
IM1
VSS
IM2
VDDIO
P68
VSS
RCM0
VDDIO
RCM1
VSS
SRGB
VDDIO
SMX
VSS
SMY
VDDIO
IDM
VSS
REV
VDDIO
RL
VSS
TB
VDDIO
SHUT
VSS
GM1
GM0
LCM
VDDIO
LCM1
VSS
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
VSS
TESEL
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
TEST/DUMMY
TRIM1
TRIM2
TRIM3
TRIM4
OSC
TE
CSX
RDX
WRX
SDA
GAMSEL
SPI4
RESX
VSS
DCX
VSS
PCLK
VSS
DE
HS
VS
TEST1
TEST2
TEST3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDD_18V
VDD_18V
VDD_18V
VCI1
VCI1
VCI1
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VDD
VDD
VDD
VDD
VDD
VREF
VREF
VREF
FB
DRV
AVDD
AVDD
AVDD
AVDD
AVDD
GVDD
GVDD
GVDD
C11P
C11P
C11P
C11N
C11N
C11N
C12P
C12P
C12P
C12N
C12N
C12N
VSSA
VSSA
VSSA
VCL
VCL
VCL
C21P
C21P
C21N
C21N
C22P
C22P
C22N
C22N
C23P
C23P
C23N
C23N
VGL
VGL
VGL
VGH
VGH
VGH
VCOMH
VCOMH
VCOMH
VCOML
VCOML
VCOML
PADB0
VCOM
VCOM
VCOM
PADA2
PADB2
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Item
Pad pitch
Bumped pad size
Chip Size
X
-
Chip thickness
PAD No.
Size
Y
13500
176~760
22
-
1, 2, 174, 175
64
-
3~173
80
-
176~760
21
96
3~173
55
96
1, 2, 174, 175
50
212
G146
G150
G154
G158
G162
DUMMY
DUMMY
PADB4
G2
G234
G230
S389
S391
S393
S395
DUMMY
DUMMY
DUMMY
S199
DUMMY
DUMMY
S198
S2
S4
S6
S8
S10
G1
DUMMY
DUMMY
DUMMY
G5
G157
G161
DUMMY
DUMMY
PADA4
G160
DUMMY
G152
G156
G144
G148
DUMMY
G236
G232
S390
S392
S394
S396
DUMMY
DUMMY
DUMMY
S200
DUMMY
DUMMY
S197
DUMMY
DUMMY
DUMMY
S1
S3
S5
S7
S9
S11
G3
G155
G159
PADA3
PADB3
DUMMY
Preliminary
SPFD54124B
9. CHIP INFORMATION
9.1. PAD Assignment
Coordinates origin: Pad Left-bottom side
9.2. PAD Dimension
Unit
700
400
96
µm
Note1: Chip size included scribe line.
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Preliminary Version: 0.6
Preliminary
SPFD54124B
9.3.
Bump Dimension
9.3.1.
9.3.2.
Input Pads
Output Pads
Item
Sumbol
Size
Item
Sumbol
Size
Bump Pitch
Bump Width
Bump height
Bump space 1
Bump space 2
Bump area
Chip boundary
A
B
C
D
E
BxC
F
22 um
21 um
96 um
35 um
23 um
2
2016 um
45-70 um
Bump Pitch
Bump Pitch
Bump Width
Bump height
Bump space 1
Bump space 2
Bump area
Chip boundary
Bump Width
Bump space 3
A
B
C
D
E
F
CxD
G
H
I
64 um
80 um
55 um
96 um
9 um
25um
2
5280 um
45-70 um
50
14
9.4. Bump Characteristics
Item
Standard
Note
Bump Hardness
75Hv
±25Hv
Bump Height
15µm
±3µm
Co-planarity (in Chip)
R≦ 2µm
R : Max-Min
Roughness (in Bump)
R≦ 2µm
R : Max-Min
Bump Size
“X” ± 4µm x “Y” ± 4µm
X/Y: bump size
Shear Force
& gt; 4.5g/mil^2
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SPFD54124B
9.5. PAD Locations
PAD No.
PAD Name
X
Y
PAD No.
PAD Name
X
Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
PADA1
PADB1
PADA0
EXTC
VSS
IM0
VDDIO
IM1
VSS
IM2
VDDIO
P68
VSS
RCM0
VDDIO
RCM1
VSS
SRGB
VDDIO
SMX
VSS
SMY
VDDIO
IDM
VSS
REV
VDDIO
RL
VSS
TB
VDDIO
SHUT
VSS
GM1
GM0
LCM0
VDDIO
LCM1
VSS
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
VSS
TESEL
DB7
DB6
DB5
DB4
246
310
390
470
550
630
710
790
870
950
1030
1110
1190
1270
1350
1430
1510
1590
1670
1750
1830
1910
1990
2070
2150
2230
2310
2390
2470
2550
2630
2710
2790
2870
2950
3030
3110
3190
3270
3350
3430
3510
3590
3670
3750
3830
3910
3990
4070
4150
4230
4310
4390
4470
4550
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
DB3
DB2
DB1
DB0
TEST/DUMMY
TRIM1
TRIM2
TRIM3
TRIM4
OSC
TE
CSX
RDX
WRX
SDA
GAMSEL
SPI4
RESX
VSS
DCX
VSS
PCLK
VSS
DE
HS
VS
TEST1
TEST2
TEST3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDD_18V
VDD_18V
VDD_18V
VCI1
VCI1
VCI1
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VDD
4630
4710
4790
4870
4950
5030
5110
5190
5270
5350
5430
5510
5590
5670
5750
5830
5910
5990
6070
6150
6230
6310
6390
6470
6550
6630
6710
6790
6870
6950
7014
7078
7142
7206
7270
7334
7414
7478
7542
7606
7670
7734
7814
7878
7942
8022
8086
8150
8230
8294
8358
8422
8486
8550
8630
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
© ORISE Technology Co., Ltd.
Proprietary & Confidential
214
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
PAD No.
PAD Name
X
Y
PAD No.
PAD Name
X
Y
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
VDD
VDD
VDD
VDD
VREF
VREF
VREF
FB
DRV
VDDA
VDDA
VDDA
VDDA
VDDA
GVDD
GVDD
GVDD
C11P
C11P
C11P
C11N
C11N
C11N
C12P
C12P
C12P
C12N
C12N
C12N
VSSA
VSSA
VSSA
VCL
VCL
VCL
C21P
C21P
C21N
C21N
C22P
C22P
C22N
C22N
C23P
C23P
C23N
C23N
VGL
VGL
VGL
VGH
VGH
VGH
VCOMH
VCOMH
VCOMH
8694
8758
8822
8886
8966
9030
9094
9174
9254
9334
9398
9462
9526
9590
9670
9734
9798
9878
9942
10006
10086
10150
10214
10294
10358
10422
10502
10566
10630
10710
10774
10838
10918
10982
11046
11126
11190
11270
11334
11414
11478
11558
11622
11702
11766
11846
11910
11990
12054
12118
12198
12262
12326
12406
12470
12534
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
VCOML
VCOML
VCOML
PADB0
VCOM
VCOM
VCOM
PADA2
PADB2
PADB4
DUMMY
PADA4
DUMMY
DUMMY
G162
G160
G158
G156
G154
G152
G150
G148
G146
G144
G142
G140
G138
G136
G134
G132
G130
G128
G126
G124
G122
G120
G118
G116
G114
G112
G110
G108
G106
G104
G102
G100
G98
G96
G94
G92
G90
G88
G86
G84
G82
G80
12614
12678
12742
12822
12902
12966
13030
13110
13174
13134
13112
13090
13068
13046
13024
13002
12980
12958
12936
12914
12892
12870
12848
12826
12804
12782
12760
12738
12716
12694
12672
12650
12628
12606
12584
12562
12540
12518
12496
12474
12452
12430
12408
12386
12364
12342
12320
12298
12276
12254
12232
12210
12188
12166
12144
12122
78
78
78
78
78
78
78
78
78
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
© ORISE Technology Co., Ltd.
Proprietary & Confidential
215
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
PAD No.
PAD Name
X
Y
PAD No.
PAD Name
X
Y
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
G78
G76
G74
G72
G70
G68
G66
G64
G62
G60
G58
G56
G54
G52
G50
G48
G46
G44
G42
G40
G38
G36
G34
G32
G30
G28
G26
G24
G22
G20
G18
G16
G14
G12
G10
G8
G6
G4
G2
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
S396
S395
S394
S393
S392
S391
S390
S389
S388
S387
S386
12100
12078
12056
12034
12012
11990
11968
11946
11924
11902
11880
11858
11836
11814
11792
11770
11748
11726
11704
11682
11660
11638
11616
11594
11572
11550
11528
11506
11484
11462
11440
11418
11396
11374
11352
11330
11308
11286
11264
11242
11220
11198
11176
11154
11132
11110
11088
11066
11044
11022
11000
10978
10956
10934
10912
10890
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
S385
S384
S383
S382
S381
S380
S379
S378
S377
S376
S375
S374
S373
S372
S371
S370
S369
S368
S367
S366
S365
S364
S363
S362
S361
S360
S359
S358
S357
S356
S355
S354
S353
S352
S351
S350
S349
S348
S347
S346
S345
S344
S343
S342
S341
S340
S339
S338
S337
S336
S335
S334
S333
S332
S331
S330
10868
10846
10824
10802
10780
10758
10736
10714
10542
10670
10648
10626
10604
10582
10560
10538
10516
10494
10472
10450
10428
10406
10384
10362
10340
10318
10296
10274
10252
10230
10208
10186
10164
10142
10120
10098
10076
10054
10032
10010
9988
9966
9944
9922
9900
9878
9856
9834
9812
9790
9768
9746
9724
9702
9680
9658
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
© ORISE Technology Co., Ltd.
Proprietary & Confidential
216
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
PAD No.
PAD Name
X
Y
PAD No.
PAD Name
X
Y
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
S329
S328
S327
S326
S325
S324
S323
S322
S321
S320
S319
S318
S317
S316
S315
S314
S313
S312
S311
S310
S309
S308
S307
S306
S305
S304
S303
S302
S301
S300
S299
S298
S297
S296
S295
S294
S293
S292
S291
S290
S289
S288
S287
S286
S285
S284
S283
S282
S281
S280
S279
S278
S277
S276
S275
S274
9636
9614
9592
9570
9548
9526
9504
9482
9460
9438
9416
9394
9372
9350
9328
9306
9284
9262
9240
9218
9196
9174
9152
9130
9108
9086
9064
9042
9020
8998
8976
8954
8932
8910
8888
8866
8844
8822
8800
8778
8756
8734
8712
8690
8668
8646
8624
8602
8580
8558
8536
8514
8492
8470
8448
8426
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
S273
S272
S271
S270
S269
S268
S267
S266
S265
S264
S263
S262
S261
S260
S259
S258
S257
S256
S255
S254
S253
S252
S251
S250
S249
S248
S247
S246
S245
S244
S243
S242
S241
S240
S239
S238
S237
S236
S235
S234
S233
S232
S231
S230
S229
S228
S227
S226
S225
S224
S223
S222
S221
S220
S219
S218
8404
8382
8360
8338
8316
8294
8272
8250
8228
8206
8184
8162
8140
8118
8096
8074
8052
8030
8008
7986
7964
7942
7920
7898
7876
7854
7832
7810
7788
7766
7744
7722
7700
7678
7656
7634
7612
7590
7568
7546
7524
7502
7480
7458
7436
7414
7392
7370
7348
7326
7304
7282
7260
7238
7216
7194
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
© ORISE Technology Co., Ltd.
Proprietary & Confidential
217
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
PAD No.
PAD Name
X
Y
PAD No.
PAD Name
X
Y
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
S217
S216
S215
S214
S213
S212
S211
S210
S209
S208
S207
S206
S205
S204
S203
S202
S201
S200
S199
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
S198
S197
S196
S195
S194
S193
S192
S191
S190
S189
S188
S187
S186
S185
S184
S183
S182
S181
S180
S179
S178
S177
S176
S175
S174
S173
S172
S171
S170
S169
S168
S167
7172
7150
7128
7106
7084
7062
7040
7018
6996
6974
6952
6930
6908
6886
6864
6842
6820
6798
6776
6754
6732
6710
6688
6666
6644
6622
6600
6578
6556
6534
6512
6490
6468
6446
6424
6402
6380
6358
6336
6314
6292
6270
6248
6226
6204
6182
6160
6138
6116
6094
6072
6050
6028
6006
5984
5962
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
S166
S165
S164
S163
S162
S161
S160
S159
S158
S157
S156
S155
S154
S153
S152
S151
S150
S149
S148
S147
S146
S145
S144
S143
S142
S141
S140
S139
S138
S137
S136
S135
S134
S133
S132
S131
S130
S129
S128
S127
S126
S125
S124
S123
S122
S121
S120
S119
S118
S117
S116
S115
S114
S113
S112
S111
5940
5918
5896
5874
5852
5830
5808
5786
5764
5742
5720
5698
5676
5654
5632
4110
5588
5566
5544
5522
5500
5478
5456
5434
5422
5390
5368
5346
5324
5302
5280
5258
5236
5214
5192
5170
5148
5126
5104
5082
5060
5038
5016
4994
4972
4950
4928
4906
4884
4862
4840
4818
4796
4774
4752
4730
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
© ORISE Technology Co., Ltd.
Proprietary & Confidential
218
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
PAD No.
PAD Name
X
Y
PAD No.
PAD Name
X
Y
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
S110
S109
S108
S107
S106
S105
S104
S103
S102
S101
S100
S99
S98
S97
S96
S95
S94
S93
S92
S91
S90
S89
S88
S87
S86
S85
S84
S83
S82
S81
S80
S79
S78
S77
S76
S75
S74
S73
S72
S71
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61
S60
S59
S58
S57
S56
S55
4708
4686
4664
4642
4620
4598
4576
4554
4532
4510
4488
4466
4444
4422
4400
4378
4356
4334
4312
4290
4268
4246
4224
4202
4180
4158
4136
4114
4092
4070
4048
4026
4004
3982
3960
3938
3916
3894
3872
3850
3828
3806
3784
3762
3740
3718
3696
3674
3652
3630
3608
3586
3564
3542
3520
3498
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
DUMMY
DUMMY
3476
3454
3432
3410
3388
3366
3344
3322
3300
3278
3256
3234
3212
3190
3168
3146
3124
3102
3080
3058
3036
3014
2992
2970
2948
2926
2904
2882
2860
2838
2816
2794
2772
2750
2728
2706
2684
2662
2640
2618
2596
2574
2552
2530
2508
2486
2464
2442
2420
2398
2376
2354
2332
2310
2288
2266
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
© ORISE Technology Co., Ltd.
Proprietary & Confidential
219
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
PAD No.
PAD Name
X
Y
PAD No.
PAD Name
X
Y
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
DUMMY
DUMMY
DUMMY
DUMMY
G1
G3
G5
G7
G9
G11
G13
G15
G17
G19
G21
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
G59
G61
G63
G65
G67
G69
G71
G73
G75
G77
G79
G81
G83
G85
G87
G89
G91
2244
2222
2200
2178
2156
2134
2112
2090
2068
2046
2024
2002
1980
1958
1936
1914
1892
1870
1848
1826
1804
1782
1760
1738
1716
1694
1672
1650
1628
1606
1584
1562
1540
1518
1496
1474
1452
1430
1408
1386
1364
1342
1320
1298
1276
1254
1232
1210
1188
1166
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
G93
G95
G97
G99
G101
G103
G105
G107
G109
G111
G113
G115
G117
G119
G121
G123
G125
G127
G129
G131
G133
G135
G137
G139
G141
G143
G145
G147
G149
G151
G153
G155
G157
G159
G161
DUMMY
DUMMY
PADB3
DUMMY
PADA3
1144
1122
1100
1078
1056
1034
1012
990
968
946
924
902
880
858
836
814
792
770
748
726
704
682
660
638
616
594
572
550
528
506
484
462
440
418
396
374
352
330
308
286
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
411
542
© ORISE Technology Co., Ltd.
Proprietary & Confidential
220
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
9.6. Alignment Mark
--Alignment Mark coordinate
Left (95, 107.5)
Right (13337.5, 107.5)
--Alignment Mark size
Left
Right
15um
25um
25um
25um
25um
25um
25um
15um
15um
15um
25um
25um
221
25um
15um
15um
25um
25um
40um
© ORISE Technology Co., Ltd.
Proprietary & Confidential
15um
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
9.7. Wiring Resistance
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Name
PADA1
PADB1
PADA0
EXTC
VSS
IM0
VDDIO
IM1
VSS
IM2
VDDIO
P68
VSS
RCM0
VDDIO
RCM1
VSS
SRGB
VDDIO
SMX
VSS
SMY
VDDIO
IDM
VSS
REV
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
VDDIO
RL
VSS
TB
VDDIO
SHUT
VSS
GM1
GM0
LCM0
VDDIO
LCM1
VSS
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
VSS
TESEL
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
TEST/Dummy
TRIM1
TRIM2
TRIM3
TRIM4
OSC
TE
CSX
RDX
WRX
SDA
Wiring Resistance
Open
Open
Note1*(200 ohm)
200 ohm
Open
200 ohm
Open
200 ohm
Open
200 ohm
Open
200 ohm
Open
200 ohm
Open
200 ohm
Open
200 ohm
Open
200 ohm
Open
200 ohm
Open
200 ohm
Open
200 ohm
Open
200 ohm
Open
200 ohm
Open
200 ohm
Open
200 ohm
200 ohm
200 ohm
200 ohm
Open
Open
100 ohm
100 ohm
100 ohm
100 ohm
100 ohm
100 ohm
100 ohm
100 ohm
100 ohm
100 ohm
Open
100 ohm
100 ohm
100 ohm
100 ohm
100 ohm
100 ohm
100 ohm
100 ohm
100 ohm
Open
Open
Open
Open
Open
200 ohm
100 ohm
100 ohm
100 ohm
100 ohm
100 ohm
© ORISE Technology Co., Ltd.
Proprietary & Confidential
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
NAME
GAMSEL
SPI4
RESX
VSS
DCX
VSS
PCLK
VSS
DE
HS
VS
TEST1
TEST2
TEST3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
WIRING RESISTANCE
200 ohm
200 ohm
200 ohm
Open
100 ohm
Open
100 ohm
Open
100 ohm
100 ohm
100 ohm
Open
Open
Open
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
VDDIO
VDD_18V
VDD_18V
VDD_18V
VCI1
VCI1
VCI1
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VDD
VDD
VDD
VDD
VDD
VREF
VREF
VREF
TEST
TESTCLK
VDDA
VDDA
VDDA
VDDA
VDDA
GVDD
GVDD
GVDD
C11P
C11P
C11P
C11N
C11N
C11N
C12P
C12P
C12P
C12N
C12N
C12N
VSSA
10 ohm
5 ohm
10 ohm
10 ohm
10 ohm
5 ohm
10 ohm
Open
Open
20 ohm
20 ohm
5 ohm
5 ohm
5 ohm
5 ohm
10 ohm
222
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
NAME
VSSA
VSSA
VCL
VCL
VCL
C21P
C21P
C21N
C21N
C22P
C22P
C22N
C22N
C23P
C23P
C23N
C23N
VGL
VGL
VGL
VGH
VGH
VGH
VCOMH
VCOMH
VCOMH
WIRING RESISTANCE
10 ohm
20 ohm
5 ohm
5 ohm
5 ohm
5 ohm
5 ohm
5 ohm
10 ohm
30 ohm
30 ohm
VCOML
VCOML
VCOML
PADB0
VCOM
VCOM
VCOM
PADA2
PADB2
TEST/Dummy
TEST/Dummy
TEST/Dummy
TEST/Dummy
PADB4
DUMMY
PADA4
DUMMY
DUMMY
30 ohm
Note1*(200 ohm)
10 ohm
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
10. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by ORISE Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of
sale only. ORISE Technology makes no warranty, express, statutory implied or by description regarding the information in this publication
or regarding the freedom of the described chip(s) from patent infringement.
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE.
alter the specifications and prices at any time without notice.
FURTHERMORE, ORISE Technology MAKES NO
ORISE Technology reserves the right to halt production or
Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders. Products described herein are intended for use in normal commercial
applications.
Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by ORISE Technology for such applications. Please note that
application circuits illustrated in this document are for reference purposes only.
© ORISE Technology Co., Ltd.
Proprietary & Confidential
223
APR. 26, 2007
Preliminary Version: 0.6
Preliminary
SPFD54124B
11. REVISION HISTORY
Date
Revision #
Description
APR. 26, 2007
0.6
Modify Chip Size
APR. 04, 2007
0.5
1. Modify the operation voltage range of VDD and VDDIO
Page
212
31,33
VDD1
1.6V~3.6V
40,42
VDD
2.6V~3.6V
197
2. Modify “VCI”
3. Modify “VDD1”
“VDD”
6
“VDDIO”
147-155
207-211
JAN. 09, 2007
0.4
1. Add PAD Dimension
212
2. Add Bump Dimension
213
3. Add Bump Characteristics
213
214
NOV. 15, 2006
0.3
Change Title From 9.PAD Location to 9. CHIP INFORMATION
NOV. 13, 2006
0.2
Add Ordering Information
JUN. 22, 2006
0.1
Original
© ORISE Technology Co., Ltd.
Proprietary & Confidential
6
221
224
APR. 26, 2007
Preliminary Version: 0.6