Lenovo Y70-70 - 80DU000HUS - Intel Core i7-4710HQ / 512GB Solid State Drive / 16GB RAM DDR3L / 17.3" FHD 1920x1080 Display Touch / NVidia GeForce 860M 4GB * inne modele cpu 4th gen. Windows 8.1 ___________________________________________ Lenovo IdeaPad Y50-70 / 70-70 płyta główna ZIVY2 LA-B111P rev. (1.0) kbc KB9022Q Core i7-4710HQ (SR1PX) / i7-4720HQ (SR1Q8) chipset HM86 PCH (SR17E) nVidia N15P-GX-A2 Napięcie z przycisku power on ? Patrz zał. ____________________ Podobno wada płyty ? Link w serii Y50-70/ Y70-70. Uaktywnia się po czasie, serwis Lenovo zmienia MB. ...jeśli nie zadziała 1. unplug the AC adapter and take out the battery 2. push the power button 10 times in a row at one second intervals. Next, push and hold the power button for 30 seconds. Then put the battery back in and push the power button… * press and hold the Power Button for 15 seconds. 3. Plug in the charger / adapter if needed and power up the system to see if the problem was resolved. Podobny problem bywał w Lenovo Thinkpad z61
1
2
3
4
5
A
A
Compal Confidential
ZIVY2/ZIVY3
M/B
Schematics Document
B
B
Intel Shark Bay + N15P-GX
(Crescent Bay + N15P-GX)
LA-B111P
C
C
2014-02-25
REV:1.0
D
D
Compal Secret Data
Security Classification
Issued Date
2014/02/25
2015/02/25
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
1
2
3
4
Compal Electronics, Inc.
Cover Sheet
Document Number
Rev
1.0
LA-B111P
Tuesday, February 25, 2014
Sheet
5
1
of
59
1
2
3
4
5
Shark Bay/Crescent Bay
Compal Confidential
Intel
nVidia
N15P-GX
A
PEG 16X
Processor
DDR3-SO-DIMM X 2
DDR3L 1600MHz 1.35V
A
BANK 0, 1, 2, 3
+1.35V, +0.675VS
VRAM GDDR5 2G/4G
Page 36~45
Dual Channel
Haswell H
Broadwell H
Page 11, 12
eDP
LCD conn
Page 22
BGA
37.5mmX32mm
HDMI
HDMI, DDC
Page 4~10
Page 24
+VCC_CORE, +1.35V_CPU_VDDQ
port 8
Touch Panel
DMI x4
5GB/s
Page 22
port 10
BT (NGFF)
B
USB2.0
Intel
Lynx-Point
PCH
PCI-e
(WLAN)
port 2
port 5
NGFF
Card Reader
2230 Conn.
WLAN/BT
port 3
Realtek RTS5249
Page 28
USB conn x1
Right USB Board
Page 34
port 0,1
port 1,2
Page 25
USB conn x2
Left USB Board
USB3.0
RTL8111GUL
USB Board
B
port 4
LAN
Realtek GbE
Page 34
Page 28
Page 30
port 9
Camera
USB 2.0(BT)
port 10
Page 22
DMIC
Digital Array MIC
FCBGA 695 Balls
HM86
SPI ROM
8MB
20mmX20mm
SPI
Page 16
C
C
S/PDIF
Azalia
Page 34
Audio Codec
Realtek ALC283
Combo Jack
Page 26
Page 34
Page 13 ~ 21
port 4
SATA
2.5 " SATA HDD/SDD
DC/DC Interface CKT.
GEN3
Page 29
+1.05VS, +1.5VS, +3VS,
+3V_PCH, +RTCVCC
Speaker Connector
Page 26
Page 35
LPC BUS
Subwoofer AMP.
Green CLK
TPA3113D2PWPR
Page 27
SLG3NB304VTR
Touch Pad CONN.
Fan Control
Page 32
Page 34
Thermal Sensor
SMSC 1403-2
D
ZZZ
ZZZ0
PCB-MB(DA)
Page 32
ENE KB9022 C
Int. KBD
+3VLP
page 31
LID switch
Subwoofer
Page 27
Page 27
Page 32
D
Page 33
PCB-MB(DAZ)
PCB P/N for Load BOM
Compal Secret Data
Security Classification
Issued Date
V1.0
2014/02/25
Deciphered Date
2015/02/25
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
1
2
3
4
Block Diagram
Rev
1.0
LA-B111P
Tuesday, February 25, 2014
5
Sheet
2
of
59
1
( O MEANS ON
Voltage Rails
BOM Structure Table
X MEANS OFF )
USB Port Table
B+
+3V_PCH
+5VALW
+1.35V
+3VALW
+1.5VS
+VCC_CORE
+0.675VS
+12VS
UHCI1
EHCI1
UHCI2
UHCI3
State
UHCI4
S0
O
O
O
O
O
S3
O
O
O
O
X
DeepS3
O
O
X
O
X
S5 S4/AC
O
O
X
X
X
O
X
X
X
X
X
X
X
X
EHCI2
S5 S4/ Battery only
S5 S4/AC & Battery
don't exist
X
A
EC SM Bus1 address
Device
Smart Battery
Charger
EC SM Bus2 address
Address
Device
PCH SM Bus address
Device
Device
DDR DIMM0
1010 000x
1010 010x
Board ID Table for AD channel
Vcc
Ra / Rc
Board ID
0
1
2
3
4
5
6
7
3.3V
100K +/- 1%
Rb / Rd
0
12K +/- 1%
15K +/- 1%
20K +/- 1%
27K +/- 1%
33K +/- 1%
43K +/- 1%
V AD_BID min
0 V
0.347 V
0.423 V
0.541 V
0.691 V
0.807 V
0.978 V
V AD_BID typ
0 V
0.354 V
0.430 V
0.550 V
0.702 V
0.819 V
0.992 V
V AD_BID max
0 V
0.360 V
0.438 V
0.559 V
0.713 V
0.831 V
1.006 V
A
: means Digital Ground
Install below 43 level BOM structure for ver. 0.1
: means Analog Ground
CPU part
Address
CPU1@
A4h
CPU3@
CPU4@
CPU5@
CPU6@
CPU7@
U1
U1
U1
I7_4700HQ 2.4G
I7_4850HQ 3.5G
A0h
DDR DIMM1
Touch screen
Camera
WLAN
BOM Structure
45@
CONN@
KB15@
KB17@
15@
17@
WF@
DIS@
SW@
HW@
BW@
DS3@
NODS3@
GCLK@
NOGCLK@
CMOS@/NCMOS@
@
EMI@
@EMI@
ESD@
@ESD@
TI@/Parade@
Symbol Note :
PCH SML0 Bus address
Address
UHCI6
Right USB2.0
BTO Item
45 LEVEL
Connector
KB ZIVY2 (15 " )
KB ZIVY3 (17 " )
ZIVY2 (15 " )
ZIVY3 (17 " )
Subwoofer
DIS SKU
Nvidia GC6 state
Haswell
Broadwell
Deep S3
NO Deep S3
Green clk support
No Green clk support
Unpop
Unpop
EMI Pop
EMI unpop
ESD Pop
ESD unpop
SATA re-driver
Address
Thermal Sensor EMC1403-2-AIZL-TR 1001_101xb
PCH SML1 Bus address
0x9E
nVidia N15P-GX
0b 0001 0010 (0x12H)
UHCI5
1
2
XHCI
XHCI
0
1
2
3
4
5
6
7
8
9
10
11
12
13
UHCI0
+1.05VS
5 External
USB Port
Left USB3.0
Left USB3.0
USB 3.0 Port
USB 2.0 Port
+3VS
+12VS_PANEL
power
plane
+5VS
R3
U1
R3
U1
R1
R3
U1
Click Pad
I5_4200H 2.8G
SA000071N20
I7_4750HQ 2G
SA00007A900
4319S138L03 V2G
I7_4702HQ 2.2G
SA00006TQ20
4319S138L04 V4G
SA00006TP20
SA00007J710
I7_4950HQ 3.6G
SA00007A800
4319S138L05 V4G
SMBUS Control Table
SOURCE
SMB_EC_CK1
SMB_EC_DA1
SMBCLK
SMBDATA
SML0CLK
SML0DATA
SML1CLK
SML1DATA
KB9022
+3VLP_EC
PCH
+3V_PCH
PCH
+3V_PCH
PCH
+3V_PCH
BATT
V
X
X
X
KB9022
X
X
X
V
+3VS
SODIMM
X
V
X
X
+3VS
Touch
Pad
X
V
X
X
+3VS
Thermal
sensor
X
X
X
V
+3VS
VGA
X
X
X
V
+3VS_DGPU
Compal Secret Data
Security Classification
Issued Date
2014/02/25
Deciphered Date
2015/02/25
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
1
Notes List
Rev
1.0
LA-B111P
Tuesday, February 25, 2014
Sheet
3
of
59
5
4
3
2
1
+VCOMP_OUT
2
PEG_RCOMP
24.9_0402_1%
D
1
R1
D
Note:
Trace width=12 mils ,Spacing=15mils
Max length= 400 mils.
U1A
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
AB2
AB3
AC3
AC1
(14)
(14)
(14)
(14)
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
AB1
AB4
AC4
AC2
(14)
(14)
(14)
(14)
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
AF2
AF4
AG4
AG2
(14)
(14)
(14)
(14)
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
AF1
AF3
AG3
AG1
HASWELL_BGA_E
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMI
(14)
(14)
(14)
(14)
@
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
C
FDI_CSYMC
FDI_INT
F11
F12
FDI_CSYNC
DISP_INT
PEG
(14) FDI_CSYMC
(14) FDI_INT
FDI
B
PEG_RCOMP
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15
PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15
PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15
AH6
E10
C10
B10
E9
D9
B9
L5
L2
M4
L4
M2
V5
V4
V1
Y3
Y2
F10
D10
A10
F9
C9
A9
M5
L1
M3
L3
M1
Y5
V3
V2
Y4
Y1
B6
C5
E6
D4
G4
E3
J5
G3
J3
J2
T6
R6
R2
R4
T4
T1
C6
B5
D6
E4
G5
E2
J6
G2
J4
J1
T5
R5
R1
R3
T3
T2
PEG_RCOMP
PEG_PTX_DRX_N15
PEG_PTX_DRX_N14
PEG_PTX_DRX_N13
PEG_PTX_DRX_N12
PEG_PTX_DRX_N11
PEG_PTX_DRX_N10
PEG_PTX_DRX_N9
PEG_PTX_DRX_N8
PEG_PTX_DRX_N7
PEG_PTX_DRX_N6
PEG_PTX_DRX_N5
PEG_PTX_DRX_N4
PEG_PTX_DRX_N3
PEG_PTX_DRX_N2
PEG_PTX_DRX_N1
PEG_PTX_DRX_N0
PEG_PTX_DRX_P15
PEG_PTX_DRX_P14
PEG_PTX_DRX_P13
PEG_PTX_DRX_P12
PEG_PTX_DRX_P11
PEG_PTX_DRX_P10
PEG_PTX_DRX_P9
PEG_PTX_DRX_P8
PEG_PTX_DRX_P7
PEG_PTX_DRX_P6
PEG_PTX_DRX_P5
PEG_PTX_DRX_P4
PEG_PTX_DRX_P3
PEG_PTX_DRX_P2
PEG_PTX_DRX_P1
PEG_PTX_DRX_P0
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_CRX_GTX_N15
PEG_CRX_GTX_N14
PEG_CRX_GTX_N13
PEG_CRX_GTX_N12
PEG_CRX_GTX_N11
PEG_CRX_GTX_N10
PEG_CRX_GTX_N9
PEG_CRX_GTX_N8
PEG_CRX_GTX_N7
PEG_CRX_GTX_N6
PEG_CRX_GTX_N5
PEG_CRX_GTX_N4
PEG_CRX_GTX_N3
PEG_CRX_GTX_N2
PEG_CRX_GTX_N1
PEG_CRX_GTX_N0
PEG_CRX_GTX_P15
PEG_CRX_GTX_P14
PEG_CRX_GTX_P13
PEG_CRX_GTX_P12
PEG_CRX_GTX_P11
PEG_CRX_GTX_P10
PEG_CRX_GTX_P9
PEG_CRX_GTX_P8
PEG_CRX_GTX_P7
PEG_CRX_GTX_P6
PEG_CRX_GTX_P5
PEG_CRX_GTX_P4
PEG_CRX_GTX_P3
PEG_CRX_GTX_P2
PEG_CRX_GTX_P1
PEG_CRX_GTX_P0
2
1
DIS@ C1
2
1
DIS@ C2
2
1
DIS@ C3
2
1
DIS@ C4
2
1
DIS@ C5
2
1
DIS@ C6
2
1
DIS@ C7
2
1
DIS@ C8
2
1
DIS@ C9
2
1
DIS@ C10
2
1
DIS@ C11
2
1
DIS@ C12
2
1
DIS@ C13
2
1
DIS@ C14
2
1
DIS@ C15
2
1
DIS@ C16
2
1
DIS@ C17
2
1
DIS@ C18
2
1
DIS@ C19
2
1
DIS@ C20
2
1
DIS@ C21
2
1
DIS@ C22
2
1
DIS@ C23
2
1
DIS@ C24
2
1
DIS@ C25
2
1
DIS@ C26
2
1
DIS@ C27
2
1
DIS@ C28
2
1
DIS@ C29
2
1
DIS@ C30
2
1
DIS@ C31
2
1
DIS@ C32
PEG_CRX_GTX_N[0..15] (36)
PEG_CRX_GTX_P[0..15] (36)
C
PEG_PTX_C_DRX_N[0..15] (36)
PEG_PTX_C_DRX_N15
PEG_PTX_C_DRX_N14
PEG_PTX_C_DRX_N13
PEG_PTX_C_DRX_N12
PEG_PTX_C_DRX_N11
PEG_PTX_C_DRX_N10
PEG_PTX_C_DRX_N9
PEG_PTX_C_DRX_N8
PEG_PTX_C_DRX_N7
PEG_PTX_C_DRX_N6
PEG_PTX_C_DRX_N5
PEG_PTX_C_DRX_N4
PEG_PTX_C_DRX_N3
PEG_PTX_C_DRX_N2
PEG_PTX_C_DRX_N1
PEG_PTX_C_DRX_N0
PEG_PTX_C_DRX_P15
PEG_PTX_C_DRX_P14
PEG_PTX_C_DRX_P13
PEG_PTX_C_DRX_P12
PEG_PTX_C_DRX_P11
PEG_PTX_C_DRX_P10
PEG_PTX_C_DRX_P9
PEG_PTX_C_DRX_P8
PEG_PTX_C_DRX_P7
PEG_PTX_C_DRX_P6
PEG_PTX_C_DRX_P5
PEG_PTX_C_DRX_P4
PEG_PTX_C_DRX_P3
PEG_PTX_C_DRX_P2
PEG_PTX_C_DRX_P1
PEG_PTX_C_DRX_P0
DGPU
PEG
PEG_PTX_C_DRX_P[0..15] (36)
B
1 OF 12
HSW-QUAD-CORE-GT2_BGA1364
A
A
Compal Secret Data
Security Classification
Issued Date
2014/02/25
2015/02/25
Deciphered Date
Title
Compal Electronics, Inc.
PROCESSOR(1/7) DMI,FDI,PEG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Rev
1.0
LA-B111P
Tuesday, February 25, 2014
Sheet
1
4
of
59
4
3
2
Follow Intel schematic
review-0930
G50
G51
H_CATERR#
(31) H_PECI
D
1
2
56_0402_5%
H_PROCHOT# R4
E50
D53
H_PROCHOT#_R
(18,45) H_THRMTRIP#
2
C188
100P_0402_50V8J (15) CLK_CPU_DPLL#
2 @ESD@
(15) CLK_CPU_DPLL
(15) CLK_CPU_SSC_DPLL#
(15) CLK_CPU_SSC_DPLL
(15) CLK_CPU_DMI#
ESD 9/5
(15) CLK_CPU_DMI
R5
10K_0402_5%
(18) CPU_PLTRST#
CLK_CPU_DPLL#
CLK_CPU_DPLL
CLK_CPU_SSC_DPLL#
CLK_CPU_SSC_DPLL
CLK_CPU_DMI#
CLK_CPU_DMI
D52
F50
AP48
L54
AC6
AE6
V6
Y6
AB6
AA6
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_DRAMRST
PROCHOT
THERMTRIP
PM_SYNC
PWRGOOD
SM_DRAMPWROK
PLTRSTIN
DPLL_REF_CLKN
DPLL_REF_CLKP
SSC_DPLL_REF_CLKN
SSC_DPLL_REF_CLKP
BCLKN
BCLKP
PRDY
PREQ
TCK
TMS
TRST
TDI
TDO
DBR
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
CLOCK
1
1
(18) H_CPUPWRGD
H_PM_SYNC
H_CPUPWRGD
PM_SYS_PWRGD_BUF
CPU_PLTRST#
CATERR
PECI
PWR
(14) H_PM_SYNC
MISC
PROC_DETECT
DDR3
T1
+1.35V
HASWELL_BGA_E
@
U1B
C51
JTAG
1
2
R3
62_0402_5%
THERMAL
Note:
PECI/THERMTRIP:
Trace width=4 mils ,Spacing=18mil
Zo=50 ohm
2
+VCCIO_OUT
(31) H_PROCHOT#
1
R174
470_0402_5%
BB51
BB53
BB52
BE51
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
H_DRAMRST#
N53
N52
N54
M51
M53
N49
M49
F53
XDP_PRDY#
XDP_PREQ#
XDP_TCLK
XDP_TMS
XDP_TRST#
XDP_TDI
XDP_TDO
XDP_DBRESET#
R51
R50
P49
N50
R49
P53
U51
P51
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7
R2 1
T3
T2
1
2
@ESD@
2
1
5
DDR3_DRAMRST# (11,12)
1 0.1U_0402_16V7K
C33
@ESD@
2
0_0402_5%
V0.3
V1.0
C187
100P_0402_50V8J
D
ESD 9/5
T4
T5
T6
T7
T8
T9
T10
T11
Place near SODIMM side,
remove by SIT phase
2 OF 12
HSW-QUAD-CORE-GT2_BGA1364
C
C
U1L
A3
A4
DC_TEST_B3_A3
A51
A52
A53
DC_TEST_A52_B52
DC_TEST_A53_B53
B2
B3
DC_TEST_C3_B2
DC_TEST_B3_A3
DC_TEST_A52_B52
DC_TEST_A53_B53
DC_TEST_B54_C54
DC_TEST_BE1_BD1
DC_TEST_BE54_BD54
DC_TEST_BE1_BD1
DC_TEST_BE2_BF2
DC_TEST_BE3_BF3
DC_TEST_BE52_BF52
DC_TEST_BE53_BF53
DC_TEST_BE54_BD54
DC_TEST_BE2_BF2
DC_TEST_BE3_BF3
SM_DRAMPWROK with DDR Power Gating Topology
+3V_PCH
1
DS3@
R152
100K_0402_5%
2
B
A
3
DAISY_CHAIN_NCTF_C54
DAISY_CHAIN_NCTF_D1
DAISY_CHAIN_NCTF_D54
C1
C2
C3
C54
D1
DDR3 COMPENSATION SIGNALS
DC_TEST_BE52_BF52
DC_TEST_BE53_BF53
SM_RCOMP0
R6 1
2 100_0402_1%
SM_RCOMP1
R8 1
2 75_0402_1%
SM_RCOMP2
DC_TEST_C1_C2
DC_TEST_C1_C2
DC_TEST_C3_B2
R9 1
2 100_0402_1%
DC_TEST_B54_C54
Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mils
D54
DAISY_CHAIN_NCTF_BC1
DAISY_CHAIN_NCTF_BC54
DAISY_CHAIN_NCTF_BD1
PU/PD for JTAG signals
B
DAISY_CHAIN_NCTF_BD54
DAISY_CHAIN_NCTF_BE1
DAISY_CHAIN_NCTF_BE2
DAISY_CHAIN_NCTF_BE3
DAISY_CHAIN_NCTF_BE52
DAISY_CHAIN_NCTF_BE53
DAISY_CHAIN_NCTF_BE54
DAISY_CHAIN_NCTF_BF2
DAISY_CHAIN_NCTF_BF3
DAISY_CHAIN_NCTF_BF4
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
AN35
AN37
AF9
AE9
G14
G17
AD45
AG45
+3VS
XDP_DBRESET# R11
2
XDP_TMS
XDP_TDI
2
2
1 1K_0402_5%
+1.05VS
R12
R13
@
@
RP1
1
2
3
4
XDP_TDO
XDP_TCLK
XDP_TRST#
R7
1.8K_0402_1%
1 51_0402_5%
1 51_0402_5%
8
7
6
5
51_0804_8P4R_5%
DS3@
TMS/TDI no require pull high on Check list
12 OF 12
HSW-QUAD-CORE-GT2_BGA1364
4
74AHC1G09GW_TSSOP5
PM_SYS_PWRGD_BUF
R10
3.3K_0402_1%
2
2
DS3@
C191
0.01U_0402_16V7K
1
DAISY_CHAIN_NCTF_B52
DAISY_CHAIN_NCTF_B53
DAISY_CHAIN_NCTF_B54
DAISY_CHAIN_NCTF_C1
DAISY_CHAIN_NCTF_C2
DAISY_CHAIN_NCTF_C3
BF51
BF52
BF53
U6
O
2
(14) PM_DRAM_PWRGD
DAISY_CHAIN_NCTF_B2
DAISY_CHAIN_NCTF_B3
2
1
(14,31) SYS_PWROK
P
5
2
2
DS3@
R153
100K_0402_5%
+1.35V_CPU_VDDQ
C192 @
0.1U_0402_16V7K
DAISY_CHAIN_NCTF_A51
DAISY_CHAIN_NCTF_A52
DAISY_CHAIN_NCTF_A53
DAISY_CHAIN_NCTF_BF51
DAISY_CHAIN_NCTF_BF52
DAISY_CHAIN_NCTF_BF53
G
1
1
BD54
BE1
BE2
BE3
BE52
BE53
BE54
BF2
BF3
BF4
DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4
1
+3V_PCH
BC1
BC54
BD1
HASWELL_BGA_E
1
B
B52
B53
B54
@
R70
1
2 0_0402_5%
NODS3@
A
A
Compal Secret Data
Security Classification
Issued Date
2014/02/25
2015/02/25
Deciphered Date
Title
Compal Electronics, Inc.
PROCESSOR(2/7) PM,XDP,CLK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
LA-B111P
Date:
5
4
3
2
Sheet
Tuesday, February 25, 2014
1
5
of
59
5
4
D
U1C
(11) DDR_A_D[0..63]
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
C
B
+SM_VREF
+SA_DIMM_VREFDQ
+SB_DIMM_VREFDQ
AH54
AH52
AK51
AK54
AH53
AH51
AK52
AK53
AN54
AN52
AR51
AR53
AN53
AN51
AR52
AR54
AV52
AV53
AY52
AY51
AV51
AV54
AY54
AY53
AY47
AY49
BA47
BA45
AY45
AY43
BA49
BA43
BF14
BC14
BC11
BF11
BE14
BD14
BD11
BE11
BC9
BE9
BE6
BC6
BD9
BF9
BE5
BD6
BB4
BC2
AW3
AW2
BB3
BB2
AW4
AW1
AU3
AU1
AR1
AR4
AU2
AU4
AR2
AR3
AM6
+SM_VREF
+SA_DIMM_VREFDQ AR6
+SB_DIMM_VREFDQ AN6
BC53
@
3
2
HASWELL_BGA_E
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
RSVD
SA_CKN0
SA_CK0
SA_CKE0
SA_CKN1
SA_CK1
SA_CKE1
SA_CKN2
SA_CK2
SA_CKE2
SA_CKN3
SA_CK3
SA_CKE3
SA_CS#0
SA_CS#1
SA_CS#2
SA_CS#3
SA_ODT0
SA_ODT1
SA_ODT2
SA_ODT3
SA_BS0
SA_BS1
SA_BS2
VSS
SA_RAS
SA_WE
SA_CAS
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
SM_VREF
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
D
@
SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7
RSVD
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
BD31
BE25 M_CLK_DDR#0
BF25 M_CLK_DDR0
BE34 DDR_CKE0_DIMMA
BD25 M_CLK_DDR#1
BC25 M_CLK_DDR1
BF34 DDR_CKE1_DIMMA
BE23
BF23
BC34
BD23
BC23
BD34
BE16 DDR_CS0_DIMMA#
BC17 DDR_CS1_DIMMA#
BE17
BD16
BC16 M_ODT0
BF16 M_ODT1
BF17
BD17
BC20 DDR_A_BS0
BD21 DDR_A_BS1
BD32 DDR_A_BS2
BC21
BF20 DDR_A_RAS#
BF21 DDR_A_WE#
BE21 DDR_A_CAS#
BD28 DDR_A_MA0
BD27 DDR_A_MA1
BF28 DDR_A_MA2
BE28 DDR_A_MA3
BF32 DDR_A_MA4
BC27 DDR_A_MA5
BF27 DDR_A_MA6
BC28 DDR_A_MA7
BE27 DDR_A_MA8
BC32 DDR_A_MA9
BD20 DDR_A_MA10
BF31 DDR_A_MA11
BC31 DDR_A_MA12
BE20 DDR_A_MA13
BE32 DDR_A_MA14
BE31 DDR_A_MA15
AJ52 DDR_A_DQS#0
AP53 DDR_A_DQS#1
AW52 DDR_A_DQS#2
AY46 DDR_A_DQS#3
BD12 DDR_A_DQS#4
BE7 DDR_A_DQS#5
BA3 DDR_A_DQS#6
AT2 DDR_A_DQS#7
AW39
AJ53 DDR_A_DQS0
AP52 DDR_A_DQS1
AW53 DDR_A_DQS2
BA46 DDR_A_DQS3
BE12 DDR_A_DQS4
BD7 DDR_A_DQS5
BA2 DDR_A_DQS6
AT3 DDR_A_DQS7
AW40
HASWELL_BGA_E
U1D
(12) DDR_B_D[0..63]
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
M_CLK_DDR#0 (11)
M_CLK_DDR0 (11)
DDR_CKE0_DIMMA (11)
M_CLK_DDR#1 (11)
M_CLK_DDR1 (11)
DDR_CKE1_DIMMA (11)
DDR_CS0_DIMMA# (11)
DDR_CS1_DIMMA# (11)
M_ODT0 (11)
M_ODT1 (11)
DDR_A_BS0 (11)
DDR_A_BS1 (11)
DDR_A_BS2 (11)
DDR_A_RAS# (11)
DDR_A_WE# (11)
DDR_A_CAS# (11)
DDR_A_MA[0..15] (11)
DDR_A_DQS#[0..7] (11)
DDR_A_DQS[0..7] (11)
AC54
AC52
AE51
AE54
AC53
AC51
AE52
AE53
AU47
AU49
AV43
AV45
AU43
AU45
AV47
AV49
BC49
BE49
BD47
BC47
BD49
BD50
BE47
BF47
BE44
BD44
BC42
BF42
BF44
BC44
BD42
BE42
BA16
AU16
BA15
AV15
AY16
AV16
AY15
AU15
AU12
AY12
BA10
AU10
AV12
BA12
AY10
AV10
AU8
BA8
AV6
BA6
AV8
AY8
AU6
AY6
AM2
AM3
AK1
AK4
AM1
AM4
AK2
AK3
1
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
RSVD
SB_CKN0
SB_CK0
SB_CKE0
SB_CKN1
SB_CK1
SB_CKE1
SB_CKN2
SB_CK2
SB_CKE2
SB_CKN3
SB_CK3
SB_CKE3
SB_CS#0
SB_CS#1
SB_CS#2
SB_CS#3
SB_ODT0
SB_ODT1
SB_ODT2
SB_ODT3
SB_BS0
SB_BS1
SB_BS2
VSS
SB_RAS
SB_WE
SB_CAS
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7
RSVD
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
RSVD
BA40
AY40
BA39
AY39
AV40
AU40
AV39
AU39
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
3 OF 12
HSW-QUAD-CORE-GT2_BGA1364
AY36
AW27 M_CLK_DDR#2
AV27 M_CLK_DDR2
AU36 DDR_CKE2_DIMMB
AW26 M_CLK_DDR#3
AV26 M_CLK_DDR3
AU35 DDR_CKE3_DIMMB
BA26
AY26
AV35
BA27
AY27
AV36
BA20 DDR_CS2_DIMMB#
AY19 DDR_CS3_DIMMB#
AU19
AW20
AY20 M_ODT2
BA19 M_ODT3
AV19
AW19
AY23 DDR_B_BS0
BA23 DDR_B_BS1
BA36 DDR_B_BS2
AU30
AV23 DDR_B_RAS#
AW23 DDR_B_WE#
AV20 DDR_B_CAS#
BA30 DDR_B_MA0
AW30 DDR_B_MA1
AY30 DDR_B_MA2
AV30 DDR_B_MA3
AW32 DDR_B_MA4
AY32 DDR_B_MA5
AT30 DDR_B_MA6
AV32 DDR_B_MA7
BA32 DDR_B_MA8
AU32 DDR_B_MA9
AU23 DDR_B_MA10
AY35 DDR_B_MA11
AW35 DDR_B_MA12
AU20 DDR_B_MA13
AW36 DDR_B_MA14
BA35 DDR_B_MA15
M_CLK_DDR#2 (12)
M_CLK_DDR2 (12)
DDR_CKE2_DIMMB (12)
M_CLK_DDR#3 (12)
M_CLK_DDR3 (12)
DDR_CKE3_DIMMB (12)
DDR_CS2_DIMMB# (12)
DDR_CS3_DIMMB# (12)
M_ODT2 (12)
M_ODT3 (12)
DDR_B_BS0 (12)
DDR_B_BS1 (12)
DDR_B_BS2 (12)
DDR_B_RAS# (12)
DDR_B_WE# (12)
DDR_B_CAS# (12)
DDR_B_MA[0..15] (12)
C
DDR_B_DQS#[0..7] (12)
AD52 DDR_B_DQS#0
AU46 DDR_B_DQS#1
BD48 DDR_B_DQS#2
BD43 DDR_B_DQS#3
AW16 DDR_B_DQS#4
AW10 DDR_B_DQS#5
AW8 DDR_B_DQS#6
AL2 DDR_B_DQS#7
BE38
AD53 DDR_B_DQS0
AV46 DDR_B_DQS1
BE48 DDR_B_DQS2
BE43 DDR_B_DQS3
AW15 DDR_B_DQS4
AW12 DDR_B_DQS5
AW6 DDR_B_DQS6
AL3 DDR_B_DQS7
BD38
DDR_B_DQS[0..7] (12)
B
BF39
BE39
BF37
BE37
BD39
BC39
BC37
BD37
4 OF 12
HSW-QUAD-CORE-GT2_BGA1364
A
A
Compal Secret Data
Security Classification
Issued Date
2014/02/25
2015/02/25
Deciphered Date
Title
PROCESSOR(3/7) DDRIII
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
LA-B111P
Date:
5
4
3
2
Tuesday, February 25, 2014
Sheet
1
6
of
59
5
4
3
2
1
D
D
COMPENSATION PU FOR eDP
+VCOMP_OUT
@
HASWELL_BGA_E
EDP_COMP
24.9_0402_1%
C
C16
D16
A16
B16
EDP_AUXN
EDP_AUXP
EDP_HPD
DDIC_TXN0
DDIC_TXP0
DDIC_TXN1
DDIC_TXP1
DDIC_TXN2
DDIC_TXP2
DDIC_TXN3
DDIC_TXP3
EDP_RCOMP
EDP_DISP_UTIL
EDP_TXN0
EDP_TXN1
EDP_TXP0
EDP_TXP1
FDI_TXN0
FDI_TXP0
FDI_TXN1
FDI_TXP1
F15
F14
E14
EDP_CPU_AUX#
EDP_CPU_AUX
EDP_HPD#
C14
A12
D14
B12
EDP_CPU_LANE_N0
EDP_CPU_LANE_N1
EDP_CPU_LANE_P0
EDP_CPU_LANE_P1
AG6
E12
C12
D12
A14
B14
EDP_CPU_LANE_N2
EDP_CPU_LANE_P2
EDP_CPU_LANE_N3
EDP_CPU_LANE_P3
1
R14
EDP_CPU_LANE_N0
EDP_CPU_LANE_N1
EDP_CPU_LANE_P0
EDP_CPU_LANE_P1
(22)
(22)
(22)
(22)
EDP_CPU_LANE_N2
EDP_CPU_LANE_P2
EDP_CPU_LANE_N3
EDP_CPU_LANE_P3
Note:
Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.
(22)
(22)
(22)
(22)
T14
HPD INVERSION FOR EDP
C
+VCCIO_OUT
DDID_TXN2
DDID_TXP2
DDID_TXN3
DDID_TXP3
1
EDP_HPD#
DDID_TXN0
DDID_TXP0
DDID_TXN1
DDID_TXP1
Q1
DTC124EKAT146_SC59-3
IN
2
V1.0
EDP_HPD (22)
2
10 OF 12
HSW-QUAD-CORE-GT2_BGA1364
3
GND
C17
D17
A17
B17
2
EDP_COMP
EDP_CPU_AUX# (22)
EDP_CPU_AUX (22)
R16 1
C21
D21
A21
B21
C20
D20
A20
B20
DDIB_TXN0
DDIB_TXP0
DDIB_TXN1
DDIB_TXP1
DDIB_TXN2
DDIB_TXP2
DDIB_TXN3
DDIB_TXP3
@
100K_0402_5%
C25
D25
A25
B25
C24
D24
A24
B24
R15 2
TMDS_B_DATA2#_PCH
TMDS_B_DATA2_PCH
TMDS_B_DATA1#_PCH
TMDS_B_DATA1_PCH
TMDS_B_DATA0#_PCH
TMDS_B_DATA0_PCH
TMDS_B_CLK#_PCH
TMDS_B_CLK_PCH
1
HDMI
TMDS_B_DATA2#_PCH
TMDS_B_DATA2_PCH
TMDS_B_DATA1#_PCH
TMDS_B_DATA1_PCH
TMDS_B_DATA0#_PCH
TMDS_B_DATA0_PCH
TMDS_B_CLK#_PCH
TMDS_B_CLK_PCH
OUT
(24)
(24)
(24)
(24)
(24)
(24)
(24)
(24)
10K_0402_5%
U1J
B
B
HPD is a active-high signal from device.
The HPD processor input is
active-low signal.
A
A
Compal Secret Data
Security Classification
Issued Date
2014/02/25
2015/02/25
Deciphered Date
Title
Compal Electronics, Inc.
PROCESSOR(4/7) eDP,DP and HDMI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
LA-B111P
Date:
5
4
3
2
Tuesday, February 25, 2014
Sheet
1
7
of
59
5
4
3
2
1
CFG Straps for Processor
2
CFG2
R17
1K_0402_1%
D
1
D
L51
C
H_CPU_TESTLO
T16
T17
T18
T19
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
F24
F25
F20
AG49
AD49
AC49
AE49
Y50
AB49
V51
W51
Y49
Y54
Y53
W53
U53
V54
R53
R52
L50
L49
E5
RSVD_TP
RSVD_TP
TESTLO_F21
VSS
VSS
VSS
VCC
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD_TP
RSVD_TP
RSVD_TP
R54
Y52
V53
Y51
V52
CFG_RCOMP
CFG16
*
T15
R18
1K_0402_1%
Embedded Display Port Presence Strap
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
CFG4
RSVD
RSVD_TP
RSVD_TP
VSS
VSS
VSS
VSS
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
0:Lane Reversed
CFG4
B50
AH49
AM48
AU27
AU26
BD4
BC4
AL6
F8
RSVD_TP
RSVD_TP
TESTLO_F20
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
definition matches
C
F16
*
G12
G10
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
CFG5
H54
H53
CFG6
H51
H52
2
L52
L53
CFG_RCOMP
CFG16
CFG18
CFG17
CFG19
2
+VCC_CORE
RSVD_TP
RSVD_TP
1: Normal Operation; Lane #
socket pin map definition
CFG2
@ R22
1K_0402_1%
N51
G53
H50
R23 @
1K_0402_1%
1
H_CPU_RSVD
RSVD_TP
RSVD_TP
F1
E1
A5
A6
1
F6
G6
G21
G24
F21
G19
F51
F52
F22
PEG Static Lane Reversal - CFG2 is for the 16x
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
1
BE4
BD3
HASWELL_BGA_E
@
2
U1K
PCIE Port Bifurcation Straps
11 OF 12
HSW-QUAD-CORE-GT2_BGA1364
11: (Default) x16 - Device 1 functions 1 and 2 disabled
CFG[6:5]
*10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
B
1
2
1
2
B
H_CPU_TESTLO
49.9_0402_1%
CFG_RCOMP
49.9_0402_1%
2
H_CPU_RSVD
49.9_0402_1%
R20
1
R21
CFG7
2
R19
1
@ R24
1K_0402_1%
PEG DEFER TRAINING
CFG7
*
1: (Default) PEG Train immediately following xxRESETB
de assertion
0: PEG Wait for BIOS for training
A
A
Compal Secret Data
Security Classification
Issued Date
2014/02/25
2015/02/25
Deciphered Date
Title
Compal Electronics, Inc.
PROCESSOR(5/7) RSVD,CFG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
LA-B111P
Date:
5
4
3
2
Tuesday, February 25, 2014
Sheet
1
8
of
59
5
4
+1.35V_CPU_VDDQ Source
+1.35V
3
+1.35V
+1.35V_CPU_VDDQ
JP@
Note:
Intel Shark Bay
Removed the S3 power reduction circuit.
1
+1.35V_CPU_VDDQ
JP1
2
@
C37
0.1U_0402_16V7K
1
2
1
JP@
2
JUMP_43X118
JP2
2
C36
@
0.1U_0402_16V7K
1
2
1
JUMP_43X118
D
D
@
U1E
+VCC_CORE
HASWELL_BGA_E
+VCC_CORE
+VCC_CORE
U1F
2
VCCSENSE_R
0_0402_5%
R25
@
1
VSSSENSE
(55) VSSSENSE
2
VSSSENSE_R
0_0402_5%
2
VSSSENSE_R
(10)
R26
100_0402_1%
1
R28
C
+VCC_CORE
AN31
L6
M6
AN22
AN18
Broadwell/Haswell
C50
VCCSENSE_R
AH9
0_0805_5%
1 +VCCIO_OUT_R D51
R29 2
1 +PCH_VPROC_R F17
R56 2
AK6
BW@ 0_0603_5%
V0.3
AN33
V1.0
W9
J12
AR49
+VCCIO_OUT
1
R31
(55) VR_SVID_ALRT#
(55) VR_SVID_CLK
(55) VR_SVID_DAT
1
2 43_0402_5%
H_CPU_SVIDALRT#
VR_SVID_CLK
VR_SVID_DAT
1
2
R30
75_0402_1%
Note:
Place the UP resistor close to CPU
2 R33
1
150_0402_1%
+1.05VS
1
2
R32
130_0402_1%
2
Note:
Place the UP resistor close to CPU
+VCCIO_OUT
+PCH_VPROC
+VCOMP_OUT
+VCCIO_OUT
B
R34
10K_0402_5%
@
+VCCIO_OUT
2
+VCC_CORE
Close to CPU
Close to CPU
2
V0.3A
V0.1A
2
@
1
2
1
+
@
2
V0.3A
1
+
2
VSS
PWR_DEBUG
VSS
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
FC_D5
FC_D3
D5
D3
Broadwell/Haswell
+1.05VS
FC_D5
FC_D3
R35
0_0805_5%
BW@
1
1
2
2
2 R36
R37
1K_0402_1%
BW@
C52
C52
330U_D2_2V_Y
330U_D2_2V_Y
2
1
C51
C51
220U_D2_4VM_R15
2
1
C50
10U_0603_6.3V6M
@
1
C49
10U_0603_6.3V6M
2
1
C48
10U_0603_6.3V6M
2
1
VIDALERT
VIDSCLK
VIDSOUT
5 OF 12
HSW-QUAD-CORE-GT2_BGA1364
Close to CPU
C47
10U_0603_6.3V6M
1
C46
10U_0603_6.3V6M
2
@
C45
10U_0603_6.3V6M
2
1
C44
C44
10U_0603_6.3V6M
10U_0603_6.3V6M
1
C43
C43
10U_0603_6.3V6M
10U_0603_6.3V6M
@
C42
10U_0603_6.3V6M
2
C41
10U_0603_6.3V6M
1
A36
A38
A39
A42
A43
A45
A46
A48
AA46
AA47
AA8
AA9
VCC_SENSE
RSVD
VCCIO_OUT
FC_F17
VCOMP_OUT
RSVD
RSVD
RSVD
RSVD
AB45
AB46
AB8
AC46
AC47
AC8
AC9
AD46
AD8
AE46
AE47
AE8
AF8
AG46
AG8
AH46
AH47
AH8
AJ45
AJ46
AK46
AK47
AK8
AL45
AL46
AL8
AL9
AM46
AM47
AM8
AM9
AN10
AN12
AN13
AN14
AN15
AN16
AN17
AN19
AN20
AN21
AN23
AN24
AN25
AN26
AN27
AN29
AN30
AN32
AN34
AN36
AN38
AN39
AN40
AN41
AN42
AN43
AN44
AN45
AN46
AN8
AN9
AP10
AP12
AP13
AP14
AP15
AP16
AP17
AP18
AP19
AP20
AP21
AP22
AP23
AP24
AP25
AP26
AP27
AP29
AP30
AP31
AP32
AP33
AP34
AP35
AP36
AP37
AP38
AP39
AP40
AP41
AP42
AP43
AP44
AP46
AP47
AP8
AP9
AR35
AR37
AR39
AR41
AR43
AR45
AR46
H30
H31
H32
C40 @
C40 @
10U_0603_6.3V6M
10U_0603_6.3V6M
VDDQ DECOUPLING (Follow INTEL DG)
+1.35V_CPU_VDDQ
B51
F19
E52
V49
U49
AM49
W49
V50
AN49
AJ49
AG50
AK49
AJ50
AP49
AB50
AP50
AD50
AM50
RSVD
VCC
VCC
RSVD
RSVD
C39 BW@
0.1U_0402_16V7K
C38
2.2U_0603_10V6K
1
J53
J52
J50
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
B43
B45
B46
B48
C27
C28
C31
C32
C34
C36
C38
C39
C42
C43
C45
C46
C48
D27
D28
D31
D32
D34
D36
D38
D39
D42
D43
D45
D46
D48
E27
E28
E31
E32
E34
E36
E38
E39
E42
E43
E45
E46
E48
F27
F28
F31
F32
F34
F36
F38
F39
F42
F43
F45
F46
F48
G27
G29
G31
G32
G34
G36
G38
G39
G42
G43
G45
G46
G48
H11
H12
H13
H14
H16
H17
H18
H19
H20
H21
H23
H24
H25
H26
H27
H29
1
@
1
VCCSENSE
(55) VCCSENSE
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCST
1
PCH_PWROK
(14,31)
2K_0402_1%
BW@
2
1
2
R27
100_0402_1%
Note:
0 ohm Resistor should be placed
cloose to CPU
RSVD
RSVD
RSVD
RSVD
2
AR29
AR31
AR33
AT13
AT19
AT23
AT27
AT32
AT36
AV37
AW22
AW25
AW29
AW33
AY18
BB21
BB22
BB26
BB27
BB30
BB31
BB34
BB36
BD22
BD26
BD30
BD33
BE18
BE22
BE26
BE30
BE33
+VCC_CORE
VCC_SENSE
J17
J21
J26
J31
1
+1.35V_CPU_VDDQ
@
V0.1A
V0.3A
A
@
2
@
2
2
1
2
C63
C63
22U_0805_6.3V6M
22U_0805_6.3V6M
V0.1A
2
1
C62
22U_0805_6.3V6M
Close to CPU
2
1
C61
22U_0805_6.3V6M
V0.3A
2
1
C60
22U_0805_6.3V6M
2
1
C59
22U_0805_6.3V6M
@
1
C58
22U_0805_6.3V6M
2
1
C57
22U_0805_6.3V6M
@
1
C56
22U_0805_6.3V6M
2
1
C55
C55
22U_0805_6.3V6M
22U_0805_6.3V6M
@
1
C54
C54
22U_0805_6.3V6M
22U_0805_6.3V6M
2
C53
22U_0805_6.3V6M
1
@
6 OF 12
HSW-QUAD-CORE-GT2_BGA1364
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
H33
H34
H36
H37
H38
H39
H40
H42
H43
H45
H46
H48
H8
H9
J10
J14
J19
J24
J29
J33
J36
J37
J38
J39
J40
J42
J43
J45
J46
J48
J8
J9
K38
K40
K43
K44
K45
K46
K48
K8
K9
L37
L38
L39
L40
L42
L43
L44
L46
L47
L8
M37
M38
M39
M40
M42
M43
M44
M45
M46
M8
M9
N37
N38
N39
N40
N42
N43
N44
N46
N47
N8
N9
P45
P46
P8
R46
R47
R8
R9
T45
T46
U46
U47
U8
U9
V45
V46
V8
W46
W47
W8
Y45
Y46
Y8
A27
A28
A31
A32
A34
B27
B28
B31
B32
B34
B36
B38
B39
B42
C
B
A
@
V0.3A
Compal Secret Data
Security Classification
Issued Date
Close to CPU
2014/02/25
Deciphered Date
2015/02/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
PROCESSOR(6/7) PWR
Size
C
Date:
5
HASWELL_BGA_E
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
4
3
2
Document Number
Rev
1.0
LA-B111P
Sheet
Tuesday, February 25, 2014
1
9
of
59
5
4
U1I @
3
2
HASWELL_BGA_E
U1G @
BC10
BC12
BC15
BC18
BC22
BC26
BC3
BC30
BC33
BC36
BC38
BC41
BC43
BC46
BC48
BC5
BC50
BC52
BC7
BD10
BD15
BD18
BD36
BD41
BD46
BD5
BD51
BE10
BE15
BE36
BE41
BE46
BF10
BF12
BF15
BF18
BF22
BF26
BF30
BF33
BF36
BF38
BF41
BF43
BF46
BF48
BF7
C11
C15
C19
C22
C26
C30
C33
C37
C4
C40
C44
C49
C52
C8
D11
D15
D19
D22
D26
D30
D33
D37
D40
D44
D49
D8
E11
E15
E16
E17
E19
E20
E21
E22
E24
E25
E26
E30
E33
E37
E40
E44
E49
E51
E53
E8
F2
F26
F3
F30
F33
F37
F4
F40
F44
F49
F5
G11
G13
G16
D
C
B
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_SENSE
G20
G23
G25
G26
G30
G33
G37
G40
G44
G49
G52
G54
G7
G8
G9
H44
H49
H7
J44
J49
J51
J54
J7
K1
K2
K3
K4
K5
K6
K7
L48
L7
L9
M48
M50
M52
M54
M7
N48
N7
P1
P2
P3
P4
P48
P5
P50
P52
P54
P6
P7
R48
R7
T48
U1
U2
U3
U4
U48
U5
U50
U52
U54
U6
U7
V48
V7
V9
W48
W50
W52
W54
W7
Y48
Y7
Y9
A11
A15
A19
A22
A26
A30
A33
A37
A40
A44
AA1
AA2
AA3
AA4
AA48
AA5
AA7
AB5
AB51
AB52
AB53
AB54
AB7
AB9
AC48
AC5
AC50
AC7
AD48
AD51
AD54
AD7
AD9
AE1
AE2
AE3
AE4
AE48
AE5
AE50
AE7
AF5
AF6
AF7
AG48
AG5
AG51
AG52
AG53
AG54
AG7
AG9
AH1
AH2
AH3
AH4
AH48
AH5
AH50
AH7
U1H @
HASWELL_BGA_E
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AT40
AT42
AT43
AT45
AT46
AT47
AT49
AT5
AT50
AT51
AT52
AT53
AT54
AT6
AT8
AT9
AU13
AU18
AU22
AU25
AU29
AU33
AU37
AU42
AU5
AU9
AV1
AV13
AV18
AV2
AV22
AV25
AV29
AV3
AV33
AV4
AV42
AV5
AV50
AV9
AW13
AW18
AW37
AW42
AW43
AW45
AW46
AW47
AW49
AW5
AW50
AW51
AW54
AW9
AY13
AY22
AY25
AY29
AY33
AY37
AY42
AJ48
AJ51
AJ54
AK48
AK5
AK50
AK7
AK9
AL1
AL4
AL48
AL5
AL7
AM5
AM51
AM52
AM53
AM54
AM7
AN1
AN2
AN3
AN4
AN48
AN5
AN50
AN7
AP51
AP54
AP7
AR12
AR14
AR16
AR18
AR20
AR24
AR26
AR48
AR5
AR50
AR7
AR8
AR9
AT1
AT10
AT12
AT15
AT16
AT18
AT20
AT22
AT25
AT26
AT29
AT33
AT35
AT37
AT39
AT4
7 OF 12
HSW-QUAD-CORE-GT2_BGA1364
HASWELL_BGA_E
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AY50
AY9
B11
B15
B19
B22
B26
B30
B33
B37
B40
B44
B49
B8
BA13
BA18
BA22
BA25
BA29
BA33
BA37
BA4
BA42
BA5
BA50
BA51
BA52
BA53
BA9
BB10
BB11
BB12
BB14
BB15
BB16
BB17
BB18
BB20
BB23
BB25
BB28
BB32
BB33
BB37
BB38
BB39
BB41
BB42
BB43
BB44
BB46
BB47
BB48
BB49
BB5
BB6
BB7
BB9
D
C
8 OF 12
HSW-QUAD-CORE-GT2_BGA1364
B
AR22
AB48
P9
G18
A49
A50
A8
B4
BA1
BA54
BB1
BB54
BD2
BD53
BF49
BF5
BF50
BF6
C53
D2
E54
F54
G1
D50
VSSSENSE_R (9)
A
9 OF 12
HSW-QUAD-CORE-GT2_BGA1364
Compal Secret Data
Security Classification
Issued Date
2014/02/25
2015/02/25
Deciphered Date
Title
Compal Electronics, Inc.
PROCESSOR(7/7) VSS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
LA-B111P
Date:
5
4
3
2
Tuesday, February 25, 2014
Sheet
1
10
of
59
5
4
3
V53.1@A3
(6) DDR_A_D[0..63]
DDR_A_D34
DDR_A_D35
DDR_A_D45
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
V0.3A 2
@
1
2
C87
0.1U_0402_16V7K
1
A
C86
2.2U_0603_10V6K
+3VS
205
207
GND1
BOSS1
GND2
BOSS2
206
208
2
2
1
2
1
2
pin204
C
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
CPU DRIVER
VREF PATH IS
DEFAULT
DDR_CS0_DIMMA#
M_ODT0
M_ODT1
+SM_VREF
DDR_A_BS1 (6)
DDR_A_RAS# (6)
R38
1K_0402_1%
DDR_CS0_DIMMA# (6)
M_ODT0 (6)
R39
1
2
2.2_0402_1%
M_ODT1 (6)
+VREF_CA
DDR_A_D36
DDR_A_D37
1
2
DDR_A_D38
DDR_A_D39
1
2
@
@
V0.3A
*M3+M1:Default Recommendation
M1:VREF_DQ driven by a voltage Divider Network during
Processor power-off state.
M3:VREF_DQ driven by Processor.
+1.35V
Note:
VREF trace width:20 mils at least
Spacing:20mils to other signal/planes
2
DDR_A_BS1
DDR_A_RAS#
M_CLK_DDR1 (6)
M_CLK_DDR#1 (6)
1
M_CLK_DDR1
M_CLK_DDR#1
+VREF_CA
+VREF_CA (12)
2
DDR_A_MA2
DDR_A_MA0
R40
1K_0402_1%
V0.3A
R41
24.9_0402_1%
@
1
DDR_A_MA6
DDR_A_MA4
B
DDR_A_D44
DDR_A_D40
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
+SA_DIMM_VREFDQ
+1.35V
DDR_A_D52
DDR_A_D53
Note:
VREF trace width:20 mils at least
Spacing:20mils to other signal/planes
DDR_A_D54
DDR_A_D55
R42
1K_0402_1%
DDR_A_D60
DDR_A_D61
C85
C85
0.022U_0402_16V7K
DDR_A_D62
DDR_A_D58
2
1
DDR_CKE1_DIMMA (6)
C82
0.022U_0402_16V7K
B
Place near JDIMM1 pin203
DDR_CKE1_DIMMA
C84
2.2U_0603_10V6K
DDR_A_DQS#4
DDR_A_DQS4
2
1
DDR_A_D28
DDR_A_D27
C83
0.1U_0402_16V7K
0.1U_0402_16V7K
DDR_A_D33
DDR_A_D32
2
1
2
DDR_A_MA13
DDR_CS1_DIMMA#
(6) DDR_CS1_DIMMA#
2
1
DDR_A_DQS#7
DDR_A_DQS7
@
DDR_A_D63
DDR_A_D59
SMB_DATA_S3
SMB_CLK_S3
SMB_DATA_S3 (12,16,32)
SMB_CLK_S3 (12,16,32)
1
R43 2
2.2_0402_1%
+VREF_DQ_DIMMA
R44
1K_0402_1%
V0.3A
R45 @
24.9_0402_1%
+0.675VS
A
LCN_DAN06-K4406-0103
SP07000LT00
Compal Secret Data
Security Classification
Issued Date
2014/02/25
2015/02/25
Deciphered Date
Title
Compal Electronics, Inc.
DDRIII-SODIMM SLOT1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
LA-B111P
Date:
5
C81
0.1U_0402_16V7K
0.1U_0402_16V7K
(6) DDR_A_WE#
(6) DDR_A_CAS#
2
1
C80
0.1U_0402_16V7K
DDR_A_WE#
DDR_A_CAS#
2
1
C79
0.1U_0402_16V7K
DDR_A_MA10
DDR_A_BS0
2
1
C78
0.1U_0402_16V7K
0.1U_0402_16V7K
(6) DDR_A_BS0
2
1
@
C77
10U_0603_6.3V6M
M_CLK_DDR0
M_CLK_DDR#0
1
@
C76
10U_0603_6.3V6M
(6) M_CLK_DDR0
(6) M_CLK_DDR#0
@2
1
C75
10U_0603_6.3V6M
10U_0603_6.3V6M
DDR_A_MA3
DDR_A_MA1
2
1
C74
10U_0603_6.3V6M
DDR_A_MA8
DDR_A_MA5
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
@2
1
C73
10U_0603_6.3V6M
DDR_A_MA12
DDR_A_MA9
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
2
DDR_A_DQS#3
DDR_A_DQS3
1
C72
10U_0603_6.3V6M
10U_0603_6.3V6M
DDR_A_BS2
(6) DDR_A_BS2
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
1
DDR_A_D30
DDR_A_D25
C71
10U_0603_6.3V6M
C
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
DDR_A_D22
DDR_A_D23
+1.35V
C69
0.1U_0402_16V7K
0.1U_0402_16V7K
DDR_CKE0_DIMMA
(6) DDR_CKE0_DIMMA
+0.675VS
DDR_A_D17
DDR_A_D21
C68
0.1U_0402_16V7K
DDR_A_D29
DDR_A_D31
DDR_A_D11
DDR_A_D15
C67
0.1U_0402_16V7K
0.1U_0402_16V7K
DDR_A_D26
DDR_A_D24
Layout Note:
Place near JDIMM1
Layout Note:
Place near JDIMM1
DDR3_DRAMRST# (12,5)
C66
1U_0402_6.3V6K
DDR_A_D18
DDR_A_D19
DDR3_DRAMRST#
C70
10U_0603_6.3V6M
DDR_A_DQS#2
DDR_A_DQS2
D
DDR_A_D8
DDR_A_D13
1
DDR_A_D16
DDR_A_D20
DDR_A_D3
DDR_A_D7
2
DDR_A_D14
DDR_A_D10
(6) DDR_A_MA[0..15]
DDR_A_DQS#0
DDR_A_DQS0
1
DDR_A_DQS#1
DDR_A_DQS1
(6) DDR_A_DQS#[0..7]
DDR_A_D4
DDR_A_D5
1
DDR_A_D12
DDR_A_D9
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
1 2
DDR_A_D6
DDR_A_D2
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
2
2
(6) DDR_A_DQS[0..7]
CONN@
1
@
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
2
2
1
C65
C65
0.1U_0402_16V7K
0.1U_0402_16V7K
V0.3A
D
C64
2.2U_0603_10V6K
1
DDR_A_D0
DDR_A_D1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
V576.0@A56.0
V576.0@A56.0
V576.0@A56.0
V576.0@A56.0
JDIMM1
+VREF_DQ_DIMMA
1
+1.35V
DDR3 SO-DIMM A
1 2
+1.35V
2
4
3
2
Tuesday, February 25, 2014
Sheet
1
11
of
59
4
3
2
V53.1@A3
+1.35V
DDR_B_D12
DDR_B_D10
DDR_B_D21
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_BS2
(6) DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
2
R50
0_0402_5%
1
+3VS
A
205
1
2
C114
2
@
0.1U_0402_16V7K
C112
2.2U_0603_10V6K
V0.3A
1
G1
G2
206
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
M_ODT3
M_CLK_DDR3 (6)
M_CLK_DDR#3 (6)
1
1
@
DDR_B_BS1 (6)
DDR_B_RAS# (6)
2
DDR_CS2_DIMMB# (6)
M_ODT2 (6)
1
@
2
2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
M_ODT3 (6)
+VREF_CA (11)
DDR_B_D36
DDR_B_D32
1
2
DDR_B_D35
DDR_B_D39
DDR_B_D41
DDR_B_D45
1
2
@
+SB_DIMM_VREFDQ
+1.35V
B
V0.3A
Note:
VREF trace width:20 mils at least
Spacing:20mils to other signal/planes
DDR_B_DQS#5
DDR_B_DQS5
R46
1K_0402_1%
DDR_B_D47
DDR_B_D43
DDR_B_D53
DDR_B_D49
@
DDR_B_D50
DDR_B_D54
DDR_B_D60
DDR_B_D61
1
R47 2
2.2_0402_1%
+VREF_DQ_DIMMB
R48
1K_0402_1%
V0.3A
R49
24.9_0402_1%
@
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D63
DDR_B_D59
SMB_DATA_S3
SMB_CLK_S3
SMB_DATA_S3 (11,16,32)
SMB_CLK_S3 (11,16,32)
+0.675VS
A
LCN_DAN06-K4806-0103
SP07000M200
Compal Secret Data
Security Classification
Issued Date
2014/02/25
2015/02/25
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
1
C110
0.1U_0402_16V7K
DDR_B_D62
DDR_B_D58
+1.35V
DDR_B_MA2
DDR_B_MA0
C109
C109
0.1U_0402_16V7K
DDR_B_D56
DDR_B_D57
DDR_B_MA6
DDR_B_MA4
C108
0.1U_0402_16V7K
DDR_B_D55
DDR_B_D51
+3VS
C
Layout Note:
Place near JDIMM2
DDR_B_MA11
DDR_B_MA7
C107
0.1U_0402_16V7K
DDR_B_DQS#6
DDR_B_DQS6
DDR_CKE3_DIMMB (6)
DDR_B_MA15
DDR_B_MA14
C96
0.022U_0402_16V7K
DDR_B_D52
DDR_B_D48
DDR_CKE3_DIMMB
pin204
C106
C106
10U_0603_6.3V6M
DDR_B_D46
DDR_B_D42
Place near JDIMM2 pin203
C105
10U_0603_6.3V6M
DDR_B_D40
DDR_B_D44
@2
C104
10U_0603_6.3V6M
DDR_B_D34
DDR_B_D38
2
1
C98
C98
2.2U_0603_10V6K
DDR_B_DQS#4
DDR_B_DQS4
B
2
1
DDR_B_D30
DDR_B_D31
C97
0.1U_0402_16V7K
DDR_B_D33
DDR_B_D37
1
C103
C103
10U_0603_6.3V6M
DDR_B_MA13
DDR_CS3_DIMMB#
(6) DDR_CS3_DIMMB#
2
DDR_B_DQS#3
DDR_B_DQS3
@
C102
10U_0603_6.3V6M
DDR_B_WE#
DDR_B_CAS#
(6) DDR_B_WE#
(6) DDR_B_CAS#
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
1
DDR_B_D25
DDR_B_D29
C101
10U_0603_6.3V6M
(6) DDR_B_BS0
DDR_B_MA10
DDR_B_BS0
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
DDR_B_D19
DDR_B_D18
C100
C100
10U_0603_6.3V6M
M_CLK_DDR2
M_CLK_DDR#2
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
+0.675VS
C99
10U_0603_6.3V6M
(6) M_CLK_DDR2
(6) M_CLK_DDR#2
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
DDR_B_D16
DDR_B_D20
C95
C95
0.1U_0402_16V7K
DDR_CKE2_DIMMB
(6) DDR_CKE2_DIMMB
C
Layout Note:
Place near JDIMM2
DDR3_DRAMRST# (11,5)
DDR_B_D11
DDR_B_D13
C94
0.1U_0402_16V7K
DDR_B_D26
DDR_B_D27
DDR3_DRAMRST#
C93
0.1U_0402_16V7K
DDR_B_D28
DDR_B_D24
D
DDR_B_D8
DDR_B_D14
C92
1U_0402_6.3V6K
DDR_B_D23
DDR_B_D22
DDR_B_D6
DDR_B_D7
2
DDR_B_DQS#1
DDR_B_DQS1
(6) DDR_B_MA[0..15]
DDR_B_DQS#0
DDR_B_DQS0
1
DDR_B_D15
DDR_B_D9
(6) DDR_B_DQS#[0..7]
2
DDR_B_D2
DDR_B_D3
(6) DDR_B_DQS[0..7]
DDR_B_D5
DDR_B_D1
1
2
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
1
1
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
CONN@
2
V0.3A
@
C91
0.1U_0402_16V7K
2
C90
2.2U_0603_10V6K
2.2U_0603_10V6K
1
D
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
V576.0@A56.0
V576.0@A56.0
V576.0@A56.0
DDR_B_D0
DDR_B_D4
(6) DDR_B_D[0..63]
+1.35V
JDIMM2
+VREF_DQ_DIMMB
1
1 2
5
4
3
2
Compal Electronics, Inc.
DDRIII-SODIMM SLOT2
Document Number
Rev
1.0
LA-B111P
Tuesday, February 25, 2014
Sheet
1
12
of
59
5
4
3
2
Note:
PCH_RTCX1/PCHRTCX2
Trace length & lt; 1000 mils
Green CLK
PCH_RTCX1
D
D
NOGCLK@
1
2
R51
10M_0402_5%
+RTCVCC
PCH_RTCX1
R155 1 GCLK@ 2 0_0402_5%
CLK_32K_RTC_XIN (27)
1
INTVRMEN
V0.2
(INTEGRATED SUS 1.05V VR)
* H Integrated VRM enable
L Integrated VRM disable
(INTVRMEN should always be pull high.)
1
2
Y1 NOGCLK@
2
32.768KHZ 9PF 20PPM 9H03200033
1
2
9P_0402_50V_D
PCH_INTVRMEN
PCH_RTCX2
SM_INTRUDER#
2 330K_0402_5%
NOGCLK@ C116
2 1M_0402_5%
1
9P_0402_50V_D
1
R53
NOGCLK@ C115
R52
1
：
：
V0.2
+3VS
@
2 1K_0402_5%
HDA_SPKR
Note: +RTCVCC
Need to check with PWR update
ME_FLASH
2
1
2
1U_0402_6.3V6K
EMI
RP2
8
7
6
5
(26) HDA_SYNC_AUDIO
(26) HDA_SDOUT_AUDIO
(26) HDA_RST_AUDIO#
(26) HDA_BITCLK_AUDIO
1
2
3
4
SHORT CLEAR ME RTC REGISTER
HDA_SYNC
ME_FLASH
HDA_RST#
HDA_BIT_CLK
PCH_RTCX1
B5
PCH_RTCX2
B4
B9
PCH_SRTCRST#
PCH_RTCRST#
1
* Low = Disabled (Default)
High = Enabled [Flash Descriptor Security Override]
CLRP2
SHORT PADS
2
R54 20K_0402_5%
1
2
R55 20K_0402_5%
C117
CLRP1
OPEN SAVE ME RTC REGISTER
SM_INTRUDER#
A8
PCH_INTVRMEN G10
CLRP2
OPEN SAVE CMOS
D9
SHORT CLEAR CMOS
HDA_BIT_CLK
B25
HDA_SYNC
C24
L22
K22
G22
V0.2
F22
ME_FLASH
(31) ME_FLASH
+3VS
B
R59
RP3
(18) PCH_GPIO35
PCH_GPIO35
SATA_LED#
PCH_GPIO21
BBS_BIT0_R
4
3
2
1
+3V_PCH
5
6
7
8
1
R61
1
A24
2 1K_0402_1% PCH_GPIO33
B17
2 10K_0402_5% PCH_GPIO13
@
C22
RTCX2
SATA_TXN_0
SATA_TXP_0
SRTCRST#
SATA_RXN_1
SATA_RXP_1
INTRUDER#
INTVRMEN
SATA_TXN_1
SATA_TXP_1
RTCRST#
SATA_RXN_2
SATA_RXP_2
HDA_BCLK
SATA_TXN_2
SATA_TXP_2
HDA_SYNC
SPKR
SATA_RXN_3
SATA_RXP_3
HDA_RST#
AZALIA
HDA_SDIN0
(26) HDA_SDIN0
EMI@
AL10
HDA_RST#
(26) HDA_SPKR
33_0804_8P4R_5%
A22
HDA_SPKR
SATA_RXN_0
SATA_RXP_0
RTCX1
RTC
1
2
1U_0402_6.3V6K
2
@ 1 1K_0402_5%
1
2
1
C118
R60
CLRP1 mask
SHORT PADS
+3V_PCH
C
LPT_PCH_M_EDS
U2A
+RTCVCC
HDA_SDI0
SATA
1
R58
HIGH= Enable ( No Reboot )
* LOW= Disable (Default)
HDA_SDI1
SATA_RXN4/PERN1
SATA_RXP4/PERP1
HDA_SDI2
HDA_SDI3
SATA_TXN4/PETN1
SATA_TXP4/PETP1
HDA_SDO
SATA_RXN5/PERN2
SATA_RXP5/PERP2
DOCKEN#/GPIO33
HDA_DOCK_RST#/GPIO13
SATA_TXN5/PETN2
SATA_TXP5/PETP2
SATA_RCOMP
10K_0804_8P4R_5%
SATALED#
2 R62
1
51_0402_5%
T25
T26
T27
SATA Impedance Compensation
PCH_JTAG_TMS AD1
PCH_JTAG_TDI AE2
PCH_JTAG_TDO AD3
F8
+1.5VS
1
PCH_JTAG_TCK AB3
C26
2
T20
R66
Note:
Trace width:4mils
Place the resistor to PCH & lt; 500 mils, to 1.5V & lt; 100 mils.Avoid
routing next to clock pins.
PCH_JTAG_RST#AB6
JTAG_TCK
SATA0GP/GPIO21
JTAG_TMS
SATA1GP/GPIO19
JTAG_TDI
JTAG
V0.2
SATA_COMP
7.5K_0402_1%
SATA_TXN_3
SATA_TXP_3
SATA_IREF
JTAG_TDO
TP9
TP25
TP8
BC8
BE8
C
AW8
AY8
BC10
BE10
HM86 NA
AV10
AW10
BB9
BD9
AY13
AW13
BC12
BE12
HM86 NA
AR13
AT13
BD13
BB13
SATA_PRX_DTX_N4
SATA_PRX_DTX_P4
AV15
AW15
SATA_PTX_DRX_N4
SATA_PTX_DRX_P4
SATA_PRX_DTX_N4 (29)
SATA_PRX_DTX_P4 (29)
HDD
SATA_PTX_DRX_N4 (29)
SATA_PTX_DRX_P4 (29)
BC14
BE14
B
AP15
AR15
AY5 SATA_COMP
AP3 SATA_LED#
SATA_LED# (33)
AT1 PCH_GPIO21
AU2
BBS_BIT0_R
BD4
+1.5VS
BA2
BB2
TP22
TP20
1 OF 11
DH82HM86-SR17E-C2_FCBGA695
A
A
Compal Secret Data
Security Classification
Issued Date
2014/02/25
2015/02/25
Deciphered Date
Title
Compal Electronics, Inc.
PCH (1/9) SATA,HDA,SPI, LPC, XDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
LA-B111P
Date:
5
4
3
2
Tuesday, February 25, 2014
Sheet
1
13
of
59
5
4
(4) DMI_CTX_PRX_N2
(4) DMI_CTX_PRX_N3
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
AP17
AV20
(4) DMI_CTX_PRX_P0
(4) DMI_CTX_PRX_P1
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
AY22
AP20
(4) DMI_CTX_PRX_P2
(4) DMI_CTX_PRX_P3
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
AR17
AW20
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
BD21
BE20
D
(4) DMI_CRX_PTX_N0
(4) DMI_CRX_PTX_N1
BB21
BC20
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
(4) DMI_CRX_PTX_P2
(4) DMI_CRX_PTX_P3
BD17
BE18
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
(4) DMI_CRX_PTX_P0
(4) DMI_CRX_PTX_P1
BB17
BC18
BE16
+1.5VS
AW17
SUSACK# is only used on platform
that support the Deep Sx state.
R71
+1.5VS
1
AV17
2
DMI_RCOMP AY17
7.5K_0402_1%
SUSWARN#_R 1
R150
(18) SYS_RST#
2
R72 1
100K_0402_1%
(31,5) SYS_PWROK
R6
AM1
SYS_PWROK
@
AD7
F10
PCH_PWROK
(31,9) PCH_PWROK
2 R73
1 10K_0402_5%
AB7
PM_DRAM_PWRGD
H3
EC_RSMRST#
J2
DS3@ 2 SUSWARN#_R
0_0402_5%
PBTN_OUT#
J4
(5) PM_DRAM_PWRGD
(31) EC_RSMRST#
C
DS3@ 2 SUSACK#_R
0_0402_5%
SYS_RST#
1
R151
(31) SUSWARN#
(31) PBTN_OUT#
K1
E6
AC_PRESENT_R
(31) AC_PRESENT_R
K7
PCH_GPIO72
N4
RI#
(18) RI#
AB10
D2
FDI_RXN_0
DMI_RXN_2
DMI_RXN_3
FDI_RXN_1
DMI_RXP_0
DMI_RXP_1
FDI_RXP_0
FDI_RXP_1
DMI_RXP_2
DMI_RXP_3
TP16
DMI_TXN_0
DMI_TXN_1
TP5
DMI
FDI
TP15
DMI_TXN_2
DMI_TXN_3
TP10
DMI_TXP_0
DMI_TXP_1
FDI_CSYNC
FDI_INT
DMI_TXP_2
DMI_TXP_3
FDI_IREF
DMI_IREF
TP17
TP12
TP13
TP7
FDI_RCOMP
AJ35
T45
AL35
U44
AJ36
V45
AL36
M43
AV43
M45
AY45
N42
AV45
N44
AW44
U40
AL39
FDI_CSYMC
AL40
U39
(4)
PCH_PWM
AR44
R148 1
INTEL Recommend
FDI_IREF and FDI_RCOMP can floating
DMI_RCOMP
SUSACK#
DSWVRMEN
SYS_RESET#
DPWROK
SYS_PWROK
WAKE#
PWROK
CLKRUN#
System Power
Management
APWROK
SUS_STAT#/GPIO61
DRAMPWROK
SUSCLK/GPIO62
RSMRST#
SLP_S5#/GPIO63
SUSWARN#/SUSPWRNACK/GPIO30
SLP_S4#
PWRBTN#
SLP_S3#
ACPRESENT/GPIO31
SLP_A#
BATLOW#/GPIO72
SLP_SUS#
RI#
PMSYNCH
TP21
SLP_LAN#
C8
PCH_DPWROK
1 NODS3@2
EC_RSMRST#
R172
0_0402_5%
PCIE_WAKE#
SUSCLK
B13
DGPU_PWR_EN
C12
BBS_BIT1
Y7
PM_SLP_S5# (31)
A10
PCH_GPIO55
T23
*
SUSCLK (28)
C10
PCH_GPIO53
T21
C6
DDPB_CTRLDATA
VGA_RED
DDPC_CTRLCLK
VGA_DDC_CLK
DDPC_CTRLDATA
VGA_DDC_DATA
DDPD_CTRLCLK
VGA_HSYNC
DDPD_CTRLDATA
VGA_VSYNC
DAC_IREF
VGA_IRTN
AL6
EDP_BKLTCTL
EDP_BKLTEN
DDPB_AUXN
DDPC_AUXN
DDPB_AUXP
DDPC_AUXP
EDP_VDDEN
DDPD_AUXP
DDPB_HPD
PIRQA#
DDPC_HPD
PIRQB#
DDPD_HPD
R40 HDMICLK_NB
HDMICLK_NB
(16,24)
R39 HDMIDAT_NB
HDMIDAT_NB
(16,24)
R35
R36
N40
D
N38
H45
K43
J42
H43
K45
J44
K40
TMDS_B_HPD
H39
PIRQD#
PIRQE#/GPIO2
GPIO50
PIRQF#/GPIO3
PCI
GPIO52
PIRQG#/GPIO4
GPIO54
PIRQH#/GPIO5
GPIO51
PME#
GPIO53
PLTRST#
GPIO55
DH82HM86-SR17E-C2_FCBGA695
G17
PCH_GPIO2
F17
GPU_EVENT#
L15
GC6_FB_EN
M15
GPU_ALL_PGOOD
SLP_A#
F1
SLP_SUS#
T24
GPU_EVENT#
GC6_FB_EN
(36)
(36,38)
GPU_ALL_PGOOD
(45)
AD10
Y11 PCH_PLTRST#
1
5 OF 11
2
PM_SLP_S3# (31)
F3
(24)
K38
PIRQC#
PM_SLP_S4# (31)
H1
C193
100P_0402_50V8J
@ESD@
C
SLP_A# can be left NC when IAMT is
not support on the platfrom
SLP_SUS# (31)
AY3 H_PM_SYNC
G5
DGPU_HOLD_RST# A12
(36) DGPU_HOLD_RST#
(31,45) DGPU_PWR_EN
SUS_STAT#
M20
(18,28)
AN7 PM_CLKRUN#
Y6
K17
PCI_PIRQD#
PCIE_WAKE#
U7
L20
PCI_PIRQC#
DSWODVREN
L13
K3
H20
PCI_PIRQB#
2 7.5K_0402_1%
G36
PCI_PIRQA#
(22) PCH_ENVDD
AU44
K36
PCH_ENVDD
(31) ENBKL
N36
ENBKL
(22) PCH_PWM
+1.5VS
AU42
DDPB_CTRLCLK
VGA_GREEN
DDPD_AUXN
FDI_INT (4)
AT45
VGA_BLUE
LVDS
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
(4) DMI_CRX_PTX_N2
(4) DMI_CRX_PTX_N3
LPT_PCH_M_EDS
U2E
DMI_RXN_0
DMI_RXN_1
DISPLAY
AW22
AR20
1
CRT
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
2
LPT_PCH_M_EDS
U2B
(4) DMI_CTX_PRX_N0
(4) DMI_CTX_PRX_N1
3
H_PM_SYNC
(5)
SLP_LAN# can be left NC if no use
integrated LAN.
SLP_WLAN#/GPIO29
DH82HM86-SR17E-C2_FCBGA695
4 OF 11
+RTCVCC
ESD 9/5
R75
1
EC_RSMRST#
1 100P_0402_50V8J
+3VS
1
330K_0402_5%
2
330K_0402_5%
SYS_PWROK
C190 2
2
R77
DSWODVREN
@ESD@
1 100P_0402_50V8J
C189 2
@
BBS_BIT1
2 R76
V0.2
1 10K_0402_5%
DGPU_HOLD_RST#
R146 2 DIS@
1 10K_0402_5%
@ESD@
DSWODVREN - On Die DSW VR Enable
H Enable (DEFAULT)
L Disable
：
：
*
+3VALW
B
SATA_SLPD
(BBS_BIT0)
0
1
RP4
(18,28) W_DISABLE#1
(18,31) GATEA20
(18,31) KB_RST#
(18,28) W_DISABLE#2
APWROK can be connect to
PWROK if iAMT disable
5
6
7
8
W_DISABLE#1
GATEA20
KB_RST#
W_DISABLE#2
4
3
2
1
2 0_0402_5%
LPC
0
B
PCI
1
1
* SPI
V0.3A
1
V0.2
GPIO51 needs pull up 10k to ensure proper behavior.
2
33_0402_5%
R74
+3VS
+3VS
1
2
3
4
@
U3
8.2K_0804_8P4R_5%
+3VS
AC_PRESENT_R
V0.2
(25,28,31,34,36)
V0.2
1
@
1
2 R117
GPIO55
10K_0402_5%
1
@
2 R173
10K_0402_5%
1
@
2 R84
1 10K_0402_5%
1
PCH_PLTRST#
2
10K_0402_5%
1
10K_0402_5%
2
V0.3
R78
100K_0402_5%
Low=A16 swap
override/Top-Block
PCI_GNT3# Swap Override enabled
High=Default
Follow Intel schematic
review-0930
+3V_PCH
IN2
A16 swap overide Strap/Top-Block
Swap Override jumper
PM_CLKRUN#
A
IN1
2 R113
2
10K_0402_5%
GPU_EVENT#
2 R82
@
1
GPU_ALL_PGOOD
2 8.2K_0402_5%
10K_0402_5%
PCH_GPIO2
1 R80
OUT
2 1K_0402_5%
DGPU_PWR_EN
+3VS
PLT_RST#
2 10K_0402_5%
1
1
3
+3VS
CLKRUN#:
External pull up to core well is required.
R83
R79
PCH_GPIO55
4
MC74VHC1G08DFT2G SC70 5P
VCC
8
7
6
5
PCI_PIRQC#
PCI_PIRQB#
PCI_PIRQA#
PCI_PIRQD#
Follow Intel schematic
review-0930
R81 @
1
2
200K_0402_5%
(31)
Reserved (NAND)
RP5
+3V_PCH
DPWROK_EC
Boot BIOS Location
1
10K_0804_8P4R_5%
SUSACK# and SUSWARN# can be tied together if
EC does not want to involve in the handshake
mechanism for the Deep Sleep state entry and exit.
R171 1 DS3@
PCH_DPWROK
0
0
+3VS
PCH_GPIO72
5
2 10K_0402_5%
GND
1
R149
Boot BIOS Strap (GPIO51)
BBS_BIT1
*
2 R154
EC_RSMRST#
1 R339
A
SUSCLK
RP15
8
7
6
5
1 PCH_GPIO28
2 SUSWARN#_R
3
4 PCH_GPIO24
PCH_GPIO28
(18)
PCH_GPIO24
@
(18)
Compal Secret Data
Security Classification
Issued Date
10K_0804_8P4R_5%
2014/02/25
Deciphered Date
2015/02/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
PCH (2/9) PCIE, SMBUS, CLK
Size
C
Date:
5
4
3
2
Document Number
Rev
1.0
LA-B111P
Sheet
Tuesday, February 25, 2014
1
14
of
59
5
4
3
2
1
LPT_PCH_M_EDS
U2C
D
D
Y43
Y45
PCH_GPIO73
AB1
AA44
AA42
PCH_GPIO18
CLK_PCIE_WLAN1#
(28) CLK_PCIE_WLAN1#
WLAN
CLK_PCIE_WLAN1
(28) CLK_PCIE_WLAN1
CLKREQ_WLAN#
(28) CLKREQ_WLAN#
LAN
CLK_PCIE_LAN#
CLK_PCIE_LAN
CLKREQ_LAN#
(25) CLK_PCIE_LAN#
(25) CLK_PCIE_LAN
(18,25) CLKREQ_LAN#
AB45
AF3
AD43
AD45
T3
PCH_GPIO26
AF43
AF45
V3
CLKREQ_CR#
AE44
AE42
AA2
PCH_GPIO45
(17) PCH_GPIO26
CR
AF1
AB43
AB40
AB39
AE4
CLK_PCIE_CR#
CLK_PCIE_CR
(34) CLK_PCIE_CR#
(34) CLK_PCIE_CR
(34) CLKREQ_CR#
C
AJ44
AJ42
PCH_GPIO46
Y3
AH43
EMI
CLK_PCI_LPBACK
(31) CLK_PCI_EC
22_0402_5% 1
22_0402_5% 1
EMI@ 2 R90
EMI@ 2 R91
AH45
CLK_PCI_LPBACK_R D44
CLK_PCI_EC_R
E44
B42
F41
A40
CLKOUT_PCIE_N_0
CLKOUT_PEG_A
CLKOUT_PCIE_P_0
CLKOUT_PEG_A_P
PCIECLKRQ0#/GPIO73
PEGA_CLKRQ#/GPIO47
CLKOUT_PCIE_N_1
CLKOUT_PCIE_P_1
CLKOUT_PEG_B
CLKOUT_PEG_B_P
PCIECLKRQ1#/GPIO18
PEGB_CLKRQ#/GPIO56
CLKOUT_PCIE_N_2
CLKOUT_DMI
CLKOUT_PCIE_P_2
CLKOUT_DMI_P
PCIECLKRQ2#/GPIO20/SMI#
CLKOUT_DP
CLKOUT_DP_P
CLKOUT_PCIE_N_3
CLKOUT_PCIE_P_3
PCIECLKRQ3#/GPIO25
CLKOUT_PCIE_N_4
CLKOUT_PCIE_P_4
PCIECLKRQ4#/GPIO26
CLKOUT_DPNS
CLKOUT_DPNS_P
CLKIN_DMI
CLKIN_DMI_P
CLOCK SIGNAL
CLKOUT_PCIE_N5
CLKOUT_PCIE_P_5
PCIECLKRQ5#/GPIO44
CLKOUT_PCIE_N_6
CLKOUT_PCIE_P_6
PCIECLKRQ6#/GPIO45
CLKIN_GND
CLKIN_GND_P
CLKIN_DOT96N
CLKIN_DOT96P
CLKIN_SATA
CLKIN_SATA_P
CLKOUT_PCIE_N_7
CLKOUT_PCIE_P_7
REFCLK14IN
CLKIN_33MHZLOOPBACK
PCIECLKRQ7#/GPIO46
XTAL25_IN
XTAL25_OUT
CLKOUT_ITPXDP
CLKOUTFLEX0/GPIO64
CLKOUT_ITPXDP_P
CLKOUTFLEX1/GPIO65
CLKOUT_33MHZ0
CLKOUTFLEX2/GPIO66
CLKOUT_33MHZ1
CLKOUTFLEX3/GPIO67
CLKOUT_33MHZ2
ICLK_IREF
CLKOUT_33MHZ3
TP19
TP18
CLKOUT_33MHZ4
DIFFCLK_BIASREF
DH82HM86-SR17E-C2_FCBGA695
AB35
CLK_PEG_VGA#
AB36
CLK_PEG_VGA
AF6
CLK_PEG_VGA# (36)
CLK_REQ_VGA#
+3VS
dGPU
RP8
CLK_PEG_VGA (36)
4
3
2
1
CLK_REQ_VGA# (36)
Y39
5
6
7
8
PCH_GPIO49
PCH_GPIO49 (18)
PCH_GPIO18
CLKREQ_WLAN#
Y38
10K_0804_8P4R_5%
U4
PCH_GPIO56
AF39
CLK_CPU_DMI#
AF40
CLK_CPU_DMI
AJ40
AJ39
CLK_CPU_SSC_DPLL#
CLK_CPU_SSC_DPLL
AF35
AF36
CLK_CPU_DPLL#
CLK_CPU_DPLL
AY24
AW24
CLK_BUF_DMI#
CLK_BUF_DMI
AR24
AT24
CLK_BUF_BCLK#
CLK_BUF_BCLK
H33
G33
CLK_BUF_DOT96#
CLK_BUF_DOT96
BE6
BC6
CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD
F45
D17
CLK_PCH_14M
CLK_PCI_LPBACK
PCH_GPIO56 (17)
CLK_CPU_DMI# (5)
+3V_PCH
CLK_CPU_DMI (5)
RP9
CLK_CPU_SSC_DPLL# (5)
CLK_CPU_SSC_DPLL (5)
4
3
2
1
CLK_CPU_DPLL# (5)
CLK_CPU_DPLL (5)
5
6
7
8
PCH_GPIO73
CLKREQ_CR#
PCH_GPIO8
PCH_GPIO46
PCH_GPIO8 (18)
10K_0804_8P4R_5%
1
R132
2 10K_0402_5%
PCH_GPIO45
C
RP10
AM43
AL44
4
3
2
1
CLK_BUF_BCLK#
CLK_BUF_BCLK
CLK_BUF_DMI
CLK_BUF_DMI#
XTAL25_IN
XTAL25_OUT
C40
5
6
7
8
10K_0804_8P4R_5%
F38
CLK_BUF_DOT96#
CLK_BUF_DOT96
2
2
R85
R86
1 10K_0402_5%
1 10K_0402_5%
F36
F39
PCH_GPIO67
CLK_BUF_CKSSCD# R176 2
CLK_BUF_CKSSCD
R175 2
PCH_GPIO67 (18)
AM45
+1.5VS
AD39
AD38
AN44
CLK_PCH_14M
PCH_CLK_BIASREF
1 R93
2
7.5K_0402_1%
1 10K_0402_5%
1 10K_0402_5%
V0.2
2
R89
1 10K_0402_5%
+1.5VS
2 OF 11
CLOCK TERMINATION for FCIM and need close to PCH
B
B
Green CLK
XTAL25_IN
R156 1 GCLK@ 2 0_0402_5%
CLK_25M_PCH_XIN (27)
NOGCLK@
C122 1
XTAL25_IN
2 12P_0402_50V8J
R94
2
Y2
1
3
1
1M_0402_5%
NOGCLK@
XTAL25_OUT
NOGCLK@
2
XTAL0 GND0
4
XTAL1 GND1
25MHZ_10PF_7V25000014
C121
1
2
V0.2
12P_0402_50V8J
NOGCLK@
A
Compal Secret Data
Security Classification
Issued Date
2014/02/25
2015/02/25
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
A
Compal Electronics, Inc.
PCH (3/9) DMI,FDI,PM,
Document Number
Rev
1.0
LA-B111P
Tuesday, February 25, 2014
Sheet
1
15
of
59
5
4
3
2
1
LPT_PCH_M_EDS
U2D
+3VS
(31) LPC_AD3
B21
(31) LPC_FRAME#
+3VS
D21
2
R98
1 10K_0402_5%
G20
AL11
SERIRQ
(31) SERIRQ
LAD_1
LAD_2
U11
SMBDATA
AJ11
SPI_SB_CS0#
AJ7
SML0DATA
LDRQ0#
SML1ALERT#/PCHHOT#/GPIO74
LDRQ1#/GPIO23
AL7
AJ10
SPI_SO_R
SPI_IO2
AH3
AJ4
C
SPI_IO3
AJ2
PCH_SMBCLK
SML1CLK
N11
SML1CLK/GPIO58
1
1
PCH_GPI074
R100
2.2K_0402_5%
K6
SERIRQ
PCH_SMBDATA 3
SML1DATA
2.2K_0402_5%
6
1
SMB_CLK_S3
Q2A
2N7002KDWH_SOT363-6
4
DIMM1
DIMM2
SMB_DATA_S3 (11,12,32)Click Pad
SMB_CLK_S3 (11,12,32)
SMB_DATA_S3
Q2B
2N7002KDWH_SOT363-6
AF11
CL_CLK
SPI_CLK
AF10
CL_DATA
SPI_CS0#
+3VS
AF7
CL_RST#
SPI_CS1#
SPI_CS2#
SPI
AH1
SPI_SI
PCH_SML0DATA
H6
LFRAME#
PCH_SML0CLK
R7
SML0CLK
R99
PCH_GPIO60
U8
LAD_3
C-Link
PCH_SMBDATA
N8
SML0ALERT#/GPIO60
SML1DATA/GPIO75
SPI_CLK_PCH_R
PCH_SMBCLK
2
A18
C18
D
R10
SMBCLK
LPC
(31) LPC_AD2
SMBus
2
C20
+3VS
PCH_GPI011
2
(31) LPC_AD1
N7
SMBALERT#/GPIO11
LAD_0
BA45
TP1
SPI_MOSI
BC45
TP2
Thermal
SPI_MISO
SML1CLK
SPI_IO2
3
4
BE44
TP3
MAIN@ Q3B
SPI_IO3
AY43
TD_IREF
DH82HM86-SR17E-C2_FCBGA695
2N7002KDWH_SOT363-6
BE43
TP4
PCH_TD_IREF 1
R101
EC_SMB_CK2
2
A20
5
(31) LPC_AD0
5
D
EC_SMB_CK2 (31,32,36)
2N7002KDWH_SOT363-6
6
SML1DATA
MAIN@ Q3A
8.2K_0402_1%
1 EC_SMB_DA2
EC_SMB_DA2 (31,32,36)
Keep -Thermal
3 OF 11
PCH_SMBCLK
C125
1
2 0_0402_5%
SMB_CLK_S3
@
2 0_0402_5%
SMB_DATA_S3
R161 1
@
2 0_0402_5%
EC_SMB_CK2
SML1DATA
R159 1
@
2 0_0402_5%
EC_SMB_DA2
2
+3V_PCH
@
R160 1
SML1CLK
+3V_PCH
R162 1
PCH_SMBDATA
+3V_PCH
C
EC
2
R102
2
1K_0402_5%
R106
1
2
1K_0402_5%
U4
1
2
3
4
CS#
SO
WP#
GND
R107 15_0402_5%
0.1U_0402_16V7K
VCC
HOLD#
SCLK
SI
8
7
6
5
SPI_IO3_2
R105 1
SPI_CLK_PCH R108 1
SPI_SI_R
R109 1
Follow Intel schematic
review-0930
1
R104 15_0402_5%
SPI_SB_CS0#
2 SPI_SO_L
SPI_SO_R 1
1
2 SPI_IO2_2
SPI_IO2
2 15_0402_5% SPI_IO3
2 15_0402_5% SPI_CLK_PCH_R
2 15_0402_5% SPI_SI
+3V_PCH
PCH_SMBDATA
PCH_SMBCLK
SML1CLK
SML1DATA
SA000039A30
2
2
2
2
1
1
1
1
1K_0402_5%
1K_0402_5%
1K_0402_5%
1K_0402_5%
R163 2
R164 2
1
1
1K_0402_5%
1K_0402_5%
HDMICLK_NB
HDMIDAT_NB
B
R170
R168
R169
R167
PCH_SML0CLK
PCH_SML0DATA
64M W25Q64FVSSIQ SOIC 8P
R165 2
R166 2
1 2.2K_0402_5%
1 2.2K_0402_5%
B
SPI_CLK_PCH
1
EC/BIOS Share ROM
+3VS
R103
33_0402_5%
@EMI@
2
SPI_CLK_PCH
SPI_SI_R
SPI_SO_L
SPI_SB_CS0#
SPI_CLK_PCH (31)
SPI_SI_R (31)
SPI_SO_L (31)
SPI_SB_CS0# (31)
(14,24) HDMICLK_NB
(14,24) HDMIDAT_NB
C126
22P_0402_50V8J
@EMI@
+3V_PCH
R237;c120 close
to U4 pin
PCH_GPI011
R95
1
2
10K_0402_5%
PCH_GPI074
R96
1
2
10K_0402_5%
PCH_GPIO60
EMI
R97
2
1
1K_0402_5%
A
A
Compal Secret Data
Security Classification
Issued Date
2014/02/25
2015/02/25
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Compal Electronics, Inc.
PCH (4/9) LVDS,CRT,DP,HDMI
Document Number
Rev
1.0
LA-B111P
Tuesday, February 25, 2014
Sheet
1
16
of
59
5
4
3
2
1
D
D
U2I
V0.3
BE32
BC32
WLAN
(28) PCIE_PTX_C_DRX_N2
(28) PCIE_PTX_C_DRX_P2
LAN
PCIE_PRX_DTX_N2 AT31
PCIE_PRX_DTX_P2 AR31
(28) PCIE_PRX_DTX_N2
(28) PCIE_PRX_DTX_P2
C131 2
C132 2
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
1
1
PCIE_PTX_DRX_N2 BD33
PCIE_PTX_DRX_P2 BB33
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
PCIE_PRX_DTX_N3 AW33
PCIE_PRX_DTX_P3 AY33
(25) PCIE_PRX_DTX_N3
(25) PCIE_PRX_DTX_P3
(25) PCIE_PTX_C_DRX_N3
(25) PCIE_PTX_C_DRX_P3
C127
C128
PCIE_PTX_DRX_N3 BE34
PCIE_PTX_DRX_P3 BC34
AT33
AR33
BE36
BC36
Card Reader
(34) PCIE_PTX_C_DRX_N5
(34) PCIE_PTX_C_DRX_P5
C129
C130
2
2
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
PCIE_PTX_DRX_N5 BD37
PCIE_PTX_DRX_P5 BB37
AY38
AW38
BC38
BE38
AT40
AT39
BE40
BC40
AN38
AN39
BD42
BD41
BE30
+1.5VS
BC30
BB29
B
+1.5VS
1
R111
2
PCH_PCIE_RCOMP BD29
7.5K_0402_1%
USB DEBUG=PORT1 AND PORT9
PETN1/USB3TN3
PETP1/USB3TP3
PERN2/USB3RN4
PERP2/USB3RP4
PETN2/USB3TN4
PETP2/USB3TP4
PERN_3
PERP_3
PETN_3
PETP_3
PERN_4
PERP_4
PETN_4
PETP_4
PERN_5
PERP_5
PCIe
C
PCIE_PRX_DTX_N5 AW36
PCIE_PRX_DTX_P5 AV36
(34) PCIE_PRX_DTX_N5
(34) PCIE_PRX_DTX_P5
LPT_PCH_M_EDS
PERN1/USB3RN3
PERP1/USB3RP3
USB
AW31
AY31
USB2N0
USB2P0
USB2N1
USB2P1
USB2N2
USB2P2
USB2N3
USB2P3
USB2N4
USB2P4
USB2N5
USB2P5
USB2N6
USB2P6
USB2N7
USB2P7
USB2N8
USB2P8
USB2N9
USB2P9
USB2N10
USB2P10
USB2N11
USB2P11
USB2N12
USB2P12
USB2N13
USB2P13
PETN_5
PETP_5
USB3RN1
USB3RP1
USB3TN1
USB3TP1
USB3RN2
USB3RP2
USB3TN2
USB3TP2
USB3RN5
USB3RP5
USB3TN5
USB3TP5
USB3RN6
USB3RP6
USB3TN6
USB3TP6
PERN_6
PERP_6
PETN_6
PETP_6
PERN_7
PERP_7
PETN_7
PETP_7
PERN_8
PERP_8
PETN_8
PETP_8
USBRBIAS#
USBRBIAS
PCIE_IREF
TP24
TP23
TP11
OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14
TP6
PCIE_RCOMP
DH82HM86-SR17E-C2_FCBGA695
B37
D37
A38
C38
A36
C36
A34
C34
B33
D33
F31
G31
K31
L31
G29
H29
A32
C32
A30
C30
B29
D29
A28
C28
G26
F26
F24
G24
USB20_N0
USB20_P0
USB20_N1
USB20_P1
AR26
AP26
BE24
BD23
AW26
AV26
BD25
BC24
AW29
AV29
BE26
BC26
AR29
AP29
BD27
BE28
USB3_RX1_N
USB3_RX1_P
USB3_TX1_N
USB3_TX1_P
USB3_RX2_N
USB3_RX2_P
USB3_TX2_N
USB3_TX2_P
K24
K26
USB20_N4
USB20_P4
USB20_N8
USB20_P8
USB20_N9
USB20_P9
USB20_N10
USB20_P10
USB20_N0
USB20_P0
USB20_N1
USB20_P1
(30)
(30)
(30)
(30)
Left USB
(USB 3.0)
Left USB
USB20_N4 (34)
USB20_P4 (34)
EHCI1
Right USB/B (USB 2.0)
USB20_N8 (22)
USB20_P8 (22)
USB20_N9 (22)
USB20_P9 (22)
USB20_N10 (28)
USB20_P10 (28)
Touch panel
USB Camera
BT
EHCI2
C
USB3_RX1_N (30)
USB3_RX1_P (30)
USB3_TX1_N (30)
USB3_TX1_P (30)
USB3_RX2_N (30)
USB3_RX2_P (30)
USB3_TX2_N (30)
USB3_TX2_P (30)
Left USB
Left USB
HM86 NA
HM86 NA
USBRBIAS
1
R110 2
22.6_0402_1%
M33
L33
P3 USB_OC0#
V1 USB_OC#
U2 USB_OC2#
P1 USB_OC#
M3 USB_OC#
T1 USB_OC#
N2 USB_OC#
M1 USB_OC#
CAD NOTE:
Route single-end 50-ohms and max 500-mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15 mils.
USB_OC0# (18,30)
USB_OC2# (34)
B
9 OF 11
+3V_PCH
RP14
4
3
2
1
PCH_GPIO56
USB_OC2#
USB_OC#
PCH_GPIO26
(15) PCH_GPIO56
(15) PCH_GPIO26
5
6
7
8
10K_0804_8P4R_5%
A
A
Compal Secret Data
Security Classification
Issued Date
2014/02/25
2015/02/25
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Compal Electronics, Inc.
PCH (5/9) PCI, USB
Document Number
Rev
1.0
LA-B111P
Tuesday, February 25, 2014
Sheet
1
17
of
59
5
4
3
2
1
+3V_PCH
Weak internal pull-high
RP17
CLKREQ_LAN#
USB_OC0#
RI#
PCIE_WAKE#
CLKREQ_LAN# (15,25)
USB_OC0# (17,30)
RI# (14)
PCIE_WAKE# (14,28)
D
D
R112 1
+3VS
2 10K_0402_5%
PCH_GPIO0
AT8
F13
A14
+3V_PCH
EC_SCI#
(31) EC_SCI#
V0.2
(15) PCH_GPIO8
1 10K_0402_5%
R114 1
+3V_PCH
PCH_GPIO57
R116 1
@
2 10K_0402_5%
PCH_GPIO8
G15
Y1
2 1K_0402_5%
PCH_GPIO28
(14) PCH_GPIO28
+3VALW
PCH_GPIO27
BB4
Y10
R11
AD11
W_DISABLE#1
AN6
PCH_GPIO35
(13) PCH_GPIO35
2 10K_0402_5%
AN2
PCH_GPIO27
(14,28) W_DISABLE#1
1
AB11
PCH_GPIO24
(14) PCH_GPIO24
PCH_GPIO27 (Have internal Pull-High)
High: VCCVRM VR Enable
Low: VCCVRM VR Disable
R121
K13
PCH_GPIO15
W_DISABLE#2
(14,28) W_DISABLE#2
C
V0.2
DGPU_PWROK C14
(36,45,54) DGPU_PWROK
*
PCH_GPIO12
PCH_GPIO16
R115 2
AP1
TS_ON
(22) TS_ON
PCH_GPIO37
AT3
AK1
CMOS_ON#
1
R123
2
TS_ON
10K_0402_5%
2
1
AK3
DGPU_PWROK
10K_0402_5%
PCH_GPIO57
PCH_GPIO68
@
2
AN4
PCH_GPIO49
(15) PCH_GPIO49
R122
200K_0402_5%
AM3
PCH_GPIO48
+3VS
AT7
PCH_GPIO39
(22) CMOS_ON#
+3VS
1
R158
PCH_GPIO70
1 15@
R125
2 17@
R128
2
R124
10K_0402_5%
2
U12
C16
D13
1
PCH_GPIO37
@
LPT_PCH_M_EDS
U2F
10K_0804_8P4R_5%
PCH_GPIO68
10K_0402_5%
G13
V0.3
PCH_GPIO71
H15
1
BMBUSY#/GPIO0
TACH1/GPIO1
TACH2/GPIO6
CPU/Misc
GPIO8
+1.05VS
LAN_PHY_PWR_CTRL/GPIO12
TP14
GPIO15
PECI
SATA4GP/GPIO16
RCIN#
GPIO
TACH0/GPIO17
PROCPWRGD
SCLOCK/GPIO22
THRMTRIP#
GPIO24
PLTRST_PROC#
GPIO27
VSS
V0.3
PCH_GPIO68
======================================
Y50 : High (R125 stuff ,R128 un-stuff)
Y70 : Low (R125 un-stuff ,R128 stuff)
AN10
AY1
AT6
R157
GATEA20 (14,31)
KB_RST#
BW@
R119 BW@
1K_0402_5%
KB_RST# (14,31)
AV3
H_CPUPWRGD (5)
AV1
H_THRMTRIP#_R
AU4
CPU_PLTRST#
0_0402_5%
SD028000080
HW@
1
R157
2
390_0402_5%
H_THRMTRIP# (45,5)
CPU_PLTRST# (5)
N10
1
GPIO28
GPIO34
2
GPIO35/NMI#
SATA2GP/GPIO36
C186
1000P_0402_50V7K
@ESD@
C
ESD 9/5
SATA3GP/GPIO37
SLOAD/GPIO38
SDATAOUT0/GPIO39
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SDATAOUT1/GPIO48
SATA5GP/GPIO49
GPIO57
TACH4/GPIO68
TACH5/GPIO69
TACH6/GPIO70
TACH7/GPIO71
10K_0402_5%
BE41
BE5
C45
A5
Broadwell/Haswell
TACH3/GPIO7
2
5
6
7
8
1
4
3
2
1
VSS
VSS
VSS
VSS
NCTF
DH82HM86-SR17E-C2_FCBGA695
A2
A41
A43
A44
B1
B2
B44
B45
BA1
BC1
BD1
BD2
BD44
BD45
BE2
BE3
D1
E1
E45
A4
6 OF 11
B
B
+3VS
R127 1
2 10K_0402_5%
CMOS_ON#
R126 1
2 10K_0402_5%
PCH_GPIO67
R130 1
2 10K_0402_5%
PCH_GPIO71
R131 1
2 10K_0402_5%
PCH_GPIO70
PCH_GPIO67 (15)
+3VS
RP18
4
3
2
1
5
6
7
8
PCH_GPIO16
PCH_GPIO48
SYS_RST#
PCH_GPIO39
SYS_RST# (14)
10K_0804_8P4R_5%
A
A
Compal Secret Data
Security Classification
Issued Date
2014/02/25
2015/02/25
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
PCH (6/9) GPIO, CPU, MISC
Document Number
Rev
1.0
LA-B111P
Tuesday, February 25, 2014
Sheet
1
18
of
59
5
4
3
2
1
D
D
LPT_PCH_M_EDS
U2G
+1.05VS
VSS
CRT DAC
VCCADACBG3_3
VCCVRM
FDI
VCCIO
VCCIO
Core
+1.05VS
C
2
1
2
C143
1U_0402_6.3V6K
1
C142
1U_0402_6.3V6K
2
C141
22U_0805_6.3V6M
1
+PCH_VCCDSW U14
AA18
U18
U20
U22
U24
V18
V20
V22
V24
Y18
Y20
Y22
DCPSUS3
DCPSUS3
VCCIO
VCCVRM
VCCVRM
USB3
DCPSUSBYP
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCVRM
PCIe/DMI
VCCIO
VCCVRM
SATA
VCCIO
VCCMPHY
1
BB44
1
AN34
+3VS
AN35
2
Y12
+3V_PCH
+PCH_USB_DCPSUS1
AJ30
AJ32
AJ26
AJ28
AK20
AK26
AK28
1
1
+PCH_USB_DCPSUS3
2
2
Voltage Rail
VCC
@
Voltage
S0 Iccmax Current (A)
1.05V
VCCIO
1.29 A
3.629 A
1.5V
0.070 A
VCCADAC3_3
+1.5VS
1.05V
VCCADAC1_5
R30
R32
3.3V
0.0133 A
AK18
0.306 A
3.3V
0.055 A
1.5V
0.179 A
3.3V
0.133 A
VCCASW
1.05V
0.67 A
AK22
+1.05VS
1
3.3V
0.01 A
VCCSPI
C148
10U_0603_6.3V6M
1
C147
1U_0402_6.3V6K
1
C146
1U_0402_6.3V6K
1
C145
1U_0402_6.3V6K
VCCSUSHDA
1
3.3V
0.022 A
2
7 OF 11
2
2
2
2
VCCSUS3_3
3.3V
0.261 A
VCCDSW3_3
3.3V
0.015 A
V_PROC_IO
DH82HM86-SR17E-C2_FCBGA695
C
+1.5VS
+1.05VS
AN11
AM18
AM20
AM22
AP22
AR22
AT22
1.05V
VCC3_3
+1.5VS
BE22
VCCCLK
VCCCLK3_3
VCCVRM
2
+1.05VS
C144
1U_0402_6.3V6K
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
PCH Power Rail Table
+1.05VS
C140
0.1U_0402_16V7K
DCPSUS1
VCCSUS3_3
VCCSUS3_3
+1.5VS
M31
C139
0.1U_0402_16V7K
VCC3_3_R30
VCC3_3_R32
HVCMOS
P45
P43
C137
10U_0603_6.3V6M
10U_0603_6.3V6M
2
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
C138
1U_0402_6.3V6K
2
1
C135
1U_0402_6.3V6K
2
1
C134
1U_0402_6.3V6K
1
C136
1U_0402_6.3V6K
2
C133
10U_0603_6.3V6M
10U_0603_6.3V6M
1
VCCADAC1_5
AA24
AA26
AD20
AD22
AD24
AD26
AD28
AE18
AE20
AE22
AE24
AE26
AG18
AG20
AG22
AG24
Y26
1.05V
0.004 A
B
B
+1.05VS
1 R136
2
0_0402_5%
@
+PCH_USB_DCPSUS1
+PCH_VCCDSW_R
1
2
C149
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2 +PCH_VCCDSW
R134 5.1_0402_1%
@
+1.05VS
+PCH_USB_DCPSUS3
2
@
1
2
C152
10U_0603_6.3V6M
1
C151
10U_0603_6.3V6M
10U_0603_6.3V6M
2
C150
1U_0402_6.3V6K
1
2 R137
1
0_0603_5%
@
@
A
A
Compal Secret Data
Security Classification
Issued Date
2014/02/25
2015/02/25
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Compal Electronics, Inc.
PCH (7/9) PWR
Document Number
Rev
1.0
LA-B111P
Tuesday, February 25, 2014
Sheet
1
19
of
59
5
4
3
2
1
+3V_PCH
+PCH_VCCDSW3_3
1
+3V_PCH
D
M24
+3VS
2
+1.05VS
+PCH_USB_DCPSUS2
Y35
AF34
2
AP45
+PCH_VCC
Y32
+PCH_VCCCLK
M29
2
AD34
+PCH_VCCCLK
AA30
AA32
AD35
@
AG30
AG32
+PCH_VCC
AD36
+1.05VS
AE30
AE32
+PCH_VCC
1
2
VCCSUS3_3
VCCCLK
VCCRTC
RTC
VCCCLK3_3
DCPRTC
DCPRTC
P14
P16
+PCH_DCPRTC
AJ12
AJ14
+PCH_VPROC
1
0.1U_0402_16V7K
V_PROC_IO
V_PROC_IO
CPU
VCCCLK3_3
VCCCLK3_3
VCCSPI
SPI
VCCCLK
VCC
VCC
VCCCLK
VCCCLK
VCCASW
VCCCLK
VCCASW
VCCCLK
VCCCLK
VCCVRM
VCCCLK
VCC3_3
Thermal
VCCCLK
VCCCLK
VCC3_3
DH82HM86-SR17E-C2_FCBGA695
2
+3V_PCH
AD12
P18
P20
1
+PCH_VCCCFUSE
L17
2
+1.05VS
R18
1
2
1
2
VCCADAC1_5
01/02 EC/BIOS share ROM
AW40
1.5V
0.070 A
3.3V
0.0133 A
1.05V
0.306 A
3.3V
0.055 A
1.5V
0.179 A
3.3V
0.133 A
1.05V
0.67 A
VCCSUSHDA
2
C164
1
2
2
3.629 A
VCCASW
A6
VCCCLK3_3
VCCCLK3_3
VCCCLK3_3
1
1.29 A
1.05V
VCC3_3
+RTCVCC
K8
1.05V
VCCIO
VCCVRM
1
VCC
VCCCLK3_3
A26
VCCVRM
VCC
S0 Iccmax Current (A)
VCCCLK
2
Azalia
VCCSUSHDA
Voltage
VCCADAC3_3
+1.05VS
3.3V
0.01 A
VCCSPI
3.3V
0.022 A
VCCSUS3_3
3.3V
0.261 A
VCCDSW3_3
3.3V
0.015 A
V_PROC_IO
1.05V
C
0.004 A
+1.5VS
+3VS
AK30
AK32
1
C171
C171
1U_0402_6.3V6K
2
C170
10U_0603_6.3V6M
1
U36
1
8 OF 11
2
C172
0.1U_0402_16V7K
L1
1
2
4.7UH_NRS2012T4R7MGJ_20%
Voltage Rail
+3V_PCH
+3V_PCH
DCPSUS2
PCH Power Rail Table
0.1U_0402_16V7K
C169
1U_0402_6.3V6K
1U_0402_6.3V6K
1
VCCIO
ICC
U32
V32
+PCH_USB_DCPSUS2
C168
C168
1U_0402_6.3V6K
1 R139
2
0_0402_5%
@
VCC3_3
VCC3_3
VCC3_3
VCCIO
VCCIO
VCCIO
VCCIO
+3VALW
+3VS
C167
1U_0402_6.3V6K
L26
M26
+1.05VS
VCC3_3
AE14
AF12
AG14
C166
C166
0.1U_0402_16V7K
0.1U_0402_16V7K
L29
VCCUSBPLL
AA14
C165
0.1U_0402_16V7K
+PCH_VCCCLK3_3
DCPSST
C163
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
VCCDSW3_3
VSS
+PCH_VCCDSW3_3
C157
2
+PCH_VCCSST 1
C161
0.1U_0402_16V7K
+1.5VS
C162
10U_0603_6.3V6M
2
C160
1U_0402_6.3V6K
1
2
A16
C159
0.1U_0402_16V7K
1
U30
V28
V30
Y30
VCCSUS3_3
VCCSUS3_3
2
0_0402_5%
D
1
GPIO/LPC
USB
L24
C158
0.1U_0402_16V7K
2
C155
0.1U_0402_16V7K
1
U35
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
R20
R22
1
R138
C153
0.1U_0402_16V7K
2
R24
R26
R28
U26
+1.05VS
C154
0.1U_0402_16V7K
1
C
LPT_PCH_M_EDS
C156
0.1U_0402_16V7K
0.1U_0402_16V7K
U2H
Place near pin AP45
Broadwell
+PCH_VPROC
+1.05VS
B
B
+1.05VS
Place near pin AD34
2
1
2
1
2
C180
C180
1U_0402_6.3V6K
Place near pin Y32,AA30,AA32
1
C179
1U_0402_6.3V6K
2
C178
1U_0402_6.3V6K
1
C177
1U_0402_6.3V6K
2
C176
1U_0402_6.3V6K
1
2
1
2
1
2
1 0_0603_5%
C175
1U_0402_6.3V6K
1
C174
0.1U_0402_16V7K
0.1U_0402_16V7K
2
0_0603_5%
C173
0.1U_0402_16V7K
1
R141
R140 2
+PCH_VPROC
+PCH_VCCCLK
INTEL Recommend follow 486714 DG
Different with COMPAL
Place near pin AD35,AD36
Place near pin AG30,AG32,AE30,AE32
+3VS
+PCH_VCCCFUSE
+PCH_VCCCLK3_3
2
0_0603_5%
1
Place near pin L29
2
1
2
Place near pin L26,M26
V0.2
A
Compal Secret Data
2014/02/25
2015/02/25
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
+1.05VS
Place near pin U32,V32
Security Classification
Issued Date
2
C185
1U_0402_6.3V6K
2
1
C184
1U_0402_6.3V6K
1U_0402_6.3V6K
Place near pin M29
1
C183
1U_0402_6.3V6K
2
A
C182
C182
1U_0402_6.3V6K
1U_0402_6.3V6K
1
0_0805_5%
2
C181
C181
1U_0402_6.3V6K
1U_0402_6.3V6K
1
R143
R142 1
2
PCH (8/9) PWR
Document Number
Rev
1.0
LA-B111P
Tuesday, February 25, 2014
Sheet
1
20
of
59
5
4
3
2
1
D
D
U2J
AL34
AL38
AL8
AM14
AM24
AM26
AM28
AM30
AM32
AM16
AN36
AN40
AN42
AN8
AP13
AP24
AP31
AP43
AR2
AK16
AT10
AT15
AT17
AT20
AT26
AT29
AT36
AT38
D42
AV13
AV22
AV24
AV31
AV33
BB25
AV40
AV6
AW2
F43
AY10
AY15
AY20
AY26
AY29
AY7
B11
B15
C
B
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
LPT_PCH_M_EDS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K39
L2
L44
M17
M22
N12
N35
N39
N6
P22
P24
P26
P28
P30
P32
R12
R14
R16
R2
R34
R38
R44
R8
T43
U10
U16
U28
U34
U38
U42
U6
V14
V16
V26
V43
W2
W44
Y14
Y16
Y24
Y28
Y34
Y36
Y40
Y8
U2K
AA16
AA20
AA22
AA28
AA4
AB12
AB34
AB38
AB8
AC2
AC44
AD14
AD16
AD18
AD30
AD32
AD40
AD6
AD8
AE16
AE28
AF38
AF8
AG16
AG2
AG26
AG28
AG44
AJ16
AJ18
AJ20
AJ22
AJ24
AJ34
AJ38
AJ6
AJ8
AK14
AK24
AK43
AK45
AL12
AL2
BC22
BB42
DH82HM86-SR17E-C2_FCBGA695
10 OF 11
LPT_PCH_M_EDS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B19
B23
B27
B31
B35
B39
B7
BA40
BD11
BD15
BD19
AY36
AT43
BD31
BD35
BD39
BD7
D25
AV7
F15
F20
F29
F33
BC16
D4
G2
G38
G44
G8
H10
H13
H17
H22
H24
H26
H31
H36
H40
H7
K10
K15
K20
K29
K33
BC28
C
B
DH82HM86-SR17E-C2_FCBGA695
11 OF 11
A
A
Compal Secret Data
Security Classification
Issued Date
2014/02/25
2015/02/25
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Compal Electronics, Inc.
PCH (9/9) VSS
Document Number
Rev
1.0
LA-B111P
Tuesday, February 25, 2014
Sheet
1
21
of
59
A
CMOS Camera
C
D
1
V1.0
R255
NCMOS@
1
2
0_0603_5%
2
D
1
S
3
V0.3A
2
G
Q14
CMOS@
AO3413_SOT23
JEDP1
EDP_CONN_LANE_N1
EDP_CONN_LANE_P1
R204
@
(20 MIL)
1
10U
1
0_0603_5%
C317
0.1U_0402_16V7K
EDP_CONN_LANE_N3
EDP_CONN_LANE_P3
1
2
2
EDP_CONN_LANE_N2
EDP_CONN_LANE_P2
eDP
C318 @
10U_0603_6.3V6M
EDP_CONN_LANE_N0
EDP_CONN_LANE_P0
V1.0
R220
CMOS@
150K_0402_5%
EDP_CONN_AUX
EDP_CONN_AUX#
(18) CMOS_ON#
for CMOS shake issue reserve
200mA
USB20_N9_CONN
USB20_P9_CONN
Camera
R238 1
10K_0402_5%
2
(14) PCH_PWM
+3VS_CMOS
+3VS
+3VS_TOUCH
+LCDVDD
W=80mils
R205
2
1
0_0805_5%
@
V0.2
U11
5
2A
1
IN
OUT
GND
4
2
EN
OC
1090mA
R375
2
1
0_0805_5%
+12VS_PANEL
W=80mils
1
2A
W=80mils
+3VS_TOUCH
INVPWR_B+
W=80mils
CPU_B+
LCD POWER CIRCUIT
2
TS_RST#
0_0402_5% EDP_HPD
BKOFF#
PCH_PWM
+3VS_CMOS
@
C316
2
+3VS
1
R207
(18) TS_ON
(7) EDP_HPD
V0.3
(31) BKOFF#
DMIC_DATA
DMIC_CLK
(26) DMIC_DATA
(26) DMIC_CLK
DMIC
2
1
+LCDVDD
V1.0
+LCDVDD
V0.2A
C315
2
USB20_N8
USB20_P8
(17) USB20_N8
(17) USB20_P8
Touch PANEL
@
250mA
2
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
0.1U_0603_25V7K
C319 CMOS@
0.1U_0402_16V7K
@
1
C307
0.1U_0402_16V7K
E
+3VS_CMOS
+3VS
(20 MIL)
0.1U_0603_25V7K
1
B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
eDP Panel
CAMERA
DMIC
TOUCH SCREEN
2
G1
G2
G3
G4
G5
41
42
43
44
45
ACES_50398-04041-001
CONN@
confirm PWR
2
1
3
C308
4.7U_0603_6.3V6K
2
V1.0
1
2
C309
0.1U_0402_16V7K
SY6288C20AAC_SOT23-5
V0.2
(14) PCH_ENVDD
(7) EDP_CPU_LANE_N1
(7) EDP_CPU_LANE_P1
3
(7) EDP_CPU_LANE_N0
(7) EDP_CPU_LANE_P0
(7) EDP_CPU_AUX
(7) EDP_CPU_AUX#
(7) EDP_CPU_LANE_N2
(7) EDP_CPU_LANE_P2
Touch Panel
(7) EDP_CPU_LANE_N3
(7) EDP_CPU_LANE_P3
+3VS
C301
C302
1
1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
EDP_CONN_LANE_N1
EDP_CONN_LANE_P1
EDP_CPU_LANE_N0
EDP_CPU_LANE_P0
C303
C304
1
1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
EDP_CONN_LANE_N0
EDP_CONN_LANE_P0
EDP_CPU_AUX
EDP_CPU_AUX#
C305
C306
1
1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
EDP_CONN_AUX
EDP_CONN_AUX#
EDP_CPU_LANE_N2
EDP_CPU_LANE_P2
C310
C311
1
1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
EDP_CONN_LANE_N2
EDP_CONN_LANE_P2
EDP_CPU_LANE_N3
EDP_CPU_LANE_P3
C313
C314
1
1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
EDP_CONN_LANE_N3
EDP_CONN_LANE_P3
EDP_CPU_LANE_N1
EDP_CPU_LANE_P1
3
+3VS_TOUCH
JP11
1
JP@
JUMP_43X79
1
2
2
2 EMI@
R201
L28
(17) USB20_N9
USB20_N9
(17) USB20_P9
USB20_P9
2
R206
4
4
USB20_N9_CONN
1
USB20_P9_CONN
MCF12102G900-T_4P
2
1 0_0402_5%
EMI@
V0.2
4
Compal Secret Data
Security Classification
Issued Date
1 0_0402_5%
@EMI@
3
2014/02/25
2015/02/25
Deciphered Date
Title
Compal Electronics, Inc.
LCD Conn/Camera, Touch
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev
1.0
LA-B111P
Tuesday, February 25, 2014
Sheet
E
22
of
59
5
4
3
2
1
HDMI Connector
+HDMI_5V_OUT
+3VS
C320 @
@1
+5VS
2 2200P_0402_50V7K
1
2 2200P_0402_50V7K
1
HDMIDAT_CONN
HDMICLK_CONN
Co-lay for EMI
HDMI_TX0+_CK
HDMI_TX1-_CK
R215 1 @EMI@ 2 0_0402_5%
R216 1 @EMI@ 2 0_0402_5%
HDMI_TX0+_CONN
HDMI_TX1-_CONN
HDMI_TX1+_CK
HDMI_TX2-_CK
R217 1 @EMI@ 2 0_0402_5%
R218 1 @EMI@ 2 0_0402_5%
HDMI_TX1+_CONN
HDMI_TX2-_CONN
HDMI_TX2+_CK
R219 1 @EMI@ 2 0_0402_5%
HDMI_TX2+_CONN
C
D13
HDMI_TX0-_CONN 9
2
4
5
1
2
1
2
1
2
1
2
1
20
21
22
23
C-H_13-13201948CP
2
C
V0.3
1
HDMI_TX2-_CONN
HDMI_TX2+_CONN 6
1
2
CONN@
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
HDMI_TX0+_CONN
HDMI_TX2-_CONN 7
1
2
2
D
EMI
@ESD@
1
HDMI_TX0-_CONN
HDMI_TX0+_CONN 8
2
@EMI@
2.2P_0402_50V8C
C341
HDMI_CLK+_CONN
HDMI_TX0-_CONN
@EMI@
2.2P_0402_50V8C
C340
HDMI_CLK-_CONN
@EMI@
2.2P_0402_50V8C
C339
TMDS_B_DATA2_PCH
R212 1 @EMI@ 2 0_0402_5%
HDMI_CLK+_CK R213 1 @EMI@ 2 0_0402_5%
HDMI_TX0-_CK R214 1 @EMI@ 2 0_0402_5%
HDMI_CLK-_CK
0.1U_0402_16V7K
2
2 0.1U_0402_16V7K
0.1U_0402_16V7K
2
2 0.1U_0402_16V7K
0.1U_0402_16V7K
2
2 0.1U_0402_16V7K
0.1U_0402_16V7K
2
0.1U_0402_16V7K
@EMI@
2.2P_0402_50V8C
C338
TMDS_B_DATA1_PCH
TMDS_B_DATA2#_PCH
2
@EMI@
2.2P_0402_50V8C
C337
(7) TMDS_B_DATA2_PCH
TMDS_B_DATA0_PCH
TMDS_B_DATA1#_PCH
1
C327 1
C328
1
C329 1
C330
1
C331 1
C332
1
C333
@EMI@
2.2P_0402_50V8C
C336
(7) TMDS_B_DATA1_PCH
(7) TMDS_B_DATA2#_PCH
C326
@EMI@
2.2P_0402_50V8C
C335
(7) TMDS_B_DATA0_PCH
(7) TMDS_B_DATA1#_PCH
1
TMDS_B_CLK#_PCH
TMDS_B_CLK_PCH
TMDS_B_DATA0#_PCH
@EMI@
2.2P_0402_50V8C
C334
(7) TMDS_B_CLK_PCH
(7) TMDS_B_DATA0#_PCH
@
C325
C324
GND
JHDMI1
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HDMI_DET
R211
20K_0402_5%
(7) TMDS_B_CLK#_PCH
2
1
2200P_0402_50V7K
1
0.1U_0402_16V7K
1
2
AP2330W-7_SC59
2
1
VOUT
2
@
1
D
D
TMDS_B_HPD
VIN
C321
W=40mils
3
R210
2.2K_0402_1%
2N7002H_SOT23-3
3
S
S
(14) TMDS_B_HPD
1
R209
2.2K_0402_1%
2
1
1
G
2
Q6
W=40mils
2
R208
1M_0402_5%
1
0.1U_0402_16V7K
2
C322
D
2200P_0402_50V7K
C323
2
Q9
HDMI_TX2+_CONN
+3VS
Pull up R for PCH OR VGA SIDE
Co-lay for EMI
L11
HDMI_CLK+_CK
3
HDMI_CLK-_CK
2
EMI@
4
4
HDMI_CLK+_CONN
1
3
HDMI_CLK-_CONN
2N7002KDWH_SOT363-6
Q15A
2
3
TVWDF1004AD0_DFN9
2
1
DLW21HN900HQ2L_4P
1
6
HDMICLK_CONN
5
(14,16) HDMICLK_NB
D12
HDMI_CLK-_CONN
9
HDMI_CLK+_CONN
@ESD@
1
HDMI_CLK-_CONN
8
2
3
HDMI_TX1+_CK
3
HDMI_TX1-_CK
2
HDMI_TX2-_CK
2
HDMI_TX2+_CK
2
HDMI_TX0-_CK
HDMI_TX0+_CK
B
3
DLW21HN900HQ2L_4P
1
2
1
HDMI_TX0-_CONN
(14,16) HDMIDAT_NB
HDMI_CLK+_CONN
HDMI_TX1-_CONN
7
4
HDMI_TX1-_CONN
HDMI_TX1+_CONN
6
5
4
4
4
3
HDMIDAT_CONN
B
Q15B
2N7002KDWH_SOT363-6
HDMI_TX0+_CONN
HDMI_TX1+_CONN
1
3
4
HDMI_TX1-_CONN
HDMI_TX1+_CONN
L12
EMI@
L13
EMI@
3
4
3
TVWDF1004AD0_DFN9
2
1
DLW21HN900HQ2L_4P
DLW21HN900HQ2L_4P
1
2
1
3
4
4
+HDMI_5V_OUT
@ESD@
3
3
4
HDMI_TX2+_CONN
1
1
1
1
2
2
2
2
470_0402_5%
470_0402_5%
470_0402_5%
470_0402_5%
HDMI_TX0-_CK
HDMI_TX0+_CK
HDMI_TX2-_CK
HDMI_TX2+_CK
HDMI_TX2-_CONN
4
R360
R357
R361
R356
R355
R359
R354
R358
1
1
1
1
2
2
2
2
470_0402_5%
470_0402_5%
470_0402_5%
470_0402_5%
EMI@
+3VS
1
L14
D11
HDMI_TX1+_CK
HDMI_TX1-_CK
HDMI_CLK+_CK
HDMI_CLK-_CK
D
HDMICLK_CONN
3
S
5
+5VS
Vbus
GND
2
G
Q5
2N7002H_SOT23-3
2
A
A
HDMI_DET
6
6
1
1
HDMIDAT_CONN
Compal Secret Data
Security Classification
Issued Date
YSUSB2.0-5_SOT-23-6-6
2014/02/25
2015/02/25
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Compal Electronics, Inc.
HDMI LS & Conn.
Document Number
Rev
1.0
LA-B111P
Tuesday, February 25, 2014
Sheet
1
24
of
59
5
4
3
2
1
+3_LAN Rising time (10%~90%) & gt; 1mS and & lt; 100mS
+3V_LAN
+3VALW
W=60mils
JP6
1
JP@
2
2
1
370mA
JUMP_43X39
Layout Notice : Place as close
chip as possible.
D
V0.2
+3V_LAN
1
2
1
2
2
1
1
2
C343
2
1
4.7U_0603_6.3V6K
2
1
2
1
2
1
2
0.1U_0402_16V7K
1
C355
C355
2
C354
0.1U_0402_16V7K
1
0.1U_0402_16V7K
2
C353
C353
1
0.1U_0402_16V7K
0.1U_0402_16V7K
@
C352
C348
1 0.1U_0402_16V7K
0.1U_0402_16V7K
@
2
C351
C347
4.7U_0603_6.3V6K
0.1U_0402_16V7K
C345
0.1U_0402_16V7K
C350
C344
4.7U_0603_6.3V6K
+LAN_VDD10
W=60mils
L15
1
2
+LAN_REGOUT
2.2UH +-20% HPC252012NF-2R2M
W=60mils
1U_0402_6.3V6K
4.7U_0603_6.3V6K
+3V_LAN
C349
C342
2
1
+3V_LAN
D
+3V_LAN
close to pin 22
These caps close to U12 : Pin 23
( Should be place within 200 mils )
These components close to U12 : Pin 24
These components close to U12 : Pin 3,8,22,30
1uF reserved on Pin 22
R221
These caps close to U12 : Pin 11,32
DVDD33
1
2 10K_0402_5%
LAN_WAKE#_R
R567
close to U12 : Pin 11, 32
1
2 10K_0402_5%
LAN_PWRDN#_R
V0.3
U12
Green CLK
C
C
NOGCLK@
C356 1
2 12P_0402_50V8J
Y3
4
1
2
100_0402_1%
NOGCLK@
GND1 XTAL1
These caps close to U11
XTLI
(15,18)
(17)
(17)
(15)
(15)
V0.3A
NOGCLK@
GND0 XTAL0
(27)
EMI@
R372
V0.3A
2
CLK_25M_LAN_XIN
1
CLKREQ_LAN#
PCIE_PTX_C_DRX_P3
PCIE_PTX_C_DRX_N3
CLK_PCIE_LAN
CLK_PCIE_LAN#
MDI0+
MDI0+LAN_VDD10
MDI1+
MDI1MDI2+
MDI2+LAN_VDD10
MDI3+
MDI3+3V_LAN
LAN_CLKREQ#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MDIP0
MDIN0
AVDD10
MDIP1
MDIN1
MDIP2
MDIN2
AVDD10
MDIP3
MDIN3
AVDD33
CLKREQB
HSIP
HSIN
REFCLK_P
REFCLK_N
HSOP
HSON
PERSTB
ISOLATEB
LANWAKEB
DVDD10
VDDREG
REGOUT
LED2
LED1/GPIO
LED0
CKXTAL1
CKXTAL2
AVDD10
RSET
AVDD33
GND
3
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
PCIE_PRX_C_DTX_P3 C357 1
PCIE_PRX_C_DTX_N3 C358 1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
PCIE_PRX_DTX_P3
PCIE_PRX_DTX_N3
2 1K_0402_5%
ISOLATEB
R222 1
+3VS
2 0_0402_5%
LAN_WAKE#_R
R223 1
V0.3
+LAN_VDD10
+3V_LAN
+LAN_REGOUT
1
T36
1
2 0_0402_5%
LAN_PWRDN#_R
R566
@
1
T37
V0.3
XTLO
XTLI
+LAN_VDD10
R225
1
2
LAN_RSET
2.49K_0402_1%
+3V_LAN
PCIE_PRX_DTX_P3 (17)
PCIE_PRX_DTX_N3 (17)
PLT_RST# (14,28,31,34,36)
LAN_WAKE# (31)
LAN_PWRDN#
(31)
to
EC
ISOLATEB
1
R362 1 GCLK@ 2 0_0402_5%
XTLI
R226
15K_0402_5%
2
25MHZ_10PF_7V25000014
NOGCLK@
C359 1
2 12P_0402_50V8J
RTL8111GUL-CG_QFN32_4X4
SA00006ML10
XTLO
V0.3A
JRJ1
CONN@
B
B
MDO0+
MDO0-
MDI0+
2
MDI0-
3
+V_DAC
4
MDI1+
5
MDI1-
6
+V_DAC
7
MDI2+
8
MDI2-
9
+V_DAC
12
MCT1
TD1+
MX1+
TD1-
MX1-
TCT2
MCT2
TD2
MX2+
TD2-
MX2-
TCT3
MCT3
TD3+
MX3+
TD3-
MX3-
TCT4
MCT4
TD4+
MX4+
TD4-
MX4-
I/O1
I/O3
4
MDI3+
24
23
MDO0+
22
2
MDO03
MDI3MDO1+
19
MDO1-
EMI@
1
2
R227
1
2
75_0805_5%
I/O2
VDD
I/O4
5
6
MDI2-
6
7
MDO3-
V0.2
8
GND
10
PR2+
CHASSIS1_GND
PR3+
PR3PR2PR4+
GND
PR4GND
11
12
SANTA_130460-3
DC234007K00
Place Close to TS1
10P_0603_50V8-J
9
PR1-
AZC099-04S.R7G_SOT23-6
CHASSIS1_GND
C360
GND
MDO1MDO3+
21
20
5
ESD@
GND
PR1+
18
2
17
16
MDO2-
1
D14
MDO2+
1
MDI0DL1
BS4200N-C-LV_SMB-F2
EMI@
15
2
14
MDO3-
I/O3
GND
VDD
I/O2
I/O4
4
V0.3A
MDI1-
5
MDO3+
13
ESD@
I/O1
3
MDI0+
6
MDI1+
AZC099-04S.R7G_SOT23-6
1
2
11
MDI3A
10
MDI3+
TCT1
4
MDO2-
1
MDI2+
TS1
1
3
MDO2+
V0.3A
D10
2
MDO1+
FOR EMI suggest
+V_DAC
1
C300
0.01U_0402_16V7K
IH-160-A
SP050007E00
A
Place Close to TS1
V0.2
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2014/02/25
Deciphered Date
2015/02/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
LAN-RTL8111GUL
Size Document Number
Custom
Date:
Rev
1.0
LA-B111P
Sheet
Tuesday, February 25, 2014
1
25
of
59
A
B
C
D
E
F
G
H
600ohms @100MHz 2A
P/N: SM01000EE00
+5VDDA_CODEC
Place near U10
+3VS
1 1U_0402_6.3V6K
2
2
R240 1
2 0_0402_5%
40
VREF
JDREF
CPVEE
MIC-CAP
C363
0.1U_0402_16V7K
2
C362
1
1U_0402_6.3V6K
C361
C368
4.7U_0603_6.3V6K
C367
0.1U_0402_16V7K
SPK_LSPK_L+
45
44
SPK_R+
SPK_R-
JACK_PLUG Delay circutis
32
33
HP_OUTL (34)
HP_OUTR (34)
10
6
HDA_SYNC_AUDIO
HDA_BITCLK_AUDIO
+3VS
+3VS
HDA_SYNC_AUDIO
(13)
HDA_BITCLK_AUDIO
(13)
5
8 R236
48
HDA_SDOUT_AUDIO
1
2 33_0402_5%
EMI@
2 SBY100505T-301Y-N
R346 1
V0.3
16
HDA_SDOUT_AUDIO
HDA_SDIN0 (13)
DVSS
Thermal PAD
AVSS1
AVSS2
@
R377
100K_0402_5%
(13)
SPDIF-OUT
MONO-OUT (27)
JACK_SENSE#
@
R378
100K_0402_5%
(34)
5
Sub-woofer
MIC2-VREFO
29
7
39
27
28
15
34
JDREF
CPVEE
C372 2
C374 2
1 4.7U_0603_6.3V6K
1 4.7U_0603_6.3V6K
C375 2
1
1 4.7U_0603_6.3V6K
2 100K_0402_5%
C377 1
LDO3
LDO2
LDO1
R379
(34)
2 1U_0402_6.3V6K
R239 1
25
38
1
1
PLUG_IN#
(34) PLUG_IN#
2
@
R380
10K_0402_5% 1
@
C500
10U_0603_6.3V6M
2
@
Q19A
DMN66D0LDW-7_SOT363-6
@
Q19B
2
DMN66D0LDW-7_SOT363-6
1
@
C499
2 10U_0603_6.3V6M
2
2 20K_0402_1%
2
4
49
V0.3
1
Place near Pin9
1
26
AVDD2
LDO3-CAP
LDO2-CAP
LDO1-CAP
CPVREF
19
1 4.7U_0603_6.3V6K
43
42
CPVDD
20
C378
46
MIC2-VREFO
1 4.7U_0603_6.3V6K
2
Place near Pin1
MIC2-VREFO
CBP
CBN
36
C376
AVDD1
MONO-OUT
SENSE A
SENSE B
37
35
V0.3
C373 2
PCBEEP
13
14
2
SDATA-OUT
SDATA-IN
SPDIF-OUT/GPIO2
12
PC_BEEP
2 39.2K_0402_1%
SYNC
BCLK
ALC283-CG
PDB
RESETB
V0.3
JACK_SENSE# R237 1
HPOUT-L(PORT-I-L)
HPOUT-R(PORT-I-R)
GPIO0/DMIC-DATA
GPIO1/DMIC-CLK
47
11
@
3
2 0_0402_5% PDB
HDA_RST_AUDIO#
1
4
R235 1
2
2
1
@
2
22P_0402_50V8J
C370
2
EMI@
V0.3
EMI@
V0.2
(31) EC_MUTE#
(13) HDA_RST_AUDIO#
2
3
DMIC_DATA
DMIC_CLK_R
SBY100505T-301Y-N
2
1
6
L16
1
2
SPK-OUT-R+
SPK-OUT-R-
MIC2-L(PORT-F-L) /RING2
MIC2-R(PORT-F-R) /SLEEVE
LINE1-VREFO-L
LINE1-VREFO-R
@
1
1
DMIC_CLK
SPK-OUT-LSPK-OUT-L+
LINE2-L(PORT-E-L)
LINE2-R(PORT-E-R)
31
30
WF_MUTE#_R
2
2
1
1
V0.2
2
0_0402_5%
1
C369
1U_0402_6.3V6K
2
0_0603_5%
V1.0
1
Place near Pin40
LINE1-L(PORT-C-L)
LINE1-R(PORT-C-R)
17
18
EXT_MIC_RING2
EXT_MIC_SLEEVE
(34) EXT_MIC_RING2
(34) EXT_MIC_SLEEVE
W=40 mils
@
1
2
22
21
24
23
(22) DMIC_DATA
(22) DMIC_CLK
9
2 100K_0402_5%
V0.2
V0.3
PVDD2
WF_MUTE#_R
PVDD1
R203 1
DVDD
(31) WF_MUTE#
2 0_0402_5%
41
R231
1
U10
R202 1
@
L10
+1.5VS
0.1U_0402_16V7K
1
+IOVDD_CODEC
+3VDD_CODEC
1
2
DVDD-IO
1
0.1U_0402_16V7K
0.1U_0402_16V7K
C366
C364
2
+IOVDD_CODEC
R229
0_0603_5%
G
1
+3VDD_CODEC
0_0603_5%
2
S
1
R228
D
2
+3VDD_CODEC
Place near Pin26
G
G
0_0805_5%
4.7U_0603_6.3V6K
C365
+5VS_PVDD
1
+3VS
+5VS
2
S
R230
@
D
1
+5VS
PLUG_IN#
C379
1U_0402_6.3V6K
1
R376
2 0_0402_5%
JACK_SENSE#
Reserve for cancel Delay circutis
ALC283-CG_MQFN48_6X6
SA000060500
R240 pop on ALC283,
NC on ALC233
+3VLP
2
6
GNDA
1
C385
R249
1
2
1K_0402_5%
2
1
1
1
1
2
2
2
2
JSPK1
PBY160808T-330Y-N
PBY160808T-330Y-N
PBY160808T-330Y-N
PBY160808T-330Y-N
4
3
2
1
SPK_R+_CONN
SPK_R-_CONN
SPK_L+_CONN
SPK_L-_CONN
PC_BEEP
EMI@
EMI@
EMI@
EMI@
@
R250
10K_0402_5%
PC Beep
2 0_0402_5%
1
0.1U_0402_16V7K
1
2PC_BEEP1
0.1U_0402_16V7K
R241
R242
R243
R244
1
2
V0.2
V0.3A
EMI@
1
2
EMI@
EMI@
1
2
1
2
EMI@
1000P_0402_50V7K
(13) HDA_SPKR
2 0_0402_5%
C386
C383
2 0_0402_5%
SPK_R+
SPK_RSPK_L+
SPK_L-
1000P_0402_50V7K
2
0.1U_0402_16V7K
C382
1
C384
C381
(31) BEEP#
C380
EC Beep
1000P_0402_50V7K
@EMI@
@
2
2
R200 1
@EMI@
2
1
3
wide 40MIL
2 0_0402_5%
PCH Beep
R247 1
1
2
R234
10K_0402_5%
D16
PACDN042Y3R_SOT23-3
1000P_0402_50V7K
@EMI@
5
4
1
R246 1
@EMI@
@ESD@
D15
PACDN042Y3R_SOT23-3
1
@ESD@
1
HDA_RST_AUDIO#
R245 1
3
1
2
2
3
2
27_0402_5%
@EMI@
C387
33P_0402_50V8J
C371
1U_0402_6.3V6K
2
R233 @
100K_0402_5%
Q16A
2N7002KDWH_SOT363-6
R248@EMI@
SPK_L+_CONN
HDA_BITCLK_AUDIO
3
2
SPK_L-_CONN
SPK_R-_CONN
1
EXT_MIC_SLEEVE
Q16B
Q16B
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
SPK_R+_CONN
3
R232
100K_0402_5%
Reserve for ESD request.
EMI
1
1
+3VS
4
3
2
1
G2
G1
CONN@
6
5
CVILU_CI4304M2HR0-NH
SP02000Y500
4
4
V0.2
GND
GNDA
Compal Secret Data
Security Classification
2014/02/25
Issued Date
Deciphered Date
2015/02/25
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
C
Date:
A
B
C
D
E
F
G
Compal Electronics, Inc.
HD Audio ALC283
Document Number
Rev
1.0
LA-B111P
Tuesday, February 25, 2014
Sheet
26
H
of
59
Sub Woofer
Place near Pin25
+5VS
+12VS_WF
2
V0.2
WF@
WF@
WF@
WF@
WF_GNDA
WF_GNDA
@
2 10K_0402_5%
2
1
WF@ C389
10U_0805_25V6K
WF_GNDA
WF_GNDA
EMI@
1
C397
2
C396
2
1 2
C478 @EMI@
330P_0402_50V7K
1000P 50V X7R 0603
EMI@
1
1
1
C477
330P_0402_50V7K
ACES_50271-0020N-001
WF_GNDA
WF_GNDA
WF_GNDA
GAIN0
R258 1
@
2 10K_0402_5%
GAIN1
R259 1
WF@
2 10K_0402_5%
2 0_0402_5%
V
@EMI@
2 0_0402_5%
@EMI@
R383 1
C388
@EMI@
CONN@
GND
GND
2
1
WF_GNDA
R257 1
R381 1
2
+12VS_WF
1
+5VS
R382 1
WF@
0.1U_0402_16V7K
TPA3113D2PWPR_HTSSOP28
SA00004UH00
R348 @EMI@
10_0402_5%
10_0402_5%
29
GND
R349
SPKWF-_CONN
V0.2
1000P 50V X7R 0603
C443 @
22P_0402_50V8J
@EMI@
16
15
4
3
2
1
SPKWF+_CONN
2
1
RPVDD
RPVDD
SPKWF-
1 2
WF_GNDA
1
C450 @
22P_0402_50V8J
2
NC
MONO
SPKWFC394 WF@
1
2 0.47U_0603_10V
18
17
ROUTP
RBSP
EMI@
1
2
L29
FBMA-L11-201209-221LMA30_2P
EMI@
1
2
L40
FBMA-L11-201209-221LMA30_2P
SPKWF+
19
PGND
RINN
RINP
JSPK2
SPKWF+
21
20
RBSN
ROUTN
VCLAMP
PLIMIT
0.47U_0603_10V
23
22
LOUTN
LBSN
AGND
C392 1
R224 2
C469 2
WF@
2
2
V1.0
WF_GNDA
R1565
@
2
1
0_0402_5%
20K_0402_1%
1U_0402_16V6K
1
24
PGND
AVDD
WF_GNDA
C390
26
25
1
R1564
@
2
1
0_0402_5%
7
+12VS
0_0805_5%
WF@ C470
10U_0805_25V6K
(26) MONO-OUT
GAIN0
GAIN1
8
2 1U_0402_16V6K
VCLAMP
1
2 WF@
1
9
R297 62K_0402_1% 10
1
V0.2
17.4K_0402_1% 2 R299
1 C393 1
2 0.1U_0603_16V7K
11
12
2 R341
1 C395 1
2
30K_0402_1%
13
0.1U_0603_16V7K
41.2K_0402_1% 2 R342
14
1
WF@
WF@
680P_0402_50V7K 2
1 C472
WF_GNDA
WF_GNDA
2 1U_0402_16V6K
LBSP
LOUTP
C471
C391 1
5
6
GAIN0
GAIN1
28
27
LPVDD
LPVDD
LINP
LINN
2
WF@
WF@
WF@
WF@
2
V0.2
R251
1
@
WF@
SD#
FLAG#
3
4
V0.3
1
WF@
1
2
WF_GNDA
Close to U14
1
2 1K_0402_5%
0.1U_0402_16V7K
WF@
R254 1
(31) EC_MUTE#_WF
100K_0402_5%
R253
U14
@
2
from EC
WF@
2
1
R252
10_0603_5%
2
2 0_0402_5%
R260 1
@EMI@
WF@
2 10K_0402_5%
V1.0
WF_GNDA
Green CLK
+CHGRTC_R
GCLK@
1 R366
2
22U_0603_6.3V6M
1
C496
R374
0_0402_5%
@
C495
U24
GCLK@
+3VLP
10
GCLK@
C485
1
2
0.1U_0402_16V7K
15
2
+3V_LAN
VBAT
VDD_RTC_OUT
VDD
1
2
25M_GREEN_XIN
25M_GREEN_XOUT
1
16
CLK_32K_RTC_XIN_R
R373 1 GCLK@ 2 0_0402_5% CLK_32K_RTC_XIN
12
CLK_27M_VGA_XIN_R
R364 1 GCLK@ 2 22_0402_5% CLK_27M_VGA_XIN
VDDIO_25M_A
VDDIO_25M_B
XTAL_IN
XTAL_OUT
SLG3NB304VTR_TQFN16_2X3
25MHz_A
6
CLK_25M_LAN_XIN_R
R365 1 GCLK@ 2 33_0402_5% CLK_25M_LAN_XIN
5
CLK_25M_PCH_XIN_R
R363 1 GCLK@ 2 0_0402_5% CLK_25M_PCH_XIN
25MHz_B
2 2.2U_0402_6.3V6M
2
C498 1
@EMI@
2
C491 1
@EMI@
2
C492 1
@EMI@
2
C490 1
@EMI@
GCLK@
V0.3A
2 18P_0402_50V8J
CLK_32K_RTC_XIN
(13)
CLK_27M_VGA_XIN
(36)
CLK_25M_LAN_XIN
(25)
CLK_25M_PCH_XIN
(15)
for EMI
GND4
C486
9
1
GCLK@
17
2
V0.2A
GCLK@
C494 1
1
GCLK@
2
C488
GCLK@
1
0.1U_0402_16V7K
GCLK@
GCLK@
2
C487
27MHz
GND1
GND2
GND3
+1.05VS
3
0.1U_0402_16V7K
8
0.1U_0402_16V7K
+3V_LAN
VDDIO_27M
4
7
13
+3V3_AON
14
+V3.3A
32kHz
11
C489 1
+RTCVCC
1
2
2
390_0402_5%
0.1U_0402_16V7K
WF_GNDA
10P_0402_25V8J
10P_0402_25V8J
10P_0402_25V8J
10P_0402_25V8J
25M_GREEN_XIN
Reserve for EMI
Y4
2
4
GCLK@
GND0 XTAL0
GND1 XTAL1
1
V0.3A
3
25MHZ_12PF_7V25000012
C493 1
2 15P_0402_50V8J
25M_GREEN_XOUT
GCLK@
V0.3A
V0.2
Compal Secret Data
Security Classification
Issued Date
2014/02/25
Deciphered Date
2015/02/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Compal Electronics, Inc.
Sub-Woofer / Green CLK
Size
C
Date:
Document Number
Rev
1.0
LA-B111P
Tuesday, February 25, 2014
Sheet
27
of
59
1
2
3
4
5
WLAN
A
A
+3VS
+3VS_WLAN
JP7
1
1
2
2
JUMP_43X39
JP@
For Power consumption
Measurement
1
2
1
C398
4.7U_0603_6.3V6K
2
C399 @
0.1U_0402_16V7K
NGFF for WLAN (TYPE 2230)
V0.3A
+3VS_WLAN
JWLAN1
Bluetooth
USB20_P10
USB20_N10
(17) USB20_P10
(17) USB20_N10
B
V0.2
(17) PCIE_PTX_C_DRX_P2
(17) PCIE_PTX_C_DRX_N2
(17) PCIE_PRX_DTX_P2
(17) PCIE_PRX_DTX_N2
(15) CLK_PCIE_WLAN1
(15) CLK_PCIE_WLAN1#
(15) CLKREQ_WLAN#
(14,18) PCIE_WAKE#
C
R263 1
@
2 0_0402_5%
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
GND
USB_D+
USB_DGND
SIDO_CLK
SDIO_CMD
SDO_DAT0
SDO_DAT1
SDO_DAT2
SDO_DAT3
SDIO_W AKE#
SDIO_RESET#
GND
PETP0
PETN0
GND
PERP0
PERN0
GND
REFCLKP0
REFCLKN0
GND
CLKEQ0#
PEW AKE0#
GND
RSRVD/PETP1
RSRVD/PETN1
GND
RSRVD/PERP1
RSRVD/PERN1
GND
RESERVED
RESERVED
GND
MTG77
CONN@
3.3VAUX
3.3VAUX
LED1#
PCM_CLK
PCM_SYNC
PCM_IN
PCM_OUT
LED2#
GND
UART_W AKE#
UART_RX
UART_TX
UART_CTS
UART_RTS
RESERVED
RESERVED
RESERVED
COEX3
COEX2
COEX1
SUSCLK
PERST0#
W _DISABLE2#
W _DISABLE1#
I2C_DATA
I2C_CLK
ALERT
RESERVED
RESERVED
RESERVED
RESERVED
3.3VAUX
3.3VAUX
MTG76
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
B
For EC to detect
debug card insert.
2
R267 1
100K_0402_5%
EC_TX (31,34)
EC_RX (31,34)
SUSCLK
SUSCLK (14)
PLT_RST# (14,25,31,34,36)
W_DISABLE#2 (14,18)
W_DISABLE#1 (14,18)
C
+3VS_WLAN
68
CONCR_213EAAA32FA
SP070011I00
D
D
Compal Secret Data
Security Classification
Issued Date
2014/02/25
2015/02/25
Deciphered Date
Title
Compal Electronics, Inc.
NGFF (WLAN/BT)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
1
2
3
4
Rev
1.0
LA-B111P
Tuesday, February 25, 2014
Sheet
5
28
of
59
1
2
3
4
5
SATA HDD CONN.
A
A
+3VS
JHDD1
SATA_PTX_C_DRX_P4_R
C400 2
SATA_PTX_C_DRX_N4_R
C402 2
U15
7
+3VS
SATA_PTX_DRX_P4
SATA_PTX_DRX_N4
(13) SATA_PRX_DTX_P4
(13) SATA_PRX_DTX_N4
0.01U_0402_16V7K
0.01U_0402_16V7K
1
1
2 C405
2 C401
0.01U_0402_16V7K
0.01U_0402_16V7K
1
1
2 C406
2 C407
SATA_PRX_C_DTX_P4 5
SATA_PRX_C_DTX_N4 4
SDA
DE_A
EQ2
EQ1
SATA1_A_PRE1
SATA1_B_PRE1
SCK
GND
SATA1_TEST
A_INp
A_INn
B_OUTp
B_OUTn
19
17
18
3
13
21
A_PRE1
B_PRE1
TEST
GND
GND
EPAD
SATA_PTX_DRX_P4_C
SATA_PTX_DRX_N4_C
1 0.01U_0402_16V7K
1 0.01U_0402_16V7K
SATA_PRX_DTX_N4_C
SATA_PRX_DTX_P4_C
@
EN
SATA_PTX_C_DRX_P4 1
SATA_PTX_C_DRX_N4 2
SATA_PRX_DTX_P4
SATA_PRX_DTX_N4
(13) SATA_PTX_DRX_P4
(13) SATA_PTX_DRX_N4
1 0.01U_0402_16V7K
1 0.01U_0402_16V7K
SATA_PRX_C_DTX_N4_R
C403 2
SATA_PRX_C_DTX_P4_R
C404 2
V1.0
VDD
VDD
NC
NC
A_PRE0
B_PRE0
A_OUTp
A_OUTn
B_INp
B_INn
10
20
6
16
DEW2
DEW1
9
8
SATA1_A_PRE0
SATA1_B_PRE0
VCC
VCC
DE1 REXT
DE2 DE_B
15
14
2
+5VS_HDD
0_0805_5%
@
SATA_PRX_C_DTX_P4_R
SATA_PRX_C_DTX_N4_R
11
12
Parade@
U15
GND
GND
ACES_50208-01001-001
CONN@
PS8527CTQFN20GTR2-A1_TQFN20_4X4
U15
1
2
3
4
5
6
7
8
9
10
SATA_PTX_C_DRX_P4_R
SATA_PTX_C_DRX_N4_R
11
12
1
R345
+5VS
1
2
3
4
5
6
7
8
9
10
TI@
SP01000JF10
B
B
PS8527CTQFN20GTR2-A1_TQFN20_4X4
SN75LVCP601RTJR_TQFN20_4X4
SA00007JU00
V0.2
SA00003ZX00
Add EQ pin for PI3EQX6741STZDEX
DE_B
DE2
TI
2 0_0402_5%
2 0_0402_5%
VCC
2 0_0402_5%
VCC
DE1/DE2
dB
EQ1/EQ2
-6
0
-3
NC
0
1
0
7
14
1
4.7K_0402_5%
4.7K_0402_5%
V0.3A
2
2
2
1
2
@
1
2
@
1
2
C
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
dB
NC
0
1
Asmidia
V1.0
1
C410
0.1U_0402_16V7K
2 0_0402_5%
+5VS_HDD
1
C409
0.1U_0402_16V7K
2 0_0402_5%
4.7K_0402_5%
1
C414
10U_0603_6.3V6M
DE1
0_0402_5%
C413
10U_0603_6.3V6M
EQ2
2 0_0402_5%
@
2
SATA1_TEST 1 R268
@
1
2
SATA1_B_PRE1 R271
Parade@
2
SATA1_A_PRE1 1 R273
@
1
2
SATA1_A_PRE0 R275
@
1
2
SATA1_B_PRE0 R277
@
1 R340
2
DEW1
@
1 R384
2
DEW2
2
SDA
REXT
2 0_0402_5%
C412
0.01U_0402_16V7K
C
EQ1
TI@
SATA1_TEST 1 R269
@
1
SATA1_B_PRE1 R270
@
1
SATA1_A_PRE1 R272
@
1 R274
SATA1_A_PRE0
@
1
SATA1_B_PRE0 R276
@
1 R296
DEW1
@
1 R369
DEW2
+5VS_HDD
C411
0.1U_0402_16V7K
DE_A
GND
C408
1U_0402_6.3V6K
1U_0402_6.3V6K
SCK
51U raen
.spac ecalP
+3VS
V0.3
NNOC DDH raen ecaelP
+3VS
DE_X
dB
0
1
V0.3
+1.5
+3.0
D
D
Compal Secret Data
Security Classification
Issued Date
2014/02/25
2015/02/25
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
1
2
3
4
Compal Electronics, Inc.
HDD/SSD
Document Number
Rev
1.0
LA-B111P
Tuesday, February 25, 2014
Sheet
5
29
of
59
A
B
@EMI@
1 0_0402_5%
2
R278
L17
3
(17) USB3_RX1_N
C
4
4
JUSB1
9
1
8
3
7
2
6
4
5
2
R279
U3RXDP1
U3TXDN1
CON-USBP0+
1 0_0402_5%
CON-USBP0U3RXDP1
@EMI@
1
2 @EMI@ 1 0_0402_5%
R280
U3RXDN1
L18
(17) USB3_TX1_N
(17) USB3_TX1_P
2
1
U3TXDN1_R
0.1U_0402_16V7K
3
2
1
2
C419
C420
U3TXDP1_R
0.1U_0402_16V7K
EMI@
4
4
U3TXDN1
1
3
U3TXDP1
2
CONN@
U16
SSTX+
VBUS
SSTXD+
GND
DSSRX+
GND
SSRX-
5
1
10
11
12
13
0.1U_0402_16V7K
2
2
C417
GND
GND
GND
GND
1
4
@ C418
OUT
IN
GND
EN
OCB
2.2U_0603_10V6K
1
W=80mils
2
3
USB_OC0#
SY6288D20AAC_SOT23-5
1
+
C415
220U_6.3V_M
PCB Footprint = C_MP6VLPS220MC4R2
TAITW_PUBAU2-09FNLS1NN4H0
DC233008A20
USB_OC0# (17,18)
1
V0.2
2
1
DLW21HN900HQ2L_4P
R281
+USB3_VCCA
2A
+5VALW
U3RXDN1
1
2
1
DLW21HN900HQ2L_4P
E
+USB3_VCCA
EMI@
3
U3TXDP1
2
(17) USB3_RX1_P
D
2
USB_ON#
(31) USB_ON#
1 0_0402_5%
@EMI@
EMI
Co-lay
D17
U3TXDP1
8U3TXDN1
U3RXDP1
4
7U3RXDP1
5
6U3RXDN1
D18
3
DLW21HN900HQ2L_4P
2
1
2
1
CON-USBP0-
USB20_P0
3
CON-USBP0-
2
CON-USBP0+
1
1
@EMI@ 0_0402_5%
USB20_N0
(17) USB20_N0
2
U3RXDN1
2
9U3TXDP1
U3TXDN1
EMI
R282
1
CON-USBP0+
YSLC05CH_SOT23-3
@ESD@
3
(17) USB20_P0
R283
3
L19
4
4
TVWDF1004AD0_DFN9
@ESD@
EMI@
2
1 0_0402_5%
@EMI@
2
2
+USB3_VCCB
2
R284
@EMI@
1 0_0402_5%
JUSB2
U3TXDP2
L20
3
(17) USB3_RX2_N
2
(17) USB3_RX2_P
EMI@
3
4
4
U3RXDN2
1
2
1
DLW21HN900HQ2L_4P
2
R285
U3RXDP2
1 0_0402_5%
U3TXDN2
CON-USBP1+
CON-USBP1U3RXDP2
U3RXDN2
9
1
8
3
7
2
6
4
5
@EMI@
SSTX+
VBUS
SSTXD+
GND
DSSRX+
GND
SSRX-
CONN@
+USB3_VCCB
U17
GND
GND
GND
GND
10
11
12
13
5
1
C423
0.1U_0402_16V7K
TAITW_PUBAU2-09FNLS1NN4H0
3
2
R286
L21
2
1
U3TXDN2_R
0.1U_0402_16V7K
3
2
(17) USB3_TX2_N
1
2
C425
3
1 0_0402_5%
@EMI@
EMI@
4
U3TXDN2
4
2A
+5VALW
2
2
1
4
@ C424
OUT
IN
GND
EN
OCB
2.2U_0603_10V6K
1
W=80mils
2
3
SY6288D20AAC_SOT23-5
DC233008A20
V0.2
USB_OC0#
1
+
2
3
C416
220U_6.3V_M
PCB Footprint = C_MP6VLPS220MC4R2
USB_ON#
(17) USB3_TX2_P
C426
U3TXDP2_R
0.1U_0402_16V7K
1
2
1
DLW21HN900HQ2L_4P
2
R287
EMI
U3TXDP2
1 0_0402_5%
@EMI@
D19
L22
USB20_N1
2
(17) USB20_P1
(17) USB20_N1
R289
8 U3RXDP2
4
7 U3TXDN2
5
6 U3TXDP2
D20
3
3
EMI@
3
4
4
2
CON-USBP1-
YSLC05CH_SOT23-3
@ESD@
CON-USBP1+
1
2
1
DLW21HN900HQ2L_4P
CON-USBP1+
2
1
@EMI@
1 0_0402_5%
2
3
9 U3RXDN2
2
U3TXDP2
EMI
USB20_P1
1
U3TXDN2
R288
U3RXDN2
U3RXDP2
Co-lay
CON-USBP1-
TVWDF1004AD0_DFN9
@ESD@
1 0_0402_5%
@EMI@
4
4
Compal Secret Data
Security Classification
Issued Date
2014/02/25
2015/02/25
Deciphered Date
Title
Compal Electronics, Inc.
USB3.0 Port
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev
1.0
LA-B111P
Tuesday, February 25, 2014
Sheet
E
30
of
59
V0.2
2
(14,18) KB_RST#
(16) SERIRQ
(16) LPC_FRAME#
(16) LPC_AD3
(16) LPC_AD2
(16) LPC_AD1
(16) LPC_AD0
(15) CLK_PCI_EC
(14,25,28,34,36) PLT_RST#
T38
(18) EC_SCI#
V1.0
1 0_0402_5%
1
2
3
4
5
7
8
10
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
CLK_PCI_EC
EC_RST#
EC_SCI#
V0.2
12
13
37
20
38
PWR cancel
GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC & MISC
LPC_AD0
AD Input
(32) KSI[0..7]
@
2
LAN_WAKE#
10K_0402_5%
1
@
2
VCIN1_BATT_TEMP
47K_0402_5%
R295
C
R293
(32) KSO[0..17]
V0.2
1
2
ACIN
100P_0402_50V8J
C435
2
@
2
@
EC
1 VCOUT1_PROCHOT#
100K_0402_5%
1
EC_MUTE#
10K_0402_5%
R300
R302
@EMI@
@EMI@
2
1
2
1CLK_PCI_EC
C436
R303
22P_0402_50V8J 33_0402_5%
1
2
(47,48)
(47,48)
(16,32,36)
(16,32,36)
PLT_RST#
100P_0402_50V8J
C497
@ESD@
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
(14) PM_SLP_S3#
(14) PM_SLP_S5#
DS3
(35) PCH_PWR_EN
(25) LAN_WAKE#
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
77
78
79
80
PM_SLP_S3#
PM_SLP_S5#
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
V0.2
LAN_WAKE#
(14) SLP_SUS#
B
+3VLP_EC
RP25
1
2
3
4
8
7
6
5
EC_SMB_CK1
EC_SMB_DA1 EC
EC_SMB_CK2
EC_SMB_DA2
2.2K_0804_8P4R_5%
1
R304
1
R305
2
1
R294
2
EC_TACH1
10K_0402_5%
2
EC_TACH2
10K_0402_5%
V0.2
EC_TACH1
EC_TACH2 V0.2
EC_TX
EC_RX
PCH_PWROK
2
EC_SCI#
10K_0402_5%
1
R568
1
R569
(54) PWR_GPS_DOWN#
(14) AC_PRESENT_R
(48) ACOFF
(34) EC_TACH1
(34) EC_TACH2
(28,34) EC_TX
(28,34) EC_RX
(14,9) PCH_PWROK
V0.3
(33) TP_LOCK_LED#
(32) NUM_LED#
2
TP_CLK
4.7K_0402_5%
TP_DATA
4.7K_0402_5%
EC
V0.3
(33) NOVO#
(14,45) DGPU_PWR_EN
DGPU_PWR_EN
122
123
BATT_TEMP/GPIO38
GPIO39
ADP_I/GPIO3A
GPIO3B
GPIO42
IMON/GPIO43
DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F
EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F
CPU1.5V_S3_GATE/GPXIOA00
WOL_EN/GPXIOA01
ME_EN/GPXIOA02
VCIN0_PH/GPXIOD00
15K +/- 1%
20K +/- 1%
SPI Flash ROM
GPIO
Bus
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A
GPIO
SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A
ENBKL/GPIO40
PECI_KB930/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
BATT_LOW_LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59
EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11
AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
GPI
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07
XCLKI/GPIO5D
XCLKO/GPIO5E
V
2
typ
KB9022C_LQFP128_14X14
SA000075S20
R291 @
100K_0402_1%
Ra
V
V
V
V0.2
1
0
12K +/- 1%
21
23
26
27
BRDID
1
R292 @
0_0402_5%
2
63
64
65
66
75
76
V18R
BATT_TEMP
VCIN1_BATT_TEMP (47)
VCIN1_BATT_DROP (47)
ADP_I (47,48)
ADP_ID (46)
2 @
1
0_0402_5%
68
70
71
72
D
1 100P_0402_50V8J ECAGND
BRDID
R368
83
84
85
86
87
88
2
C438
VCIN1_BATT_TEMP
VCIN1_BATT_DROP
ADP_I
C433
0.1U_0402_16V7K
@
Analog Board ID definition,
Please see page 3.
KBL_W_PWM (32)
BEEP# (26)
EC_FAN_PWM1 (34)
EC_FAN_PWM2 (34)
ENBKL (14)
BKOFF#
AOU_EN (34)
AOU_ILIM (34)
ADP_ID_CLOSE (46)
V0.2
DS3
SUSWARN# (14)
EC_MUTE#
USB_ON#
EC_MUTE#_WF
EC_MUTE# (26)
USB_ON# (30)
EC_MUTE#_WF (27)
SYS_PWROK (14,5)
TP_CLK (32)
TP_DATA (32)
V0.2
TP_CLK
TP_DATA
97
98
99
109
ME_FLASH
VCIN0_PH1
119
120
126
128
SPI_SO_L
SPI_SI_R
1
SPI_CLK_PCH_EC
SPI_SB_CS0#
R118
73
74
89
90
91
92
93
95
121
127
VGA_ALERT#
100
101
102
103
104
105
106
107
108
EC_RSMRST#
AOU_CTL3
110
112
114
115
116
117
118
ACIN
EC_ON
ON/OFF
LID_SW#
SUSP#
NUVOTON_VTT R370 1
PECI_KB9012 R306 1
124
+V18R
C
LAN_PWRDN# (25)
PWR_LEVEL (36) VGA_AC_DET
ME_FLASH (13)
NTC_V
VCIN0_PH1 (47)
SPI Device Interface
V0.2
V0.3
GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13
PS2 Interface
11
24
35
94
113
+3VS
EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
SM
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47
ECAGND (47)
+3VLP_EC
VAD_BID
0 V
0.354
0.430
0.550
Rb
DA Output
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
GND/GND
GND/GND
GND/GND
GND/GND
GND0
1
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
+3VLP_EC
0
1
2
3
C432
0.1U_0402_16V7K
PWM Output
CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D
Rb
2
U18
MAIN@
R560
2
ECAGND
D
(14,18) GATEA20
V0.3
Board ID
100K +/- 1%
Board ID
67
1
+3VLP
+EC_VCCLPC
EC_VDD/AVCC
2
9
22
33
96
111
125
1
@
1
3.3V
Vcc
Ra
L23
1
2 +EC_VCCA
BLM15PD800SN1D
1
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC
2
0_0402_5%
R290
2
2
@
1000P_0402_50V7K
1000P_0402_50V7K
C431
1
JUMP_43X39
@
V0.3
2
1
1000P_0402_50V7K
C430
+3VALW
2
2
@
0.1U_0402_16V7K
C429
1
1
0.1U_0402_16V7K
0.1U_0402_16V7K
C428
1
JP12
0.1U_0402_16V7K
C427
C427
JUMP_43X39
JP@
1
2
2
1
+EC_VCCA
V0.2
2
AGND/AGND
JP8
2
+3VLP_EC
For Power consumption
Measurement
+3VLP
1
3
1
4
ECAGND 69
5
SPI_SO_L (16)
SPI_SI_R (16)
SPI_CLK_PCH (16)
SPI_SB_CS0# (16)
2
15_0402_5%
VGA_ALERT# (36)
VGATE (55)
WF_MUTE# (26) V0.2
BATT_CHG_LED# (33)
CAPS_LED# (32)
PWR_LED# (33)
BATT_LOW_LED# (33)
SYSON (35,50)
VR_ON (55)
PM_SLP_S4# (14)
BATT_CHG_LED#
CAPS_LED#
PWR_LED#
BATT_LOW_LED#
SYSON
PM_SLP_S4#
EC_RSMRST# (14)
AOU_CTL3 (34)
VCIN1_ADP_PROCHOT (47)
VCOUT1_PROCHOT# (47)
VCOUT0_MAIN_PWR_ON (49)
BKOFF# (22)
PBTN_OUT# (14)
V0.2
VCOUT1_PROCHOT#
VCOUT0_MAIN_PWR_ON
2
1 BKOFF#
R367
PBTN_OUT#
0_0402_5%
DPWROK_EC
+1.05VS_PGOOD
V0.2
B
DS3
DPWROK_EC (14)
+1.05VS_PGOOD (52)
2 10K_0402_5%
2 43_0402_1%
@
R307 1
Turbo_V
PROCHOT
MAINPWON
2 0_0402_5%
ACIN (48)
EC_ON (49)
ON/OFF (33)
LID_SW# (33)
SUSP# (35,50,51,52,53)
+1.05VS
H_PECI (5)
+3VLP_EC
V0.3
20mil
V0.2 -- PWR
L24
2
1
BLM15PD800SN1D
V0.2
(55) VR_HOT#
R309 1
2 0_0402_5%
R308 1
2 0_0402_5%
VCOUT1_PROCHOT#
V0.3
(5) H_PROCHOT#
H_PROCHOT#
V0.2
ECAGND
A
A
Compal Secret Data
Security Classification
2014/02/25
Issued Date
Deciphered Date
2015/02/25
Title
Compal Electronics, Inc.
EC ENE-KB9022 C
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
LA-B111P
Date:
5
4
3
2
Tuesday, February 25, 2014
Sheet
1
31
of
59
KSI[0..7]
INT_KBD CONN.
KSO[0..17]
SMSC thermal sensor
placed near by VRAM
15 "
KB15@
KB15@
KB15@
KB15@
KB15@
KB15@
KB15@
KB15@
KB15@
KB15@
KB15@
KB15@
2
2
2
2
2
2
2
2
2
2
2
2
V0.3
+5VS
(31) CAPS_LED#
+5VS
(31) NUM_LED#
620_0402_5%
2
R311 1
R344 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
KB01
KB02
KB03
KB04
KB05
KB06
KB07
KB08
KB09
KB10
KB11
KB12
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
KSO16
KSO17
+5VS_CAPLED
CAPS_LED#
+5VS_NUMLED
NUM_LED#
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
2
620_0402_5%
CONN@
JKB2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
KSO16
KSO17
GND
GND
+5VS_CAPLED
CAPS_LED#
+5VS_NUMLED
NUM_LED#
31
32
R1021 1
R1022 1
R1023 1
R1024 1
R1025 1
R1026 1
R1027 1
R1028 1
R1029 1
R1030 1
R1031 1
R1032 1
KB17@
KB17@
KB17@
KB17@
KB17@
KB17@
KB17@
KB17@
KB17@
KB17@
KB17@
KB17@
2
2
2
2
2
2
2
2
2
2
2
2
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KB01
KB02
KB03
KB04
KB05
KB06
KB07
KB08
KB09
KB10
KB11
KB12
ACES_88514-3001
SP010011A00
R310
10K_0402_5%
@
U20
C444
2
0.1U_0402_16V7K
1
1
REMOTE1+
4
REMOTE2-
(33) REMOTE2-
3
REMOTE2+
(33) REMOTE2+
2
REMOTE1-
5
VDD
SMCLK
DP1
SMDATA
DN1
ALERT#
DP2
THERM#
DN2
GND
10
EC_SMB_CK2
9
EC_SMB_DA2
EC_SMB_CK2 (16,31,36)
EC_SMB_DA2 (16,31,36)
8
7
6
EMC1403-2-AIZL-TR_MSOP10
Address 1001_101xb
GND
GND
Close U20
31
32
Close to DDR
REMOTE1+
REMOTE1+ MMST3904-7-F_SOT323-3
1
C
2
@
C441
Q12
B
100P_0402_50V8J
2
E
REMOTE1-
1
ACES_88514-3001
SP010011A00
1 C479
@ESD@
2
0.1U_0402_16V7K
1
+3VS
CONN@
C442
2200P_0402_50V7K
2 0.1U_0402_16V7K
2
REMOTE1-
3
C480
@ESD@
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
R1001 1
R1002 1
R1003 1
R1004 1
R1005 1
R1006 1
R1007 1
R1008 1
R1009 1
R1010 1
R1011 1
R1012 1
KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
+3VS
17 "
1
JKB1
2
(31) KSI[0..7]
(31) KSO[0..17]
V1.0
REMOTE2+
KB Backlight
15 "
1
C445 @
2200P_0402_50V7K
KB BackLight Control
V0.2
2
Close to FAN
REMOTE2-
move to power board
40mil
REMOTE1,2+/-:
Trace width/space:10/10 mil
Trace length: & lt; 8 "
KB Backlight
17 "
V0.2
JKBL2
+5VS_KBL
+5VS_KBL
V0.3A
2
G
R335
1
2
Q23
2
1
2
0.01U_0402_16V7K
OUT
@
1
C449
1U_0402_16V6K
1
C434
GND
(31) KBL_W_PWM
IN
3
2
1
2
3
4
5
6
100K_0402_5%
V0.3
JKBL1
CONN@
1
2
3
4
5
6
1
2
3
4
+3VS
TouchPad
GND
GND
C446
E & T_6916-Q04N-03R
SP01000TB00
0.1U_0402_16V7K
GND
GND
E & T_6916-Q04N-03R
SP01000TB00
JTP1
TP_CLK
TP_DATA
(31) TP_CLK
(31) TP_DATA
@EMI@
C447
100P_0402_50V8J
1
1
2
2
@EMI@
C448
100P_0402_50V8J
3
1
V0.2
30mil
1
2
3
4
(11,12,16) SMB_CLK_S3
(11,12,16) SMB_DATA_S3
0_0402_5%
1 PCH_SMB_CLK_TP
R313 2
@
2
1 PCH_SMB_DATA_TP
@
R314
0_0402_5%
6
5
4
3
2
1
CONN@
8
7
6 G2
5 G1
4
3
2
1
ACES_51524-0060N-001
SP010014M10
@ESD@
D22
PSOT24C_SOT23-3
V0.3A
DTC124EKAT146_SC59-3
1
1
10K_0402_5%
R315
2
1
R337
3
D
2
Q11
AO3413_SOT23
S
10K_0402_5%
+5VS
@
CONN@
+5VS
2
+5VALW
Compal Secret Data
Security Classification
Issued Date
2014/02/25
Deciphered Date
2015/02/25
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Compal Electronics, Inc.
KB/TP/Thermal sensor
Document Number
Rev
1.0
LA-B111P
Tuesday, February 25, 2014
Sheet
32
of
59
A
B
C
D
E
Connector: 0.3A / pin
PWR Board CONN.
+3VLP
Power Board
+3VALW
4
4
1
2
ON/OFF
NOVO# (31)
3
2
3
1
(31) PWR_LED#
DAN202UT106_SC70-3
D24 @ESD@
PJSOT24C 3P C/A SOT-23
2
ON/OFFBTN#
Q24
AO3413_SOT23
V0.2
PWR_LED
1
1
@
R319
2
PWR_LED#
1
ON/OFF (31)
3
NOVO#
2
2
NOVO_BTN#
R371
10K_0402_5%
NOVO_BTN#
ON/OFFBTN#
1
D23
G
1
R318
100K_0402_5%
D
R317
100K_0402_5%
S
2
V0.2
1
2
C421
0.1U_0402_16V7K
JPWR1
6
5
4
3
2
1
0_0402_5%
ON/OFFBTN#
NOVO_BTN#
REMOTE2+
REMOTE2-
1
(32) REMOTE2+
(32) REMOTE2-
JPW1 @
0_0805_5%
CONN@
8
7
2
ACES_51524-0060N-001
SP010014M10
1
3
6 G2
5 G1
4
3
2
1
C440
10P_0402_25V8J
@ESD@
QAD on/off test purpose
1
2
2
C439
10P_0402_25V8J
@ESD@
3
Lid switch
LED-B CONN
1 R320
2
100K_0402_5%
+3VALW
2
V0.2
VOUT
2
LID_SW# (31)
+3VLP
(31) BATT_LOW_LED#
(31) BATT_CHG_LED#
(13) SATA_LED#
(31) TP_LOCK_LED#
2
1
PWR_LED
BATT_LOW_LED#
BATT_CHG_LED#
SATA_LED#
TP_LOCK_LED#
C453
10P_0402_50V8J
+3VS
V0.3
GND
2
VCC
1
C452
0.1U_0402_16V7K
3
LID_SW#
2
JLED1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
G2
G1
10
9
1
ACES_51522-00801-001
CONN@
V0.3
U21
SA00004PT00
1
1
Compal Secret Data
Security Classification
Issued Date
2014/02/25
2015/02/25
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Compal Electronics, Inc.
PWR_BTN/PWR_B/LED_B/LID
Document Number
Rev
1.0
LA-B111P
Tuesday, February 25, 2014
Sheet
E
33
of
59
5
4
3
2
1
+5VALW
@
C454
2 0.1U_0402_16V7K
@EMI@
Alway on USB
USB20_P4_CONN
USB20_N4_L
2
1
USB20_N4_CONN
12
10
11
2
3
15
16
14
17
USB20_P4_L
USB20_N4_L
R324 1
R323 1
USB20_N4 (17)
USB20_P4 (17)
2 80.6K_0402_1%
2 20K_0402_1%
1
2
@
CTL1~3,ILIM_SEL
0 1 0 1
0 1 0 1
S3
USB Board CONN.
0 1 1 1
0 1 0 0
0 1 0 0
JSUB1
31
+USB2_VCCC
V0.2
(14,25,28,31,36) PLT_RST#
(15) CLKREQ_CR#
(17) PCIE_PTX_C_DRX_P5
(17) PCIE_PTX_C_DRX_N5
(17) PCIE_PRX_DTX_P5
(17) PCIE_PRX_DTX_N5
(26) HP_OUTL
(26) HP_OUTR
(26) EXT_MIC_SLEEVE
(26) EXT_MIC_RING2
EMC
1
SPDIF-OUT
@EMI@
2
R347
22_0402_5%
1
2
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
PCIE_PTX_C_DRX_P5
PCIE_PTX_C_DRX_N5
PCIE_PRX_DTX_P5
PCIE_PRX_DTX_N5
HP_OUTL
HP_OUTR
EXT_MIC_SLEEVE
EXT_MIC_RING2
40 mils
40 mils
(26) MIC2-VREFO
R321 1
2 2.2K_0402_5%
R322 1
@EMI@
C476
22P_0402_50V8J
FD1
FIDUCAL
@
FD4
FIDUCAL
1
1
1
@
H_4P2
H6 @
HOLEA
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
USB20_P4_CONN
USB20_N4_CONN
CLK_PCIE_CR
CLK_PCIE_CR#
C
CLK_PCIE_CR (15)
CLK_PCIE_CR# (15)
+3VS
PLUG_IN#
SPDIF-OUT
+5VS
PLUG_IN# (26)
SPDIF-OUT (26)
ACES_50255-03001-001
SP02000RN00
0_0603_5%
2
JFAN1
1
2
3
4
5
6
+5VS_FAN
(31) EC_TACH1
(31) EC_FAN_PWM1
H10 @
HOLEA
V1.0
H12 @
HOLEA
2
H13 @
HOLEA
MB
C456
10U_0603_6.3V6M
1
1
1
1
H_4P2
H_4P2
H_2P5
H_2P5
CONN@
1
2
3
4
G5
G6
ACES_50273-0040N-001
SP02000TI00
1
1
H_4P2
B
+5VS
@
R325
1
H5 @
HOLEA
@
1
1
H3 @
HOLEA
FD3
FIDUCAL
1
1
@
FD2
FIDUCAL
1
CPU
32
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
Fan1 Control Circuit
V1.0
GPU
H_4P2
CONN@
31
2 2.2K_0402_5%
B
H_4P2
YSLC05CH_SOT23-3
@ESD@
@EMI@
C
H4 @
HOLEA
V0.3
TPS2544RTER_QFN16_3X3
SA000070N00
S4/S5
H2 @
HOLEA
EXT_MIC_RING2
1
V0.2A
MCF12102G900-T_4P
2
1 0_0402_5%
R336
D
EXT_MIC_SLEEVE
2
1
OUT
DP_IN
DM_IN
DM_OUT
DP_OUT
ILIM_LO
ILIM_HI
GND
T-PAD
S0
H1 @
HOLEA
D25
3
IN
STATUS#
FAULT#
ILIM_SEL
EN
CTL1
CTL2
CTL3
S3/S4/S5
Disable
4
2
1
9
13
4
5
6
7
8
Mode
S0
Enable
3
C467
R564
R301 1
1
R316
EMI@
USB20_P4_L
U22
0.1U_0402_16V7K
C468
C468
1
1 0_0402_5%
L25
+USB2_VCCC
2
0_0402_5%
2
0_0402_5%
2 0_0402_5%
@
2
0_0402_5%
V0.2
R561
2
R338
+USB2_VCCC
47U_0805_6.3V6M
V0.2
(35) SUSP
(31) AOU_CTL3
1
2
1 R562
@
10K_0402_5%
2
1 R565
@
10K_0402_5%
2
1
0_0402_5% R563
D
1
2 4.7U_0402_6.3V6M
C455
(17) USB_OC2#
(31) AOU_ILIM
(31) AOU_EN
1
H_3P0
10U
H7 @
HOLEA
H15 @
HOLEA
H16 @
HOLEA
1
1
1
H_3P2
A
1
WLAN
H_2P5
H_2P5
JDUG1
1
2
3
4
5
6
+3VS
(28,31) EC_TX
(28,31) EC_RX
H_3P0
H8 @
HOLEA
H9 @
HOLEA
H20
HOLEA
H21
HOLEA
CONN@
R343
1
2
3
4
G5
G6
1
@
0_0603_5%
2
JFAN2
1
2
3
4
5
6
+5VS_FAN2
(31) EC_TACH2
(31) EC_FAN_PWM2
2
ACES_50273-0040N-001
SP02000TI00
1
H22
HOLEA
C474
10U_0603_6.3V6M
CONN@
1
2
3
4
G5
G6
A
ACES_50273-0040N-001
SP02000TI00
10U
1
1
1
1
1
LAN
FAN2 Control Circuit
+5VS
H17 @
HOLEA
H_3P3
H_1P5N
H_1P5N
for LAN screw hole
CHASSIS1_GND
H_3P3
Issued Date
橢橢橢
5
Compal Secret Data
Security Classification
H_4P0X3P0
2014/02/25
2015/02/25
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
4
3
2
Compal Electronics, Inc.
USB charge/FAN/Screw holes
Document Number
Rev
1.0
LA-B111P
Tuesday, February 25, 2014
Sheet
1
34
of
59
A
B
C
D
E
+5VALW to +5VS Transfer
+5VALW
+3VALW
+5VS
VIN2
VIN2
120mil
V0.2
SA00006FD00
APE8990GN3B
2
2
+5VALW
R353
1@
2
2
1
DS3@
2
PCH_PWR_EN#
@
R352
470_0603_5%
2
1
1
@
1
15
GPAD
2@
2
C461
470P_0402_50V7K
+3VSJ
9
8
VOUT2
VOUT2
C460
2
1 TPS22966DPUR_SON14_2X3
C464
2
C463
10U_0603_6.3V6M
0.1U_0402_16V7K
1
C462 1
10
CT2
2
Q10
DS3@
@ C482
2
1
GND
1
1U_0402_6.3V6K
ON2
11
1
1
D
2
PCH_PWR_EN#
G
Q13 @
2N7002K_SOT23-3
S
3
@
6
7
VBIAS
220P_0402_50V7K
1
47K_0402_5%
1
V0.2
+3VSJ
+3VS
JP@
2
2
V0.3
JP9
JUMP_43X118
1
2
1
1
D
2
G
(31) PCH_PWR_EN
3
+3VALW
CT1
2
3
10U_0603_6.3V6M
5
ON1
C459 1
0.01U_0402_16V7K
4
12
JP5
JUMP_43X118
1
2
1
DS3@ C484
4.7U_0603_6.3V6K
C466
R327
10K_0402_5%
10K_0402_5%
2
3
200mil
14
13
VOUT1
VOUT1
1
(31,50,51,52,53) SUSP#
1
3VS_EN
0_0402_5%
VIN1
VIN1
1
DS3@ C483
U23
1
2
+5VL
R326 2
JP@
2
C465
0.1U_0402_16V7K
+5VSJ
1
1
C458
0.01U_0402_16V7K
2
10U_0603_6.3V6M
AO3413_SOT23
2
2
C457 @
10U_0603_6.3V6M
1
+3V_PCH
JP10
JP@
JUMP_43X39
2
1
2
1
+5VSJ
4.7U_0603_6.3V6K
1
S
C481 DS3@
0.1U_0402_16V7K
2
2N7002K_SOT23-3
DS3@
Q21
2
+3VALW to +3VS Transfer
Discharge circuit-1
+1.35V
+0.675VS
+5VALW
+1.05VS
+1.5VS
1
1
+3VALW
1
2
6
Q8
2N7002H_SOT23-3
@
SUSP
Q18A
2N7002KDWH_SOT363-6
@
2
S
3
2
3
2
1
D
2
G
SUSP
Q18B
2N7002KDWH_SOT363-6
@
5
4
Q7
2N7002H_SOT23-3
@
SUSP#
@
V0.3A
1
S
5
SUSP
Q17A
2N7002KDWH_SOT363-6
@
4
2
3
2
6
3
(34) SUSP
Q17B
2N7002KDWH_SOT363-6
SYSON#
1
1
D
2
G
V0.3A
@
V0.2
1
@
10K_0402_5%
R334
R334
2
SYSON
(31,50) SYSON
V0.3A
R332
100_0402_1%
@
VCCP_CHG
V0.3A
@
R333
100K_0402_5%
V0.2
1.5VS_CHG
V0.3A
1.35V_CHG
V0.3A
@
0.675VS_CHG
@
3
R331
100_0402_1%
1
R328
22_0402_5%
R330
68_0402_5%
2
R329
100K_0402_5%
@
2
1
1
3
4
4
Compal Secret Data
Security Classification
Issued Date
2014/02/25
2015/02/25
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Compal Electronics, Inc.
DC/DC Interface
Document Number
Rev
1.0
LA-B111P
Tuesday, February 25, 2014
Sheet
E
35
of
59
5
4
3
2
1
+3V3_AON
U30A
AJ12
AP29
under GPU
close to AD8
C603
10U_0603_6.3V6M
DIS@
1
2
AM9
AN9
2
I2C
RP38
I2CC_SCL
I2CC_SDA
I2CS_SCL
I2CS_SDA
SMB_CLK_GPU
SMB_DATA_GPU
1
T4
T3
+3V_PCH
10K_8P4R_5%
DIS@
Green CLK
SP_PLLVDD
VID_PLLVDD
PEX_RST_N
PEX_TERMP
XTAL_IN
XTAL_OUT
XTAL_OUTBUFF
XTAL_SSIN
AD8
GCLK@
1
XTALIN
R516
+PLLVDD
AE8
AD7
+GPU_PLLVDD
H3
H2
XTALIN
XTAL_OUT
J4
H1
XTAL_OUTBUFF
XTAL_SSIN
DIS@
1
2
DIS@
1
2
+1.05VSG
L30
BLM15PX181SN1D
1
2
DIS@
1
DIS@
DIS@
2
2
0_0402_5%
C638
NOGCLK@
15P_0402_50V8J
1
1
3
GND
GND
2
4
2
V1.0
NOGCLK@
1
R423 2
3
C639
NOGCLK@
15P_0402_50V8J
XTAL_OUT
B
1
2
1K_0402_1%
V0.3
V0.3A
C640 under GPU
close to ball : AE8,AD7
DIS@
V1.0
V1.0
+3V3_AON
+3V3_AON
D
CLK_REQ_VGA#
CLK_REQ_VGA# (15)
2 DIS@
C646
0.1U_0402_25V6K
(14,25,28,31,34) PLT_RST#
IN2
+3V3_AON
4
SYS_PEX_RST_MON# 1
DGPU_RST_HOLD#
MC74VHC1G08DFT2G SC70 5P
DIS@
5
A
2
SMB_CLK_GPU
DIS@
1
Q32A
4
Q32B
2
IN1
IN2
5
U39
OUT
1
VCC
2
IN1
3
Internal Thermal Sensor
1
GND
V0.2
(14) DGPU_HOLD_RST#
2 SW@
C645
0.1U_0402_25V6K
1
3
U40
VCC
When REFCLK current is below 20mA, don't need
above gate control for CLKREQ_GPU#, and keep
REFCLK free running
GND
2N7002K_SOT23-3
1
2
@
R403
0_0402_5%
SMB_DATA_GPU
CLK_27M_VGA_XIN (27)
V0.2
NOGCLK@
Y5 27MHZ_10PF_7V27000050
1
XTALIN
5
1
8
7
6
5
1
1
Q33
V0.2
RP35
1
2
3
VGA_CLKREQ#_R 4
NVVDD_PSI
R501
10K_0402_5%
DIS@
3
8
7
6
5
10K_8P4R_5%
DIS@
(37) JTAG_TRST
(37) TESTMODE
N15P-GX_BGA908
S
VGA_CLKREQ#_R
1
GC6_FB_EN
2
GPU_EVENT#_R
DGPU_RST_HOLD# 3
4
DIS@
R488
100K_0402_5%
VGA_EDID_CLK
VGA_EDID_DATA
C
RP39
1.35V_PWR_EN (45)
2
2
HDCP_SCL
HDCP_SDA
R2
R3
8
7
6
5
2.2K_8P4R_5%
@
2
DGPU_PWROK
G
G
2
V0.3
R402
2.49K_0402_1%
1
2
3
4
3
VGA_CRT_CLK
VGA_CRT_DATA
R7
R6
8
7
6
5
2.2K_8P4R_5%
DIS@
VGA_CRT_CLK
VGA_CRT_DATA
HDCP_SDA
HDCP_SCL
D30
DAN202UT106_SC70-3
I2CB_SCL
I2CB_SDA
1
2
3
4
SW@
R4
R5
8
7
6
5
RP37
22U 0603 C941,C945
for layout limitation
(18,45,54) DGPU_PWROK
I2CA_SCL
I2CA_SDA
+3V3_AON
RP36
1
2
3
4
3V3_MAIN_EN
VGA_ALERT#
GPU_OVERT#
XTAL_SSIN
SMB_CLK_GPU
SMB_DATA_GPU
VGA_EDID_DATA
VGA_EDID_CLK
11.35V_PWR_EN
NC
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N
2
1
@
C644
AJ26
AK26
1
GC6_FB_EN
PLLVDD
PEX_REFCLK
PEX_REFCLK_N
PEX_CLKREQ_N
GPU_EVENT# (14)
10K_8P4R_5%
DIS@
2
Default unstuffed
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT#
DGPU_PEX_RST#
B
1
2
@
R401
200_0402_1%
AL13
AK13
AK12
DIS@
1
2
BLM15AX300SN1D
10U_0603_6.3V6M
VGA_CLKREQ#_R
(15) CLK_PEG_VGA
(15) CLK_PEG_VGA#
DACA_VDD
DACA_VREF
DACA_RSET
AK9
AL10
AL9
AG10
AP9
AP8
D
1
(37,45) GPU_OVERT#
+PLLVDD
DACA_HSYNC
DACA_VSYNC
1 DIS@ 2
R517
10K_0402_5%
RB751V-40_SOD323-2
+1.05VSG
1
AJ11
PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N
PWR_LEVEL (31)
D34
RB751V-40_SOD323-2
1
DIS@ 2
R421
0_0402_5%
DGPU_RST_HOLD#
C643
2
AK14
AJ14
AH14
AG14
AK15
AJ15
AL16
AK16
AK17
AJ17
AH17
AG17
AK18
AJ18
AL19
AK19
AK20
AJ20
AH20
AG20
AK21
AJ21
AL22
AK22
AK23
AJ23
AH23
AG23
AK24
AJ24
AL25
AK25
1
@
GPU_EVENT#_R 2
EC
22U_0603_6.3V6M
PEG_CRX_C_GTX_P0
PEG_CRX_C_GTX_N0
PEG_CRX_C_GTX_P1
PEG_CRX_C_GTX_N1
PEG_CRX_C_GTX_P2
PEG_CRX_C_GTX_N2
PEG_CRX_C_GTX_P3
PEG_CRX_C_GTX_N3
PEG_CRX_C_GTX_P4
PEG_CRX_C_GTX_N4
PEG_CRX_C_GTX_P5
PEG_CRX_C_GTX_N5
PEG_CRX_C_GTX_P6
PEG_CRX_C_GTX_N6
PEG_CRX_C_GTX_P7
PEG_CRX_C_GTX_N7
PEG_CRX_C_GTX_P8
PEG_CRX_C_GTX_N8
PEG_CRX_C_GTX_P9
PEG_CRX_C_GTX_N9
PEG_CRX_C_GTX_P10
PEG_CRX_C_GTX_N10
PEG_CRX_C_GTX_P11
PEG_CRX_C_GTX_N11
PEG_CRX_C_GTX_P12
PEG_CRX_C_GTX_N12
PEG_CRX_C_GTX_P13
PEG_CRX_C_GTX_N13
PEG_CRX_C_GTX_P14
PEG_CRX_C_GTX_N14
PEG_CRX_C_GTX_P15
PEG_CRX_C_GTX_N15
VGA_ALERT# (31)
VRAM_VREF_CTL (41,43)
NVVDD_PWM_VID (54)
TO
PWR_LEVEL_R (47)
NVVDD_PSI (54)
4.7U_0603_6.3V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
2
2
10K_0402_5%
TO PCH THRMTRIP#
TO EC
C602
22U_0603_6.3V6M
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
PWR_LEVEL_R
TO PCH
D31
SYS_PEX_RST_MON#
VGA_ALERT#
VRAM_VREF_CTL
NVVDD_PWM_VID
PWR_LEVEL_R
NVVDD_PSI
C642
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3V3_MAIN_EN (45,54)
C607
0.1U_0402_16V7K
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C601
C604
C606
C609
C610
C611
C612
C613
C614
C615
C616
C617
C618
C619
C620
C621
C622
C623
C624
C625
C626
C627
C628
C629
C630
C631
C632
C633
C634
C635
C636
C637
1 DIS@ 2
R502
100K_0402_5%
DIS@
3V3_MAIN_EN
GPU_EVENT#_R
L31
DACA_RED
DACA_GREEN
DACA_BLUE
1
R503
XTAL_OUTBUFF
TO PCH
GC6_FB_EN (14,38)
0.1U_0402_16V7K
C
PEG_CRX_GTX_P0
PEG_CRX_GTX_N0
PEG_CRX_GTX_P1
PEG_CRX_GTX_N1
PEG_CRX_GTX_P2
PEG_CRX_GTX_N2
PEG_CRX_GTX_P3
PEG_CRX_GTX_N3
PEG_CRX_GTX_P4
PEG_CRX_GTX_N4
PEG_CRX_GTX_P5
PEG_CRX_GTX_N5
PEG_CRX_GTX_P6
PEG_CRX_GTX_N6
PEG_CRX_GTX_P7
PEG_CRX_GTX_N7
PEG_CRX_GTX_P8
PEG_CRX_GTX_N8
PEG_CRX_GTX_P9
PEG_CRX_GTX_N9
PEG_CRX_GTX_P10
PEG_CRX_GTX_N10
PEG_CRX_GTX_P11
PEG_CRX_GTX_N11
PEG_CRX_GTX_P12
PEG_CRX_GTX_N12
PEG_CRX_GTX_P13
PEG_CRX_GTX_N13
PEG_CRX_GTX_P14
PEG_CRX_GTX_N14
PEG_CRX_GTX_P15
PEG_CRX_GTX_N15
XTAL_OUTBUFF
PWR_LEVEL_R
GC6_FB_EN
C640
SE095224K00
S CER CAP 0.22U 10V K X5R 0402
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
P6
M3
L6
P5
P7
L7
M7
N8
L3
M2
L1
M5
N3
M4
N4
P2
R8
M6
R1
P3
P4
P1
DIS@
D
@
GPIO
PEG_PTX_C_DRX_N[0..15]
(4) PEG_PTX_C_DRX_N[0..15]
Part 1 of 7
DACs
PEG_PTX_C_DRX_P[0..15]
(4) PEG_PTX_C_DRX_P[0..15]
PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N
I2C
PEG_CRX_GTX_N[0..15]
(4) PEG_CRX_GTX_N[0..15]
AN12
AM12
AN14
AM14
AP14
AP15
AN15
AM15
AN17
AM17
AP17
AP18
AN18
AM18
AN20
AM20
AP20
AP21
AN21
AM21
AN23
AM23
AP23
AP24
AN24
AM24
AN26
AM26
AP26
AP27
AN27
AM27
CLK
PEG_PTX_C_DRX_P0
PEG_PTX_C_DRX_N0
PEG_PTX_C_DRX_P1
PEG_PTX_C_DRX_N1
PEG_PTX_C_DRX_P2
PEG_PTX_C_DRX_N2
PEG_PTX_C_DRX_P3
PEG_PTX_C_DRX_N3
PEG_PTX_C_DRX_P4
PEG_PTX_C_DRX_N4
PEG_PTX_C_DRX_P5
PEG_PTX_C_DRX_N5
PEG_PTX_C_DRX_P6
PEG_PTX_C_DRX_N6
PEG_PTX_C_DRX_P7
PEG_PTX_C_DRX_N7
PEG_PTX_C_DRX_P8
PEG_PTX_C_DRX_N8
PEG_PTX_C_DRX_P9
PEG_PTX_C_DRX_N9
PEG_PTX_C_DRX_P10
PEG_PTX_C_DRX_N10
PEG_PTX_C_DRX_P11
PEG_PTX_C_DRX_N11
PEG_PTX_C_DRX_P12
PEG_PTX_C_DRX_N12
PEG_PTX_C_DRX_P13
PEG_PTX_C_DRX_N13
PEG_PTX_C_DRX_P14
PEG_PTX_C_DRX_N14
PEG_PTX_C_DRX_P15
PEG_PTX_C_DRX_N15
PCI EXPRESS
PEG_CRX_GTX_P[0..15]
(4) PEG_CRX_GTX_P[0..15]
OUT
4
DGPU_PEX_RST#
DGPU_PEX_RST# (45)
MC74VHC1G08DFT2G SC70 5P
SW@
A
DIS@
3
EC_SMB_CK2 (16,31,32)
2N7002KDWH_SOT363-6
Compal Secret Data
Security Classification
Issued Date
6
2N7002KDWH_SOT363-6
2014/02/25
2015/02/25
Deciphered Date
Title
Compal Electronics, Inc.
N15P-GX (1/5) PEG & DAC
EC_SMB_DA2 (16,31,32)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
LA-B111P
Date:
5
4
3
2
Tuesday, February 25, 2014
Sheet
1
36
of
59
5
4
3
2
Logical
Strapping Bit3
Logical
Strapping Bit2
Logical
Strapping Bit1
Logical
Strapping Bit0
+3VS_DGPU
SOR3_EXPOSED
SOR2_EXPOSED
SOR1_EXPOSED
SOR0_EXPOSED
ROM_SO
+3VS_DGPU
RAM_CFG[3]
ROM_SI
+3VS_DGPU
DEVID_SEL
Physical
Strapping pin
ROM_SCLK
U30D
Part 4 of 7
AG3
AG2
AK3
AK2
AB3
AB4
AF3
AF2
SKU
R404
100_0402_1%
Device ID
N15P-GX
bit5 to bit0
5K
0x1392
L5
VSSSENSE_VGA
AK11
OVERT
IFPC_AUX_I2CW_SCL
IFPC_AUX_I2CW_SDA_N
IFPD_AUX_I2CX_SCL
IFPD_AUX_I2CX_SDA_N
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
PAD
PAD
PAD
PAD
T51
T52
T50
T53
M1
J1
0101
1110
0110
1111
0111
C
@
@
@
@
MULTI LEVEL STRAPS
+3V3_AON
+3VS_DGPU
MULTI_STRAP_REF0_GND
@
@
@
@
@
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
THERMDP
THERMDN
GPU
FB Memory DDR5
X76L02@
K3
K4
Samsung
2G
X76L01@
ZZZ4
X76L03@
B
ROM_SI
K4G20325FD-FC03
PD 5K
Hynix
2G
H5GC2H24BFR-T2C
Hynix
4G
H5GC4H24MFR-T2C
Samsung
4G
K4G41325FC-HC03
PD 10K
10K_0402_1%
15K_0402_1%
X7654438L01
X76L01@
IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N
2
1
R413
4.99K_0402_1%
For X76 (N15P-GX)
128Mx16
IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA_N
DIS@
GPU_OVERT# (36,45)
1 DIS@ 2
R424
40.2K_0402_1%
ZZZ3
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
J2
J7
J6
J5
J3
DIS@
@
2
1
R419
4.99K_0402_1%
ROM_SI
ROM_SO
ROM_SCLK
STRAP3
STRAP4
@
2
1
R439
10K_0402_1%
@
2
1
R420
4.99K_0402_1%
2
1
R410
10K_0402_1%
@
2
1
R418
45.3K_0402_1%
DIS@
1
2
R422
10K_0402_5%
GPU_OVERT#
@
2
1
R409
45.3K_0402_1%
STRAP0
STRAP1
STRAP2
ROM_SCLK
ROM_SI
ROM_SO
@
2
1
R408
4.99K_0402_1%
@
2
1
R407
4.99K_0402_1%
JTAG_TRST (36)
2
1
R417
4.99K_0402_1%
L2
0100
1101
35K
@
BUFRST_N
0011
1100
30K
SERIAL
GENERAL
0010
1011
TESTMODE (36)
AM10
AM11
AP12
AP11
AN11
H6
H4
H5
H7
0001
1010
25K
VSSSENSE_VGA (54)
1001
15K
VCCSENSE_VGA (54)
DIS@
ROM_CS_N
ROM_SCLK
ROM_SI
ROM_SO
0000
10K
20K
VCCSENSE_VGA
TEST
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
Pull-down to Gnd
45K
L4
2 DIS@ 1
R405
100_0402_1%
TESTMODE
Pull-up to +3VS
_DGPU
1000
Resistor Values
2
1
R412
14.7K_0402_1%
GND_SENSE
MULTI_STRAP_REF0_GND
B
STRAP4
+VGA_CORE
2
1
R416
4.99K_0402_1%
IFPF_L0
IFPF_L0_N
IFPF_L1
IFPF_L1_N
IFPF_L2
IFPF_L2_N
IFPF_L3
IFPF_L3_N
RESERVED
2
1
R415
4.99K_0402_1%
AE3
AE4
AF4
AF5
AD4
AD5
AG1
AF1
IFPE_L0
IFPE_L0_N
IFPE_L1
IFPE_L1_N
IFPE_L2
IFPE_L2_N
IFPE_L3
IFPE_L3_N
STRAP2
D
STRAP3
2
1
R406
49.9K_0402_1%
AD2
AD3
AD1
AC1
AC2
AC3
AC4
AC5
IFPD_L0
IFPD_L0_N
IFPD_L1
IFPD_L1_N
IFPD_L2
IFPD_L2_N
IFPD_L3
IFPD_L3_N
VGA_DEVICE
Keep pull-up to 3V3_AON and pull-down to GND foot print and stuff 50K ohm pull-up
2
1
R414
4.99K_0402_1%
C
IFPC_L0
IFPC_L0_N
IFPC_L1
IFPC_L1_N
IFPC_L2
IFPC_L2_N
IFPC_L3
IFPC_L3_N
LVDS/TMDS
AM1
AM2
AM3
AM4
AL3
AL4
AK4
AK5
RAM_CFG[0]
STRAP0
STRAP1
trace width: 16mils
differential voltage sensing.
differential signal routing.
DIS@
VDD_SENSE
AK1
AJ1
AJ3
AJ2
AH3
AH4
AG5
AG4
RAM_CFG[1]
SMB_ALT_ADDR
RAM_CFG[2]
PCIE_CFG
2
1
R411
4.99K_0402_1%
IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N
Power Rail
2
AJ9
AH9
AP6
AP5
AM7
AL7
AN8
AM8
AK8
AL8
3V3AUX_NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
P8
AC6
AJ28
AJ4
AJ5
AL11
C15
D19
D20
D23
D26
H31
T8
V32
1
D
IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N
NC
AM6
AN6
AP3
AN3
AN5
AM5
AL6
AK6
AJ6
AH6
1
X7654438L03
ZZZ5
X76L02@
ZZZ6
X76L04@
N15P-GX
X76L03@
PD 15K
256Mx16
N15P-GX_BGA908
5K_0402_1%
X76L04@
20K_0402_1%
X7654438L02
X7654438L04
PD 20K
A
A
Compal Secret Data
Security Classification
Issued Date
2014/02/25
2015/02/25
Deciphered Date
Title
Compal Electronics, Inc.
N15P-GX (2/5) TMDS/LVDS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
LA-B111P
Date:
5
4
3
2
Tuesday, February 25, 2014
Sheet
1
37
of
59
5
4
3
2
MDA[15..0]
U30C
(41) DQMA[3..0]
DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7
(42) DQMA[7..4]
(41) DQSA[3..0]
DQSA0
DQSA1
DQSA2
DQSA3
DQSA4
DQSA5
DQSA6
DQSA7
(42) DQSA[7..4]
P30
F31
F34
M32
AD31
AL29
AM32
AF34
M31
G31
E33
M33
AE31
AK30
AN33
AF33
M30
H30
E34
M34
AF30
AK31
AM34
AF32
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
FBA_CMD32
FBA_CMD33
FBA_CMD34
FBA_CMD35
FBA_CLK0
FBA_CLK0_N
FBA_CLK1
FBA_CLK1_N
FBA_WCK01
FBA_WCK01_N
FBA_WCK23
FBA_WCK23_N
FBA_WCK45
FBA_WCK45_N
FBA_WCK67
FBA_WCK67_N
NC
NC
NC
NC
NC
NC
NC
NC
FB_CLAMP
FB_DLL_AVDD
FBA_PLL_AVDD
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
FB_VREF
U30
CMDA0
T31
CMDA1
U29
CMDA2
R34
CMDA3
R33
CMDA4
U32
CMDA5
U33
CMDA6
U28
CMDA7
V28
CMDA8
V29
CMDA9
V30
CMDA10
U34
CMDA11
U31
CMDA12
V34
CMDA13
V33
CMDA14
Y32
CMDA15
AA31
CMDA16
AA29
CMDA17
AA28
CMDA18
AC34
CMDA19
AC33
CMDA20
AA32
CMDA21
AA33
CMDA22
Y28
CMDA23
Y29
CMDA24
W31
CMDA25
Y30
CMDA26
AA34
CMDA27
Y31
CMDA28
Y34
CMDA29
Y33
CMDA30
V31
CMDA31
R28
AC28
R32 FBA_DEBUG0
AC32 FBA_DEBUG1
R427
2
@
2
@
R429
R30
R31
AB31
AC31
+1.35VSG
1 60.4_0402_1%
1
60.4_0402_1%
CLKA0 (41)
CLKA0# (41)
CLKA1 (42)
CLKA1# (42)
K31
L30
H34
J34
AG30
AG31
AJ34
AK34
FBA_WCK01 (41)
FBA_WCK01# (41)
FBA_WCK23 (41)
FBA_WCK23# (41)
FBA_WCK45 (42)
FBA_WCK45# (42)
FBA_WCK67 (42)
FBA_WCK67# (42)
J30
J31
J32
J33
AH31
AJ31
AJ32
AJ33
E1
(43) DQMC[3..0]
(44) DQMC[7..4]
(43) DQSC[3..0]
GC6_FB_EN_R
K27
Under GPU
close to ball : K27
U27
C648 DIS@
1
2
0.1U_0402_16V7K
+FB_PLLAVDD
H26
(44) DQSC[7..4]
DQMC0
DQMC1
DQMC2
DQMC3
DQMC4
DQMC5
DQMC6
DQMC7
DQSC0
DQSC1
DQSC2
DQSC3
DQSC4
DQSC5
DQSC6
DQSC7
G9
E9
G8
F9
F11
G11
F12
G12
G6
F5
E6
F6
F4
G4
E2
F3
C2
D4
D3
C1
B3
C4
B5
C5
A11
C11
D11
B11
D8
A8
C8
B8
F24
G23
E24
G24
D21
E21
G21
F21
G27
D27
G26
E27
E29
F29
E30
D30
A32
C31
C32
B32
D29
A29
C29
B29
B21
C23
A21
C21
B24
C24
B26
C26
E11
E3
A3
C9
F23
F27
C30
A24
D10
D5
C3
B9
E23
E28
B30
A23
D9
E4
B2
A9
D22
D28
A30
B23
1
2
C649
0.1U_0402_16V7K
DIS@
Under GPU
close to ball : U27
N15P-GX_BGA908
A
CMDC[31..0] (42,43,44)
Part 3 of 7
MDC0
MDC1
MDC2
MDC3
MDC4
MDC5
MDC6
MDC7
MDC8
MDC9
MDC10
MDC11
MDC12
MDC13
MDC14
MDC15
MDC16
MDC17
MDC18
MDC19
MDC20
MDC21
MDC22
MDC23
MDC24
MDC25
MDC26
MDC27
MDC28
MDC29
MDC30
MDC31
MDC32
MDC33
MDC34
MDC35
MDC36
MDC37
MDC38
MDC39
MDC40
MDC41
MDC42
MDC43
MDC44
MDC45
MDC46
MDC47
MDC48
MDC49
MDC50
MDC51
MDC52
MDC53
MDC54
MDC55
MDC56
MDC57
MDC58
MDC59
MDC60
MDC61
MDC62
MDC63
FBB_D0
FBB_D1
FBB_D2
FBB_D3
FBB_D4
FBB_D5
FBB_D6
FBB_D7
FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D30
FBB_D31
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63
FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8
FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_CMD31
FBB_CMD32
FBB_CMD33
FBB_CMD34
FBB_CMD35
FBB_CLK0
FBB_CLK0_N
FBB_CLK1
FBB_CLK1_N
FBB_WCK01
FBB_WCK01_N
FBB_WCK23
FBB_WCK23_N
FBB_WCK45
FBB_WCK45_N
FBB_WCK67
FBB_WCK67_N
NC
NC
NC
NC
NC
NC
NC
NC
FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3
FBB_DQM4
FBB_DQM5
FBB_DQM6
FBB_DQM7
FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7
D13
CMDC0
E14
CMDC1
F14
CMDC2
A12
CMDC3
B12
CMDC4
C14
CMDC5
B14
CMDC6
G15
CMDC7
F15
CMDC8
E15
CMDC9
D15
CMDC10
A14
CMDC11
D14
CMDC12
A15
CMDC13
B15
CMDC14
C17
CMDC15
D18
CMDC16
E18
CMDC17
F18
CMDC18
A20
CMDC19
B20
CMDC20
C18
CMDC21
B18
CMDC22
G18
CMDC23
G17
CMDC24
F17
CMDC25
D16
CMDC26
A18
CMDC27
D17
CMDC28
A17
CMDC29
B17
CMDC30
E17
CMDC31
G14
G20
R428
C12 FBC_DEBUG0
2
@
C20 FBC_DEBUG1
2
@
R430
D12
E12
E20
F20
D
C
+1.35VSG
1 60.4_0402_1%
1
60.4_0402_1%
CLKC0 (43)
CLKC0# (43)
CLKC1 (44)
CLKC1# (44)
F8
E8
A5
A6
D24
D25
B27
C27
FBB_WCK01 (43)
FBB_WCK01# (43)
FBB_WCK23 (43)
FBB_WCK23# (43)
FBB_WCK45 (44)
FBB_WCK45# (44)
FBB_WCK67 (44)
FBB_WCK67# (44)
+FB_PLLAVDD
D6
D7
C6
B6
F26
E26
A26
A27
+1.05VSG
+FB_PLLAVDD
1
2
B
L32
DIS@
1
2
BLM15AX300SN1D
Or use same as L10 PN: SM01000FE00
L15= 30ohm
FBB_PLL_AVDD
H17
+FB_PLLAVDD
1
FBB_DQS_RN0
FBB_DQS_RN1
FBB_DQS_RN2
FBB_DQS_RN3
FBB_DQS_RN4
FBB_DQS_RN5
FBB_DQS_RN6
FBB_DQS_RN7
DIS@
2
C650
0.1U_0402_16V7K
B
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
MEMORY INTERFACE
A
C
L28
M29
L29
M28
N31
P29
R29
P28
J28
H29
J29
H28
G29
E31
E32
F30
C34
D32
B33
C33
F33
F32
H33
H32
P34
P32
P31
P33
L31
L34
L32
L33
AG28
AF29
AG29
AF28
AD30
AD29
AC29
AD28
AJ29
AK29
AJ30
AK28
AM29
AM31
AN29
AM30
AN31
AN32
AP30
AP32
AM33
AL31
AK33
AK32
AD34
AD32
AC30
AD33
AF31
AG34
AG32
AG33
DIS@ C647
22U_0805_6.3V6M
CMDA[31..0] (41,42)
Part 2 of 7
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
MDC[63..48]
(44) MDC[63..48]
U30B
D
MDC[47..32]
(44) MDC[47..32]
MDA[63..48]
(42) MDA[63..48]
MDC[31..16]
(43) MDC[31..16]
MDA[47..32]
(42) MDA[47..32]
MDC[15..0]
(43) MDC[15..0]
MDA[31..16]
(41) MDA[31..16]
MEMORY INTERFACE B
(41) MDA[15..0]
1
Under GPU
close to ball : H17
N15P-GX_BGA908
@
2
0_0402_5%
A
GC6_FB_EN (14,36)
2
GC6_FB_EN_R 1
R426
DIS@
1
Near GPU
R518
10K_0402_5%
Compal Secret Data
Security Classification
Issued Date
2014/02/25
2015/02/25
Deciphered Date
Title
Compal Electronics, Inc.
N15P-GX (3/5) TMDS/LVDS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
LA-B111P
Date:
5
4
3
2
Tuesday, February 25, 2014
Sheet
1
38
of
59
2
FB_VDDQ_SENSE
FB_GND_SENSE
B
2
FB_CAL_PD_VDDQ
DIS@ 1
R433
40.2_0402_1%
J27
2
FB_CAL_PU_GND
DIS@ 1
R434
40.2_0402_1%
H27
2
FB_CAL_TERM_GND H25
DIS@ 1
R435
60.4_0402_1%
FB_CAL_PD_VDDQ
FB_CAL_PU_GND
FB_CAL_TERM_GND
2
DIS@ C655
DIS@ C665
DIS@ C674
2
1
22U_0805_6.3V6M
DIS@ C664
1
10U_0603_6.3V6M
2
10U_0603_6.3V6M
DIS@ C663
22U_0805_6.3V6M
DIS@ C654
22U_0805_6.3V6M
DIS@ C671
10U_0603_6.3V6M
DIS@ C670
10U_0603_6.3V6M
DIS@ C653
DIS@ C662
DIS@ C661
1U_0402_6.3V6K
DIS@ C673
1U_0402_6.3V6K
2
1
1
2
1
2
4.7U_0603_6.3V6K
DIS@ C683
2
4.7U_0603_6.3V6K
DIS@ C682
DIS@ C681
1U_0402_6.3V6K
2
1
C
@
RP40
IFPA_IOVDD
IFPB_IOVDD
IFPC_IOVDD
IFPD_PLLVDD
NC
IFPD_IOVDD
IFPEF_PLVDD
IFPEF_RSET
IFPE_IOVDD
IFPF_IOVDD
Under GPU
8
7
6
5
Near GPU
AG8
AG9
IFPC_PLLVDD
2
2
@
RP41
IFPD_IOVDD 1
IFPD_PLLVDD 2
IFPAB_PLLVDD3
IFPB_IOVDD 4
IFPA_IOVDD
IFPB_IOVDD
AF7
AF8
2
1
4.7U_0603_6.3V6K
IFPAB_PLLVDD
DIS@ C688
AH8
AJ8
1
1U_0402_6.3V6K
2.2K_8P4R_5%
1
DIS@ C687
IFPAB_PLLVDD
IFPAB_RSET
J8
K8
L8
M8
DIS@ C686
3V3_AON
3V3_AON
3V3_MAIN
3V3_MAIN
IFPEF_PLLVDD 1
IFPA_IOVDD 2
IFPC_IOVDD 3
IFPC_PLLVDD 4
AF6
IFPD_PLLVDD
AG6
IFPD_IOVDD
AB8
AD6
@
RP42
+3V3_AON
Near GPU
IFPE_IOVDD
IFPF_IOVDD
1
2
3
4
8
7
6
5
IFPEF_PLLVDD
AC7
AC8
Under GPU (one per pin)
IFPC_IOVDD
AG7
AN2
8
7
6
5
10K_8P4R_5%
IFPE_IOVDD
IFPF_IOVDD
1
2
1
2
Under GPU (one per pin)
Place near balls
N15P-GX_BGA908
1
2
1
2
1
2
4.7U_0603_6.3V6K
F2
1
2
D
2
1
2
B
+3VS_DGPU
Near GPU
1
10K_8P4R_5%
1
2
4.7U_0603_6.3V6K
F1
2
0.1U_0402_16V7K
DIS@ C689
+1.35VSG
1
FB_VDDQ_SENSE
10_0402_5%
2
FB_GND_SENSE
DIS@ 1
R432
10_0402_5%
1
C685
1
AG26
DIS@ C693
2
@
R431
2
1
+1.05VSG
+1.05VSG
IFPC_PLLVDD
IFPC_RSET
+1.35VSG
2
0.1U_0402_16V7K
@
PEX_PLLVDD
1
C684
1U_0402_6.3V6K
FBVDDQ_AON
FBVDDQ_AON
FBVDDQ_AON
FBVDDQ_AON
FBVDDQ_AON
FBVDDQ_AON
FBVDDQ_AON
FBVDDQ_AON
2
2
1
Near GPU
AG12
1U_0402_6.3V6K
B16
E16
H15
H16
V27
W27
W30
W33
@
PEX_SVDD_3V3
DIS@ C695
N14P_GB4-128
DG-6246_V04
2
1
2
1
+3V3_AON
DIS@ C705
2
1
2
1
AH12
0.1U_0402_16V7K
2
1
2
1
Near GPU
PEX_PLL_HVDD
DIS@ C691
1
22U_0805_6.3V6M
2
DIS@ C766
1
22U_0805_6.3V6M
DIS@ C764
2
DIS@ C795
1
10U_0603_6.3V6M
2
DIS@ C680
1
22U_0805_6.3V6M
2
DIS@ C679
1
22U_0805_6.3V6M
2
DIS@ C678
1
10U_0603_6.3V6M
2
DIS@ C677
+
V0.3
0.1U_0402_16V7K
V0.3
1
10U_0603_6.3V6M
DIS@ C790
C
SGA20331E10
330U 2V D2 LESR9M EEFSX H1.9
V0.3
DIS@ C694
Near GPU
2
Under GPU
AG13
AG15
AG16
AG18
AG25
AH15
AH18
AH26
AH27
AJ27
AK27
AL27
AM28
AN28
0.1U_0402_16V7K
2
PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
AG19
AG21
AG22
AG24
AH21
AH25
DIS@ C690
DIS@ C669
2
1
1U_0402_6.3V6K
DIS@ C668
2
1
1U_0402_6.3V6K
DIS@ C676
2
1
1U_0402_6.3V6K
DIS@ C667
2
1
1U_0402_6.3V6K
DIS@ C675
2
1
4.7U_0603_6.3V6K
DIS@ C666
1
4.7U_0603_6.3V6K
Under GPU
PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5
0.1U_0402_16V7K
2
FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_11
FBVDDQ_12
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
FBVDDQ_30
FBVDDQ_31
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37
FBVDDQ_38
FBVDDQ_43
POWER
DIS@ C660
2
1
0.1U_0402_16V7K
DIS@ C659
2
1
0.1U_0402_16V7K
DIS@ C672
2
1
0.1U_0402_16V7K
DIS@ C658
2
1
0.1U_0402_16V7K
DIS@ C657
1
4.7U_0603_6.3V6K
DIS@ C656
2
4.7U_0603_6.3V6K
1
AA27
AA30
AB27
AB33
AC27
AD27
AE27
AF27
AG27
B13
B19
E13
E19
H10
H11
H12
H13
H14
H18
H19
H20
H21
H22
H23
H24
H8
H9
L27
M27
N27
P27
R27
T27
T30
T33
Y27
1
4.7U_0603_6.3V6K
Part 5 of 7
9000mA
DIS@ C692
Under GPU
+1.35VSG
1
DIS@ C652
DIS@ C651
U30E
1U_0402_6.3V6K
D
+1.05VSG
Near GPU
1U_0402_6.3V6K
Under GPU
1
22U_0805_6.3V6M
3
4.7U_0603_6.3V6K
4
0.1U_0402_16V7K
5
A
A
Compal Secret Data
Security Classification
Issued Date
2014/02/25
2015/02/25
Deciphered Date
Title
Compal Electronics, Inc.
N15P-GX (4/5) POWER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
LA-B111P
Date:
5
4
3
2
Tuesday, February 25, 2014
Sheet
1
39
of
59
5
4
3
2
1
U30F
+VGA_CORE
U30G
AA12
AA14
AA16
AA19
AA21
AA23
AB13
AB15
AB17
AB18
AB20
AB22
AC12
AC14
AC16
AC19
AC21
AC23
M12
M14
M16
M19
M21
M23
N13
N15
N17
N18
N20
N22
P12
P14
P16
P19
P21
P23
R13
R15
R17
R18
R20
R22
T12
T14
T16
T19
T21
T23
U13
U15
U17
U18
U20
U22
V13
V15
C
VDD_0
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49
VDD_50
VDD_51
VDD_52
VDD_53
VDD_54
VDD_55
POWER
Part 7 of 7
D
VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71
XVDD_1
XVDD_2
XVDD_3
XVDD_4
XVDD_5
XVDD_6
XVDD_7
XVDD_8
XVDD_9
XVDD_10
XVDD_11
XVDD_12
XVDD_13
XVDD_14
XVDD_15
XVDD_16
XVDD_17
XVDD_18
XVDD_19
XVDD_20
XVDD_21
XVDD_22
NC
NC
NC
XVDD_23
XVDD_24
XVDD_25
XVDD_26
XVDD_27
NC
NC
NC
NC
NC
NC
NC
NC
V17
V18
V20
V22
W12
W14
W16
W19
W21
W23
Y13
Y15
Y17
Y18
Y20
Y22
U1
U2
U3
U4
U5
U6
U7
U8
V1
V2
V3
V4
V5
V6
V7
V8
W2
W3
W4
W5
W7
W8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
B
N15P-GX_BGA908
GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99
GND
Part 6 of 7
+VGA_CORE
A2
AA17
AA18
AA20
AA22
AB12
AB14
AB16
AB19
AB2
AB21
A33
AB23
AB28
AB30
AB32
AB5
AB7
AC13
AC15
AC17
AC18
AA13
AC20
AC22
AE2
AE28
AE30
AE32
AE33
AE5
AE7
AH10
AA15
AH13
AH16
AH19
AH2
AH22
AH24
AH28
AH29
AH30
AH32
AH33
AH5
AH7
AJ7
AK10
AK7
AL12
AL14
AL15
AL17
AL18
AL2
AL20
AL21
AL23
AL24
AL26
AL28
AL30
AL32
AL33
AL5
AM13
AM16
AM19
AM22
AM25
AN1
AN10
AN13
AN16
AN19
AN22
AN25
AN30
AN34
AN4
AN7
AP2
AP33
B1
B10
B22
B25
B28
B31
B34
B4
B7
C10
C13
C19
C22
C25
C28
C7
A
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192
GND_193
GND_194
GND_195
GND_196
GND_197
GND_198
GND_199
GND_OPT
GND_OPT
D2
D31
D33
E10
E22
E25
E5
E7
F28
F7
G10
G13
G16
G19
G2
G22
G25
G28
G3
G30
G32
G33
G5
G7
K2
K28
K30
K32
K33
K5
K7
M13
M15
M17
M18
M20
M22
N12
N14
N16
N19
N2
N21
N23
N28
N30
N32
N33
N5
N7
P13
P15
P17
P18
P20
P22
R12
R14
R16
R19
R21
R23
T13
T15
T17
T18
T2
T20
T22
AG11
T28
T32
T5
T7
U12
U14
U16
U19
U21
U23
V12
V14
V16
V19
V21
V23
W13
W15
W17
W18
W20
W22
W28
Y12
Y14
Y16
Y19
Y21
Y23
AH11
C16
W32
D
C
B
A
N15P-GX_BGA908
Compal Secret Data
Security Classification
Issued Date
2014/02/25
2015/02/25
Deciphered Date
Title
Compal Electronics, Inc.
N15P-GX (5/5) POWER/ GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
LA-B111P
Date:
5
4
3
2
Sheet
Tuesday, February 25, 2014
1
40
of
59
4
3
Memory Partition A - Lower 16 bits
2
DIS@
2N7002KDWH_SOT363-6
1
100K_0402_5%
R500
1
(36,43) VRAM_VREF_CTL
+1.35VSG
DIS@
2
G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14
B
CLKA0
1
(38) CLKA0
2
DIS@
R487
80.6_0402_1%
(38) CLKA0#
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CLKA0#
H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
170-BALL
SGRAM GDDR5
A
@
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
CMDA13
J2
WCK01#
WCK01
VREFD
VREFD
VREFC
RESET#
+1.35VSG
G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
170-BALL
SGRAM GDDR5
@
A7_A8
CMD7
A6_A11
CMD23
A6_A11
CMD8
ABI*
CMD24
ABI*
CMD9
A12_RFU
CMD25
A12_RFU
CMD10
A0_A10
CMD26
A0_A10
CMD11
A1_A9
CMD27
A1_A9
CMD12
RAS*
CMD28
RAS*
CMD13
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
WE*
CMD22
RST*
CMD29
RST*
CMD14
CK1*
CMD30
CK1*
CMD15
CAS*
CMD31
CAS*
CMD32
NO USED
CMD33
NO USED
CMD34
Debug0
CMD35
Debug1
C
B
+1.35VSG
1
2
1
2
1
2
V0.2
1
2
1
2
V0.2
1
2
@ C704
RESET#
WCK23#
WCK23
WCK23#
WCK23
CMD21
A7_A8
V0.2
1
2
V0.2
+1.35VSG
V0.2
1
2
1
2
1
2
1
2
1
2
1
2
2
1
A
V0.2
K4G41325FC-HC04_FBGA170~D
K4G41325FC-HC04_FBGA170~D
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2014/02/25
Deciphered Date
2015/02/25
Title
N15P-GX GDDR5 1/4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R & D Document Number
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
LA-B111P
Date:
5
4
3
2
D
0.1U_0402_16V7K
J2
FBA_VREFC
A10
U10
J14
WCK01#
WCK01
WE*
CMD6
@ C703
6
CMDA13
Q37A
FBA_WCK01# P5
FBA_WCK01 P4
CAS#
WE#
RAS#
CS#
A5_BA1
0.1U_0402_16V7K
VREFD
VREFD
VREFC
FBA_WCK23#D5
FBA_WCK23 D4
ABI#
RAS#
CS#
CAS#
WE#
A4_BA2
CMD20
CMD5
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
CMD19
A5_BA1
DIS@ C714
A10
U10
J14
WCK01#
WCK01
J4
G3
G12
L3
L12
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A2_BA0
A4_BA2
CMD4
32..63
0.1U_0402_16V7K
DIS@
2
1 FBA_VREFC
C761
820P_0402_25V8K
CMDA8
CMDA15
CMDA5
CMDA12
CMDA0
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
MF
SEN
ZQ
CMD18
CMD3
+1.35VSG
A2_BA0
0.1U_0402_16V7K
R494
1.33K_0402_1%
DIS@
SEN0
ZQ1
1 DIS@ 2
R441
121_0402_1%
J1
J10
J13
NC
NC
A3_BA3
CMD2
DIS@ C713
WCK23#
WCK23
2
2
R498
931_0402_1%
DIS@
R438
1K_0402_1% DIS@
CMD17
0.1U_0402_16V7K
WCK01#
WCK01
WCK23#
WCK23
A5
U5
A3_BA3
@ C701
2
(38) FBA_WCK23#
(38) FBA_WCK23
1
1
FBA_VREFC (42)
P5
P4
BA1/A5
BA2/A4
A11/A6
A8/A7
CS*
CMD1
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
CMD16
DIS@ C702
D5
D4
(38) FBA_WCK01#
(38) FBA_WCK01
BA3/A3
BA0/A2
A9/A1
A10/A0
A10/A0
A9/A1
BA3/A3
BA0/A2
Mode H
Address
CS*
0.1U_0402_16V7K
CAS#
WE#
RAS#
CS#
A8/A7
A11/A6
BA1/A5
BA2/A4
0..31
CMD0
@ C712
ABI#
RAS#
CS#
CAS#
WE#
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
H10
H11
H5
H4
A12/A13
Mode H
Address
0.1U_0402_16V7K
R492
549_0402_1%
DIS@
+1.35VSG
K4
K5
K10
K11
CMDA4
CMDA3
CMDA7
CMDA6
+1.35VSG
MF
SEN
ZQ
J5
CMDA10
CMDA11
CMDA1
CMDA2
CK
CK#
CKE#
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
DIS@ C700
J4
G3
G12
L3
L12
CMDA9
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
J12
J11
J3
DBI3#
DBI2#
DBI1#
DBI0#
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
0.1U_0402_16V7K
J1
J10
J13
1
+1.35VSG
MF0
SEN0
ZQ0
CLKA0
CLKA0#
CMDA14
DBI0#
DBI1#
DBI2#
DBI3#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
1U_0402_6.3V6K
2 1K_0402_1%
2 1K_0402_1%
2 121_0402_1%
NC
NC
MF=0
DIS@ C711
C
DIS@ 1
DIS@ 1
DIS@ 1
CMDA8
CMDA12
CMDA0
CMDA15
CMDA5
R436
R437
R440
BA1/A5
BA2/A4
A11/A6
A8/A7
DQMA1
D2
D13
P13
P2
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
0.1U_0402_16V7K
A5
U5
BA3/A3
BA0/A2
A9/A1
A10/A0
MF=1
EDC3
EDC2
EDC1
EDC0
@ C698
MDA[63..0]
(38,42) MDA[63..0]
H10
H11
H5
H4
A10/A0
A9/A1
BA3/A3
BA0/A2
DQMA3
EDC0
EDC1
EDC2
EDC3
DIS@ C699
CMDA1
CMDA2
CMDA11
CMDA10
DQSA[7..0]
(38,42) DQSA[7..0]
A8/A7
A11/A6
BA1/A5
BA2/A4
DQSA1
C2
C13
R13
R2
1U_0402_6.3V6K
(38,42) CMDA[31..0]
A12/A13
DQSA3
DIS@ C710
CMDA[31..0]
CK
CK#
CKE#
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
0.1U_0402_16V7K
K4
K5
K10
K11
DBI3#
DBI2#
DBI1#
DBI0#
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
2
1
DIS@ C697
10U_0805_25V6K
CMDA6
CMDA7
CMDA4
CMDA3
DQMA[7..0]
J5
DBI0#
DBI1#
DBI2#
DBI3#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DIS@ C709
CMDA9
(38,42) DQMA[7..0]
J12
J11
J3
EDC3
EDC2
EDC1
EDC0
MF=1
MF=0
1U_0402_6.3V6K
CLKA0
CLKA0#
CMDA14
EDC0
EDC1
EDC2
EDC3
MF=1
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
2
1
DIS@ C696
10U_0805_25V6K
DQMA2
D2
D13
P13
P2
MF=1
C708
DQMA0
MF=0
MF=0
C2
C13
R13
R2
@
128Mx16 GDDR5 *8== & gt; 2GB
256Mx16 GDDR5 *8== & gt; 4GB
U31
1U_0402_6.3V6K
D
DQSA2
1
U32
2
VRAM DDR5 chips
DQSA0
2
MIRROR
NORMAL
1
5
Tuesday, February 25, 2014
1
Sheet
41
of
59
4
3
2
NORMAL
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
P5
P4
(38) FBA_WCK67#
(38) FBA_WCK67
FBA_VREFC
CMDA29
(41) FBA_VREFC
J2
WCK23#
WCK23
WCK23#
WCK23
WCK01#
WCK01
VREFD
VREFD
VREFC
RESET#
CLKA1
1
(38) CLKA1
+1.35VSG
2
DIS@
R455
80.6_0402_1%
B
A10
U10
J14
WCK01#
WCK01
(38) CLKA1#
G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14
CLKA1#
H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
170-BALL
SGRAM GDDR5
A
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
FBA_WCK67#D5
FBA_WCK67 D4
FBA_WCK45# P5
FBA_WCK45 P4
DIS@
2
1 FBA_VREFC
C765
820P_0402_25V8K
CMDA29
A10
U10
J14
J2
WCK23#
WCK23
WCK23#
WCK23
WCK01#
WCK01
VREFD
VREFD
VREFC
RESET#
+1.35VSG
G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
170-BALL
SGRAM GDDR5
@
@
WCK01#
WCK01
CMD23
A6_A11
ABI*
CMD24
ABI*
CMD9
A12_RFU
CMD25
A12_RFU
CMD10
A0_A10
CMD26
A0_A10
CMD11
A1_A9
CMD27
A1_A9
CMD12
RAS*
CMD28
RAS*
CMD13
RST*
CMD29
RST*
CMD14
CK1*
CMD30
CK1*
CMD15
CAS*
CMD31
CAS*
CMD32
NO USED
CMD33
NO USED
CMD34
Debug0
CMD35
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
A6_A11
CMD8
Debug1
C
B
+1.35VSG
V0.2
1
2
1
2
1
2
1
1
2
1
2
1
2
DIS@ C718
2 DIS@
2 DIS@
2 DIS@
2 DIS@
D5
D4
(38) FBA_WCK45#
(38) FBA_WCK45
CAS#
WE#
RAS#
CS#
A7_A8
D
1
2
0.1U_0402_16V7K
R510 1
R514 1
R515 1
R511 1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
ABI#
RAS#
CS#
CAS#
WE#
CMD22
CMD7
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
WE*
A7_A8
DIS@ C728
CMDA13
CMDA29
CMDC13
CMDC29
DIS@
DIS@
DIS@
DIS@
J4
G3
G12
L3
L12
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A5_BA1
CMD21
0.1U_0402_16V7K
(38,41,42)
(38,42)
(38,43)
(38,44)
2
2
2
2
CAS#
WE#
RAS#
CS#
1 R451
2
121_0402_1%
DIS@
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
MF
SEN
ZQ
CMD20
WE*
CMD6
+1.35VSG
A5_BA1
CMD5
V0.2
+1.35VSG
1
2
1
2
1
2
1
2
2
1
2
DIS@ C721
R508
R512
R509
R513
ABI#
RAS#
CS#
CAS#
WE#
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
SEN1
ZQ3
CMD4
32..63
2
1
0.1U_0402_16V7K
CMDA14
CMDA30
CMDC14
CMDC30
MF
SEN
ZQ
J1
J10
J13
CMDA24
CMDA31
CMDA21
CMDA28
CMDA16
+1.35VSG
NC
NC
A4_BA2
DIS@ C715
+1.35VSG
1
1
1
1
(38,41,42)
(38,42)
(38,43)
(38,44)
J4
G3
G12
L3
L12
DIS@
A2_BA0
CMD19
0.1U_0402_16V7K
C
J1
J10
J13
A5
U5
R447
1K_0402_1%
CMD18
A4_BA2
DIS@ C723
MF1
SEN1
ZQ2
BA1/A5
BA2/A4
A11/A6
A8/A7
A2_BA0
CMD3
0.1U_0402_16V7K
2 1K_0402_1%
2 1K_0402_1%
2 121_0402_1%
NC
NC
+1.35VSG
BA3/A3
BA0/A2
A9/A1
A10/A0
A3_BA3
CMD2
DIS@ C720
DIS@ 1
DIS@ 1
DIS@ 1
CMDA24
CMDA28
CMDA16
CMDA31
CMDA21
R446
R449
R450
BA1/A5
BA2/A4
A11/A6
A8/A7
CMD17
0.1U_0402_16V7K
A5
U5
BA3/A3
BA0/A2
A9/A1
A10/A0
H10
H11
H5
H4
A10/A0
A9/A1
BA3/A3
BA0/A2
A3_BA3
0.1U_0402_16V7K
(38,41) CMDA[31..0]
CMDA20
CMDA19
CMDA23
CMDA22
A8/A7
A11/A6
BA1/A5
BA2/A4
CS*
CMD1
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
CMD16
DIS@ C724
H10
H11
H5
H4
K4
K5
K10
K11
A12/A13
Mode H
Address
CS*
0.1U_0402_16V7K
CMDA[31..0]
CMDA26
CMDA27
CMDA17
CMDA18
CK
CK#
CKE#
0..31
CMD0
@ C717
MDA[63..0]
(38,41) MDA[63..0]
A10/A0
A9/A1
BA3/A3
BA0/A2
J5
Mode H
Address
1U_0402_6.3V6K
(38,41) DQMA[7..0]
A8/A7
A11/A6
BA1/A5
BA2/A4
CMDA25
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
J12
J11
J3
DBI3#
DBI2#
DBI1#
DBI0#
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
DIS@ C722
K4
K5
K10
K11
CMDA17
CMDA18
CMDA27
CMDA26
DQMA[7..0]
A12/A13
CLKA1
CLKA1#
CMDA30
DBI0#
DBI1#
DBI2#
DBI3#
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
0.1U_0402_16V7K
CMDA22
CMDA23
CMDA20
CMDA19
DQSA[7..0]
(38,41) DQSA[7..0]
CK
CK#
CKE#
D2
D13
P13
P2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
@ C707
J5
DQMA5
EDC3
EDC2
EDC1
EDC0
MF=0
DIS@ C706
CMDA25
DQMA7
EDC0
EDC1
EDC2
EDC3
MF=1
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
1U_0402_6.3V6K
J12
J11
J3
DBI3#
DBI2#
DBI1#
DBI0#
MF=1
DIS@ C719
CLKA1
CLKA1#
CMDA30
DBI0#
DBI1#
DBI2#
DBI3#
DQSA5
C2
C13
R13
R2
0.1U_0402_16V7K
D2
D13
P13
P2
DQSA7
2
1
@ C727
10U_0805_25V6K
DQMA6
MF=0
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
1U_0402_6.3V6K
DQMA4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
DIS@ C725
128Mx16 GDDR5 *8== & gt; 2GB
256Mx16 GDDR5 *8== & gt; 4GB
EDC3
EDC2
EDC1
EDC0
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
MF=0
2
1
DIS@ C726
10U_0805_25V6K
D
EDC0
EDC1
EDC2
EDC3
MF=1
2
VRAM DDR5 chips
DQSA6
C2
C13
R13
R2
MF=1
1
DQSA4
U34
MF=0
@ C716
U33
Memory Partition A - Upper 16 bits
1
MIRROR
1U_0402_6.3V6K
5
A
V0.2
V0.2
K4G41325FC-HC04_FBGA170~D
K4G41325FC-HC04_FBGA170~D
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2014/02/25
Deciphered Date
2015/02/25
Title
N15P-GX GDDR5 2/4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R & D Document Number
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
LA-B111P
Date:
5
4
3
2
Tuesday, February 25, 2014
1
Sheet
42
of
59
4
3
CMDC13
J2
RESET#
3
Q37B
2N7002KDWH_SOT363-6
5
DIS@
+1.35VSG
4
(36,41) VRAM_VREF_CTL
G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14
B
CLKC0
1
(38) CLKC0
2
DIS@
R465
80.6_0402_1%
(38) CLKC0#
H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14
CLKC0#
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
170-BALL
SGRAM GDDR5
A
@
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
FBB_WCK23#D5
FBB_WCK23 D4
FBB_WCK01# P5
FBB_WCK01 P4
FBB_VREFC
CMDC13
A10
U10
J14
J2
ABI#
RAS#
CS#
CAS#
WE#
CAS#
WE#
RAS#
CS#
WCK01#
WCK01
WCK23#
WCK23
WCK23#
WCK23
WCK01#
WCK01
VREFD
VREFD
VREFC
RESET#
+1.35VSG
G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
170-BALL
SGRAM GDDR5
@
Issued Date
ABI*
CMD25
A12_RFU
A0_A10
CMD26
A0_A10
CMD11
A1_A9
CMD27
A1_A9
CMD12
RAS*
CMD28
RAS*
CMD13
RST*
CMD29
RST*
CMD14
CK1*
CMD30
CK1*
CMD15
CAS*
CMD31
CAS*
CMD32
NO USED
CMD33
NO USED
CMD34
Debug0
CMD35
Debug1
C
+1.35VSG
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
1
2
1
2
1
2
1
2
1
2
1
2
1
2
B
V0.2
+1.35VSG
1
2
1
2
1
2
1
2
1
2
1
2
2
1
V0.2
V0.2
V0.2
A
K4G41325FC-HC04_FBGA170~D
Compal Electronics, Inc.
Compal Secret Data
Security Classification
K4G41325FC-HC04_FBGA170~D
A6_A11
CMD24
A12_RFU
D
0.1U_0402_16V7K
DIS@
J4
G3
G12
L3
L12
CMD23
ABI*
CMD9
@ C744
VREFD
VREFD
VREFC
CMDC8
CMDC15
CMDC5
CMDC12
CMDC0
A6_A11
CMD8
DIS@ C734
WCK01#
WCK01
R460
121_0402_1%
CMD7
0.1U_0402_16V7K
WCK23#
WCK23
DIS@
A7_A8
DIS@ C737
A10
U10
J14
WCK23#
WCK23
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
CMD22
CMD10
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
WE*
A7_A8
32..63
0.1U_0402_16V7K
R495
1.33K_0402_1%
DIS@
2
2
R499
931_0402_1%
DIS@
1
FBB_VREFC
820P_0402_25V8K
WCK01#
WCK01
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A5_BA1
CMD21
DIS@ C731
1
1
C762
2
ZQ5
MF
SEN
ZQ
CMD20
WE*
CMD6
+1.35VSG
A5_BA1
CMD5
0.1U_0402_16V7K
2
FBB_VREFC (44)
SEN2
J1
J10
J13
NC
NC
CMD4
DIS@ C739
P5
P4
(38) FBB_WCK23#
(38) FBB_WCK23
DIS@
A4_BA2
0.1U_0402_16V7K
D5
D4
(38) FBB_WCK01#
(38) FBB_WCK01
R493
549_0402_1%
DIS@
CAS#
WE#
RAS#
CS#
A5
U5
A2_BA0
CMD19
DIS@ C736
1
+1.35VSG
ABI#
RAS#
CS#
CAS#
WE#
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
BA1/A5
BA2/A4
A11/A6
A8/A7
CMD18
A4_BA2
0.1U_0402_16V7K
J4
G3
G12
L3
L12
R458
1K_0402_1%
+1.35VSG
MF
SEN
ZQ
BA3/A3
BA0/A2
A9/A1
A10/A0
A3_BA3
A2_BA0
CMD3
@ C733
CMDC8
CMDC12
CMDC0
CMDC15
CMDC5
C
J1
J10
J13
A10/A0
A9/A1
BA3/A3
BA0/A2
CMD17
0.1U_0402_16V7K
MF2
SEN2
ZQ4
H10
H11
H5
H4
A8/A7
A11/A6
BA1/A5
BA2/A4
A3_BA3
CMD2
MDC8
MDC9
MDC10
MDC11
MDC12
MDC13
MDC14
MDC15
CS*
CMD1
DIS@ C740
2 1K_0402_1%
2 1K_0402_1%
2 121_0402_1%
CMDC4
CMDC3
CMDC7
CMDC6
+1.35VSG
K4
K5
K10
K11
A12/A13
CMD16
0.1U_0402_16V7K
DIS@ 1
DIS@ 1
DIS@ 1
NC
NC
CMDC10
CMDC11
CMDC1
CMDC2
MDC16
MDC17
MDC18
MDC19
MDC20
MDC21
MDC22
MDC23
CK
CK#
CKE#
Mode H
Address
CS*
0.1U_0402_16V7K
R456
R457
R462
BA1/A5
BA2/A4
A11/A6
A8/A7
J5
0..31
CMD0
DIS@ C729
A5
U5
BA3/A3
BA0/A2
A9/A1
A10/A0
CMDC9
Mode H
Address
1U_0402_6.3V6K
H10
H11
H5
H4
A10/A0
A9/A1
BA3/A3
BA0/A2
J12
J11
J3
DBI3#
DBI2#
DBI1#
DBI0#
MDC24
MDC25
MDC26
MDC27
MDC28
MDC29
MDC30
MDC31
@ C738
CMDC1
CMDC2
CMDC11
CMDC10
A8/A7
A11/A6
BA1/A5
BA2/A4
CLKC0
CLKC0#
CMDC14
DBI0#
DBI1#
DBI2#
DBI3#
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
DIS@ C730
K4
K5
K10
K11
D2
D13
P13
P2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
1U_0402_6.3V6K
CMDC6
CMDC7
CMDC4
CMDC3
A12/A13
DQMC1
EDC3
EDC2
EDC1
EDC0
DIS@ C735
J5
DQMC3
EDC0
EDC1
EDC2
EDC3
2
1
DIS@ C743
10U_0805_25V6K
CMDC9
CK
CK#
CKE#
DQSC1
1U_0402_6.3V6K
J12
J11
J3
MDC[63..0]
(38,44) MDC[63..0]
CLKC0
CLKC0#
CMDC14
MDC0
MDC1
MDC2
MDC3
MDC4
MDC5
MDC6
MDC7
DIS@ C741
DQSC[7..0]
DBI3#
DBI2#
DBI1#
DBI0#
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
MF=0
2
1
DIS@ C742
10U_0805_25V6K
CMDC[31..0]
(38,44) DQSC[7..0]
DBI0#
DBI1#
DBI2#
DBI3#
MF=1
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
2
DQMC[7..0]
D2
D13
P13
P2
EDC3
EDC2
EDC1
EDC0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
1
DQMC0
EDC0
EDC1
EDC2
EDC3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
C2
C13
R13
R2
2
DQSC2
C2
C13
R13
R2
MF=1
MF=0
1
DQSC0
DQMC2
(38,44) DQMC[7..0]
MF=1
0.1U_0402_16V7K
MF=0
MF=1
DQSC3
128Mx16 GDDR5 *8== & gt; 2GB
256Mx16 GDDR5 *8== & gt; 4GB
(38,42,44) CMDC[31..0]
U35
NORMAL
U36
MF=0
VRAM DDR5 chips
1
@ C732
Memory Partition B - Lower 16 bits
D
2
MIRROR
1U_0402_6.3V6K
5
2014/02/25
Deciphered Date
2015/02/25
Title
N15P-GX GDDR5 3/4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R & D Document Number
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
LA-B111P
Date:
5
4
3
2
Tuesday, February 25, 2014
1
Sheet
43
of
59
4
3
U37
K4
K5
K10
K11
CMDC17
CMDC18
CMDC27
CMDC26
H10
H11
H5
H4
A5
U5
R466
R467
R472
DIS@ 1
DIS@ 1
DIS@ 1
2 1K_0402_1%
2 1K_0402_1%
2 121_0402_1%
MF3
SEN3
ZQ6
CMDC24
CMDC28
CMDC16
CMDC31
CMDC21
C
J1
J10
J13
J4
G3
G12
L3
L12
D5
D4
(38) FBB_WCK45#
(38) FBB_WCK45
P5
P4
(38) FBB_WCK67#
(38) FBB_WCK67
FBB_VREFC
A10
U10
J14
CMDC29
(43) FBB_VREFC
J2
A8/A7
A11/A6
BA1/A5
BA2/A4
A10/A0
A9/A1
BA3/A3
BA0/A2
BA3/A3
BA0/A2
A9/A1
A10/A0
BA1/A5
BA2/A4
A11/A6
A8/A7
NC
NC
ABI#
RAS#
CS#
CAS#
WE#
CAS#
WE#
RAS#
CS#
WCK01#
WCK01
WCK23#
WCK23
WCK23#
WCK23
WCK01#
WCK01
VREFD
VREFD
VREFC
RESET#
CLKC1
1
(38) CLKC1
2
DIS@
R475
80.6_0402_1%
B
(38) CLKC1#
+1.35VSG
G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14
CLKC1#
H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
170-BALL
SGRAM GDDR5
A
@
R468
1K_0402_1%
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
H10
H11
H5
H4
A5
U5
DIS@
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
SEN3
ZQ7
J1
J10
J13
CMDC24
CMDC31
CMDC21
CMDC28
CMDC16
1 R470
2
DIS@
121_0402_1%
+1.35VSG
MF
SEN
ZQ
CMDC20
CMDC19
CMDC23
CMDC22
+1.35VSG
K4
K5
K10
K11
A8/A7
A11/A6
BA1/A5
BA2/A4
BA3/A3
BA0/A2
A9/A1
A10/A0
A10/A0
A9/A1
BA3/A3
BA0/A2
BA1/A5
BA2/A4
A11/A6
A8/A7
J4
G3
G12
L3
L12
FBB_WCK67#D5
FBB_WCK67 D4
FBB_WCK45# P5
FBB_WCK45 P4
A10
U10
J14
C763
2
1 FBB_VREFC
820P_0402_25V8K
NC
NC
MF
SEN
ZQ
ABI#
RAS#
CS#
CAS#
WE#
CAS#
WE#
RAS#
CS#
WCK01#
WCK01
WCK23#
WCK23
WCK23#
WCK23
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
WCK01#
WCK01
VREFD
VREFD
VREFC
DIS@
CMDC29
J2
RESET#
+1.35VSG
G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
170-BALL
SGRAM GDDR5
@
K4G41325FC-HC04_FBGA170~D
A3_BA3
A2_BA0
CMD18
A2_BA0
A4_BA2
CMD19
A4_BA2
CMD4
A5_BA1
CMD20
A5_BA1
CMD5
WE*
CMD21
WE*
CMD6
A7_A8
CMD22
A7_A8
CMD7
A6_A11
CMD23
A6_A11
CMD8
ABI*
CMD24
ABI*
CMD9
A12_RFU
CMD25
A12_RFU
CMD10
A0_A10
CMD26
A0_A10
CMD11
A1_A9
CMD27
A1_A9
CMD12
RAS*
CMD28
RAS*
CMD13
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
CMD17
CMD3
RST*
CMD29
RST*
CMD14
CK1*
CMD30
CK1*
CMD15
CAS*
CMD31
CAS*
CMD32
NO USED
CMD33
NO USED
CMD34
Debug0
CMD35
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
A3_BA3
CMD2
+1.35VSG
CS*
CMD1
MDC40
MDC41
MDC42
MDC43
MDC44
MDC45
MDC46
MDC47
CMD16
Debug1
32..63
D
C
B
+1.35VSG
1
2
1
2
1
2
1
2
1
2
1
2
1
2
DIS@
C750
0.1U_0402_16V7K
CMDC22
CMDC23
CMDC20
CMDC19
CMDC26
CMDC27
CMDC17
CMDC18
MDC48
MDC49
MDC50
MDC51
MDC52
MDC53
MDC54
MDC55
A12/A13
Mode H
Address
CS*
DIS@
C760
0.1U_0402_16V7K
CMDC[31..0]
(38,42,43) CMDC[31..0]
A12/A13
CK
CK#
CKE#
0..31
CMD0
+1.35VSG
1
2
1
2
1
2
1
2
1
2
1
2
2
1
DIS@ C753
0.1U_0402_16V7K
J5
J5
Mode H
Address
DIS@
C747
0.1U_0402_16V7K
CMDC25
CMDC25
MDC56
MDC57
MDC58
MDC59
MDC60
MDC61
MDC62
MDC63
DIS@ C755
0.1U_0402_16V7K
MDC[63..0]
(38,43) MDC[63..0]
CK
CK#
CKE#
J12
J11
J3
DBI3#
DBI2#
DBI1#
DBI0#
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
DIS@
C752
0.1U_0402_16V7K
J12
J11
J3
CLKC1
CLKC1#
CMDC30
DBI0#
DBI1#
DBI2#
DBI3#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DIS@
C756
0.1U_0402_16V7K
CLKC1
CLKC1#
CMDC30
DQMC[7..0]
DBI3#
DBI2#
DBI1#
DBI0#
DQMC5
EDC3
EDC2
EDC1
EDC0
DIS@ C749
0.1U_0402_16V7K
DQSC[7..0]
(38,43) DQSC[7..0]
(38,43) DQMC[7..0]
DBI0#
DBI1#
DBI2#
DBI3#
D2
D13
P13
P2
DQMC7
EDC0
EDC1
EDC2
EDC3
DIS@ C745
1U_0402_6.3V6K
DQMC6
D2
D13
P13
P2
DQSC5
DIS@ C754
0.1U_0402_16V7K
DQMC4
EDC3
EDC2
EDC1
EDC0
MDC32
MDC33
MDC34
MDC35
MDC36
MDC37
MDC38
MDC39
MF=0
DIS@ C746
1U_0402_6.3V6K
128Mx16 GDDR5 *8== & gt; 2GB
256Mx16 GDDR5 *8== & gt; 4GB
EDC0
EDC1
EDC2
EDC3
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
2
D
DQSC6
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
1
VRAM DDR5 chips
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
MF=1
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DIS@ C751
0.1U_0402_16V7K
C2
C13
R13
R2
DQSC7
C2
C13
R13
R2
MF=1
MF=0
DIS@ C757
1U_0402_6.3V6K
MF=1
1
MF=0
MF=1
C758
10U_0805_25V6K
2
1
DIS@
C759
10U_0805_25V6K
NORMAL
U38
MF=0
DQSC4
1
2
DIS@
Memory Partition B - Upper 16 bits
2
MIRROR
DIS@ C748
1U_0402_6.3V6K
5
A
K4G41325FC-HC04_FBGA170~D
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2014/02/25
Deciphered Date
2015/02/25
Title
N15P-GX GDDR5 4/4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R & D Document Number
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
LA-B111P
Date:
5
4
3
2
Tuesday, February 25, 2014
1
Sheet
44
of
59
5
4
3
+3VS to +3V3_AON
2
1
+3VS to +3VS_DGPU
Vgs=-4.5V,Id=3A,Rds & lt; 97mohm
Vgs=-4.5V,Id=3A,Rds & lt; 97mohm
+3VS_DGPU
1
2
2
0.01U_0402_16V7K
2
D
V0.2A
2 3V3_MAIN_EN#
G
Q35
2N7002H_SOT23-3
SW@
S
1
S
2
G
DGPU_PWR_EN
V0.3
2
2
R505
1
2
SW@ 10K_0402_5%
3V3_MAIN_EN#
D
C784
0.01U_0402_16V7K
V0.2A
V0.2A
D
3
10K_0402_5%
DIS@
(14,31) DGPU_PWR_EN
1
@
@
R479
1
1
2
C783
0.1U_0402_16V7K
1
2
R504
220_0402_5%
1
2
2
3 1
C779
DIS@
0.1U_0402_16V7K
DGPU_PWR_EN#
4
1
G
G
@
1
AO3413_SOT23
D
3
SW@
S
6 1
+3VS
Q36
G
1
C778
R478
20K_0402_5%
DIS@
Q31B
2N7002KDWH_SOT363-6
DIS@
DGPU_PWR_EN# 5
2N7002KDWH_SOT363-6
+3VS_DGPU
1
AO3413_SOT23
D
Q31A
2
3
Q25
SW@
DIS@
1
+3V3_AON
DIS@
+3VS
R477
470_0805_5%
DIS@
S
R476
220_0402_5%
DIS@
D
+3VS
2
2
+VGA_CORE
3
+3V3_AON
2N7002K_SOT23-3
Q34
DIS@
+1.35V to +1.35VSG
2
5
2N7002KDWH_SOT363-6
Q28B
2N7002KDWH_SOT363-6
DIS@
5
2
R521
10K_0402_5%
DIS@
1
+1.05VS_DGPU_PGOOD
D
2N7002K_SOT23-3
Q38
DIS@
2
G
C
S
Q42
1
MMST3904-7-F_SOT323-3
3
2
B
DIS@ E
1
2
1
Q28A
2 3V3_MAIN_EN#
2N7002KDWH_SOT363-6
DIS@
C
R523
10K_0402_5%
DIS@
1
1
1
R525
10K_0402_5%
DIS@
3
1
2
2
2
2
R482
470_0805_5%
DIS@
1
2
V0.2A
C605
DIS@
R530 200K_0402_5%
2
@
B+
1 R491
2
+12VS
DIS@ 200K_0402_5%
R490
820K_0402_5%
DIS@
2
C791
DIS@
1 C600
DIS@
4.7U_0603_6.3V6K
1
0.01U_0402_25V7K
VRAM_1.05VS_GATE
1
6
1
6
1.35V_PWR_EN
1
2
3
4
AO4354_SO8
C789
2 0.1U_0402_16V7K
DIS@
Q30B
@
+5VALW
1
2
100K_0402_5%
R486
DIS@
C788
2 0.1U_0402_16V7K
V0.2A
DIS@
Q30A
4
(36) 1.35V_PWR_EN
S
S
S
G
0.01U_0402_25V7K
S
DIS@
D
D
D
D
8
7
6
5
2N7002K_SOT23-3
Q39
DIS@
3
Q26
D
Q41
1
MMST3904-7-F_SOT323-3
@
+3V3_AON
+1.05VSG
4
1
3
1
C
+1.05VS
+1.35VSG_PGOOD
2
G
+5VALW
1
2
100K_0402_5%
R485
DIS@
+3V3_AON
R524
10K_0402_5%
@
2
1
Q29B
2N7002KDWH_SOT363-6
DIS@
2
B
E
DIS@
3
2 1.35V_PWR_EN# 5
2N7002KDWH_SOT363-6
DIS@
R522
10K_0402_5%
DIS@
1
2
1
V0.3
3
+12VS
4
DIS@
B+
R526
10K_0402_5%
DIS@
Q29A
3
2
R484
820K_0402_5%
R480
470_0402_5%
DIS@
1
C781
DIS@
6
1
1
2
2
VRAM_1.35VS_GATE
0.01U_0402_25V7K
C780
DIS@
4.7U_0603_6.3V6K
1
R529 @
1
2
180K_0402_5%
R483 DIS@
1
2
180K_0402_5%
2
+3V3_AON
V0.3
4
C
+1.05VS to +1.05VSG
+3V3_AON
+1.35VSG
Q27
DIS@
AON6504_POWERDFN56-8-5
1
2
5
3
1
+1.35V
3V3_MAIN_EN
2
2N7002KDWH_SOT363-6
1
(36,54) 3V3_MAIN_EN
+3V3_AON
+3V3_AON
B
B
3
@
DIS@
Q44B
C786
2 0.1U_0402_16V7K
DIS@
DIS@
1
+1.05VS_DGPU_PGOOD
RB751V-40_SOD323-2
4
6
2N7002KDWH_SOT363-6
DIS@
2N7002KDWH_SOT363-6
2
(36,37) GPU_OVERT#
1
Q44A
1
@
2
D32
2
2
0_0402_5%
GPU_ALL_PGOOD
GPU_ALL_PGOOD (14)
DIS@
1
DIS@
2
2
0_0402_5%
G
1
V0.2
D
DIS@
3
C785
2 0.1U_0402_16V7K
1
R520
(36) DGPU_PEX_RST#
+1.35VSG_PGOOD R519 1
R528
10K_0402_5%
DIS@
D33
1
RB751V-40_SOD323-2
(18,36,54) DGPU_PWROK
5
1
GPU_OVERT
2
1
DIS@
R527
10K_0402_5%
1
2
H_THRMTRIP# (18,5)
S
Q40
2N7002K_SOT23-3
@
1
3V3_MAIN_EN 2 R532
1K_0402_5%
+1.05VS_DGPU_PGOOD
1
@
C787
2 0.1U_0402_16V7K
@
@
2
1
1.35V_PWR_EN R533
10K_0402_5%
+1.35VSG_PGOOD
1
C793
0.1U_0402_16V7K
@
2
C792
0.1U_0402_16V7K
2
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2014/02/25
2015/02/25
Deciphered Date
Title
N15P-GX DC-DC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
LA-B111P
Date:
5
4
3
2
Sheet
Tuesday, February 25, 2014
1
45
of
59
4
EMI@ PL101
FBMA-L11-201209-121LMA50T_0805
1
2
PR104
2
100K_0402_5%
5
1
2
PC103 EMI@
100P_0402_50V8J
1
1
2
2
PR103
100K_0402_5%
1
2
1
VIN
PQ101B
2N7002KDW-2N_SOT363-6
4
3
2
1
+3VALW
2
PQ101A
2N7002KDW-2N_SOT363-6
0_0402_1%
1
2
6
1
PR102
750_0402_1%
PC106
680P_0603_50V7K
1
@ PR101
2
1
2
135W adaptor
PC105
0.1U_0402_16V7K
D
1
SP040006C00
ACES_50299-00501-003_5P
CONN@
SP02000YD00
2
1
VIN
SM01000BY00
1
2
EMI@ PL102
FBMA-L11-201209-121LMA50T_0805
100P_0402_50V8J
PF101
12A_24VDC_429007.WRML
1
2 APDIN1
PC102 EMI@
APDIN
2
1
2
3
4
5
1
2
3
4
5
PC101 EMI@
1000P_0402_50V7K
JDCIN1
3
PC104 EMI@
1000P_0402_50V7K
5
D
ADP_ID (31)
A/D
ADP_ID_CLOSE (31)
+CHGRTC
C
PR105
1K_0603_5%
1
2
+RTCVCC
PD101
S SCH DIO BAS40CW SOT-323
2
1
3
C
+3VLP
+CHGRTC_R
PR106
1K_0603_5%
1
2
JRTC1 CONN@
1
2 1
3 2
4 GND
GND
ACES_50271-0020N-001
RTC Battery
GC02001DR00
BATT CR2032 3V 210MAH MB 5 W/C
30MM
B
B
A
A
Compal Secret Data
Security Classification
Issued Date
2014/02/25
2015/02/25
Deciphered Date
Title
Compal Electronics, Inc.
PWR DCIN / RTC Battery
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
BE_BDW
Date:
5
4
3
2
Tuesday, February 25, 2014
Sheet
1
46
of
59
5
PF201
1
2S2P / 54W
PC201
1000P_0402_50V7K
1
1
EMI@
2
1
1
BATT+
PC202
EMI@
2
SUYIN_125017GA007G101ZL
LTCX005GY00
2
15A_24V_F1206HB10V024TM
EMI@
SP040006F00
PC207
2
1
PR211
100_0402_1%
EC_SMCA
EC_SMDA
1000P_0402_50V7K
1
2
3
4
5
6
7
8
9
2
1
PR201
100_0402_1%
D
1
2
3
4
5
6
7
GND
GND
2
CONN@
JBATT1
EMI@ PL202
SM01000AZ00_2P
1
2
PL201
SM01000AZ00_2P
1
2
EMI@
PC208 EMI@
1
VMB
2
D
0.01U_0402_25V7K
2
VMB2
3
0.01U_0402_25V7K
V0.2
4
+EC_VCCA
VCIN1_BATT_TEMP (31)
@
2
1
PR215
16.5K_0402_1%
(31) VCIN0_PH1
1
2
A/D
1
2
PR214
10K_0402_5%
2
1
+3VLP
1
VCOUT1_PROCHOT#
EC_SMB_DA1 (31,48)
PR217
30K_0402_1%
EC_SMB_CK1 (31,48)
1
2
PR212
6.49K_0402_1%
PR216
10K_0402_1%
(31,48) ADP_I
(31) VCIN1_ADP_PROCHOT
2
PH201
100K_0402_1%_TSM0B104F4251RZ
2
PR221
110K_0402_1%
PWR_LEVEL_R (36)
1
(31) VCOUT1_PROCHOT#
PR228
0_0402_5%
PR230
0_0402_5%
C
2
1
+5VS
1
+5VS
C
2
2
ECAGND (31)
1
1
3
2
PQ202B
2N7002KDW-2N_SOT363-6
5
+5VS
1
2
8
P
+
O
7
5
PQ215B
2N7002KDW-2N_SOT363-6
ENE9022 Battery Voltage drop detection.
Connect to ENE9022 pin64 AD1.
4
-
G
6
3
1
2
1
1
2
G
PR229
10K_0402_1%
5
VCIN1_BATT_DROP
PU202B
AS393MTR-E1 SO 8P OP
4
1
1
D
PQ205
2N7002KW_SOT323-3
2
2
1
4
2
PR218
10K_0402_1%
PR226
665K_0402_1%
1
2
PR227
15K_0402_1%
PR222
47K_0402_1%
+2.48V
+5VS
PR231
10K_0402_1%
B
PC203
0.01U_0402_25V7K
PD204
1N4148WS-7-F_SOD323-2
5
4
1
2
PQ201B
2N7002KDW-2N_SOT363-6
PR232
14.7K_0402_1%
1
PQ201A
2N7002KDW-2N_SOT363-6
2
2
1
4
1
PR202
1.5M_0402_5%
2
1
O
PU202A
AS393MTR-E1 SO 8P OP
2
-
1
+
2
+2.48V
3
3
P
VCIN1_BATT_DROP
G
8
2
6
2
PQ202A
2N7002KDW-2N_SOT363-6
10K_0402_1%
PR220
47K_0402_1%
6
1
PR219
PC204
0.01U_0402_25V7K
B
6
3
S
B+ near 5V input
2N7002KDW-2N_SOT363-6
PQ215A
1
2
B+
1
layou near +5VALWP
+2.48V
PR225
3.65K_0603_1%
1
2
PR12
PR223
1
2
10K_0402_1%
PR224
1
2
10K_0402_1%
56.2K_0402_1%
2
+5VS
2
VCIN1_BATT_DROP (31)
0.1U_0402_25V6
PR13
10K_0402_1%
2
Cathode
A
PU201
APL431LBAC-TRL_SOT23-3
SA00001MU00
1
@ PC8
REF
3
2
1
2
1
PC209
470P_0402_50V7K
A
Anode
1
Compal Secret Data
Security Classification
Issued Date
2014/02/25
2015/02/25
Deciphered Date
Title
Compal Electronics, Inc.
PWR-BATTERY CONN/OTP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
1.0
BE_BDW
Date:
5
4
3
2
Tuesday, February 25, 2014
Sheet
1
47
of
59
4
PC302
5600P_0402_25V7K
ACDET
DISCHG_G
PR304
200K_0402_1%
1
2
4
2
17
PR318
2.2_0603_5%
1
2
BST_CHG
PD301
REGN
16
PC315
1
2
4
0.047U_0603_16V7K
2
1
2
3
2
1
BQ24737VDD
SRP
SRN
BATT+
@
DL_CHG
PC321
1
2
1
15
14
PR321
10_0603_5%
RB751V-40_SOD323-2
PC319
1U_0603_16V7
1
3
2
1
5
DH_CHG
1
18
SD00000K820
SH00000Q900
PR314
0.01_1206_1%
PL302
4.7UH +-20% PCMB104T-4R7MS 8.5A
1
2CHG 1
4
SB000010U00
2
3
PQ312
AON7752 1N DFN
LODRV
GND
SRP
1U_0603_25V6K
19
3
3
2
C
EMI@ PR319
4.7_1206_5%
1
2PACIN_2
G
S
10x10xH4
DCR: 17~20mohm
Idc: 8.5A
Isat: 15A
16251_SN
2
BQ24737VCC
PQ309
2N7002KW _SOT323-3
D
EMI@ PC320
680P_0603_50V7K
20
SB00000H800
PQ310
AON7408L 1N DFN
ACN
5
PR310
10_1206_5%
2
1
1
2
CMPOUT
ACP
3
CMPIN
ACOK
BTST
2
B
2
PC323
0.1U_0402_25V6
2
+3VALW
1
1
0.1U_0402_25V6
2
VILIM=3.366V*(196/(196+200))
=20*Ichg*10m
Ichg=Idchg=8.33A
PR313
0_0402_5%
1
LX_CHG
HIDRV
ILIM
@ PR323
10K_0402_5%
B
PHASE
SA00004RZ00
SCL
1
3
+3VLP
10
VCC
SRN
PR317
201K_0402_1%
1
2
21
PC314
PU301
SDA
BQ24737RGRR_VQFN20_3P5X3P5
13
1
(31,47) EC_SMB_CK1
10K_0402_1%
1
9
TP
IOUT
2
(31,47) EC_SMB_DA1
ACOFF-1 2
7
100P_0603_50V8
8
4
5
PC312
2
0.01u_0402_25V7K
BM
PC313
1
2
ACDET
11
6
6.8_0603_5%
2
1 12
PR322
PR328
2
1
249K_0402_1%
PR309
2
1
124K_0402_1%
(31,47) ADP_I
2
2
1
0.1U_0402_25V6
PR320
196K_0402_1%
(31) ACOFF
1 PR315
PR312
20K_0402_1%
1
2
PACIN
PC316
0.01U_0402_25V7K
2
1
PQ311
DTC115EUA_SC70-3
1
4
5
PC311
0.1U_0603_25V7K
2
1
1
2
P2-2
3
PQ307B
PR311
47K_0402_1%
1
2
PACIN
charge current: 7.4A
discharge current: 9A
Hybrid: BATT limit 6.5A
P2
PC310
1
2
VIN
2N7002KDW-2N_SOT363-6
PR308
150K_0402_1%
6
1
PACIN_2
C
ACPRN#
1
PD303
1SS355_UMD2-2
1
2
2
PQ307A
2N7002KDW -2N_SOT363-6
PR306
200K_0402_1%
2
2ACOFF-1
PQ306
DTC115EUA_SC70-3
3
DTC115EUA_SC70-3
PC309
0.1U_0402_25V6
1
2
PD302
PC308
0.1U_0402_25V6
1
2
1
1DISCHG_G-1
2
1
PQ305
PR305
47K_0402_1%
1SS355_UMD2-2
1
1
P2-1
2
2
VIN
ACN
ACP
V1
D
PC324
10U_0805_25V6K
2
1
2
@EMI@ PC303
10U_0805_25V6K
PQ303 SB000012B00
AO4455 1P SO8
8
7
6
5
4
2
2
1
@EMI@ PC307
2200P_0402_50V7K
1
2
2
PC301
0.1U_0603_25V7K
2
1
PR303
200K_0402_1%
2
3
1
PR301
47K_0402_5%
1
DTA144EUA_SC70-3
3.8x3.8xH1.8
DCR: 20~25mohm
Idc / Isat: 3.8A
1
PQ304
D
1
2
3
SH00000YG00
PC318
10U_0805_25V6K
2
1
3
2
1
@EMI@ PC306
0.1U_0402_25V6
2
CHG_B+
EMI@ PL301
1UH +-20% PH041H-1R0MS 3.8A
1
2
4
2
1
PC305
10U_0805_25V6K
1
1
Need EC write ChargeOption() bit[8]=0
to disable iFault_Hi function.
B+
SD00000K820
PR302
0.01_1206_1%
4
4
PQ302 SB000012200
AO4447A 1P SOIC8
1
8
2
7
3
6
5
2
PC317
10U_0805_25V6K
2
1
Power Rating = 1W
VACP~VACN spec & lt; 80.64mV
P3
P2
PQ301 SB00000DL10
AO4407AL 1P SO8
8
1
7
2
6
3
5
VIN
3
2
1
PC304
10U_0805_25V6K
5
AO4407AL Vds=-30V
Rds_on=12.7~17mohm@Vgs=-6V
ID = 10A (Ta=70C)
@ PC322
0.1U_0402_25V6
ACIN (31)
PR325
10K_0402_1%
PACIN
1
1 2
PR324
47K_0402_1%
2
MOSFET: 3x3 DFN
H/S Rds(on): 22mohm(Typ), 34mohm(Max)
Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C
PR326
10K_0402_1%
1
2
1
1
BQ24737VDD
PR327
2
ACPRN#
2
L/S Rds(on): 8.2mohm(Typ), 14.5mohm(Max)
Idsm: 12A@Ta=25C, 15A@Ta=70C
DTC115EUA_SC70-3
A
12K_0402_1%
3
PQ314
A
For disable pre-charge circuit
2014/02/25
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2015/02/25
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Charger_BQ24737
Document Number
Rev
1.0
BE_BDW
Tuesday, February 25, 2014
Sheet
1
48
of
59
A
B
C
D
E
1
1
PR401
499K_0402_1%
1
2
PU401
7
8
IN
EN1
IN
EN2
BS
3
6
PC403
PR403
0.01U_0402_25V7K 1K_0402_5%
1
2
1
2
3V5V_EN
1
BST_3V
3V_FB
PR405
2
0_0603_5%
1
PC404
2
PL402
3.3V LDO 150mA~300mA
PR407
2.2K_0402_5%
1
2
(31) EC_ON
1
(31) VCOUT0_MAIN_PWR_ON
@ PR408
2
1
2
1
2
1
5x5xH3
DCR: 20~25mohm
Idc: 6A
Isat: 10A
1
+3VALWP
2
PC412
4.7U_0603_6.3V6M
2
2
+3VLP
2
SY8208BQNC_QFN10_3X3
SA000061M00
PR406
1
5
@EMI@
1 3V_SN
2
LDO
680P_0603_50V7K 4.7_1206_5%
PG
@EMI@ PC413
2
OUT
1.5UH_PCMB053T-1R5MS_6A_20%
SH00000SC00
22U_0603_6.3V6M
PC411
2
GND
1
LX_3V
4
22U_0603_6.3V6M
PC410
9
10
1
LX
T80
2
B+
0.1U_0603_25V7K
@
@P
22U_0603_6.3V6M
PC409
PC406
10U_0805_25V6K
2
1
PC407
C407
10U_0805_25V6K
2
1
3V_VIN
1
22U_0603_6.3V6M
PC408
@EMI@ PC405
2200P_0402_50V7K
2
1
EMI@ PL401
HCB2012KF-121T50_0805
1
2
@EMI@ PC401
0.1U_0402_25V6
2
1
B+
PR404
150K_0402_1%
2
1
ENLDO_3V5V
TDC=6A
Iocp : 8A
FSW : 750KHz
2
@ PJ401
0_0402_5%
1
+3VALWP
MAINPWON
1
2
2
+3VALW
JUMP_43X118
EMI@ PL403
HCB2012KF-121T50_0805
1
2
@EMI@ PC420
0.1U_0402_25V6
2
1
1
PU402
8
IN
EN1
EN2
BS
1
5V_FB
PC415
PR412
6800P_0402_25V7K 1K_0402_5%
1
2
1
2
3V5V_EN
3
6
BST_5V
1
PR413
0_0603_5%
2
PC417
0.1U_0603_25V7K
1
2
3
PL404
5V LDO 150mA~300mA
1
2
1
2
1
2
1
2
1
2
1
7x7xH3
DCR: 20~25mohm
Idc: 8A
Isat: 12A
2
680P_0603_50V7K 4.7_1206_5%
+5VL
@EMI@ PC427
@EMI@ PR414
2
1 5V_SN
2
1
7
1
1
PC421
4.7U_0603_6.3V6M
LDO
+5VALWP
22U_0603_6.3V6M
PC429
PG
SY8208CQNC_QFN10_3X3
SA000061N00
2
1.5UH +-20% PCMC063T-1R5MN 9A
SH000008800
22U_0603_6.3V6M
22U_0603_6.3V6M
PC428
OUT
1
LX_5V
4
22U_0603_6.3V6M
PC425
VCC
10
22U_0603_6.3V6M
PC424
2
LX
22U_0603_6.3V6M
PC423
2
GND
22U_0603_6.3V6M
PC422
5
2
9
5V_VCC
PC426
4.7U_0603_6.3V6M
@EMI@ PC419
2200P_0402_50V7K
2
1
3
PC418
10U_0805_25V6K
2
1
5V_VIN
PC416
10U_0805_25V6K
2
1
B+
PC414
4.7U_0402_6.3V6M
2
2
1
PR410
1M_0402_1%
3V5V_EN
TDC=6A
Iocp : 9A
FSW : 750KHz
@ PJ402
+5VALWP
1
1
2
2
+5VALW
JUMP_43X118
PR402
1
2
10_0402_1%
4
4
Compal Secret Data
Security Classification
2014/02/25
Issued Date
2015/02/25
Deciphered Date
Title
Compal Electronics, Inc.
+3VALW/+5VALW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev
1.0
BE_BDW
Tuesday, February 25, 2014
Sheet
E
49
of
59
5
4
3
2
1
D
D
EMI@ PL503
HCB2012KF-121T50_0805
1
2
PR501
0_0603_5%
1
2
BOOT_1.35V
1
PC507
10U_0805_6.3V6K
VTT
2
1
2
3
4
+VTTREFP
5
+1.35VP
2
FB
PC509
0.033U_0402_16V7K
6
S3
S5
7
2
1
PC506
10U_0805_6.3V6K
20
19
VLDOIN
18
BOOT
17
PHASE
FB_1.35V
PR507
887K_0402_1%
1
2
1.35V_B+
PR506
8.45K_0402_1%
1
2
+1.35VP
1
B
Vout=0.75V* (1+Rup/Rdown)
PR508
10K_0402_1%
2
@ PR509
1
2
(31,35) SYSON
C
2
PR505 100K_0402_5%
0_0402_5%
L/S Rds(on): 2.8mohm(Typ), 3.8mohm(Max)
Idsm: 33.5A@Ta=25C, 42A@Ta=70C
@ PC514
0.1U_0402_10V7K
1
VTTREF_1.35V
off
on
on
8
1
EN_1.35V
+3VALW
VDDQ
21
2
+0.675VSP
off
off
on
VDD
2
MOSFET: 5x6 DFN
H/S Rds(on): 5mohm(Typ), 8.5mohm(Max)
Idsm: 23A@Ta=25C, 18A@Ta=70C
Level
L
L
H
VTTREF
PR513
5.1_0603_5%
B
Mode
S5
S3
S0
VDDP
EN_0.675VSP
PC512
1U_0603_10V6K
1
GND
RT8207MZQW _W QFN20_3X3
TON
+5VALW
CS
12
11
VDD_1.35V
VTTSNS
9
+5VALW
UGATE
16
4
PR504
5.1_0603_5%
1
2
13
PAD
VTTGND
PGND
TON_1.35V
2
LGATE
10
@EMI@ PC513
680P_0402_50V7K
15
14
PR502
11K_0402_1%
1
2 CS_1.35V
PC508
1U_0603_10V6K
1
2
1
+
DL_1.35V
2
1
1 2
@EMI@ PR503
4.7_1206_5%
4
PU501
1
1
5
ESR 12mohm
1
2
TDC=17A (+VRAM)
Iocp : 25A
FSW : 300KHz
SF000003X00
PC510
390U 2.5V M C6 R10M SVPE H5.9
+1.35VP
PL502
1UH_PCMB104T-1R0MH_18A_20%
1
2
SH00000N800
MDU1511RH 1N DFN56-8
SB00000SD00
PQ502
SB00000S800
MDU1516URH 1N DFN56-8
1
1
2
2
3
5
3
10x10xH4
DCR: 3~3.3mohm
Idc: 18A
Isat: 28A
+0.675VSP
SW _1.35V
PC505
0.1U_0603_25V7K
PQ501
C
+1.35VP
DH_1.35V
2
1
2
BST_1.35V
PC511
10U_0805_25V6K
1
2
PC504
10U_0805_25V6K
2
1
PC503
10U_0805_25V6K
1
2
@EMI@ PC502
2200P_0402_50V7K
2
1
1.35V_B+
PGOOD
EMI@ PL501
HCB2012KF-121T50_0805
1
2
@EMI@ PC501
0.1U_0402_25V6
B+
Note: S3 - sleep ; S5 - power off
@ PJ501
1
+1.35VP
2
1
(31,35,51,52,53) SUSP#
PR510
47K_0402_1%
1
2
1
2
2
+1.35V
JUMP_43X118
@ PJ502
1
2
1
2
PC515
0.1U_0402_10V7K
JUMP_43X118
PJ503 @
1
+0.675VSP
1
2
2
+0.675VS
JUMP_43X39
A
Compal Secret Data
Security Classification
Issued Date
2014/02/25
Deciphered Date
2015/02/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
A
Compal Electronics, Inc.
RT8207M
Size
Document Number
Custom
Date:
Rev
1.0
BE_BDW
Tuesday, February 25, 2014
Sheet
1
50
of
59
A
B
C
D
1
+3VALW
2
1
1
PC603
1U_0402_6.3V6K
PU601 SA000034S00
APL5930KAI-TRG_SO8
3
4
FB
PR605
20K_0402_1%
1
FB=0.8V
PR601
2
+1.5VSP_EN
1
PR603
1M_0402_5%
PR606
22.6K_0402_1%
2
2
PC601
0.1U_0402_16V7K
FB_1.5VSP_UMA
1
10K_0402_5%
1
1
PJ602
2
(31,35,50,52,53) SUSP#
1
2
2
1
PC604
0.022U_0402_16V7K
2
1
+1.5VSP
2
EN
POK
2
T81
VOUT
VOUT
GND
8
7
VCNTL
VIN
VIN
22U_0603_6.3V6M
PC605
PC605
PC602
4.7U_0603_6.3V6K
1
6
5
9
1
+1.5VSP
1
@
2
2
+1.5VS
JUMP_43X79
2
2
+12VSP_Panel
COMP
PC1222
22U_0805_25V
2
1
PC1223
22U_0805_25V
2
1
1
2
PC1221 0.01U_0402_16V7K
10 1
2
3
1
@ PC1215
+
2
47U 16V M D2 ESR40M TQC H1.9
SGA00006W 00
PR1210
10K_0402_1%
1
GND
100K_0402_1%
PR1209
PJ1202
2
+12VSP_Panel
1
1
@
2
2
+12VS_PANEL
2
1
GND
2
1
EN
2
SS
12PAL_FB
PC1220
100P_0402_25V8K
1
88.7K_0402_1%
PR1208
2
+12VSP_Panel
1
6
LX
1
PR1213
47K_0402_1%
3
2
2
PR1212
100K_0402_1%
1
PC1226
0.1U_0402_10V7K
2
1
12PAL_EN
FREQ
PAD
0_0402_5%
1
2
PR1211
FB
4
9
12PAL_FREQ
Vin
11
8
12PAL_VIN
PU1203
LX
10U_0805_25V6K
PC1225
2
1
7
PD1202
SX34_SMA2
PC1219
22U_0805_25V
2
1
SH00000G200
1
PC1218
22U_0805_25V
2
1
2
LX_AVDD
5
1
2
3
PC1216
10U_0805_25V6K
PL1203
1UH +-20% MMD-04BZ-1R0M-V1 3.75A
2
1
+5VALW
JUMP_43X79
PC1224
470P 50V K X7R 0402
SA00004JV00
RT9297GQW _W DFN10_3X3
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2014/02/25
Deciphered Date
2015/02/25
Title
+1.5VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
Rev
1.0
BE_BDW
Tuesday, February 25, 2014
D
Sheet
51
of
59
5
4
3
2
1
D
D
PR702
2.2K_0402_5%
1
2
SUSP# (31,35,50,51,53)
1
C
PC702
0.1U_0402_16V7K
PJ701
2
1M_0402_1%
PR703
2
1
C
1
+1.05VSP
1
2
JUMP_43X118
3VLDO_1.05VS
SY8208DQNC_QFN10_3X3
SA000061Q00
2
2
PR708
@
0_0402_5%
1
2
1
2
1
2
1
2
1
2
1
2
2
1
1
PC708
330P_0402_50V7K
5
2
LDO
Rup
PR707
100K_0402_1%
PG
+3VALW
+1.05VSP
TDC=8A
Iocp 12A
FSW 800KHz
1
+1.05VS_PGOOD 2
7
7x7xH3
DCR: 6.7~7.4mohm
Idc: 12A
Isat: 15A
PR709
127K_0402_1%
Rdown
2
2
PR701
10K_0402_5%
BYP
4
1
1
ILMT
PL702
1UH_PCMB063T-1R0MS_12A_20%
1
2
SH00000YE00
LX_1.05VS
2
FB
3
ILMT_1.05VS
10
PC704
0.1U_0603_25V7K
1
2
PC714
4.7U_0603_6.3V6K
LX
1
10U_0805_25V6K
PC707
2
1
10U_0805_25V6K
PC706
2
1
@EMI@
PC705
0.1U_0402_25V6
2
1
GND
PR705
0_0603_5%
1
2
BST_1.05VS
PC713
4.7U_0603_6.3V6K
2
9
1
6
22U_0603_6.3V6M
PC716
1
BS
22U_0603_6.3V6M
PC715
+3VS
EN
22U_0603_6.3V6M
PC712
ILMT_1.05VS
IN
22U_0603_6.3V6M
PC711
PR706
0_0402_5%
8
22U_0603_6.3V6M
PC710
@
+1.05VS
@
PU701
B+_1.05VS
22U_0603_6.3V6M
22U_0603_6.3V6M
PC709
PC709
1
3VLDO_1.05VS
EMI@ PL701
HCB2012KF-121T50_0805
1
2
@EMI@
PC701
2200P_0402_50V7K
2
1
B+
2
@EMI@ PR704
@EMI@ PC703
4.7_1206_5%
680P_0603_50V7K
1
2SNB_1.05VSP
1
2
(31) +1.05VS_PGOOD
B
The current limit is set to 8A, 12A or 16A when this pin
is pull low, floating or pull high
B
VFB=0.6V
Vout=0.6V* (1+Rup/Rdown)
A
A
Compal Secret Data
Security Classification
Issued Date
2014/02/25
Deciphered Date
2015/02/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Size
C
Date:
5
4
3
2
Compal Electronics, Inc.
Document Number
+1.05VS
Rev
1.0
BE_BDW
Sheet
Tuesday, February 25, 2014
1
52
of
59
5
4
3
2
1
D
D
PR1207
@EMI@
1
4.7_1206_5%
1
COMP
1COMP_12VSP
1
2
@EMI@ PC1212
2200P_0402_50V7K
1
2
@EMI@ PC1213
0.1U_0402_25V6
1
2
1
1
2
2
1
GND
GND
10K_0402_1%
PR1201
5
C
+12VSP
PR1202
10K_0402_1%
EN
PAD
PC1209
10U_0805_25V6K
PC1202 0.01U_0402_16V7K
10
1
2
SS_12VSP
2
2FB_12VSP
PC1208
10U_0805_25V6K
SS
11
S
1
2
2
FREQ
4
SA00004JV00
RT9297GQW _W DFN10_3X3
2
@ PC1203
0.1U_0402_10V7K
1
0_0402_5%
3
FB
PQ1202
2N7002KW _SOT323-3
2
G
3
(31,35,50,51,52) SUSP#
D
9
EN_12VSP
2
FREQ_12VSP
Vin
@
PC1207
10U_0805_25V6K
8
PC1214
100P_0402_25V8K
2
1
VIN_12VSP
88.7K_0402_1%
PR1203
7
10U_0805_25V6K
PC1206
2
1
PU1201
EMI@ PL1202
HCB2012KF-121T50_0805
1
2
1
SS1P4-M3-84A_DO-220AA2
LX_12VSP
PR1205
10K_0402_1%
@ PR1206
1
2
PD1201
2
1
PL1201
4.7UH_PCMB063T-4R7MS_5.5A_20%
1
2
SH00000YC00
1
2
6
2
1
PC1205
1500P_0402_50V7K
1
2
PC1210
0.022U_0402_25V7K
2
2
PR1204
100K_0402_1%
4
1
1
5
1
+5VALW
1
680P_0603_50V7K
PC1204
10U_0805_25V6K
C
PC1211
LX
SB00000TJ00
PQ1201 AON7407_DFN8-5
1
2
3
@EMI@
2
LX
P-MOS
7x7xH3
DCR: 28~33mohm
Idc: 5.5A
Isat: 6.5A
2
B
PC1201
4700P_0402_25V7K
B
PJ1201 @
1
+12VSP
1
2
2
+12VS
JUMP_43X39
A
A
Compal Secret Data
Security Classification
2014/02/25
Issued Date
Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Compal Electronics, Inc.
+12V-Boost
Size
A3
Date:
Document Number
Rev
1.0
VPUAE
Tuesday, February 25, 2014
Sheet
1
53
of
59
A
B
C
D
3
2
1
U2_PHASE1
5
L/S Rds(on): 2.8mohm(Typ), 3.8mohm(Max)
Idsm: 33.5A@Ta=25C, 42A@Ta=70C
4
U2_LGATE1
1
1K_0402_5%
2
1
Rocset
+3V3_AON
2
NVVDD_PWM_VID
2
(36)
PC901
10U_0805_25V6K
2
1
1
2
PC905
10U_0805_25V6K
2
1
PC904
10U_0805_25V6K
PL902
0.22UH 20% PCME064T-R22MS0R985 28A
1
2
SH00000OY00
1
+VGA_CORE
1
+@
+
2
PR903 @EMI@
4.7_1206_5%
2
ESR: 9mohm
PC911 @EMI@
680P_0603_50V7K
2
3
2
1
@ PR906 1K_0402_5%
1
2
PR905
14.3K_0402_1%
@ PR904
1
7x7xH4
DCR: 0.98mohm
Idc / Isat: 28A
SGA00006J00
PC909
560U 2V M D2 LESR4.5M SX H1.9
PR902
0_0603_5%
MOSFET: 5x6 DFN
H/S Rds(on): 5mohm(Typ), 8.5mohm(Max)
Idsm: 23A@Ta=25C, 18A@Ta=70C
1
For intel N15P-GX
Imax: 51A
Peck current: 76.5A
OCP: 91.8A
Frequency: 450KHz
SGA20331E10
PC907
330U 2V D2 LESR9M EEFSX H1.9
4
1
2
2
1
U2_UGATE1
MDU1516URH 1N DFN56-8
2
PQ901
SB00000S800
PC906
0.22U_0603_25V7K
1
1
1
SB00000SD00
PQ902
MDU1511RH 1NDFN56-8
2
PR901
2.2_0603_5%
1
2
U2_BOOT1
5
PC1134
+
@EMI@ PC903
2200P_0402_50V7K
2
1
GPU_B+
1
FBMA-L11-201209-121LMA50T_0805
1
2
EMI@
PL901
100U_25V_M
B+
@EMI@ PC902
0.1U_0402_25V6
2
1
GPU_B+
EMI@ PL905
FBMA-L11-201209-121LMA50T_0805
1
2
EMI@
PL906
FBMA-L11-201209-121LMA50T_0805
1
2
+VGA_CORE
1
Rref1
GPU_B+
2
(31) PWR_GPS_DOWN#
3
4
VCC TMSNS1
GND RHYST1
OT1 TMSNS2
OT2 RHYST2
8
7
1
2
PC914
10U_0805_25V6K
2
1
2
1
PC919
10U_0805_25V6K
2
1
PC918
10U_0805_25V6K
@EMI@ PC917
2200P_0402_50V7K
2
1
@EMI@ PC916
0.1U_0402_25V6
2
1
MDU1516URH 1N DFN56-8
U2_PHASE2
PL903
0.22UH 20% PCME064T-R22MS0R985 28A
1
2
+VGA_CORE
3
2
1
1
1 2
PC926 RF@
680P_0603_50V7K
1
7
PC936
0.22U_0603_25V7K
2
U2_PHASE3
RT9610BZQW_WDFN8_2X2
PC935
10U_0805_25V6K
2
1
2
1
PC934
10U_0805_25V6K
2
1
PC933
10U_0805_25V6K
@EMI@ PC932
2200P_0402_50V7K
2
1
PL904
0.22UH 20% PCME064T-R22MS0R985 28A
1
2
+VGA_CORE
SH00000OY00
PR934
10K_0402_1%
4
3
2
1
U2_LGATE3
1
+
PR933 RF@
4.7_1206_5%
2
PC939 RF@
680P_0603_50V7K
(18,36,45)
SGA20331E10
PC937
330U 2V D2 LESR9M EEFSX H1.9
LGATE
1
1
GND
4
2
1 2
PHASE
2
U2_UGATE3 1
PR928
2.2_0603_5%
PR926
1
2
U2_BOOT3
0_0603_5%
2
6
PWM
4
SB00000SD00
PQ906
MDU1511RH 1NDFN56-8
PC941
BOOT
5
2
EN
TP
1
VCC
MDU1516URH 1N DFN56-8
5
5
2
PR929
@
+3V3_AON
1
PQ905
SB00000S800
3
2
1
8
0_0402_5% PR927
1
2
SA00005Z710
3
UGATE
@EMI@ PC931
0.1U_0402_25V6
2
1
2
PU902
9
U2_PWM3 1
0_0402_5%
GPU_B+
3
0.01UF_0402_25V7K
18
U2_BOOT2
GPU_EN
DGPU_PWROK
+
2
PR923
2.2_0603_1%
0.1U_0603_25V7K
2
1
U2_PHASE2
PC928
U2_LGATE2
19
0.1U_0603_25V7K
2
1
20
SGA20331E10
PC923
330U 2V D2 LESR9M EEFSX H1.9
U2_PWM3
21
+5VS
PC929
22
PR921
2.2_0603_1%
1
PR918 RF@
4.7_1206_5%
2
U2_LGATE1
2
23
4
U2_LGATE2
1
U2_PHASE1
SB00000SD00
PQ904
MDU1511RH 1NDFN56-8
5
U2_UGATE1
GPU_EN
U2_BOOT1
BOOT2
24
RT8813AGQW_WQFN24_4X4
SA00005ZV00
1
UGATE2
PGOOD
PHASE2
2
U2_PHASE1
U2_PHASE2
PH901
100K_0402_1%_NCP15WF104F03RC
PU903
1
(36,45)
2
PR935
7.68K_0402_1%
1
4
2
U2_PHASE3
1
PR938
8.66K_0402_1%
4
1
BOOT1
2
3
EN
UGATE1
4
PSI
6
5
VID
REFADJ
2
10K_0402_1%
2
10K_0402_1%
2
10K_0402_1%
17
SS
LAGTE2
16
@ PC930
0.01U_0402_16V7K
1
2
2
2
PC908
0.1U_0603_25V7K
2
3
2
1
GPU_VID
VSNS
PVCC
VCC/ISEN1
12
GND/PWM3
V0.1A
1
3V3_MAIN_EN
@ PC938
@PC938
0.01UF_0402_25V7K
+5VS
RGND
U2_UGATE2
Css
@ PR925
100_0402_1%
+3VLP
1
SH00000OY00
PHASE1
TON
15
GPU_FB
2
2
LGATE1
TALERT/ISEN2
GPU_COMP
2
PC913
0.22U_0603_25V7K
PR915
0_0603_5%
1
VREF
TSNS/ISEN3
11
@ PC927
47P_0402_50V8J
0_0402_1%
1
9
10
REFIN
GND
2
@ PR924
1
8
14
GPU_TON
7
13
GPU_VREF
GPU_FBRTN
@ PR922
100_0402_1%
+VGA_CORE
@ PC925
@PC925
0.01UF_0402_25V7K
2
3
(37) VCCSENSE_VGA
GPU_REFIN
25
2
PR916
1K_0402_5%
1
2
GPU_PSI
1
2
C
PR919
357K_0402_1%
1
2
1
1
2
PQ903
SB00000S800
GPU_FBRTN
1
@ PR920
0_0402_1%
2
1
1
(36)
U2_UGATE2
PU901
(37) VSSSENSE_VGA
NVVDD_PSI
5
@ PR912 0_0402_1%
1
2
GPU_REFADJ
1
PR917
0_0402_5%
PC921
2700P_0402_50V7K
2
1
2
2
PR911
20K_0402_1%
1
2
@ PC915 47P_0402_50V8J
1
2
@ PC920
0.01U_0402_16V7K
1
PR914
18K_0402_1%
PR910
2K_0402_5%
1
2
Rton
PR909
2.2_0603_5%
2
U2_BOOT2 1
Rrefadj
2
Rboot
Rref2
2
PR908
20K_0402_1%
1
GPU_TSNS/ISEN3
PR930
1 GPU_TALERT/ISEN2
PR931
1
GPU_VCC/ISEN1
PR932
GPU_PGOOD1
2
1
1
+@
PC912
1U_0402_6.3V6K
2
GPU_B+
SGA20331E10
PC910
330U 2V D2 LESR9M EEFSX H1.9
@ PR907 0_0402_1%
4
6
5
G718TM1U_SOT23-8
Compal Secret Data
Security Classification
Issued Date
2014/02/25
Deciphered Date
2015/02/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
RT8813
Size
Date:
A
B
C
Compal Electronics, Inc.
Document Number
Rev
1.0
Tuesday, February 25, 2014
D
Sheet
54
of
59
A
B
C
D
2
PGND2
VSW
BOOT_R PGND1
BOOT
VDD
PWM
SKIP#
4
1
3
2
2
1
+5VS
1
2
SKIP#
@ PR1118
@PR1118
0_0402_5%
4
3
3
1
2
PC1105
0.15U_0402_10V6K
1
2
CSN3
+VCC_CORE
2
7x7xH4
DCR: 0.66mohm
Idc: 36A
Isat: 45A
PC1110
1U_0402_6.3V6K
VGATE (31)
2
6
2.2_0402_1%
1
2
7
.1U_0402_16V7K
8
VIN
PGND2
VSW
BOOT_R PGND1
BOOT
VDD
PWM
SKIP#
4
1
3
2
2
1
PU1102
SA000066Y00
CSD97374CQ4M_SON8_3P5X4P5
+5VS
1
2
SKIP#
@ PR1131
@PR1131
0_0402_5%
4
1
2
@
PC1113
0.15U_0402_10V6K
PC1112
0.15U_0402_10V6K
1
2
CSN1
+VCC_CORE
3
PL1102 SH00000U300
0.15UH 20% PCME064T-R15MS0R667 36A
For intel SB 47W
TDC: 33A
Support Turbo: 95A
OCP setting: 114A
Frequency: 1MHz
DC_LL: -1.5mV/A
PC1123
1U_0402_6.3V6K
1
PR1132
10_0402_1%
1
2
PR1124
3.01K_0402_1%
2
1
2
2
CSP1
1
5
PR1130
1
PR1126
RF@
4.7_1206_5%
1
2
PH1103
10K_0402_1%_B25/50 3370K
RF@
PC1114
680P_0402_50V7K
1
2
9
PC1119
2
1
PC1118
2
1
1
2
EMI Part (47.1)
CPU_B+
2
1
PC1116 @EMI@
2200P_0402_50V7K
2
1
+3VS
PR1125
11.8K_0402_1%
2
1
EMI Part (47.1)
1
1
PR1123
10K_0402_1%
10U_0805_25V6K
2
1
PC1111
1U_0402_6.3V6K
PR1120
2.43K_0402_1%
2
CSP1-1 1
10U_0805_25V6K
PAD
1
VR_SVID_DAT
2
1
PR1122
10_0402_1%
2
PC1122
PWM2
2
2
7
.1U_0402_16V7K
8
VIN
PGND2
VSW
BOOT_R PGND1
BOOT
PWM
VDD
SKIP#
4
1
3
2
2
1
PU1103
SA000066Y00
CSD97374CQ4M_SON8_3P5X4P5
@ PC1133
@PC1133
47P_0402_50V8J
+5VS
1
2
@ PR1140
@PR1140
0_0402_5%
SKIP#
4
3
1
2
@
PC1126
0.15U_0402_10V6K
PC1125
0.15U_0402_10V6K
1
2
CSP2
CSN2
+VCC_CORE
PL1103 SH00000U300
0.15UH 20% PCME064T-R15MS0R667 36A
PC1132
1U_0402_6.3V6K
2
1
VR_HOT#
6
3
1
(9) VR_SVID_DAT
5
2
2.2_0402_1%
2
1
PC1131
PR1138
@EMI@
4.7_1206_5%
1
2
9
PC1130
2
1
1
PR1139
(9) VR_SVID_ALRT#
10U_0805_25V6K
PC1129
2
1
(9) VR_SVID_CLK
10U_0805_25V6K
PR1137
130_0402_1%
2
1
PR1136
54.9_0402_1%
2
1
1
2
PC1128
.1U_0402_16V7K
@EMI@ PC1127
680P_0402_50V7K
1
2
PH1104
10K_0402_1%_B25/50 3370K
EMI Part (47.1)
CPU_B+
1
PR1135
11.8K_0402_1%
2
1
2
+VCCIO_OUT
PR1134
3.01K_0402_1%
2
1
PR1133
2.43K_0402_1%
2
CSP2-1 1
PC1124
1U_0402_6.3V6K
(31) VR_HOT#
@
CSP3
PL1104 SH00000U300
0.15UH 20% PCME064T-R15MS0R667 36A
2
PU1104
SA000066Y00
CSD97374CQ4M_SON8_3P5X4P5
PWM1
+5VS
VIN
1
PR1141
1.5K_0402_1%
@
PC1121
0.33U_0402_10V6K
3
5
2
PWM3
PR1116
RF@
4.7_1206_5%
1
2
9
PC1108
2
1
10U_0805_25V6K
PC1107
2
1
PWM2
4
PC1109
PWM3
1
PWM1
5
33
ALERT#
VCLK
VR_HOT#
6
RF@
PC1106
680P_0402_50V7K
1
2
2
6
2.2_0402_1%
2
7
.1U_0402_16V7K
8
1
SKIP#
VREF
PR1129
PC1120
10K_0402_1% 330P_0402_50V7K
1
2
1
2
10U_0805_25V6K
9
O-USR
11
10
F-IMAX
OCP-I
B-RAMP
IMON
12
13
14
PR1127
3.4K_0402_1%
1
2
1
PR1117
VR_ON (31)
7
PC1117 @EMI@
0.1U_0402_25V6
PR1128
10K_0402_1%
1
2
VDIO
8
2
@ PC1115
2.2P_0402_50V8C
1
2
VR_SVID_ALRT# 32
@ PR1121
@PR1121
0_0402_5%
GND
VFB
VDD
31
2
GFB
PWM3
PGOOD
30
24
SA000062510
CSN3
25
1
VFB
TPS51631ARSMR_QFN32_4X4
CSP3
VR_SVID_CLK
@ PR1119
@PR1119
0_0402_5%
1
2
23
VR_HOT#
GFB
PWM2
V5A
22
CSN3
PWM1
CSP2
29
21
CSP3
CSN2
28
20
SKIP#
VREF
19
CSP2
VR_ON
CSN1
27
CSN2
CSP1
COMP
18
DROOP
17
CSN1
26
CSP1
THERM
VBAT
PU1101
SLEWA
16
15
O-USR
10K_0402_1%
(9) VCCSENSE
F-IMAX
2
2
(9) VSSSENSE
B-RAM
OCP-I
SLEWA
PR1115
1
CPU_B+
PC1104
0.15U_0402_10V6K
EMI Part (47.1)
CPU_B+
PH1101
10K_0402_1%_B25/50 3370K
2
PR1112
2.43K_0402_1%
2
CSP3-1 1
PR1101
3.01K_0402_1%
2
1
+
1
2
CPU_B+
1
100U_25V_M
SF000004L00
PC1101
+
100U_25V_M
SF000004L00
PC1135
PR1111
20K_0402_1%
2
1
PR1110
150K_0402_1%
2
1
PR1109
150K_0402_1%
2
1
1
PR1114
11.8K_0402_1%
2
1
PR1106
36.5K_0402_1%
2
1
PR1105
255K_0402_1%
2
1
PR1103
105K_0402_1%
2
1
PC1102
4700P_0402_16V7K
2
1
PR1107
39K_0402_1%
2
1
PR1113
39K_0402_1%
1
2
EMI@ PL1106
FBMA-L11-201209-121LMA50T_0805
2
TPS51361A = & gt; 39Kohm,
TPS51633RSMR = & gt; 20Kohm
EMI@ PL1101
FBMA-L11-201209-121LMA50T_0805
1
2
EMI@ PL1105
FBMA-L11-201209-121LMA50T_0805
1
2
B+
PC1103
1000P_0402_50V7K
2
1
1
2
@ PR1102
10K_0402_1%
PR1108
8.06K_0402_5%
2
1
1
VREF
@ PR1104
100K_0402_1%
2
1
1
PH1102
100K_0402_1%_B25/50 4250K
2
1
1
4
4
2014/02/25
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Deciphered Date
2015/02/25
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R & D Document Number
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
CPU_CORE-47W
Rev
1.0
Sheet
55
of
59
2
1
1
1
1
2
Security Classification
Issued Date
2014/02/25
3
1
2
1
2
1
2
Deciphered Date
1
2
PC951
22U_0603_6.3V6M
1
2
PC952
22U_0603_6.3V6M
1
2
2
1
2015/02/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Compal Secret Data
Date:
PC962
4.7U_0603_6.3V6M
PC960
4.7U_0603_6.3V6M
2
1
PC964
4.7U_0603_6.3V6M
2
1
1
2
1
2
1
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
PC970
4.7U_0603_6.3V6M
2
1
1
2
PC967
4.7U_0603_6.3V6M
2
1
1U_0402_6.3V6K
PC1022
2
1
1U_0402_6.3V6K
PC1023
2
1
2
2
2
2
2
2
2
2
1
PC955
4.7U_0603_6.3V6M
PC965
4.7U_0603_6.3V6M
2
1
PC944
4.7U_0603_6.3V6M
2
1
PC958
4.7U_0603_6.3V6M
2
1
1U_0402_6.3V6K
PC1026
2
1
1U_0402_6.3V6K
PC1027
PC943
4.7U_0603_6.3V6M
2
1
PC940
4.7U_0603_6.3V6M
2
1
PC946
4.7U_0603_6.3V6M
2
1
PC959
4.7U_0603_6.3V6M
2
1
PC954
4.7U_0603_6.3V6M
2
1
PC961
4.7U_0603_6.3V6M
2
1
2
2
1U_0402_6.3V6K
PC1025
2
1
PC966
4.7U_0603_6.3V6M
PC969
4.7U_0603_6.3V6M
2
1
1U_0402_6.3V6K
PC1021
2
1
1U_0402_6.3V6K
PC1024
2
1
PC968
4.7U_0603_6.3V6M
2
1
1U_0402_6.3V6K
PC1020
2
1
2
1
1
1
1
1
1
1
1
1
1
1
Under VGA Core
PC953
4.7U_0603_6.3V6M
2
1
PC963
4.7U_0603_6.3V6M
2
1
2
1
2
2
3
PC971
22U_0603_6.3V6M
2
+VGA_CORE
PC949
22U_0603_6.3V6M
2
1
+VGA_CORE
PC948
22U_0603_6.3V6M
1
C
PC947
22U_0603_6.3V6M
2
2
4
PC942
22U_0603_6.3V6M
PC1330
1U_0402_6.3V6K
2
1U_0402_6.3V6K
PC1329
2
1U_0402_6.3V6K
PC1328
1
PC1320
PC1320
22U_0603_6.3V6M
2
@
PC1310
PC1310
22U_0603_6.3V6M
4
@
PC1319
22U_0603_6.3V6M
+
PC1309
22U_0603_6.3V6M
2
PC1318
22U_0603_6.3V6M
330U_D2_2VM_R9M
PC1308
22U_0603_6.3V6M
@ PC1332
PC1317
22U_0603_6.3V6M
22U_0603_6.3V6M
@
PC1325
22U_0603_6.3V6M
1
PC1307
22U_0603_6.3V6M
22U_0603_6.3V6M
PC1316
22U_0603_6.3V6M
+VCC_CORE
PC1306
22U_0603_6.3V6M
@
PC1326
22U_0603_6.3V6M
2
PC1315
22U_0603_6.3V6M
330U_D2_2VM_R9M
+
PC1305
22U_0603_6.3V6M
@
PC1324
22U_0603_6.3V6M
22U_0603_6.3V6M
PC1331
PC1314
22U_0603_6.3V6M
22U_0603_6.3V6M
1
PC1304
22U_0603_6.3V6M
22U_0603_6.3V6M
2
@
PC1323
PC1323
22U_0603_6.3V6M
+
PC1313
PC1313
22U_0603_6.3V6M
PC1322
22U_0603_6.3V6M
+VCC_CORE
PC1303
PC1303
22U_0603_6.3V6M
PC1312
22U_0603_6.3V6M
1
PC1302
22U_0603_6.3V6M
PC1321
22U_0603_6.3V6M
22U_0603_6.3V6M
5
PC1311
22U_0603_6.3V6M
22U_0603_6.3V6M
2
@
PC1301
22U_0603_6.3V6M
22U_0603_6.3V6M
B
1U_0402_6.3V6K
PC1327
5
2
1
+VCC_CORE
D
GB4B-128 package
D
C
Near VGA Core
B
+VCC_CORE
1
330U_D2_2VM_R9M
@ PC1333
A
A
Title
Compal Electronics, Inc.
Size
Document Number
Custom
PWR-PROCESSOR_DECOUPLING
Tuesday, February 25, 2014
BE_BDW
Sheet
1
56
of
59
Rev
1.0
5
4
3
2
Version change list (P.I.R. List)
Item
1
Page 1 of 1
for PWR
Reason for change
PG#
Modify List
Date
Phase
11/15
SIV
11/15
SIV
SIV
1
for panel Vdrop
51
add boost solution
2
for EMI request
48
PR319, PC320 change to mount
3
for RF request
54
PR918, PC926, PR933, PC939 change to mount
11/18
for RF request
55
PC1114, PR1126, PC1106, PR1116 change to mount
11/18
SIV
47
del PR222, PR227, PC204, PR220, PU202, PC206,
PR219, PQ201, PQ205, PR228
12/30
SIT
12/30
SIT
12/30
SIT
D
D
4
6
battery can't be remove
7
for acoustic noise
8
55, 56
SIV rework
48
C
9
SIV rework
47
10
for HW request
50
11
accuracy modify
52
PR226, PD201, PC205, PR218,
add PC1135, 1332
PR309
PR312
Add a
PC312
PQ302
is changed from 392K_0402_1% to 124K_0402_1% (SD034124380)
is changed from 59K_0402_1% to 20K_0402_1% (SD034200280)
resistor 249K_0402_1% (SD034249380) between pin 6 of PU301 and PACIN.
is changed from 2200pF_0402_25V_X7R to 0.01uF_0402_25V_X7R (SE075103K80)
change to AO4447A
C
PR217 change to 30K
PR221 change to 110k
12/30
SIT
PR506 change to SD000000680 8.45K 1%
12/30
SIT
PR707 change to 100K +-1%
PR709 change to 127K +-1%
1/20
SVT
B
B
15
16
17
A
A
2014/02/25
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Deciphered Date
2015/02/25
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
PIR (PWR)
Rev
1.0
BE_BDW
Tuesday, February 25, 2014
Sheet
1
57
of
59
5
4
3
2
Version change list (P.I.R. List)
Item
D
Fixed Issue
Page 1 of 1 for HW
Reason for change
Add 3D Camera function
1
Rev.
PG#
0.2
23
22
Remove LPF for woofer amplifier
2
1
0.2
27
Modify List
Add
Add
Del
Add
Date
U25,C502~C511.
R386~R400,R550~R559.
Q14,R205,C319
U13
10/30
Phase
SIV
Verify
SIV
Phase
D
Change R224- & gt; 20K,R297- & gt; 62K
Change R1564,R1565- & gt; 0 ohm,R341- & gt; 15K,
Change R342- & gt; 20.5K,R81- & gt; 200K.
un-stuff C450,C443
10/30
SIV
Verified by
SDV rework.
3
0.2
14
31
Del D1
Add AC_PRESENT_R to U18 pin 19
11/03
SIV
Verified by
SDV rework.
4
Change USB power switch
(follow B/E series)
0.2
30
Change U16,U17- & gt; SY6288D20AAC
11/04
SIV
Verified by
SDV rework.
5
Add resistor for 15”/17” K/B co-lay
0.2
31
Add R1001~R1012,R1021~R1032
11/04
SIV
SIV
6
Cancel 3D Camera function
0.3
23
22
C
AC/DC detect issue
Del
Del
Del
Del
C
U25,C502~C508
R387~R400,R550~R557.
R255,R256,R261,R262,L41,L42,D21.
R204,R386,R558,R559
12/17
SIT
7
TP lock LED function
0.3
31
TP_LOCK_LED# from U18_pin34 to LED
12/24
SIT
8
KB Backight behavior
0.3
32
Add R337,R335,C434,Q23
12/24
SIT
9
Improve VRAM
0.3
39
C790 stuff 330uf
12/25
SIT
+1.35V
10
Hole size change for Thermal bracket.
1.0
34
H1,H2,H3,H4,H5,H6 : change to 4.2 mm.
2/5
SVT
11
B
Phase
ESD reserve
1.0
32
Reserve C479,C480.
2/5
SVT
SIT
Phase
Verified by
SIV rework.
Verified by
SIV rework.
Verified by
SIV rework.
Verified by
SIT rework.
SVT
Phase
B
12
13
14
15
16
17
18
19
A
A
20
Compal Secret Data
Security Classification
Issued Date
2014/02/25
2015/02/25
Deciphered Date
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
PIR-HW
Rev
1.0
LA-B111P
Tuesday, February 25, 2014
Sheet
1
58
of
59
5
4
3
2
1
Timing Diagram for G3 or S4-5/M-off (Suspend Well Off) to S0/M0 [non Deep S4/S5 Platform]
+3VLP
EC_ON
T1=NA
D
D
T2 & gt; 100 ms
ON_OFF
T6=100ms
T5=110ms
PBTN_OUT#
EC_RSMRST#
T4=110ms
PM_SLP_S5#
PM_SLP_S4#
T7=0ms
SYSON
C
C
PM_SLP_S3#
T8=20ms
SUSP#
KB_RST#
T9=20ms
EC_SCI
VR_ON
T10=100ms
12/11/20
VGATE
B
B
T11=20ms
PCH_PWROK
T12=40ms
SYS_PWROK
H_CPUPWRGD
PM_DRAM_PWRGD
PLT_RST#
A
A
Color
Command
Signal Names
Timing of these signals is set by PCH or processor
Signal Names
Timing of these signals should be met by the platform (EC)
Signal Names
Timing of these signals is set by IntelR MVP
Signal Names
Voltage rails or chip-to-chip buses
Compal Secret Data
Security Classification
Issued Date
2014/02/25
Deciphered Date
2015/02/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Date:
5
4
3
2
Compal Electronics, Inc.
Power Sequence
Size
Document Number
Custom
1
Tuesday, February 25, 2014
Rev
1.0
LA-B111P
Sheet
59
of
59
www.s-manuals.com