Tak prawą ręką przez lewą nogę zrobiłem koledze projekt do AC6 bez HAL-a (zajęlo to 4 minuty wliczając ładowanie AC6 i CubeMx) (załacznik na dole tego postu). W ac6 import project <ciach> Post raportowany. Takie sprawy proszę załatwiać przez PW, gdyż dla moderatora obsługującego raport powstaje niezręczna sytuacja, że post dot. sposobu moderacji także podlega moderacji. :) Dodano po 23 : bo Ac6 też nie wydaje mi się tym czym bym chciał. No to już kolega widzę specjalista - a jeszcze linijki kodu nie napisał pod ARM-a. Można od razu pisać. Gdzieś na necie widziałem kod z plikiem nagłówkowym stm32f103.h, ale teraz nie wiem gdzie... Rzeczywiście do F030 jak ulał - proponuję zaincludować jakiś z ATMega - może się nada (był już na forum Kolega, który używał nazw rejestrów timera Atmegi na STM-ie i się dziwił że się ni kompiluje - bo w końcu płytka była o nazwie arduino)
/* ----------------------------------------------------------------------
* Copyright (C) 2010-2015 ARM Limited. All rights reserved.
*
* $Date: 20. October 2015
* $Revision: V1.4.5 b
*
* Project: CMSIS DSP Library
* Title: arm_math.h
*
* Description: Public header file for CMSIS DSP Library
*
* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* " AS IS " AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
/**
\mainpage CMSIS DSP Software Library
*
* Introduction
* ------------
*
* This user manual describes the CMSIS DSP software library,
* a suite of common signal processing functions for use on Cortex-M processor based devices.
*
* The library is divided into a number of functions each covering a specific category:
* - Basic math functions
* - Fast math functions
* - Complex math functions
* - Filters
* - Matrix functions
* - Transforms
* - Motor control functions
* - Statistical functions
* - Support functions
* - Interpolation functions
*
* The library has separate functions for operating on 8-bit integers, 16-bit integers,
* 32-bit integer and 32-bit floating-point values.
*
* Using the Library
* ------------
*
* The library installer contains prebuilt versions of the libraries in the & lt; code & gt; Lib & lt; /code & gt; folder.
* - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7)
* - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7)
* - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7)
* - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7)
* - arm_cortexM7l_math.lib (Little endian on Cortex-M7)
* - arm_cortexM7b_math.lib (Big endian on Cortex-M7)
* - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
* - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
* - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
* - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
* - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
* - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
* - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+)
* - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+)
*
* The library functions are declared in the public file & lt; code & gt; arm_math.h & lt; /code & gt; which is placed in the & lt; code & gt; Include & lt; /code & gt; folder.
* Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
* public header file & lt; code & gt; arm_math.h & lt; /code & gt; for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
* Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or
* ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
*
* Examples
* --------
*
* The library ships with a number of examples which demonstrate how to use the library functions.
*
* Toolchain Support
* ------------
*
* The library has been developed and tested with MDK-ARM version 5.14.0.0
* The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
*
* Building the Library
* ------------
*
* The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the & lt; code & gt; CMSIS\\DSP_Lib\\Source\\ARM & lt; /code & gt; folder.
* - arm_cortexM_math.uvprojx
*
*
* The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
*
* Pre-processor Macros
* ------------
*
* Each library project have differant pre-processor macros.
*
* - UNALIGNED_SUPPORT_DISABLE:
*
* Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
*
* - ARM_MATH_BIG_ENDIAN:
*
* Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
*
* - ARM_MATH_MATRIX_CHECK:
*
* Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
*
* - ARM_MATH_ROUNDING:
*
* Define macro ARM_MATH_ROUNDING for rounding on support functions
*
* - ARM_MATH_CMx:
*
* Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
* and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
* ARM_MATH_CM7 for building the library on cortex-M7.
*
* - __FPU_PRESENT:
*
* Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
*
* & lt; hr & gt;
* CMSIS-DSP in ARM::CMSIS Pack
* -----------------------------
*
* The following files relevant to CMSIS-DSP are present in the & lt; b & gt; ARM::CMSIS & lt; /b & gt; Pack directories:
* |File/Folder |Content |
* |------------------------------|------------------------------------------------------------------------|
* |\b CMSIS\\Documentation\\DSP | This documentation |
* |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) |
* |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions |
* |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library |
*
* & lt; hr & gt;
* Revision History of CMSIS-DSP
* ------------
* Please refer to \ref ChangeLog_pg.
*
* Copyright Notice
* ------------
*
* Copyright (C) 2010-2015 ARM Limited. All rights reserved.
*/
/**
* @defgroup groupMath Basic Math Functions
*/
/**
* @defgroup groupFastMath Fast Math Functions
* This set of functions provides a fast approximation to sine, cosine, and square root.
* As compared to most of the other functions in the CMSIS math library, the fast math functions
* operate on individual values and not arrays.
* There are separate functions for Q15, Q31, and floating-point data.
*
*/
/**
* @defgroup groupCmplxMath Complex Math Functions
* This set of functions operates on complex data vectors.
* The data in the complex arrays is stored in an interleaved fashion
* (real, imag, real, imag, ...).
* In the API functions, the number of samples in a complex array refers
* to the number of complex values; the array contains twice this number of
* real values.
*/
/**
* @defgroup groupFilters Filtering Functions
*/
/**
* @defgroup groupMatrix Matrix Functions
*
* This set of functions provides basic matrix math operations.
* The functions operate on matrix data structures. For example,
* the type
* definition for the floating-point matrix structure is shown
* below:
* & lt; pre & gt;
* typedef struct
* {
* uint16_t numRows; // number of rows of the matrix.
* uint16_t numCols; // number of columns of the matrix.
* float32_t *pData; // points to the data of the matrix.
* } arm_matrix_instance_f32;
* & lt; /pre & gt;
* There are similar definitions for Q15 and Q31 data types.
*
* The structure specifies the size of the matrix and then points to
* an array of data. The array is of size & lt; code & gt; numRows X numCols & lt; /code & gt;
* and the values are arranged in row order. That is, the
* matrix element (i, j) is stored at:
* & lt; pre & gt;
* pData[i*numCols + j]
* & lt; /pre & gt;
*
* \par Init Functions
* There is an associated initialization function for each type of matrix
* data structure.
* The initialization function sets the values of the internal structure fields.
* Refer to the function & lt; code & gt; arm_mat_init_f32() & lt; /code & gt; , & lt; code & gt; arm_mat_init_q31() & lt; /code & gt;
* and & lt; code & gt; arm_mat_init_q15() & lt; /code & gt; for floating-point, Q31 and Q15 types, respectively.
*
* \par
* Use of the initialization function is optional. However, if initialization function is used
* then the instance structure cannot be placed into a const data section.
* To place the instance structure in a const data
* section, manually initialize the data structure. For example:
* & lt; pre & gt;
* & lt; code & gt; arm_matrix_instance_f32 S = {nRows, nColumns, pData}; & lt; /code & gt;
* & lt; code & gt; arm_matrix_instance_q31 S = {nRows, nColumns, pData}; & lt; /code & gt;
* & lt; code & gt; arm_matrix_instance_q15 S = {nRows, nColumns, pData}; & lt; /code & gt;
* & lt; /pre & gt;
* where & lt; code & gt; nRows & lt; /code & gt; specifies the number of rows, & lt; code & gt; nColumns & lt; /code & gt;
* specifies the number of columns, and & lt; code & gt; pData & lt; /code & gt; points to the
* data array.
*
* \par Size Checking
* By default all of the matrix functions perform size checking on the input and
* output matrices. For example, the matrix addition function verifies that the
* two input matrices and the output matrix all have the same number of rows and
* columns. If the size check fails the functions return:
* & lt; pre & gt;
* ARM_MATH_SIZE_MISMATCH
* & lt; /pre & gt;
* Otherwise the functions return
* & lt; pre & gt;
* ARM_MATH_SUCCESS
* & lt; /pre & gt;
* There is some overhead associated with this matrix size checking.
* The matrix size checking is enabled via the \#define
* & lt; pre & gt;
* ARM_MATH_MATRIX_CHECK
* & lt; /pre & gt;
* within the library project settings. By default this macro is defined
* and size checking is enabled. By changing the project settings and
* undefining this macro size checking is eliminated and the functions
* run a bit faster. With size checking disabled the functions always
* return & lt; code & gt; ARM_MATH_SUCCESS & lt; /code & gt; .
*/
/**
* @defgroup groupTransforms Transform Functions
*/
/**
* @defgroup groupController Controller Functions
*/
/**
* @defgroup groupStats Statistics Functions
*/
/**
* @defgroup groupSupport Support Functions
*/
/**
* @defgroup groupInterpolation Interpolation Functions
* These functions perform 1- and 2-dimensional interpolation of data.
* Linear interpolation is used for 1-dimensional data and
* bilinear interpolation is used for 2-dimensional data.
*/
/**
* @defgroup groupExamples Examples
*/
#ifndef _ARM_MATH_H
#define _ARM_MATH_H
/* ignore some GCC warnings */
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored " -Wsign-conversion "
#pragma GCC diagnostic ignored " -Wconversion "
#pragma GCC diagnostic ignored " -Wunused-parameter "
#endif
#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
#if defined(ARM_MATH_CM7)
#include " core_cm7.h "
#elif defined (ARM_MATH_CM4)
#include " core_cm4.h "
#elif defined (ARM_MATH_CM3)
#include " core_cm3.h "
#elif defined (ARM_MATH_CM0)
#include " core_cm0.h "
#define ARM_MATH_CM0_FAMILY
#elif defined (ARM_MATH_CM0PLUS)
#include " core_cm0plus.h "
#define ARM_MATH_CM0_FAMILY
#else
#error " Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0 "
#endif
#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
#include " string.h "
#include " math.h "
#ifdef __cplusplus
extern " C "
{
#endif
/**
* @brief Macros required for reciprocal calculation in Normalized LMS
*/
#define DELTA_Q31 (0x100)
#define DELTA_Q15 0x5
#define INDEX_MASK 0x0000003F
#ifndef PI
#define PI 3.14159265358979f
#endif
/**
* @brief Macros required for SINE and COSINE Fast math approximations
*/
#define FAST_MATH_TABLE_SIZE 512
#define FAST_MATH_Q31_SHIFT (32 - 10)
#define FAST_MATH_Q15_SHIFT (16 - 10)
#define CONTROLLER_Q31_SHIFT (32 - 9)
#define TABLE_SIZE 256
#define TABLE_SPACING_Q31 0x400000
#define TABLE_SPACING_Q15 0x80
/**
* @brief Macros required for SINE and COSINE Controller functions
*/
/* 1.31(q31) Fixed value of 2/360 */
/* -1 to +1 is divided into 360 values so total spacing is (2/360) */
#define INPUT_SPACING 0xB60B61
/**
* @brief Macro for Unaligned Support
*/
#ifndef UNALIGNED_SUPPORT_DISABLE
#define ALIGN4
#else
#if defined (__GNUC__)
#define ALIGN4 __attribute__((aligned(4)))
#else
#define ALIGN4 __align(4)
#endif
#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
/**
* @brief Error status returned by some functions in the library.
*/
typedef enum
{
ARM_MATH_SUCCESS = 0, /** & lt; No error */
ARM_MATH_ARGUMENT_ERROR = -1, /** & lt; One or more arguments are incorrect */
ARM_MATH_LENGTH_ERROR = -2, /** & lt; Length of data buffer is incorrect */
ARM_MATH_SIZE_MISMATCH = -3, /** & lt; Size of matrices is not compatible with the operation. */
ARM_MATH_NANINF = -4, /** & lt; Not-a-number (NaN) or infinity is generated */
ARM_MATH_SINGULAR = -5, /** & lt; Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
ARM_MATH_TEST_FAILURE = -6 /** & lt; Test Failed */
} arm_status;
/**
* @brief 8-bit fractional data type in 1.7 format.
*/
typedef int8_t q7_t;
/**
* @brief 16-bit fractional data type in 1.15 format.
*/
typedef int16_t q15_t;
/**
* @brief 32-bit fractional data type in 1.31 format.
*/
typedef int32_t q31_t;
/**
* @brief 64-bit fractional data type in 1.63 format.
*/
typedef int64_t q63_t;
/**
* @brief 32-bit floating-point type definition.
*/
typedef float float32_t;
/**
* @brief 64-bit floating-point type definition.
*/
typedef double float64_t;
/**
* @brief definition to read/write two 16 bit values.
*/
#if defined __CC_ARM
#define __SIMD32_TYPE int32_t __packed
#define CMSIS_UNUSED __attribute__((unused))
#elif defined(__ARMCC_VERSION) & & (__ARMCC_VERSION & gt; = 6010050)
#define __SIMD32_TYPE int32_t
#define CMSIS_UNUSED __attribute__((unused))
#elif defined __GNUC__
#define __SIMD32_TYPE int32_t
#define CMSIS_UNUSED __attribute__((unused))
#elif defined __ICCARM__
#define __SIMD32_TYPE int32_t __packed
#define CMSIS_UNUSED
#elif defined __CSMC__
#define __SIMD32_TYPE int32_t
#define CMSIS_UNUSED
#elif defined __TASKING__
#define __SIMD32_TYPE __unaligned int32_t
#define CMSIS_UNUSED
#else
#error Unknown compiler
#endif
#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))
#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))
#define __SIMD64(addr) (*(int64_t **) & (addr))
#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
/**
* @brief definition to pack two 16 bit values.
*/
#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) & lt; & lt; 0) & (int32_t)0x0000FFFF) | \
(((int32_t)(ARG2) & lt; & lt; ARG3) & (int32_t)0xFFFF0000) )
#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) & lt; & lt; 0) & (int32_t)0xFFFF0000) | \
(((int32_t)(ARG2) & gt; & gt; ARG3) & (int32_t)0x0000FFFF) )
#endif
/**
* @brief definition to pack four 8 bit values.
*/
#ifndef ARM_MATH_BIG_ENDIAN
#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) & lt; & lt; 0) & (int32_t)0x000000FF) | \
(((int32_t)(v1) & lt; & lt; 8) & (int32_t)0x0000FF00) | \
(((int32_t)(v2) & lt; & lt; 16) & (int32_t)0x00FF0000) | \
(((int32_t)(v3) & lt; & lt; 24) & (int32_t)0xFF000000) )
#else
#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) & lt; & lt; 0) & (int32_t)0x000000FF) | \
(((int32_t)(v2) & lt; & lt; 8) & (int32_t)0x0000FF00) | \
(((int32_t)(v1) & lt; & lt; 16) & (int32_t)0x00FF0000) | \
(((int32_t)(v0) & lt; & lt; 24) & (int32_t)0xFF000000) )
#endif
/**
* @brief Clips Q63 to Q31 values.
*/
static __INLINE q31_t clip_q63_to_q31(
q63_t x)
{
return ((q31_t) (x & gt; & gt; 32) != ((q31_t) x & gt; & gt; 31)) ?
((0x7FFFFFFF ^ ((q31_t) (x & gt; & gt; 63)))) : (q31_t) x;
}
/**
* @brief Clips Q63 to Q15 values.
*/
static __INLINE q15_t clip_q63_to_q15(
q63_t x)
{
return ((q31_t) (x & gt; & gt; 32) != ((q31_t) x & gt; & gt; 31)) ?
((0x7FFF ^ ((q15_t) (x & gt; & gt; 63)))) : (q15_t) (x & gt; & gt; 15);
}
/**
* @brief Clips Q31 to Q7 values.
*/
static __INLINE q7_t clip_q31_to_q7(
q31_t x)
{
return ((q31_t) (x & gt; & gt; 24) != ((q31_t) x & gt; & gt; 23)) ?
((0x7F ^ ((q7_t) (x & gt; & gt; 31)))) : (q7_t) x;
}
/**
* @brief Clips Q31 to Q15 values.
*/
static __INLINE q15_t clip_q31_to_q15(
q31_t x)
{
return ((q31_t) (x & gt; & gt; 16) != ((q31_t) x & gt; & gt; 15)) ?
((0x7FFF ^ ((q15_t) (x & gt; & gt; 31)))) : (q15_t) x;
}
/**
* @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
*/
static __INLINE q63_t mult32x64(
q63_t x,
q31_t y)
{
return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) & gt; & gt; 32) +
(((q63_t) (x & gt; & gt; 32) * y)));
}
/*
#if defined (ARM_MATH_CM0_FAMILY) & & defined ( __CC_ARM )
#define __CLZ __clz
#endif
*/
/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */
#if defined (ARM_MATH_CM0_FAMILY) & & ((defined (__ICCARM__)) )
static __INLINE uint32_t __CLZ(
q31_t data);
static __INLINE uint32_t __CLZ(
q31_t data)
{
uint32_t count = 0;
uint32_t mask = 0x80000000;
while((data & mask) == 0)
{
count += 1u;
mask = mask & gt; & gt; 1u;
}
return (count);
}
#endif
/**
* @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
*/
static __INLINE uint32_t arm_recip_q31(
q31_t in,
q31_t * dst,
q31_t * pRecipTable)
{
q31_t out;
uint32_t tempVal;
uint32_t index, i;
uint32_t signBits;
if(in & gt; 0)
{
signBits = ((uint32_t) (__CLZ( in) - 1));
}
else
{
signBits = ((uint32_t) (__CLZ(-in) - 1));
}
/* Convert input sample to 1.31 format */
in = (in & lt; & lt; signBits);
/* calculation of index for initial approximated Val */
index = (uint32_t)(in & gt; & gt; 24);
index = (index & INDEX_MASK);
/* 1.31 with exp 1 */
out = pRecipTable[index];
/* calculation of reciprocal value */
/* running approximation for two iterations */
for (i = 0u; i & lt; 2u; i++)
{
tempVal = (uint32_t) (((q63_t) in * out) & gt; & gt; 31);
tempVal = 0x7FFFFFFFu - tempVal;
/* 1.31 with exp 1 */
/* out = (q31_t) (((q63_t) out * tempVal) & gt; & gt; 30); */
out = clip_q63_to_q31(((q63_t) out * tempVal) & gt; & gt; 30);
}
/* write output */
*dst = out;
/* return num of signbits of out = 1/in value */
return (signBits + 1u);
}
/**
* @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
*/
static __INLINE uint32_t arm_recip_q15(
q15_t in,
q15_t * dst,
q15_t * pRecipTable)
{
q15_t out = 0;
uint32_t tempVal = 0;
uint32_t index = 0, i = 0;
uint32_t signBits = 0;
if(in & gt; 0)
{
signBits = ((uint32_t)(__CLZ( in) - 17));
}
else
{
signBits = ((uint32_t)(__CLZ(-in) - 17));
}
/* Convert input sample to 1.15 format */
in = (in & lt; & lt; signBits);
/* calculation of index for initial approximated Val */
index = (uint32_t)(in & gt; & gt; 8);
index = (index & INDEX_MASK);
/* 1.15 with exp 1 */
out = pRecipTable[index];
/* calculation of reciprocal value */
/* running approximation for two iterations */
for (i = 0u; i & lt; 2u; i++)
{
tempVal = (uint32_t) (((q31_t) in * out) & gt; & gt; 15);
tempVal = 0x7FFFu - tempVal;
/* 1.15 with exp 1 */
out = (q15_t) (((q31_t) out * tempVal) & gt; & gt; 14);
/* out = clip_q31_to_q15(((q31_t) out * tempVal) & gt; & gt; 14); */
}
/* write output */
*dst = out;
/* return num of signbits of out = 1/in value */
return (signBits + 1);
}
/*
* @brief C custom defined intrinisic function for only M0 processors
*/
#if defined(ARM_MATH_CM0_FAMILY)
static __INLINE q31_t __SSAT(
q31_t x,
uint32_t y)
{
int32_t posMax, negMin;
uint32_t i;
posMax = 1;
for (i = 0; i & lt; (y - 1); i++)
{
posMax = posMax * 2;
}
if(x & gt; 0)
{
posMax = (posMax - 1);
if(x & gt; posMax)
{
x = posMax;
}
}
else
{
negMin = -posMax;
if(x & lt; negMin)
{
x = negMin;
}
}
return (x);
}
#endif /* end of ARM_MATH_CM0_FAMILY */
/*
* @brief C custom defined intrinsic function for M3 and M0 processors
*/
#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
/*
* @brief C custom defined QADD8 for M3 and M0 processors
*/
static __INLINE uint32_t __QADD8(
uint32_t x,
uint32_t y)
{
q31_t r, s, t, u;
r = __SSAT(((((q31_t)x & lt; & lt; 24) & gt; & gt; 24) + (((q31_t)y & lt; & lt; 24) & gt; & gt; 24)), 8) & (int32_t)0x000000FF;
s = __SSAT(((((q31_t)x & lt; & lt; 16) & gt; & gt; 24) + (((q31_t)y & lt; & lt; 16) & gt; & gt; 24)), 8) & (int32_t)0x000000FF;
t = __SSAT(((((q31_t)x & lt; & lt; 8) & gt; & gt; 24) + (((q31_t)y & lt; & lt; 8) & gt; & gt; 24)), 8) & (int32_t)0x000000FF;
u = __SSAT(((((q31_t)x ) & gt; & gt; 24) + (((q31_t)y ) & gt; & gt; 24)), 8) & (int32_t)0x000000FF;
return ((uint32_t)((u & lt; & lt; 24) | (t & lt; & lt; 16) | (s & lt; & lt; 8) | (r )));
}
/*
* @brief C custom defined QSUB8 for M3 and M0 processors
*/
static __INLINE uint32_t __QSUB8(
uint32_t x,
uint32_t y)
{
q31_t r, s, t, u;
r = __SSAT(((((q31_t)x & lt; & lt; 24) & gt; & gt; 24) - (((q31_t)y & lt; & lt; 24) & gt; & gt; 24)), 8) & (int32_t)0x000000FF;
s = __SSAT(((((q31_t)x & lt; & lt; 16) & gt; & gt; 24) - (((q31_t)y & lt; & lt; 16) & gt; & gt; 24)), 8) & (int32_t)0x000000FF;
t = __SSAT(((((q31_t)x & lt; & lt; 8) & gt; & gt; 24) - (((q31_t)y & lt; & lt; 8) & gt; & gt; 24)), 8) & (int32_t)0x000000FF;
u = __SSAT(((((q31_t)x ) & gt; & gt; 24) - (((q31_t)y ) & gt; & gt; 24)), 8) & (int32_t)0x000000FF;
return ((uint32_t)((u & lt; & lt; 24) | (t & lt; & lt; 16) | (s & lt; & lt; 8) | (r )));
}
/*
* @brief C custom defined QADD16 for M3 and M0 processors
*/
static __INLINE uint32_t __QADD16(
uint32_t x,
uint32_t y)
{
/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */
q31_t r = 0, s = 0;
r = __SSAT(((((q31_t)x & lt; & lt; 16) & gt; & gt; 16) + (((q31_t)y & lt; & lt; 16) & gt; & gt; 16)), 16) & (int32_t)0x0000FFFF;
s = __SSAT(((((q31_t)x ) & gt; & gt; 16) + (((q31_t)y ) & gt; & gt; 16)), 16) & (int32_t)0x0000FFFF;
return ((uint32_t)((s & lt; & lt; 16) | (r )));
}
/*
* @brief C custom defined SHADD16 for M3 and M0 processors
*/
static __INLINE uint32_t __SHADD16(
uint32_t x,
uint32_t y)
{
q31_t r, s;
r = (((((q31_t)x & lt; & lt; 16) & gt; & gt; 16) + (((q31_t)y & lt; & lt; 16) & gt; & gt; 16)) & gt; & gt; 1) & (int32_t)0x0000FFFF;
s = (((((q31_t)x ) & gt; & gt; 16) + (((q31_t)y ) & gt; & gt; 16)) & gt; & gt; 1) & (int32_t)0x0000FFFF;
return ((uint32_t)((s & lt; & lt; 16) | (r )));
}
/*
* @brief C custom defined QSUB16 for M3 and M0 processors
*/
static __INLINE uint32_t __QSUB16(
uint32_t x,
uint32_t y)
{
q31_t r, s;
r = __SSAT(((((q31_t)x & lt; & lt; 16) & gt; & gt; 16) - (((q31_t)y & lt; & lt; 16) & gt; & gt; 16)), 16) & (int32_t)0x0000FFFF;
s = __SSAT(((((q31_t)x ) & gt; & gt; 16) - (((q31_t)y ) & gt; & gt; 16)), 16) & (int32_t)0x0000FFFF;
return ((uint32_t)((s & lt; & lt; 16) | (r )));
}
/*
* @brief C custom defined SHSUB16 for M3 and M0 processors
*/
static __INLINE uint32_t __SHSUB16(
uint32_t x,
uint32_t y)
{
q31_t r, s;
r = (((((q31_t)x & lt; & lt; 16) & gt; & gt; 16) - (((q31_t)y & lt; & lt; 16) & gt; & gt; 16)) & gt; & gt; 1) & (int32_t)0x0000FFFF;
s = (((((q31_t)x ) & gt; & gt; 16) - (((q31_t)y ) & gt; & gt; 16)) & gt; & gt; 1) & (int32_t)0x0000FFFF;
return ((uint32_t)((s & lt; & lt; 16) | (r )));
}
/*
* @brief C custom defined QASX for M3 and M0 processors
*/
static __INLINE uint32_t __QASX(
uint32_t x,
uint32_t y)
{
q31_t r, s;
r = __SSAT(((((q31_t)x & lt; & lt; 16) & gt; & gt; 16) - (((q31_t)y ) & gt; & gt; 16)), 16) & (int32_t)0x0000FFFF;
s = __SSAT(((((q31_t)x ) & gt; & gt; 16) + (((q31_t)y & lt; & lt; 16) & gt; & gt; 16)), 16) & (int32_t)0x0000FFFF;
return ((uint32_t)((s & lt; & lt; 16) | (r )));
}
/*
* @brief C custom defined SHASX for M3 and M0 processors
*/
static __INLINE uint32_t __SHASX(
uint32_t x,
uint32_t y)
{
q31_t r, s;
r = (((((q31_t)x & lt; & lt; 16) & gt; & gt; 16) - (((q31_t)y ) & gt; & gt; 16)) & gt; & gt; 1) & (int32_t)0x0000FFFF;
s = (((((q31_t)x ) & gt; & gt; 16) + (((q31_t)y & lt; & lt; 16) & gt; & gt; 16)) & gt; & gt; 1) & (int32_t)0x0000FFFF;
return ((uint32_t)((s & lt; & lt; 16) | (r )));
}
/*
* @brief C custom defined QSAX for M3 and M0 processors
*/
static __INLINE uint32_t __QSAX(
uint32_t x,
uint32_t y)
{
q31_t r, s;
r = __SSAT(((((q31_t)x & lt; & lt; 16) & gt; & gt; 16) + (((q31_t)y ) & gt; & gt; 16)), 16) & (int32_t)0x0000FFFF;
s = __SSAT(((((q31_t)x ) & gt; & gt; 16) - (((q31_t)y & lt; & lt; 16) & gt; & gt; 16)), 16) & (int32_t)0x0000FFFF;
return ((uint32_t)((s & lt; & lt; 16) | (r )));
}
/*
* @brief C custom defined SHSAX for M3 and M0 processors
*/
static __INLINE uint32_t __SHSAX(
uint32_t x,
uint32_t y)
{
q31_t r, s;
r = (((((q31_t)x & lt; & lt; 16) & gt; & gt; 16) + (((q31_t)y ) & gt; & gt; 16)) & gt; & gt; 1) & (int32_t)0x0000FFFF;
s = (((((q31_t)x ) & gt; & gt; 16) - (((q31_t)y & lt; & lt; 16) & gt; & gt; 16)) & gt; & gt; 1) & (int32_t)0x0000FFFF;
return ((uint32_t)((s & lt; & lt; 16) | (r )));
}
/*
* @brief C custom defined SMUSDX for M3 and M0 processors
*/
static __INLINE uint32_t __SMUSDX(
uint32_t x,
uint32_t y)
{
return ((uint32_t)(((((q31_t)x & lt; & lt; 16) & gt; & gt; 16) * (((q31_t)y ) & gt; & gt; 16)) -
((((q31_t)x ) & gt; & gt; 16) * (((q31_t)y & lt; & lt; 16) & gt; & gt; 16)) ));
}
/*
* @brief C custom defined SMUADX for M3 and M0 processors
*/
static __INLINE uint32_t __SMUADX(
uint32_t x,
uint32_t y)
{
return ((uint32_t)(((((q31_t)x & lt; & lt; 16) & gt; & gt; 16) * (((q31_t)y ) & gt; & gt; 16)) +
((((q31_t)x ) & gt; & gt; 16) * (((q31_t)y & lt; & lt; 16) & gt; & gt; 16)) ));
}
/*
* @brief C custom defined QADD for M3 and M0 processors
*/
static __INLINE int32_t __QADD(
int32_t x,
int32_t y)
{
return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
}
/*
* @brief C custom defined QSUB for M3 and M0 processors
*/
static __INLINE int32_t __QSUB(
int32_t x,
int32_t y)
{
return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
}
/*
* @brief C custom defined SMLAD for M3 and M0 processors
*/
static __INLINE uint32_t __SMLAD(
uint32_t x,
uint32_t y,
uint32_t sum)
{
return ((uint32_t)(((((q31_t)x & lt; & lt; 16) & gt; & gt; 16) * (((q31_t)y & lt; & lt; 16) & gt; & gt; 16)) +
((((q31_t)x ) & gt; & gt; 16) * (((q31_t)y ) & gt; & gt; 16)) +
( ((q31_t)sum ) ) ));
}
/*
* @brief C custom defined SMLADX for M3 and M0 processors
*/
static __INLINE uint32_t __SMLADX(
uint32_t x,
uint32_t y,
uint32_t sum)
{
return ((uint32_t)(((((q31_t)x & lt; & lt; 16) & gt; & gt; 16) * (((q31_t)y ) & gt; & gt; 16)) +
((((q31_t)x ) & gt; & gt; 16) * (((q31_t)y & lt; & lt; 16) & gt; & gt; 16)) +
( ((q31_t)sum ) ) ));
}
/*
* @brief C custom defined SMLSDX for M3 and M0 processors
*/
static __INLINE uint32_t __SMLSDX(
uint32_t x,
uint32_t y,
uint32_t sum)
{
return ((uint32_t)(((((q31_t)x & lt; & lt; 16) & gt; & gt; 16) * (((q31_t)y ) & gt; & gt; 16)) -
((((q31_t)x ) & gt; & gt; 16) * (((q31_t)y & lt; & lt; 16) & gt; & gt; 16)) +
( ((q31_t)sum ) ) ));
}
/*
* @brief C custom defined SMLALD for M3 and M0 processors
*/
static __INLINE uint64_t __SMLALD(
uint32_t x,
uint32_t y,
uint64_t sum)
{
/* return (sum + ((q15_t) (x & gt; & gt; 16) * (q15_t) (y & gt; & gt; 16)) + ((q15_t) x * (q15_t) y)); */
return ((uint64_t)(((((q31_t)x & lt; & lt; 16) & gt; & gt; 16) * (((q31_t)y & lt; & lt; 16) & gt; & gt; 16)) +
((((q31_t)x ) & gt; & gt; 16) * (((q31_t)y ) & gt; & gt; 16)) +
( ((q63_t)sum ) ) ));
}
/*
* @brief C custom defined SMLALDX for M3 and M0 processors
*/
static __INLINE uint64_t __SMLALDX(
uint32_t x,
uint32_t y,
uint64_t sum)
{
/* return (sum + ((q15_t) (x & gt; & gt; 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y & gt; & gt; 16)); */
return ((uint64_t)(((((q31_t)x & lt; & lt; 16) & gt; & gt; 16) * (((q31_t)y ) & gt; & gt; 16)) +
((((q31_t)x ) & gt; & gt; 16) * (((q31_t)y & lt; & lt; 16) & gt; & gt; 16)) +
( ((q63_t)sum ) ) ));
}
/*
* @brief C custom defined SMUAD for M3 and M0 processors
*/
static __INLINE uint32_t __SMUAD(
uint32_t x,
uint32_t y)
{
return ((uint32_t)(((((q31_t)x & lt; & lt; 16) & gt; & gt; 16) * (((q31_t)y & lt; & lt; 16) & gt; & gt; 16)) +
((((q31_t)x ) & gt; & gt; 16) * (((q31_t)y ) & gt; & gt; 16)) ));
}
/*
* @brief C custom defined SMUSD for M3 and M0 processors
*/
static __INLINE uint32_t __SMUSD(
uint32_t x,
uint32_t y)
{
return ((uint32_t)(((((q31_t)x & lt; & lt; 16) & gt; & gt; 16) * (((q31_t)y & lt; & lt; 16) & gt; & gt; 16)) -
((((q31_t)x ) & gt; & gt; 16) * (((q31_t)y ) & gt; & gt; 16)) ));
}
/*
* @brief C custom defined SXTB16 for M3 and M0 processors
*/
static __INLINE uint32_t __SXTB16(
uint32_t x)
{
return ((uint32_t)(((((q31_t)x & lt; & lt; 24) & gt; & gt; 24) & (q31_t)0x0000FFFF) |
((((q31_t)x & lt; & lt; 8) & gt; & gt; 8) & (q31_t)0xFFFF0000) ));
}
#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
/**
* @brief Instance structure for the Q7 FIR filter.
*/
typedef struct
{
uint16_t numTaps; /** & lt; number of filter coefficients in the filter. */
q7_t *pState; /** & lt; points to the state variable array. The array is of length numTaps+blockSize-1. */
q7_t *pCoeffs; /** & lt; points to the coefficient array. The array is of length numTaps.*/
} arm_fir_instance_q7;
/**
* @brief Instance structure for the Q15 FIR filter.
*/
typedef struct
{
uint16_t numTaps; /** & lt; number of filter coefficients in the filter. */
q15_t *pState; /** & lt; points to the state variable array. The array is of length numTaps+blockSize-1. */
q15_t *pCoeffs; /** & lt; points to the coefficient array. The array is of length numTaps.*/
} arm_fir_instance_q15;
/**
* @brief Instance structure for the Q31 FIR filter.
*/
typedef struct
{
uint16_t numTaps; /** & lt; number of filter coefficients in the filter. */
q31_t *pState; /** & lt; points to the state variable array. The array is of length numTaps+blockSize-1. */
q31_t *pCoeffs; /** & lt; points to the coefficient array. The array is of length numTaps. */
} arm_fir_instance_q31;
/**
* @brief Instance structure for the floating-point FIR filter.
*/
typedef struct
{
uint16_t numTaps; /** & lt; number of filter coefficients in the filter. */
float32_t *pState; /** & lt; points to the state variable array. The array is of length numTaps+blockSize-1. */
float32_t *pCoeffs; /** & lt; points to the coefficient array. The array is of length numTaps. */
} arm_fir_instance_f32;
/**
* @brief Processing function for the Q7 FIR filter.
* @param[in] S points to an instance of the Q7 FIR filter structure.
* @param[in] pSrc points to the block of input data.
* @param[out] pDst points to the block of output data.
* @param[in] blockSize number of samples to process.
*/
void arm_fir_q7(
const arm_fir_instance_q7 * S,
q7_t * pSrc,
q7_t * pDst,
uint32_t blockSize);
/**
* @brief Initialization function for the Q7 FIR filter.
* @param[in,out] S points to an instance of the Q7 FIR structure.
* @param[in] numTaps Number of filter coefficients in the filter.
* @param[in] pCoeffs points to the filter coefficients.
* @param[in] pState points to the state buffer.
* @param[in] blockSize number of samples that are processed.
*/
void arm_fir_init_q7(
arm_fir_instance_q7 * S,
uint16_t numTaps,
q7_t * pCoeffs,
q7_t * pState,
uint32_t blockSize);
/**
* @brief Processing function for the Q15 FIR filter.
* @param[in] S points to an instance of the Q15 FIR structure.
* @param[in] pSrc points to the block of input data.
* @param[out] pDst points to the block of output data.
* @param[in] blockSize number of samples to process.
*/
void arm_fir_q15(
const arm_fir_instance_q15 * S,
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
/**
* @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
* @param[in] S points to an instance of the Q15 FIR filter structure.
* @param[in] pSrc points to the block of input data.
* @param[out] pDst points to the block of output data.
* @param[in] blockSize number of samples to process.
*/
void arm_fir_fast_q15(
const arm_fir_instance_q15 * S,
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
/**
* @brief Initialization function for the Q15 FIR filter.
* @param[in,out] S points to an instance of the Q15 FIR filter structure.
* @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
* @param[in] pCoeffs points to the filter coefficients.
* @param[in] pState points to the state buffer.
* @param[in] blockSize number of samples that are processed at a time.
* @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
* & lt; code & gt; numTaps & lt; /code & gt; is not a supported value.
*/
arm_status arm_fir_init_q15(
arm_fir_instance_q15 * S,
uint16_t numTaps,
q15_t * pCoeffs,
q15_t * pState,
uint32_t blockSize);
/**
* @brief Processing function for the Q31 FIR filter.
* @param[in] S points to an instance of the Q31 FIR filter structure.
* @param[in] pSrc points to the block of input data.
* @param[out] pDst points to the block of output data.
* @param[in] blockSize number of samples to process.
*/
void arm_fir_q31(
const arm_fir_instance_q31 * S,
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
/**
* @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
* @param[in] S points to an instance of the Q31 FIR structure.
* @param[in] pSrc points to the block of input data.
* @param[out] pDst points to the block of output data.
* @param[in] blockSize number of samples to process.
*/
void arm_fir_fast_q31(
const arm_fir_instance_q31 * S,
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
/**
* @brief Initialization function for the Q31 FIR filter.
* @param[in,out] S points to an instance of the Q31 FIR structure.
* @param[in] numTaps Number of filter coefficients in the filter.
* @param[in] pCoeffs points to the filter coefficients.
* @param[in] pState points to the state buffer.
* @param[in] blockSize number of samples that are processed at a time.
*/
void arm_fir_init_q31(
arm_fir_instance_q31 * S,
uint16_t numTaps,
q31_t * pCoeffs,
q31_t * pState,
uint32_t blockSize);
/**
* @brief Processing function for the floating-point FIR filter.
* @param[in] S points to an instance of the floating-point FIR structure.
* @param[in] pSrc points to the block of input data.
* @param[out] pDst points to the block of output data.
* @param[in] blockSize number of samples to process.
*/
void arm_fir_f32(
const arm_fir_instance_f32 * S,
float32_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
/**
* @brief Initialization function for the floating-point FIR filter.
* @param[in,out] S points to an instance of the floating-point FIR filter structure.
* @param[in] numTaps Number of filter coefficients in the filter.
* @param[in] pCoeffs points to the filter coefficients.
* @param[in] pState points to the state buffer.
* @param[in] blockSize number of samples that are processed at a time.
*/
void arm_fir_init_f32(
arm_fir_instance_f32 * S,
uint16_t numTaps,
float32_t * pCoeffs,
float32_t * pState,
uint32_t blockSize);
/**
* @brief Instance structure for the Q15 Biquad cascade filter.
*/
typedef struct
{
int8_t numStages; /** & lt; number of 2nd order stages in the filter. Overall order is 2*numStages. */
q15_t *pState; /** & lt; Points to the array of state coefficients. The array is of length 4*numStages. */
q15_t *pCoeffs; /** & lt; Points to the array of coefficients. The array is of length 5*numStages. */
int8_t postShift; /** & lt; Additional shift, in bits, applied to each output sample. */
} arm_biquad_casd_df1_inst_q15;
/**
* @brief Instance structure for the Q31 Biquad cascade filter.
*/
typedef struct
{
uint32_t numStages; /** & lt; number of 2nd order stages in the filter. Overall order is 2*numStages. */
q31_t *pState; /** & lt; Points to the array of state coefficients. The array is of length 4*numStages. */
q31_t *pCoeffs; /** & lt; Points to the array of coefficients. The array is of length 5*numStages. */
uint8_t postShift; /** & lt; Additional shift, in bits, applied to each output sample. */
} arm_biquad_casd_df1_inst_q31;
/**
* @brief Instance structure for the floating-point Biquad cascade filter.
*/
typedef struct
{
uint32_t numStages; /** & lt; number of 2nd order stages in the filter. Overall order is 2*numStages. */
float32_t *pState; /** & lt; Points to the array of state coefficients. The array is of length 4*numStages. */
float32_t *pCoeffs; /** & lt; Points to the array of coefficients. The array is of length 5*numStages. */
} arm_biquad_casd_df1_inst_f32;
/**
* @brief Processing function for the Q15 Biquad cascade filter.
* @param[in] S points to an instance of the Q15 Biquad cascade structure.
* @param[in] pSrc points to the block of input data.
* @param[out] pDst points to the block of output data.
* @param[in] blockSize number of samples to process.
*/
void arm_biquad_cascade_df1_q15(
const arm_biquad_casd_df1_inst_q15 * S,
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
/**
* @brief Initialization function for the Q15 Biquad cascade filter.
* @param[in,out] S points to an instance of the Q15 Biquad cascade structure.
* @param[in] numStages number of 2nd order stages in the filter.
* @param[in] pCoeffs points to the filter coefficients.
* @param[in] pState points to the state buffer.
* @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
*/
void arm_biquad_cascade_df1_init_q15(
arm_biquad_casd_df1_inst_q15 * S,
uint8_t numStages,
q15_t * pCoeffs,
q15_t * pState,
int8_t postShift);
/**
* @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
* @param[in] S points to an instance of the Q15 Biquad cascade structure.
* @param[in] pSrc points to the block of input data.
* @param[out] pDst points to the block of output data.
* @param[in] blockSize number of samples to process.
*/
void arm_biquad_cascade_df1_fast_q15(
const arm_biquad_casd_df1_inst_q15 * S,
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
/**
* @brief Processing function for the Q31 Biquad cascade filter
* @param[in] S points to an instance of the Q31 Biquad cascade structure.
* @param[in] pSrc points to the block of input data.
* @param[out] pDst points to the block of output data.
* @param[in] blockSize number of samples to process.
*/
void arm_biquad_cascade_df1_q31(
const arm_biquad_casd_df1_inst_q31 * S,
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
/**
* @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
* @param[in] S points to an instance of the Q31 Biquad cascade structure.
* @param[in] pSrc points to the block of input data.
* @param[out] pDst points to the block of output data.
* @param[in] blockSize number of samples to process.
*/
void arm_biquad_cascade_df1_fast_q31(
const arm_biquad_casd_df1_inst_q31 * S,
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
/**
* @brief Initialization function for the Q31 Biquad cascade filter.
* @param[in,out] S points to an instance of the Q31 Biquad cascade structure.
* @param[in] numStages number of 2nd order stages in the filter.
* @param[in] pCoeffs points to the filter coefficients.
* @param[in] pState points to the state buffer.
* @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
*/
void arm_biquad_cascade_df1_init_q31(
arm_biquad_casd_df1_inst_q31 * S,
uint8_t numStages,
q31_t * pCoeffs,
q31_t * pState,
int8_t postShift);
/**
* @brief Processing function for the floating-point Biquad cascade filter.
* @param[in] S points to an instance of the floating-point Biquad cascade structure.
* @param[in] pSrc points to the block of input data.
* @param[out] pDst points to the block of output data.
* @param[in] blockSize number of samples to process.
*/
void arm_biquad_cascade_df1_f32(
const arm_biquad_casd_df1_inst_f32 * S,
float32_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
/**
* @brief Initialization function for the floating-point Biquad cascade filter.
* @param[in,out] S points to an instance of the floating-point Biquad cascade structure.
* @param[in] numStages number of 2nd order stages in the filter.
* @param[in] pCoeffs points to the filter coefficients.
* @param[in] pState points to the state buffer.
*/
void arm_biquad_cascade_df1_init_f32(
arm_biquad_casd_df1_inst_f32 * S,
uint8_t numStages,
float32_t * pCoeffs,
float32_t * pState);
/**
* @brief Instance structure for the floating-point matrix structure.
*/
typedef struct
{
uint16_t numRows; /** & lt; number of rows of the matrix. */
uint16_t numCols; /** & lt; number of columns of the matrix. */
float32_t *pData; /** & lt; points to the data of the matrix. */
} arm_matrix_instance_f32;
/**
* @brief Instance structure for the floating-point matrix structure.
*/
typedef struct
{
uint16_t numRows; /** & lt; number of rows of the matrix. */
uint16_t numCols; /** & lt; number of columns of the matrix. */
float64_t *pData; /** & lt; points to the data of the matrix. */
} arm_matrix_instance_f64;
/**
* @brief Instance structure for the Q15 matrix structure.
*/
typedef struct
{
uint16_t numRows; /** & lt; number of rows of the matrix. */
uint16_t numCols; /** & lt; number of columns of the matrix. */
q15_t *pData; /** & lt; points to the data of the matrix. */
} arm_matrix_instance_q15;
/**
* @brief Instance structure for the Q31 matrix structure.
*/
typedef struct
{
uint16_t numRows; /** & lt; number of rows of the matrix. */
uint16_t numCols; /** & lt; number of columns of the matrix. */
q31_t *pData; /** & lt; points to the data of the matrix. */
} arm_matrix_instance_q31;
/**
* @brief Floating-point matrix addition.
* @param[in] pSrcA points to the first input matrix structure
* @param[in] pSrcB points to the second input matrix structure
* @param[out] pDst points to output matrix structure
* @return The function returns either
* & lt; code & gt; ARM_MATH_SIZE_MISMATCH & lt; /code & gt; or & lt; code & gt; ARM_MATH_SUCCESS & lt; /code & gt; based on the outcome of size checking.
*/
arm_status arm_mat_add_f32(
const arm_matrix_instance_f32 * pSrcA,
const arm_matrix_instance_f32 * pSrcB,
arm_matrix_instance_f32 * pDst);
/**
* @brief Q15 matrix addition.
* @param[in] pSrcA points to the first input matrix structure
* @param[in] pSrcB points to the second input matrix structure
* @param[out] pDst points to output matrix structure
* @return The function returns either
* & lt; code & gt; ARM_MATH_SIZE_MISMATCH & lt; /code & gt; or & lt; code & gt; ARM_MATH_SUCCESS & lt; /code & gt; based on the outcome of size checking.
*/
arm_status arm_mat_add_q15(
const arm_matrix_instance_q15 * pSrcA,
const arm_matrix_instance_q15 * pSrcB,
arm_matrix_instance_q15 * pDst);
/**
* @brief Q31 matrix addition.
* @param[in] pSrcA points to the first input matrix structure
* @param[in] pSrcB points to the second input matrix structure
* @param[out] pDst points to output matrix structure
* @return The function returns either
* & lt; code & gt; ARM_MATH_SIZE_MISMATCH & lt; /code & gt; or & lt; code & gt; ARM_MATH_SUCCESS & lt; /code & gt; based on the outcome of size checking.
*/
arm_status arm_mat_add_q31(
const arm_matrix_instance_q31 * pSrcA,
const arm_matrix_instance_q31 * pSrcB,
arm_matrix_instance_q31 * pDst);
/**
* @brief Floating-point, complex, matrix multiplication.
* @param[in] pSrcA points to the first input matrix structure
* @param[in] pSrcB points to the second input matrix structure
* @param[out] pDst points to output matrix structure
* @return The function returns either
* & lt; code & gt; ARM_MATH_SIZE_MISMATCH & lt; /code & gt; or & lt; code & gt; ARM_MATH_SUCCESS & lt; /code & gt; based on the outcome of size checking.
*/
arm_status arm_mat_cmplx_mult_f32(
const arm_matrix_instance_f32 * pSrcA,
const arm_matrix_instance_f32 * pSrcB,
arm_matrix_instance_f32 * pDst);
/**
* @brief Q15, complex, matrix multiplication.
* @param[in] pSrcA points to the first input matrix structure
* @param[in] pSrcB points to the second input matrix structure
* @param[out] pDst points to output matrix structure
* @return The function returns either
* & lt; code & gt; ARM_MATH_SIZE_MISMATCH & lt; /code & gt; or & lt; code & gt; ARM_MATH_SUCCESS & lt; /code & gt; based on the outcome of size checking.
*/
arm_status arm_mat_cmplx_mult_q15(
const arm_matrix_instance_q15 * pSrcA,
const arm_matrix_instance_q15 * pSrcB,
arm_matrix_instance_q15 * pDst,
q15_t * pScratch);
/**
* @brief Q31, complex, matrix multiplication.
* @param[in] pSrcA points to the first input matrix structure
* @param[in] pSrcB points to the second input matrix structure
* @param[out] pDst points to output matrix structure
* @return The function returns either
* & lt; code & gt; ARM_MATH_SIZE_MISMATCH & lt; /code & gt; or & lt; code & gt; ARM_MATH_SUCCESS & lt; /code & gt; based on the outcome of size checking.
*/
arm_status arm_mat_cmplx_mult_q31(
const arm_matrix_instance_q31 * pSrcA,
const arm_matrix_instance_q31 * pSrcB,
arm_matrix_instance_q31 * pDst);
/**
* @brief Floating-point matrix transpose.
* @param[in] pSrc points to the input matrix
* @param[out] pDst points to the output matrix
* @return The function returns either & lt; code & gt; ARM_MATH_SIZE_MISMATCH & lt; /code & gt;
* or & lt; code & gt; ARM_MATH_SUCCESS & lt; /code & gt; based on the outcome of size checking.
*/
arm_status arm_mat_trans_f32(
const arm_matrix_instance_f32 * pSrc,
arm_matrix_instance_f32 * pDst);
/**
* @brief Q15 matrix transpose.
* @param[in] pSrc points to the input matrix
* @param[out] pDst points to the output matrix
* @return The function returns either & lt; code & gt; ARM_MATH_SIZE_MISMATCH & lt; /code & gt;
* or & lt; code & gt; ARM_MATH_SUCCESS & lt; /code & gt; based on the outcome of size checking.
*/
arm_status arm_mat_trans_q15(
const arm_matrix_instance_q15 * pSrc,
arm_matrix_instance_q15 * pDst);
/**
* @brief Q31 matrix transpose.
* @param[in] pSrc points to the input matrix
* @param[out] pDst points to the output matrix
* @return The function returns either & lt; code & gt; ARM_MATH_SIZE_MISMATCH & lt; /code & gt;
* or & lt; code & gt; ARM_MATH_SUCCESS & lt; /code & gt; based on the outcome of size checking.
*/
arm_status arm_mat_trans_q31(
const arm_matrix_instance_q31 * pSrc,
arm_matrix_instance_q31 * pDst);
/**
* @brief Floating-point matrix multiplication
* @param[in] pSrcA points to the first input matrix structure
* @param[in] pSrcB points to the second input matrix structure
* @param[out] pDst points to output matrix structure
* @return The function returns either
* & lt; code & gt; ARM_MATH_SIZE_MISMATCH & lt; /code & gt; or & lt; code & gt; ARM_MATH_SUCCESS & lt; /code & gt; based on the outcome of size checking.
*/
arm_status arm_mat_mult_f32(
const arm_matrix_instance_f32 * pSrcA,
const arm_matrix_instance_f32 * pSrcB,
arm_matrix_instance_f32 * pDst);
/**
* @brief Q15 matrix multiplication
* @param[in] pSrcA points to the first input matrix structure
* @param[in] pSrcB points to the second input matrix structure
* @param[out] pDst points to output matrix structure
* @param[in] pState points to the array for storing intermediate results
* @return The function returns either
* & lt; code & gt; ARM_MATH_SIZE_MISMATCH & lt; /code & gt; or & lt; code & gt; ARM_MATH_SUCCESS & lt; /code & gt; based on the outcome of size checking.
*/
arm_status arm_mat_mult_q15(
const arm_matrix_instance_q15 * pSrcA,
const arm_matrix_instance_q15 * pSrcB,
arm_matrix_instance_q15 * pDst,
q15_t * pState);
/**
* @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
* @param[in] pSrcA points to the first input matrix structure
* @param[in] pSrcB points to the second input matrix structure
* @param[out] pDst points to output matrix structure
* @param[in] pState points to the array for storing intermediate results
* @return The function returns either
* & lt; code & gt; ARM_MATH_SIZE_MISMATCH & lt; /code & gt; or & lt; code & gt; ARM_MATH_SUCCESS & lt; /code & gt; based on the outcome of size checking.
*/
arm_status arm_mat_mult_fast_q15(
const arm_matrix_instance_q15 * pSrcA,
const arm_matrix_instance_q15 * pSrcB,
arm_matrix_instance_q15 * pDst,
q15_t * pState);
/**
* @brief Q31 matrix multiplication
* @param[in] pSrcA points to the first input matrix structure
* @param[in] pSrcB points to the second input matrix structure
* @param[out] pDst points to output matrix structure
* @return The function returns either
* & lt; code & gt; ARM_MATH_SIZE_MISMATCH & lt; /code & gt; or & lt; code & gt; ARM_MATH_SUCCESS & lt; /code & gt; based on the outcome of size checking.
*/
arm_status arm_mat_mult_q31(
const arm_matrix_instance_q31 * pSrcA,
const arm_matrix_instance_q31 * pSrcB,
arm_matrix_instance_q31 * pDst);
/**
* @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
* @param[in] pSrcA points to the first input matrix structure
* @param[in] pSrcB points to the second input matrix structure
* @param[out] pDst points to output matrix structure
* @return The function returns either
* & lt; code & gt; ARM_MATH_SIZE_MISMATCH & lt; /code & gt; or & lt; code & gt; ARM_MATH_SUCCESS & lt; /code & gt; based on the outcome of size checking.
*/
arm_status arm_mat_mult_fast_q31(
const arm_matrix_instance_q31 * pSrcA,
const arm_matrix_instance_q31 * pSrcB,
arm_matrix_instance_q31 * pDst);
/**
* @brief Floating-point matrix subtraction
* @param[in] pSrcA points to the first input matrix structure
* @param[in] pSrcB points to the second input matrix structure
* @param[out] pDst points to output matrix structure
* @return The function returns either
* & lt; code & gt; ARM_MATH_SIZE_MISMATCH & lt; /code & gt; or & lt; code & gt; ARM_MATH_SUCCESS & lt; /code & gt; based on the outcome of size checking.
*/
arm_status arm_mat_sub_f32(
const arm_matrix_instance_f32 * pSrcA,
const arm_matrix_instance_f32 * pSrcB,
arm_matrix_instance_f32 * pDst);
/**
* @brief Q15 matrix subtraction
* @param[in] pSrcA points to the first input matrix structure
* @param[in] pSrcB points to the second input matrix structure
* @param[out] pDst points to output matrix structure
* @return The function returns either
* & lt; code & gt; ARM_MATH_SIZE_MISMATCH & lt; /code & gt; or & lt; code & gt; ARM_MATH_SUCCESS & lt; /code & gt; based on the outcome of size checking.
*/
arm_status arm_mat_sub_q15(
const arm_matrix_instance_q15 * pSrcA,
const arm_matrix_instance_q15 * pSrcB,
arm_matrix_instance_q15 * pDst);
/**
* @brief Q31 matrix subtraction
* @param[in] pSrcA points to the first input matrix structure
* @param[in] pSrcB points to the second input matrix structure
* @param[out] pDst points to output matrix structure
* @return The function returns either
* & lt; code & gt; ARM_MATH_SIZE_MISMATCH & lt; /code & gt; or & lt; code & gt; ARM_MATH_SUCCESS & lt; /code & gt; based on the outcome of size checking.
*/
arm_status arm_mat_sub_q31(
const arm_matrix_instance_q31 * pSrcA,
const arm_matrix_instance_q31 * pSrcB,
arm_matrix_instance_q31 * pDst);
/**
* @brief Floating-point matrix scaling.
* @param[in] pSrc points to the input matrix
* @param[in] scale scale factor
* @param[out] pDst points to the output matrix
* @return The function returns either
* & lt; code & gt; ARM_MATH_SIZE_MISMATCH & lt; /code & gt; or & lt; code & gt; ARM_MATH_SUCCESS & lt; /code & gt; based on the outcome of size checking.
*/
arm_status arm_mat_scale_f32(
const arm_matrix_instance_f32 * pSrc,
float32_t scale,
arm_matrix_instance_f32 * pDst);
/**
* @brief Q15 matrix scaling.
* @param[in] pSrc points to input matrix
* @param[in] scaleFract fractional portion of the scale factor
* @param[in] shift number of bits to shift the result by
* @param[out] pDst points to output matrix
* @return The function returns either
* & lt; code & gt; ARM_MATH_SIZE_MISMATCH & lt; /code & gt; or & lt; code & gt; ARM_MATH_SUCCESS & lt; /code & gt; based on the outcome of size checking.
*/
arm_status arm_mat_scale_q15(
const arm_matrix_instance_q15 * pSrc,
q15_t scaleFract,
int32_t shift,
arm_matrix_instance_q15 * pDst);
/**
* @brief Q31 matrix scaling.
* @param[in] pSrc points to input matrix
* @param[in] scaleFract fractional portion of the scale factor
* @param[in] shift number of bits to shift the result by
* @param[out] pDst points to output matrix structure
* @return The function returns either
* & lt; code & gt; ARM_MATH_SIZE_MISMATCH & lt; /code & gt; or & lt; code & gt; ARM_MATH_SUCCESS & lt; /code & gt; based on the outcome of size checking.
*/
arm_status arm_mat_scale_q31(
const arm_matrix_instance_q31 * pSrc,
q31_t scaleFract,
int32_t shift,
arm_matrix_instance_q31 * pDst);
/**
* @brief Q31 matrix initialization.
* @param[in,out] S points to an instance of the floating-point matrix structure.
* @param[in] nRows number of rows in the matrix.
* @param[in] nColumns number of columns in the matrix.
* @param[in] pData points to the matrix data array.
*/
void arm_mat_init_q31(
arm_matrix_instance_q31 * S,
uint16_t nRows,
uint16_t nColumns,
q31_t * pData);
/**
* @brief Q15 matrix initialization.
* @param[in,out] S points to an instance of the floating-point matrix structure.
* @param[in] nRows number of rows in the matrix.
* @param[in] nColumns number of columns in the matrix.
* @param[in] pData points to the matrix data array.
*/
void arm_mat_init_q15(
arm_matrix_instance_q15 * S,
uint16_t nRows,
uint16_t nColumns,
q15_t * pData);
/**
* @brief Floating-point matrix initialization.
* @param[in,out] S points to an instance of the floating-point matrix structure.
* @param[in] nRows number of rows in the matrix.
* @param[in] nColumns number of columns in the matrix.
* @param[in] pData points to the matrix data array.
*/
void arm_mat_init_f32(
arm_matrix_instance_f32 * S,
uint16_t nRows,
uint16_t nColumns,
float32_t * pData);
/**
* @brief Instance structure for the Q15 PID Control.
*/
typedef struct
{
q15_t A0; /** & lt; The derived gain, A0 = Kp + Ki + Kd . */
#ifdef ARM_MATH_CM0_FAMILY
q15_t A1;
q15_t A2;
#else
q31_t A1; /** & lt; The derived gain A1 = -Kp - 2Kd | Kd.*/
#endif
q15_t state[3]; /** & lt; The state array of length 3. */
q15_t Kp; /** & lt; The proportional gain. */
q15_t Ki; /** & lt; The integral gain. */
q15_t Kd; /** & lt; The derivative gain. */
} arm_pid_instance_q15;
/**
* @brief Instance structure for the Q31 PID Control.
*/
typedef struct
{
q31_t A0; /** & lt; The derived gain, A0 = Kp + Ki + Kd . */
q31_t A1; /** & lt; The derived gain, A1 = -Kp - 2Kd. */
q31_t A2; /** & lt; The derived gain, A2 = Kd . */
q31_t state[3]; /** & lt; The state array of length 3. */
q31_t Kp; /** & lt; The proportional gain. */
q31_t Ki; /** & lt; The integral gain. */
q31_t Kd; /** & lt; The derivative gain. */
} arm_pid_instance_q31;
/**
* @brief Instance structure for the floating-point PID Control.
*/
typedef struct
{
float32_t A0; /** & lt; The derived gain, A0 = Kp + Ki + Kd . */
float32_t A1; /** & lt; The derived gain, A1 = -Kp - 2Kd. */
float32_t A2; /** & lt; The derived gain, A2 = Kd . */
float32_t state[3]; /** & lt; The state array of length 3. */
float32_t Kp; /** & lt; The proportional gain. */
float32_t Ki; /** & lt; The integral gain. */
float32_t Kd; /** & lt; The derivative gain. */
} arm_pid_instance_f32;
/**
* @brief Initialization function for the floating-point PID Control.
* @param[in,out] S points to an instance of the PID structure.
* @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
*/
void arm_pid_init_f32(
arm_pid_instance_f32 * S,
int32_t resetStateFlag);
/**
* @brief Reset function for the floating-point PID Control.
* @param[in,out] S is an instance of the floating-point PID Control structure
*/
void arm_pid_reset_f32(
arm_pid_instance_f32 * S);
/**
* @brief Initialization function for the Q31 PID Control.
* @param[in,out] S points to an instance of the Q15 PID structure.
* @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
*/
void arm_pid_init_q31(
arm_pid_instance_q31 * S,
int32_t resetStateFlag);
/**
* @brief Reset function for the Q31 PID Control.
* @param[in,out] S points to an instance of the Q31 PID Control structure
*/
void arm_pid_reset_q31(
arm_pid_instance_q31 * S);
/**
* @brief Initialization function for the Q15 PID Control.
* @param[in,out] S points to an instance of the Q15 PID structure.
* @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
*/
void arm_pid_init_q15(
arm_pid_instance_q15 * S,
int32_t resetStateFlag);
/**
* @brief Reset function for the Q15 PID Control.
* @param[in,out] S points to an instance of the q15 PID Control structure
*/
void arm_pid_reset_q15(
arm_pid_instance_q15 * S);
/**
* @brief Instance structure for the floating-point Linear Interpolate function.
*/
typedef struct
{
uint32_t nValues; /** & lt; nValues */
float32_t x1; /** & lt; x1 */
float32_t xSpacing; /** & lt; xSpacing */
float32_t *pYData; /** & lt; pointer to the table of Y values */
} arm_linear_interp_instance_f32;
/**
* @brief Instance structure for the floating-point bilinear interpolation function.
*/
typedef struct
{
uint16_t numRows; /** & lt; number of rows in the data table. */
uint16_t numCols; /** & lt; number of columns in the data table. */
float32_t *pData; /** & lt; points to the data table. */
} arm_bilinear_interp_instance_f32;
/**
* @brief Instance structure for the Q31 bilinear interpolation function.
*/
typedef struct
{
uint16_t numRows; /** & lt; number of rows in the data table. */
uint16_t numCols; /** & lt; number of columns in the data table. */
q31_t *pData; /** & lt; points to the data table. */
} arm_bilinear_interp_instance_q31;
/**
* @brief Instance structure for the Q15 bilinear interpolation function.
*/
typedef struct
{
uint16_t numRows; /** & lt; number of rows in the data table. */
uint16_t numCols; /** & lt; number of columns in the data table. */
q15_t *pData; /** & lt; points to the data table. */
} arm_bilinear_interp_instance_q15;
/**
* @brief Instance structure for the Q15 bilinear interpolation function.
*/
typedef struct
{
uint16_t numRows; /** & lt; number of rows in the data table. */
uint16_t numCols; /** & lt; number of columns in the data table. */
q7_t *pData; /** & lt; points to the data table. */
} arm_bilinear_interp_instance_q7;
/**
* @brief Q7 vector multiplication.
* @param[in] pSrcA points to the first input vector
* @param[in] pSrcB points to the second input vector
* @param[out] pDst points to the output vector
* @param[in] blockSize number of samples in each vector
*/
void arm_mult_q7(
q7_t * pSrcA,
q7_t * pSrcB,
q7_t * pDst,
uint32_t blockSize);
/**
* @brief Q15 vector multiplication.
* @param[in] pSrcA points to the first input vector
* @param[in] pSrcB points to the second input vector
* @param[out] pDst points to the output vector
* @param[in] blockSize number of samples in each vector
*/
void arm_mult_q15(
q15_t * pSrcA,
q15_t * pSrcB,
q15_t * pDst,
uint32_t blockSize);
/**
* @brief Q31 vector multiplication.
* @param[in] pSrcA points to the first input vector
* @param[in] pSrcB points to the second input vector
* @param[out] pDst points to the output vector
* @param[in] blockSize number of samples in each vector
*/
void arm_mult_q31(
q31_t * pSrcA,
q31_t * pSrcB,
q31_t * pDst,
uint32_t blockSize);
/**
* @brief Floating-point vector multiplication.
* @param[in] pSrcA points to the first input vector
* @param[in] pSrcB points to the second input vector
* @param[out] pDst points to the output vector
* @param[in] blockSize number of samples in each vector
*/
void arm_mult_f32(
float32_t * pSrcA,
float32_t * pSrcB,
float32_t * pDst,
uint32_t blockSize);
/**
* @brief Instance structure for the Q15 CFFT/CIFFT function.
*/
typedef struct
{
uint16_t fftLen; /** & lt; length of the FFT. */
uint8_t ifftFlag; /** & lt; flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
uint8_t bitReverseFlag; /** & lt; flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
q15_t *pTwiddle; /** & lt; points to the Sin twiddle factor table. */
uint16_t *pBitRevTable; /** & lt; points to the bit reversal table. */
uint16_t twidCoefModifier; /** & lt; twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
uint16_t bitRevFactor; /** & lt; bit reversal modifier that supports different size FFTs with the same bit reversal table. */
} arm_cfft_radix2_instance_q15;
/* Deprecated */
arm_status arm_cfft_radix2_init_q15(
arm_cfft_radix2_instance_q15 * S,
uint16_t fftLen,
uint8_t ifftFlag,
uint8_t bitReverseFlag);
/* Deprecated */
void arm_cfft_radix2_q15(
const arm_cfft_radix2_instance_q15 * S,
q15_t * pSrc);
/**
* @brief Instance structure for the Q15 CFFT/CIFFT function.
*/
typedef struct
{
uint16_t fftLen; /** & lt; length of the FFT. */
uint8_t ifftFlag; /** & lt; flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
uint8_t bitReverseFlag; /** & lt; flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
q15_t *pTwiddle; /** & lt; points to the twiddle factor table. */
uint16_t *pBitRevTable; /** & lt; points to the bit reversal table. */
uint16_t twidCoefModifier; /** & lt; twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
uint16_t bitRevFactor; /** & lt; bit reversal modifier that supports different size FFTs with the same bit reversal table. */
} arm_cfft_radix4_instance_q15;
/* Deprecated */
arm_status arm_cfft_radix4_init_q15(
arm_cfft_radix4_instance_q15 * S,
uint16_t fftLen,
uint8_t ifftFlag,
uint8_t bitReverseFlag);
/* Deprecated */
void arm_cfft_radix4_q15(
const arm_cfft_radix4_instance_q15 * S,
q15_t * pSrc);
/**
* @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
*/
typedef struct
{
uint16_t fftLen; /** & lt; length of the FFT. */
uint8_t ifftFlag; /** & lt; flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
uint8_t bitReverseFlag; /** & lt; flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
q31_t *pTwiddle; /** & lt; points to the Twiddle factor table. */
uint16_t *pBitRevTable; /** & lt; points to the bit reversal table. */
uint16_t twidCoefModifier; /** & lt; twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
uint16_t bitRevFactor; /** & lt; bit reversal modifier that supports different size FFTs with the same bit reversal table. */
} arm_cfft_radix2_instance_q31;
/* Deprecated */
arm_status arm_cfft_radix2_init_q31(
arm_cfft_radix2_instance_q31 * S,
uint16_t fftLen,
uint8_t ifftFlag,
uint8_t bitReverseFlag);
/* Deprecated */
void arm_cfft_radix2_q31(
const arm_cfft_radix2_instance_q31 * S,
q31_t * pSrc);
/**
* @brief Instance structure for the Q31 CFFT/CIFFT function.
*/
typedef struct
{
uint16_t fftLen; /** & lt; length of the FFT. */
uint8_t ifftFlag; /** & lt; flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
uint8_t bitReverseFlag; /** & lt; flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
q31_t *pTwiddle; /** & lt; points to the twiddle factor table. */
uint16_t *pBitRevTable; /** & lt; points to the bit reversal table. */
uint16_t twidCoefModifier; /** & lt; twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
uint16_t bitRevFactor; /** & lt; bit reversal modifier that supports different size FFTs with the same bit reversal table. */
} arm_cfft_radix4_instance_q31;
/* Deprecated */
void arm_cfft_radix4_q31(
const arm_cfft_radix4_instance_q31 * S,
q31_t * pSrc);
/* Deprecated */
arm_status arm_cfft_radix4_init_q31(
arm_cfft_radix4_instance_q31 * S,
uint16_t fftLen,
uint8_t ifftFlag,
uint8_t bitReverseFlag);
/**
* @brief Instance structure for the floating-point CFFT/CIFFT function.
*/
typedef struct
{
uint16_t fftLen; /** & lt; length of the FFT. */
uint8_t ifftFlag; /** & lt; flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
uint8_t bitReverseFlag; /** & lt; flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
float32_t *pTwiddle; /** & lt; points to the Twiddle factor table. */
uint16_t *pBitRevTable; /** & lt; points to the bit reversal table. */
uint16_t twidCoefModifier; /** & lt; twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
uint16_t bitRevFactor; /** & lt; bit reversal modifier that supports different size FFTs with the same bit reversal table. */
float32_t onebyfftLen; /** & lt; value of 1/fftLen. */
} arm_cfft_radix2_instance_f32;
/* Deprecated */
arm_status arm_cfft_radix2_init_f32(
arm_cfft_radix2_instance_f32 * S,
uint16_t fftLen,
uint8_t ifftFlag,
uint8_t bitReverseFlag);
/* Deprecated */
void arm_cfft_radix2_f32(
const arm_cfft_radix2_instance_f32 * S,
float32_t * pSrc);
/**
* @brief Instance structure for the floating-point CFFT/CIFFT function.
*/
typedef struct
{
uint16_t fftLen; /** & lt; length of the FFT. */
uint8_t ifftFlag; /** & lt; flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
uint8_t bitReverseFlag; /** & lt; flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
float32_t *pTwiddle; /** & lt; points to the Twiddle factor table. */
uint16_t *pBitRevTable; /** & lt; points to the bit reversal table. */
uint16_t twidCoefModifier; /** & lt; twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
uint16_t bitRevFactor; /** & lt; bit reversal modifier that supports different size FFTs with the same bit reversal table. */
float32_t onebyfftLen; /** & lt; value of 1/fftLen. */
} arm_cfft_radix4_instance_f32;
/* Deprecated */
arm_status arm_cfft_radix4_init_f32(
arm_cfft_radix4_instance_f32 * S,
uint16_t fftLen,
uint8_t ifftFlag,
uint8_t bitReverseFlag);
/* Deprecated */
void arm_cfft_radix4_f32(
const arm_cfft_radix4_instance_f32 * S,
float32_t * pSrc);
/**
* @brief Instance structure for the fixed-point CFFT/CIFFT function.
*/
typedef struct
{
uint16_t fftLen; /** & lt; length of the FFT. */
const q15_t *pTwiddle; /** & lt; points to the Twiddle factor table. */
const uint16_t *pBitRevTable; /** & lt; points to the bit reversal table. */
uint16_t bitRevLength; /** & lt; bit reversal table length. */
} arm_cfft_instance_q15;
void arm_cfft_q15(
const arm_cfft_instance_q15 * S,
q15_t * p1,
uint8_t ifftFlag,
uint8_t bitReverseFlag);
/**
* @brief Instance structure for the fixed-point CFFT/CIFFT function.
*/
typedef struct
{
uint16_t fftLen; /** & lt; length of the FFT. */
const q31_t *pTwiddle; /** & lt; points to the Twiddle factor table. */
const uint16_t *pBitRevTable; /** & lt; points to the bit reversal table. */
uint16_t bitRevLength; /** & lt; bit reversal table length. */
} arm_cfft_instance_q31;
void arm_cfft_q31(
const arm_cfft_instance_q31 * S,
q31_t * p1,
uint8_t ifftFlag,
uint8_t bitReverseFlag);
/**
* @brief Instance structure for the floating-point CFFT/CIFFT function.
*/
typedef struct
{
uint16_t fftLen; /** & lt; length of the FFT. */
const float32_t *pTwiddle; /** & lt; points to the Twiddle factor table. */
const uint16_t *pBitRevTable; /** & lt; points to the bit reversal table. */
uint16_t bitRevLength; /** & lt; bit reversal table length. */
} arm_cfft_instance_f32;
void arm_cfft_f32(
const arm_cfft_instance_f32 * S,
float32_t * p1,
uint8_t ifftFlag,
uint8_t bitReverseFlag);
/**
* @brief Instance structure for the Q15 RFFT/RIFFT function.
*/
typedef struct
{
uint32_t fftLenReal; /** & lt; length of the real FFT. */
uint8_t ifftFlagR; /** & lt; flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
uint8_t bitReverseFlagR; /** & lt; flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
uint32_t twidCoefRModifier; /** & lt; twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
q15_t *pTwiddleAReal; /** & lt; points to the real twiddle factor table. */
q15_t *pTwiddleBReal; /** & lt; points to the imag twiddle factor table. */
const arm_cfft_instance_q15 *pCfft; /** & lt; points to the complex FFT instance. */
} arm_rfft_instance_q15;
arm_status arm_rfft_init_q15(
arm_rfft_instance_q15 * S,
uint32_t fftLenReal,
uint32_t ifftFlagR,
uint32_t bitReverseFlag);
void arm_rfft_q15(
const arm_rfft_instance_q15 * S,
q15_t * pSrc,
q15_t * pDst);
/**
* @brief Instance structure for the Q31 RFFT/RIFFT function.
*/
typedef struct
{
uint32_t fftLenReal; /** & lt; length of the real FFT. */
uint8_t ifftFlagR; /** & lt; flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
uint8_t bitReverseFlagR; /** & lt; flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
uint32_t twidCoefRModifier; /** & lt; twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
q31_t *pTwiddleAReal; /** & lt; points to the real twiddle factor table. */
q31_t *pTwiddleBReal; /** & lt; points to the imag twiddle factor table. */
const arm_cfft_instance_q31 *pCfft; /** & lt; points to the complex FFT instance. */
} arm_rfft_instance_q31;
arm_status arm_rfft_init_q31(
arm_rfft_instance_q31 * S,
uint32_t fftLenReal,
uint32_t ifftFlagR,
uint32_t bitReverseFlag);
void arm_rfft_q31(
const arm_rfft_instance_q31 * S,
q31_t * pSrc,
q31_t * pDst);
/**
* @brief Instance structure for the floating-point RFFT/RIFFT function.
*/
typedef struct
{
uint32_t fftLenReal; /** & lt; length of the real FFT. */
uint16_t fftLenBy2; /** & lt; length of the complex FFT. */
uint8_t ifftFlagR; /** & lt; flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
uint8_t bitReverseFlagR; /** & lt; flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
uint32_t twidCoefRModifier; /** & lt; twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
float32_t *pTwiddleAReal; /** & lt; points to the real twiddle factor table. */
float32_t *pTwiddleBReal; /** & lt; points to the imag twiddle factor table. */
arm_cfft_radix4_instance_f32 *pCfft; /** & lt; points to the complex FFT instance. */
} arm_rfft_instance_f32;
arm_status arm_rfft_init_f32(
arm_rfft_instance_f32 * S,
arm_cfft_radix4_instance_f32 * S_CFFT,
uint32_t fftLenReal,
uint32_t ifftFlagR,
uint32_t bitReverseFlag);
void arm_rfft_f32(
const arm_rfft_instance_f32 * S,
float32_t * pSrc,
float32_t * pDst);
/**
* @brief Instance structure for the floating-point RFFT/RIFFT function.
*/
typedef struct
{
arm_cfft_instance_f32 Sint; /** & lt; Internal CFFT structure. */
uint16_t fftLenRFFT; /** & lt; length of the real sequence */
float32_t * pTwiddleRFFT; /** & lt; Twiddle factors real stage */
} arm_rfft_fast_instance_f32 ;
arm_status arm_rfft_fast_init_f32 (
arm_rfft_fast_instance_f32 * S,
uint16_t fftLen);
void arm_rfft_fast_f32(
arm_rfft_fast_instance_f32 * S,
float32_t * p, float32_t * pOut,
uint8_t ifftFlag);
/**
* @brief Instance structure for the floating-point DCT4/IDCT4 function.
*/
typedef struct
{
uint16_t N; /** & lt; length of the DCT4. */
uint16_t Nby2; /** & lt; half of the length of the DCT4. */
float32_t normalize; /** & lt; normalizing factor. */
float32_t *pTwiddle; /** & lt; points to the twiddle factor table. */
float32_t *pCosFactor; /** & lt; points to the cosFactor table. */
arm_rfft_instance_f32 *pRfft; /** & lt; points to the real FFT instance. */
arm_cfft_radix4_instance_f32 *pCfft; /** & lt; points to the complex FFT instance. */
} arm_dct4_instance_f32;
/**
* @brief Initialization function for the floating-point DCT4/IDCT4.
* @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure.
* @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
* @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
* @param[in] N length of the DCT4.
* @param[in] Nby2 half of the length of the DCT4.
* @param[in] normalize normalizing factor.
* @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if & lt; code & gt; fftLenReal & lt; /code & gt; is not a supported transform length.
*/
arm_status arm_dct4_init_f32(
arm_dct4_instance_f32 * S,
arm_rfft_instance_f32 * S_RFFT,
arm_cfft_radix4_instance_f32 * S_CFFT,
uint16_t N,
uint16_t Nby2,
float32_t normalize);
/**
* @brief Processing function for the floating-point DCT4/IDCT4.
* @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure.
* @param[in] pState points to state buffer.
* @param[in,out] pInlineBuffer points to the in-place input and output buffer.
*/
void arm_dct4_f32(
const arm_dct4_instance_f32 * S,
float32_t * pState,
float32_t * pInlineBuffer);
/**
* @brief Instance structure for the Q31 DCT4/IDCT4 function.
*/
typedef struct
{
uint16_t N; /** & lt; length of the DCT4. */
uint16_t Nby2; /** & lt; half of the length of the DCT4. */
q31_t normalize; /** & lt; normalizing factor. */
q31_t *pTwiddle; /** & lt; points to the twiddle factor table. */
q31_t *pCosFactor; /** & lt; points to the cosFactor table. */
arm_rfft_instance_q31 *pRfft; /** & lt; points to the real FFT instance. */
arm_cfft_radix4_instance_q31 *pCfft; /** & lt; points to the complex FFT instance. */
} arm_dct4_instance_q31;
/**
* @brief Initialization function for the Q31 DCT4/IDCT4.
* @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure.
* @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure
* @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure
* @param[in] N length of the DCT4.
* @param[in] Nby2 half of the length of the DCT4.
* @param[in] normalize normalizing factor.
* @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if & lt; code & gt; N & lt; /code & gt; is not a supported transform length.
*/
arm_status arm_dct4_init_q31(
arm_dct4_instance_q31 * S,
arm_rfft_instance_q31 * S_RFFT,
arm_cfft_radix4_instance_q31 * S_CFFT,
uint16_t N,
uint16_t Nby2,
q31_t normalize);
/**
* @brief Processing function for the Q31 DCT4/IDCT4.
* @param[in] S points to an instance of the Q31 DCT4 structure.
* @param[in] pState points to state buffer.
* @param[in,out] pInlineBuffer points to the in-place input and output buffer.
*/
void arm_dct4_q31(
const arm_dct4_instance_q31 * S,
q31_t * pState,
q31_t * pInlineBuffer);
/**
* @brief Instance structure for the Q15 DCT4/IDCT4 function.
*/
typedef struct
{
uint16_t N; /** & lt; length of the DCT4. */
uint16_t Nby2; /** & lt; half of the length of the DCT4. */
q15_t normalize; /** & lt; normalizing factor. */
q15_t *pTwiddle; /** & lt; points to the twiddle factor table. */
q15_t *pCosFactor; /** & lt; points to the cosFactor table. */
arm_rfft_instance_q15 *pRfft; /** & lt; points to the real FFT instance. */
arm_cfft_radix4_instance_q15 *pCfft; /** & lt; points to the complex FFT instance. */
} arm_dct4_instance_q15;
/**
* @brief Initialization function for the Q15 DCT4/IDCT4.
* @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure.
* @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
* @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
* @param[in] N length of the DCT4.
* @param[in] Nby2 half of the length of the DCT4.
* @param[in] normalize normalizing factor.
* @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if & lt; code & gt; N & lt; /code & gt; is not a supported transform length.
*/
arm_status arm_dct4_init_q15(
arm_dct4_instance_q15 * S,
arm_rfft_instance_q15 * S_RFFT,
arm_cfft_radix4_instance_q15 * S_CFFT,
uint16_t N,
uint16_t Nby2,
q15_t normalize);
/**
* @brief Processing function for the Q15 DCT4/IDCT4.
* @param[in] S points to an instance of the Q15 DCT4 structure.
* @param[in] pState points to state buffer.
* @param[in,out] pInlineBuffer points to the in-place input and output buffer.
*/
void arm_dct4_q15(
const arm_dct4_instance_q15 * S,
q15_t * pState,
q15_t * pInlineBuffer);
/**
* @brief Floating-point vector addition.
* @param[in] pSrcA points to the first input vector
* @param[in] pSrcB points to the second input vector
* @param[out] pDst points to the output vector
* @param[in] blockSize number of samples in each vector
*/
void arm_add_f32(
float32_t * pSrcA,
float32_t * pSrcB,
float32_t * pDst,
uint32_t blockSize);
/**
* @brief Q7 vector addition.
* @param[in] pSrcA points to the first input vector
* @param[in] pSrcB points to the second input vector
* @param[out] pDst points to the output vector
* @param[in] blockSize number of samples in each vector
*/
void arm_add_q7(
q7_t * pSrcA,
q7_t * pSrcB,
q7_t * pDst,
uint32_t blockSize);
/**
* @brief Q15 vector addition.
* @param[in] pSrcA points to the first input vector
* @param[in] pSrcB points to the second input vector
* @param[out] pDst points to the output vector
* @param[in] blockSize number of samples in each vector
*/
void arm_add_q15(
q15_t * pSrcA,
q15_t * pSrcB,
q15_t * pDst,
uint32_t blockSize);
/**
* @brief Q31 vector addition.
* @param[in] pSrcA points to the first input vector
* @param[in] pSrcB points to the second input vector
* @param[out] pDst points to the output vector
* @param[in] blockSize number of samples in each vector
*/
void arm_add_q31(
q31_t * pSrcA,
q31_t * pSrcB,
q31_t * pDst,
uint32_t blockSize);
/**
* @brief Floating-point vector subtraction.
* @param[in] pSrcA points to the first input vector
* @param[in] pSrcB points to the second input vector
* @param[out] pDst points to the output vector
* @param[in] blockSize number of samples in each vector
*/
void arm_sub_f32(
float32_t * pSrcA,
float32_t * pSrcB,
float32_t * pDst,
uint32_t blockSize);
/**
* @brief Q7 vector subtraction.
* @param[in] pSrcA points to the first input vector
* @param[in] pSrcB points to the second input vector
* @param[out] pDst points to the output vector
* @param[in] blockSize number of samples in each vector
*/
void arm_sub_q7(
q7_t * pSrcA,
q7_t * pSrcB,
q7_t * pDst,
uint32_t blockSize);
/**
* @brief Q15 vector subtraction.
* @param[in] pSrcA points to the first input vector
* @param[in] pSrcB points to the second input vector
* @param[out] pDst points to the output vector
* @param[in] blockSize number of samples in each vector
*/
void arm_sub_q15(
q15_t * pSrcA,
q15_t * pSrcB,
q15_t * pDst,
uint32_t blockSize);
/**
* @brief Q31 vector subtraction.
* @param[in] pSrcA points to the first input vector
* @param[in] pSrcB points to the second input vector
* @param[out] pDst points to the output vector
* @param[in] blockSize number of samples in each vector
*/
void arm_sub_q31(
q31_t * pSrcA,
q31_t * pSrcB,
q31_t * pDst,
uint32_t blockSize);
/**
* @brief Multiplies a floating-point vector by a scalar.
* @param[in] pSrc points to the input vector
* @param[in] scale scale factor to be applied
* @param[out] pDst points to the output vector
* @param[in] blockSize number of samples in the vector
*/
void arm_scale_f32(
float32_t * pSrc,
float32_t scale,
float32_t * pDst,
uint32_t blockSize);
/**
* @brief Multiplies a Q7 vector by a scalar.
* @param[in] pSrc points to the input vector
* @param[in] scaleFract fractional portion of the scale value
* @param[in] shift number of bits to shift the result by
* @param[out] pDst points to the output vector
* @param[in] blockSize number of samples in the vector
*/
void arm_scale_q7(
q7_t * pSrc,
q7_t scaleFract,
int8_t shift,
q7_t * pDst,
uint32_t blockSize);
/**
* @brief Multiplies a Q15 vector by a scalar.
* @param[in] pSrc points to the input vector
* @param[in] scaleFract fractional portion of the scale value
* @param[in] shift number of bits to shift the result by
* @param[out] pDst points to the output vector
* @param[in] blockSize number of samples in the vector
*/
void arm_scale_q15(
q15_t * pSrc,
q15_t scaleFract,
int8_t shift,
q15_t * pDst,
uint32_t blockSize);
/**
* @brief Multiplies a Q31 vector by a scalar.
* @param[in] pSrc points to the input vector
* @param[in] scaleFract fractional portion of the scale value
* @param[in] shift number of bits to shift the result by
* @param[out] pDst points to the output vector
* @param[in] blockSize number of samples in the vector
*/
void arm_scale_q31(
q31_t * pSrc,
q31_t scaleFract,
int8_t shift,
q31_t * pDst,
uint32_t blockSize);
/**
* @brief Q7 vector absolute value.
* @param[in] pSrc points to the input buffer
* @param[out] pDst points to the output buffer
* @param[in] blockSize number of samples in each vector
*/
void arm_abs_q7(
q7_t * pSrc,
q7_t * pDst,
uint32_t blockSize);
/**
* @brief Floating-point vector absolute value.
* @param[in] pSrc points to the input buffer
* @param[out] pDst points to the output buffer
* @param[in] blockSize number of samples in each vector
*/
void arm_abs_f32(
float32_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
/**
* @brief Q15 vector absolute value.
* @param[in] pSrc points to the input buffer
* @param[out] pDst points to the output buffer
* @param[in] blockSize number of samples in each vector
*/
void arm_abs_q15(
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
/**
* @brief Q31 vector absolute value.
* @param[in] pSrc points to the input buffer
* @param[out] pDst points to the output buffer
* @param[in] blockSize number of samples in each vector
*/
void arm_abs_q31(
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
/**
* @brief Dot product of floating-point vectors.
* @param[in] pSrcA points to the first input vector
* @param[in] pSrcB points to the second input vector
* @param[in] blockSize number of samples in each vector
* @param[out] result output result returned here
*/
void arm_dot_prod_f32(
float32_t * pSrcA,
float32_t * pSrcB,
uint32_t blockSize,
float32_t * result);
/**
* @brief Dot product of Q7 vectors.
* @param[in] pSrcA points to the first input vector
* @param[in] pSrcB points to the second input vector
* @param[in] blockSize number of samples in each vector
* @param[out] result output result returned here
*/
void arm_dot_prod_q7(
q7_t * pSrcA,
q7_t * pSrcB,
uint32_t blockSize,
q31_t * result);
/**
* @brief Dot product of Q15 vectors.
* @param[in] pSrcA points to the first input vector
* @param[in] pSrcB points to the second input vector
* @param[in] blockSize number of samples in each vector
* @param[out] result output result returned here
*/
void arm_dot_prod_q15(
q15_t * pSrcA,
q15_t * pSrcB,
uint32_t blockSize,
q63_t * result);
/**
* @brief Dot product of Q31 vectors.
* @param[in] pSrcA points to the first input vector
* @param[in] pSrcB points to the second input vector
* @param[in] blockSize number of samples in each vector
* @param[out] result output result returned here
*/
void arm_dot_prod_q31(
q31_t * pSrcA,
q31_t * pSrcB,
uint32_t blockSize,
q63_t * result);
/**
* @brief Shifts the elements of a Q7 vector a specified number of bits.
* @param[in] pSrc points to the input vector
* @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
* @param[out] pDst points to the output vector
* @param[in] blockSize number of samples in the vector
*/
void arm_shift_q7(
q7_t * pSrc,
int8_t shiftBits,
q7_t * pDst,
uint32_t blockSize);
/**
* @brief Shifts the elements of a Q15 vector a specified number of bits.
* @param[in] pSrc points to the input vector
* @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
* @param[out] pDst points to the output vector
* @param[in] blockSize number of samples in the vector
*/
void arm_shift_q15(
q15_t * pSrc,
int8_t shiftBits,
q15_t * pDst,
uint32_t blockSize);
/**
* @brief Shifts the elements of a Q31 vector a specified number of bits.
* @param[in] pSrc points to the input vector
* @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
* @param[out] pDst points to the output vector
* @param[in] blockSize number of samples in the vector
*/
void arm_shift_q31(
q31_t * pSrc,
int8_t shiftBits,
q31_t * pDst,
uint32_t blockSize);
/**
* @brief Adds a constant offset to a floating-point vector.
* @param[in] pSrc points to the input vector
* @param[in] offset is the offset to be added
* @param[out] pDst points to the output vector
* @param[in] blockSize number of samples in the vector
*/
void arm_offset_f32(
float32_t * pSrc,
float32_t offset,
float32_t * pDst,
uint32_t blockSize);
/**
* @brief Adds a constant offset to a Q7 vector.
* @param[in] pSrc points to the input vector
* @param[in] offset is the offset to be added
* @param[out] pDst points to the output vector
* @param[in] blockSize number of samples in the vector
*/
void arm_offset_q7(
q7_t * pSrc,
q7_t offset,
q7_t * pDst,
uint32_t blockSize);
/**
* @brief Adds a constant offset to a Q15 vector.
* @param[in] pSrc points to the input vector
* @param[in] offset is the offset to be added
* @param[out] pDst points to the output vector
* @param[in] blockSize number of samples in the vector
*/
void arm_offset_q15(
q15_t * pSrc,
q15_t offset,
q15_t * pDst,
uint32_t blockSize);
/**
* @brief Adds a constant offset to a Q31 vector.
* @param[in] pSrc points to the input vector
* @param[in] offset is the offset to be added
* @param[out] pDst points to the output vector
* @param[in] blockSize number of samples in the vector
*/
void arm_offset_q31(
q31_t * pSrc,
q31_t offset,
q31_t * pDst,
uint32_t blockSize);
/**
* @brief Negates the elements of a floating-point vector.
* @param[in] pSrc points to the input vector
* @param[out] pDst points to the output vector
* @param[in] blockSize number of samples in the vector
*/
void arm_negate_f32(
float32_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
/**
* @brief Negates the elements of a Q7 vector.
* @param[in] pSrc points to the input vector
* @param[out] pDst points to the output vector
* @param[in] blockSize number of samples in the vector
*/
void arm_negate_q7(
q7_t * pSrc,
q7_t * pDst,
uint32_t blockSize);
/**
* @brief Negates the elements of a Q15 vector.
* @param[in] pSrc points to the input vector
* @param[out] pDst points to the output vector
* @param[in] blockSize number of samples in the vector
*/
void arm_negate_q15(
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
/**
* @brief Negates the elements of a Q31 vector.
* @param[in] pSrc points to the input vector
* @param[out] pDst points to the output vector
* @param[in] blockSize number of samples in the vector
*/
void arm_negate_q31(
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
/**
* @brief Copies the elements of a floating-point vector.
* @param[in] pSrc input pointer
* @param[out] pDst output pointer
* @param[in] blockSize number of samples to process
*/
void arm_copy_f32(
float32_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
/**
* @brief Copies the elements of a Q7 vector.
* @param[in] pSrc input pointer
* @param[out] pDst output pointer
* @param[in] blockSize number of samples to process
*/
void arm_copy_q7(
q7_t * pSrc,
q7_t * pDst,
uint32_t blockSize);
/**
* @brief Copies the elements of a Q15 vector.
* @param[in] pSrc input pointer
* @param[out] pDst output pointer
* @param[in] blockSize number of samples to process
*/
void arm_copy_q15(
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
/**
* @brief Copies the elements of a Q31 vector.
* @param[in] pSrc input pointer
* @param[out] pDst output pointer
* @param[in] blockSize number of samples to process
*/
void arm_copy_q31(
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
/**
* @brief Fills a constant value into a floating-point vector.
* @param[in] value input value to be filled
* @param[out] pDst output pointer
* @param[in] blockSize number of samples to process
*/
void arm_fill_f32(
float32_t value,
float32_t * pDst,
uint32_t blockSize);
/**
* @brief Fills a constant value into a Q7 vector.
* @param[in] value input value to be filled
* @param[out] pDst output pointer
* @param[in] blockSize number of samples to process
*/
void arm_fill_q7(
q7_t value,
q7_t * pDst,
uint32_t blockSize);
/**
* @brief Fills a constant value into a Q15 vector.
* @param[in] value input value to be filled
* @param[out] pDst output pointer
* @param[in] blockSize number of samples to process
*/
void arm_fill_q15(
q15_t value,
q15_t * pDst,
uint32_t blockSize);
/**
* @brief Fills a constant value into a Q31 vector.
* @param[in] value input value to be filled
* @param[out] pDst output pointer
* @param[in] blockSize number of samples to process
*/
void arm_fill_q31(
q31_t value,
q31_t * pDst,
uint32_t blockSize);
/**
* @brief Convolution of floating-point sequences.
* @param[in] pSrcA points to the first input sequence.
* @param[in] srcALen length of the first input sequence.
* @param[in] pSrcB points to the second input sequence.
* @param[in] srcBLen length of the second input sequence.
* @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
*/
void arm_conv_f32(
float32_t * pSrcA,
uint32_t srcALen,
float32_t * pSrcB,
uint32_t srcBLen,
float32_t * pDst);
/**
* @brief Convolution of Q15 sequences.
* @param[in] pSrcA points to the first input sequence.
* @param[in] srcALen length of the first input sequence.
* @param[in] pSrcB points to the second input sequence.
* @param[in] srcBLen length of the second input sequence.
* @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
* @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
* @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
*/
void arm_conv_opt_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst,
q15_t * pScratch1,
q15_t * pScratch2);
/**
* @brief Convolution of Q15 sequences.
* @param[in] pSrcA points to the first input sequence.
* @param[in] srcALen length of the first input sequence.
* @param[in] pSrcB points to the second input sequence.
* @param[in] srcBLen length of the second input sequence.
* @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
*/
void arm_conv_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst);
/**
* @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
* @param[in] pSrcA points to the first input sequence.
* @param[in] srcALen length of the first input sequence.
* @param[in] pSrcB points to the second input sequence.
* @param[in] srcBLen length of the second input sequence.
* @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
*/
void arm_conv_fast_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst);
/**
* @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
* @param[in] pSrcA points to the first input sequence.
* @param[in] srcALen length of the first input sequence.
* @param[in] pSrcB points to the second input sequence.
* @param[in] srcBLen length of the second input sequence.
* @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
* @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
* @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
*/
void arm_conv_fast_opt_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst,
q15_t * pScratch1,
q15_t * pScratch2);
/**
* @brief Convolution of Q31 sequences.
* @param[in] pSrcA points to the first input sequence.
* @param[in] srcALen length of the first input sequence.
* @param[in] pSrcB points to the second input sequence.
* @param[in] srcBLen length of the second input sequence.
* @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
*/
void arm_conv_q31(
q31_t * pSrcA,
uint32_t srcALen,
q31_t * pSrcB,
uint32_t srcBLen,
q31_t * pDst);
/**
* @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
* @param[in] pSrcA points to the first input sequence.
* @param[in] srcALen length of the first input sequence.
* @param[in] pSrcB points to the second input sequence.
* @param[in] srcBLen length of the second input sequence.
* @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
*/
void arm_conv_fast_q31(
q31_t * pSrcA,
uint32_t srcALen,
q31_t * pSrcB,
uint32_t srcBLen,
q31_t * pDst);
/**
* @brief Convolution of Q7 sequences.
* @param[in] pSrcA points to the first input sequence.
* @param[in] srcALen length of the first input sequence.
* @param[in] pSrcB points to the second input sequence.
* @param[in] srcBLen length of the second input sequence.
* @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
* @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
* @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
*/
void arm_conv_opt_q7(
q7_t * pSrcA,
uint32_t srcALen,
q7_t * pSrcB,
uint32_t srcBLen,
q7_t * pDst,
q15_t * pScratch1,
q15_t * pScratch2);
/**
* @brief Convolution of Q7 sequences.
* @param[in] pSrcA points to the first input sequence.
* @param[in] srcALen length of the first input sequence.
* @param[in] pSrcB points to the second input sequence.
* @param[in] srcBLen length of the second input sequence.
* @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
*/
void arm_conv_q7(
q7_t * pSrcA,
uint32_t srcALen,
q7_t * pSrcB,
uint32_t srcBLen,
q7_t * pDst);
/**
* @brief Partial convolution of floating-point sequences.
* @param[in] pSrcA points to the first input sequence.
* @param[in] srcALen length of the first input sequence.
* @param[in] pSrcB points to the second input sequence.
* @param[in] srcBLen length of the second input sequence.
* @param[out] pDst points to the block of output data
* @param[in] firstIndex is the first output sample to start with.
* @param[in] numPoints is the number of output points to be computed.
* @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
*/
arm_status arm_conv_partial_f32(
float32_t * pSrcA,
uint32_t srcALen,
float32_t * pSrcB,
uint32_t srcBLen,
float32_t * pDst,
uint32_t firstIndex,
uint32_t numPoints);
/**
* @brief Partial convolution of Q15 sequences.
* @param[in] pSrcA points to the first input sequence.
* @param[in] srcALen length of the first input sequence.
* @param[in] pSrcB points to the second input sequence.
* @param[in] srcBLen length of the second input sequence.
* @param[out] pDst points to the block of output data
* @param[in] firstIndex is the first output sample to start with.
* @param[in] numPoints is the number of output points to be computed.
* @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
* @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
* @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
*/
arm_status arm_conv_partial_opt_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst,
uint32_t firstIndex,
uint32_t numPoints,
q15_t * pScratch1,
q15_t * pScratch2);
/**
* @brief Partial convolution of Q15 sequences.
* @param[in] pSrcA points to the first input sequence.
* @param[in] srcALen length of the first input sequence.
* @param[in] pSrcB points to the second input sequence.
* @param[in] srcBLen length of the second input sequence.
* @param[out] pDst points to the block of output data
* @param[in] firstIndex is the first output sample to start with.
* @param[in] numPoints is the number of output points to be computed.
* @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
*/
arm_status arm_conv_partial_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst,
uint32_t firstIndex,
uint32_t numPoints);
/**
* @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
* @param[in] pSrcA points to the first input sequence.
* @param[in] srcALen length of the first input sequence.
* @param[in] pSrcB points to the second input sequence.
* @param[in] srcBLen length of the second input sequence.
* @param[out] pDst points to the block of output data
* @param[in] firstIndex is the first output sample to start with.
* @param[in] numPoints is the number of output points to be computed.
* @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
*/
arm_status arm_conv_partial_fast_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst,
uint32_t firstIndex,
uint32_t numPoints);
/**
* @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
* @param[in] pSrcA points to the first input sequence.
* @param[in] srcALen length of the first input sequence.
* @param[in] pSrcB points to the second input sequence.
* @param[in] srcBLen length of the second input sequence.
* @param[out] pDst points to the block of output data
* @param[in] firstIndex is the first output sample to start with.
* @param[in] numPoints is the number of output points to be computed.
* @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
* @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
* @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
*/
arm_status arm_conv_partial_fast_opt_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst,
uint32_t firstIndex,
uint32_t numPoints,
q15_t * pScratch1,
q15_t * pScratch2);
/**
* @brief Partial convolution of Q31 sequences.
* @param[in] pSrcA points to the first input sequence.
* @param[in] srcALen length of the first input sequence.
* @param[in] pSrcB points to the second input sequence.
* @param[in] srcBLen length of the second input sequence.
* @param[out] pDst points to the block of output data
* @param[in] firstIndex is the first output sample to start with.
* @param[in] numPoints is the number of output points to be computed.
* @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
*/
arm_status arm_conv_partial_q31(
q31_t * pSrcA,
uint32_t srcALen,
q31_t * pSrcB,
uint32_t srcBLen,
q31_t * pDst,
uint32_t firstIndex,
uint32_t numPoints);
/**
* @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
* @param[in] pSrcA points to the first input sequence.
* @param[in] srcALen length of the first input sequence.
* @param[in] pSrcB points to the second input sequence.
* @param[in] srcBLen length of the second input sequence.
* @param[out] pDst points to the block of output data
* @param[in] firstIndex is the first output sample to start with.
* @param[in] numPoints is the number of output points to be computed.
* @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
*/
arm_status arm_conv_partial_fast_q31(
q31_t * pSrcA,
uint32_t srcALen,
q31_t * pSrcB,
uint32_t srcBLen,
q31_t * pDst,
uint32_t firstIndex,
uint32_t numPoints);
/**
* @brief Partial convolution of Q7 sequences
* @param[in] pSrcA points to the first input sequence.
* @param[in] srcALen length of the first input sequence.
* @param[in] pSrcB points to the second input sequence.
* @param[in] srcBLen length of the second input sequence.
* @param[out] pDst points to the block of output data
* @param[in] firstIndex is the first output sample to start with.
* @param[in] numPoints is the number of output points to be computed.
* @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
* @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
* @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
*/
arm_status arm_conv_partial_opt_q7(
q7_t * pSrcA,
uint32_t srcALen,
q7_t * pSrcB,
uint32_t srcBLen,
q7_t * pDst,
uint32_t firstIndex,
uint32_t numPoints,
q15_t * pScratch1,
q15_t * pScratch2);
/**
* @brief Partial convolution of Q7 sequences.
* @param[in] pSrcA points to the first input sequence.
* @param[in] srcALen length of the first input sequence.
* @param[in] pSrcB points to the second input sequence.
* @param[in] srcBLen length of the second input sequence.
* @param[out] pDst points to the block of output data
* @param[in] firstIndex is the first output sample to start with.
* @param[in] numPoints is the number of output points to be computed.
* @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
*/
arm_status arm_conv_partial_q7(
q7_t * pSrcA,
uint32_t srcALen,
q7_t * pSrcB,
uint32_t srcBLen,
q7_t * pDst,
uint32_t firstIndex,
uint32_t numPoints);
/**
* @brief Instance structure for the Q15 FIR decimator.
*/
typedef struct
{
uint8_t M; /** & lt; decimation factor. */
uint16_t numTaps; /** & lt; number of coefficients in the filter. */
q15_t *pCoeffs; /** & lt; points to the coefficient array. The array is of length numTaps.*/
q15_t *pState; /** & lt; points to the state variable array. The array is of length numTaps+blockSize-1. */
} arm_fir_decimate_instance_q15;
/**
* @brief Instance structure for the Q31 FIR decimator.
*/
typedef struct
{
uint8_t M; /** & lt; decimation factor. */
uint16_t numTaps; /** & lt; number of coefficients in the filter. */
q31_t *pCoeffs; /** & lt; points to the coefficient array. The array is of length numTaps.*/
q31_t *pState; /** & lt; points to the state variable array. The array is of length numTaps+blockSize-1. */
} arm_fir_decimate_instance_q31;
/**
* @brief Instance structure for the floating-point FIR decimator.
*/
typedef struct
{
uint8_t M; /** & lt; decimation factor. */
uint16_t numTaps; /** & lt; number of coefficients in the filter. */
float32_t *pCoeffs; /** & lt; points to the coefficient array. The array is of length numTaps.*/
float32_t *pState; /** & lt; points to the state variable array. The array is of length numTaps+blockSize-1. */
} arm_fir_decimate_instance_f32;
/**
* @brief Processing function for the floating-point FIR decimator.
* @param[in] S points to an instance of the floating-point FIR decimator structure.
* @param[in] pSrc points to the block of input data.
* @param[out] pDst points to the block of output data
* @param[in] blockSize number of input samples to process per call.
*/
void arm_fir_decimate_f32(
const arm_fir_decimate_instance_f32 * S,
float32_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
/**
* @brief Initialization function for the floating-point FIR decimator.
* @param[in,out] S points to an instance of the floating-point FIR decimator structure.
* @param[in] numTaps number of coefficients in the filter.
* @param[in] M decimation factor.
* @param[in] pCoeffs points to the filter coefficients.
* @param[in] pState points to the state buffer.
* @param[in] blockSize number of input samples to process per call.
* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
* & lt; code & gt; blockSize & lt; /code & gt; is not a multiple of & lt; code & gt; M & lt; /code & gt; .
*/
arm_status arm_fir_decimate_init_f32(
arm_fir_decimate_instance_f32 * S,
uint16_t numTaps,
uint8_t M,
float32_t * pCoeffs,
float32_t * pState,
uint32_t blockSize);
/**
* @brief Processing function for the Q15 FIR decimator.
* @param[in] S points to an instance of the Q15 FIR decimator structure.
* @param[in] pSrc points to the block of input data.
* @param[out] pDst points to the block of output data
* @param[in] blockSize number of input samples to process per call.
*/
void arm_fir_decimate_q15(
const arm_fir_decimate_instance_q15 * S,
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
/**
* @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
* @param[in] S points to an instance of the Q15 FIR decimator structure.
* @param[in] pSrc points to the block of input data.
* @param[out] pDst points to the block of output data
* @param[in] blockSize number of input samples to process per call.
*/
void arm_fir_decimate_fast_q15(
const arm_fir_decimate_instance_q15 * S,
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
/**
* @brief Initialization function for the Q15 FIR decimator.
* @param[in,out] S points to an instance of the Q15 FIR decimator structure.
* @param[in] numTaps number of coefficients in the filter.
* @param[in] M decimation factor.
* @param[in] pCoeffs points to the filter coefficients.
* @param[in] pState points to the state buffer.
* @param[in] blockSize number of input samples to process per call.
* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
* & lt; code & gt; blockSize & lt; /code & gt; is not a multiple of & lt; code & gt; M & lt; /code & gt; .
*/
arm_status arm_fir_decimate_init_q15(
arm_fir_decimate_instance_q15 * S,
uint16_t numTaps,
uint8_t M,
q15_t * pCoeffs,
q15_t * pState,
uint32_t blockSize);
/**
* @brief Processing function for the Q31 FIR decimator.
* @param[in] S points to an instance of the Q31 FIR decimator structure.
* @param[in] pSrc points to the block of input data.
* @param[out] pDst points to the block of output data
* @param[in] blockSize number of input samples to process per call.
*/
void arm_fir_decimate_q31(
const arm_fir_decimate_instance_q31 * S,
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
/**
* @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
* @param[in] S points to an instance of the Q31 FIR decimator structure.
* @param[in] pSrc points to the block of input data.
* @param[out] pDst points to the block of output data
* @param[in] blockSize number of input samples to process per call.
*/
void arm_fir_decimate_fast_q31(
arm_fir_decimate_instance_q31 * S,
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
/**
* @brief Initialization function for the Q31 FIR decimator.
* @param[in,out] S points to an instance of the Q31 FIR decimator structure.
* @param[in] numTaps number of coefficients in the filter.
* @param[in] M decimation factor.
* @param[in] pCoeffs points to the filter coefficients.
* @param[in] pState points to the state buffer.
* @param[in] blockSize number of input samples to process per call.
* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
* & lt; code & gt; blockSize & lt; /code & gt; is not a multiple of & lt; code & gt; M & lt; /code & gt; .
*/
arm_status arm_fir_decimate_init_q31(
arm_fir_decimate_instance_q31 * S,
uint16_t numTaps,
uint8_t M,
q31_t * pCoeffs,
q31_t * pState,
uint32_t blockSize);
/**
* @brief Instance structure for the Q15 FIR interpolator.
*/
typedef struct
{
uint8_t L; /** & lt; upsample factor. */
uint16_t phaseLength; /** & lt; length of each polyphase filter component. */
q15_t *pCoeffs; /** & lt; points to the coefficient array. The array is of length L*phaseLength. */
q15_t *pState; /** & lt; points to the state variable array. The array is of length blockSize+phaseLength-1. */
} arm_fir_interpolate_instance_q15;
/**
* @brief Instance structure for the Q31 FIR interpolator.
*/
typedef struct
{
uint8_t L; /** & lt; upsample factor. */
uint16_t phaseLength; /** & lt; length of each polyphase filter component. */
q31_t *pCoeffs; /** & lt; points to the coefficient array. The array is of length L*phaseLength. */
q31_t *pState; /** & lt; points to the state variable array. The array is of length blockSize+phaseLength-1. */
} arm_fir_interpolate_instance_q31;
/**
* @brief Instance structure for the floating-point FIR interpolator.
*/
typedef struct
{
uint8_t L; /** & lt; upsample factor. */
uint16_t phaseLength; /** & lt; length of each polyphase filter component. */
float32_t *pCoeffs; /** & lt; points to the coefficient array. The array is of length L*phaseLength. */
float32_t *pState; /** & lt; points to the state variable array. The array is of length phaseLength+numTaps-1. */
} arm_fir_interpolate_instance_f32;
/**
* @brief Processing function for the Q15 FIR interpolator.
* @param[in] S points to an instance of the Q15 FIR interpolator structure.
* @param[in] pSrc points to the block of input data.
* @param[out] pDst points to the block of output data.
* @param[in] blockSize number of input samples to process per call.
*/
void arm_fir_interpolate_q15(
const arm_fir_interpolate_instance_q15 * S,
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
/**
* @brief Initialization function for the Q15 FIR interpolator.
* @param[in,out] S points to an instance of the Q15 FIR interpolator structure.
* @param[in] L upsample factor.
* @param[in] numTaps number of filter coefficients in the filter.
* @param[in] pCoeffs points to the filter coefficient buffer.
* @param[in] pState points to the state buffer.
* @param[in] blockSize number of input samples to process per call.
* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
* the filter length & lt; code & gt; numTaps & lt; /code & gt; is not a multiple of the interpolation factor & lt; code & gt; L & lt; /code & gt; .
*/
arm_status arm_fir_interpolate_init_q15(
arm_fir_interpolate_instance_q15 * S,
uint8_t L,
uint16_t numTaps,
q15_t * pCoeffs,
q15_t * pState,
uint32_t blockSize);
/**
* @brief Processing function for the Q31 FIR interpolator.
* @param[in] S points to an instance of the Q15 FIR interpolator structure.
* @param[in] pSrc points to the block of input data.
* @param[out] pDst points to the block of output data.
* @param[in] blockSize number of input samples to process per call.
*/
void arm_fir_interpolate_q31(
const arm_fir_interpolate_instance_q31 * S,
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
/**
* @brief Initialization function for the Q31 FIR interpolator.
* @param[in,out] S points to an instance of the Q31 FIR interpolator structure.
* @param[in] L upsample factor.
* @param[in] numTaps number of filter coefficients in the filter.
* @param[in] pCoeffs points to the filter coefficient buffer.
* @param[in] pState points to the state buffer.
* @param[in] blockSize number of input samples to process per call.
* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
* the filter length & lt; code & gt; numTaps & lt; /code & gt; is not a multiple of the interpolation factor & lt; code & gt; L & lt; /code & gt; .
*/
arm_status arm_fir_interpolate_init_q31(
arm_fir_interpolate_instance_q31 * S,
uint8_t L,
uint16_t numTaps,
q31_t * pCoeffs,
q31_t * pState,
uint32_t blockSize);
/**
* @brief Processing function for the floating-point FIR interpolator.
* @param[in] S points to an instance of the floating-point FIR interpolator structure.
* @param[in] pSrc points to the block of input data.
* @param[out] pDst points to the block of output data.
* @param[in] blockSize number of input samples to process per call.
*/
void arm_fir_interpolate_f32(
const arm_fir_interpolate_instance_f32 * S,
float32_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
/**
* @brief Initialization function for the floating-point FIR interpolator.
* @param[in,out] S points to an instance of the floating-point FIR interpolator structure.
* @param[in] L upsample factor.
* @param[in] numTaps number of filter coefficients in the filter.
* @param[in] pCoeffs points to the filter coefficient buffer.
* @param[in] pState points to the state buffer.
* @param[in] blockSize number of input samples to process per call.
* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
* the filter length & lt; code & gt; numTaps & lt; /code & gt; is not a multiple of the interpolation factor & lt; code & gt; L & lt; /code & gt; .
*/
arm_status arm_fir_interpolate_init_f32(
arm_fir_interpolate_instance_f32 * S,
uint8_t L,
uint16_t numTaps,
float32_t * pCoeffs,
float32_t * pState,
uint32_t blockSize);
/**
* @brief Instance structure for the high precision Q31 Biquad cascade filter.
*/
typedef struct
{
uint8_t numStages; /** & lt; number of 2nd order stages in the filter. Overall order is 2*numStages. */
q63_t *pState; /** & lt; points to the array of state coefficients. The array is of length 4*numStages. */
q31_t *pCoeffs; /** & lt; points to the array of coefficients. The array is of length 5*numStages. */
uint8_t postShift; /** & lt; additional shift, in bits, applied to each output sample. */
} arm_biquad_cas_df1_32x64_ins_q31;
/**
* @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure.
* @param[in] pSrc points to the block of input data.
* @param[out] pDst points to the block of output data
* @param[in] blockSize number of samples to process.
*/
void arm_biquad_cas_df1_32x64_q31(
const arm_biquad_cas_df1_32x64_ins_q31 * S,
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
/**
* @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure.
* @param[in] numStages number of 2nd order stages in the filter.
* @param[in] pCoeffs points to the filter coefficients.
* @param[in] pState points to the state buffer.
* @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
*/
void arm_biquad_cas_df1_32x64_init_q31(
arm_biquad_cas_df1_32x64_ins_q31 * S,
uint8_t numStages,
q31_t * pCoeffs,
q63_t * pState,
uint8_t postShift);
/**
* @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
*/
typedef struct
{
uint8_t numStages; /** & lt; number of 2nd order stages in the filter. Overall order is 2*numStages. */
float32_t *pState; /** & lt; points to the array of state coefficients. The array is of length 2*numStages. */
float32_t *pCoeffs; /** & lt; points to the array of coefficients. The array is of length 5*numStages. */
} arm_biquad_cascade_df2T_instance_f32;
/**
* @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
*/
typedef struct
{
uint8_t numStages; /** & lt; number of 2nd order stages in the filter. Overall order is 2*numStages. */
float32_t *pState; /** & lt; points to the array of state coefficients. The array is of length 4*numStages. */
float32_t *pCoeffs; /** & lt; points to the array of coefficients. The array is of length 5*numStages. */
} arm_biquad_cascade_stereo_df2T_instance_f32;
/**
* @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
*/
typedef struct
{
uint8_t numStages; /** & lt; number of 2nd order stages in the filter. Overall order is 2*numStages. */
float64_t *pState; /** & lt; points to the array of state coefficients. The array is of length 2*numStages. */
float64_t *pCoeffs; /** & lt; points to the array of coefficients. The array is of length 5*numStages. */
} arm_biquad_cascade_df2T_instance_f64;
/**
* @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
* @param[in] S points to an instance of the filter data structure.
* @param[in] pSrc points to the block of input data.
* @param[out] pDst points to the block of output data
* @param[in] blockSize number of samples to process.
*/
void arm_biquad_cascade_df2T_f32(
const arm_biquad_cascade_df2T_instance_f32 * S,
float32_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
/**
* @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
* @param[in] S points to an instance of the filter data structure.
* @param[in] pSrc points to the block of input data.
* @param[out] pDst points to the block of output data
* @param[in] blockSize number of samples to process.
*/
void arm_biquad_cascade_stereo_df2T_f32(
const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
float32_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
/**
* @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
* @param[in] S points to an instance of the filter data structure.
* @param[in] pSrc points to the block of input data.
* @param[out] pDst points to the block of output data
* @param[in] blockSize number of samples to process.
*/
void arm_biquad_cascade_df2T_f64(
const arm_biquad_cascade_df2T_instance_f64 * S,
float64_t * pSrc,
float64_t * pDst,
uint32_t blockSize);
/**
* @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
* @param[in,out] S points to an instance of the filter data structure.
* @param[in] numStages number of 2nd order stages in the filter.
* @param[in] pCoeffs points to the filter coefficients.
* @param[in] pState points to the state buffer.
*/
void arm_biquad_cascade_df2T_init_f32(
arm_biquad_cascade_df2T_instance_f32 * S,
uint8_t numStages,
float32_t * pCoeffs,
float32_t * pState);
/**
* @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
* @param[in,out] S points to an instance of the filter data structure.
* @param[in] numStages number of 2nd order stages in the filter.
* @param[in] pCoeffs points to the filter coefficients.
* @param[in] pState points to the state buffer.
*/
void arm_biquad_cascade_stereo_df2T_init_f32(
arm_biquad_cascade_stereo_df2T_instance_f32 * S,
uint8_t numStages,
float32_t * pCoeffs,
float32_t * pState);
/**
* @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
* @param[in,out] S points to an instance of the filter data structure.
* @param[in] numStages number of 2nd order stages in the filter.
* @param[in] pCoeffs points to the filter coefficients.
* @param[in] pState points to the state buffer.
*/
void arm_biquad_cascade_df2T_init_f64(
arm_biquad_cascade_df2T_instance_f64 * S,
uint8_t numStages,
float64_t * pCoeffs,
float64_t * pState);
/**
* @brief Instance structure for the Q15 FIR lattice filter.
*/
typedef struct
{
uint16_t numStages; /** & lt; number of filter stages. */
q15_t *pState; /** & lt; points to the state variable array. The array is of length numStages. */
q15_t *pCoeffs; /** & lt; points to the coefficient array. The array is of length numStages. */
} arm_fir_lattice_instance_q15;
/**
* @brief Instance structure for the Q31 FIR lattice filter.
*/
typedef struct
{
uint16_t numStages; /** & lt; number of filter stages. */
q31_t *pState; /** & lt; points to the state variable array. The array is of length numStages. */
q31_t *pCoeffs; /** & lt; points to the coefficient array. The array is of length numStages. */
} arm_fir_lattice_instance_q31;
/**
* @brief Instance structure for the floating-point FIR lattice filter.
*/
typedef struct
{
uint16_t numStages; /** & lt; number of filter stages. */
float32_t *pState; /** & lt; points to the state variable array. The array is of length numStages. */
float32_t *pCoeffs; /** & lt; points to the coefficient array. The array is of length numStages. */
} arm_fir_lattice_instance_f32;
/**
* @brief Initialization function for the Q15 FIR lattice filter.
* @param[in] S points to an instance of the Q15 FIR lattice structure.
* @param[in] numStages number of filter stages.
* @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
* @param[in] pState points to the state buffer. The array is of length numStages.
*/
void arm_fir_lattice_init_q15(
arm_fir_lattice_instance_q15 * S,
uint16_t numStages,
q15_t * pCoeffs,
q15_t * pState);
/**
* @brief Processing function for the Q15 FIR lattice filter.
* @param[in] S points to an instance of the Q15 FIR lattice structure.
* @param[in] pSrc points to the block of input data.
* @param[out] pDst points to the block of output data.
* @param[in] blockSize number of samples to process.
*/
void arm_fir_lattice_q15(
const arm_fir_lattice_instance_q15 * S,
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
/**
* @brief Initialization function for the Q31 FIR lattice filter.
* @param[in] S points to an instance of the Q31 FIR lattice structure.
* @param[in] numStages number of filter stages.
* @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
* @param[in] pState points to the state buffer. The array is of length numStages.
*/
void arm_fir_lattice_init_q31(
arm_fir_lattice_instance_q31 * S,
uint16_t numStages,
q31_t * pCoeffs,
q31_t * pState);
/**
* @brief Processing function for the Q31 FIR lattice filter.
* @param[in] S points to an instance of the Q31 FIR lattice structure.
* @param[in] pSrc points to the block of input data.
* @param[out] pDst points to the block of output data
* @param[in] blockSize number of samples to process.
*/
void arm_fir_lattice_q31(
const arm_fir_lattice_instance_q31 * S,
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
/**
* @brief Initialization function for the floating-point FIR lattice filter.
* @param[in] S points to an instance of the floating-point FIR lattice structure.
* @param[in] numStages number of filter stages.
* @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
* @param[in] pState points to the state buffer. The array is of length numStages.
*/
void arm_fir_lattice_init_f32(
arm_fir_lattice_instance_f32 * S,
uint16_t numStages,
float32_t * pCoeffs,
float32_t * pState);
/**
* @brief Processing function for the floating-point FIR lattice filter.
* @param[in] S points to an instance of the floating-point FIR lattice structure.
* @param[in] pSrc points to the block of input data.
* @param[out] pDst points to the block of output data
* @param[in] blockSize number of samples to process.
*/
void arm_fir_lattice_f32(
const arm_fir_lattice_instance_f32 * S,
float32_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
/**
* @brief Instance structure for the Q15 IIR lattice filter.
*/
typedef struct
{
uint16_t numStages; /** & lt; number of stages in the filter. */
q15_t *pState; /** & lt; points to the state variable array. The array is of length numStages+blockSize. */
q15_t *pkCoeffs; /** & lt; points to the reflection coefficient array. The array is of length numStages. */
q15_t *pvCoeffs; /** & lt; points to the ladder coefficient array. The array is of length numStages+1. */
} arm_iir_lattice_instance_q15;
/**
* @brief Instance structure for the Q31 IIR lattice filter.
*/
typedef struct
{
uint16_t numStages; /** & lt; number of stages in the filter. */
q31_t *pState; /** & lt; points to the state variable array. The array is of length numStages+blockSize. */
q31_t *pkCoeffs; /** & lt; points to the reflection coefficient array. The array is of length numStages. */
q31_t *pvCoeffs; /** & lt; points to the ladder coefficient array. The array is of length numStages+1. */
} arm_iir_lattice_instance_q31;
/**
* @brief Instance structure for the floating-point IIR lattice filter.
*/
typedef struct
{
uint16_t numStages; /** & lt; number of stages in the filter. */
float32_t *pState; /** & lt; points to the state variable array. The array is of length numStages+blockSize. */
float32_t *pkCoeffs; /** & lt; points to the reflection coefficient array. The array is of length numStages. */
float32_t *pvCoeffs; /** & lt; points to the ladder coefficient array. The array is of length numStages+1. */
} arm_iir_lattice_instance_f32;
/**
* @brief Processing function for the floating-point IIR lattice filter.
* @param[in] S points to an instance of the floating-point IIR lattice structure.
* @param[in] pSrc points to the block of input data.
* @param[out] pDst points to the block of output data.
* @param[in] blockSize number of samples to process.
*/
void arm_iir_lattice_f32(
const arm_iir_lattice_instance_f32 * S,
float32_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
/**
* @brief Initialization function for the floating-point IIR lattice filter.
* @param[in] S points to an instance of the floating-point IIR lattice structure.
* @param[in] numStages number of stages in the filter.
* @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
* @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
* @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1.
* @param[in] blockSize number of samples to process.
*/
void arm_iir_lattice_init_f32(
arm_iir_lattice_instance_f32 * S,
uint16_t numStages,
float32_t * pkCoeffs,
float32_t * pvCoeffs,
float32_t * pState,
uint32_t blockSize);
/**
* @brief Processing function for the Q31 IIR lattice filter.
* @param[in] S points to an instance of the Q31 IIR lattice structure.
* @param[in] pSrc points to the block of input data.
* @param[out] pDst points to the block of output data.
* @param[in] blockSize number of samples to process.
*/
void arm_iir_lattice_q31(
const arm_iir_lattice_instance_q31 * S,
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
/**
* @brief Initialization function for the Q31 IIR lattice filter.
* @param[in] S points to an instance of the Q31 IIR lattice structure.
* @param[in] numStages number of stages in the filter.
* @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
* @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
* @param[in] pState points to the state buffer. The array is of length numStages+blockSize.
* @param[in] blockSize number of samples to process.
*/
void arm_iir_lattice_init_q31(
arm_iir_lattice_instance_q31 * S,
uint16_t numStages,
q31_t * pkCoeffs,
q31_t * pvCoeffs,
q31_t * pState,
uint32_t blockSize);
/**
* @brief Processing function for the Q15 IIR lattice filter.
* @param[in] S points to an instance of the Q15 IIR lattice structure.
* @param[in] pSrc points to the block of input data.
* @param[out] pDst points to the block of output data.
* @param[in] blockSize number of samples to process.
*/
void arm_iir_lattice_q15(
const arm_iir_lattice_instance_q15 * S,
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
/**
* @brief Initialization function for the Q15 IIR lattice filter.
* @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure.
* @param[in] numStages number of stages in the filter.
* @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
* @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
* @param[in] pState points to state buffer. The array is of length numStages+blockSize.
* @param[in] blockSize number of samples to process per call.
*/
void arm_iir_lattice_init_q15(
arm_iir_lattice_instance_q15 * S,
uint16_t numStages,
q15_t * pkCoeffs,
q15_t * pvCoeffs,
q15_t * pState,
uint32_t blockSize);
/**
* @brief Instance structure for the floating-point LMS filter.
*/
typedef struct
{
uint16_t numTaps; /** & lt; number of coefficients in the filter. */
float32_t *pState; /** & lt; points to the state variable array. The array is of length numTaps+blockSize-1. */
float32_t *pCoeffs; /** & lt; points to the coefficient array. The array is of length numTaps. */
float32_t mu; /** & lt; step size that controls filter coefficient updates. */
} arm_lms_instance_f32;
/**
* @brief Processing function for floating-point LMS filter.
* @param[in] S points to an instance of the floating-point LMS filter structure.
* @param[in] pSrc points to the block of input data.
* @param[in] pRef points to the block of reference data.
* @param[out] pOut points to the block of output data.
* @param[out] pErr points to the block of error data.
* @param[in] blockSize number of samples to process.
*/
void arm_lms_f32(
const arm_lms_instance_f32 * S,
float32_t * pSrc,
float32_t * pRef,
float32_t * pOut,
float32_t * pErr,
uint32_t blockSize);
/**
* @brief Initialization function for floating-point LMS filter.
* @param[in] S points to an instance of the floating-point LMS filter structure.
* @param[in] numTaps number of filter coefficients.
* @param[in] pCoeffs points to the coefficient buffer.
* @param[in] pState points to state buffer.
* @param[in] mu step size that controls filter coefficient updates.
* @param[in] blockSize number of samples to process.
*/
void arm_lms_init_f32(
arm_lms_instance_f32 * S,
uint16_t numTaps,
float32_t * pCoeffs,
float32_t * pState,
float32_t mu,
uint32_t blockSize);
/**
* @brief Instance structure for the Q15 LMS filter.
*/
typedef struct
{
uint16_t numTaps; /** & lt; number of coefficients in the filter. */
q15_t *pState; /** & lt; points to the state variable array. The array is of length numTaps+blockSize-1. */
q15_t *pCoeffs; /** & lt; points to the coefficient array. The array is of length numTaps. */
q15_t mu; /** & lt; step size that controls filter coefficient updates. */
uint32_t postShift; /** & lt; bit shift applied to coefficients. */
} arm_lms_instance_q15;
/**
* @brief Initialization function for the Q15 LMS filter.
* @param[in] S points to an instance of the Q15 LMS filter structure.
* @param[in] numTaps number of filter coefficients.
* @param[in] pCoeffs points to the coefficient buffer.
* @param[in] pState points to the state buffer.
* @param[in] mu step size that controls filter coefficient updates.
* @param[in] blockSize number of samples to process.
* @param[in] postShift bit shift applied to coefficients.
*/
void arm_lms_init_q15(
arm_lms_instance_q15 * S,
uint16_t numTaps,
q15_t * pCoeffs,
q15_t * pState,
q15_t mu,
uint32_t blockSize,
uint32_t postShift);
/**
* @brief Processing function for Q15 LMS filter.
* @param[in] S points to an instance of the Q15 LMS filter structure.
* @param[in] pSrc points to the block of input data.
* @param[in] pRef points to the block of reference data.
* @param[out] pOut points to the block of output data.
* @param[out] pErr points to the block of error data.
* @param[in] blockSize number of samples to process.
*/
void arm_lms_q15(
const arm_lms_instance_q15 * S,
q15_t * pSrc,
q15_t * pRef,
q15_t * pOut,
q15_t * pErr,
uint32_t blockSize);
/**
* @brief Instance structure for the Q31 LMS filter.
*/
typedef struct
{
uint16_t numTaps; /** & lt; number of coefficients in the filter. */
q31_t *pState; /** & lt; points to the state variable array. The array is of length numTaps+blockSize-1. */
q31_t *pCoeffs; /** & lt; points to the coefficient array. The array is of length numTaps. */
q31_t mu; /** & lt; step size that controls filter coefficient updates. */
uint32_t postShift; /** & lt; bit shift applied to coefficients. */
} arm_lms_instance_q31;
/**
* @brief Processing function for Q31 LMS filter.
* @param[in] S points to an instance of the Q15 LMS filter structure.
* @param[in] pSrc points to the block of input data.
* @param[in] pRef points to the block of reference data.
* @param[out] pOut points to the block of output data.
* @param[out] pErr points to the block of error data.
* @param[in] blockSize number of samples to process.
*/
void arm_lms_q31(
const arm_lms_instance_q31 * S,
q31_t * pSrc,
q31_t * pRef,
q31_t * pOut,
q31_t * pErr,
uint32_t blockSize);
/**
* @brief Initialization function for Q31 LMS filter.
* @param[in] S points to an instance of the Q31 LMS filter structure.
* @param[in] numTaps number of filter coefficients.
* @param[in] pCoeffs points to coefficient buffer.
* @param[in] pState points to state buffer.
* @param[in] mu step size that controls filter coefficient updates.
* @param[in] blockSize number of samples to process.
* @param[in] postShift bit shift applied to coefficients.
*/
void arm_lms_init_q31(
arm_lms_instance_q31 * S,
uint16_t numTaps,
q31_t * pCoeffs,
q31_t * pState,
q31_t mu,
uint32_t blockSize,
uint32_t postShift);
/**
* @brief Instance structure for the floating-point normalized LMS filter.
*/
typedef struct
{
uint16_t numTaps; /** & lt; number of coefficients in the filter. */
float32_t *pState; /** & lt; points to the state variable array. The array is of length numTaps+blockSize-1. */
float32_t *pCoeffs; /** & lt; points to the coefficient array. The array is of length numTaps. */
float32_t mu; /** & lt; step size that control filter coefficient updates. */
float32_t energy; /** & lt; saves previous frame energy. */
float32_t x0; /** & lt; saves previous input sample. */
} arm_lms_norm_instance_f32;
/**
* @brief Processing function for floating-point normalized LMS filter.
* @param[in] S points to an instance of the floating-point normalized LMS filter structure.
* @param[in] pSrc points to the block of input data.
* @param[in] pRef points to the block of reference data.
* @param[out] pOut points to the block of output data.
* @param[out] pErr points to the block of error data.
* @param[in] blockSize number of samples to process.
*/
void arm_lms_norm_f32(
arm_lms_norm_instance_f32 * S,
float32_t * pSrc,
float32_t * pRef,
float32_t * pOut,
float32_t * pErr,
uint32_t blockSize);
/**
* @brief Initialization function for floating-point normalized LMS filter.
* @param[in] S points to an instance of the floating-point LMS filter structure.
* @param[in] numTaps number of filter coefficients.
* @param[in] pCoeffs points to coefficient buffer.
* @param[in] pState points to state buffer.
* @param[in] mu step size that controls filter coefficient updates.
* @param[in] blockSize number of samples to process.
*/
void arm_lms_norm_init_f32(
arm_lms_norm_instance_f32 * S,
uint16_t numTaps,
float32_t * pCoeffs,
float32_t * pState,
float32_t mu,
uint32_t blockSize);
/**
* @brief Instance structure for the Q31 normalized LMS filter.
*/
typedef struct
{
uint16_t numTaps; /** & lt; number of coefficients in the filter. */
q31_t *pState; /** & lt; points to the state variable array. The array is of length numTaps+blockSize-1. */
q31_t *pCoeffs; /** & lt; points to the coefficient array. The array is of length numTaps. */
q31_t mu; /** & lt; step size that controls filter coefficient updates. */
uint8_t postShift; /** & lt; bit shift applied to coefficients. */
q31_t *recipTable; /** & lt; points to the reciprocal initial value table. */
q31_t energy; /** & lt; saves previous frame energy. */
q31_t x0; /** & lt; saves previous input sample. */
} arm_lms_norm_instance_q31;
/**
* @brief Processing function for Q31 normalized LMS filter.
* @param[in] S points to an instance of the Q31 normalized LMS filter structure.
* @param[in] pSrc points to the block of input data.
* @param[in] pRef points to the block of reference data.
* @param[out] pOut points to the block of output data.
* @param[out] pErr points to the block of error data.
* @param[in] blockSize number of samples to process.
*/
void arm_lms_norm_q31(
arm_lms_norm_instance_q31 * S,
q31_t * pSrc,
q31_t * pRef,
q31_t * pOut,
q31_t * pErr,
uint32_t blockSize);
/**
* @brief Initialization function for Q31 normalized LMS filter.
* @param[in] S points to an instance of the Q31 normalized LMS filter structure.
* @param[in] numTaps number of filter coefficients.
* @param[in] pCoeffs points to coefficient buffer.
* @param[in] pState points to state buffer.
* @param[in] mu step size that controls filter coefficient updates.
* @param[in] blockSize number of samples to process.
* @param[in] postShift bit shift applied to coefficients.
*/
void arm_lms_norm_init_q31(
arm_lms_norm_instance_q31 * S,
uint16_t numTaps,
q31_t * pCoeffs,
q31_t * pState,
q31_t mu,
uint32_t blockSize,
uint8_t postShift);
/**
* @brief Instance structure for the Q15 normalized LMS filter.
*/
typedef struct
{
uint16_t numTaps; /** & lt; Number of coefficients in the filter. */
q15_t *pState; /** & lt; points to the state variable array. The array is of length numTaps+blockSize-1. */
q15_t *pCoeffs; /** & lt; points to the coefficient array. The array is of length numTaps. */
q15_t mu; /** & lt; step size that controls filter coefficient updates. */
uint8_t postShift; /** & lt; bit shift applied to coefficients. */
q15_t *recipTable; /** & lt; Points to the reciprocal initial value table. */
q15_t energy; /** & lt; saves previous frame energy. */
q15_t x0; /** & lt; saves previous input sample. */
} arm_lms_norm_instance_q15;
/**
* @brief Processing function for Q15 normalized LMS filter.
* @param[in] S points to an instance of the Q15 normalized LMS filter structure.
* @param[in] pSrc points to the block of input data.
* @param[in] pRef points to the block of reference data.
* @param[out] pOut points to the block of output data.
* @param[out] pErr points to the block of error data.
* @param[in] blockSize number of samples to process.
*/
void arm_lms_norm_q15(
arm_lms_norm_instance_q15 * S,
q15_t * pSrc,
q15_t * pRef,
q15_t * pOut,
q15_t * pErr,
uint32_t blockSize);
/**
* @brief Initialization function for Q15 normalized LMS filter.
* @param[in] S points to an instance of the Q15 normalized LMS filter structure.
* @param[in] numTaps number of filter coefficients.
* @param[in] pCoeffs points to coefficient buffer.
* @param[in] pState points to state buffer.
* @param[in] mu step size that controls filter coefficient updates.
* @param[in] blockSize number of samples to process.
* @param[in] postShift bit shift applied to coefficients.
*/
void arm_lms_norm_init_q15(
arm_lms_norm_instance_q15 * S,
uint16_t numTaps,
q15_t * pCoeffs,
q15_t * pState,
q15_t mu,
uint32_t blockSize,
uint8_t postShift);
/**
* @brief Correlation of floating-point sequences.
* @param[in] pSrcA points to the first input sequence.
* @param[in] srcALen length of the first input sequence.
* @param[in] pSrcB points to the second input sequence.
* @param[in] srcBLen length of the second input sequence.
* @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
*/
void arm_correlate_f32(
float32_t * pSrcA,
uint32_t srcALen,
float32_t * pSrcB,
uint32_t srcBLen,
float32_t * pDst);
/**
* @brief Correlation of Q15 sequences
* @param[in] pSrcA points to the first input sequence.
* @param[in] srcALen length of the first input sequence.
* @param[in] pSrcB points to the second input sequence.
* @param[in] srcBLen length of the second input sequence.
* @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
* @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
*/
void arm_correlate_opt_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst,
q15_t * pScratch);
/**
* @brief Correlation of Q15 sequences.
* @param[in] pSrcA points to the first input sequence.
* @param[in] srcALen length of the first input sequence.
* @param[in] pSrcB points to the second input sequence.
* @param[in] srcBLen length of the second input sequence.
* @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
*/
void arm_correlate_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst);
/**
* @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
* @param[in] pSrcA points to the first input sequence.
* @param[in] srcALen length of the first input sequence.
* @param[in] pSrcB points to the second input sequence.
* @param[in] srcBLen length of the second input sequence.
* @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
*/
void arm_correlate_fast_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst);
/**
* @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
* @param[in] pSrcA points to the first input sequence.
* @param[in] srcALen length of the first input sequence.
* @param[in] pSrcB points to the second input sequence.
* @param[in] srcBLen length of the second input sequence.
* @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
* @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
*/
void arm_correlate_fast_opt_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst,
q15_t * pScratch);
/**
* @brief Correlation of Q31 sequences.
* @param[in] pSrcA points to the first input sequence.
* @param[in] srcALen length of the first input sequence.
* @param[in] pSrcB points to the second input sequence.
* @param[in] srcBLen length of the second input sequence.
* @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
*/
void arm_correlate_q31(
q31_t * pSrcA,
uint32_t srcALen,
q31_t * pSrcB,
uint32_t srcBLen,
q31_t * pDst);
/**
* @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
* @param[in] pSrcA points to the first input sequence.
* @param[in] srcALen length of the first input sequence.
* @param[in] pSrcB points to the second input sequence.
* @param[in] srcBLen length of the second input sequence.
* @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
*/
void arm_correlate_fast_q31(
q31_t * pSrcA,
uint32_t srcALen,
q31_t * pSrcB,
uint32_t srcBLen,
q31_t * pDst);
/**
* @brief Correlation of Q7 sequences.
* @param[in] pSrcA points to the first input sequence.
* @param[in] srcALen length of the first input sequence.
* @param[in] pSrcB points to the second input sequence.
* @param[in] srcBLen length of the second input sequence.
* @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
* @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
* @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
*/
void arm_correlate_opt_q7(
q7_t * pSrcA,
uint32_t srcALen,
q7_t * pSrcB,
uint32_t srcBLen,
q7_t * pDst,
q15_t * pScratch1,
q15_t * pScratch2);
/**
* @brief Correlation of Q7 sequences.
* @param[in] pSrcA points to the first input sequence.
* @param[in] srcALen length of the first input sequence.
* @param[in] pSrcB points to the second input sequence.
* @param[in] srcBLen length of the second input sequence.
* @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
*/
void arm_correlate_q7(
q7_t * pSrcA,
uint32_t srcALen,
q7_t * pSrcB,
uint32_t srcBLen,
q7_t * pDst);
/**
* @brief Instance structure for the floating-point sparse FIR filter.
*/
typedef struct
{
uint16_t numTaps; /** & lt; number of coefficients in the filter. */
uint16_t stateIndex; /** & lt; state buffer index. Points to the oldest sample in the state buffer. */
float32_t *pState; /** & lt; points to the state buffer array. The array is of length maxDelay+blockSize-1. */
float32_t *pCoeffs; /** & lt; points to the coefficient array. The array is of length numTaps.*/
uint16_t maxDelay; /** & lt; maximum offset specified by the pTapDelay array. */
int32_t *pTapDelay; /** & lt; points to the array of delay values. The array is of length numTaps. */
} arm_fir_sparse_instance_f32;
/**
* @brief Instance structure for the Q31 sparse FIR filter.
*/
typedef struct
{
uint16_t numTaps; /** & lt; number of coefficients in the filter. */
uint16_t stateIndex; /** & lt; state buffer index. Points to the oldest sample in the state buffer. */
q31_t *pState; /** & lt; points to the state buffer array. The array is of length maxDelay+blockSize-1. */
q31_t *pCoeffs; /** & lt; points to the coefficient array. The array is of length numTaps.*/
uint16_t maxDelay; /** & lt; maximum offset specified by the pTapDelay array. */
int32_t *pTapDelay; /** & lt; points to the array of delay values. The array is of length numTaps. */
} arm_fir_sparse_instance_q31;
/**
* @brief Instance structure for the Q15 sparse FIR filter.
*/
typedef struct
{
uint16_t numTaps; /** & lt; number of coefficients in the filter. */
uint16_t stateIndex; /** & lt; state buffer index. Points to the oldest sample in the state buffer. */
q15_t *pState; /** & lt; points to the state buffer array. The array is of length maxDelay+blockSize-1. */
q15_t *pCoeffs; /** & lt; points to the coefficient array. The array is of length numTaps.*/
uint16_t maxDelay; /** & lt; maximum offset specified by the pTapDelay array. */
int32_t *pTapDelay; /** & lt; points to the array of delay values. The array is of length numTaps. */
} arm_fir_sparse_instance_q15;
/**
* @brief Instance structure for the Q7 sparse FIR filter.
*/
typedef struct
{
uint16_t numTaps; /** & lt; number of coefficients in the filter. */
uint16_t stateIndex; /** & lt; state buffer index. Points to the oldest sample in the state buffer. */
q7_t *pState; /** & lt; points to the state buffer array. The array is of length maxDelay+blockSize-1. */
q7_t *pCoeffs; /** & lt; points to the coefficient array. The array is of length numTaps.*/
uint16_t maxDelay; /** & lt; maximum offset specified by the pTapDelay array. */
int32_t *pTapDelay; /** & lt; points to the array of delay values. The array is of length numTaps. */
} arm_fir_sparse_instance_q7;
/**
* @brief Processing function for the floating-point sparse FIR filter.
* @param[in] S points to an instance of the floating-point sparse FIR structure.
* @param[in] pSrc points to the block of input data.
* @param[out] pDst points to the block of output data
* @param[in] pScratchIn points to a temporary buffer of size blockSize.
* @param[in] blockSize number of input samples to process per call.
*/
void arm_fir_sparse_f32(
arm_fir_sparse_instance_f32 * S,
float32_t * pSrc,
float32_t * pDst,
float32_t * pScratchIn,
uint32_t blockSize);
/**
* @brief Initialization function for the floating-point sparse FIR filter.
* @param[in,out] S points to an instance of the floating-point sparse FIR structure.
* @param[in] numTaps number of nonzero coefficients in the filter.
* @param[in] pCoeffs points to the array of filter coefficients.
* @param[in] pState points to the state buffer.
* @param[in] pTapDelay points to the array of offset times.
* @param[in] maxDelay maximum offset time supported.
* @param[in] blockSize number of samples that will be processed per block.
*/
void arm_fir_sparse_init_f32(
arm_fir_sparse_instance_f32 * S,
uint16_t numTaps,
float32_t * pCoeffs,
float32_t * pState,
int32_t * pTapDelay,
uint16_t maxDelay,
uint32_t blockSize);
/**
* @brief Processing function for the Q31 sparse FIR filter.
* @param[in] S points to an instance of the Q31 sparse FIR structure.
* @param[in] pSrc points to the block of input data.
* @param[out] pDst points to the block of output data
* @param[in] pScratchIn points to a temporary buffer of size blockSize.
* @param[in] blockSize number of input samples to process per call.
*/
void arm_fir_sparse_q31(
arm_fir_sparse_instance_q31 * S,
q31_t * pSrc,
q31_t * pDst,
q31_t * pScratchIn,
uint32_t blockSize);
/**
* @brief Initialization function for the Q31 sparse FIR filter.
* @param[in,out] S points to an instance of the Q31 sparse FIR structure.
* @param[in] numTaps number of nonzero coefficients in the filter.
* @param[in] pCoeffs points to the array of filter coefficients.
* @param[in] pState points to the state buffer.
* @param[in] pTapDelay points to the array of offset times.
* @param[in] maxDelay maximum offset time supported.
* @param[in] blockSize number of samples that will be processed per block.
*/
void arm_fir_sparse_init_q31(
arm_fir_sparse_instance_q31 * S,
uint16_t numTaps,
q31_t * pCoeffs,
q31_t * pState,
int32_t * pTapDelay,
uint16_t maxDelay,
uint32_t blockSize);
/**
* @brief Processing function for the Q15 sparse FIR filter.
* @param[in] S points to an instance of the Q15 sparse FIR structure.
* @param[in] pSrc points to the block of input data.
* @param[out] pDst points to the block of output data
* @param[in] pScratchIn points to a temporary buffer of size blockSize.
* @param[in] pScratchOut points to a temporary buffer of size blockSize.
* @param[in] blockSize number of input samples to process per call.
*/
void arm_fir_sparse_q15(
arm_fir_sparse_instance_q15 * S,
q15_t * pSrc,
q15_t * pDst,
q15_t * pScratchIn,
q31_t * pScratchOut,
uint32_t blockSize);
/**
* @brief Initialization function for the Q15 sparse FIR filter.
* @param[in,out] S points to an instance of the Q15 sparse FIR structure.
* @param[in] numTaps number of nonzero coefficients in the filter.
* @param[in] pCoeffs points to the array of filter coefficients.
* @param[in] pState points to the state buffer.
* @param[in] pTapDelay points to the array of offset times.
* @param[in] maxDelay maximum offset time supported.
* @param[in] blockSize number of samples that will be processed per block.
*/
void arm_fir_sparse_init_q15(
arm_fir_sparse_instance_q15 * S,
uint16_t numTaps,
q15_t * pCoeffs,
q15_t * pState,
int32_t * pTapDelay,
uint16_t maxDelay,
uint32_t blockSize);
/**
* @brief Processing function for the Q7 sparse FIR filter.
* @param[in] S points to an instance of the Q7 sparse FIR structure.
* @param[in] pSrc points to the block of input data.
* @param[out] pDst points to the block of output data
* @param[in] pScratchIn points to a temporary buffer of size blockSize.
* @param[in] pScratchOut points to a temporary buffer of size blockSize.
* @param[in] blockSize number of input samples to process per call.
*/
void arm_fir_sparse_q7(
arm_fir_sparse_instance_q7 * S,
q7_t * pSrc,
q7_t * pDst,
q7_t * pScratchIn,
q31_t * pScratchOut,
uint32_t blockSize);
/**
* @brief Initialization function for the Q7 sparse FIR filter.
* @param[in,out] S points to an instance of the Q7 sparse FIR structure.
* @param[in] numTaps number of nonzero coefficients in the filter.
* @param[in] pCoeffs points to the array of filter coefficients.
* @param[in] pState points to the state buffer.
* @param[in] pTapDelay points to the array of offset times.
* @param[in] maxDelay maximum offset time supported.
* @param[in] blockSize number of samples that will be processed per block.
*/
void arm_fir_sparse_init_q7(
arm_fir_sparse_instance_q7 * S,
uint16_t numTaps,
q7_t * pCoeffs,
q7_t * pState,
int32_t * pTapDelay,
uint16_t maxDelay,
uint32_t blockSize);
/**
* @brief Floating-point sin_cos function.
* @param[in] theta input value in degrees
* @param[out] pSinVal points to the processed sine output.
* @param[out] pCosVal points to the processed cos output.
*/
void arm_sin_cos_f32(
float32_t theta,
float32_t * pSinVal,
float32_t * pCosVal);
/**
* @brief Q31 sin_cos function.
* @param[in] theta scaled input value in degrees
* @param[out] pSinVal points to the processed sine output.
* @param[out] pCosVal points to the processed cosine output.
*/
void arm_sin_cos_q31(
q31_t theta,
q31_t * pSinVal,
q31_t * pCosVal);
/**
* @brief Floating-point complex conjugate.
* @param[in] pSrc points to the input vector
* @param[out] pDst points to the output vector
* @param[in] numSamples number of complex samples in each vector
*/
void arm_cmplx_conj_f32(
float32_t * pSrc,
float32_t * pDst,
uint32_t numSamples);
/**
* @brief Q31 complex conjugate.
* @param[in] pSrc points to the input vector
* @param[out] pDst points to the output vector
* @param[in] numSamples number of complex samples in each vector
*/
void arm_cmplx_conj_q31(
q31_t * pSrc,
q31_t * pDst,
uint32_t numSamples);
/**
* @brief Q15 complex conjugate.
* @param[in] pSrc points to the input vector
* @param[out] pDst points to the output vector
* @param[in] numSamples number of complex samples in each vector
*/
void arm_cmplx_conj_q15(
q15_t * pSrc,
q15_t * pDst,
uint32_t numSamples);
/**
* @brief Floating-point complex magnitude squared
* @param[in] pSrc points to the complex input vector
* @param[out] pDst points to the real output vector
* @param[in] numSamples number of complex samples in the input vector
*/
void arm_cmplx_mag_squared_f32(
float32_t * pSrc,
float32_t * pDst,
uint32_t numSamples);
/**
* @brief Q31 complex magnitude squared
* @param[in] pSrc points to the complex input vector
* @param[out] pDst points to the real output vector
* @param[in] numSamples number of complex samples in the input vector
*/
void arm_cmplx_mag_squared_q31(
q31_t * pSrc,
q31_t * pDst,
uint32_t numSamples);
/**
* @brief Q15 complex magnitude squared
* @param[in] pSrc points to the complex input vector
* @param[out] pDst points to the real output vector
* @param[in] numSamples number of complex samples in the input vector
*/
void arm_cmplx_mag_squared_q15(
q15_t * pSrc,
q15_t * pDst,
uint32_t numSamples);
/**
* @ingroup groupController
*/
/**
* @defgroup PID PID Motor Control
*
* A Proportional Integral Derivative (PID) controller is a generic feedback control
* loop mechanism widely used in industrial control systems.
* A PID controller is the most commonly used type of feedback controller.
*
* This set of functions implements (PID) controllers
* for Q15, Q31, and floating-point data types. The functions operate on a single sample
* of data and each call to the function returns a single processed value.
* & lt; code & gt; S & lt; /code & gt; points to an instance of the PID control data structure. & lt; code & gt; in & lt; /code & gt;
* is the input sample value. The functions return the output value.
*
* \par Algorithm:
* & lt; pre & gt;
* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
* A0 = Kp + Ki + Kd
* A1 = (-Kp ) - (2 * Kd )
* A2 = Kd & lt; /pre & gt;
*
* \par
* where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
*
* \par
* \image html PID.gif " Proportional Integral Derivative Controller "
*
* \par
* The PID controller calculates an " error " value as the difference between
* the measured output and the reference input.
* The controller attempts to minimize the error by adjusting the process control inputs.
* The proportional value determines the reaction to the current error,
* the integral value determines the reaction based on the sum of recent errors,
* and the derivative value determines the reaction based on the rate at which the error has been changing.
*
* \par Instance Structure
* The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
* A separate instance structure must be defined for each PID Controller.
* There are separate instance structure declarations for each of the 3 supported data types.
*
* \par Reset Functions
* There is also an associated reset function for each data type which clears the state array.
*
* \par Initialization Functions
* There is also an associated initialization function for each data type.
* The initialization function performs the following operations:
* - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
* - Zeros out the values in the state buffer.
*
* \par
* Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
*
* \par Fixed-Point Behavior
* Care must be taken when using the fixed-point versions of the PID Controller functions.
* In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
* Refer to the function specific documentation below for usage guidelines.
*/
/**
* @addtogroup PID
* @{
*/
/**
* @brief Process function for the floating-point PID Control.
* @param[in,out] S is an instance of the floating-point PID Control structure
* @param[in] in input sample to process
* @return out processed output sample.
*/
static __INLINE float32_t arm_pid_f32(
arm_pid_instance_f32 * S,
float32_t in)
{
float32_t out;
/* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
out = (S- & gt; A0 * in) +
(S- & gt; A1 * S- & gt; state[0]) + (S- & gt; A2 * S- & gt; state[1]) + (S- & gt; state[2]);
/* Update state */
S- & gt; state[1] = S- & gt; state[0];
S- & gt; state[0] = in;
S- & gt; state[2] = out;
/* return to application */
return (out);
}
/**
* @brief Process function for the Q31 PID Control.
* @param[in,out] S points to an instance of the Q31 PID Control structure
* @param[in] in input sample to process
* @return out processed output sample.
*
* & lt; b & gt; Scaling and Overflow Behavior: & lt; /b & gt;
* \par
* The function is implemented using an internal 64-bit accumulator.
* The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
* Thus, if the accumulator result overflows it wraps around rather than clip.
* In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
* After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
*/
static __INLINE q31_t arm_pid_q31(
arm_pid_instance_q31 * S,
q31_t in)
{
q63_t acc;
q31_t out;
/* acc = A0 * x[n] */
acc = (q63_t) S- & gt; A0 * in;
/* acc += A1 * x[n-1] */
acc += (q63_t) S- & gt; A1 * S- & gt; state[0];
/* acc += A2 * x[n-2] */
acc += (q63_t) S- & gt; A2 * S- & gt; state[1];
/* convert output to 1.31 format to add y[n-1] */
out = (q31_t) (acc & gt; & gt; 31u);
/* out += y[n-1] */
out += S- & gt; state[2];
/* Update state */
S- & gt; state[1] = S- & gt; state[0];
S- & gt; state[0] = in;
S- & gt; state[2] = out;
/* return to application */
return (out);
}
/**
* @brief Process function for the Q15 PID Control.
* @param[in,out] S points to an instance of the Q15 PID Control structure
* @param[in] in input sample to process
* @return out processed output sample.
*
* & lt; b & gt; Scaling and Overflow Behavior: & lt; /b & gt;
* \par
* The function is implemented using a 64-bit internal accumulator.
* Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
* The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
* There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
* After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
* Lastly, the accumulator is saturated to yield a result in 1.15 format.
*/
static __INLINE q15_t arm_pid_q15(
arm_pid_instance_q15 * S,
q15_t in)
{
q63_t acc;
q15_t out;
#ifndef ARM_MATH_CM0_FAMILY
__SIMD32_TYPE *vstate;
/* Implementation of PID controller */
/* acc = A0 * x[n] */
acc = (q31_t) __SMUAD((uint32_t)S- & gt; A0, (uint32_t)in);
/* acc += A1 * x[n-1] + A2 * x[n-2] */
vstate = __SIMD32_CONST(S- & gt; state);
acc = (q63_t)__SMLALD((uint32_t)S- & gt; A1, (uint32_t)*vstate, (uint64_t)acc);
#else
/* acc = A0 * x[n] */
acc = ((q31_t) S- & gt; A0) * in;
/* acc += A1 * x[n-1] + A2 * x[n-2] */
acc += (q31_t) S- & gt; A1 * S- & gt; state[0];
acc += (q31_t) S- & gt; A2 * S- & gt; state[1];
#endif
/* acc += y[n-1] */
acc += (q31_t) S- & gt; state[2] & lt; & lt; 15;
/* saturate the output */
out = (q15_t) (__SSAT((acc & gt; & gt; 15), 16));
/* Update state */
S- & gt; state[1] = S- & gt; state[0];
S- & gt; state[0] = in;
S- & gt; state[2] = out;
/* return to application */
return (out);
}
/**
* @} end of PID group
*/
/**
* @brief Floating-point matrix inverse.
* @param[in] src points to the instance of the input floating-point matrix structure.
* @param[out] dst points to the instance of the output floating-point matrix structure.
* @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
* If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
*/
arm_status arm_mat_inverse_f32(
const arm_matrix_instance_f32 * src,
arm_matrix_instance_f32 * dst);
/**
* @brief Floating-point matrix inverse.
* @param[in] src points to the instance of the input floating-point matrix structure.
* @param[out] dst points to the instance of the output floating-point matrix structure.
* @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
* If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
*/
arm_status arm_mat_inverse_f64(
const arm_matrix_instance_f64 * src,
arm_matrix_instance_f64 * dst);
/**
* @ingroup groupController
*/
/**
* @defgroup clarke Vector Clarke Transform
* Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
* Generally the Clarke transform uses three-phase currents & lt; code & gt; Ia, Ib and Ic & lt; /code & gt; to calculate currents
* in the two-phase orthogonal stator axis & lt; code & gt; Ialpha & lt; /code & gt; and & lt; code & gt; Ibeta & lt; /code & gt; .
* When & lt; code & gt; Ialpha & lt; /code & gt; is superposed with & lt; code & gt; Ia & lt; /code & gt; as shown in the figure below
* \image html clarke.gif Stator current space vector and its components in (a,b).
* and & lt; code & gt; Ia + Ib + Ic = 0 & lt; /code & gt; , in this condition & lt; code & gt; Ialpha & lt; /code & gt; and & lt; code & gt; Ibeta & lt; /code & gt;
* can be calculated using only & lt; code & gt; Ia & lt; /code & gt; and & lt; code & gt; Ib & lt; /code & gt; .
*
* The function operates on a single sample of data and each call to the function returns the processed output.
* The library provides separate functions for Q31 and floating-point data types.
* \par Algorithm
* \image html clarkeFormula.gif
* where & lt; code & gt; Ia & lt; /code & gt; and & lt; code & gt; Ib & lt; /code & gt; are the instantaneous stator phases and
* & lt; code & gt; pIalpha & lt; /code & gt; and & lt; code & gt; pIbeta & lt; /code & gt; are the two coordinates of time invariant vector.
* \par Fixed-Point Behavior
* Care must be taken when using the Q31 version of the Clarke transform.
* In particular, the overflow and saturation behavior of the accumulator used must be considered.
* Refer to the function specific documentation below for usage guidelines.
*/
/**
* @addtogroup clarke
* @{
*/
/**
*
* @brief Floating-point Clarke transform
* @param[in] Ia input three-phase coordinate & lt; code & gt; a & lt; /code & gt;
* @param[in] Ib input three-phase coordinate & lt; code & gt; b & lt; /code & gt;
* @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
* @param[out] pIbeta points to output two-phase orthogonal vector axis beta
*/
static __INLINE void arm_clarke_f32(
float32_t Ia,
float32_t Ib,
float32_t * pIalpha,
float32_t * pIbeta)
{
/* Calculate pIalpha using the equation, pIalpha = Ia */
*pIalpha = Ia;
/* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
*pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
}
/**
* @brief Clarke transform for Q31 version
* @param[in] Ia input three-phase coordinate & lt; code & gt; a & lt; /code & gt;
* @param[in] Ib input three-phase coordinate & lt; code & gt; b & lt; /code & gt;
* @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
* @param[out] pIbeta points to output two-phase orthogonal vector axis beta
*
* & lt; b & gt; Scaling and Overflow Behavior: & lt; /b & gt;
* \par
* The function is implemented using an internal 32-bit accumulator.
* The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
* There is saturation on the addition, hence there is no risk of overflow.
*/
static __INLINE void arm_clarke_q31(
q31_t Ia,
q31_t Ib,
q31_t * pIalpha,
q31_t * pIbeta)
{
q31_t product1, product2; /* Temporary variables used to store intermediate results */
/* Calculating pIalpha from Ia by equation pIalpha = Ia */
*pIalpha = Ia;
/* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) & gt; & gt; 30);
/* Intermediate product is calculated by (2/sqrt(3) * Ib) */
product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) & gt; & gt; 30);
/* pIbeta is calculated by adding the intermediate products */
*pIbeta = __QADD(product1, product2);
}
/**
* @} end of clarke group
*/
/**
* @brief Converts the elements of the Q7 vector to Q31 vector.
* @param[in] pSrc input pointer
* @param[out] pDst output pointer
* @param[in] blockSize number of samples to process
*/
void arm_q7_to_q31(
q7_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
/**
* @ingroup groupController
*/
/**
* @defgroup inv_clarke Vector Inverse Clarke Transform
* Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
*
* The function operates on a single sample of data and each call to the function returns the processed output.
* The library provides separate functions for Q31 and floating-point data types.
* \par Algorithm
* \image html clarkeInvFormula.gif
* where & lt; code & gt; pIa & lt; /code & gt; and & lt; code & gt; pIb & lt; /code & gt; are the instantaneous stator phases and
* & lt; code & gt; Ialpha & lt; /code & gt; and & lt; code & gt; Ibeta & lt; /code & gt; are the two coordinates of time invariant vector.
* \par Fixed-Point Behavior
* Care must be taken when using the Q31 version of the Clarke transform.
* In particular, the overflow and saturation behavior of the accumulator used must be considered.
* Refer to the function specific documentation below for usage guidelines.
*/
/**
* @addtogroup inv_clarke
* @{
*/
/**
* @brief Floating-point Inverse Clarke transform
* @param[in] Ialpha input two-phase orthogonal vector axis alpha
* @param[in] Ibeta input two-phase orthogonal vector axis beta
* @param[out] pIa points to output three-phase coordinate & lt; code & gt; a & lt; /code & gt;
* @param[out] pIb points to output three-phase coordinate & lt; code & gt; b & lt; /code & gt;
*/
static __INLINE void arm_inv_clarke_f32(
float32_t Ialpha,
float32_t Ibeta,
float32_t * pIa,
float32_t * pIb)
{
/* Calculating pIa from Ialpha by equation pIa = Ialpha */
*pIa = Ialpha;
/* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
*pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
}
/**
* @brief Inverse Clarke transform for Q31 version
* @param[in] Ialpha input two-phase orthogonal vector axis alpha
* @param[in] Ibeta input two-phase orthogonal vector axis beta
* @param[out] pIa points to output three-phase coordinate & lt; code & gt; a & lt; /code & gt;
* @param[out] pIb points to output three-phase coordinate & lt; code & gt; b & lt; /code & gt;
*
* & lt; b & gt; Scaling and Overflow Behavior: & lt; /b & gt;
* \par
* The function is implemented using an internal 32-bit accumulator.
* The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
* There is saturation on the subtraction, hence there is no risk of overflow.
*/
static __INLINE void arm_inv_clarke_q31(
q31_t Ialpha,
q31_t Ibeta,
q31_t * pIa,
q31_t * pIb)
{
q31_t product1, product2; /* Temporary variables used to store intermediate results */
/* Calculating pIa from Ialpha by equation pIa = Ialpha */
*pIa = Ialpha;
/* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) & gt; & gt; 31);
/* Intermediate product is calculated by (1/sqrt(3) * pIb) */
product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) & gt; & gt; 31);
/* pIb is calculated by subtracting the products */
*pIb = __QSUB(product2, product1);
}
/**
* @} end of inv_clarke group
*/
/**
* @brief Converts the elements of the Q7 vector to Q15 vector.
* @param[in] pSrc input pointer
* @param[out] pDst output pointer
* @param[in] blockSize number of samples to process
*/
void arm_q7_to_q15(
q7_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
/**
* @ingroup groupController
*/
/**
* @defgroup park Vector Park Transform
*
* Forward Park transform converts the input two-coordinate vector to flux and torque components.
* The Park transform can be used to realize the transformation of the & lt; code & gt; Ialpha & lt; /code & gt; and the & lt; code & gt; Ibeta & lt; /code & gt; currents
* from the stationary to the moving reference frame and control the spatial relationship between
* the stator vector current and rotor flux vector.
* If we consider the d axis aligned with the rotor flux, the diagram below shows the
* current vector and the relationship from the two reference frames:
* \image html park.gif " Stator current space vector and its component in (a,b) and in the d,q rotating reference frame "
*
* The function operates on a single sample of data and each call to the function returns the processed output.
* The library provides separate functions for Q31 and floating-point data types.
* \par Algorithm
* \image html parkFormula.gif
* where & lt; code & gt; Ialpha & lt; /code & gt; and & lt; code & gt; Ibeta & lt; /code & gt; are the stator vector components,
* & lt; code & gt; pId & lt; /code & gt; and & lt; code & gt; pIq & lt; /code & gt; are rotor vector components and & lt; code & gt; cosVal & lt; /code & gt; and & lt; code & gt; sinVal & lt; /code & gt; are the
* cosine and sine values of theta (rotor flux position).
* \par Fixed-Point Behavior
* Care must be taken when using the Q31 version of the Park transform.
* In particular, the overflow and saturation behavior of the accumulator used must be considered.
* Refer to the function specific documentation below for usage guidelines.
*/
/**
* @addtogroup park
* @{
*/
/**
* @brief Floating-point Park transform
* @param[in] Ialpha input two-phase vector coordinate alpha
* @param[in] Ibeta input two-phase vector coordinate beta
* @param[out] pId points to output rotor reference frame d
* @param[out] pIq points to output rotor reference frame q
* @param[in] sinVal sine value of rotation angle theta
* @param[in] cosVal cosine value of rotation angle theta
*
* The function implements the forward Park transform.
*
*/
static __INLINE void arm_park_f32(
float32_t Ialpha,
float32_t Ibeta,
float32_t * pId,
float32_t * pIq,
float32_t sinVal,
float32_t cosVal)
{
/* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
*pId = Ialpha * cosVal + Ibeta * sinVal;
/* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
*pIq = -Ialpha * sinVal + Ibeta * cosVal;
}
/**
* @brief Park transform for Q31 version
* @param[in] Ialpha input two-phase vector coordinate alpha
* @param[in] Ibeta input two-phase vector coordinate beta
* @param[out] pId points to output rotor reference frame d
* @param[out] pIq points to output rotor reference frame q
* @param[in] sinVal sine value of rotation angle theta
* @param[in] cosVal cosine value of rotation angle theta
*
* & lt; b & gt; Scaling and Overflow Behavior: & lt; /b & gt;
* \par
* The function is implemented using an internal 32-bit accumulator.
* The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
* There is saturation on the addition and subtraction, hence there is no risk of overflow.
*/
static __INLINE void arm_park_q31(
q31_t Ialpha,
q31_t Ibeta,
q31_t * pId,
q31_t * pIq,
q31_t sinVal,
q31_t cosVal)
{
q31_t product1, product2; /* Temporary variables used to store intermediate results */
q31_t product3, product4; /* Temporary variables used to store intermediate results */
/* Intermediate product is calculated by (Ialpha * cosVal) */
product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) & gt; & gt; 31);
/* Intermediate product is calculated by (Ibeta * sinVal) */
product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) & gt; & gt; 31);
/* Intermediate product is calculated by (Ialpha * sinVal) */
product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) & gt; & gt; 31);
/* Intermediate product is calculated by (Ibeta * cosVal) */
product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) & gt; & gt; 31);
/* Calculate pId by adding the two intermediate products 1 and 2 */
*pId = __QADD(product1, product2);
/* Calculate pIq by subtracting the two intermediate products 3 from 4 */
*pIq = __QSUB(product4, product3);
}
/**
* @} end of park group
*/
/**
* @brief Converts the elements of the Q7 vector to floating-point vector.
* @param[in] pSrc is input pointer
* @param[out] pDst is output pointer
* @param[in] blockSize is the number of samples to process
*/
void arm_q7_to_float(
q7_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
/**
* @ingroup groupController
*/
/**
* @defgroup inv_park Vector Inverse Park transform
* Inverse Park transform converts the input flux and torque components to two-coordinate vector.
*
* The function operates on a single sample of data and each call to the function returns the processed output.
* The library provides separate functions for Q31 and floating-point data types.
* \par Algorithm
* \image html parkInvFormula.gif
* where & lt; code & gt; pIalpha & lt; /code & gt; and & lt; code & gt; pIbeta & lt; /code & gt; are the stator vector components,
* & lt; code & gt; Id & lt; /code & gt; and & lt; code & gt; Iq & lt; /code & gt; are rotor vector components and & lt; code & gt; cosVal & lt; /code & gt; and & lt; code & gt; sinVal & lt; /code & gt; are the
* cosine and sine values of theta (rotor flux position).
* \par Fixed-Point Behavior
* Care must be taken when using the Q31 version of the Park transform.
* In particular, the overflow and saturation behavior of the accumulator used must be considered.
* Refer to the function specific documentation below for usage guidelines.
*/
/**
* @addtogroup inv_park
* @{
*/
/**
* @brief Floating-point Inverse Park transform
* @param[in] Id input coordinate of rotor reference frame d
* @param[in] Iq input coordinate of rotor reference frame q
* @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
* @param[out] pIbeta points to output two-phase orthogonal vector axis beta
* @param[in] sinVal sine value of rotation angle theta
* @param[in] cosVal cosine value of rotation angle theta
*/
static __INLINE void arm_inv_park_f32(
float32_t Id,
float32_t Iq,
float32_t * pIalpha,
float32_t * pIbeta,
float32_t sinVal,
float32_t cosVal)
{
/* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
*pIalpha = Id * cosVal - Iq * sinVal;
/* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
*pIbeta = Id * sinVal + Iq * cosVal;
}
/**
* @brief Inverse Park transform for Q31 version
* @param[in] Id input coordinate of rotor reference frame d
* @param[in] Iq input coordinate of rotor reference frame q
* @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
* @param[out] pIbeta points to output two-phase orthogonal vector axis beta
* @param[in] sinVal sine value of rotation angle theta
* @param[in] cosVal cosine value of rotation angle theta
*
* & lt; b & gt; Scaling and Overflow Behavior: & lt; /b & gt;
* \par
* The function is implemented using an internal 32-bit accumulator.
* The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
* There is saturation on the addition, hence there is no risk of overflow.
*/
static __INLINE void arm_inv_park_q31(
q31_t Id,
q31_t Iq,
q31_t * pIalpha,
q31_t * pIbeta,
q31_t sinVal,
q31_t cosVal)
{
q31_t product1, product2; /* Temporary variables used to store intermediate results */
q31_t product3, product4; /* Temporary variables used to store intermediate results */
/* Intermediate product is calculated by (Id * cosVal) */
product1 = (q31_t) (((q63_t) (Id) * (cosVal)) & gt; & gt; 31);
/* Intermediate product is calculated by (Iq * sinVal) */
product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) & gt; & gt; 31);
/* Intermediate product is calculated by (Id * sinVal) */
product3 = (q31_t) (((q63_t) (Id) * (sinVal)) & gt; & gt; 31);
/* Intermediate product is calculated by (Iq * cosVal) */
product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) & gt; & gt; 31);
/* Calculate pIalpha by using the two intermediate products 1 and 2 */
*pIalpha = __QSUB(product1, product2);
/* Calculate pIbeta by using the two intermediate products 3 and 4 */
*pIbeta = __QADD(product4, product3);
}
/**
* @} end of Inverse park group
*/
/**
* @brief Converts the elements of the Q31 vector to floating-point vector.
* @param[in] pSrc is input pointer
* @param[out] pDst is output pointer
* @param[in] blockSize is the number of samples to process
*/
void arm_q31_to_float(
q31_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
/**
* @ingroup groupInterpolation
*/
/**
* @defgroup LinearInterpolate Linear Interpolation
*
* Linear interpolation is a method of curve fitting using linear polynomials.
* Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
*
* \par
* \image html LinearInterp.gif " Linear interpolation "
*
* \par
* A Linear Interpolate function calculates an output value(y), for the input(x)
* using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
*
* \par Algorithm:
* & lt; pre & gt;
* y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
* where x0, x1 are nearest values of input x
* y0, y1 are nearest values to output y
* & lt; /pre & gt;
*
* \par
* This set of functions implements Linear interpolation process
* for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
* sample of data and each call to the function returns a single processed value.
* & lt; code & gt; S & lt; /code & gt; points to an instance of the Linear Interpolate function data structure.
* & lt; code & gt; x & lt; /code & gt; is the input sample value. The functions returns the output value.
*
* \par
* if x is outside of the table boundary, Linear interpolation returns first value of the table
* if x is below input range and returns last value of table if x is above range.
*/
/**
* @addtogroup LinearInterpolate
* @{
*/
/**
* @brief Process function for the floating-point Linear Interpolation Function.
* @param[in,out] S is an instance of the floating-point Linear Interpolation structure
* @param[in] x input sample to process
* @return y processed output sample.
*
*/
static __INLINE float32_t arm_linear_interp_f32(
arm_linear_interp_instance_f32 * S,
float32_t x)
{
float32_t y;
float32_t x0, x1; /* Nearest input values */
float32_t y0, y1; /* Nearest output values */
float32_t xSpacing = S- & gt; xSpacing; /* spacing between input values */
int32_t i; /* Index variable */
float32_t *pYData = S- & gt; pYData; /* pointer to output table */
/* Calculation of index */
i = (int32_t) ((x - S- & gt; x1) / xSpacing);
if(i & lt; 0)
{
/* Iniatilize output for below specified range as least output value of table */
y = pYData[0];
}
else if((uint32_t)i & gt; = S- & gt; nValues)
{
/* Iniatilize output for above specified range as last output value of table */
y = pYData[S- & gt; nValues - 1];
}
else
{
/* Calculation of nearest input values */
x0 = S- & gt; x1 + i * xSpacing;
x1 = S- & gt; x1 + (i + 1) * xSpacing;
/* Read of nearest output values */
y0 = pYData[i];
y1 = pYData[i + 1];
/* Calculation of output */
y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
}
/* returns output value */
return (y);
}
/**
*
* @brief Process function for the Q31 Linear Interpolation Function.
* @param[in] pYData pointer to Q31 Linear Interpolation table
* @param[in] x input sample to process
* @param[in] nValues number of table values
* @return y processed output sample.
*
* \par
* Input sample & lt; code & gt; x & lt; /code & gt; is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
* This function can support maximum of table size 2^12.
*
*/
static __INLINE q31_t arm_linear_interp_q31(
q31_t * pYData,
q31_t x,
uint32_t nValues)
{
q31_t y; /* output */
q31_t y0, y1; /* Nearest output values */
q31_t fract; /* fractional part */
int32_t index; /* Index to read nearest output values */
/* Input is in 12.20 format */
/* 12 bits for the table index */
/* Index value calculation */
index = ((x & (q31_t)0xFFF00000) & gt; & gt; 20);
if(index & gt; = (int32_t)(nValues - 1))
{
return (pYData[nValues - 1]);
}
else if(index & lt; 0)
{
return (pYData[0]);
}
else
{
/* 20 bits for the fractional part */
/* shift left by 11 to keep fract in 1.31 format */
fract = (x & 0x000FFFFF) & lt; & lt; 11;
/* Read two nearest output values from the index in 1.31(q31) format */
y0 = pYData[index];
y1 = pYData[index + 1];
/* Calculation of y0 * (1-fract) and y is in 2.30 format */
y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) & gt; & gt; 32));
/* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
y += ((q31_t) (((q63_t) y1 * fract) & gt; & gt; 32));
/* Convert y to 1.31 format */
return (y & lt; & lt; 1u);
}
}
/**
*
* @brief Process function for the Q15 Linear Interpolation Function.
* @param[in] pYData pointer to Q15 Linear Interpolation table
* @param[in] x input sample to process
* @param[in] nValues number of table values
* @return y processed output sample.
*
* \par
* Input sample & lt; code & gt; x & lt; /code & gt; is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
* This function can support maximum of table size 2^12.
*
*/
static __INLINE q15_t arm_linear_interp_q15(
q15_t * pYData,
q31_t x,
uint32_t nValues)
{
q63_t y; /* output */
q15_t y0, y1; /* Nearest output values */
q31_t fract; /* fractional part */
int32_t index; /* Index to read nearest output values */
/* Input is in 12.20 format */
/* 12 bits for the table index */
/* Index value calculation */
index = ((x & (int32_t)0xFFF00000) & gt; & gt; 20);
if(index & gt; = (int32_t)(nValues - 1))
{
return (pYData[nValues - 1]);
}
else if(index & lt; 0)
{
return (pYData[0]);
}
else
{
/* 20 bits for the fractional part */
/* fract is in 12.20 format */
fract = (x & 0x000FFFFF);
/* Read two nearest output values from the index */
y0 = pYData[index];
y1 = pYData[index + 1];
/* Calculation of y0 * (1-fract) and y is in 13.35 format */
y = ((q63_t) y0 * (0xFFFFF - fract));
/* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
y += ((q63_t) y1 * (fract));
/* convert y to 1.15 format */
return (q15_t) (y & gt; & gt; 20);
}
}
/**
*
* @brief Process function for the Q7 Linear Interpolation Function.
* @param[in] pYData pointer to Q7 Linear Interpolation table
* @param[in] x input sample to process
* @param[in] nValues number of table values
* @return y processed output sample.
*
* \par
* Input sample & lt; code & gt; x & lt; /code & gt; is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
* This function can support maximum of table size 2^12.
*/
static __INLINE q7_t arm_linear_interp_q7(
q7_t * pYData,
q31_t x,
uint32_t nValues)
{
q31_t y; /* output */
q7_t y0, y1; /* Nearest output values */
q31_t fract; /* fractional part */
uint32_t index; /* Index to read nearest output values */
/* Input is in 12.20 format */
/* 12 bits for the table index */
/* Index value calculation */
if (x & lt; 0)
{
return (pYData[0]);
}
index = (x & gt; & gt; 20) & 0xfff;
if(index & gt; = (nValues - 1))
{
return (pYData[nValues - 1]);
}
else
{
/* 20 bits for the fractional part */
/* fract is in 12.20 format */
fract = (x & 0x000FFFFF);
/* Read two nearest output values from the index and are in 1.7(q7) format */
y0 = pYData[index];
y1 = pYData[index + 1];
/* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
y = ((y0 * (0xFFFFF - fract)));
/* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
y += (y1 * fract);
/* convert y to 1.7(q7) format */
return (q7_t) (y & gt; & gt; 20);
}
}
/**
* @} end of LinearInterpolate group
*/
/**
* @brief Fast approximation to the trigonometric sine function for floating-point data.
* @param[in] x input value in radians.
* @return sin(x).
*/
float32_t arm_sin_f32(
float32_t x);
/**
* @brief Fast approximation to the trigonometric sine function for Q31 data.
* @param[in] x Scaled input value in radians.
* @return sin(x).
*/
q31_t arm_sin_q31(
q31_t x);
/**
* @brief Fast approximation to the trigonometric sine function for Q15 data.
* @param[in] x Scaled input value in radians.
* @return sin(x).
*/
q15_t arm_sin_q15(
q15_t x);
/**
* @brief Fast approximation to the trigonometric cosine function for floating-point data.
* @param[in] x input value in radians.
* @return cos(x).
*/
float32_t arm_cos_f32(
float32_t x);
/**
* @brief Fast approximation to the trigonometric cosine function for Q31 data.
* @param[in] x Scaled input value in radians.
* @return cos(x).
*/
q31_t arm_cos_q31(
q31_t x);
/**
* @brief Fast approximation to the trigonometric cosine function for Q15 data.
* @param[in] x Scaled input value in radians.
* @return cos(x).
*/
q15_t arm_cos_q15(
q15_t x);
/**
* @ingroup groupFastMath
*/
/**
* @defgroup SQRT Square Root
*
* Computes the square root of a number.
* There are separate functions for Q15, Q31, and floating-point data types.
* The square root function is computed using the Newton-Raphson algorithm.
* This is an iterative algorithm of the form:
* & lt; pre & gt;
* x1 = x0 - f(x0)/f'(x0)
* & lt; /pre & gt;
* where & lt; code & gt; x1 & lt; /code & gt; is the current estimate,
* & lt; code & gt; x0 & lt; /code & gt; is the previous estimate, and
* & lt; code & gt; f'(x0) & lt; /code & gt; is the derivative of & lt; code & gt; f() & lt; /code & gt; evaluated at & lt; code & gt; x0 & lt; /code & gt; .
* For the square root function, the algorithm reduces to:
* & lt; pre & gt;
* x0 = in/2 [initial guess]
* x1 = 1/2 * ( x0 + in / x0) [each iteration]
* & lt; /pre & gt;
*/
/**
* @addtogroup SQRT
* @{
*/
/**
* @brief Floating-point square root function.
* @param[in] in input value.
* @param[out] pOut square root of input value.
* @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
* & lt; code & gt; in & lt; /code & gt; is negative value and returns zero output for negative values.
*/
static __INLINE arm_status arm_sqrt_f32(
float32_t in,
float32_t * pOut)
{
if(in & gt; = 0.0f)
{
#if (__FPU_USED == 1) & & defined ( __CC_ARM )
*pOut = __sqrtf(in);
#elif (__FPU_USED == 1) & & (defined(__ARMCC_VERSION) & & (__ARMCC_VERSION & gt; = 6010050))
*pOut = __builtin_sqrtf(in);
#elif (__FPU_USED == 1) & & defined(__GNUC__)
*pOut = __builtin_sqrtf(in);
#elif (__FPU_USED == 1) & & defined ( __ICCARM__ ) & & (__VER__ & gt; = 6040000)
__ASM( " VSQRT.F32 %0,%1 " : " =t " (*pOut) : " t " (in));
#else
*pOut = sqrtf(in);
#endif
return (ARM_MATH_SUCCESS);
}
else
{
*pOut = 0.0f;
return (ARM_MATH_ARGUMENT_ERROR);
}
}
/**
* @brief Q31 square root function.
* @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
* @param[out] pOut square root of input value.
* @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
* & lt; code & gt; in & lt; /code & gt; is negative value and returns zero output for negative values.
*/
arm_status arm_sqrt_q31(
q31_t in,
q31_t * pOut);
/**
* @brief Q15 square root function.
* @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
* @param[out] pOut square root of input value.
* @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
* & lt; code & gt; in & lt; /code & gt; is negative value and returns zero output for negative values.
*/
arm_status arm_sqrt_q15(
q15_t in,
q15_t * pOut);
/**
* @} end of SQRT group
*/
/**
* @brief floating-point Circular write function.
*/
static __INLINE void arm_circularWrite_f32(
int32_t * circBuffer,
int32_t L,
uint16_t * writeOffset,
int32_t bufferInc,
const int32_t * src,
int32_t srcInc,
uint32_t blockSize)
{
uint32_t i = 0u;
int32_t wOffset;
/* Copy the value of Index pointer that points
* to the current location where the input samples to be copied */
wOffset = *writeOffset;
/* Loop over the blockSize */
i = blockSize;
while(i & gt; 0u)
{
/* copy the input sample to the circular buffer */
circBuffer[wOffset] = *src;
/* Update the input pointer */
src += srcInc;
/* Circularly update wOffset. Watch out for positive and negative value */
wOffset += bufferInc;
if(wOffset & gt; = L)
wOffset -= L;
/* Decrement the loop counter */
i--;
}
/* Update the index pointer */
*writeOffset = (uint16_t)wOffset;
}
/**
* @brief floating-point Circular Read function.
*/
static __INLINE void arm_circularRead_f32(
int32_t * circBuffer,
int32_t L,
int32_t * readOffset,
int32_t bufferInc,
int32_t * dst,
int32_t * dst_base,
int32_t dst_length,
int32_t dstInc,
uint32_t blockSize)
{
uint32_t i = 0u;
int32_t rOffset, dst_end;
/* Copy the value of Index pointer that points
* to the current location from where the input samples to be read */
rOffset = *readOffset;
dst_end = (int32_t) (dst_base + dst_length);
/* Loop over the blockSize */
i = blockSize;
while(i & gt; 0u)
{
/* copy the sample from the circular buffer to the destination buffer */
*dst = circBuffer[rOffset];
/* Update the input pointer */
dst += dstInc;
if(dst == (int32_t *) dst_end)
{
dst = dst_base;
}
/* Circularly update rOffset. Watch out for positive and negative value */
rOffset += bufferInc;
if(rOffset & gt; = L)
{
rOffset -= L;
}
/* Decrement the loop counter */
i--;
}
/* Update the index pointer */
*readOffset = rOffset;
}
/**
* @brief Q15 Circular write function.
*/
static __INLINE void arm_circularWrite_q15(
q15_t * circBuffer,
int32_t L,
uint16_t * writeOffset,
int32_t bufferInc,
const q15_t * src,
int32_t srcInc,
uint32_t blockSize)
{
uint32_t i = 0u;
int32_t wOffset;
/* Copy the value of Index pointer that points
* to the current location where the input samples to be copied */
wOffset = *writeOffset;
/* Loop over the blockSize */
i = blockSize;
while(i & gt; 0u)
{
/* copy the input sample to the circular buffer */
circBuffer[wOffset] = *src;
/* Update the input pointer */
src += srcInc;
/* Circularly update wOffset. Watch out for positive and negative value */
wOffset += bufferInc;
if(wOffset & gt; = L)
wOffset -= L;
/* Decrement the loop counter */
i--;
}
/* Update the index pointer */
*writeOffset = (uint16_t)wOffset;
}
/**
* @brief Q15 Circular Read function.
*/
static __INLINE void arm_circularRead_q15(
q15_t * circBuffer,
int32_t L,
int32_t * readOffset,
int32_t bufferInc,
q15_t * dst,
q15_t * dst_base,
int32_t dst_length,
int32_t dstInc,
uint32_t blockSize)
{
uint32_t i = 0;
int32_t rOffset, dst_end;
/* Copy the value of Index pointer that points
* to the current location from where the input samples to be read */
rOffset = *readOffset;
dst_end = (int32_t) (dst_base + dst_length);
/* Loop over the blockSize */
i = blockSize;
while(i & gt; 0u)
{
/* copy the sample from the circular buffer to the destination buffer */
*dst = circBuffer[rOffset];
/* Update the input pointer */
dst += dstInc;
if(dst == (q15_t *) dst_end)
{
dst = dst_base;
}
/* Circularly update wOffset. Watch out for positive and negative value */
rOffset += bufferInc;
if(rOffset & gt; = L)
{
rOffset -= L;
}
/* Decrement the loop counter */
i--;
}
/* Update the index pointer */
*readOffset = rOffset;
}
/**
* @brief Q7 Circular write function.
*/
static __INLINE void arm_circularWrite_q7(
q7_t * circBuffer,
int32_t L,
uint16_t * writeOffset,
int32_t bufferInc,
const q7_t * src,
int32_t srcInc,
uint32_t blockSize)
{
uint32_t i = 0u;
int32_t wOffset;
/* Copy the value of Index pointer that points
* to the current location where the input samples to be copied */
wOffset = *writeOffset;
/* Loop over the blockSize */
i = blockSize;
while(i & gt; 0u)
{
/* copy the input sample to the circular buffer */
circBuffer[wOffset] = *src;
/* Update the input pointer */
src += srcInc;
/* Circularly update wOffset. Watch out for positive and negative value */
wOffset += bufferInc;
if(wOffset & gt; = L)
wOffset -= L;
/* Decrement the loop counter */
i--;
}
/* Update the index pointer */
*writeOffset = (uint16_t)wOffset;
}
/**
* @brief Q7 Circular Read function.
*/
static __INLINE void arm_circularRead_q7(
q7_t * circBuffer,
int32_t L,
int32_t * readOffset,
int32_t bufferInc,
q7_t * dst,
q7_t * dst_base,
int32_t dst_length,
int32_t dstInc,
uint32_t blockSize)
{
uint32_t i = 0;
int32_t rOffset, dst_end;
/* Copy the value of Index pointer that points
* to the current location from where the input samples to be read */
rOffset = *readOffset;
dst_end = (int32_t) (dst_base + dst_length);
/* Loop over the blockSize */
i = blockSize;
while(i & gt; 0u)
{
/* copy the sample from the circular buffer to the destination buffer */
*dst = circBuffer[rOffset];
/* Update the input pointer */
dst += dstInc;
if(dst == (q7_t *) dst_end)
{
dst = dst_base;
}
/* Circularly update rOffset. Watch out for positive and negative value */
rOffset += bufferInc;
if(rOffset & gt; = L)
{
rOffset -= L;
}
/* Decrement the loop counter */
i--;
}
/* Update the index pointer */
*readOffset = rOffset;
}
/**
* @brief Sum of the squares of the elements of a Q31 vector.
* @param[in] pSrc is input pointer
* @param[in] blockSize is the number of samples to process
* @param[out] pResult is output value.
*/
void arm_power_q31(
q31_t * pSrc,
uint32_t blockSize,
q63_t * pResult);
/**
* @brief Sum of the squares of the elements of a floating-point vector.
* @param[in] pSrc is input pointer
* @param[in] blockSize is the number of samples to process
* @param[out] pResult is output value.
*/
void arm_power_f32(
float32_t * pSrc,
uint32_t blockSize,
float32_t * pResult);
/**
* @brief Sum of the squares of the elements of a Q15 vector.
* @param[in] pSrc is input pointer
* @param[in] blockSize is the number of samples to process
* @param[out] pResult is output value.
*/
void arm_power_q15(
q15_t * pSrc,
uint32_t blockSize,
q63_t * pResult);
/**
* @brief Sum of the squares of the elements of a Q7 vector.
* @param[in] pSrc is input pointer
* @param[in] blockSize is the number of samples to process
* @param[out] pResult is output value.
*/
void arm_power_q7(
q7_t * pSrc,
uint32_t blockSize,
q31_t * pResult);
/**
* @brief Mean value of a Q7 vector.
* @param[in] pSrc is input pointer
* @param[in] blockSize is the number of samples to process
* @param[out] pResult is output value.
*/
void arm_mean_q7(
q7_t * pSrc,
uint32_t blockSize,
q7_t * pResult);
/**
* @brief Mean value of a Q15 vector.
* @param[in] pSrc is input pointer
* @param[in] blockSize is the number of samples to process
* @param[out] pResult is output value.
*/
void arm_mean_q15(
q15_t * pSrc,
uint32_t blockSize,
q15_t * pResult);
/**
* @brief Mean value of a Q31 vector.
* @param[in] pSrc is input pointer
* @param[in] blockSize is the number of samples to process
* @param[out] pResult is output value.
*/
void arm_mean_q31(
q31_t * pSrc,
uint32_t blockSize,
q31_t * pResult);
/**
* @brief Mean value of a floating-point vector.
* @param[in] pSrc is input pointer
* @param[in] blockSize is the number of samples to process
* @param[out] pResult is output value.
*/
void arm_mean_f32(
float32_t * pSrc,
uint32_t blockSize,
float32_t * pResult);
/**
* @brief Variance of the elements of a floating-point vector.
* @param[in] pSrc is input pointer
* @param[in] blockSize is the number of samples to process
* @param[out] pResult is output value.
*/
void arm_var_f32(
float32_t * pSrc,
uint32_t blockSize,
float32_t * pResult);
/**
* @brief Variance of the elements of a Q31 vector.
* @param[in] pSrc is input pointer
* @param[in] blockSize is the number of samples to process
* @param[out] pResult is output value.
*/
void arm_var_q31(
q31_t * pSrc,
uint32_t blockSize,
q31_t * pResult);
/**
* @brief Variance of the elements of a Q15 vector.
* @param[in] pSrc is input pointer
* @param[in] blockSize is the number of samples to process
* @param[out] pResult is output value.
*/
void arm_var_q15(
q15_t * pSrc,
uint32_t blockSize,
q15_t * pResult);
/**
* @brief Root Mean Square of the elements of a floating-point vector.
* @param[in] pSrc is input pointer
* @param[in] blockSize is the number of samples to process
* @param[out] pResult is output value.
*/
void arm_rms_f32(
float32_t * pSrc,
uint32_t blockSize,
float32_t * pResult);
/**
* @brief Root Mean Square of the elements of a Q31 vector.
* @param[in] pSrc is input pointer
* @param[in] blockSize is the number of samples to process
* @param[out] pResult is output value.
*/
void arm_rms_q31(
q31_t * pSrc,
uint32_t blockSize,
q31_t * pResult);
/**
* @brief Root Mean Square of the elements of a Q15 vector.
* @param[in] pSrc is input pointer
* @param[in] blockSize is the number of samples to process
* @param[out] pResult is output value.
*/
void arm_rms_q15(
q15_t * pSrc,
uint32_t blockSize,
q15_t * pResult);
/**
* @brief Standard deviation of the elements of a floating-point vector.
* @param[in] pSrc is input pointer
* @param[in] blockSize is the number of samples to process
* @param[out] pResult is output value.
*/
void arm_std_f32(
float32_t * pSrc,
uint32_t blockSize,
float32_t * pResult);
/**
* @brief Standard deviation of the elements of a Q31 vector.
* @param[in] pSrc is input pointer
* @param[in] blockSize is the number of samples to process
* @param[out] pResult is output value.
*/
void arm_std_q31(
q31_t * pSrc,
uint32_t blockSize,
q31_t * pResult);
/**
* @brief Standard deviation of the elements of a Q15 vector.
* @param[in] pSrc is input pointer
* @param[in] blockSize is the number of samples to process
* @param[out] pResult is output value.
*/
void arm_std_q15(
q15_t * pSrc,
uint32_t blockSize,
q15_t * pResult);
/**
* @brief Floating-point complex magnitude
* @param[in] pSrc points to the complex input vector
* @param[out] pDst points to the real output vector
* @param[in] numSamples number of complex samples in the input vector
*/
void arm_cmplx_mag_f32(
float32_t * pSrc,
float32_t * pDst,
uint32_t numSamples);
/**
* @brief Q31 complex magnitude
* @param[in] pSrc points to the complex input vector
* @param[out] pDst points to the real output vector
* @param[in] numSamples number of complex samples in the input vector
*/
void arm_cmplx_mag_q31(
q31_t * pSrc,
q31_t * pDst,
uint32_t numSamples);
/**
* @brief Q15 complex magnitude
* @param[in] pSrc points to the complex input vector
* @param[out] pDst points to the real output vector
* @param[in] numSamples number of complex samples in the input vector
*/
void arm_cmplx_mag_q15(
q15_t * pSrc,
q15_t * pDst,
uint32_t numSamples);
/**
* @brief Q15 complex dot product
* @param[in] pSrcA points to the first input vector
* @param[in] pSrcB points to the second input vector
* @param[in] numSamples number of complex samples in each vector
* @param[out] realResult real part of the result returned here
* @param[out] imagResult imaginary part of the result returned here
*/
void arm_cmplx_dot_prod_q15(
q15_t * pSrcA,
q15_t * pSrcB,
uint32_t numSamples,
q31_t * realResult,
q31_t * imagResult);
/**
* @brief Q31 complex dot product
* @param[in] pSrcA points to the first input vector
* @param[in] pSrcB points to the second input vector
* @param[in] numSamples number of complex samples in each vector
* @param[out] realResult real part of the result returned here
* @param[out] imagResult imaginary part of the result returned here
*/
void arm_cmplx_dot_prod_q31(
q31_t * pSrcA,
q31_t * pSrcB,
uint32_t numSamples,
q63_t * realResult,
q63_t * imagResult);
/**
* @brief Floating-point complex dot product
* @param[in] pSrcA points to the first input vector
* @param[in] pSrcB points to the second input vector
* @param[in] numSamples number of complex samples in each vector
* @param[out] realResult real part of the result returned here
* @param[out] imagResult imaginary part of the result returned here
*/
void arm_cmplx_dot_prod_f32(
float32_t * pSrcA,
float32_t * pSrcB,
uint32_t numSamples,
float32_t * realResult,
float32_t * imagResult);
/**
* @brief Q15 complex-by-real multiplication
* @param[in] pSrcCmplx points to the complex input vector
* @param[in] pSrcReal points to the real input vector
* @param[out] pCmplxDst points to the complex output vector
* @param[in] numSamples number of samples in each vector
*/
void arm_cmplx_mult_real_q15(
q15_t * pSrcCmplx,
q15_t * pSrcReal,
q15_t * pCmplxDst,
uint32_t numSamples);
/**
* @brief Q31 complex-by-real multiplication
* @param[in] pSrcCmplx points to the complex input vector
* @param[in] pSrcReal points to the real input vector
* @param[out] pCmplxDst points to the complex output vector
* @param[in] numSamples number of samples in each vector
*/
void arm_cmplx_mult_real_q31(
q31_t * pSrcCmplx,
q31_t * pSrcReal,
q31_t * pCmplxDst,
uint32_t numSamples);
/**
* @brief Floating-point complex-by-real multiplication
* @param[in] pSrcCmplx points to the complex input vector
* @param[in] pSrcReal points to the real input vector
* @param[out] pCmplxDst points to the complex output vector
* @param[in] numSamples number of samples in each vector
*/
void arm_cmplx_mult_real_f32(
float32_t * pSrcCmplx,
float32_t * pSrcReal,
float32_t * pCmplxDst,
uint32_t numSamples);
/**
* @brief Minimum value of a Q7 vector.
* @param[in] pSrc is input pointer
* @param[in] blockSize is the number of samples to process
* @param[out] result is output pointer
* @param[in] index is the array index of the minimum value in the input buffer.
*/
void arm_min_q7(
q7_t * pSrc,
uint32_t blockSize,
q7_t * result,
uint32_t * index);
/**
* @brief Minimum value of a Q15 vector.
* @param[in] pSrc is input pointer
* @param[in] blockSize is the number of samples to process
* @param[out] pResult is output pointer
* @param[in] pIndex is the array index of the minimum value in the input buffer.
*/
void arm_min_q15(
q15_t * pSrc,
uint32_t blockSize,
q15_t * pResult,
uint32_t * pIndex);
/**
* @brief Minimum value of a Q31 vector.
* @param[in] pSrc is input pointer
* @param[in] blockSize is the number of samples to process
* @param[out] pResult is output pointer
* @param[out] pIndex is the array index of the minimum value in the input buffer.
*/
void arm_min_q31(
q31_t * pSrc,
uint32_t blockSize,
q31_t * pResult,
uint32_t * pIndex);
/**
* @brief Minimum value of a floating-point vector.
* @param[in] pSrc is input pointer
* @param[in] blockSize is the number of samples to process
* @param[out] pResult is output pointer
* @param[out] pIndex is the array index of the minimum value in the input buffer.
*/
void arm_min_f32(
float32_t * pSrc,
uint32_t blockSize,
float32_t * pResult,
uint32_t * pIndex);
/**
* @brief Maximum value of a Q7 vector.
* @param[in] pSrc points to the input buffer
* @param[in] blockSize length of the input vector
* @param[out] pResult maximum value returned here
* @param[out] pIndex index of maximum value returned here
*/
void arm_max_q7(
q7_t * pSrc,
uint32_t blockSize,
q7_t * pResult,
uint32_t * pIndex);
/**
* @brief Maximum value of a Q15 vector.
* @param[in] pSrc points to the input buffer
* @param[in] blockSize length of the input vector
* @param[out] pResult maximum value returned here
* @param[out] pIndex index of maximum value returned here
*/
void arm_max_q15(
q15_t * pSrc,
uint32_t blockSize,
q15_t * pResult,
uint32_t * pIndex);
/**
* @brief Maximum value of a Q31 vector.
* @param[in] pSrc points to the input buffer
* @param[in] blockSize length of the input vector
* @param[out] pResult maximum value returned here
* @param[out] pIndex index of maximum value returned here
*/
void arm_max_q31(
q31_t * pSrc,
uint32_t blockSize,
q31_t * pResult,
uint32_t * pIndex);
/**
* @brief Maximum value of a floating-point vector.
* @param[in] pSrc points to the input buffer
* @param[in] blockSize length of the input vector
* @param[out] pResult maximum value returned here
* @param[out] pIndex index of maximum value returned here
*/
void arm_max_f32(
float32_t * pSrc,
uint32_t blockSize,
float32_t * pResult,
uint32_t * pIndex);
/**
* @brief Q15 complex-by-complex multiplication
* @param[in] pSrcA points to the first input vector
* @param[in] pSrcB points to the second input vector
* @param[out] pDst points to the output vector
* @param[in] numSamples number of complex samples in each vector
*/
void arm_cmplx_mult_cmplx_q15(
q15_t * pSrcA,
q15_t * pSrcB,
q15_t * pDst,
uint32_t numSamples);
/**
* @brief Q31 complex-by-complex multiplication
* @param[in] pSrcA points to the first input vector
* @param[in] pSrcB points to the second input vector
* @param[out] pDst points to the output vector
* @param[in] numSamples number of complex samples in each vector
*/
void arm_cmplx_mult_cmplx_q31(
q31_t * pSrcA,
q31_t * pSrcB,
q31_t * pDst,
uint32_t numSamples);
/**
* @brief Floating-point complex-by-complex multiplication
* @param[in] pSrcA points to the first input vector
* @param[in] pSrcB points to the second input vector
* @param[out] pDst points to the output vector
* @param[in] numSamples number of complex samples in each vector
*/
void arm_cmplx_mult_cmplx_f32(
float32_t * pSrcA,
float32_t * pSrcB,
float32_t * pDst,
uint32_t numSamples);
/**
* @brief Converts the elements of the floating-point vector to Q31 vector.
* @param[in] pSrc points to the floating-point input vector
* @param[out] pDst points to the Q31 output vector
* @param[in] blockSize length of the input vector
*/
void arm_float_to_q31(
float32_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
/**
* @brief Converts the elements of the floating-point vector to Q15 vector.
* @param[in] pSrc points to the floating-point input vector
* @param[out] pDst points to the Q15 output vector
* @param[in] blockSize length of the input vector
*/
void arm_float_to_q15(
float32_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
/**
* @brief Converts the elements of the floating-point vector to Q7 vector.
* @param[in] pSrc points to the floating-point input vector
* @param[out] pDst points to the Q7 output vector
* @param[in] blockSize length of the input vector
*/
void arm_float_to_q7(
float32_t * pSrc,
q7_t * pDst,
uint32_t blockSize);
/**
* @brief Converts the elements of the Q31 vector to Q15 vector.
* @param[in] pSrc is input pointer
* @param[out] pDst is output pointer
* @param[in] blockSize is the number of samples to process
*/
void arm_q31_to_q15(
q31_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
/**
* @brief Converts the elements of the Q31 vector to Q7 vector.
* @param[in] pSrc is input pointer
* @param[out] pDst is output pointer
* @param[in] blockSize is the number of samples to process
*/
void arm_q31_to_q7(
q31_t * pSrc,
q7_t * pDst,
uint32_t blockSize);
/**
* @brief Converts the elements of the Q15 vector to floating-point vector.
* @param[in] pSrc is input pointer
* @param[out] pDst is output pointer
* @param[in] blockSize is the number of samples to process
*/
void arm_q15_to_float(
q15_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
/**
* @brief Converts the elements of the Q15 vector to Q31 vector.
* @param[in] pSrc is input pointer
* @param[out] pDst is output pointer
* @param[in] blockSize is the number of samples to process
*/
void arm_q15_to_q31(
q15_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
/**
* @brief Converts the elements of the Q15 vector to Q7 vector.
* @param[in] pSrc is input pointer
* @param[out] pDst is output pointer
* @param[in] blockSize is the number of samples to process
*/
void arm_q15_to_q7(
q15_t * pSrc,
q7_t * pDst,
uint32_t blockSize);
/**
* @ingroup groupInterpolation
*/
/**
* @defgroup BilinearInterpolate Bilinear Interpolation
*
* Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
* The underlying function & lt; code & gt; f(x, y) & lt; /code & gt; is sampled on a regular grid and the interpolation process
* determines values between the grid points.
* Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
* Bilinear interpolation is often used in image processing to rescale images.
* The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
*
* & lt; b & gt; Algorithm & lt; /b & gt;
* \par
* The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
* For floating-point, the instance structure is defined as:
* & lt; pre & gt;
* typedef struct
* {
* uint16_t numRows;
* uint16_t numCols;
* float32_t *pData;
* } arm_bilinear_interp_instance_f32;
* & lt; /pre & gt;
*
* \par
* where & lt; code & gt; numRows & lt; /code & gt; specifies the number of rows in the table;
* & lt; code & gt; numCols & lt; /code & gt; specifies the number of columns in the table;
* and & lt; code & gt; pData & lt; /code & gt; points to an array of size & lt; code & gt; numRows*numCols & lt; /code & gt; values.
* The data table & lt; code & gt; pTable & lt; /code & gt; is organized in row order and the supplied data values fall on integer indexes.
* That is, table element (x,y) is located at & lt; code & gt; pTable[x + y*numCols] & lt; /code & gt; where x and y are integers.
*
* \par
* Let & lt; code & gt; (x, y) & lt; /code & gt; specify the desired interpolation point. Then define:
* & lt; pre & gt;
* XF = floor(x)
* YF = floor(y)
* & lt; /pre & gt;
* \par
* The interpolated output point is computed as:
* & lt; pre & gt;
* f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
* + f(XF+1, YF) * (x-XF)*(1-(y-YF))
* + f(XF, YF+1) * (1-(x-XF))*(y-YF)
* + f(XF+1, YF+1) * (x-XF)*(y-YF)
* & lt; /pre & gt;
* Note that the coordinates (x, y) contain integer and fractional components.
* The integer components specify which portion of the table to use while the
* fractional components control the interpolation processor.
*
* \par
* if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
*/
/**
* @addtogroup BilinearInterpolate
* @{
*/
/**
*
* @brief Floating-point bilinear interpolation.
* @param[in,out] S points to an instance of the interpolation structure.
* @param[in] X interpolation coordinate.
* @param[in] Y interpolation coordinate.
* @return out interpolated value.
*/
static __INLINE float32_t arm_bilinear_interp_f32(
const arm_bilinear_interp_instance_f32 * S,
float32_t X,
float32_t Y)
{
float32_t out;
float32_t f00, f01, f10, f11;
float32_t *pData = S- & gt; pData;
int32_t xIndex, yIndex, index;
float32_t xdiff, ydiff;
float32_t b1, b2, b3, b4;
xIndex = (int32_t) X;
yIndex = (int32_t) Y;
/* Care taken for table outside boundary */
/* Returns zero output when values are outside table boundary */
if(xIndex & lt; 0 || xIndex & gt; (S- & gt; numRows - 1) || yIndex & lt; 0 || yIndex & gt; (S- & gt; numCols - 1))
{
return (0);
}
/* Calculation of index for two nearest points in X-direction */
index = (xIndex - 1) + (yIndex - 1) * S- & gt; numCols;
/* Read two nearest points in X-direction */
f00 = pData[index];
f01 = pData[index + 1];
/* Calculation of index for two nearest points in Y-direction */
index = (xIndex - 1) + (yIndex) * S- & gt; numCols;
/* Read two nearest points in Y-direction */
f10 = pData[index];
f11 = pData[index + 1];
/* Calculation of intermediate values */
b1 = f00;
b2 = f01 - f00;
b3 = f10 - f00;
b4 = f00 - f01 - f10 + f11;
/* Calculation of fractional part in X */
xdiff = X - xIndex;
/* Calculation of fractional part in Y */
ydiff = Y - yIndex;
/* Calculation of bi-linear interpolated output */
out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
/* return to application */
return (out);
}
/**
*
* @brief Q31 bilinear interpolation.
* @param[in,out] S points to an instance of the interpolation structure.
* @param[in] X interpolation coordinate in 12.20 format.
* @param[in] Y interpolation coordinate in 12.20 format.
* @return out interpolated value.
*/
static __INLINE q31_t arm_bilinear_interp_q31(
arm_bilinear_interp_instance_q31 * S,
q31_t X,
q31_t Y)
{
q31_t out; /* Temporary output */
q31_t acc = 0; /* output */
q31_t xfract, yfract; /* X, Y fractional parts */
q31_t x1, x2, y1, y2; /* Nearest output values */
int32_t rI, cI; /* Row and column indices */
q31_t *pYData = S- & gt; pData; /* pointer to output table values */
uint32_t nCols = S- & gt; numCols; /* num of rows */
/* Input is in 12.20 format */
/* 12 bits for the table index */
/* Index value calculation */
rI = ((X & (q31_t)0xFFF00000) & gt; & gt; 20);
/* Input is in 12.20 format */
/* 12 bits for the table index */
/* Index value calculation */
cI = ((Y & (q31_t)0xFFF00000) & gt; & gt; 20);
/* Care taken for table outside boundary */
/* Returns zero output when values are outside table boundary */
if(rI & lt; 0 || rI & gt; (S- & gt; numRows - 1) || cI & lt; 0 || cI & gt; (S- & gt; numCols - 1))
{
return (0);
}
/* 20 bits for the fractional part */
/* shift left xfract by 11 to keep 1.31 format */
xfract = (X & 0x000FFFFF) & lt; & lt; 11u;
/* Read two nearest output values from the index */
x1 = pYData[(rI) + (int32_t)nCols * (cI) ];
x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
/* 20 bits for the fractional part */
/* shift left yfract by 11 to keep 1.31 format */
yfract = (Y & 0x000FFFFF) & lt; & lt; 11u;
/* Read two nearest output values from the index */
y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ];
y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
/* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) & gt; & gt; 32));
acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) & gt; & gt; 32));
/* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) & gt; & gt; 32));
acc += ((q31_t) ((q63_t) out * (xfract) & gt; & gt; 32));
/* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) & gt; & gt; 32));
acc += ((q31_t) ((q63_t) out * (yfract) & gt; & gt; 32));
/* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
out = ((q31_t) ((q63_t) y2 * (xfract) & gt; & gt; 32));
acc += ((q31_t) ((q63_t) out * (yfract) & gt; & gt; 32));
/* Convert acc to 1.31(q31) format */
return ((q31_t)(acc & lt; & lt; 2));
}
/**
* @brief Q15 bilinear interpolation.
* @param[in,out] S points to an instance of the interpolation structure.
* @param[in] X interpolation coordinate in 12.20 format.
* @param[in] Y interpolation coordinate in 12.20 format.
* @return out interpolated value.
*/
static __INLINE q15_t arm_bilinear_interp_q15(
arm_bilinear_interp_instance_q15 * S,
q31_t X,
q31_t Y)
{
q63_t acc = 0; /* output */
q31_t out; /* Temporary output */
q15_t x1, x2, y1, y2; /* Nearest output values */
q31_t xfract, yfract; /* X, Y fractional parts */
int32_t rI, cI; /* Row and column indices */
q15_t *pYData = S- & gt; pData; /* pointer to output table values */
uint32_t nCols = S- & gt; numCols; /* num of rows */
/* Input is in 12.20 format */
/* 12 bits for the table index */
/* Index value calculation */
rI = ((X & (q31_t)0xFFF00000) & gt; & gt; 20);
/* Input is in 12.20 format */
/* 12 bits for the table index */
/* Index value calculation */
cI = ((Y & (q31_t)0xFFF00000) & gt; & gt; 20);
/* Care taken for table outside boundary */
/* Returns zero output when values are outside table boundary */
if(rI & lt; 0 || rI & gt; (S- & gt; numRows - 1) || cI & lt; 0 || cI & gt; (S- & gt; numCols - 1))
{
return (0);
}
/* 20 bits for the fractional part */
/* xfract should be in 12.20 format */
xfract = (X & 0x000FFFFF);
/* Read two nearest output values from the index */
x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
/* 20 bits for the fractional part */
/* yfract should be in 12.20 format */
yfract = (Y & 0x000FFFFF);
/* Read two nearest output values from the index */
y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
/* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
/* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
/* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) & gt; & gt; 4u);
acc = ((q63_t) out * (0xFFFFF - yfract));
/* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) & gt; & gt; 4u);
acc += ((q63_t) out * (xfract));
/* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) & gt; & gt; 4u);
acc += ((q63_t) out * (yfract));
/* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
out = (q31_t) (((q63_t) y2 * (xfract)) & gt; & gt; 4u);
acc += ((q63_t) out * (yfract));
/* acc is in 13.51 format and down shift acc by 36 times */
/* Convert out to 1.15 format */
return ((q15_t)(acc & gt; & gt; 36));
}
/**
* @brief Q7 bilinear interpolation.
* @param[in,out] S points to an instance of the interpolation structure.
* @param[in] X interpolation coordinate in 12.20 format.
* @param[in] Y interpolation coordinate in 12.20 format.
* @return out interpolated value.
*/
static __INLINE q7_t arm_bilinear_interp_q7(
arm_bilinear_interp_instance_q7 * S,
q31_t X,
q31_t Y)
{
q63_t acc = 0; /* output */
q31_t out; /* Temporary output */
q31_t xfract, yfract; /* X, Y fractional parts */
q7_t x1, x2, y1, y2; /* Nearest output values */
int32_t rI, cI; /* Row and column indices */
q7_t *pYData = S- & gt; pData; /* pointer to output table values */
uint32_t nCols = S- & gt; numCols; /* num of rows */
/* Input is in 12.20 format */
/* 12 bits for the table index */
/* Index value calculation */
rI = ((X & (q31_t)0xFFF00000) & gt; & gt; 20);
/* Input is in 12.20 format */
/* 12 bits for the table index */
/* Index value calculation */
cI = ((Y & (q31_t)0xFFF00000) & gt; & gt; 20);
/* Care taken for table outside boundary */
/* Returns zero output when values are outside table boundary */
if(rI & lt; 0 || rI & gt; (S- & gt; numRows - 1) || cI & lt; 0 || cI & gt; (S- & gt; numCols - 1))
{
return (0);
}
/* 20 bits for the fractional part */
/* xfract should be in 12.20 format */
xfract = (X & (q31_t)0x000FFFFF);
/* Read two nearest output values from the index */
x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
/* 20 bits for the fractional part */
/* yfract should be in 12.20 format */
yfract = (Y & (q31_t)0x000FFFFF);
/* Read two nearest output values from the index */
y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
/* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
out = ((x1 * (0xFFFFF - xfract)));
acc = (((q63_t) out * (0xFFFFF - yfract)));
/* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
out = ((x2 * (0xFFFFF - yfract)));
acc += (((q63_t) out * (xfract)));
/* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
out = ((y1 * (0xFFFFF - xfract)));
acc += (((q63_t) out * (yfract)));
/* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
out = ((y2 * (yfract)));
acc += (((q63_t) out * (xfract)));
/* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
return ((q7_t)(acc & gt; & gt; 40));
}
/**
* @} end of BilinearInterpolate group
*/
/* SMMLAR */
#define multAcc_32x32_keep32_R(a, x, y) \
a = (q31_t) (((((q63_t) a) & lt; & lt; 32) + ((q63_t) x * y) + 0x80000000LL ) & gt; & gt; 32)
/* SMMLSR */
#define multSub_32x32_keep32_R(a, x, y) \
a = (q31_t) (((((q63_t) a) & lt; & lt; 32) - ((q63_t) x * y) + 0x80000000LL ) & gt; & gt; 32)
/* SMMULR */
#define mult_32x32_keep32_R(a, x, y) \
a = (q31_t) (((q63_t) x * y + 0x80000000LL ) & gt; & gt; 32)
/* SMMLA */
#define multAcc_32x32_keep32(a, x, y) \
a += (q31_t) (((q63_t) x * y) & gt; & gt; 32)
/* SMMLS */
#define multSub_32x32_keep32(a, x, y) \
a -= (q31_t) (((q63_t) x * y) & gt; & gt; 32)
/* SMMUL */
#define mult_32x32_keep32(a, x, y) \
a = (q31_t) (((q63_t) x * y ) & gt; & gt; 32)
#if defined ( __CC_ARM )
/* Enter low optimization region - place directly above function definition */
#if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
#define LOW_OPTIMIZATION_ENTER \
_Pragma ( " push " ) \
_Pragma ( " O1 " )
#else
#define LOW_OPTIMIZATION_ENTER
#endif
/* Exit low optimization region - place directly after end of function definition */
#if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
#define LOW_OPTIMIZATION_EXIT \
_Pragma ( " pop " )
#else
#define LOW_OPTIMIZATION_EXIT
#endif
/* Enter low optimization region - place directly above function definition */
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
/* Exit low optimization region - place directly after end of function definition */
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
#elif defined(__ARMCC_VERSION) & & (__ARMCC_VERSION & gt; = 6010050)
#define LOW_OPTIMIZATION_ENTER
#define LOW_OPTIMIZATION_EXIT
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
#elif defined(__GNUC__)
#define LOW_OPTIMIZATION_ENTER __attribute__(( optimize( " -O1 " ) ))
#define LOW_OPTIMIZATION_EXIT
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
#elif defined(__ICCARM__)
/* Enter low optimization region - place directly above function definition */
#if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
#define LOW_OPTIMIZATION_ENTER \
_Pragma ( " optimize=low " )
#else
#define LOW_OPTIMIZATION_ENTER
#endif
/* Exit low optimization region - place directly after end of function definition */
#define LOW_OPTIMIZATION_EXIT
/* Enter low optimization region - place directly above function definition */
#if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
_Pragma ( " optimize=low " )
#else
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
#endif
/* Exit low optimization region - place directly after end of function definition */
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
#elif defined(__CSMC__)
#define LOW_OPTIMIZATION_ENTER
#define LOW_OPTIMIZATION_EXIT
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
#elif defined(__TASKING__)
#define LOW_OPTIMIZATION_ENTER
#define LOW_OPTIMIZATION_EXIT
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
#endif
#ifdef __cplusplus
}
#endif
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
#endif /* _ARM_MATH_H */
/**
*
* End of file.
*/
/**
******************************************************************************
* File Name : main.h
* Description : This file contains the common defines of the application
******************************************************************************
*
* COPYRIGHT(c) 2017 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS " AS IS "
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MAIN_H
#define __MAIN_H
/* Includes ------------------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
/**
* @}
*/
/**
* @}
*/
#endif /* __MAIN_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file stm32f0xx_hal_conf.h
* @brief HAL configuration file.
******************************************************************************
* @attention
*
* & lt; h2 & gt; & lt; center & gt; & copy; COPYRIGHT(c) 2017 STMicroelectronics & lt; /center & gt; & lt; /h2 & gt;
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS " AS IS "
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0xx_HAL_CONF_H
#define __STM32F0xx_HAL_CONF_H
#ifdef __cplusplus
extern " C " {
#endif
#include " main.h "
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
/*#define HAL_ADC_MODULE_ENABLED */
/*#define HAL_CAN_MODULE_ENABLED */
/*#define HAL_CEC_MODULE_ENABLED */
/*#define HAL_COMP_MODULE_ENABLED */
/*#define HAL_CRC_MODULE_ENABLED */
/*#define HAL_CRYP_MODULE_ENABLED */
/*#define HAL_TSC_MODULE_ENABLED */
/*#define HAL_DAC_MODULE_ENABLED */
/*#define HAL_I2S_MODULE_ENABLED */
/*#define HAL_IWDG_MODULE_ENABLED */
/*#define HAL_LCD_MODULE_ENABLED */
/*#define HAL_LPTIM_MODULE_ENABLED */
/*#define HAL_RNG_MODULE_ENABLED */
/*#define HAL_RTC_MODULE_ENABLED */
/*#define HAL_SPI_MODULE_ENABLED */
/*#define HAL_TIM_MODULE_ENABLED */
/*#define HAL_UART_MODULE_ENABLED */
/*#define HAL_USART_MODULE_ENABLED */
/*#define HAL_IRDA_MODULE_ENABLED */
/*#define HAL_SMARTCARD_MODULE_ENABLED */
/*#define HAL_SMBUS_MODULE_ENABLED */
/*#define HAL_WWDG_MODULE_ENABLED */
/*#define HAL_PCD_MODULE_ENABLED */
#define HAL_CORTEX_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_GPIO_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
/* ########################## HSE/HSI Values adaptation ##################### */
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*! & lt; Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
/**
* @brief In the following line adjust the External High Speed oscillator (HSE) Startup
* Timeout value
*/
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*! & lt; Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)8000000) /*! & lt; Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
* Timeout value
*/
#if !defined (HSI_STARTUP_TIMEOUT)
#define HSI_STARTUP_TIMEOUT ((uint32_t)5000) /*! & lt; Time out for HSI start up */
#endif /* HSI_STARTUP_TIMEOUT */
/**
* @brief Internal High Speed oscillator for ADC (HSI14) value.
*/
#if !defined (HSI14_VALUE)
#define HSI14_VALUE ((uint32_t)14000000) /*! & lt; Value of the Internal High Speed oscillator for ADC in Hz.
The real value may vary depending on the variations
in voltage and temperature. */
#endif /* HSI14_VALUE */
/**
* @brief Internal High Speed oscillator for USB (HSI48) value.
*/
#if !defined (HSI48_VALUE)
#define HSI48_VALUE ((uint32_t)48000000) /*! & lt; Value of the Internal High Speed oscillator for USB in Hz.
The real value may vary depending on the variations
in voltage and temperature. */
#endif /* HSI48_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)40000)
#endif /* LSI_VALUE */ /*! & lt; Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
/**
* @brief External Low Speed oscillator (LSI) value.
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768) /*! & lt; Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*! & lt; Time out for LSE start up, in ms */
#endif /* LSE_STARTUP_TIMEOUT */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300) /*! & lt; Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0) /*! & lt; tick interrupt priority (lowest by default) */
/* Warning: Must be set to higher priority for HAL_Delay() */
/* and HAL_GetTick() usage under interrupt context */
#define USE_RTOS 0
#define PREFETCH_ENABLE 1
#define INSTRUCTION_CACHE_ENABLE 0
#define DATA_CACHE_ENABLE 0
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the " assert_param " macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1 */
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include " stm32f0xx_hal_rcc.h "
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include " stm32f0xx_hal_gpio.h "
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include " stm32f0xx_hal_dma.h "
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include " stm32f0xx_hal_cortex.h "
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include " stm32f0xx_hal_adc.h "
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_CAN_MODULE_ENABLED
#include " stm32f0xx_hal_can.h "
#endif /* HAL_CAN_MODULE_ENABLED */
#ifdef HAL_CEC_MODULE_ENABLED
#include " stm32f0xx_hal_cec.h "
#endif /* HAL_CEC_MODULE_ENABLED */
#ifdef HAL_COMP_MODULE_ENABLED
#include " stm32f0xx_hal_comp.h "
#endif /* HAL_COMP_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include " stm32f0xx_hal_crc.h "
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include " stm32f0xx_hal_dac.h "
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include " stm32f0xx_hal_flash.h "
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include " stm32f0xx_hal_i2c.h "
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_I2S_MODULE_ENABLED
#include " stm32f0xx_hal_i2s.h "
#endif /* HAL_I2S_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include " stm32f0xx_hal_irda.h "
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include " stm32f0xx_hal_iwdg.h "
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include " stm32f0xx_hal_pcd.h "
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include " stm32f0xx_hal_pwr.h "
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include " stm32f0xx_hal_rtc.h "
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include " stm32f0xx_hal_smartcard.h "
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_SMBUS_MODULE_ENABLED
#include " stm32f0xx_hal_smbus.h "
#endif /* HAL_SMBUS_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include " stm32f0xx_hal_spi.h "
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include " stm32f0xx_hal_tim.h "
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_TSC_MODULE_ENABLED
#include " stm32f0xx_hal_tsc.h "
#endif /* HAL_TSC_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include " stm32f0xx_hal_uart.h "
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include " stm32f0xx_hal_usart.h "
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include " stm32f0xx_hal_wwdg.h "
#endif /* HAL_WWDG_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F0xx_HAL_CONF_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file stm32f0xx_it.h
* @brief This file contains the headers of the interrupt handlers.
******************************************************************************
*
* COPYRIGHT(c) 2017 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS " AS IS "
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0xx_IT_H
#define __STM32F0xx_IT_H
#ifdef __cplusplus
extern " C " {
#endif
/* Includes ------------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void NMI_Handler(void);
void HardFault_Handler(void);
void SVC_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F0xx_IT_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32F0xx device used in the target application
* - To use or not the peripherals drivers in application code(i.e.
* code will be based on direct access to peripherals registers
* rather than drivers API), this option is controlled by
* " #define USE_HAL_DRIVER "
*
******************************************************************************
* @attention
*
* & lt; h2 & gt; & lt; center & gt; & copy; COPYRIGHT(c) 2016 STMicroelectronics & lt; /center & gt; & lt; /h2 & gt;
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS " AS IS "
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f0xx
* @{
*/
#ifndef __STM32F0xx_H
#define __STM32F0xx_H
#ifdef __cplusplus
extern " C " {
#endif /* __cplusplus */
/** @addtogroup Library_configuration_section
* @{
*/
/**
* @brief STM32 Family
*/
#if !defined (STM32F0)
#define STM32F0
#endif /* STM32F0 */
/* Uncomment the line below according to the target STM32 device used in your
application
*/
#if !defined (STM32F030x6) & & !defined (STM32F030x8) & & \
!defined (STM32F031x6) & & !defined (STM32F038xx) & & \
!defined (STM32F042x6) & & !defined (STM32F048xx) & & !defined (STM32F070x6) & & \
!defined (STM32F051x8) & & !defined (STM32F058xx) & & \
!defined (STM32F071xB) & & !defined (STM32F072xB) & & !defined (STM32F078xx) & & !defined (STM32F070xB) & & \
!defined (STM32F091xC) & & !defined (STM32F098xx) & & !defined (STM32F030xC)
/* #define STM32F030x6 */ /*! & lt; STM32F030x4, STM32F030x6 Devices (STM32F030xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
/* #define STM32F030x8 */ /*! & lt; STM32F030x8 Devices (STM32F030xx microcontrollers where the Flash memory is 64 Kbytes) */
/* #define STM32F031x6 */ /*! & lt; STM32F031x4, STM32F031x6 Devices (STM32F031xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
/* #define STM32F038xx */ /*! & lt; STM32F038xx Devices (STM32F038xx microcontrollers where the Flash memory is 32 Kbytes) */
/* #define STM32F042x6 */ /*! & lt; STM32F042x4, STM32F042x6 Devices (STM32F042xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
/* #define STM32F048x6 */ /*! & lt; STM32F048xx Devices (STM32F042xx microcontrollers where the Flash memory is 32 Kbytes) */
/* #define STM32F051x8 */ /*! & lt; STM32F051x4, STM32F051x6, STM32F051x8 Devices (STM32F051xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes) */
/* #define STM32F058xx */ /*! & lt; STM32F058xx Devices (STM32F058xx microcontrollers where the Flash memory is 64 Kbytes) */
/* #define STM32F070x6 */ /*! & lt; STM32F070x6 Devices (STM32F070x6 microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
/* #define STM32F070xB */ /*! & lt; STM32F070xB Devices (STM32F070xB microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
/* #define STM32F071xB */ /*! & lt; STM32F071x8, STM32F071xB Devices (STM32F071xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
/* #define STM32F072xB */ /*! & lt; STM32F072x8, STM32F072xB Devices (STM32F072xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
/* #define STM32F078xx */ /*! & lt; STM32F078xx Devices (STM32F078xx microcontrollers where the Flash memory is 128 Kbytes) */
/* #define STM32F030xC */ /*! & lt; STM32F030xC Devices (STM32F030xC microcontrollers where the Flash memory is 256 Kbytes) */
/* #define STM32F091xC */ /*! & lt; STM32F091xB, STM32F091xC Devices (STM32F091xx microcontrollers where the Flash memory ranges between 128 and 256 Kbytes) */
/* #define STM32F098xx */ /*! & lt; STM32F098xx Devices (STM32F098xx microcontrollers where the Flash memory is 256 Kbytes) */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
*/
#if !defined (USE_HAL_DRIVER)
/**
* @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
/*#define USE_HAL_DRIVER */
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.3.1
*/
#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*! & lt; [31:24] main version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*! & lt; [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x01) /*! & lt; [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_RC (0x00) /*! & lt; [7:0] release candidate */
#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN & lt; & lt; 24)\
|(__STM32F0_DEVICE_VERSION_SUB1 & lt; & lt; 16)\
|(__STM32F0_DEVICE_VERSION_SUB2 & lt; & lt; 8 )\
|(__STM32F0_DEVICE_VERSION_RC))
/**
* @}
*/
/** @addtogroup Device_Included
* @{
*/
#if defined(STM32F030x6)
#include " stm32f030x6.h "
#elif defined(STM32F030x8)
#include " stm32f030x8.h "
#elif defined(STM32F031x6)
#include " stm32f031x6.h "
#elif defined(STM32F038xx)
#include " stm32f038xx.h "
#elif defined(STM32F042x6)
#include " stm32f042x6.h "
#elif defined(STM32F048xx)
#include " stm32f048xx.h "
#elif defined(STM32F051x8)
#include " stm32f051x8.h "
#elif defined(STM32F058xx)
#include " stm32f058xx.h "
#elif defined(STM32F070x6)
#include " stm32f070x6.h "
#elif defined(STM32F070xB)
#include " stm32f070xb.h "
#elif defined(STM32F071xB)
#include " stm32f071xb.h "
#elif defined(STM32F072xB)
#include " stm32f072xb.h "
#elif defined(STM32F078xx)
#include " stm32f078xx.h "
#elif defined(STM32F091xC)
#include " stm32f091xc.h "
#elif defined(STM32F098xx)
#include " stm32f098xx.h "
#elif defined(STM32F030xC)
#include " stm32f030xc.h "
#else
#error " Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file) "
#endif
/**
* @}
*/
/** @addtogroup Exported_types
* @{
*/
typedef enum
{
RESET = 0,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
{
DISABLE = 0,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum
{
ERROR = 0,
SUCCESS = !ERROR
} ErrorStatus;
/**
* @}
*/
/** @addtogroup Exported_macros
* @{
*/
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) & = ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
/**
* @}
*/
#if defined (USE_HAL_DRIVER)
#include " stm32f0xx_hal.h "
#endif /* USE_HAL_DRIVER */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __STM32F0xx_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file system_stm32f0xx.h
* @author MCD Application Team
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
******************************************************************************
* @attention
*
* & lt; h2 & gt; & lt; center & gt; & copy; COPYRIGHT(c) 2016 STMicroelectronics & lt; /center & gt; & lt; /h2 & gt;
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS " AS IS "
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f0xx_system
* @{
*/
/**
* @brief Define to prevent recursive inclusion
*/
#ifndef __SYSTEM_STM32F0XX_H
#define __SYSTEM_STM32F0XX_H
#ifdef __cplusplus
extern " C " {
#endif
/** @addtogroup STM32F0xx_System_Includes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F0xx_System_Exported_types
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
3) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) by calling HAL API function HAL_RCC_ClockConfig()
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*! & lt; System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*! & lt; AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*! & lt; APB prescalers table values */
/**
* @}
*/
/** @addtogroup STM32F0xx_System_Exported_Constants
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F0xx_System_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F0xx_System_Exported_Functions
* @{
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__SYSTEM_STM32F0XX_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
/**************************************************************************//**
* @file core_cmSimd.h
* @brief CMSIS Cortex-M SIMD Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS " AS IS "
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) & & (__ARMCC_VERSION & gt; = 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMSIMD_H
#define __CORE_CMSIMD_H
#ifdef __cplusplus
extern " C " {
#endif
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include " cmsis_armcc.h "
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) & & (__ARMCC_VERSION & gt; = 6010050)
#include " cmsis_armcc_V6.h "
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include " cmsis_gcc.h "
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include & lt; cmsis_iar.h & gt;
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include & lt; cmsis_ccs.h & gt;
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use " carm -?i " to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include & lt; cmsis_csm.h & gt;
#endif
/*@} end of group CMSIS_SIMD_intrinsics */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CMSIMD_H */
/* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
*
* $Date: 19. March 2015
* $Revision: V.1.4.5
*
* Project: CMSIS DSP Library
* Title: arm_const_structs.h
*
* Description: This file has constant structs that are initialized for
* user convenience. For example, some can be given as
* arguments to the arm_cfft_f32() function.
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* " AS IS " AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_CONST_STRUCTS_H
#define _ARM_CONST_STRUCTS_H
#include " arm_math.h "
#include " arm_common_tables.h "
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
#endif
/**************************************************************************//**
* @file core_cm3.h
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS " AS IS "
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) & & (__ARMCC_VERSION & gt; = 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM3_H_GENERIC
#define __CORE_CM3_H_GENERIC
#include & lt; stdint.h & gt;
#ifdef __cplusplus
extern " C " {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file. & lt; br & gt;
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'. & lt; br & gt;
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined. & lt; br & gt;
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M3
@{
*/
/* CMSIS CM3 definitions */
#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*! & lt; [31:16] CMSIS HAL main version */
#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*! & lt; [15:0] CMSIS HAL sub version */
#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN & lt; & lt; 16U) | \
__CM3_CMSIS_VERSION_SUB ) /*! & lt; CMSIS HAL version number */
#define __CORTEX_M (0x03U) /*! & lt; Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*! & lt; asm keyword for ARM Compiler */
#define __INLINE __inline /*! & lt; inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined(__ARMCC_VERSION) & & (__ARMCC_VERSION & gt; = 6010050)
#define __ASM __asm /*! & lt; asm keyword for ARM Compiler */
#define __INLINE __inline /*! & lt; inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*! & lt; asm keyword for GNU Compiler */
#define __INLINE inline /*! & lt; inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*! & lt; asm keyword for IAR Compiler */
#define __INLINE inline /*! & lt; inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __TMS470__ )
#define __ASM __asm /*! & lt; asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*! & lt; asm keyword for TASKING Compiler */
#define __INLINE inline /*! & lt; inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __CSMC__ )
#define __packed
#define __ASM _asm /*! & lt; asm keyword for COSMIC Compiler */
#define __INLINE inline /*! & lt; inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline
#else
#error Unknown compiler
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error " Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) "
#endif
#elif defined(__ARMCC_VERSION) & & (__ARMCC_VERSION & gt; = 6010050)
#if defined __ARM_PCS_VFP
#error " Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) "
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) & & !defined(__SOFTFP__)
#error " Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) "
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error " Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) "
#endif
#elif defined ( __TMS470__ )
#if defined __TI_VFP_SUPPORT__
#error " Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) "
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error " Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) "
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error " Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) "
#endif
#endif
#include " core_cmInstr.h " /* Core Instruction Access */
#include " core_cmFunc.h " /* Core Function Access */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM3_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM3_H_DEPENDANT
#define __CORE_CM3_H_DEPENDANT
#ifdef __cplusplus
extern " C " {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM3_REV
#define __CM3_REV 0x0200U
#warning " __CM3_REV not defined in device header file; using default! "
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning " __MPU_PRESENT not defined in device header file; using default! "
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 4U
#warning " __NVIC_PRIO_BITS not defined in device header file; using default! "
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning " __Vendor_SysTickConfig not defined in device header file; using default! "
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
& lt; strong & gt; IO Type Qualifiers & lt; /strong & gt; are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*! & lt; Defines 'read only' permissions */
#else
#define __I volatile const /*! & lt; Defines 'read only' permissions */
#endif
#define __O volatile /*! & lt; Defines 'write only' permissions */
#define __IO volatile /*! & lt; Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M3 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core Debug Register
- Core MPU Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:27; /*! & lt; bit: 0..26 Reserved */
uint32_t Q:1; /*! & lt; bit: 27 Saturation condition flag */
uint32_t V:1; /*! & lt; bit: 28 Overflow condition code flag */
uint32_t C:1; /*! & lt; bit: 29 Carry condition code flag */
uint32_t Z:1; /*! & lt; bit: 30 Zero condition code flag */
uint32_t N:1; /*! & lt; bit: 31 Negative condition code flag */
} b; /*! & lt; Structure used for bit access */
uint32_t w; /*! & lt; Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*! & lt; APSR: N Position */
#define APSR_N_Msk (1UL & lt; & lt; APSR_N_Pos) /*! & lt; APSR: N Mask */
#define APSR_Z_Pos 30U /*! & lt; APSR: Z Position */
#define APSR_Z_Msk (1UL & lt; & lt; APSR_Z_Pos) /*! & lt; APSR: Z Mask */
#define APSR_C_Pos 29U /*! & lt; APSR: C Position */
#define APSR_C_Msk (1UL & lt; & lt; APSR_C_Pos) /*! & lt; APSR: C Mask */
#define APSR_V_Pos 28U /*! & lt; APSR: V Position */
#define APSR_V_Msk (1UL & lt; & lt; APSR_V_Pos) /*! & lt; APSR: V Mask */
#define APSR_Q_Pos 27U /*! & lt; APSR: Q Position */
#define APSR_Q_Msk (1UL & lt; & lt; APSR_Q_Pos) /*! & lt; APSR: Q Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*! & lt; bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*! & lt; bit: 9..31 Reserved */
} b; /*! & lt; Structure used for bit access */
uint32_t w; /*! & lt; Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*! & lt; IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /* & lt; & lt; IPSR_ISR_Pos*/) /*! & lt; IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*! & lt; bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*! & lt; bit: 9..23 Reserved */
uint32_t T:1; /*! & lt; bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*! & lt; bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*! & lt; bit: 27 Saturation condition flag */
uint32_t V:1; /*! & lt; bit: 28 Overflow condition code flag */
uint32_t C:1; /*! & lt; bit: 29 Carry condition code flag */
uint32_t Z:1; /*! & lt; bit: 30 Zero condition code flag */
uint32_t N:1; /*! & lt; bit: 31 Negative condition code flag */
} b; /*! & lt; Structure used for bit access */
uint32_t w; /*! & lt; Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*! & lt; xPSR: N Position */
#define xPSR_N_Msk (1UL & lt; & lt; xPSR_N_Pos) /*! & lt; xPSR: N Mask */
#define xPSR_Z_Pos 30U /*! & lt; xPSR: Z Position */
#define xPSR_Z_Msk (1UL & lt; & lt; xPSR_Z_Pos) /*! & lt; xPSR: Z Mask */
#define xPSR_C_Pos 29U /*! & lt; xPSR: C Position */
#define xPSR_C_Msk (1UL & lt; & lt; xPSR_C_Pos) /*! & lt; xPSR: C Mask */
#define xPSR_V_Pos 28U /*! & lt; xPSR: V Position */
#define xPSR_V_Msk (1UL & lt; & lt; xPSR_V_Pos) /*! & lt; xPSR: V Mask */
#define xPSR_Q_Pos 27U /*! & lt; xPSR: Q Position */
#define xPSR_Q_Msk (1UL & lt; & lt; xPSR_Q_Pos) /*! & lt; xPSR: Q Mask */
#define xPSR_IT_Pos 25U /*! & lt; xPSR: IT Position */
#define xPSR_IT_Msk (3UL & lt; & lt; xPSR_IT_Pos) /*! & lt; xPSR: IT Mask */
#define xPSR_T_Pos 24U /*! & lt; xPSR: T Position */
#define xPSR_T_Msk (1UL & lt; & lt; xPSR_T_Pos) /*! & lt; xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*! & lt; xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /* & lt; & lt; xPSR_ISR_Pos*/) /*! & lt; xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*! & lt; bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*! & lt; bit: 1 Stack to be used */
uint32_t _reserved1:30; /*! & lt; bit: 2..31 Reserved */
} b; /*! & lt; Structure used for bit access */
uint32_t w; /*! & lt; Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*! & lt; CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL & lt; & lt; CONTROL_SPSEL_Pos) /*! & lt; CONTROL: SPSEL Mask */
#define CONTROL_nPRIV_Pos 0U /*! & lt; CONTROL: nPRIV Position */
#define CONTROL_nPRIV_Msk (1UL /* & lt; & lt; CONTROL_nPRIV_Pos*/) /*! & lt; CONTROL: nPRIV Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[8U]; /*! & lt; Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[24U];
__IOM uint32_t ICER[8U]; /*! & lt; Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[24U];
__IOM uint32_t ISPR[8U]; /*! & lt; Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[24U];
__IOM uint32_t ICPR[8U]; /*! & lt; Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[24U];
__IOM uint32_t IABR[8U]; /*! & lt; Offset: 0x200 (R/W) Interrupt Active bit Register */
uint32_t RESERVED4[56U];
__IOM uint8_t IP[240U]; /*! & lt; Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
uint32_t RESERVED5[644U];
__OM uint32_t STIR; /*! & lt; Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
} NVIC_Type;
/* Software Triggered Interrupt Register Definitions */
#define NVIC_STIR_INTID_Pos 0U /*! & lt; STIR: INTLINESNUM Position */
#define NVIC_STIR_INTID_Msk (0x1FFUL /* & lt; & lt; NVIC_STIR_INTID_Pos*/) /*! & lt; STIR: INTLINESNUM Mask */
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*! & lt; Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*! & lt; Offset: 0x004 (R/W) Interrupt Control and State Register */
__IOM uint32_t VTOR; /*! & lt; Offset: 0x008 (R/W) Vector Table Offset Register */
__IOM uint32_t AIRCR; /*! & lt; Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*! & lt; Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*! & lt; Offset: 0x014 (R/W) Configuration Control Register */
__IOM uint8_t SHP[12U]; /*! & lt; Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
__IOM uint32_t SHCSR; /*! & lt; Offset: 0x024 (R/W) System Handler Control and State Register */
__IOM uint32_t CFSR; /*! & lt; Offset: 0x028 (R/W) Configurable Fault Status Register */
__IOM uint32_t HFSR; /*! & lt; Offset: 0x02C (R/W) HardFault Status Register */
__IOM uint32_t DFSR; /*! & lt; Offset: 0x030 (R/W) Debug Fault Status Register */
__IOM uint32_t MMFAR; /*! & lt; Offset: 0x034 (R/W) MemManage Fault Address Register */
__IOM uint32_t BFAR; /*! & lt; Offset: 0x038 (R/W) BusFault Address Register */
__IOM uint32_t AFSR; /*! & lt; Offset: 0x03C (R/W) Auxiliary Fault Status Register */
__IM uint32_t PFR[2U]; /*! & lt; Offset: 0x040 (R/ ) Processor Feature Register */
__IM uint32_t DFR; /*! & lt; Offset: 0x048 (R/ ) Debug Feature Register */
__IM uint32_t ADR; /*! & lt; Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t MMFR[4U]; /*! & lt; Offset: 0x050 (R/ ) Memory Model Feature Register */
__IM uint32_t ISAR[5U]; /*! & lt; Offset: 0x060 (R/ ) Instruction Set Attributes Register */
uint32_t RESERVED0[5U];
__IOM uint32_t CPACR; /*! & lt; Offset: 0x088 (R/W) Coprocessor Access Control Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*! & lt; SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL & lt; & lt; SCB_CPUID_IMPLEMENTER_Pos) /*! & lt; SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*! & lt; SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL & lt; & lt; SCB_CPUID_VARIANT_Pos) /*! & lt; SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*! & lt; SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL & lt; & lt; SCB_CPUID_ARCHITECTURE_Pos) /*! & lt; SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*! & lt; SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL & lt; & lt; SCB_CPUID_PARTNO_Pos) /*! & lt; SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*! & lt; SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /* & lt; & lt; SCB_CPUID_REVISION_Pos*/) /*! & lt; SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*! & lt; SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL & lt; & lt; SCB_ICSR_NMIPENDSET_Pos) /*! & lt; SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*! & lt; SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL & lt; & lt; SCB_ICSR_PENDSVSET_Pos) /*! & lt; SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*! & lt; SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL & lt; & lt; SCB_ICSR_PENDSVCLR_Pos) /*! & lt; SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*! & lt; SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL & lt; & lt; SCB_ICSR_PENDSTSET_Pos) /*! & lt; SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*! & lt; SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL & lt; & lt; SCB_ICSR_PENDSTCLR_Pos) /*! & lt; SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*! & lt; SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL & lt; & lt; SCB_ICSR_ISRPREEMPT_Pos) /*! & lt; SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*! & lt; SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL & lt; & lt; SCB_ICSR_ISRPENDING_Pos) /*! & lt; SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*! & lt; SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL & lt; & lt; SCB_ICSR_VECTPENDING_Pos) /*! & lt; SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_RETTOBASE_Pos 11U /*! & lt; SCB ICSR: RETTOBASE Position */
#define SCB_ICSR_RETTOBASE_Msk (1UL & lt; & lt; SCB_ICSR_RETTOBASE_Pos) /*! & lt; SCB ICSR: RETTOBASE Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*! & lt; SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /* & lt; & lt; SCB_ICSR_VECTACTIVE_Pos*/) /*! & lt; SCB ICSR: VECTACTIVE Mask */
/* SCB Vector Table Offset Register Definitions */
#if (__CM3_REV & lt; 0x0201U) /* core r2p1 */
#define SCB_VTOR_TBLBASE_Pos 29U /*! & lt; SCB VTOR: TBLBASE Position */
#define SCB_VTOR_TBLBASE_Msk (1UL & lt; & lt; SCB_VTOR_TBLBASE_Pos) /*! & lt; SCB VTOR: TBLBASE Mask */
#define SCB_VTOR_TBLOFF_Pos 7U /*! & lt; SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL & lt; & lt; SCB_VTOR_TBLOFF_Pos) /*! & lt; SCB VTOR: TBLOFF Mask */
#else
#define SCB_VTOR_TBLOFF_Pos 7U /*! & lt; SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL & lt; & lt; SCB_VTOR_TBLOFF_Pos) /*! & lt; SCB VTOR: TBLOFF Mask */
#endif
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*! & lt; SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL & lt; & lt; SCB_AIRCR_VECTKEY_Pos) /*! & lt; SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*! & lt; SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL & lt; & lt; SCB_AIRCR_VECTKEYSTAT_Pos) /*! & lt; SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*! & lt; SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL & lt; & lt; SCB_AIRCR_ENDIANESS_Pos) /*! & lt; SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_PRIGROUP_Pos 8U /*! & lt; SCB AIRCR: PRIGROUP Position */
#define SCB_AIRCR_PRIGROUP_Msk (7UL & lt; & lt; SCB_AIRCR_PRIGROUP_Pos) /*! & lt; SCB AIRCR: PRIGROUP Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*! & lt; SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL & lt; & lt; SCB_AIRCR_SYSRESETREQ_Pos) /*! & lt; SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*! & lt; SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL & lt; & lt; SCB_AIRCR_VECTCLRACTIVE_Pos) /*! & lt; SCB AIRCR: VECTCLRACTIVE Mask */
#define SCB_AIRCR_VECTRESET_Pos 0U /*! & lt; SCB AIRCR: VECTRESET Position */
#define SCB_AIRCR_VECTRESET_Msk (1UL /* & lt; & lt; SCB_AIRCR_VECTRESET_Pos*/) /*! & lt; SCB AIRCR: VECTRESET Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*! & lt; SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL & lt; & lt; SCB_SCR_SEVONPEND_Pos) /*! & lt; SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*! & lt; SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL & lt; & lt; SCB_SCR_SLEEPDEEP_Pos) /*! & lt; SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*! & lt; SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL & lt; & lt; SCB_SCR_SLEEPONEXIT_Pos) /*! & lt; SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*! & lt; SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL & lt; & lt; SCB_CCR_STKALIGN_Pos) /*! & lt; SCB CCR: STKALIGN Mask */
#define SCB_CCR_BFHFNMIGN_Pos 8U /*! & lt; SCB CCR: BFHFNMIGN Position */
#define SCB_CCR_BFHFNMIGN_Msk (1UL & lt; & lt; SCB_CCR_BFHFNMIGN_Pos) /*! & lt; SCB CCR: BFHFNMIGN Mask */
#define SCB_CCR_DIV_0_TRP_Pos 4U /*! & lt; SCB CCR: DIV_0_TRP Position */
#define SCB_CCR_DIV_0_TRP_Msk (1UL & lt; & lt; SCB_CCR_DIV_0_TRP_Pos) /*! & lt; SCB CCR: DIV_0_TRP Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*! & lt; SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL & lt; & lt; SCB_CCR_UNALIGN_TRP_Pos) /*! & lt; SCB CCR: UNALIGN_TRP Mask */
#define SCB_CCR_USERSETMPEND_Pos 1U /*! & lt; SCB CCR: USERSETMPEND Position */
#define SCB_CCR_USERSETMPEND_Msk (1UL & lt; & lt; SCB_CCR_USERSETMPEND_Pos) /*! & lt; SCB CCR: USERSETMPEND Mask */
#define SCB_CCR_NONBASETHRDENA_Pos 0U /*! & lt; SCB CCR: NONBASETHRDENA Position */
#define SCB_CCR_NONBASETHRDENA_Msk (1UL /* & lt; & lt; SCB_CCR_NONBASETHRDENA_Pos*/) /*! & lt; SCB CCR: NONBASETHRDENA Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_USGFAULTENA_Pos 18U /*! & lt; SCB SHCSR: USGFAULTENA Position */
#define SCB_SHCSR_USGFAULTENA_Msk (1UL & lt; & lt; SCB_SHCSR_USGFAULTENA_Pos) /*! & lt; SCB SHCSR: USGFAULTENA Mask */
#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*! & lt; SCB SHCSR: BUSFAULTENA Position */
#define SCB_SHCSR_BUSFAULTENA_Msk (1UL & lt; & lt; SCB_SHCSR_BUSFAULTENA_Pos) /*! & lt; SCB SHCSR: BUSFAULTENA Mask */
#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*! & lt; SCB SHCSR: MEMFAULTENA Position */
#define SCB_SHCSR_MEMFAULTENA_Msk (1UL & lt; & lt; SCB_SHCSR_MEMFAULTENA_Pos) /*! & lt; SCB SHCSR: MEMFAULTENA Mask */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*! & lt; SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL & lt; & lt; SCB_SHCSR_SVCALLPENDED_Pos) /*! & lt; SCB SHCSR: SVCALLPENDED Mask */
#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*! & lt; SCB SHCSR: BUSFAULTPENDED Position */
#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL & lt; & lt; SCB_SHCSR_BUSFAULTPENDED_Pos) /*! & lt; SCB SHCSR: BUSFAULTPENDED Mask */
#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*! & lt; SCB SHCSR: MEMFAULTPENDED Position */
#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL & lt; & lt; SCB_SHCSR_MEMFAULTPENDED_Pos) /*! & lt; SCB SHCSR: MEMFAULTPENDED Mask */
#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*! & lt; SCB SHCSR: USGFAULTPENDED Position */
#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL & lt; & lt; SCB_SHCSR_USGFAULTPENDED_Pos) /*! & lt; SCB SHCSR: USGFAULTPENDED Mask */
#define SCB_SHCSR_SYSTICKACT_Pos 11U /*! & lt; SCB SHCSR: SYSTICKACT Position */
#define SCB_SHCSR_SYSTICKACT_Msk (1UL & lt; & lt; SCB_SHCSR_SYSTICKACT_Pos) /*! & lt; SCB SHCSR: SYSTICKACT Mask */
#define SCB_SHCSR_PENDSVACT_Pos 10U /*! & lt; SCB SHCSR: PENDSVACT Position */
#define SCB_SHCSR_PENDSVACT_Msk (1UL & lt; & lt; SCB_SHCSR_PENDSVACT_Pos) /*! & lt; SCB SHCSR: PENDSVACT Mask */
#define SCB_SHCSR_MONITORACT_Pos 8U /*! & lt; SCB SHCSR: MONITORACT Position */
#define SCB_SHCSR_MONITORACT_Msk (1UL & lt; & lt; SCB_SHCSR_MONITORACT_Pos) /*! & lt; SCB SHCSR: MONITORACT Mask */
#define SCB_SHCSR_SVCALLACT_Pos 7U /*! & lt; SCB SHCSR: SVCALLACT Position */
#define SCB_SHCSR_SVCALLACT_Msk (1UL & lt; & lt; SCB_SHCSR_SVCALLACT_Pos) /*! & lt; SCB SHCSR: SVCALLACT Mask */
#define SCB_SHCSR_USGFAULTACT_Pos 3U /*! & lt; SCB SHCSR: USGFAULTACT Position */
#define SCB_SHCSR_USGFAULTACT_Msk (1UL & lt; & lt; SCB_SHCSR_USGFAULTACT_Pos) /*! & lt; SCB SHCSR: USGFAULTACT Mask */
#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*! & lt; SCB SHCSR: BUSFAULTACT Position */
#define SCB_SHCSR_BUSFAULTACT_Msk (1UL & lt; & lt; SCB_SHCSR_BUSFAULTACT_Pos) /*! & lt; SCB SHCSR: BUSFAULTACT Mask */
#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*! & lt; SCB SHCSR: MEMFAULTACT Position */
#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /* & lt; & lt; SCB_SHCSR_MEMFAULTACT_Pos*/) /*! & lt; SCB SHCSR: MEMFAULTACT Mask */
/* SCB Configurable Fault Status Register Definitions */
#define SCB_CFSR_USGFAULTSR_Pos 16U /*! & lt; SCB CFSR: Usage Fault Status Register Position */
#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL & lt; & lt; SCB_CFSR_USGFAULTSR_Pos) /*! & lt; SCB CFSR: Usage Fault Status Register Mask */
#define SCB_CFSR_BUSFAULTSR_Pos 8U /*! & lt; SCB CFSR: Bus Fault Status Register Position */
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL & lt; & lt; SCB_CFSR_BUSFAULTSR_Pos) /*! & lt; SCB CFSR: Bus Fault Status Register Mask */
#define SCB_CFSR_MEMFAULTSR_Pos 0U /*! & lt; SCB CFSR: Memory Manage Fault Status Register Position */
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /* & lt; & lt; SCB_CFSR_MEMFAULTSR_Pos*/) /*! & lt; SCB CFSR: Memory Manage Fault Status Register Mask */
/* SCB Hard Fault Status Register Definitions */
#define SCB_HFSR_DEBUGEVT_Pos 31U /*! & lt; SCB HFSR: DEBUGEVT Position */
#define SCB_HFSR_DEBUGEVT_Msk (1UL & lt; & lt; SCB_HFSR_DEBUGEVT_Pos) /*! & lt; SCB HFSR: DEBUGEVT Mask */
#define SCB_HFSR_FORCED_Pos 30U /*! & lt; SCB HFSR: FORCED Position */
#define SCB_HFSR_FORCED_Msk (1UL & lt; & lt; SCB_HFSR_FORCED_Pos) /*! & lt; SCB HFSR: FORCED Mask */
#define SCB_HFSR_VECTTBL_Pos 1U /*! & lt; SCB HFSR: VECTTBL Position */
#define SCB_HFSR_VECTTBL_Msk (1UL & lt; & lt; SCB_HFSR_VECTTBL_Pos) /*! & lt; SCB HFSR: VECTTBL Mask */
/* SCB Debug Fault Status Register Definitions */
#define SCB_DFSR_EXTERNAL_Pos 4U /*! & lt; SCB DFSR: EXTERNAL Position */
#define SCB_DFSR_EXTERNAL_Msk (1UL & lt; & lt; SCB_DFSR_EXTERNAL_Pos) /*! & lt; SCB DFSR: EXTERNAL Mask */
#define SCB_DFSR_VCATCH_Pos 3U /*! & lt; SCB DFSR: VCATCH Position */
#define SCB_DFSR_VCATCH_Msk (1UL & lt; & lt; SCB_DFSR_VCATCH_Pos) /*! & lt; SCB DFSR: VCATCH Mask */
#define SCB_DFSR_DWTTRAP_Pos 2U /*! & lt; SCB DFSR: DWTTRAP Position */
#define SCB_DFSR_DWTTRAP_Msk (1UL & lt; & lt; SCB_DFSR_DWTTRAP_Pos) /*! & lt; SCB DFSR: DWTTRAP Mask */
#define SCB_DFSR_BKPT_Pos 1U /*! & lt; SCB DFSR: BKPT Position */
#define SCB_DFSR_BKPT_Msk (1UL & lt; & lt; SCB_DFSR_BKPT_Pos) /*! & lt; SCB DFSR: BKPT Mask */
#define SCB_DFSR_HALTED_Pos 0U /*! & lt; SCB DFSR: HALTED Position */
#define SCB_DFSR_HALTED_Msk (1UL /* & lt; & lt; SCB_DFSR_HALTED_Pos*/) /*! & lt; SCB DFSR: HALTED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[1U];
__IM uint32_t ICTR; /*! & lt; Offset: 0x004 (R/ ) Interrupt Controller Type Register */
#if ((defined __CM3_REV) & & (__CM3_REV & gt; = 0x200U))
__IOM uint32_t ACTLR; /*! & lt; Offset: 0x008 (R/W) Auxiliary Control Register */
#else
uint32_t RESERVED1[1U];
#endif
} SCnSCB_Type;
/* Interrupt Controller Type Register Definitions */
#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*! & lt; ICTR: INTLINESNUM Position */
#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /* & lt; & lt; SCnSCB_ICTR_INTLINESNUM_Pos*/) /*! & lt; ICTR: INTLINESNUM Mask */
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*! & lt; ACTLR: DISFOLD Position */
#define SCnSCB_ACTLR_DISFOLD_Msk (1UL & lt; & lt; SCnSCB_ACTLR_DISFOLD_Pos) /*! & lt; ACTLR: DISFOLD Mask */
#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*! & lt; ACTLR: DISDEFWBUF Position */
#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL & lt; & lt; SCnSCB_ACTLR_DISDEFWBUF_Pos) /*! & lt; ACTLR: DISDEFWBUF Mask */
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*! & lt; ACTLR: DISMCYCINT Position */
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /* & lt; & lt; SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*! & lt; ACTLR: DISMCYCINT Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*! & lt; Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*! & lt; Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*! & lt; Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*! & lt; Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*! & lt; SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL & lt; & lt; SysTick_CTRL_COUNTFLAG_Pos) /*! & lt; SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*! & lt; SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL & lt; & lt; SysTick_CTRL_CLKSOURCE_Pos) /*! & lt; SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*! & lt; SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL & lt; & lt; SysTick_CTRL_TICKINT_Pos) /*! & lt; SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*! & lt; SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /* & lt; & lt; SysTick_CTRL_ENABLE_Pos*/) /*! & lt; SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*! & lt; SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /* & lt; & lt; SysTick_LOAD_RELOAD_Pos*/) /*! & lt; SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*! & lt; SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /* & lt; & lt; SysTick_VAL_CURRENT_Pos*/) /*! & lt; SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*! & lt; SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL & lt; & lt; SysTick_CALIB_NOREF_Pos) /*! & lt; SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*! & lt; SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL & lt; & lt; SysTick_CALIB_SKEW_Pos) /*! & lt; SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*! & lt; SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /* & lt; & lt; SysTick_CALIB_TENMS_Pos*/) /*! & lt; SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
@{
*/
/**
\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
*/
typedef struct
{
__OM union
{
__OM uint8_t u8; /*! & lt; Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
__OM uint16_t u16; /*! & lt; Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
__OM uint32_t u32; /*! & lt; Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
} PORT [32U]; /*! & lt; Offset: 0x000 ( /W) ITM Stimulus Port Registers */
uint32_t RESERVED0[864U];
__IOM uint32_t TER; /*! & lt; Offset: 0xE00 (R/W) ITM Trace Enable Register */
uint32_t RESERVED1[15U];
__IOM uint32_t TPR; /*! & lt; Offset: 0xE40 (R/W) ITM Trace Privilege Register */
uint32_t RESERVED2[15U];
__IOM uint32_t TCR; /*! & lt; Offset: 0xE80 (R/W) ITM Trace Control Register */
uint32_t RESERVED3[29U];
__OM uint32_t IWR; /*! & lt; Offset: 0xEF8 ( /W) ITM Integration Write Register */
__IM uint32_t IRR; /*! & lt; Offset: 0xEFC (R/ ) ITM Integration Read Register */
__IOM uint32_t IMCR; /*! & lt; Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
uint32_t RESERVED4[43U];
__OM uint32_t LAR; /*! & lt; Offset: 0xFB0 ( /W) ITM Lock Access Register */
__IM uint32_t LSR; /*! & lt; Offset: 0xFB4 (R/ ) ITM Lock Status Register */
uint32_t RESERVED5[6U];
__IM uint32_t PID4; /*! & lt; Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
__IM uint32_t PID5; /*! & lt; Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
__IM uint32_t PID6; /*! & lt; Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
__IM uint32_t PID7; /*! & lt; Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
__IM uint32_t PID0; /*! & lt; Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
__IM uint32_t PID1; /*! & lt; Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
__IM uint32_t PID2; /*! & lt; Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
__IM uint32_t PID3; /*! & lt; Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
__IM uint32_t CID0; /*! & lt; Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
__IM uint32_t CID1; /*! & lt; Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
__IM uint32_t CID2; /*! & lt; Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
__IM uint32_t CID3; /*! & lt; Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
} ITM_Type;
/* ITM Trace Privilege Register Definitions */
#define ITM_TPR_PRIVMASK_Pos 0U /*! & lt; ITM TPR: PRIVMASK Position */
#define ITM_TPR_PRIVMASK_Msk (0xFUL /* & lt; & lt; ITM_TPR_PRIVMASK_Pos*/) /*! & lt; ITM TPR: PRIVMASK Mask */
/* ITM Trace Control Register Definitions */
#define ITM_TCR_BUSY_Pos 23U /*! & lt; ITM TCR: BUSY Position */
#define ITM_TCR_BUSY_Msk (1UL & lt; & lt; ITM_TCR_BUSY_Pos) /*! & lt; ITM TCR: BUSY Mask */
#define ITM_TCR_TraceBusID_Pos 16U /*! & lt; ITM TCR: ATBID Position */
#define ITM_TCR_TraceBusID_Msk (0x7FUL & lt; & lt; ITM_TCR_TraceBusID_Pos) /*! & lt; ITM TCR: ATBID Mask */
#define ITM_TCR_GTSFREQ_Pos 10U /*! & lt; ITM TCR: Global timestamp frequency Position */
#define ITM_TCR_GTSFREQ_Msk (3UL & lt; & lt; ITM_TCR_GTSFREQ_Pos) /*! & lt; ITM TCR: Global timestamp frequency Mask */
#define ITM_TCR_TSPrescale_Pos 8U /*! & lt; ITM TCR: TSPrescale Position */
#define ITM_TCR_TSPrescale_Msk (3UL & lt; & lt; ITM_TCR_TSPrescale_Pos) /*! & lt; ITM TCR: TSPrescale Mask */
#define ITM_TCR_SWOENA_Pos 4U /*! & lt; ITM TCR: SWOENA Position */
#define ITM_TCR_SWOENA_Msk (1UL & lt; & lt; ITM_TCR_SWOENA_Pos) /*! & lt; ITM TCR: SWOENA Mask */
#define ITM_TCR_DWTENA_Pos 3U /*! & lt; ITM TCR: DWTENA Position */
#define ITM_TCR_DWTENA_Msk (1UL & lt; & lt; ITM_TCR_DWTENA_Pos) /*! & lt; ITM TCR: DWTENA Mask */
#define ITM_TCR_SYNCENA_Pos 2U /*! & lt; ITM TCR: SYNCENA Position */
#define ITM_TCR_SYNCENA_Msk (1UL & lt; & lt; ITM_TCR_SYNCENA_Pos) /*! & lt; ITM TCR: SYNCENA Mask */
#define ITM_TCR_TSENA_Pos 1U /*! & lt; ITM TCR: TSENA Position */
#define ITM_TCR_TSENA_Msk (1UL & lt; & lt; ITM_TCR_TSENA_Pos) /*! & lt; ITM TCR: TSENA Mask */
#define ITM_TCR_ITMENA_Pos 0U /*! & lt; ITM TCR: ITM Enable bit Position */
#define ITM_TCR_ITMENA_Msk (1UL /* & lt; & lt; ITM_TCR_ITMENA_Pos*/) /*! & lt; ITM TCR: ITM Enable bit Mask */
/* ITM Integration Write Register Definitions */
#define ITM_IWR_ATVALIDM_Pos 0U /*! & lt; ITM IWR: ATVALIDM Position */
#define ITM_IWR_ATVALIDM_Msk (1UL /* & lt; & lt; ITM_IWR_ATVALIDM_Pos*/) /*! & lt; ITM IWR: ATVALIDM Mask */
/* ITM Integration Read Register Definitions */
#define ITM_IRR_ATREADYM_Pos 0U /*! & lt; ITM IRR: ATREADYM Position */
#define ITM_IRR_ATREADYM_Msk (1UL /* & lt; & lt; ITM_IRR_ATREADYM_Pos*/) /*! & lt; ITM IRR: ATREADYM Mask */
/* ITM Integration Mode Control Register Definitions */
#define ITM_IMCR_INTEGRATION_Pos 0U /*! & lt; ITM IMCR: INTEGRATION Position */
#define ITM_IMCR_INTEGRATION_Msk (1UL /* & lt; & lt; ITM_IMCR_INTEGRATION_Pos*/) /*! & lt; ITM IMCR: INTEGRATION Mask */
/* ITM Lock Status Register Definitions */
#define ITM_LSR_ByteAcc_Pos 2U /*! & lt; ITM LSR: ByteAcc Position */
#define ITM_LSR_ByteAcc_Msk (1UL & lt; & lt; ITM_LSR_ByteAcc_Pos) /*! & lt; ITM LSR: ByteAcc Mask */
#define ITM_LSR_Access_Pos 1U /*! & lt; ITM LSR: Access Position */
#define ITM_LSR_Access_Msk (1UL & lt; & lt; ITM_LSR_Access_Pos) /*! & lt; ITM LSR: Access Mask */
#define ITM_LSR_Present_Pos 0U /*! & lt; ITM LSR: Present Position */
#define ITM_LSR_Present_Msk (1UL /* & lt; & lt; ITM_LSR_Present_Pos*/) /*! & lt; ITM LSR: Present Mask */
/*@}*/ /* end of group CMSIS_ITM */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
\brief Type definitions for the Data Watchpoint and Trace (DWT)
@{
*/
/**
\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
*/
typedef struct
{
__IOM uint32_t CTRL; /*! & lt; Offset: 0x000 (R/W) Control Register */
__IOM uint32_t CYCCNT; /*! & lt; Offset: 0x004 (R/W) Cycle Count Register */
__IOM uint32_t CPICNT; /*! & lt; Offset: 0x008 (R/W) CPI Count Register */
__IOM uint32_t EXCCNT; /*! & lt; Offset: 0x00C (R/W) Exception Overhead Count Register */
__IOM uint32_t SLEEPCNT; /*! & lt; Offset: 0x010 (R/W) Sleep Count Register */
__IOM uint32_t LSUCNT; /*! & lt; Offset: 0x014 (R/W) LSU Count Register */
__IOM uint32_t FOLDCNT; /*! & lt; Offset: 0x018 (R/W) Folded-instruction Count Register */
__IM uint32_t PCSR; /*! & lt; Offset: 0x01C (R/ ) Program Counter Sample Register */
__IOM uint32_t COMP0; /*! & lt; Offset: 0x020 (R/W) Comparator Register 0 */
__IOM uint32_t MASK0; /*! & lt; Offset: 0x024 (R/W) Mask Register 0 */
__IOM uint32_t FUNCTION0; /*! & lt; Offset: 0x028 (R/W) Function Register 0 */
uint32_t RESERVED0[1U];
__IOM uint32_t COMP1; /*! & lt; Offset: 0x030 (R/W) Comparator Register 1 */
__IOM uint32_t MASK1; /*! & lt; Offset: 0x034 (R/W) Mask Register 1 */
__IOM uint32_t FUNCTION1; /*! & lt; Offset: 0x038 (R/W) Function Register 1 */
uint32_t RESERVED1[1U];
__IOM uint32_t COMP2; /*! & lt; Offset: 0x040 (R/W) Comparator Register 2 */
__IOM uint32_t MASK2; /*! & lt; Offset: 0x044 (R/W) Mask Register 2 */
__IOM uint32_t FUNCTION2; /*! & lt; Offset: 0x048 (R/W) Function Register 2 */
uint32_t RESERVED2[1U];
__IOM uint32_t COMP3; /*! & lt; Offset: 0x050 (R/W) Comparator Register 3 */
__IOM uint32_t MASK3; /*! & lt; Offset: 0x054 (R/W) Mask Register 3 */
__IOM uint32_t FUNCTION3; /*! & lt; Offset: 0x058 (R/W) Function Register 3 */
} DWT_Type;
/* DWT Control Register Definitions */
#define DWT_CTRL_NUMCOMP_Pos 28U /*! & lt; DWT CTRL: NUMCOMP Position */
#define DWT_CTRL_NUMCOMP_Msk (0xFUL & lt; & lt; DWT_CTRL_NUMCOMP_Pos) /*! & lt; DWT CTRL: NUMCOMP Mask */
#define DWT_CTRL_NOTRCPKT_Pos 27U /*! & lt; DWT CTRL: NOTRCPKT Position */
#define DWT_CTRL_NOTRCPKT_Msk (0x1UL & lt; & lt; DWT_CTRL_NOTRCPKT_Pos) /*! & lt; DWT CTRL: NOTRCPKT Mask */
#define DWT_CTRL_NOEXTTRIG_Pos 26U /*! & lt; DWT CTRL: NOEXTTRIG Position */
#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL & lt; & lt; DWT_CTRL_NOEXTTRIG_Pos) /*! & lt; DWT CTRL: NOEXTTRIG Mask */
#define DWT_CTRL_NOCYCCNT_Pos 25U /*! & lt; DWT CTRL: NOCYCCNT Position */
#define DWT_CTRL_NOCYCCNT_Msk (0x1UL & lt; & lt; DWT_CTRL_NOCYCCNT_Pos) /*! & lt; DWT CTRL: NOCYCCNT Mask */
#define DWT_CTRL_NOPRFCNT_Pos 24U /*! & lt; DWT CTRL: NOPRFCNT Position */
#define DWT_CTRL_NOPRFCNT_Msk (0x1UL & lt; & lt; DWT_CTRL_NOPRFCNT_Pos) /*! & lt; DWT CTRL: NOPRFCNT Mask */
#define DWT_CTRL_CYCEVTENA_Pos 22U /*! & lt; DWT CTRL: CYCEVTENA Position */
#define DWT_CTRL_CYCEVTENA_Msk (0x1UL & lt; & lt; DWT_CTRL_CYCEVTENA_Pos) /*! & lt; DWT CTRL: CYCEVTENA Mask */
#define DWT_CTRL_FOLDEVTENA_Pos 21U /*! & lt; DWT CTRL: FOLDEVTENA Position */
#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL & lt; & lt; DWT_CTRL_FOLDEVTENA_Pos) /*! & lt; DWT CTRL: FOLDEVTENA Mask */
#define DWT_CTRL_LSUEVTENA_Pos 20U /*! & lt; DWT CTRL: LSUEVTENA Position */
#define DWT_CTRL_LSUEVTENA_Msk (0x1UL & lt; & lt; DWT_CTRL_LSUEVTENA_Pos) /*! & lt; DWT CTRL: LSUEVTENA Mask */
#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*! & lt; DWT CTRL: SLEEPEVTENA Position */
#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL & lt; & lt; DWT_CTRL_SLEEPEVTENA_Pos) /*! & lt; DWT CTRL: SLEEPEVTENA Mask */
#define DWT_CTRL_EXCEVTENA_Pos 18U /*! & lt; DWT CTRL: EXCEVTENA Position */
#define DWT_CTRL_EXCEVTENA_Msk (0x1UL & lt; & lt; DWT_CTRL_EXCEVTENA_Pos) /*! & lt; DWT CTRL: EXCEVTENA Mask */
#define DWT_CTRL_CPIEVTENA_Pos 17U /*! & lt; DWT CTRL: CPIEVTENA Position */
#define DWT_CTRL_CPIEVTENA_Msk (0x1UL & lt; & lt; DWT_CTRL_CPIEVTENA_Pos) /*! & lt; DWT CTRL: CPIEVTENA Mask */
#define DWT_CTRL_EXCTRCENA_Pos 16U /*! & lt; DWT CTRL: EXCTRCENA Position */
#define DWT_CTRL_EXCTRCENA_Msk (0x1UL & lt; & lt; DWT_CTRL_EXCTRCENA_Pos) /*! & lt; DWT CTRL: EXCTRCENA Mask */
#define DWT_CTRL_PCSAMPLENA_Pos 12U /*! & lt; DWT CTRL: PCSAMPLENA Position */
#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL & lt; & lt; DWT_CTRL_PCSAMPLENA_Pos) /*! & lt; DWT CTRL: PCSAMPLENA Mask */
#define DWT_CTRL_SYNCTAP_Pos 10U /*! & lt; DWT CTRL: SYNCTAP Position */
#define DWT_CTRL_SYNCTAP_Msk (0x3UL & lt; & lt; DWT_CTRL_SYNCTAP_Pos) /*! & lt; DWT CTRL: SYNCTAP Mask */
#define DWT_CTRL_CYCTAP_Pos 9U /*! & lt; DWT CTRL: CYCTAP Position */
#define DWT_CTRL_CYCTAP_Msk (0x1UL & lt; & lt; DWT_CTRL_CYCTAP_Pos) /*! & lt; DWT CTRL: CYCTAP Mask */
#define DWT_CTRL_POSTINIT_Pos 5U /*! & lt; DWT CTRL: POSTINIT Position */
#define DWT_CTRL_POSTINIT_Msk (0xFUL & lt; & lt; DWT_CTRL_POSTINIT_Pos) /*! & lt; DWT CTRL: POSTINIT Mask */
#define DWT_CTRL_POSTPRESET_Pos 1U /*! & lt; DWT CTRL: POSTPRESET Position */
#define DWT_CTRL_POSTPRESET_Msk (0xFUL & lt; & lt; DWT_CTRL_POSTPRESET_Pos) /*! & lt; DWT CTRL: POSTPRESET Mask */
#define DWT_CTRL_CYCCNTENA_Pos 0U /*! & lt; DWT CTRL: CYCCNTENA Position */
#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /* & lt; & lt; DWT_CTRL_CYCCNTENA_Pos*/) /*! & lt; DWT CTRL: CYCCNTENA Mask */
/* DWT CPI Count Register Definitions */
#define DWT_CPICNT_CPICNT_Pos 0U /*! & lt; DWT CPICNT: CPICNT Position */
#define DWT_CPICNT_CPICNT_Msk (0xFFUL /* & lt; & lt; DWT_CPICNT_CPICNT_Pos*/) /*! & lt; DWT CPICNT: CPICNT Mask */
/* DWT Exception Overhead Count Register Definitions */
#define DWT_EXCCNT_EXCCNT_Pos 0U /*! & lt; DWT EXCCNT: EXCCNT Position */
#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /* & lt; & lt; DWT_EXCCNT_EXCCNT_Pos*/) /*! & lt; DWT EXCCNT: EXCCNT Mask */
/* DWT Sleep Count Register Definitions */
#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*! & lt; DWT SLEEPCNT: SLEEPCNT Position */
#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /* & lt; & lt; DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*! & lt; DWT SLEEPCNT: SLEEPCNT Mask */
/* DWT LSU Count Register Definitions */
#define DWT_LSUCNT_LSUCNT_Pos 0U /*! & lt; DWT LSUCNT: LSUCNT Position */
#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /* & lt; & lt; DWT_LSUCNT_LSUCNT_Pos*/) /*! & lt; DWT LSUCNT: LSUCNT Mask */
/* DWT Folded-instruction Count Register Definitions */
#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*! & lt; DWT FOLDCNT: FOLDCNT Position */
#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /* & lt; & lt; DWT_FOLDCNT_FOLDCNT_Pos*/) /*! & lt; DWT FOLDCNT: FOLDCNT Mask */
/* DWT Comparator Mask Register Definitions */
#define DWT_MASK_MASK_Pos 0U /*! & lt; DWT MASK: MASK Position */
#define DWT_MASK_MASK_Msk (0x1FUL /* & lt; & lt; DWT_MASK_MASK_Pos*/) /*! & lt; DWT MASK: MASK Mask */
/* DWT Comparator Function Register Definitions */
#define DWT_FUNCTION_MATCHED_Pos 24U /*! & lt; DWT FUNCTION: MATCHED Position */
#define DWT_FUNCTION_MATCHED_Msk (0x1UL & lt; & lt; DWT_FUNCTION_MATCHED_Pos) /*! & lt; DWT FUNCTION: MATCHED Mask */
#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*! & lt; DWT FUNCTION: DATAVADDR1 Position */
#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL & lt; & lt; DWT_FUNCTION_DATAVADDR1_Pos) /*! & lt; DWT FUNCTION: DATAVADDR1 Mask */
#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*! & lt; DWT FUNCTION: DATAVADDR0 Position */
#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL & lt; & lt; DWT_FUNCTION_DATAVADDR0_Pos) /*! & lt; DWT FUNCTION: DATAVADDR0 Mask */
#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*! & lt; DWT FUNCTION: DATAVSIZE Position */
#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL & lt; & lt; DWT_FUNCTION_DATAVSIZE_Pos) /*! & lt; DWT FUNCTION: DATAVSIZE Mask */
#define DWT_FUNCTION_LNK1ENA_Pos 9U /*! & lt; DWT FUNCTION: LNK1ENA Position */
#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL & lt; & lt; DWT_FUNCTION_LNK1ENA_Pos) /*! & lt; DWT FUNCTION: LNK1ENA Mask */
#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*! & lt; DWT FUNCTION: DATAVMATCH Position */
#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL & lt; & lt; DWT_FUNCTION_DATAVMATCH_Pos) /*! & lt; DWT FUNCTION: DATAVMATCH Mask */
#define DWT_FUNCTION_CYCMATCH_Pos 7U /*! & lt; DWT FUNCTION: CYCMATCH Position */
#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL & lt; & lt; DWT_FUNCTION_CYCMATCH_Pos) /*! & lt; DWT FUNCTION: CYCMATCH Mask */
#define DWT_FUNCTION_EMITRANGE_Pos 5U /*! & lt; DWT FUNCTION: EMITRANGE Position */
#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL & lt; & lt; DWT_FUNCTION_EMITRANGE_Pos) /*! & lt; DWT FUNCTION: EMITRANGE Mask */
#define DWT_FUNCTION_FUNCTION_Pos 0U /*! & lt; DWT FUNCTION: FUNCTION Position */
#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /* & lt; & lt; DWT_FUNCTION_FUNCTION_Pos*/) /*! & lt; DWT FUNCTION: FUNCTION Mask */
/*@}*/ /* end of group CMSIS_DWT */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_TPI Trace Port Interface (TPI)
\brief Type definitions for the Trace Port Interface (TPI)
@{
*/
/**
\brief Structure type to access the Trace Port Interface Register (TPI).
*/
typedef struct
{
__IOM uint32_t SSPSR; /*! & lt; Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
__IOM uint32_t CSPSR; /*! & lt; Offset: 0x004 (R/W) Current Parallel Port Size Register */
uint32_t RESERVED0[2U];
__IOM uint32_t ACPR; /*! & lt; Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
uint32_t RESERVED1[55U];
__IOM uint32_t SPPR; /*! & lt; Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
uint32_t RESERVED2[131U];
__IM uint32_t FFSR; /*! & lt; Offset: 0x300 (R/ ) Formatter and Flush Status Register */
__IOM uint32_t FFCR; /*! & lt; Offset: 0x304 (R/W) Formatter and Flush Control Register */
__IM uint32_t FSCR; /*! & lt; Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
uint32_t RESERVED3[759U];
__IM uint32_t TRIGGER; /*! & lt; Offset: 0xEE8 (R/ ) TRIGGER */
__IM uint32_t FIFO0; /*! & lt; Offset: 0xEEC (R/ ) Integration ETM Data */
__IM uint32_t ITATBCTR2; /*! & lt; Offset: 0xEF0 (R/ ) ITATBCTR2 */
uint32_t RESERVED4[1U];
__IM uint32_t ITATBCTR0; /*! & lt; Offset: 0xEF8 (R/ ) ITATBCTR0 */
__IM uint32_t FIFO1; /*! & lt; Offset: 0xEFC (R/ ) Integration ITM Data */
__IOM uint32_t ITCTRL; /*! & lt; Offset: 0xF00 (R/W) Integration Mode Control */
uint32_t RESERVED5[39U];
__IOM uint32_t CLAIMSET; /*! & lt; Offset: 0xFA0 (R/W) Claim tag set */
__IOM uint32_t CLAIMCLR; /*! & lt; Offset: 0xFA4 (R/W) Claim tag clear */
uint32_t RESERVED7[8U];
__IM uint32_t DEVID; /*! & lt; Offset: 0xFC8 (R/ ) TPIU_DEVID */
__IM uint32_t DEVTYPE; /*! & lt; Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
} TPI_Type;
/* TPI Asynchronous Clock Prescaler Register Definitions */
#define TPI_ACPR_PRESCALER_Pos 0U /*! & lt; TPI ACPR: PRESCALER Position */
#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /* & lt; & lt; TPI_ACPR_PRESCALER_Pos*/) /*! & lt; TPI ACPR: PRESCALER Mask */
/* TPI Selected Pin Protocol Register Definitions */
#define TPI_SPPR_TXMODE_Pos 0U /*! & lt; TPI SPPR: TXMODE Position */
#define TPI_SPPR_TXMODE_Msk (0x3UL /* & lt; & lt; TPI_SPPR_TXMODE_Pos*/) /*! & lt; TPI SPPR: TXMODE Mask */
/* TPI Formatter and Flush Status Register Definitions */
#define TPI_FFSR_FtNonStop_Pos 3U /*! & lt; TPI FFSR: FtNonStop Position */
#define TPI_FFSR_FtNonStop_Msk (0x1UL & lt; & lt; TPI_FFSR_FtNonStop_Pos) /*! & lt; TPI FFSR: FtNonStop Mask */
#define TPI_FFSR_TCPresent_Pos 2U /*! & lt; TPI FFSR: TCPresent Position */
#define TPI_FFSR_TCPresent_Msk (0x1UL & lt; & lt; TPI_FFSR_TCPresent_Pos) /*! & lt; TPI FFSR: TCPresent Mask */
#define TPI_FFSR_FtStopped_Pos 1U /*! & lt; TPI FFSR: FtStopped Position */
#define TPI_FFSR_FtStopped_Msk (0x1UL & lt; & lt; TPI_FFSR_FtStopped_Pos) /*! & lt; TPI FFSR: FtStopped Mask */
#define TPI_FFSR_FlInProg_Pos 0U /*! & lt; TPI FFSR: FlInProg Position */
#define TPI_FFSR_FlInProg_Msk (0x1UL /* & lt; & lt; TPI_FFSR_FlInProg_Pos*/) /*! & lt; TPI FFSR: FlInProg Mask */
/* TPI Formatter and Flush Control Register Definitions */
#define TPI_FFCR_TrigIn_Pos 8U /*! & lt; TPI FFCR: TrigIn Position */
#define TPI_FFCR_TrigIn_Msk (0x1UL & lt; & lt; TPI_FFCR_TrigIn_Pos) /*! & lt; TPI FFCR: TrigIn Mask */
#define TPI_FFCR_EnFCont_Pos 1U /*! & lt; TPI FFCR: EnFCont Position */
#define TPI_FFCR_EnFCont_Msk (0x1UL & lt; & lt; TPI_FFCR_EnFCont_Pos) /*! & lt; TPI FFCR: EnFCont Mask */
/* TPI TRIGGER Register Definitions */
#define TPI_TRIGGER_TRIGGER_Pos 0U /*! & lt; TPI TRIGGER: TRIGGER Position */
#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /* & lt; & lt; TPI_TRIGGER_TRIGGER_Pos*/) /*! & lt; TPI TRIGGER: TRIGGER Mask */
/* TPI Integration ETM Data Register Definitions (FIFO0) */
#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*! & lt; TPI FIFO0: ITM_ATVALID Position */
#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL & lt; & lt; TPI_FIFO0_ITM_ATVALID_Pos) /*! & lt; TPI FIFO0: ITM_ATVALID Mask */
#define TPI_FIFO0_ITM_bytecount_Pos 27U /*! & lt; TPI FIFO0: ITM_bytecount Position */
#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL & lt; & lt; TPI_FIFO0_ITM_bytecount_Pos) /*! & lt; TPI FIFO0: ITM_bytecount Mask */
#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*! & lt; TPI FIFO0: ETM_ATVALID Position */
#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL & lt; & lt; TPI_FIFO0_ETM_ATVALID_Pos) /*! & lt; TPI FIFO0: ETM_ATVALID Mask */
#define TPI_FIFO0_ETM_bytecount_Pos 24U /*! & lt; TPI FIFO0: ETM_bytecount Position */
#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL & lt; & lt; TPI_FIFO0_ETM_bytecount_Pos) /*! & lt; TPI FIFO0: ETM_bytecount Mask */
#define TPI_FIFO0_ETM2_Pos 16U /*! & lt; TPI FIFO0: ETM2 Position */
#define TPI_FIFO0_ETM2_Msk (0xFFUL & lt; & lt; TPI_FIFO0_ETM2_Pos) /*! & lt; TPI FIFO0: ETM2 Mask */
#define TPI_FIFO0_ETM1_Pos 8U /*! & lt; TPI FIFO0: ETM1 Position */
#define TPI_FIFO0_ETM1_Msk (0xFFUL & lt; & lt; TPI_FIFO0_ETM1_Pos) /*! & lt; TPI FIFO0: ETM1 Mask */
#define TPI_FIFO0_ETM0_Pos 0U /*! & lt; TPI FIFO0: ETM0 Position */
#define TPI_FIFO0_ETM0_Msk (0xFFUL /* & lt; & lt; TPI_FIFO0_ETM0_Pos*/) /*! & lt; TPI FIFO0: ETM0 Mask */
/* TPI ITATBCTR2 Register Definitions */
#define TPI_ITATBCTR2_ATREADY_Pos 0U /*! & lt; TPI ITATBCTR2: ATREADY Position */
#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /* & lt; & lt; TPI_ITATBCTR2_ATREADY_Pos*/) /*! & lt; TPI ITATBCTR2: ATREADY Mask */
/* TPI Integration ITM Data Register Definitions (FIFO1) */
#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*! & lt; TPI FIFO1: ITM_ATVALID Position */
#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL & lt; & lt; TPI_FIFO1_ITM_ATVALID_Pos) /*! & lt; TPI FIFO1: ITM_ATVALID Mask */
#define TPI_FIFO1_ITM_bytecount_Pos 27U /*! & lt; TPI FIFO1: ITM_bytecount Position */
#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL & lt; & lt; TPI_FIFO1_ITM_bytecount_Pos) /*! & lt; TPI FIFO1: ITM_bytecount Mask */
#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*! & lt; TPI FIFO1: ETM_ATVALID Position */
#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL & lt; & lt; TPI_FIFO1_ETM_ATVALID_Pos) /*! & lt; TPI FIFO1: ETM_ATVALID Mask */
#define TPI_FIFO1_ETM_bytecount_Pos 24U /*! & lt; TPI FIFO1: ETM_bytecount Position */
#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL & lt; & lt; TPI_FIFO1_ETM_bytecount_Pos) /*! & lt; TPI FIFO1: ETM_bytecount Mask */
#define TPI_FIFO1_ITM2_Pos 16U /*! & lt; TPI FIFO1: ITM2 Position */
#define TPI_FIFO1_ITM2_Msk (0xFFUL & lt; & lt; TPI_FIFO1_ITM2_Pos) /*! & lt; TPI FIFO1: ITM2 Mask */
#define TPI_FIFO1_ITM1_Pos 8U /*! & lt; TPI FIFO1: ITM1 Position */
#define TPI_FIFO1_ITM1_Msk (0xFFUL & lt; & lt; TPI_FIFO1_ITM1_Pos) /*! & lt; TPI FIFO1: ITM1 Mask */
#define TPI_FIFO1_ITM0_Pos 0U /*! & lt; TPI FIFO1: ITM0 Position */
#define TPI_FIFO1_ITM0_Msk (0xFFUL /* & lt; & lt; TPI_FIFO1_ITM0_Pos*/) /*! & lt; TPI FIFO1: ITM0 Mask */
/* TPI ITATBCTR0 Register Definitions */
#define TPI_ITATBCTR0_ATREADY_Pos 0U /*! & lt; TPI ITATBCTR0: ATREADY Position */
#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /* & lt; & lt; TPI_ITATBCTR0_ATREADY_Pos*/) /*! & lt; TPI ITATBCTR0: ATREADY Mask */
/* TPI Integration Mode Control Register Definitions */
#define TPI_ITCTRL_Mode_Pos 0U /*! & lt; TPI ITCTRL: Mode Position */
#define TPI_ITCTRL_Mode_Msk (0x1UL /* & lt; & lt; TPI_ITCTRL_Mode_Pos*/) /*! & lt; TPI ITCTRL: Mode Mask */
/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11U /*! & lt; TPI DEVID: NRZVALID Position */
#define TPI_DEVID_NRZVALID_Msk (0x1UL & lt; & lt; TPI_DEVID_NRZVALID_Pos) /*! & lt; TPI DEVID: NRZVALID Mask */
#define TPI_DEVID_MANCVALID_Pos 10U /*! & lt; TPI DEVID: MANCVALID Position */
#define TPI_DEVID_MANCVALID_Msk (0x1UL & lt; & lt; TPI_DEVID_MANCVALID_Pos) /*! & lt; TPI DEVID: MANCVALID Mask */
#define TPI_DEVID_PTINVALID_Pos 9U /*! & lt; TPI DEVID: PTINVALID Position */
#define TPI_DEVID_PTINVALID_Msk (0x1UL & lt; & lt; TPI_DEVID_PTINVALID_Pos) /*! & lt; TPI DEVID: PTINVALID Mask */
#define TPI_DEVID_MinBufSz_Pos 6U /*! & lt; TPI DEVID: MinBufSz Position */
#define TPI_DEVID_MinBufSz_Msk (0x7UL & lt; & lt; TPI_DEVID_MinBufSz_Pos) /*! & lt; TPI DEVID: MinBufSz Mask */
#define TPI_DEVID_AsynClkIn_Pos 5U /*! & lt; TPI DEVID: AsynClkIn Position */
#define TPI_DEVID_AsynClkIn_Msk (0x1UL & lt; & lt; TPI_DEVID_AsynClkIn_Pos) /*! & lt; TPI DEVID: AsynClkIn Mask */
#define TPI_DEVID_NrTraceInput_Pos 0U /*! & lt; TPI DEVID: NrTraceInput Position */
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /* & lt; & lt; TPI_DEVID_NrTraceInput_Pos*/) /*! & lt; TPI DEVID: NrTraceInput Mask */
/* TPI DEVTYPE Register Definitions */
#define TPI_DEVTYPE_MajorType_Pos 4U /*! & lt; TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL & lt; & lt; TPI_DEVTYPE_MajorType_Pos) /*! & lt; TPI DEVTYPE: MajorType Mask */
#define TPI_DEVTYPE_SubType_Pos 0U /*! & lt; TPI DEVTYPE: SubType Position */
#define TPI_DEVTYPE_SubType_Msk (0xFUL /* & lt; & lt; TPI_DEVTYPE_SubType_Pos*/) /*! & lt; TPI DEVTYPE: SubType Mask */
/*@}*/ /* end of group CMSIS_TPI */
#if (__MPU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__IM uint32_t TYPE; /*! & lt; Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*! & lt; Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*! & lt; Offset: 0x008 (R/W) MPU Region RNRber Register */
__IOM uint32_t RBAR; /*! & lt; Offset: 0x00C (R/W) MPU Region Base Address Register */
__IOM uint32_t RASR; /*! & lt; Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
__IOM uint32_t RBAR_A1; /*! & lt; Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
__IOM uint32_t RASR_A1; /*! & lt; Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
__IOM uint32_t RBAR_A2; /*! & lt; Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
__IOM uint32_t RASR_A2; /*! & lt; Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
__IOM uint32_t RBAR_A3; /*! & lt; Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
__IOM uint32_t RASR_A3; /*! & lt; Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
} MPU_Type;
/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U /*! & lt; MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL & lt; & lt; MPU_TYPE_IREGION_Pos) /*! & lt; MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8U /*! & lt; MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL & lt; & lt; MPU_TYPE_DREGION_Pos) /*! & lt; MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0U /*! & lt; MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /* & lt; & lt; MPU_TYPE_SEPARATE_Pos*/) /*! & lt; MPU TYPE: SEPARATE Mask */
/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*! & lt; MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL & lt; & lt; MPU_CTRL_PRIVDEFENA_Pos) /*! & lt; MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1U /*! & lt; MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL & lt; & lt; MPU_CTRL_HFNMIENA_Pos) /*! & lt; MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0U /*! & lt; MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /* & lt; & lt; MPU_CTRL_ENABLE_Pos*/) /*! & lt; MPU CTRL: ENABLE Mask */
/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U /*! & lt; MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /* & lt; & lt; MPU_RNR_REGION_Pos*/) /*! & lt; MPU RNR: REGION Mask */
/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_ADDR_Pos 5U /*! & lt; MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL & lt; & lt; MPU_RBAR_ADDR_Pos) /*! & lt; MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4U /*! & lt; MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL & lt; & lt; MPU_RBAR_VALID_Pos) /*! & lt; MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0U /*! & lt; MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL /* & lt; & lt; MPU_RBAR_REGION_Pos*/) /*! & lt; MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register Definitions */
#define MPU_RASR_ATTRS_Pos 16U /*! & lt; MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL & lt; & lt; MPU_RASR_ATTRS_Pos) /*! & lt; MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_XN_Pos 28U /*! & lt; MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL & lt; & lt; MPU_RASR_XN_Pos) /*! & lt; MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_AP_Pos 24U /*! & lt; MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL & lt; & lt; MPU_RASR_AP_Pos) /*! & lt; MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_TEX_Pos 19U /*! & lt; MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL & lt; & lt; MPU_RASR_TEX_Pos) /*! & lt; MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_S_Pos 18U /*! & lt; MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL & lt; & lt; MPU_RASR_S_Pos) /*! & lt; MPU RASR: ATTRS.S Mask */
#define MPU_RASR_C_Pos 17U /*! & lt; MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL & lt; & lt; MPU_RASR_C_Pos) /*! & lt; MPU RASR: ATTRS.C Mask */
#define MPU_RASR_B_Pos 16U /*! & lt; MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL & lt; & lt; MPU_RASR_B_Pos) /*! & lt; MPU RASR: ATTRS.B Mask */
#define MPU_RASR_SRD_Pos 8U /*! & lt; MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL & lt; & lt; MPU_RASR_SRD_Pos) /*! & lt; MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1U /*! & lt; MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL & lt; & lt; MPU_RASR_SIZE_Pos) /*! & lt; MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0U /*! & lt; MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL /* & lt; & lt; MPU_RASR_ENABLE_Pos*/) /*! & lt; MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Type definitions for the Core Debug Registers
@{
*/
/**
\brief Structure type to access the Core Debug Register (CoreDebug).
*/
typedef struct
{
__IOM uint32_t DHCSR; /*! & lt; Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /*! & lt; Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /*! & lt; Offset: 0x008 (R/W) Debug Core Register Data Register */
__IOM uint32_t DEMCR; /*! & lt; Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
} CoreDebug_Type;
/* Debug Halting Control and Status Register Definitions */
#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*! & lt; CoreDebug DHCSR: DBGKEY Position */
#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL & lt; & lt; CoreDebug_DHCSR_DBGKEY_Pos) /*! & lt; CoreDebug DHCSR: DBGKEY Mask */
#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*! & lt; CoreDebug DHCSR: S_RESET_ST Position */
#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL & lt; & lt; CoreDebug_DHCSR_S_RESET_ST_Pos) /*! & lt; CoreDebug DHCSR: S_RESET_ST Mask */
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*! & lt; CoreDebug DHCSR: S_RETIRE_ST Position */
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL & lt; & lt; CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*! & lt; CoreDebug DHCSR: S_RETIRE_ST Mask */
#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*! & lt; CoreDebug DHCSR: S_LOCKUP Position */
#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL & lt; & lt; CoreDebug_DHCSR_S_LOCKUP_Pos) /*! & lt; CoreDebug DHCSR: S_LOCKUP Mask */
#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*! & lt; CoreDebug DHCSR: S_SLEEP Position */
#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL & lt; & lt; CoreDebug_DHCSR_S_SLEEP_Pos) /*! & lt; CoreDebug DHCSR: S_SLEEP Mask */
#define CoreDebug_DHCSR_S_HALT_Pos 17U /*! & lt; CoreDebug DHCSR: S_HALT Position */
#define CoreDebug_DHCSR_S_HALT_Msk (1UL & lt; & lt; CoreDebug_DHCSR_S_HALT_Pos) /*! & lt; CoreDebug DHCSR: S_HALT Mask */
#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*! & lt; CoreDebug DHCSR: S_REGRDY Position */
#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL & lt; & lt; CoreDebug_DHCSR_S_REGRDY_Pos) /*! & lt; CoreDebug DHCSR: S_REGRDY Mask */
#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*! & lt; CoreDebug DHCSR: C_SNAPSTALL Position */
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL & lt; & lt; CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*! & lt; CoreDebug DHCSR: C_SNAPSTALL Mask */
#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*! & lt; CoreDebug DHCSR: C_MASKINTS Position */
#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL & lt; & lt; CoreDebug_DHCSR_C_MASKINTS_Pos) /*! & lt; CoreDebug DHCSR: C_MASKINTS Mask */
#define CoreDebug_DHCSR_C_STEP_Pos 2U /*! & lt; CoreDebug DHCSR: C_STEP Position */
#define CoreDebug_DHCSR_C_STEP_Msk (1UL & lt; & lt; CoreDebug_DHCSR_C_STEP_Pos) /*! & lt; CoreDebug DHCSR: C_STEP Mask */
#define CoreDebug_DHCSR_C_HALT_Pos 1U /*! & lt; CoreDebug DHCSR: C_HALT Position */
#define CoreDebug_DHCSR_C_HALT_Msk (1UL & lt; & lt; CoreDebug_DHCSR_C_HALT_Pos) /*! & lt; CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*! & lt; CoreDebug DHCSR: C_DEBUGEN Position */
#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /* & lt; & lt; CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*! & lt; CoreDebug DHCSR: C_DEBUGEN Mask */
/* Debug Core Register Selector Register Definitions */
#define CoreDebug_DCRSR_REGWnR_Pos 16U /*! & lt; CoreDebug DCRSR: REGWnR Position */
#define CoreDebug_DCRSR_REGWnR_Msk (1UL & lt; & lt; CoreDebug_DCRSR_REGWnR_Pos) /*! & lt; CoreDebug DCRSR: REGWnR Mask */
#define CoreDebug_DCRSR_REGSEL_Pos 0U /*! & lt; CoreDebug DCRSR: REGSEL Position */
#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /* & lt; & lt; CoreDebug_DCRSR_REGSEL_Pos*/) /*! & lt; CoreDebug DCRSR: REGSEL Mask */
/* Debug Exception and Monitor Control Register Definitions */
#define CoreDebug_DEMCR_TRCENA_Pos 24U /*! & lt; CoreDebug DEMCR: TRCENA Position */
#define CoreDebug_DEMCR_TRCENA_Msk (1UL & lt; & lt; CoreDebug_DEMCR_TRCENA_Pos) /*! & lt; CoreDebug DEMCR: TRCENA Mask */
#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*! & lt; CoreDebug DEMCR: MON_REQ Position */
#define CoreDebug_DEMCR_MON_REQ_Msk (1UL & lt; & lt; CoreDebug_DEMCR_MON_REQ_Pos) /*! & lt; CoreDebug DEMCR: MON_REQ Mask */
#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*! & lt; CoreDebug DEMCR: MON_STEP Position */
#define CoreDebug_DEMCR_MON_STEP_Msk (1UL & lt; & lt; CoreDebug_DEMCR_MON_STEP_Pos) /*! & lt; CoreDebug DEMCR: MON_STEP Mask */
#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*! & lt; CoreDebug DEMCR: MON_PEND Position */
#define CoreDebug_DEMCR_MON_PEND_Msk (1UL & lt; & lt; CoreDebug_DEMCR_MON_PEND_Pos) /*! & lt; CoreDebug DEMCR: MON_PEND Mask */
#define CoreDebug_DEMCR_MON_EN_Pos 16U /*! & lt; CoreDebug DEMCR: MON_EN Position */
#define CoreDebug_DEMCR_MON_EN_Msk (1UL & lt; & lt; CoreDebug_DEMCR_MON_EN_Pos) /*! & lt; CoreDebug DEMCR: MON_EN Mask */
#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*! & lt; CoreDebug DEMCR: VC_HARDERR Position */
#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL & lt; & lt; CoreDebug_DEMCR_VC_HARDERR_Pos) /*! & lt; CoreDebug DEMCR: VC_HARDERR Mask */
#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*! & lt; CoreDebug DEMCR: VC_INTERR Position */
#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL & lt; & lt; CoreDebug_DEMCR_VC_INTERR_Pos) /*! & lt; CoreDebug DEMCR: VC_INTERR Mask */
#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*! & lt; CoreDebug DEMCR: VC_BUSERR Position */
#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL & lt; & lt; CoreDebug_DEMCR_VC_BUSERR_Pos) /*! & lt; CoreDebug DEMCR: VC_BUSERR Mask */
#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*! & lt; CoreDebug DEMCR: VC_STATERR Position */
#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL & lt; & lt; CoreDebug_DEMCR_VC_STATERR_Pos) /*! & lt; CoreDebug DEMCR: VC_STATERR Mask */
#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*! & lt; CoreDebug DEMCR: VC_CHKERR Position */
#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL & lt; & lt; CoreDebug_DEMCR_VC_CHKERR_Pos) /*! & lt; CoreDebug DEMCR: VC_CHKERR Mask */
#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*! & lt; CoreDebug DEMCR: VC_NOCPERR Position */
#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL & lt; & lt; CoreDebug_DEMCR_VC_NOCPERR_Pos) /*! & lt; CoreDebug DEMCR: VC_NOCPERR Mask */
#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*! & lt; CoreDebug DEMCR: VC_MMERR Position */
#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL & lt; & lt; CoreDebug_DEMCR_VC_MMERR_Pos) /*! & lt; CoreDebug DEMCR: VC_MMERR Mask */
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*! & lt; CoreDebug DEMCR: VC_CORERESET Position */
#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /* & lt; & lt; CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*! & lt; CoreDebug DEMCR: VC_CORERESET Mask */
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value & lt; & lt; field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) & gt; & gt; field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M3 Hardware */
#define SCS_BASE (0xE000E000UL) /*! & lt; System Control Space Base Address */
#define ITM_BASE (0xE0000000UL) /*! & lt; ITM Base Address */
#define DWT_BASE (0xE0001000UL) /*! & lt; DWT Base Address */
#define TPI_BASE (0xE0040000UL) /*! & lt; TPI Base Address */
#define CoreDebug_BASE (0xE000EDF0UL) /*! & lt; Core Debug Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*! & lt; SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*! & lt; NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*! & lt; System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*! & lt; System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*! & lt; SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*! & lt; SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*! & lt; NVIC configuration struct */
#define ITM ((ITM_Type *) ITM_BASE ) /*! & lt; ITM configuration struct */
#define DWT ((DWT_Type *) DWT_BASE ) /*! & lt; DWT configuration struct */
#define TPI ((TPI_Type *) TPI_BASE ) /*! & lt; TPI configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*! & lt; Core Debug configuration struct */
#if (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*! & lt; Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*! & lt; Memory Protection Unit */
#endif
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Debug Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/**
\brief Set Priority Grouping
\details Sets the priority grouping field using the required unlock sequence.
The parameter PriorityGroup is assigned to the field SCB- & gt; AIRCR [10:8] PRIGROUP field.
Only values from 0..7 are used.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB- & gt; AIRCR; /* read old register configuration */
reg_value & = ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
reg_value = (reg_value |
((uint32_t)0x5FAUL & lt; & lt; SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp & lt; & lt; 8U) ); /* Insert write key and priorty group */
SCB- & gt; AIRCR = reg_value;
}
/**
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB- & gt; AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
{
return ((uint32_t)((SCB- & gt; AIRCR & SCB_AIRCR_PRIGROUP_Msk) & gt; & gt; SCB_AIRCR_PRIGROUP_Pos));
}
/**
\brief Enable External Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC- & gt; ISER[(((uint32_t)(int32_t)IRQn) & gt; & gt; 5UL)] = (uint32_t)(1UL & lt; & lt; (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Disable External Interrupt
\details Disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC- & gt; ICER[(((uint32_t)(int32_t)IRQn) & gt; & gt; 5UL)] = (uint32_t)(1UL & lt; & lt; (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Get Pending Interrupt
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t)(((NVIC- & gt; ISPR[(((uint32_t)(int32_t)IRQn) & gt; & gt; 5UL)] & (1UL & lt; & lt; (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC- & gt; ISPR[(((uint32_t)(int32_t)IRQn) & gt; & gt; 5UL)] = (uint32_t)(1UL & lt; & lt; (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC- & gt; ICPR[(((uint32_t)(int32_t)IRQn) & gt; & gt; 5UL)] = (uint32_t)(1UL & lt; & lt; (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Get Active Interrupt
\details Reads the active register in NVIC and returns the active bit.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
*/
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
{
return((uint32_t)(((NVIC- & gt; IABR[(((uint32_t)(int32_t)IRQn) & gt; & gt; 5UL)] & (1UL & lt; & lt; (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Interrupt Priority
\details Sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) & lt; 0)
{
SCB- & gt; SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority & lt; & lt; (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
else
{
NVIC- & gt; IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority & lt; & lt; (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of an interrupt.
The interrupt number can be positive to specify an external (device specific) interrupt,
or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) & lt; 0)
{
return(((uint32_t)SCB- & gt; SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] & gt; & gt; (8U - __NVIC_PRIO_BITS)));
}
else
{
return(((uint32_t)NVIC- & gt; IP[((uint32_t)(int32_t)IRQn)] & gt; & gt; (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) & gt; (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) & lt; (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL & lt; & lt; (PreemptPriorityBits)) - 1UL)) & lt; & lt; SubPriorityBits) |
((SubPriority & (uint32_t)((1UL & lt; & lt; (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) & gt; (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) & lt; (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority & gt; & gt; SubPriorityBits) & (uint32_t)((1UL & lt; & lt; (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL & lt; & lt; (SubPriorityBits )) - 1UL);
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB- & gt; AIRCR = (uint32_t)((0x5FAUL & lt; & lt; SCB_AIRCR_VECTKEY_Pos) |
(SCB- & gt; AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable & lt; b & gt; __Vendor_SysTickConfig & lt; /b & gt; is set to 1, then the
function & lt; b & gt; SysTick_Config & lt; /b & gt; is not included. In this case, the file & lt; b & gt; & lt; i & gt; device & lt; /i & gt; .h & lt; /b & gt;
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) & gt; SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick- & gt; LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL & lt; & lt; __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick- & gt; VAL = 0UL; /* Load the SysTick Counter Value */
SysTick- & gt; CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
/* ##################################### Debug In/Output function ########################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_core_DebugFunctions ITM Functions
\brief Functions that access the ITM debug interface.
@{
*/
extern volatile int32_t ITM_RxBuffer; /*! & lt; External variable to receive characters. */
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*! & lt; Value identifying \ref ITM_RxBuffer is ready for next character. */
/**
\brief ITM Send Character
\details Transmits a character via the ITM channel 0, and
\li Just returns when no debugger is connected that has booked the output.
\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
\param [in] ch Character to transmit.
\returns Character to transmit.
*/
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
{
if (((ITM- & gt; TCR & ITM_TCR_ITMENA_Msk) != 0UL) & & /* ITM enabled */
((ITM- & gt; TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
{
while (ITM- & gt; PORT[0U].u32 == 0UL)
{
__NOP();
}
ITM- & gt; PORT[0U].u8 = (uint8_t)ch;
}
return (ch);
}
/**
\brief ITM Receive Character
\details Inputs a character via the external variable \ref ITM_RxBuffer.
\return Received character.
\return -1 No character pending.
*/
__STATIC_INLINE int32_t ITM_ReceiveChar (void)
{
int32_t ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
{
ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
}
return (ch);
}
/**
\brief ITM Check Character
\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
\return 0 No character available.
\return 1 Character available.
*/
__STATIC_INLINE int32_t ITM_CheckChar (void)
{
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
{
return (0); /* no character available */
}
else
{
return (1); /* character available */
}
}
/*@} end of CMSIS_core_DebugFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM3_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
/**************************************************************************//**
* @file core_cm0plus.h
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS " AS IS "
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) & & (__ARMCC_VERSION & gt; = 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0PLUS_H_GENERIC
#define __CORE_CM0PLUS_H_GENERIC
#include & lt; stdint.h & gt;
#ifdef __cplusplus
extern " C " {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file. & lt; br & gt;
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'. & lt; br & gt;
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined. & lt; br & gt;
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex-M0+
@{
*/
/* CMSIS CM0+ definitions */
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*! & lt; [31:16] CMSIS HAL main version */
#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*! & lt; [15:0] CMSIS HAL sub version */
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN & lt; & lt; 16U) | \
__CM0PLUS_CMSIS_VERSION_SUB ) /*! & lt; CMSIS HAL version number */
#define __CORTEX_M (0x00U) /*! & lt; Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*! & lt; asm keyword for ARM Compiler */
#define __INLINE __inline /*! & lt; inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined(__ARMCC_VERSION) & & (__ARMCC_VERSION & gt; = 6010050)
#define __ASM __asm /*! & lt; asm keyword for ARM Compiler */
#define __INLINE __inline /*! & lt; inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*! & lt; asm keyword for GNU Compiler */
#define __INLINE inline /*! & lt; inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*! & lt; asm keyword for IAR Compiler */
#define __INLINE inline /*! & lt; inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __TMS470__ )
#define __ASM __asm /*! & lt; asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*! & lt; asm keyword for TASKING Compiler */
#define __INLINE inline /*! & lt; inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __CSMC__ )
#define __packed
#define __ASM _asm /*! & lt; asm keyword for COSMIC Compiler */
#define __INLINE inline /*! & lt; inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline
#else
#error Unknown compiler
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error " Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) "
#endif
#elif defined(__ARMCC_VERSION) & & (__ARMCC_VERSION & gt; = 6010050)
#if defined __ARM_PCS_VFP
#error " Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) "
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) & & !defined(__SOFTFP__)
#error " Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) "
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error " Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) "
#endif
#elif defined ( __TMS470__ )
#if defined __TI_VFP_SUPPORT__
#error " Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) "
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error " Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) "
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error " Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) "
#endif
#endif
#include " core_cmInstr.h " /* Core Instruction Access */
#include " core_cmFunc.h " /* Core Function Access */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0PLUS_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0PLUS_H_DEPENDANT
#define __CORE_CM0PLUS_H_DEPENDANT
#ifdef __cplusplus
extern " C " {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0PLUS_REV
#define __CM0PLUS_REV 0x0000U
#warning " __CM0PLUS_REV not defined in device header file; using default! "
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning " __MPU_PRESENT not defined in device header file; using default! "
#endif
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 0U
#warning " __VTOR_PRESENT not defined in device header file; using default! "
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning " __NVIC_PRIO_BITS not defined in device header file; using default! "
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning " __Vendor_SysTickConfig not defined in device header file; using default! "
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
& lt; strong & gt; IO Type Qualifiers & lt; /strong & gt; are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*! & lt; Defines 'read only' permissions */
#else
#define __I volatile const /*! & lt; Defines 'read only' permissions */
#endif
#define __O volatile /*! & lt; Defines 'write only' permissions */
#define __IO volatile /*! & lt; Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex-M0+ */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core MPU Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*! & lt; bit: 0..27 Reserved */
uint32_t V:1; /*! & lt; bit: 28 Overflow condition code flag */
uint32_t C:1; /*! & lt; bit: 29 Carry condition code flag */
uint32_t Z:1; /*! & lt; bit: 30 Zero condition code flag */
uint32_t N:1; /*! & lt; bit: 31 Negative condition code flag */
} b; /*! & lt; Structure used for bit access */
uint32_t w; /*! & lt; Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*! & lt; APSR: N Position */
#define APSR_N_Msk (1UL & lt; & lt; APSR_N_Pos) /*! & lt; APSR: N Mask */
#define APSR_Z_Pos 30U /*! & lt; APSR: Z Position */
#define APSR_Z_Msk (1UL & lt; & lt; APSR_Z_Pos) /*! & lt; APSR: Z Mask */
#define APSR_C_Pos 29U /*! & lt; APSR: C Position */
#define APSR_C_Msk (1UL & lt; & lt; APSR_C_Pos) /*! & lt; APSR: C Mask */
#define APSR_V_Pos 28U /*! & lt; APSR: V Position */
#define APSR_V_Msk (1UL & lt; & lt; APSR_V_Pos) /*! & lt; APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*! & lt; bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*! & lt; bit: 9..31 Reserved */
} b; /*! & lt; Structure used for bit access */
uint32_t w; /*! & lt; Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*! & lt; IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /* & lt; & lt; IPSR_ISR_Pos*/) /*! & lt; IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*! & lt; bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*! & lt; bit: 9..23 Reserved */
uint32_t T:1; /*! & lt; bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*! & lt; bit: 25..27 Reserved */
uint32_t V:1; /*! & lt; bit: 28 Overflow condition code flag */
uint32_t C:1; /*! & lt; bit: 29 Carry condition code flag */
uint32_t Z:1; /*! & lt; bit: 30 Zero condition code flag */
uint32_t N:1; /*! & lt; bit: 31 Negative condition code flag */
} b; /*! & lt; Structure used for bit access */
uint32_t w; /*! & lt; Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*! & lt; xPSR: N Position */
#define xPSR_N_Msk (1UL & lt; & lt; xPSR_N_Pos) /*! & lt; xPSR: N Mask */
#define xPSR_Z_Pos 30U /*! & lt; xPSR: Z Position */
#define xPSR_Z_Msk (1UL & lt; & lt; xPSR_Z_Pos) /*! & lt; xPSR: Z Mask */
#define xPSR_C_Pos 29U /*! & lt; xPSR: C Position */
#define xPSR_C_Msk (1UL & lt; & lt; xPSR_C_Pos) /*! & lt; xPSR: C Mask */
#define xPSR_V_Pos 28U /*! & lt; xPSR: V Position */
#define xPSR_V_Msk (1UL & lt; & lt; xPSR_V_Pos) /*! & lt; xPSR: V Mask */
#define xPSR_T_Pos 24U /*! & lt; xPSR: T Position */
#define xPSR_T_Msk (1UL & lt; & lt; xPSR_T_Pos) /*! & lt; xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*! & lt; xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /* & lt; & lt; xPSR_ISR_Pos*/) /*! & lt; xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*! & lt; bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*! & lt; bit: 1 Stack to be used */
uint32_t _reserved1:30; /*! & lt; bit: 2..31 Reserved */
} b; /*! & lt; Structure used for bit access */
uint32_t w; /*! & lt; Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*! & lt; CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL & lt; & lt; CONTROL_SPSEL_Pos) /*! & lt; CONTROL: SPSEL Mask */
#define CONTROL_nPRIV_Pos 0U /*! & lt; CONTROL: nPRIV Position */
#define CONTROL_nPRIV_Msk (1UL /* & lt; & lt; CONTROL_nPRIV_Pos*/) /*! & lt; CONTROL: nPRIV Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*! & lt; Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*! & lt; Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*! & lt; Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*! & lt; Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*! & lt; Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*! & lt; Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*! & lt; Offset: 0x004 (R/W) Interrupt Control and State Register */
#if (__VTOR_PRESENT == 1U)
__IOM uint32_t VTOR; /*! & lt; Offset: 0x008 (R/W) Vector Table Offset Register */
#else
uint32_t RESERVED0;
#endif
__IOM uint32_t AIRCR; /*! & lt; Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*! & lt; Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*! & lt; Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*! & lt; Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*! & lt; Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*! & lt; SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL & lt; & lt; SCB_CPUID_IMPLEMENTER_Pos) /*! & lt; SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*! & lt; SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL & lt; & lt; SCB_CPUID_VARIANT_Pos) /*! & lt; SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*! & lt; SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL & lt; & lt; SCB_CPUID_ARCHITECTURE_Pos) /*! & lt; SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*! & lt; SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL & lt; & lt; SCB_CPUID_PARTNO_Pos) /*! & lt; SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*! & lt; SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /* & lt; & lt; SCB_CPUID_REVISION_Pos*/) /*! & lt; SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*! & lt; SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL & lt; & lt; SCB_ICSR_NMIPENDSET_Pos) /*! & lt; SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*! & lt; SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL & lt; & lt; SCB_ICSR_PENDSVSET_Pos) /*! & lt; SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*! & lt; SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL & lt; & lt; SCB_ICSR_PENDSVCLR_Pos) /*! & lt; SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*! & lt; SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL & lt; & lt; SCB_ICSR_PENDSTSET_Pos) /*! & lt; SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*! & lt; SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL & lt; & lt; SCB_ICSR_PENDSTCLR_Pos) /*! & lt; SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*! & lt; SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL & lt; & lt; SCB_ICSR_ISRPREEMPT_Pos) /*! & lt; SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*! & lt; SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL & lt; & lt; SCB_ICSR_ISRPENDING_Pos) /*! & lt; SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*! & lt; SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL & lt; & lt; SCB_ICSR_VECTPENDING_Pos) /*! & lt; SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*! & lt; SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /* & lt; & lt; SCB_ICSR_VECTACTIVE_Pos*/) /*! & lt; SCB ICSR: VECTACTIVE Mask */
#if (__VTOR_PRESENT == 1U)
/* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 8U /*! & lt; SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL & lt; & lt; SCB_VTOR_TBLOFF_Pos) /*! & lt; SCB VTOR: TBLOFF Mask */
#endif
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*! & lt; SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL & lt; & lt; SCB_AIRCR_VECTKEY_Pos) /*! & lt; SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*! & lt; SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL & lt; & lt; SCB_AIRCR_VECTKEYSTAT_Pos) /*! & lt; SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*! & lt; SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL & lt; & lt; SCB_AIRCR_ENDIANESS_Pos) /*! & lt; SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*! & lt; SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL & lt; & lt; SCB_AIRCR_SYSRESETREQ_Pos) /*! & lt; SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*! & lt; SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL & lt; & lt; SCB_AIRCR_VECTCLRACTIVE_Pos) /*! & lt; SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*! & lt; SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL & lt; & lt; SCB_SCR_SEVONPEND_Pos) /*! & lt; SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*! & lt; SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL & lt; & lt; SCB_SCR_SLEEPDEEP_Pos) /*! & lt; SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*! & lt; SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL & lt; & lt; SCB_SCR_SLEEPONEXIT_Pos) /*! & lt; SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*! & lt; SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL & lt; & lt; SCB_CCR_STKALIGN_Pos) /*! & lt; SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*! & lt; SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL & lt; & lt; SCB_CCR_UNALIGN_TRP_Pos) /*! & lt; SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*! & lt; SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL & lt; & lt; SCB_SHCSR_SVCALLPENDED_Pos) /*! & lt; SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*! & lt; Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*! & lt; Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*! & lt; Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*! & lt; Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*! & lt; SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL & lt; & lt; SysTick_CTRL_COUNTFLAG_Pos) /*! & lt; SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*! & lt; SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL & lt; & lt; SysTick_CTRL_CLKSOURCE_Pos) /*! & lt; SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*! & lt; SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL & lt; & lt; SysTick_CTRL_TICKINT_Pos) /*! & lt; SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*! & lt; SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /* & lt; & lt; SysTick_CTRL_ENABLE_Pos*/) /*! & lt; SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*! & lt; SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /* & lt; & lt; SysTick_LOAD_RELOAD_Pos*/) /*! & lt; SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*! & lt; SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /* & lt; & lt; SysTick_VAL_CURRENT_Pos*/) /*! & lt; SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*! & lt; SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL & lt; & lt; SysTick_CALIB_NOREF_Pos) /*! & lt; SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*! & lt; SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL & lt; & lt; SysTick_CALIB_SKEW_Pos) /*! & lt; SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*! & lt; SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /* & lt; & lt; SysTick_CALIB_TENMS_Pos*/) /*! & lt; SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
#if (__MPU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__IM uint32_t TYPE; /*! & lt; Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*! & lt; Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*! & lt; Offset: 0x008 (R/W) MPU Region RNRber Register */
__IOM uint32_t RBAR; /*! & lt; Offset: 0x00C (R/W) MPU Region Base Address Register */
__IOM uint32_t RASR; /*! & lt; Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
} MPU_Type;
/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U /*! & lt; MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL & lt; & lt; MPU_TYPE_IREGION_Pos) /*! & lt; MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8U /*! & lt; MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL & lt; & lt; MPU_TYPE_DREGION_Pos) /*! & lt; MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0U /*! & lt; MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /* & lt; & lt; MPU_TYPE_SEPARATE_Pos*/) /*! & lt; MPU TYPE: SEPARATE Mask */
/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*! & lt; MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL & lt; & lt; MPU_CTRL_PRIVDEFENA_Pos) /*! & lt; MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1U /*! & lt; MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL & lt; & lt; MPU_CTRL_HFNMIENA_Pos) /*! & lt; MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0U /*! & lt; MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /* & lt; & lt; MPU_CTRL_ENABLE_Pos*/) /*! & lt; MPU CTRL: ENABLE Mask */
/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U /*! & lt; MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /* & lt; & lt; MPU_RNR_REGION_Pos*/) /*! & lt; MPU RNR: REGION Mask */
/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_ADDR_Pos 8U /*! & lt; MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL & lt; & lt; MPU_RBAR_ADDR_Pos) /*! & lt; MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4U /*! & lt; MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL & lt; & lt; MPU_RBAR_VALID_Pos) /*! & lt; MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0U /*! & lt; MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL /* & lt; & lt; MPU_RBAR_REGION_Pos*/) /*! & lt; MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register Definitions */
#define MPU_RASR_ATTRS_Pos 16U /*! & lt; MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL & lt; & lt; MPU_RASR_ATTRS_Pos) /*! & lt; MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_XN_Pos 28U /*! & lt; MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL & lt; & lt; MPU_RASR_XN_Pos) /*! & lt; MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_AP_Pos 24U /*! & lt; MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL & lt; & lt; MPU_RASR_AP_Pos) /*! & lt; MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_TEX_Pos 19U /*! & lt; MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL & lt; & lt; MPU_RASR_TEX_Pos) /*! & lt; MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_S_Pos 18U /*! & lt; MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL & lt; & lt; MPU_RASR_S_Pos) /*! & lt; MPU RASR: ATTRS.S Mask */
#define MPU_RASR_C_Pos 17U /*! & lt; MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL & lt; & lt; MPU_RASR_C_Pos) /*! & lt; MPU RASR: ATTRS.C Mask */
#define MPU_RASR_B_Pos 16U /*! & lt; MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL & lt; & lt; MPU_RASR_B_Pos) /*! & lt; MPU RASR: ATTRS.B Mask */
#define MPU_RASR_SRD_Pos 8U /*! & lt; MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL & lt; & lt; MPU_RASR_SRD_Pos) /*! & lt; MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1U /*! & lt; MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL & lt; & lt; MPU_RASR_SIZE_Pos) /*! & lt; MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0U /*! & lt; MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL /* & lt; & lt; MPU_RASR_ENABLE_Pos*/) /*! & lt; MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0+ header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value & lt; & lt; field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) & gt; & gt; field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M0+ Hardware */
#define SCS_BASE (0xE000E000UL) /*! & lt; System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*! & lt; SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*! & lt; NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*! & lt; System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*! & lt; SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*! & lt; SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*! & lt; NVIC configuration struct */
#if (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*! & lt; Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*! & lt; Memory Protection Unit */
#endif
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) & gt; & gt; 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) & gt; & gt; 2UL) )
/**
\brief Enable External Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC- & gt; ISER[0U] = (uint32_t)(1UL & lt; & lt; (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Disable External Interrupt
\details Disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC- & gt; ICER[0U] = (uint32_t)(1UL & lt; & lt; (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Get Pending Interrupt
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t)(((NVIC- & gt; ISPR[0U] & (1UL & lt; & lt; (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC- & gt; ISPR[0U] = (uint32_t)(1UL & lt; & lt; (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC- & gt; ICPR[0U] = (uint32_t)(1UL & lt; & lt; (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Set Interrupt Priority
\details Sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) & lt; 0)
{
SCB- & gt; SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB- & gt; SHP[_SHP_IDX(IRQn)] & ~(0xFFUL & lt; & lt; _BIT_SHIFT(IRQn))) |
(((priority & lt; & lt; (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) & lt; & lt; _BIT_SHIFT(IRQn)));
}
else
{
NVIC- & gt; IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC- & gt; IP[_IP_IDX(IRQn)] & ~(0xFFUL & lt; & lt; _BIT_SHIFT(IRQn))) |
(((priority & lt; & lt; (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) & lt; & lt; _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of an interrupt.
The interrupt number can be positive to specify an external (device specific) interrupt,
or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) & lt; 0)
{
return((uint32_t)(((SCB- & gt; SHP[_SHP_IDX(IRQn)] & gt; & gt; _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) & gt; & gt; (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((NVIC- & gt; IP[ _IP_IDX(IRQn)] & gt; & gt; _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) & gt; & gt; (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB- & gt; AIRCR = ((0x5FAUL & lt; & lt; SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable & lt; b & gt; __Vendor_SysTickConfig & lt; /b & gt; is set to 1, then the
function & lt; b & gt; SysTick_Config & lt; /b & gt; is not included. In this case, the file & lt; b & gt; & lt; i & gt; device & lt; /i & gt; .h & lt; /b & gt;
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) & gt; SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick- & gt; LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL & lt; & lt; __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick- & gt; VAL = 0UL; /* Load the SysTick Counter Value */
SysTick- & gt; CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0PLUS_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS " AS IS "
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) & & (__ARMCC_VERSION & gt; = 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include " cmsis_armcc.h "
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) & & (__ARMCC_VERSION & gt; = 6010050)
#include " cmsis_armcc_V6.h "
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include " cmsis_gcc.h "
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include & lt; cmsis_iar.h & gt;
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include & lt; cmsis_ccs.h & gt;
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use " carm -?i " to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include & lt; cmsis_csm.h & gt;
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */