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RFP30N06LE, RF1S30N06LESM
Data Sheet
30A, 60V, ESD Rated, 0.047 Ohm, Logic
Level N-Channel Power MOSFETs
These are N-Channel power MOSFETs manufactured using
the MegaFET process. This process, which uses feature
sizes approaching those of LSI integrated circuits gives
optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers and relay drivers. These transistors can be operated
directly from integrated circuits.
These transistors incorporate ESD protection and are
designed to withstand 2kV (Human Body Model) of ESD.
Formerly developmental type TA49027.
January 2004
Features
• 30A, 60V
• rDS(ON) = 0.047Ω
• 2kV ESD Protected
• Temperature Compensating PSPICE® Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Ordering Information
PART NUMBER
D
PACKAGE
BRAND
RFP30N06LE
TO-220AB
RF1S30N06LESM
TO-263AB
G
P30N06LE
1S30N06L
NOTE: When ordering use the entire part number. Add suffix, 9A, to
obtain the TO-263 variant in tape and reel i.e. RF1S30N06LESM9A.
S
Packaging
JEDEC TO-220AB
JEDEC TO-263AB
SOURCE
DRAIN
GATE
DRAIN (FLANGE)
©2004 Fairchild Semiconductor Corporation
GATE
DRAIN
(FLANGE)
SOURCE
RFP30N06LE, RF1S30N06LESM Rev. B1
RFP30N06LE, RF1S30N06LESM
Absolute Maximum Ratings
TA = 25oC, Unless Otherwise Specified
RFP30N06LE, RF1S30N06LESM
60
60
+10, -8
30
Refer to Peak Current Curve
Refer to UIS Curve
96
0.645
2
-55 to 175
UNITS
V
V
V
A
300
260
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (R GS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrostatic Discharge Rating, MIL-STD-883, Category B(2). . . . . . . . . . . . . . . .ESD
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
oC
oC
W
W/oC
kV
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
Drain to Source Breakdown Voltage
Gate to Threshold Voltage
BVDSS
VGS(TH)
MIN
TYP
MAX
UNITS
ID = 250µA, V GS = 0V, Figure 11
TEST CONDITIONS
60
-
-
V
VGS = VDS, ID = 250µA, Figure 10
1
-
2
V
IDSS
Gate to Source Leakage Current
Drain to Source On Resistance (Note 2)
IGSS
rDS(ON)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
VDS = Rated BVDSS , VGS = 0
-
-
25
µA
VDS = 0.8 x Rated B VDSS, VGS = 0, TC = 150oC
Zero Gate Voltage Drain Current
-
-
250
µA
VGS = +10, -8V
-
-
±10
µA
ID = 30A, VGS = 5V, Figure 9
-
-
0.047
Ω
VDD = 30V, ID = 30A, RL = 1Ω, VGS = 5V,
RGS = 2.5Ω,
Figures 13, 16, 17
-
-
140
ns
Total Gate Charge
ns
-
ns
-
30
-
ns
tf
Turn-Off Time
-
88
-
40
-
ns
tOFF
Fall Time
11
-
td(OFF)
Turn-Off Delay Time
-
tr
Rise Time
-
-
100
ns
-
51
62
nC
Qg(TOT)
VGS = 0V to 10V
Qg(5)
VGS = 0V to 5V
Qg(TH)
VGS = 0V to 1V
Gate Charge at 5V
Threshold Gate Charge
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
VDD = 48V,
ID = 30A,
RL = 1.6Ω
Figures 18, 19
-
nC
2.6
nC
1350
-
pF
-
290
-
pF
-
CRSS
34
1.8
-
VDS = 25V, VGS = 0V,
f = 1MHz
Figure 12
28
-
85
-
pF
Thermal Resistance Junction to Case
RθJC
-
-
1.55
oC/W
Thermal Resistance Junction to Ambient
RθJA
-
-
80
oC/W
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage (Note 2)
Diode Reverse Recovery Time
SYMBOL
VSD
trr
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ISD = 30A
-
-
1.5
V
ISD = 30A, dISD/dt = 100A/µs
-
-
125
ns
NOTES:
2. Pulse Test: Pulse Width ≤300ms, Duty Cycle ≤2%.
3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance Curve (Figure 3) and Peak Current
Capability Curve (Figure 5).
©2004 Fairchild Semiconductor Corporation
RFP30N06LE, RF1S30N06LESM Rev. B1
RFP30N06LE, RF1S30N06LESM
Typical Performance Curves
Unless Otherwise Specified
POWER DISSIPATION MULTIPLIER
1.2
40
ID , DRAIN CURRENT (A)
1.0
0.8
0.6
0.4
30
20
10
0.2
0
0
25
125
50
75
100
TC , CASE TEMPERATURE (oC)
0
25
175
150
50
75
100
125
150
175
TC , CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
1
ZθJC , NORMALIZED
THERMAL IMPEDANCE
0.5
0.2
PDM
0.1
0.1
t1
0.05
t2
0.02
0.01
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x Rθ JC + TC
SINGLE PULSE
0.01
10-5
10 -4
10 -2
10-3
10-1
10 0
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
TC = 25 oC
TJ = MAX RATED
ID , DRAIN CURRENT (A)
100
100ms
10
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
10ms
100ms
DC
1
1
10
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
©2004 Fairchild Semiconductor Corporation
100
500
IDM , PEAK CURRENT CAPABILITY (A)
200
VGS = 10V
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
175 – T c
I = I ----------------------
25
150
VGS = 5V
TC = 25oC
100
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
20
10-6
10-5
10-4
10-3
10-2
10 -1
t, PULSE WIDTH (s)
10 0
101
FIGURE 5. PEAK CURRENT CAPABILITY
RFP30N06LE, RF1S30N06LESM Rev. B1
RFP30N06LE, RF1S30N06LESM
Typical Performance Curves
Unless Otherwise Specified (Continued)
100
TC = 25oC
STARTING TJ = 150oC
10
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
1
0.01
VGS = 5V
VGS = 4.5V
60
VGS = 4V
40
VGS = 3V
20
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
1
0.1
tAV, TIME IN AVALANCHE (ms)
10
0
0
1.5
4.5
3.0
6.0
VDS , DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
3.0
100
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
80
-55oC
60
25 oC
175oC
40
20
VDD = 15V
6.0
1.5
3.0
4.5
VGS , GATE TO SOURCE VOLTAGE (V)
0
2.5
2.0
1.5
1.0
0.5
-40
0
40
80
120
160
200
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
2.0
2.0
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
VGS = VDS, I D = 250µA
1.5
1.0
0.5
0
-80
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
VGS = 5V, I D = 30A
0
-80
7.5
FIGURE 8. TRANSFER CHARACTERISTICS
NORMALIZED GATE
THRESHOLD VOLTAGE
7.5
FIGURE 7. SATURATION CHARACTERISTICS
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
IDS(ON) , DRAIN TO SOURCE CURRENT (A)
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
0
VGS = 10V
80
ID , DRAIN CURRENT (A)
IAS , AVALANCHE CURRENT (A)
100
STARTING TJ = 25oC
-40
160
120
0
40
80
TJ , JUNCTION TEMPERATURE (oC)
200
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
©2004 Fairchild Semiconductor Corporation
ID = 250µA
1.5
1.0
0.5
0
-80
-40
0
40
80
120
160
200
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
RFP30N06LE, RF1S30N06LESM Rev. B1
RFP30N06LE, RF1S30N06LESM
Typical Performance Curves
VDS , DRAIN TO SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
2000
CISS
1500
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
1000
COSS
500
CRSS
5.0
60
VDD = BVDSS
3.75
2.5
30
0.75 BVDSS 0.75 BVDSS
0.50 BVDSS 0.50 BVDSS
0.25 BVDSS 0.25 BVDSS
15
10
15
20
5
VDS , DRAIN TO SOURCE VOLTAGE (V)
0
1.25
RL = 2.0Ω
IG(REF) = 0.62mA
VGS = 5V
0
0
20
0
VDD = BVDSS
45
25
IG(REF)
IG(ACT)
t, TIME (s)
80
VGS , GATE TO SOURCE VOLTAGE (V)
Unless Otherwise Specified (Continued)
IG(REF)
IG(ACT)
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS
BVDSS
L
tP
VARY tP TO OBTAIN
REQUIRED PEAK IAS
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
tP
0V
IAS
0
0.01Ω
tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
tON
tOFF
td(ON)
td(OFF)
RL
VDS
VDS
VGS
tf
tr
90%
90%
+
VGS
-
10%
0
10%
0V
RGS
90%
DUT
VGS
0
FIGURE 16. SWITCHING TIME TEST CIRCUIT
©2004 Fairchild Semiconductor Corporation
10%
50%
50%
PULSE WIDTH
FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
RFP30N06LE, RF1S30N06LESM Rev. B1
RFP30N06LE, RF1S30N06LESM
Test Circuits and Waveforms
(Continued)
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 10V
VGS
Qg(5)
+
VDD
DUT
IG(REF)
VGS = 5V
VGS
-
VGS = 1V
0
Qg(TH)
IG(REF)
0
FIGURE 18. GATE CHARGE TEST CIRCUIT
©2004 Fairchild Semiconductor Corporation
FIGURE 19. GATE CHARGE WAVEFORMS
RFP30N06LE, RF1S30N06LESM Rev. B1
RFP30N06LE, RF1S30N06LESM
PSPICE Electrical Model
SUBCKT RFP30N06LE 2 1 3;
CA 12 8 1 3.34e-9
CB 15 14 3.44e-9
CIN 6 8 0 1.343e-9
rev 6/2/93
DPLCAP
DRAIN
2
LDRAIN
5
10
DBODY 7 5 DBDMOD
DBREAK 5 11 DBKMOD
DESD1 91 9 DESD1MOD
DESD2 91 7 DESD2MOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 75.39
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1
RSCL2
LDRAIN 2 5 1e-9
LGATE 1 9 7.22e-9
LSOURCE 3 7 6.31e-9
MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01
RBREAK 17 18 RBKMOD 1
RDRAIN 50 16 RDSMOD 11.86e-3
RGATE 9 20 2.52
RIN 6 8 1e9
RSCL1 5 51 RSLVCMOD 1e-6
RSCL2 5 50 1e3
RSOURCE 8 7 RDSMOD 26.6e-3
RVTO 18 19 RVTOMOD 1
5
51
-
DBREAK
RDRAIN
EVTO
20 + 18 8
LGATE RGATE
VTO +
21
DBODY
MOS2
MOS1
RIN
DESD1
+
17
18
-
16
6
9
91
11
EBREAK
+
GATE
ESCL
50
6
8
ESG
1
IT 8 17 1
RSCL1
+ 51
CIN
8
DESD2
LSOURCE
RSOURCE
3
7
S1A
12
SOURCE
S2A
13
8
S1B
RBREAK
15
14
13
17
18
S2B
13
CA
RVTO
CB
+
EGS
-
6
8
EDS
-
IT
14
+
19
VBAT
+
5
8
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 8 19 DC 1
VTO 21 6 0.5
ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/89,7))
.MODEL DBDMOD D (IS = 3.80e-13 RS = 1.12e-2 TRS1 = 1.61e-3 TRS2 = 6.08e-6 CJO = 1.05e-9 TT = 3.84e-8)
.MODEL DBKMOD D (RS = 1.82e-1 TRS1 = 7.50e-3 TRS2 = -4.0e-5)
.MODEL DESD1MOD D (BV = 13.54 TBV1 = 0 TBV2 = 0 RS = 45.5 TRS1 = 0 TRS2 = 0)
.MODEL DESD2MOD D (BV = 11.46 TBV1 = -7.576e-4 TBV2 = -3.0e-6 RS = 0 TRS1 = 0 TRS2 = 0)
.MODEL DPLCAPMOD D (CJO = 0.591e-9 IS = 1e-30 N = 10)
.MODEL MOSMOD NMOS (VTO = 1.94 KP = 139.2 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 1.07e-3 TC2 = -3.03e-7)
.MODEL RDSMOD RES (TC1 = 5.38e-3 TC2 = 1.64e-5)
.MODEL RSLVCMOD RES (TC1 = 1.75e-3 TC2 = 3.90e-6)
.MODEL RVTOMOD RES (TC1 = -2.15e-3 TC2 = -5.43e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.05 VOFF = -1.5)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.5 VOFF = -4.05)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.2 VOFF = 2.8)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.8 VOFF = -2.2)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records 1991.
©2004 Fairchild Semiconductor Corporation
RFP30N06LE, RF1S30N06LESM Rev. B1
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not intended to be an exhaustive list of all such trademarks.
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GTO™
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E2CMOSTM
I2C™
TM
EnSigna
ImpliedDisconnect™
FACT™
ISOPLANAR™
Across the board. Around the world.™
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MICROCOUPLER™
MicroFET™
MicroPak™
MICROWIRE™
MSX™
MSXPro™
OCX™
OCXPro™
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OPTOPLANAR™
PACMAN™
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QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY
ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT
CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
2. A critical component is any component of a life
1. Life support devices or systems are devices or
support device or system whose failure to perform can
systems which, (a) are intended for surgical implant into
be reasonably expected to cause the failure of the life
the body, or (b) support or sustain life, or (c) whose
support device or system, or to affect its safety or
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. I6