https://obrazki.elektroda.pl/6316123800_1531718264_thumb.jpeg :idea: DAP013 datasheet układu masz w załączniku. Albo uszkodzony sam ukł DAP013 , albo zobacz oporniki wysokoomowe podłączone pod pin.11 (pomiar ich wartości miernikiem, po wylutowaniu) Ważny układ kontroli (stabilizacji) nap. wyjściowego podłączony pod pin.6 - transoptor + elementy zastosowane na stronie wtórnej np. TL431/ lub inne rozwiązanie np. z DAS001 Kondensator elektrolityczny ukł. PFC to 86µF/ 450V PS. Układ pracy z macbook-power-adapter-magsafe-2 Zabezpieczenie przed wzrostem nap. wyjściowego to : transoptor , Q34 i ZD31 https://obrazki.elektroda.pl/2906160700_1531719822_thumb.jpeg Pamiętaj tylko, że ten model SADP-90FH B(AD-9019S) ma rozwiązanie z "igiełką (dodatkowy 3-ci pin) we wtyku dla laptopów firmy Samsung SADP-90FH D (AD-9019S) 19V 4.74A 90W ( wtyk 5.5x3.0 z "szpilką") Z uwagi na cenę zasilacza kupionego w sklepie/ebay (ok.20€), a ceną laptopa ( koszt serwisu po nie udanej naprawie zasilacza SADP-9019s ?) zalecałbym raczej zakup nowego SADP. SADP-90FH to kopia oryginalnego zasilacza adaptera od Samsung BA44–00215A (drogi). 917007
AND8331/D
Quasi-Resonant CurrentMode Controller for HighPower ac-dc Adapters
Prepared by: Stéphanie Conseil
ON Semiconductor
http://onsemi.com
Introduction
Pin Description
This document describes the implementation of the
DAP013 inside an AC-DC adapter.
The DAP013 offers everything to build high performance
AC-DC converters or offline adapters. Thanks to a novel
valley lockout system, the controller is able to switch inside
the drain-source valley and is immune to valley jumping
instabilities. When the output load decreases significantly,
the controller toggles to a fixed peak current/variable
frequency mode that ensures very low standby power
consumption. And last, but not least, the DAP013 features
the usual protections that help to build cheap and safe power
supplies: OVP, OTP, Brown-Out (C and D options),
Short-circuit protection (latched for A, C versions and
auto-recovery for D, F versions), soft-start, OPP, internal
TSD...
To summarise, the DAP013 offers the following
characteristics:
• Quasi-resonant Peak Current-mode Control Operation
• Valley Switching Operation with Valley-lockout for
Noise-immune Operation
• VCO Mode (fixed peak current, variable frequency) in
Light Output Load for Improved Standby Dissipation
• Internal 5 ms Soft-start
• Loss-free Adjustable Over Power Protection
• Auto-recovery or Latched Internal Output Short-circuit
Protection
• Adjustable Timer for Improved Short-circuit Protection
• Over-voltage and Over-temperature Protection Inputs
• Brown-out Input for C and D Versions
• +500 mA / –800 mA Peak Current Source/Sink
Capability
• Internal Temperature Shutdown
• Direct Optocoupler Connection
• 3 ms Blanking Delay to Ignore Leakage Ringing at
Turn-off
• Extremely Low No-load Standby Power
• SO14 Package
Over Power Protection pin (OPP, pin 1): applying a
negative voltage on this pin reduces the internal maximum
peak current set point.
Over Temperature Protection pin (OTP, pin 2): Connect
an NTC between this pin and ground. An internal current
source biases the NTC. When the NTC pulls the pin down,
the circuit permanently latches-off.
Timer pin (Timer, pin 3): Wiring a capacitor from this pin
to ground helps selecting the timer duration.
Zero Voltage Detection pin (ZCD, pin 4): Connected to
the auxiliary winding, this pin detects the core reset event.
Timing Capacitor pin (Ct, pin 5): A capacitor connected
to this pin acts as the timing capacitor in VCO mode.
Feedback pin (FB, pin 6): Hooking an optocoupler
collector to this pin will allow regulation.
Current Sense pin (CS, pin 7): This pin monitors the
primary current and triggers the fault if needed.
Ground pin (GND, pin 8): The controller ground.
Driver pin (DRV, pin 9): This pin delivers pulses to the
power MOSFET.
Power Supply pin (VCC, pin 10): This pin supplies the
controller and accepts voltage up to 28 V.
Brown-Out pin (BO, pin 11): Allows shutting-down the
controller for a chosen input voltage level. (C and D versions
only)
Over Voltage Protection pin (OVP, pin 12): By pulling
this pin high, the controller can be permanently latched-off.
High Voltage pin (HV, pin 14): Connected to the bulk
capacitor, this pin powers the internal current source to
deliver a start-up current that charges the VCC capacitor.
© Semiconductor Components Industries, LLC, 2008
June, 2008 − Rev. 0
I. Over Power Protection
1. How Does It Work?
A flyback operated in Quasi Resonant mode exhibits wide
peak current variations in relationship to the input voltage
conditions. As a result, the converter output power range
widens as the input voltage increases. To cope with safety
requirements, the designer needs to make the power output
capability independent from the input conditions. A possible
1
Publication Order Number:
AND8331/D
AND8331/D
way of doing it is call Over Power Protection (OPP). The
novel technique implemented in the DAP00X takes benefits
of the auxiliary winding voltage whose negative amplitude
relates to the input rail voltage. When the power MOSFET
is conducting, the auxiliary winding voltage becomes the
input voltage VIN affected by the auxiliary to primary turn ratio
ǒ
N p,aux +
By applying this voltage through a resistor divider on the
OPP pin, we have an image of the input voltage transferred
to the controller via this pin. This voltage is added internally
to the 0.8 V reference and affects the maximum peak current
(see Figure 1). As the OPP voltage is negative, an increase
of input voltage implies a decrease of the maximum peak
current setpoint:
Ǔ
N aux
:
Np
V CS,max + 0.8 ) V OPP
V aux + −N p,auxV IN
If OPP pin is grounded, there is no decrease of the peak
current setpoint.
(eq. 1)
Rupper
CS
OPP
Aux
+
1
ESD
Protection
Rlower
(eq. 2)
0.8 V + Vopp
+
+
-
IpFlag
0.8 V
Figure 1. OPP Circuitry
But knowing the amount of current that will circulate
inside the OPP diode for these values of VOPP, it is possible
to set a higher bias current inside the resistor divider in order
to neglect the diode leakage for OPP voltage lower than
−300 mV. Figure 2 shows the diode leakage at different
junction temperatures according to VOPP. In any case, it is
forbidden to inject current higher than 2 mA in this pin
otherwise, substrate injections could occur, leading to a
possible erratic behaviour.
The amount of negative voltage that can be applied on the
OPP pin is limited by the ESD diode placed on the pin to
protect the silicon. Temperature characterization shows that
this diode will start to conduct if the applied bias (VOPP) is
lower than −300 mV. Thus, if a voltage lower than −300 mV
is applied on the OPP pin, the peak current decrease will no
longer be linear.
100
90
80
70
125°C
IOPP (mA)
60
50
40
110°C
30
20
10
0
0.20
25°C
0.25
0.30
0.35
0.40
0.45
VOPP (V)
0.50
0.55
0.60
0.65
Figure 2. OPP Diode Leakage Current vs. VOPP at TJ = 255C, 1105C, 1255C
In order to filter the switching noise on OPP signal, the designer can add a small capacitor between OPP and GND. This
capacitor value can be adjusted according to the power MOSFET on-time duration at high line and must not be higher than 200 pF.
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AND8331/D
2. OPP Resistors Calculation
Let us assume the design needs a peak current reduction of 34% at 370 V dc, therefore, the amount of voltage we must apply
on pin 2 is:
V OPP + −0.8
0.34 + −272 mV
(eq. 3)
By using the resistor divider law on Rupper, Rlower we obtain:
V OPP + *
R lower
N
V
R upper * R lower p,aux IN
(eq. 4)
Or:
R upper
N p,auxV IN * V OPP
+*
R lower
V OPP
(eq. 5)
If our auxiliary to primary turn ratio is 0.12, we obtain:
R upper
0.12
+*
R lower
370 * (−0.272)
[ 164
−0.272
(eq. 6)
Thus, we can select:
Rupper = 160 kW and Rlower = 1 kW
The bridge current during the on time is:
V OPP
R lower
(eq. 7)
I bridge + 0.272 + 272 mA
1000
(eq. 8)
I bridge +
3. Why is the OPP Non Dissipative?
Let us try to calculate the average current in the OPP bridge:
T sw
I bridge,mean + 1
T sw
ŕ ŤR
0
Ť
V aux(t)
dt
upper ) R lower
(eq. 9)
After some calculations, we obtain:
I bridge,mean +
ǒ
T
T on
1
N
V ) off (V ) V f)
R upper ) R lower T sw p,aux IN T sw CC
Ǔ
(eq. 10)
Keeping up with our example from before, we can measure Ton, Toff, Tsw on our adapter at 370 V dc, light output load (we
are in VCO mode): Ton = 1.2 ms, Toff = 3.6 ms, Tsw = 40 ms
I bridge,mean +
ǒ
1.2 m
1
160 k ) 1 k 40 m
0.12
370 )
Ǔ
3.6 m
25.6 + 2.26 mA
40 m
(eq. 11)
If we had selected Rlower = 100 W and Rupper = 16 kW (meaning we impose a higher bias current in the resistor bridge), we
would have Ibridge = 22.6 mA only!
4. OPP Trick
From our previous example, we have calculated the OPP resistors in order to have a peak current reduction of 34% at 370 V
dc that corresponds to VOPP = -272 mV.
We obtained: Rlower = 1 kW and Rupper = 160 kW
Now, with these resistors what will be the peak current reduction at 110 V dc?
V OPP + −
R lower
N
V + 1
161
R upper ) R lower aux,p IN
0.12
110 + 82 mV
(eq. 12)
This corresponds to a peak current reduction of 10.2% at low line. However because of the internal propagation delay, the
peak current reduction is smaller is reality.
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AND8331/D
Ipk Set Point
Ipk Set Point
100%
100%
90%
90%
66%
66%
110
370
110
VIN (V)
Design Example:
If we want to avoid losing 10% maximum of peak current
at low line, we can introduce a simple threshold in the OPP
circuitry through a zener diode placed in series with the
resistive divider as shown in Figure 4.
This extra diode allows selecting the input voltage at
which we want to start applying over power compensation.
We want to start reducing the maximum peak current
around 220 V dc (roughly 155 Vrms).
This corresponds to an auxiliary winding voltage:
V aux + −N p,auxV IN + −0.12
220 + −26.4 V
(eq. 13)
So we need a zener diode with a breakdown voltage:
BV DZ + 0.12
(370 * 220) + 18 V
(eq. 14)
The new values for OPP resistors can be calculated using
Equation 15:
Zener
N p,auxV IN * BV DZ * V OPP
R upper
+*
R lower
V OPP
OPP
Rupper
Aux
Cdec
VIN (V)
Figure 5. Ipk Set Point over Input Voltage using a
Zener in Series with the OPP Resistors
Figure 3. Peak Current Set Point over the Input
Voltage with Rupper = 160 kW and Rlower = 1 kW
Rbias
370
220
R upper
0.12
+*
R lower
Rlower
(eq. 15)
370 * 18 * (−0.272)
+ 98 (eq. 16)
−0.272
We choose: Rupper = 100 kW and Rlower = 1 kW
II. Over Temperature Protection
The adapter operating in a confined area, e.g. the plastic
case protecting the converter, it is important to look after the
internal ambient temperature. If this temperature would
increase beyond a certain point, catastrophic failures could
occur through semiconductors thermal runaway or
transformer saturation. To prevent this from happening, the
DAP00X embeds a novel Over Temperature Protection
(OTP) circuitry appearing in Figure 6.
Figure 4. OPP with Zener Diode
VDD
Ilatch
OVP Comp
End of
Soft−start
2
OTP
NTC
Cfilt
+
+
VOTP
Figure 6. OTP Schematic
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20 ms Filter
AND8331/D
The Ilatch current (91 mA typ.) biases the Negative
Temperature Coefficient sensor (NTC), naturally imposing
a dc voltage on the OTP pin. When the temperature
increases, the NTC’s resistance reduces (at 110°C, RNTC =
8.8 kW instead of 470 kW at 25°C) bringing the pin 2 voltage
down until it reaches a typical value of 0.8 V: the comparator
trips and latches-off the controller (Figure 7). Controller
reset occurs when a) the VCC is cycled from on to off b) the
brown-out pin senses a stop condition on the bulk voltage.
During start-up and soft-start, the output of the OTP
comparator is masked to allow the voltage on pin OTP to
grow if a filtering capacitor is installed across the NTC.
The filtering capacitor value should be 1 nF.
In DAP013, the OTP trip point corresponds to a resistance of:
R NTC +
V OTP
+ 0.8 + 8.79 kW
I latch
91 m
(eq. 17)
This corresponds to a temperature of 110°C using the
TTC03-474.
VCC
VDRV
VOTP
Figure 7. Capture of an OTP Event. Here, the NTC was Heated with a Hairdryer...
III. Timer Pin and Fault Management
Protection against short-circuit or overload is insured by
monitoring the current sense signal. The controller reaction
is thus fully independent from the auxiliary to power
winding coupling. When the primary current exceeds ILimit,
the “Max Ip” comparator trips and the timer capacitor
charges by the ItimerC current source. When the current
comes back within safe limits, the “Max Ip” comparator
becomes silent and the PWM comparator triggers the
discharge of the timer capacitor. The timer capacitor is thus
discharged by a constant current ItimerD. The internal
circuitry appears in Figure 8.
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AND8331/D
HV
Vcc
Vcc Management
S
Q
Vdd
DRV
Q
Fault
R
CS
FB/4
ItimerC
PNOK
PWM
PWM
Reset
Comparator
+
-
Timer
+
R
Vtim Fault
+
ItimerD
Ctimer
Q
OPP
Ilimit
Max Ip
IpFlag
Comparator
+
+
Ilimit + Vopp
+
Q
S
Figure 8. Timer Circuitry
For D and F versions, when the voltage of timer capacitor reaches VtimFault, the output pulses are stopped and the controller
tries to re-start via a triple hiccup. (see Figure 9): this is the so-called auto-recovery operation.
VCC
Vdrain
4.5 s
Vtimer
93 ms
Figure 9. The Triple Hiccup in Fault Mode
For versions A and C, when Vtimer reaches VtimFault, the
controller stops pulsing and stays latched. To reset the
controller, the user must unplug the power supply to allow
VCC to drop below VCCreset level (5.5 V). (see Figure 10)
The triple hiccup helps to reduce the power consumption
in fault mode. In Figure 9, the burst is only 2% for a 60 W
adapter (with CVcc = 100 mF).
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AND8331/D
VCC
VDRV
5 V fault threshold
VTimer
Figure 10. The Latched Short-circuit Protection in A and C Versions
Choosing Timer Duration and Timer Capacitor
Where :
− Tfault is the duration before the fault validation
− ItimerC is the charging current (10 mA typ. from
datasheet)
− VtimFault is the timer voltage threshold at which the
fault is validated (5 V typ. from datasheet)
While choosing the timer duration, the user must ensure
that it is long enough to allow the power supply to enter
regulation at low line and full load. (see Figure 11)
The timer capacitor value can be calculated with:
C timer +
T faultI timerC
V timFault
VFB
(eq. 18)
VtimFault = 5 V
1V
Softstart
Vtimer
VOUT
Vdrain
Figure 11. Timer Margin at Low Line, Full Load on a 19 V / 3 A Adapter
IV. Zero Voltage Crossing Detection
The Zero Crossing Detection circuit (ZCD) allows turning
on the power MOSFET when the drain-source voltage is the
lowest. This detection is achieved by monitoring the auxiliary
winding voltage. The typical detection level is around 50 mV
(Figure 12). By delaying this signal thanks to an RC network
(the internal ESD protection features a parasitic capacitance
of 10 pF) it is possible to switch right in the valley of the
drain-source voltage.
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AND8331/D
VZCD
VTh
Figure 12. Typical ZCD Signal. Here, the Power
Supply Operates in 2nd Valley
Rdem
ZCD
Resd
+
-
Aux
Cdem
+
Vth
Dz
ESD
demag
Tblank
GND
DRV
Leakage Blanking
Figure 13. Zero Voltage Crossing Detection Circuit
V. VCO Mode and Timing Capacitor
Rdem should be calculated to limit the current inside pin
4 to less than +3 mA/-2 mA.
For example, if the voltage on auxiliary winding is –45 V
at highest line, Rdem should be higher than 45/0.002 =
22.5 kW.
In order to avoid false triggering by the leakage
inductance, a blanking circuit masks the ZCD signal during
2 to 4 ms. So when designing the power supply, the designer
must ensure that during valley operation, the
demagnetization duration is higher than 4 ms. If not, the 1st
valley will also be blanked and valley switching instabilities
will occur.
1. How Does it Work?
At nominal power, the power supply operates in a variable
frequency system where discrete frequency steps occur as
the controller looks for the different valley positions. At low
output power, the controller enters a Voltage-Controlled
Oscillator (VCO) mode where the switching frequency is
folded back. This mode is entered when VFB drops below
0.8 V. The controller remains in this mode until VFB
increases above 1.4 V. During the VCO operation (VFB & lt;
0.8 V), the peak current is frozen to 25% of its maximum
value and the frequency diminishes as the output power
decreases. (Figure 14)
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AND8331/D
Figure 14. Idrain, Vdrain, VCt, at Different Output Loads in VCO Mode
0 V and a new period starts. The relationship between FB
voltage and the internal threshold is:
The switching frequency is set by the end of charge of the
timing capacitor Ct. This capacitor is charged by a constant
current source ICt and its voltage VCt is compared to an
internal threshold fixed by the FB loop. When VCt reaches
the threshold, the capacitor is rapidly discharged down to
V FBth + 6.5 * (10ń3)V FB + V Ct
(eq. 19)
VDD
VCO
Rpullup
FB
VFBth
6.5 − (10/3) Vfb
+
VDD
DRV
ICt
Q
Q
S
Ct
R
Ct Discharge
CS Comparator
Figure 15. VCO Schematic
the switching frequency in the 4th valley and the switching
frequency imposed by the Ct capacitor, the frequency jump
may create an instability by forcing the peak current to leave
its frozen state: an hesitation between 4th valley and the
VCO mode takes place (Figure 16) and can create output
ripple and noise.
2. How to Calculate the Timing Capacitor Value?
The timing capacitor must be selected with care. Indeed,
when the controller leaves the valley switching mode to
enter the VCO mode, the frequency changes from a
valley-position-controlled value to a switching frequency
imposed by the Ct capacitor. If a too big gap exists between
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AND8331/D
Figure 17 shows a normal transition from 4th valley to the
VCO mode. At the beginning, the output load is such that it
imposes a VFB near 0.8 V in 4th valley operation, with a
switching period Tsw1. Then, if the load is slightly
decreased, the FB voltage also passes below the 0.8 V
threshold: the VCO mode is entered and the switching
frequency decreases. (In VCO mode, the switching
frequency is imposed by the FB voltage regardless of the
position in the drain signal). The controller will stay in VCO
mode until the FB voltage increases above 1.4 V. If we have
an optimum timing capacitor value, the new steady state
point is such that VFB is near 1.4 V and imposes a switching
period Tsw2 larger than Tsw1.
VFB
Vdrain
4th valley
VCO mode
Figure 16. The Controller Hesitates between VCO
Mode and 4th Valley: Ct is Too Big!
Load
VFB
1.4 V
0.8 V
VFBth
Tsw2
Tsw1
4th Valley
VCO Mode
Figure 17. 4th Valley to VCO Mode Transition with an Optimum Timing Capacitor Ct
To calculate Ct, we first need to estimate the switching period at the end of the 4th valley operation, for a FB voltage near
0.8 V by using Equation 20 or by directly measuring it on our adapter:
T sw1 +
ǒ
Ǔ
N ps
0.2 L
1
)
) 7p ǸL pC lump
R sense p V IN,minDC V out ) V f
Where:
− Rsense is the sense resistor
− 0.2 relates to the voltage setpoint on the current-sense
comparator when VFB = 0.8 V.
− Lp is the primary inductance
− VIN,minDC is the minimum DC input voltage, bulk
ripple included
(eq. 20)
− Nps = Ns/Np is the primary to secondary turn ratio of
the transformer
− Vout is the output voltage
− Vf is the output diode forward voltage
− Clump regroups all capacitances surrounding the drain
node (MOSFET capacitor, transformer parasitics...). As
a first approximation, you can use the MOSFET
drain-source capacitance COSS instead of Clump.
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AND8331/D
Based on lab experiments, the switching period gap
between the end of 4th valley operation (Tsw1) and VCO
mode (Tsw2) for a FB voltage near 1.4 V (which is the
threshold for VCO mode to 4th valley transition, VFB
increasing ) must not exceed 12 ms. Thus, for VFB = 1.4 V,
we will have:
T sw2 + T sw1 ) 12 ms
Thus, we can deduce the timing capacitor value knowing
VCt, Tsw2 and the charging current source ICt (20 mA typ.
from datasheet):
Ct +
T sw1 +
1.4 + 1.83 V
•
•
•
•
•
•
VIN,minDC = 100 V
Vout + Vf = 19 + 0.6 V
Lp = 190 mH
Clump = 200 pF
Nps = 0.25
Rsense = 0.25
First, with Equation 14, we estimate Tsw1 which is the
switching period of our power supply for an output load
corresponding to a VFB = 0.8 V:
(eq. 22)
ǒ
Ǔ
N ps
0.2 L
1
)
) 7p ǸL pC lump
R sense P V IN,minDC V out ) V f
+ 0.2 190
0.25
10 *6
(eq. 23)
Application Example: 19 V/60 W Adapter
(eq. 21)
Equation 13 allows calculating VCt for VFB = 1.4 V:
V Ct + 6.5 * (10ń3)
I CtT sw2
1.83
1
ǒ100 ) 190.25 Ǔ ) 7p Ǹ190
) 0.6
(eq. 24)
10 *6
200
10 *12 + 7.75 ms (129 kHz)
When measured on the adapter we have: Tsw1 = 8.47 ms (Fsw1 = 118 kHz) corresponds to an ouput power of 9 W.
We calculate the timing capacitor value:
Ct +
I CT(T sw1 ) 12 m)
20
+
1.83
10 *6(7.75
10 *6 ) 12
1.83
10 *6)
+ 216 pF
(eq. 25)
We select Ct = 220 pF.
VI. Feedback
The feedback pin features an internal pull-up resistor
which connects to the optocoupler, as shown in Figure 18.
This pin is also connected to the internal valley comparators
that will select the operating valley according to the FB
voltage (see datasheet).
It is recommended to add a capacitor between FB pin and
GND pin of the controller. This capacitor has two
advantages: it offers a filtering action on the FB signal and
it forms with Rpullup a pole located at:
fp +
(eq. 26)
This pole will help you to stabilize the power supply.
Rpullup
+
VDD
5V
1
2p R pullupC pole
FB
VII. VCC
The DAP013 includes a high voltage startup circuitry that
derives current from the bulk line to charge the VCC
capacitor. When the power supply is first connected to the
mains outlet, the internal current source is biased and
charges up the VCC capacitor. When the voltage on this VCC
capacitor reaches the VCCon level, the current source turns
off, reducing the amount of power being dissipated. At this
time, the controller is only supplied by the VCC capacitor,
and the auxiliary supply should take over before VCC
collapses below VCCmin. Figure 19 shows the internal
arrangement of this structure:
Cpole
GND
Figure 18. FB Pin Features an Internal Pull-up
Resistor...
The pull-up resistor value is typically around 20 kW and
is referenced in the datasheet.
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AND8331/D
14
+
-
Where:
− ICC2 is the controller consumption (see datasheet)
− Qg is the MOSFET total gate charge
− Fsw is the switching frequency in maximum load,
minimum input voltage
Now, we need to estimate the total startup time.
The high voltage startup circuit features two startup
levels, IC1 and IC2. At power-up, as long as VCC is below
VTh (0.70 V typ.), the source delivers IC1 (around 300 mA
typical). The duration is:
HV
IC1 or IC2
10
+
VCCon
VCCmin
+
8
t 1 + C Vcc
V Th
I C1
(eq. 28)
Then, when VCC reaches 0.70 V, the source smoothly
transitions to IC2 (6 mA typ.) and delivers its nominal value.
When VCC reaches VCCon, the source is turned-off:
Figure 19. Startup Circuitry
t 2 + C Vcc
1. How to Choose VCC Capacitor?
The VCC capacitor is calculated to allow the power supply
to close the loop before VCC drops to VCCmin. If we call treg
the time needed by the power supply to close the loop, the
VCC capacitor can be estimated with:
C Vcc +
(I CC2 ) Q gF sw)t reg
V CCon * V CCmin
C Vcc +
(I CC2 ) Q qF sw)t reg
(2.5
+
V CCon * V CCmin
V CCon * V Th
I C2
(eq. 29)
The total startup time is the sum of t1, t2 and treg.
t startup + C Vcc
ǒ
Ǔ
V Th V CCon * V Th
)
) t reg
I C1
I C2
(eq. 30)
For Example:
(eq. 27)
The time needed by the power supply to enter regulation
is 45 ms worst case (full load).
The MOSFET is a 6A / 600 V with a gate charge:
Qg = 24 nC
10 *3 ) 24
10 *9 65000) 45
15 * 9
10 *3
+ 30.45 mF
We choose: CVcc = 47 mF
VCC
IC2
VOUT
VTh
IC1
t1
t2
treg
Figure 20. The Dual Level Startup Current Source in Action, Here with a Vcc Capacitor of 100 mF
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(eq. 31)
AND8331/D
2. What is the Benefit of Using a Dual Level Startup Current Source?
The dual level startup current source allows to limit the
power dissipation of the controller in case of short-circuit
between VCC and GND.
Without the dual level startup, in high line conditions
(VHV = 370 V dc), the current delivered by the startup device
will seriously increase the junction temperature. For
instance, since IC2 equals 3 mA (the minimum corresponds
to the highest TJ), the device would dissipate 370 x 3 m =
1.11 W.
Thanks to the dual level startup, the current source deliver
IC1 = 300 mA if Vcc is below 0.70 V. Thus, in case of
short-circuit between VCC and GND, the power dissipation
will drop to 370 x 300u = 111 mW.
VIII. Brown Out
The C and D versions of DAP013 feature a Brown Out pin
(BO) which protects the power supply against low input
voltage conditions (Figure 21). This pin permanently
monitors a fraction of the bulk voltage through a voltage
divider. When this image of bulk voltage is below the BO
threshold, the controller stops switching. When the bulk
voltage comes back within safe limits, the circuit goes
through a new startup sequence including soft-start and
re-starts switching (Figure 24). The hysteresis on brown-out
pin is implemented with a low side current source sinking
10 mA when the brown-out comparator is low (Vbulk & lt;
Vbulk(ON)). This offers adequate precision at shutdown.
HV−bulk
VBO
Rupper
+
20 ms Noise Delay
BO
BO Comp
11
Rlower
BO Reset
+
IBO
IBO “on” if BO Comp “low”
IBO “off” if BO Comp “high”
Figure 21. Brown-Out Circuit
1. Calculating the BO Resistors
Vbulk(ON)
Vbulk(OFF)
Rupper
Rupper
BO
iu
ibo
il
11
iu
BO
iu
11
IBO
Rlower
Rlower
Figure 22. Brown-out Equivalent Schematic at Startup
First of all, select the bulk voltage value at which the
controller must start switching (Vbulk(ON)) and the bulk
voltage for shutdown (Vbulk(OFF)). According to Figure 22,
we have:
i u + i l ) I BO
When Vbulk reaches Vbulk(ON), the hysteresis current
source is turned OFF. Thus, at shutdown, the BO voltage
only depends of Vbulk(OFF) and Rupper, Rlower (Figure 23).
V BO +
(eq. 32)
R upper
+
V BO
) I BO
R lower
R lower
V
R upper ) R lower bulk(OFF)
(eq. 34)
Deducing Rupper from Equatio 34, we replace Rupper by its
expression in Equation 33. We obtain:
Where: IBO is the brown-out hysteresis current.
By replacing iu and il by their values, the previous
equation becomes:
V bulk(ON) * V BO
Figure 23. Brown-out at Shutdown
R lower +
(eq. 33)
R upper +
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13
V BO(V bulk(ON) * V bulk(OFF))
I BO(V bulk(OFF) * V BO)
R lower(V bulk(OFF) * V BO)
V BO
(eq. 35)
(eq. 36)
AND8331/D
Design Example
* V BO + 0.8 V
R lower +
* I BO + 10 mA
* V bulk(ON) + 120 V
R upper +
* V bulk(OFF) + 60 V
V BO(V bulk(ON) * V bulk(OFF))
I BO(V bulk(OFF) * V BO)
R lower(V bulk(OFF) * V BO)
V BO
+
+
0.8(120 * 60)
+ 81.1 kW
10 m(60 * 0.8)
81.1 k
(60 * 0.8)
+ 6 MW
0.8
(eq. 37)
(eq. 38)
VCC
IBO turnson when
VCC is high enough
VBO
Vbulk
BO threshold
VDRV
IBO turnsoff
Figure 24. BO at Startup. The Controller Starts Pulsing if VBO & gt; BO Threshold and VCC & gt; VCCon
IX. Over Voltage Protection
The DAP013 also provides a protection against an over voltage condition (OVP), e.g. in case of the optocoupler destruction
(Figure 25).
VCC
Vcc
Ru
OVP
12
or
Rl
+
Rbias
20 us filter
−
Vovp
Figure 25. OVP Circuit
The OVP pin (12) is connected to an internal comparator that will latch the controller if a voltage higher than 3 V is applied
on this pin. Once the controller is latched, the user must unplug the power supply to allow VCC falling below VCCreset (around
5 V) to reset the controller.
As pin 12 is high impedance, the over voltage protection can be implemented also by using a resistor divider instead of the
traditional zener diode.
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AND8331/D
VCC
VDRV
OVP threshold
VOVP
Figure 26. Scope Shot of an Over voltage Event. Here, the OVP
was Implemented with an 18 V Zener Diode
X. Typical Application Schematic
The schematic in Figure 27 shows the implementation of DAP013 inside a 19 V/60 W power supply.
L
N
U4
KBU4K
FL1
C9
X2
220nF
C18
100nF
C14
100u
+
IN
R1
10
R23
6Meg
−
R25, 6.8k
R30
270k
C6
22p
C5a +
1N4937 D1
1.2mF
35V
12
4
11
5
10
6
9
7
C4
330p
13
3
C13
220n
R12
6.8k
8
C5
1n
C8
C15
2.2nF
14
2
U5
NTC
U2b
R4
6.8k
U1
DAP013D
R18
8.2k
1
R31
1k
T1
C1
10n
220p
D2
MBR20200
R22
3Meg
D5
R16
C17
R17
22k
1n
C20
100n
R29
1k
D3
1N4148
+
C11
33u
+
C7
100uF
25V
Gnd
Gnd
R9
1k
R5
27k
R15
1k
U2a
M1
10
Vout
Type = Y1
SPP06N60
C10
R3
47k
R26
0.5
R7
39k
47n
R27
0.5
Figure 27. 19 V /60 W Power Supply Schematic with DAP013D
Conclusion
+
C5b
1.2mF
35V
Lp = 190 mH
Nps = 0.25
Nauxp = 0.22
D6
1N967
1N4937
R21
82k
L3
2.2u
U3
TL431
R8
10k
Gnd
This controller associate a quasi-resonant operation mode
for high output loads with a VCO mode to improve the
efficiency of the power supply at light loads.
This application note has described in detail how to select
the components surrounding the DAP013.
The DAP013 contains all the features (OPP, OVP, OTP,
short-circuit protection, BO...) to build high performance
ac-dc power supplies.
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AND8331/D
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