820-00165-A NYKS 94V-0 NMI9 455T 02A na naklejce jest jeszcze: MLB 2.2G EL 8G SI dodam jeszcze układ wokół którego są ubytki: 980 YFE LM4FS1EH 5BBCIG 59AQFYW G1 chyba znalazłem schemat, dorzucam także screen: https://obrazki.elektroda.pl/7159271500_1541592413_thumb.jpg Najgorsze, że na płycie niema oznaczeń elementów.
8
7
6
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
D
5
4
ECN
& lt; REV & gt;
& lt; ECN & gt;
DESCRIPTION OF REVISION
CK
APPD
DATE
J113 MLB SCHEMATIC
10/03/14
(.csa)
TABLE_TABLEOFCONTENTS_HEAD
Date
Contents
MASTER
Table of Contents
2
BOM Configuration
3
BOM Variants
4
MASTER
PD PARTS
TABLE_TABLEOFCONTENTS_ITEM
6
02/06/2013
7
8
CPU/PCH POWER
9
10
TABLE_TABLEOFCONTENTS_ITEM
12
PCH Audio/JTAG/SATA/CLK
13
PCH PCIe/USB/LPC/SPI/SMBus
1.05V S0 Power Supply
J41_MLB
Misc Power Supplies
J41_MLB
Power FETs
J41_MLB
Power Control
J41_MLB
Internal DisplayPort Connector
J41_MLB
Left I/O (LIO) Connector
CLEAN_J43
Power Aliases
J41_MLB
Signal Aliases
J41_MLB
Func Test / No Test
J41_MLB
Project FCT/NC/Aliases
J41_MLB
PCB Rule Definitions
CONSTRAINTS
CPU Constraints
CONSTRAINTS
PCH Constraints 1
CLEAN_J43
09/17/2012
05/21/2013
02/06/2013
78
TABLE_TABLEOFCONTENTS_ITEM
02/06/2013
80
TABLE_TABLEOFCONTENTS_ITEM
02/06/2013
81
59
J41_MLB
TABLE_TABLEOFCONTENTS_ITEM
J41_MLB
LCD/KBD Backlight Driver
58
02/06/2013
J41_MLB
05/21/2013
77
TABLE_TABLEOFCONTENTS_ITEM
J41_MLB
15
14
5V S4RS3 / 3.3V S5 Power Supply
57
02/06/2013
PCH PM/PCI/GFX
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
J41_MLB
14
J41_MLB
05/21/2013
76
56
02/06/2013
J41_MLB
LPDDR3 Supply
55
02/07/2013
13
TABLE_TABLEOFCONTENTS_ITEM
CPU VR12.5 VCC Power Stage
04/09/2013
75
TABLE_TABLEOFCONTENTS_ITEM
J41_MLB
J41_MLB
05/21/2013
74
TABLE_TABLEOFCONTENTS_ITEM
WILL_J43
PCH Decoupling
12
11
J41_MLB
CPU VR12.6 VCC Regulator IC
54
01/08/2013
CPU Decoupling
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
J41_MLB
10
J41_MLB
73
53
02/06/2013
CPU/PCH GROUNDS
TABLE_TABLEOFCONTENTS_ITEM
DC-In & G3H Supply
72
TABLE_TABLEOFCONTENTS_ITEM
J41_MLB
9
MASTER
02/06/2013
PBus Supply & Battery Charger
52
04/09/2013
MASTER
04/26/2013
71
TABLE_TABLEOFCONTENTS_ITEM
J41_MLB
8
TABLE_TABLEOFCONTENTS_ITEM
Battery Connector
51
02/06/2013
CPU DDR3/LPDDR3 Interfaces
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
J41_MLB
7
J41_MLB
70
50
04/02/2013
CPU Misc/JTAG/CFG/RSVD
Audio: Speaker Amp
49
J41_MLB
6
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
MASTER
CPU GFX/NCTF/RSVD
5
5
J41_MLB
69
48
K21_MLB
4
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
D
04/02/2013
LPC+SPI Debug Connector
64
47
11/16/2010
& lt; ECODATE & gt;
Sync
61
TABLE_TABLEOFCONTENTS_ITEM
J41_MLB
3
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_HEAD
Contents
46
04/09/2013
& lt; ECO_DESCRIPTION & gt;
Date
Page
MASTER
2
TABLE_TABLEOFCONTENTS_ITEM
(.csa)
Sync
1
1
TABLE_TABLEOFCONTENTS_ITEM
02/06/2013
TABLE_TABLEOFCONTENTS_ITEM
16
15
04/02/2013
PCH GPIO/MISC/LPIO
83
60
J41_MLB
TABLE_TABLEOFCONTENTS_ITEM
02/06/2013
TABLE_TABLEOFCONTENTS_ITEM
18
16
02/06/2013
CPU/PCH Merged XDP
95
61
J41_MLB
TABLE_TABLEOFCONTENTS_ITEM
11/13/2012
C
TABLE_TABLEOFCONTENTS_ITEM
19
17
02/06/2013
Chipset Support
DDR3 VREF MARGINING
62
J41_MLB
J41_MLB
20
18
TABLE_TABLEOFCONTENTS_ITEM
02/15/2013
02/12/2013
20
02/06/2013
LPDDR3 DRAM Channel A (0-31)
21
22
LPDDR3 DRAM Channel B (0-31)
TABLE_TABLEOFCONTENTS_ITEM
23
24
TABLE_TABLEOFCONTENTS_ITEM
02/06/2013
26
Thunderbolt Host (2 of 2)
27
TBT Power Support
28
Thunderbolt Connector A
TABLE_TABLEOFCONTENTS_ITEM
29
Wireless Connector
30
SSD Connector
31
Camera 1 of 2
SD CONTROLLER (GL3219)
J41_MLB
SMC
J41_MLB
SMC Shared Support
J41_MLB
SMC Project Support
J41_MLB
SMBus Connections
J41_MLB
High Side Current Sensing
J41_MLB
Voltage & Load Side Current Sensing
J41_MLB
Debug Sensors 1
J41_MLB
Thermal Sensors
J41_MLB
Fan
07/03/2012
J41_MLB
TABLE_TABLEOFCONTENTS_ITEM
B
10/11/2010
02/07/2013
48
36
J41_MLB
J41_MLB
IPD Connector
35
Reference
09/25/2012
07/01/2011
46
TABLE_TABLEOFCONTENTS_ITEM
CONSTRAINTS
MASTER
External A USB3 Connector
34
Project Specific Constraints
12/07/2012
MASTER
45
TABLE_TABLEOFCONTENTS_ITEM
J41_MLB
121
76
03/20/2013
44
33
TABLE_TABLEOFCONTENTS_ITEM
Project Specific Constraints
09/25/2012
J41_MLB
SD READER CONNECTOR
TABLE_TABLEOFCONTENTS_ITEM
CONSTRAINTS
01/30/2013
119
TABLE_TABLEOFCONTENTS_ITEM
J41_MLB
Camera 2 of 2
SMC Constraints
75
04/02/2013
J41_MLB
09/25/2012
118
TABLE_TABLEOFCONTENTS_ITEM
J41_MLB
40
32
Camera Constraints
74
04/09/2013
39
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
J41_MLB
CONSTRAINTS
117
73
02/06/2013
37
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
J41_MLB
35
TABLE_TABLEOFCONTENTS_ITEM
Thunderbolt Constraints
09/25/2012
116
72
02/07/2013
CONSTRAINTS
115
TABLE_TABLEOFCONTENTS_ITEM
J41_MLB
32
J41_MLB
Memory Constraints
71
02/06/2013
12/14/2012
PCH Constraints 2
114
TABLE_TABLEOFCONTENTS_ITEM
J41_MLB
30
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
70
02/06/2013
11/13/2012
113
69
J41_MLB
29
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
J41_MLB
Thunderbolt Host (1 of 2)
28
25
09/25/2012
112
68
02/06/2013
LPDDR3 DRAM Termination
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
J41_MLB
27
10/24/2012
111
67
02/06/2013
LPDDR3 DRAM Channel B (32-63)
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
J41_MLB
26
09/13/2012
110
66
02/06/2013
02/01/2013
105
TABLE_TABLEOFCONTENTS_ITEM
J41_MLB
25
08/30/2012
104
TABLE_TABLEOFCONTENTS_ITEM
65
02/06/2013
LPDDR3 DRAM Channel A (32-63)
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
J41_MLB
24
01/30/2013
102
64
23
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
63
22
19
TABLE_TABLEOFCONTENTS_ITEM
100
J41_MLB
Project Chipset Support
TABLE_TABLEOFCONTENTS_ITEM
B
1
REV
Page
C
2
3
02/12/2013
TABLE_TABLEOFCONTENTS_ITEM
50
37
02/06/2013
TABLE_TABLEOFCONTENTS_ITEM
51
38
02/06/2013
TABLE_TABLEOFCONTENTS_ITEM
52
39
TABLE_TABLEOFCONTENTS_ITEM
02/06/2013
53
40
TABLE_TABLEOFCONTENTS_ITEM
02/06/2013
54
41
TABLE_TABLEOFCONTENTS_ITEM
03/28/2013
55
42
TABLE_TABLEOFCONTENTS_ITEM
03/28/2013
56
43
TABLE_TABLEOFCONTENTS_ITEM
03/28/2013
58
44
TABLE_TABLEOFCONTENTS_ITEM
02/06/2013
60
45
02/06/2013
TABLE_TABLEOFCONTENTS_ITEM
ALIASES RESOLVED
A
A
DRAWING TITLE
& lt; PART_DESCRIPTION & gt;
Schematic / PCB #’s
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
051-00385
1
SCHEM,MLB,J43A
SCH
1
PCBF,MLB,J43
PCB
CRITICAL
TITLE=MLB
ABBREV=DRAWING
3 11:36:00 2014
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
R
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DRAWING
LAST_MODIFIED=Fri Oct
DRAWING NUMBER
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
CRITICAL
820-00165
BOM OPTION
PRODUCT SAFETY REQUIREMENTS:
PCB, UL RECOGNIZED, MIN. 130-C TEMP. RATING AND V-0 FLAME RATING PER UL 796 & UL 94.
PCB TO BE SILK-SCREENED WITH UL/CUL RECOGNITION MARK, MANUFACTURER’S UL FILE
NUMBER, UL PCB MATERIAL DESIGNATION, 130-C TEMP. RATING AND V-0 FLAME RATING.
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
1 OF 121
SHEET
1 OF 76
1
8
7
6
5
4
3
BOM Groups
1
Alternate Parts
TABLE_BOMGROUP_HEAD
BOM GROUP
2
BOM OPTIONS
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR
PART NUMBER
REF DES
COMMENTS:
376S1032
376S0855
ALL
Toshiba alt for Diodes dual
376S1129
376S0855
ALL
NXP alt for Diodes dual
376S1089
376S1128
ALL
NXP alt for Diodes single
138S0684
138S0660
ALL
Murata alt to Taiyo Yuden
138S0703
138S0648
ALL
Murata alt to Taiyo Yuden
152S0586
152S1301
ALL
Dale/Vishay alt to Cyntec
372S0186
372S0185
ALL
NXP alt to Diodes
197S0479
197S0478
ALL
200uW Epson alt to NDK
376S1053
376S0604
ALL
Diodes alt to Fairchild
371S0713
371S0558
ALL
Diodes alt to ST Micro
TABLE_BOMGROUP_ITEM
MLB_COMMON
ALTERNATE,COMMON,MLB_MISC,MLB_DEBUG:PVT,MLB_PROGPARTS
MLB_MISC
BOM OPTION
PP5V5_DCIN:NO,TBTHV:P15V,EDP,CAM_XTAL:NO,CAM_WAKE:NO,APCLKRQ:ISOL,TPAD_INTWAKE:SHARED,USB_PWR:S3,SD_ON_MLB,VCORE_FETS,SSD_LPSR:S3
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
MLB_DEVEL:ENG
ALTERNATE,BKLT:ENG,XDP_CONN,DDRVREF_DAC,S0PGOOD_ISL,DBGLED,ISNS:ENG
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
MLB_DEVEL:PVT
XDP_CONN
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
MLB_DEBUG:ENG
XDP,SAMCONN
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
MLB_DEBUG:PVT
D
BKLT:PROD,XDP,SAMCONN,ISNS:ENG,DBGLED,XDP_CONN
D
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
MLB_DEBUG:PROD
BKLT:PROD,SAMCONN,XDP,ISNS:PROD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
Current Sensor Configuration
TABLE_ALT_ITEM
CPU DRAM CFG Chart
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
ISNS:ENG
CPU_HS_ISNS:YES,CPUVR_ISNS:YES,DRAM_ISNS:YES,P1V05_ISNS:YES,AIRPORT_ISNS:YES,SSD_ISNS:YES,LCDBKLT_ISNS:YES,P3V3S5_ISNS:YES,3V3S0_ISNS:YES,OTHER_HS_ISNS:YES,CAM_ISNS:YES,CPUDDR_ISNS:YES,PANEL_ISNS:YES
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
VENDOR
CFG 1
CFG 0
0
0
TABLE_ALT_ITEM
128S0371
ISNS:PROD
ALL
Kemet alt to Sanyo
152S1757
ALL
Cyntec alt to NEC
197S0480
197S0343
ALL
NDK crystal alt to TXC
197S0481
197S0343
ALL
Epson crystal alt to TXC
107S0254
HYNIX
CPU_HS_ISNS:YES,CPUVR_ISNS:YES,DRAM_ISNS:YES,P1V05_ISNS:NO,AIRPORT_ISNS:NO,SSD_ISNS:YES,LCDBKLT_ISNS:NO,P3V3S5_ISNS:NO,3V3S0_ISNS:NO,OTHER_HS_ISNS:NO,CAM_ISNS:NO,CPUDDR_ISNS:NO,PANEL_ISNS:NO
128S0376
152S1821
TABLE_BOMGROUP_ITEM
107S0241
ALL
Cyntec sense R alt to TFT
TABLE_ALT_ITEM
SAMSUNG
1
0
MICRON
0
1
ELPIDA
1
1
TABLE_ALT_ITEM
CPU DRAM SPD Straps
TABLE_ALT_ITEM
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
DDR3:HYNIX_4GB
RAMCFG0:L,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:HYNIX_4GB
DDR3:HYNIX_8GB
RAMCFG0:L,RAMCFG1:L,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:HYNIX_8GB
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
353S3452
377S0104
ALL
OnSemi alt to Infineon
128S0220
ALL
Kemet alt to Sanyo
197S0544
ALL
NDK alt to TXC
197S0544
ALL
Epson alt to TXC
138S0681
138S0638
ALL
Taiyo alt to Samsung
138S0841
138S0638
ALL
Murata alt to Samsung
376S00014
376S0761
ALL
Renesas alt to Vishay
152S1876
152S1804
ALL
TDK alt to Toko
107S0240
ALL
Cyntec alt to TFT
107S0250
107S0248
ALL
Cyntec alt to TFT
870-5074
870-1938
ALL
ALT POGO PIN W_O CAP
860-3428
860-1327
ALL
ALT STANDOFF W_O MYLAR
333S0787
333S0677
ALL
ALT STANDOFF W_O MYLAR
860-3690
860-1328
ALL
ALT STANDOFF W_O MYLAR
333S0785
333S0681
ALL
ALT STANDOFF W_O MYLAR
353S3814
353S3812
ALL
ALT TBT PORT MUX
311S00008
311S0271
ALL
ALT AND GATE
311S00007
311S0426
ALL
ALT SNGL BUFFER
311S00015
311S0450
ALL
ALT 2-INPT AND
311S00013
311S0508
ALL
ALT SNGL BUFFER
311S00014
311S0515
ALL
ALT DUAL BUFFER
353S00133
0
1
1
353S2741
ALL
ALT PWR DIST SW
RAMCFG0:H,RAMCFG1:L,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:MICRON_8GB
DDR3:HYNIX_16GB
1
RAMCFG0:L,RAMCFG1:L,RAMCFG2:L,RAMCFG3:H,DRAM_TYPE:HYNIX_16GB
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
C
Kemet alt to Sanyo
128S0398
1
RAMCFG0:H,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:MICRON_4GB
DDR3:MICRON_8GB
0
RSVD
RAMCFG0:H,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:ELPIDA_8GB
DDR3:MICRON_4GB
ALL
107S0255
DDR3:ELPIDA_8GB
128S0325
377S0155
0
16GB
RAMCFG0:H,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:ELPIDA_4GB
0
8GB
RAMCFG0:L,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:SAMSUNG_8GB
DDR3:ELPIDA_4GB
4GB
RAMCFG0:L,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:SAMSUNG_4GB
DDR3:SAMSUNG_8GB
Kemet alt to Sanyo
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
DDR3:SAMSUNG_4GB
Maxim alt to Microchip
ALL
128S0397
CFG 2
ALL
197S0545
CFG 3
128S0284
197S0542
SIZE
353S1286
128S0386
TABLE_BOMGROUP_ITEM
DDR3:SAMSUNG_16GB
RAMCFG0:L,RAMCFG1:H,RAMCFG2:L,RAMCFG3:H,DRAM_TYPE:SAMSUNG_16GB
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
DDR3:ELPIDA_16GB
RAMCFG0:H,RAMCFG1:H,RAMCFG2:L,RAMCFG3:H,DRAM_TYPE:ELPIDA_16GB
DDR3:MICRON_16GB
C
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
RAMCFG0:H,RAMCFG1:L,RAMCFG2:L,RAMCFG3:H,DRAM_TYPE:MICRON_16GB
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
Programmable Parts
TABLE_ALT_ITEM
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
TABLE_ALT_ITEM
335S0915
1
U2890
EEPROM,4MBIT,SPI,50MHZ,1.8V,USON8
CRITICAL
TBTROM:BLANK
TABLE_ALT_ITEM
341S00159
1
T29,EEPROM,FALCON RIDGE(V27.1), PROtO 0,J110/J113
U2890
CRITICAL
TBTROM:PROG
338S1214
1
IC,SMC12-B1,40MHZ/50DMIPS MCU,157BGA
U5000
CRITICAL
SMC:BLANK
335S00006
1
IC,SERIAL FLASH,64 MBIT 3V,WSON,QE=1
U6100
CRITICAL
BOOTROM_MAC:BLANK
335S00007
1
IC,SERIAL FLASH,64 MBIT 3V,WSON,QE=1
U6100
CRITICAL
BOOTROM_NUM:BLANK
341S00153
1
IC,EFI ROM(V0108)), PROTO 0,J110/J113
U6100
CRITICAL
BOOTROM:PROG
DRAM_TYPE:HYNIX_4GB
TABLE_ALT_ITEM
TABLE_ALT_ITEM
DRAM_TYPE:HYNIX_8GB
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
Module Parts
TABLE_ALT_ITEM
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
TABLE_ALT_ITEM
337S00029
BDW,QGH9,D0,1.8,15W,2+2,0.7,4M,B1168
U0500
CRITICAL
CPU:2.1GHZ
337S00073
1
BDW,QGHB,D0,1.6,15W,2+2,0.6,4M,B1168
U0500
CRITICAL
CPU:1.6GHZ
338S00069
1
IC,TBT,FR-2C,288,12x12 ,FC-CSP,TRAY
U2800
CRITICAL
338S1264
1
IC,BCM15700A2KFEB4G,S2 CMRA,8X8,208FCBGA
U3900
CRITICAL
607-6811
1
ASSEMBLY,SUBASSY,PCBA,HALL EFFECT,K99
J6955
CRITICAL
946-5477
B
1
1
UV GLUE,MLB,J41_J43
GLUE
CRITICAL
B
J113_MLB
825-7987
1
LABEL,MLB,J41/J43
NEW_LABEL
376S00036
2
MOSFET,N-CH,30V,52A,5.9M,8P 3.3X3.3 DFN
Q7310,Q7320
CRITICAL
376S00037
2
MOSFET,N-CH,30V,64A,3.5M,8P 3.3X3.3 DFN
Q7311,Q7321
CRITICAL
VCORE_FET:REN
376S1194
2
MOSFET,N-CH,30V,15.3A,12M,8P 3.3X3.3 DFN
Q7310,Q7320
CRITICAL
VCORE_FET:VSHY
MOSFET,N-CH,30V,22A,6.0M,8P 3.3X3.3 DFN
Q7311,Q7321
CRITICAL
VCORE_FET:VSHY
SOLDERPASTE
CRITICAL
376S1193
2
900-0090
1
825-7670
1
LABEL,TEXT,MLB,K21/K78
LABEL
DESCRIPTION
REFERENCE DES
VCORE_FET:REN
DRAM Parts
PART NUMBER
QTY
CRITICAL
BOM OPTION
333S0677
IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA
U2300,U2400,U2500,U2600
CRITICAL
333S0681
A
4
4
IC,SDRAM,16Gb,LPDDR3-1600,178P FBGA
U2300,U2400,U2500,U2600
CRITICAL
DRAM_TYPE:HYNIX_8GB
333S00001
4
IC,SDRAM,23NM,8GB,LPDDR3-1600,178P FBGA
U2300,U2400,U2500,U2600
CRITICAL
DRAM_TYPE:SAMSUNG_4GB
333S00003
4
IC,SDRAM,23NM,16GB,LPDDR3-1600,178P FBGA
U2300,U2400,U2500,U2600
CRITICAL
DRAM_TYPE:SAMSUNG_8GB
DRAM_TYPE:HYNIX_4GB
SYNC_MASTER=J43_MLB
SYNC_DATE=01/17/2013
PAGE TITLE
BOM Configuration
333S0793
4
IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA
U2300,U2400,U2500,U2600
CRITICAL
DRAM_TYPE:ELPIDA_4GB
333S0791
4
IC,SDRAM,16Gb,LPDDR3-1600,178P FBGA
U2300,U2400,U2500,U2600
CRITICAL
DRAM_TYPE:ELPIDA_8GB
DRAWING NUMBER
333S0793
4
IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA
U2300,U2400,U2500,U2600
CRITICAL
DRAM_TYPE:MICRON_4GB
333S0791
4
IC,SDRAM,16GB,LPDDR3-1600,178P FBGA
U2300,U2400,U2500,U2600
CRITICAL
DRAM_TYPE:MICRON_8GB
333S0789
4
IC,SDRAM,25nm,32Gb,LPDDR3-1600,178P FBGA
U2300,U2400,U2500,U2600
CRITICAL
Apple Inc.
DRAM_TYPE:ELPIDA_16GB
8
7
6
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
2 OF 121
SHEET
2 OF 76
1
A
8
7
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1
Alternate Parts
BOM Variants
TABLE_ALT_HEAD
PART NUMBER
BOM NUMBER
BOM NAME
333S0704
BOM OPTIONS
639-00623
PCBA,MLB,BEST,HY-4GB,X430
MLB_CMNPTS,CPU:2.1GHZ,DDR3:HYNIX_4GB,ALTERNATE
ALTERNATE FOR
PART NUMBER
685-00047
TABLE_BOMGROUP_HEAD
BOM OPTION
REF DES
COMMENTS:
685-00048
ALL
Renesas alt to Vishay
333S0700
ALL
Elpida CAM DRAM alt to Hynix
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
639-00624
PCBA,MLB,BEST,HY-8GB,X433
MLB_CMNPTS,CPU:2.1GHZ,DDR3:HYNIX_8GB,ALTERNATE
639-00625
PCBA,MLB,BEST,HY-16GB,X433
MLB_CMNPTS,CPU:2.1GHZ,DDR3:HYNIX_16GB
639-00626
PCBA,MLB,BEST,SM-4GB,X433
MLB_CMNPTS,CPU:2.1GHZ,DDR3:SAMSUNG_4GB,ALTERNATE
639-00627
PCBA,MLB,BEST,SM-8GB,X433
MLB_CMNPTS,CPU:2.1GHZ,DDR3:SAMSUNG_8GB,ALTERNATE
639-00628
PCBA,MLB,BEST,MI-4GB,X433
MLB_CMNPTS,CPU:2.1GHZ,DDR3:MICRON_4GB
639-00629
PCBA,MLB,BEST,MI-8GB,X433
MLB_CMNPTS,CPU:2.1GHZ,DDR3:MICRON_8GB
639-00630
PCBA,MLB,BEST,MI-16GB,X433
MLB_CMNPTS,CPU:2.1GHZ,DDR3:MICRON_16GB
639-00631
PCBA,MLB,BEST,EL-4GB,X433
MLB_CMNPTS,CPU:2.1GHZ,DDR3:ELPIDA_4GB
639-00632
PCBA,MLB,BEST,EL-8GB,X433
MLB_CMNPTS,CPU:2.1GHZ,DDR3:ELPIDA_8GB
639-00633
PCBA,MLB,BETTER,HY-4GB,X433
MLB_CMNPTS,CPU:1.6GHZ,DDR3:HYNIX_4GB,ALTERNATE
639-00634
PCBA,MLB,BETTER,HY-8GB,X433
MLB_CMNPTS,CPU:1.6GHZ,DDR3:HYNIX_8GB,ALTERNATE
639-00635
PCBA,MLB,BETTER,HY-16GB,X433
MLB_CMNPTS,CPU:1.6GHZ,DDR3:HYNIX_16GB
639-00636
PCBA,MLB,BETTER,SM-4GB,X433
MLB_CMNPTS,CPU:1.6GHZ,DDR3:SAMSUNG_4GB,ALTERNATE
639-00637
PCBA,MLB,BETTER,SM-8GB,X433
MLB_CMNPTS,CPU:1.6GHZ,DDR3:SAMSUNG_8GB,ALTERNATE
639-00638
PCBA,MLB,BETTER,MI-4GB,X433
MLB_CMNPTS,CPU:1.6GHZ,DDR3:MICRON_4GB
639-00639
PCBA,MLB,BETTER,MI-8GB,X433
MLB_CMNPTS,CPU:1.6GHZ,DDR3:MICRON_8GB
639-00640
PCBA,MLB,BETTER,MI-16GB,X433
MLB_CMNPTS,CPU:1.6GHZ,DDR3:MICRON_16GB
639-00641
PCBA,MLB,BETTER,EL-4GB,X433
MLB_CMNPTS,CPU:1.6GHZ,DDR3:ELPIDA_4GB
639-00642
PCBA,MLB,BETTER,EL-8GB,X433
MLB_CMNPTS,CPU:1.6GHZ,DDR3:ELPIDA_8GB
685-00046
CMN PTS,PCBA,MLB,X433
MLB_COMMON,J113_MLB
685-00047
VCORE FET,REN,X433
VCORE_FET:REN
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
D
D
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
C
685-00048
VCORE FET,VSHY,X433
VCORE_FET:VSHY
639-00697
PCBA,MLB,BETTER,EL-16GB,X433
MLB_CMNPTS,CPU:1.6GHZ,DDR3:ELPIDA_16GB
C
TABLE_BOMGROUP_ITEM
B
B
Module Parts
PART NUMBER
338S1246
QTY
1
DESCRIPTION
REFERENCE DES
U4500
IC,GL3219,USB3 SD CARD READER,46P,LQFN
CRITICAL
BOM OPTION
CRITICAL
BOM Groups
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
MLB_PROGPARTS
BOOTROM:PROG,SMC:PROG,TBTROM:PROG
TABLE_BOMGROUP_ITEM
Programmable Parts
A
PART NUMBER
341S00148
QTY
1
DESCRIPTION
REFERENCE DES
U5000
IC,SMC-B1,EXT(Vxxxx),PROTO 0,J113
CRITICAL
CRITICAL
BOM OPTION
SYNC_MASTER=MASTER
SYNC_DATE=MASTER
PAGE TITLE
SMC:PROG
BOM Variants
DRAWING NUMBER
Sub-BOMs
Apple Inc.
PART NUMBER
DESCRIPTION
REFERENCE DES
685-00046
1
CMN PTS,PCBA,MLB,J113
CMNPTS
CRITICAL
MLB_CMNPTS
685-00048
1
VCORE FET,VSHY,J113
VCOREFETS
CRITICAL
VCORE_FETS
8
QTY
7
CRITICAL
BOM OPTION
6
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
3 OF 121
SHEET
3 OF 76
1
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8
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PD Module Parts
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
806-5107
CAN,TOPSIDE,ALT,J41/J43
TBTTOPSIDE_2P_FENCE
806-5108
1
CAN,TOPSIDE,COVER,ALT,J41/J43
TBTTOPSIDE_2P_COVER
1
CAN,TBT,J11/J13
TBTFENCE
CRITICAL
806-3215
1
CAN,COVER,TBT,J11/J13
TBTCOVER
CRITICAL
806-3216
1
CAN,MDP,J11/J13
MDPCAN
CRITICAL
806-3083
1
SHLD,USB,MLB,J11/J13
USBCAN
BOM OPTION
CRITICAL
806-3142
D
1
CRITICAL
CRITICAL
D
Plated Board Slot
SL0400
TH-NSP
1
SL-2.3X3.9-2.9X4.5
CPU Heat Sink Mounting Bosses
Z0413
STDOFF-4.5OD1.52H-SM
Can Slots
Z0410
STDOFF-4.5OD1.52H-SM
1
SL0401
TH-NSP
SL-1.1X0.4-1.4X0.7
Z0411
STDOFF-4.5OD1.52H-SM
Z0412
STDOFF-4.5OD1.52H-SM
1
C
SL0402
TH-NSP
1
1
SL0403
TH-NSP
1
1
2x TBT pin diodes
SL-1.1X0.4-1.4X0.7
SL0406
TH-NSP
C
1
1
4x 860-1327
SL-1.1X0.4-1.4X0.7
SL-1.1X0.4-1.4X0.7
Fan Boss
X21 Boss
Z0414
Z0415
STDOFF-4.5OD1.8H-SM
STDOFF-4.5OD1.9H-SM
SL0405
TH-NSP
SSD Boss
Z0405
2x MDP Connector
SL0407
TH-NSP
STDOFF-4.5OD1.9H-SM
1
1
860-1327
SL-1.1X0.45-1.4X0.75
860-1327
1
SL-1.1X0.45-1.4X0.75
2x TBT chip
1
860-1327
1
SL0404
TH-NSP
SL0408
TH-NSP
1
1
2x USB Connector
SL-1.1X0.4-1.4X0.7
SL-1.1X0.4-1.4X0.7
EMI I/O Pogo Pins
DisplayPort Pogo
USB/SD Card Pogo
CRITICAL
CRITICAL
ZS0405
ZS0406
POGO-2.0OD-3.6H-K86-K87
POGO-2.0OD-3.6H-K86-K87
SM
SM
1
1
870-1938
870-1938
B
B
A
SYNC_MASTER=MASTER
SYNC_DATE=MASTER
PAGE TITLE
PD PARTS
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
4 OF 121
SHEET
4 OF 76
1
A
8
7
6
5
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3
2
1
CRITICAL
OMIT_TABLE
U0500
BROADWELL-ULT
2C+GT2
BGA
SYM 1 OF 19
DDI Port Assignments:
OUT
67 25
D
OUT
67 25
OUT
67 25
OUT
67 25
OUT
67 25
TBT Sink 0
OUT
67 25
OUT
67 25
OUT
67 25 18
67 25 18
OUT
67 25 18
OUT
67 25 18
TBT Sink 1
(MUXed with HDMI
if necessary)
OUT
OUT
67 25 18
OUT
67 25 18
OUT
67 25 18
OUT
67 25 18
OUT
DP_TBTSNK0_ML_C_N & lt; 0 & gt;
DP_TBTSNK0_ML_C_P & lt; 0 & gt;
DP_TBTSNK0_ML_C_N & lt; 1 & gt;
DP_TBTSNK0_ML_C_P & lt; 1 & gt;
DP_TBTSNK0_ML_C_N & lt; 2 & gt;
DP_TBTSNK0_ML_C_P & lt; 2 & gt;
DP_TBTSNK0_ML_C_N & lt; 3 & gt;
DP_TBTSNK0_ML_C_P & lt; 3 & gt;
C54
C55
B58
C58
B55
A55
A57
B57
DP_TBTSNK1_ML_C_N & lt; 0 & gt;
DP_TBTSNK1_ML_C_P & lt; 0 & gt;
DP_TBTSNK1_ML_C_N & lt; 1 & gt;
DP_TBTSNK1_ML_C_P & lt; 1 & gt;
DP_TBTSNK1_ML_C_N & lt; 2 & gt;
DP_TBTSNK1_ML_C_P & lt; 2 & gt;
DP_TBTSNK1_ML_C_N & lt; 3 & gt;
DP_TBTSNK1_ML_C_P & lt; 3 & gt;
C51
C50
C53
B54
C49
B50
A53
B53
eDP Port Assignment:
EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1
DDI1_TXN0
DDI1_TXP0
DDI1_TXN1
DDI1_TXP1
DDI1_TXN2
DDI1_TXP2
DDI1_TXN3
DDI1_TXP3
DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3
C45
B46
A47
B47
DP_INT_ML_C_N & lt; 0 & gt;
DP_INT_ML_C_P & lt; 0 & gt;
NC_INT_ML_CN & lt; 1 & gt;
NC_INT_ML_CP & lt; 1 & gt;
EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3
DDI
EDP
67 25
C47
C46
A49
B49
NC_INT_ML_CN & lt; 2 & gt;
NC_INT_ML_CP & lt; 2 & gt;
NC_INT_ML_CN & lt; 3 & gt;
NC_INT_ML_CP & lt; 3 & gt;
EDP_AUXN
EDP_AUXP
OUT
60 67
OUT
60 67
OUT
64
OUT
64
OUT
64
OUT
64
OUT
64
OUT
64
D
Internal panel
PPVCOMP_S0_CPU
1
A45
B45
DP_INT_AUXCH_C_N
DP_INT_AUXCH_C_P
BI
60 67
BI
60 67
D20
A43
R0530
24.9
2
EDP_RCOMP
EDP_DISP_UTIL
8
1%
1/20W
MF
201
MCP_EDP_RCOMP
TP_EDP_DISP_UTIL
MCP Daisy-Chain Strategy:
CRITICAL
OMIT_TABLE
Each corner of CPU has two testpoints.
Other corner test signals connected in
daisy-chain fashion. Continuity should
exist between both TP’s on each corner.
U0500
C
BROADWELL-ULT
2C+GT2
NO_TEST
5
5
TP0531
TP
1
TP-P6
5
5
TP0501
TP
1
TP-P6
5
5
MCP_DC_AW2_AY2
MCP_DC_AW3_AY3
MCP_DC_AY60
MCP_DC_AW61_AY61
MCP_DC_AW62_AY62
MCP_DC_B2
MCP_DC_A3_B3
MCP_DC_A61_B61
MCP_DC_B62_B63
MCP_DC_C1_C2
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
AY2
AY3
AY60
AY61
AY62
B2
B3
B61
B62
B63
C1
C2
BGA
SYM 17 OF 19
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
C
NO_TEST
A3
A4
A60
A61
A62
AV1
AW1
AW2
AW3
AW61
AW62
AW63
TRUE
MCP_DC_A3_B3
MCP_DC_A4
5
1
TP
TP-P6
TRUE
TRUE
TRUE
TRUE
TRUE
MCP_DC_A60
MCP_DC_A61_B61
MCP_DC_A62
MCP_DC_AV1
MCP_DC_AW1
MCP_DC_AW2_AY2
MCP_DC_AW3_AY3
MCP_DC_AW61_AY61
MCP_DC_AW62_AY62
MCP_DC_AW63
1
5
TP
TP-P6
1
TP
TP-P6
1
TP
TP-P6
1
5
TP
TP-P6
TP0500
TP0510
TP0511
TP0520
TP0521
5
5
5
1
TP
TP-P6
TP0530
CRITICAL
OMIT_TABLE
U0500
B
B
BROADWELL-ULT
2C+GT2
AT2
NC
AU44
NC
AV44
NC
D15
NC
NC
NC
NC
F22
H22
J21
BGA
SYM 18 OF 19
RSVD
SPARE
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
N23
R23
T23
U10
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
AL1
AM11
AP7
AU10
AU15
AW14
AY14
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A
SYNC_MASTER=WILL_J43
SYNC_DATE=09/13/2012
PAGE TITLE
CPU GFX/NCTF/RSVD
DRAWING NUMBER
Apple Inc.
& lt; SCH_NUM & gt;
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
5 OF 121
SHEET
5 OF 76
1
SIZE
D
A
8
7
6
5
4
3
2
1
CRITICAL
OMIT_TABLE
U0500
D
D
BROADWELL-ULT
2C+GT2
PP1V05_S0
NC
BI
CPU_CATERR_L
67 38
BI
CPU_PECI
N62
CPU_PROCHOT_R_L
K63
R0611
2
CATERR*
PECI
1
5%
1/20W
MF
201
(IPU)
C61
PROCHOT*
67
CPU_PWRGD
CPU_SM_RCOMP & lt; 0 & gt;
CPU_SM_RCOMP & lt; 1 & gt;
CPU_SM_RCOMP & lt; 2 & gt;
AU60
AV60
AU61
TP_CPU_MEM_RESET_L
AV15
SM_DRAMRST*
67
R0650
R0651
1
R0652
1
R0620
200
121
100
1%
1/20W
MF
201
1%
1/20W
MF
201
5%
1/20W
MF
201
18
OUT
PROCPWRGD
2
2
2
PROC_TCK E60
PROC_TMS E61
PROC_TRST* E59
PROC_TDI F63
PROC_TDO F62
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
10K
1%
1/20W
MF
201
1
(IPU)
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
67
(IPU)
17
OUT
CPU_MEMVTT_PWR_EN_LSVDDQ
AV61
PRDY* J62
PREQ* K62
XDP_CPU_PRDY_L
XDP_CPU_PREQ_L
16 64 67
IN
16 64 67
IN
16 64 67
IN
16 64 67
IN
12 16 64 67
IN
16 64 67
OUT
XDP_CPU_TCK
XDP_CPU_TMS
XDP_CPUPCH_TRST_L
OUT
16 64 67
THERMAL
67
1
(IPD)
(IPU)
56
CPU_PROCHOT_L
(IPU)
PWR
JTAG
67 51 38 37
OUT
K61
MISC
67 37
62
2
PROC_DETECT*
(IPU)
R0610 1
5%
1/20W
MF
201
D61
BGA
SYM 2 OF 19
DDR3
58 55 51 42 38 17 16 15 11 8
64 62 59
SM_PG_CNTL1
(IPU)
(IPU)
2
BPM0*
BPM1*
BPM2*
BPM3*
BPM4*
BPM5*
BPM6*
BPM7*
J60
H60
H61
H62
K59
H63
K60
J61
XDP_CPU_TDI
XDP_CPU_TDO
XDP_BPM_L & lt; 0 & gt;
XDP_BPM_L & lt; 1 & gt;
XDP_BPM_L & lt; 2 & gt;
XDP_BPM_L & lt; 3 & gt;
XDP_BPM_L & lt; 4 & gt;
XDP_BPM_L & lt; 5 & gt;
XDP_BPM_L & lt; 6 & gt;
XDP_BPM_L & lt; 7 & gt;
BI
16 67
BI
16 67
BI
16 67
BI
16 67
BI
16 67
BI
16 67
BI
16 67
BI
16 67
PLACE_NEAR=U0500.AU60:12.7mm
PLACE_NEAR=U0500.AV60:12.7mm
PLACE_NEAR=U0500.AU61:12.7mm
PLACE_NEAR=U0500.C61:12.7mm
C
C
CRITICAL
OMIT_TABLE
U0500
BROADWELL-ULT
2C+GT2
67 16 6
67 16 6
BI
67 16
BI
67 16
BI
67 16
BI
67 16
BI
67 16
BI
16
BI
16
BI
16
BI
16
BI
AC60
AC62
AC63
AA63
AA60
Y62
Y61
Y60
V62
V61
V60
U60
T63
T62
T61
T60
CFG0 (IPU)
CFG1 (IPU)
CFG2 (IPU)
CFG3 (IPU)
CFG4 (IPU)
CFG5 (IPU)
CFG6 (IPU)
CFG7 (IPU)
CFG8 (IPU)
CFG9 (IPU)
CFG10 (IPU)
CFG11 (IPU)
CFG12 (IPU)
CFG13 (IPU)
CFG14 (IPU)
CFG15 (IPU)
CPU_CFG & lt; 16 & gt;
CPU_CFG & lt; 18 & gt;
CPU_CFG & lt; 17 & gt;
CPU_CFG & lt; 19 & gt;
BI
67 16 6
POWER FEATURES NOT ACTIVE
VR DOES NOT SUPPORT SVID
NOA ALWAYS UNLOCKED
ENABLED
PCH-LESS MODE
STALL AFTER PCU PLL LOCK
BI
67 16 6
=
=
=
=
=
=
BI
67 16 6
0
0
0
0
0
0
BI
67 16
NORMAL OPERATION
VR SUPPORTS SVID
NORMAL OPERATION
DISABLED
NORMAL OPERATION
NORMAL OPERATION
BI
67 16
=
=
=
=
=
=
BI
67 16
1
1
1
1
1
1
BI
67 16 6
CFG & lt; 10 & gt; :SAFE MODE BOOT
CFG & lt; 9 & gt; :NO SVID-CAPABLE VR
CFG & lt; 8 & gt; :ALLOW NOA ON LOCKED UNITS
CFG & lt; 4 & gt; :eDP ENABLE/DISABLE
CFG & lt; 1 & gt; :PCH-LESS MODE
CFG & lt; 0 & gt; :RESET SEQUENCE STALL
BI
67 64 16
B
BI
67 16
CPU_CFG & lt; 0 & gt;
CPU_CFG & lt; 1 & gt;
CPU_CFG & lt; 2 & gt;
CPU_CFG & lt; 3 & gt;
CPU_CFG & lt; 4 & gt;
CPU_CFG & lt; 5 & gt;
CPU_CFG & lt; 6 & gt;
CPU_CFG & lt; 7 & gt;
CPU_CFG & lt; 8 & gt;
CPU_CFG & lt; 9 & gt;
CPU_CFG & lt; 10 & gt;
CPU_CFG & lt; 11 & gt;
CPU_CFG & lt; 12 & gt;
CPU_CFG & lt; 13 & gt;
CPU_CFG & lt; 14 & gt;
CPU_CFG & lt; 15 & gt;
BI
AA62
U63
AA61
U62
CFG16
CFG18
CFG17
CFG19
NC
These can be placed close to J1800
and are only for debug access
CPU_CFG & lt; 10 & gt;
CPU_CFG & lt; 9 & gt;
CPU_CFG & lt; 8 & gt;
CPU_CFG & lt; 1 & gt;
CPU_CFG & lt; 0 & gt;
NOSTUFF
HSW_PRE_ES2
R0640 1
1
1K
A
5%
1/20W
MF
201
NOSTUFF
R0638 1
R0639
1K
2
2
NOSTUFF
1
1K
5%
1/20W
MF
201
5%
1/20W
MF
201
R0631
2
NC
NC
NC
NC
6 16 67
6 16 67
6 16 67
PCH_TD_IREF
6 16 67
R0680
1%
1/20W
MF
201
1K
5%
1/20W
MF
201
2
1
1
49.9
R0630
5%
1/20W
MF
201
A5
E1
D1
J20
H18
B12
RSVD_TP AV63
RSVD_TP AU63
TP_MCP_RSVD_AV63
TP_MCP_RSVD_AU63
RSVD_TP C63
RSVD_TP C62
TP_MCP_RSVD_C63
TP_MCP_RSVD_C62
RSVD_B43 B43
NC
RSVD_TP A51
RSVD_TP B51
TP_MCP_RSVD_A51
TP_MCP_RSVD_B51
RSVD_TP L60
TP_MCP_RSVD_L60
RSVD N60
NC
NC
(IPU)
(IPU)
B
NC
RSVD W23
RSVD Y22
PROC_OPI_COMP AY15
CPU_OPI_RCOMP
(IPU)
(IPU)
RSVD AV62
RSVD D58
CFG_RCOMP
RSVD
1
NC
NC
RSVD
RSVD
RSVD
RSVD
TD_IREF
RSVD P20
RSVD R20
R0690
49.9
VSS P22
VSS N21
6 16 67
NOSTUFF
1
1K
2
V63
CPU_CFG_RCOMP
BGA
SYM 19 OF 19
RESERVED
2
1%
1/20W
MF
201
NC
NC
R0685
8.25K
2
2
1%
1/20W
MF
201
SYNC_MASTER=WILL_J43
SYNC_DATE=09/13/2012
PAGE TITLE
NOTE: Pre-ES2 CPUs have issue with Sx cycling, must set CFG & lt; 9 & gt; low to avoid
issue, but this locks CPU VR at 1.7V Vboot (CPU Sighting #4391569).
CPU Misc/JTAG/CFG/RSVD
DRAWING NUMBER
CPU_CFG & lt; 4 & gt;
6 16 67
Apple Inc.
EDP
1
R
& lt; E4LABEL & gt;
R0634
NOTICE OF PROPRIETARY PROPERTY:
1K
2
& lt; SCH_NUM & gt;
REVISION
5%
1/20W
MF
201
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
BRANCH
& lt; BRANCH & gt;
PAGE
6 OF 121
SHEET
6 OF 76
1
SIZE
D
A
8
7
6
5
4
3
CRITICAL
OMIT_TABLE
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
D
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
C
BI
70 63 21
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
B
BI
70 63
BI
AH63
AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57
AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54
AL55
AK55
AR54
AN54
AY58
AW58
AY56
AW56
AV58
AU58
AV56
AU56
AY54
AW54
AY52
AW52
AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51
MEM_A_DQ & lt; 0 & gt;
MEM_A_DQ & lt; 1 & gt;
MEM_A_DQ & lt; 2 & gt;
MEM_A_DQ & lt; 3 & gt;
MEM_A_DQ & lt; 4 & gt;
MEM_A_DQ & lt; 5 & gt;
MEM_A_DQ & lt; 6 & gt;
MEM_A_DQ & lt; 7 & gt;
MEM_A_DQ & lt; 8 & gt;
MEM_A_DQ & lt; 9 & gt;
MEM_A_DQ & lt; 10 & gt;
MEM_A_DQ & lt; 11 & gt;
MEM_A_DQ & lt; 12 & gt;
MEM_A_DQ & lt; 13 & gt;
MEM_A_DQ & lt; 14 & gt;
MEM_A_DQ & lt; 15 & gt;
MEM_A_DQ & lt; 16 & gt;
MEM_A_DQ & lt; 17 & gt;
MEM_A_DQ & lt; 18 & gt;
MEM_A_DQ & lt; 19 & gt;
MEM_A_DQ & lt; 20 & gt;
MEM_A_DQ & lt; 21 & gt;
MEM_A_DQ & lt; 22 & gt;
MEM_A_DQ & lt; 23 & gt;
MEM_A_DQ & lt; 24 & gt;
MEM_A_DQ & lt; 25 & gt;
MEM_A_DQ & lt; 26 & gt;
MEM_A_DQ & lt; 27 & gt;
MEM_A_DQ & lt; 28 & gt;
MEM_A_DQ & lt; 29 & gt;
MEM_A_DQ & lt; 30 & gt;
MEM_A_DQ & lt; 31 & gt;
MEM_A_DQ & lt; 32 & gt;
MEM_A_DQ & lt; 33 & gt;
MEM_A_DQ & lt; 34 & gt;
MEM_A_DQ & lt; 35 & gt;
MEM_A_DQ & lt; 36 & gt;
MEM_A_DQ & lt; 37 & gt;
MEM_A_DQ & lt; 38 & gt;
MEM_A_DQ & lt; 39 & gt;
MEM_A_DQ & lt; 40 & gt;
MEM_A_DQ & lt; 41 & gt;
MEM_A_DQ & lt; 42 & gt;
MEM_A_DQ & lt; 43 & gt;
MEM_A_DQ & lt; 44 & gt;
MEM_A_DQ & lt; 45 & gt;
MEM_A_DQ & lt; 46 & gt;
MEM_A_DQ & lt; 47 & gt;
MEM_A_DQ & lt; 48 & gt;
MEM_A_DQ & lt; 49 & gt;
MEM_A_DQ & lt; 50 & gt;
MEM_A_DQ & lt; 51 & gt;
MEM_A_DQ & lt; 52 & gt;
MEM_A_DQ & lt; 53 & gt;
MEM_A_DQ & lt; 54 & gt;
MEM_A_DQ & lt; 55 & gt;
MEM_A_DQ & lt; 56 & gt;
MEM_A_DQ & lt; 57 & gt;
MEM_A_DQ & lt; 58 & gt;
MEM_A_DQ & lt; 59 & gt;
MEM_A_DQ & lt; 60 & gt;
MEM_A_DQ & lt; 61 & gt;
MEM_A_DQ & lt; 62 & gt;
MEM_A_DQ & lt; 63 & gt;
U0500
SA_DQ0
SA_CLK0*
BROADWELL-ULT
SA_DQ1
SA_CLK0
2C+GT2
BGA
SA_DQ2
SA_CLK1*
SYM 3 OF 19
SA_DQ3
SA_CLK1
SA_DQ4
SA_DQ5
SA_CKE0
SA_DQ6
SA_CKE1
SA_DQ7
SA_CKE2
SA_DQ8
SA_CKE3
SA_DQ9
SA_DQ10
SA_CS0*
SA_DQ11
SA_CS1*
SA_DQ12
SA_DQ13
SA_ODT0
SA_DQ14
LPDDR3
SA_DQ15
CAB3 SA_RAS*
SA_DQ16
CAB2
SA_WE*
SA_DQ17
CAB1 SA_CAS*
SA_DQ18
SA_DQ19
CAB4
SA_BA0
SA_DQ20
CAB6
SA_BA1
SA_DQ21
CAA5
SA_BA2
SA_DQ22
SA_DQ23
CAB9
SA_MA0
SA_DQ24
CAB8
SA_MA1
SA_DQ25
SA_MA2
CAB5
SA_DQ26
RSVD1
SA_MA3
SA_DQ27
SA_MA4
RSVD2
SA_DQ28
CAA0
SA_MA5
SA_DQ29
SA_MA6
CAA2
SA_DQ30
SA_MA7
CAA4
SA_DQ31
CAA3
SA_MA8
SA_DQ32
CAA1
SA_MA9
SA_DQ33
CAB7 SA_MA10
SA_DQ34
CAA7 SA_MA11
SA_DQ35
CAA6 SA_MA12
SA_DQ36
CAB0 SA_MA13
SA_DQ37
CAA9 SA_MA14
SA_DQ38
CAA8 SA_MA15
SA_DQ39
SA_DQ40
SA_DQSN0
SA_DQ41
SA_DQSN1
SA_DQ42
SA_DQSN2
SA_DQ43
SA_DQSN3
SA_DQ44
SA_DQSN4
SA_DQ45
SA_DQSN5
SA_DQ46
SA_DQSN6
SA_DQ47
SA_DQSN7
SA_DQ48
SA_DQ49
SA_DQSP0
SA_DQ50
SA_DQSP1
SA_DQ51
SA_DQSP2
SA_DQ52
SA_DQSP3
SA_DQ53
SA_DQSP4
SA_DQ54
SA_DQSP5
SA_DQ55
SA_DQSP6
SA_DQ56
SA_DQSP7
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SM_VREF_CA
SA_DQ61
SM_VREF_DQ0
SA_DQ62
SA_DQ63
SM_VREF_DQ1
AU37
AV37
AW36
AY36
MEM_A_CLK_N & lt; 0 & gt;
MEM_A_CLK_P & lt; 0 & gt;
MEM_A_CLK_N & lt; 1 & gt;
MEM_A_CLK_P & lt; 1 & gt;
MEM_A_CKE & lt; 0 & gt;
MEM_A_CKE & lt; 1 & gt;
MEM_A_CKE & lt; 2 & gt;
MEM_A_CKE & lt; 3 & gt;
AP33
AR32
MEM_A_CS_L & lt; 0 & gt;
MEM_A_CS_L & lt; 1 & gt;
20 24 70
70 63
BI
OUT
20 24 70
70 63
BI
OUT
21 24 70
70 63
BI
OUT
21 24 70
70 63
BI
70 63
AU43
AW43
AY42
AY43
OUT
BI
AY34
AW34
AU34
=MEM_A_RAS_L
=MEM_A_WE_L
=MEM_A_CAS_L
70 63
BI
20 24 70
70 63
BI
OUT
21 24 70
70 63
BI
OUT
21 24 70
70 63
BI
BI
OUT
20 21 24 70
70 63
BI
OUT
20 21 24 70
70 63
BI
70 63
MEM_A_ODT & lt; 0 & gt;
20 24 70
OUT
70 63
AP32
OUT
BI
OUT
20 21 24 63 70
OUT
63
OUT
OUT
BI
70 63
BI
63
70 63
BI
63
70 63
BI
70 63
=MEM_A_BA & lt; 0 & gt;
MEM_A_CAB & lt; 6 & gt;
=MEM_A_BA & lt; 2 & gt;
BI
70 63
AU35
AV35
AY41
70 63
BI
=MEM_A_A & lt; 0 & gt;
=MEM_A_A & lt; 1 & gt;
=MEM_A_A & lt; 2 & gt;
TP_LPDDR3_RSVD1
TP_LPDDR3_RSVD2
=MEM_A_A & lt; 5 & gt;
=MEM_A_A & lt; 6 & gt;
=MEM_A_A & lt; 7 & gt;
=MEM_A_A & lt; 8 & gt;
=MEM_A_A & lt; 9 & gt;
=MEM_A_A & lt; 10 & gt;
=MEM_A_A & lt; 11 & gt;
MEM_A_CAA & lt; 6 & gt;
=MEM_A_A & lt; 13 & gt;
=MEM_A_A & lt; 14 & gt;
=MEM_A_A & lt; 15 & gt;
63
70 63
BI
OUT
21 24 63 70
70 63
BI
OUT
63
70 63
BI
70 63
AU36
AY37
AR38
AP36
AU39
AR36
AV40
AW39
AY39
AU40
AP35
AW41
AU41
AR35
AV42
AU42
OUT
BI
MEM_A_DQS_N & lt; 0 & gt;
MEM_A_DQS_N & lt; 1 & gt;
MEM_A_DQS_N & lt; 2 & gt;
MEM_A_DQS_N & lt; 3 & gt;
MEM_A_DQS_N & lt; 4 & gt;
MEM_A_DQS_N & lt; 5 & gt;
MEM_A_DQS_N & lt; 6 & gt;
MEM_A_DQS_N & lt; 7 & gt;
AJ62
AN61
AN58
AN55
AW57
AW53
AL42
AL49
MEM_A_DQS_P & lt; 0 & gt;
MEM_A_DQS_P & lt; 1 & gt;
MEM_A_DQS_P & lt; 2 & gt;
MEM_A_DQS_P & lt; 3 & gt;
MEM_A_DQS_P & lt; 4 & gt;
MEM_A_DQS_P & lt; 5 & gt;
MEM_A_DQS_P & lt; 6 & gt;
MEM_A_DQS_P & lt; 7 & gt;
63
70 63
BI
OUT
63
70 63
BI
OUT
63
70 63
BI
OUT
63
70 63
BI
OUT
63
70 63
BI
OUT
63
70 63
BI
OUT
63
70 63
BI
OUT
63
70 63
BI
OUT
63
70 63
BI
OUT
63
70 63 23
BI
OUT
63
70 63
BI
OUT
63
70 63
BI
OUT
20 24 63 70
70 63
BI
OUT
63
70 63
BI
OUT
63
70 63
BI
OUT
63
70 63
BI
70 63
AJ61
AN62
AM58
AM55
AV57
AV53
AL43
AL48
OUT
BI
AP51
CPU_DIMMB_VREFDQ
BI
63 70
70 63
BI
BI
63 70
70 63
BI
BI
63 70
70 63
BI
BI
63 70
70 63
BI
BI
63 70
70 63
BI
BI
21 63 70
70 63
BI
BI
63 70
70 63
BI
BI
BI
63 70
70 63
BI
BI
63 70
70 63
BI
BI
63 70
70 63
BI
BI
63 70
70 63
BI
BI
63 70
70 63
BI
BI
63 70
70 63
BI
BI
21 63 70
70 63
BI
BI
63 70
70 63
BI
BI
BI
70 63
CPU_DIMMA_VREFDQ
BI
70 63
AR51
70 63
70 63
CPU_DIMM_VREFCA
63 70
70 63
AP49
BI
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
OUT
OUT
OUT
19
19
19
MEM_B_DQ & lt; 0 & gt;
MEM_B_DQ & lt; 1 & gt;
MEM_B_DQ & lt; 2 & gt;
MEM_B_DQ & lt; 3 & gt;
MEM_B_DQ & lt; 4 & gt;
MEM_B_DQ & lt; 5 & gt;
MEM_B_DQ & lt; 6 & gt;
MEM_B_DQ & lt; 7 & gt;
MEM_B_DQ & lt; 8 & gt;
MEM_B_DQ & lt; 9 & gt;
MEM_B_DQ & lt; 10 & gt;
MEM_B_DQ & lt; 11 & gt;
MEM_B_DQ & lt; 12 & gt;
MEM_B_DQ & lt; 13 & gt;
MEM_B_DQ & lt; 14 & gt;
MEM_B_DQ & lt; 15 & gt;
MEM_B_DQ & lt; 16 & gt;
MEM_B_DQ & lt; 17 & gt;
MEM_B_DQ & lt; 18 & gt;
MEM_B_DQ & lt; 19 & gt;
MEM_B_DQ & lt; 20 & gt;
MEM_B_DQ & lt; 21 & gt;
MEM_B_DQ & lt; 22 & gt;
MEM_B_DQ & lt; 23 & gt;
MEM_B_DQ & lt; 24 & gt;
MEM_B_DQ & lt; 25 & gt;
MEM_B_DQ & lt; 26 & gt;
MEM_B_DQ & lt; 27 & gt;
MEM_B_DQ & lt; 28 & gt;
MEM_B_DQ & lt; 29 & gt;
MEM_B_DQ & lt; 30 & gt;
MEM_B_DQ & lt; 31 & gt;
MEM_B_DQ & lt; 32 & gt;
MEM_B_DQ & lt; 33 & gt;
MEM_B_DQ & lt; 34 & gt;
MEM_B_DQ & lt; 35 & gt;
MEM_B_DQ & lt; 36 & gt;
MEM_B_DQ & lt; 37 & gt;
MEM_B_DQ & lt; 38 & gt;
MEM_B_DQ & lt; 39 & gt;
MEM_B_DQ & lt; 40 & gt;
MEM_B_DQ & lt; 41 & gt;
MEM_B_DQ & lt; 42 & gt;
MEM_B_DQ & lt; 43 & gt;
MEM_B_DQ & lt; 44 & gt;
MEM_B_DQ & lt; 45 & gt;
MEM_B_DQ & lt; 46 & gt;
MEM_B_DQ & lt; 47 & gt;
MEM_B_DQ & lt; 48 & gt;
MEM_B_DQ & lt; 49 & gt;
MEM_B_DQ & lt; 50 & gt;
MEM_B_DQ & lt; 51 & gt;
MEM_B_DQ & lt; 52 & gt;
MEM_B_DQ & lt; 53 & gt;
MEM_B_DQ & lt; 54 & gt;
MEM_B_DQ & lt; 55 & gt;
MEM_B_DQ & lt; 56 & gt;
MEM_B_DQ & lt; 57 & gt;
MEM_B_DQ & lt; 58 & gt;
MEM_B_DQ & lt; 59 & gt;
MEM_B_DQ & lt; 60 & gt;
MEM_B_DQ & lt; 61 & gt;
MEM_B_DQ & lt; 62 & gt;
MEM_B_DQ & lt; 63 & gt;
AY31
AW31
AY29
AW29
AV31
AU31
AV29
AU29
AY27
AW27
AY25
AW25
AV27
AU27
AV25
AU25
AM29
AK29
AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AK25
AL25
AY23
AW23
AY21
AW21
AV23
AU23
AV21
AU21
AY19
AW19
AY17
AW17
AV19
AU19
AV17
AU17
AR21
AR22
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18
AL18
AK20
AM20
AR18
AP18
U0500
SB_DQ0
SB_CK0*
BROADWELL-ULT
SB_DQ1
SB_CK0
2C+GT2
BGA
SB_DQ2
SB_CK1*
SYM 4 OF 19
SB_DQ3
SB_CK1
SB_DQ4
SB_DQ5
SB_CKE0
SB_DQ6
SB_CKE1
SB_DQ7
SB_CKE2
SB_DQ8
SB_CKE3
SB_DQ9
SB_DQ10
SB_CS0*
SB_DQ11
SB_CS1*
SB_DQ12
SB_DQ13
SB_ODT0
SB_DQ14
LPDDR3
SB_DQ15
CAB3 SB_RAS*
SB_DQ16
CAB2
SB_WE*
SB_DQ17
CAB1 SB_CAS*
SB_DQ18
SB_DQ19
SB_BA0
CAB4
SB_DQ20
CAB6
SB_BA1
SB_DQ21
CAA5
SB_BA2
SB_DQ22
SB_DQ23
CAB9
SB_MA0
SB_DQ24
CAB8
SB_MA1
SB_DQ25
SB_MA2
CAB5
SB_DQ26
RSVD3
SB_MA3
SB_DQ27
SB_MA4
RSVD4
SB_DQ28
CAA0
SB_MA5
SB_DQ29
SB_MA6
CAA2
SB_DQ30
SB_MA7
CAA4
SB_DQ31
CAA3
SB_MA8
SB_DQ32
CAA1
SB_MA9
SB_DQ33
CAB7 SB_MA10
SB_DQ34
CAA7 SB_MA11
SB_DQ35
CAA6 SB_MA12
SB_DQ36
CAB0 SB_MA13
SB_DQ37
CAA9 SB_MA14
SB_DQ38
CAA8 SB_MA15
SB_DQ39
SB_DQ40
SB_DQSN0
SB_DQ41
SB_DQSN1
SB_DQ42
SB_DQSN2
SB_DQ43
SB_DQSN3
SB_DQ44
SB_DQSN4
SB_DQ45
SB_DQSN5
SB_DQ46
SB_DQSN6
SB_DQ47
SB_DQSN7
SB_DQ48
SB_DQ49
SB_DQSP0
SB_DQ50
SB_DQSP1
SB_DQ51
SB_DQSP2
SB_DQ52
SB_DQSP3
SB_DQ53
SB_DQSP4
SB_DQ54
SB_DQSP5
SB_DQ55
SB_DQSP6
SB_DQ56
SB_DQSP7
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
MEMORY CHANNEL B
BI
70 63
1
CRITICAL
OMIT_TABLE
MEMORY CHANNEL A
70 63
2
A
AM38
AN38
AK38
AL38
MEM_B_CLK_N & lt; 0 & gt;
MEM_B_CLK_P & lt; 0 & gt;
MEM_B_CLK_N & lt; 1 & gt;
MEM_B_CLK_P & lt; 1 & gt;
AY49
AU50
AW49
AV50
MEM_B_CKE & lt; 0 & gt;
MEM_B_CKE & lt; 1 & gt;
MEM_B_CKE & lt; 2 & gt;
MEM_B_CKE & lt; 3 & gt;
AM32
AK32
OUT
22 24 70
OUT
22 24 70
OUT
23 24 70
OUT
23 24 70
OUT
22 24 70
OUT
22 24 70
OUT
23 24 70
OUT
23 24 70
MEM_B_CS_L & lt; 0 & gt;
MEM_B_CS_L & lt; 1 & gt;
OUT
22 23 24 70
OUT
22 23 24 70
AL32
MEM_B_ODT & lt; 0 & gt;
OUT
22 23 24 63 70
AM35
AK35
AM33
=MEM_B_RAS_L
=MEM_B_WE_L
=MEM_B_CAS_L
OUT
63
OUT
63
OUT
63
AL35
AM36
AU49
=MEM_B_BA & lt; 0 & gt;
MEM_B_CAB & lt; 6 & gt;
=MEM_B_BA & lt; 2 & gt;
OUT
63
OUT
23 24 63 70
OUT
63
AP40
AR40
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AK36
AV47
AU47
AK33
AR46
AP46
=MEM_B_A & lt; 0 & gt;
=MEM_B_A & lt; 1 & gt;
=MEM_B_A & lt; 2 & gt;
TP_LPDDR3_RSVD3
TP_LPDDR3_RSVD4
=MEM_B_A & lt; 5 & gt;
=MEM_B_A & lt; 6 & gt;
=MEM_B_A & lt; 7 & gt;
=MEM_B_A & lt; 8 & gt;
=MEM_B_A & lt; 9 & gt;
=MEM_B_A & lt; 10 & gt;
=MEM_B_A & lt; 11 & gt;
MEM_B_CAA & lt; 6 & gt;
=MEM_B_A & lt; 13 & gt;
=MEM_B_A & lt; 14 & gt;
=MEM_B_A & lt; 15 & gt;
OUT
63
OUT
63
OUT
63
OUT
63
OUT
63
OUT
63
OUT
63
OUT
63
OUT
63
OUT
63
OUT
63
OUT
63
OUT
22 24 63 70
OUT
63
OUT
63
OUT
63
AW30
AV26
AN28
AN25
AW22
AV18
AN21
AN18
MEM_B_DQS_N & lt; 0 & gt;
MEM_B_DQS_N & lt; 1 & gt;
MEM_B_DQS_N & lt; 2 & gt;
MEM_B_DQS_N & lt; 3 & gt;
MEM_B_DQS_N & lt; 4 & gt;
MEM_B_DQS_N & lt; 5 & gt;
MEM_B_DQS_N & lt; 6 & gt;
MEM_B_DQS_N & lt; 7 & gt;
AV30
AW26
AM28
AM25
AV22
AW18
AM21
AM18
MEM_B_DQS_P & lt; 0 & gt;
MEM_B_DQS_P & lt; 1 & gt;
MEM_B_DQS_P & lt; 2 & gt;
MEM_B_DQS_P & lt; 3 & gt;
MEM_B_DQS_P & lt; 4 & gt;
MEM_B_DQS_P & lt; 5 & gt;
MEM_B_DQS_P & lt; 6 & gt;
MEM_B_DQS_P & lt; 7 & gt;
BI
63 70
BI
63 70
BI
63 70
BI
63 70
BI
63 70
BI
23 63 70
BI
63 70
BI
63 70
BI
63 70
BI
63 70
BI
63 70
BI
63 70
BI
63 70
BI
23 63 70
BI
C
63 70
BI
D
63 70
B
SYNC_MASTER=WILL_J43
SYNC_DATE=09/13/2012
PAGE TITLE
CPU DDR3/LPDDR3 Interfaces
DRAWING NUMBER
Apple Inc.
& lt; SCH_NUM & gt;
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
7 OF 121
SHEET
7 OF 76
1
SIZE
D
A
8
7
6
5
4
3
2
HSW-ULT current estimates from Haswell Mobile ULT Processor EDS vol 1, doc #502406, v0.9.
LPT-LP current estimates from Lynx Point-LP PCH EDS, doc #503118, v1.0.
Note [1] current numbers from clarification email, from Srini, dated 9/10/2012 2:11pm.
CRITICAL
OMIT_TABLE
PPVCC_S0_CPU
55 51 42 38 17 16 15 11 8 6
64 62 59 58
PP1V05_S0
67 51
R0800
1
1
R0802
75
1%
1/20W
MF
201
67 51
IN
OUT
R0810
2
CPU_VIDALERT_L
43
1
1%
1/20W
MF
201
2
Max load: 300mA
5
2
CPU_VCCSENSE_P
TP_PPVCCIO_S0_CPU
NC
PPVCOMP_S0_CPU
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
Max load: 300mA
OUT
0
BI
PLACE_NEAR=U0500.L63:2.54mm
17 16
IN
R0810.2:
PLACE_NEAR=U0500.L62:38.1mm
51 17
OUT
PLACE_NEAR=R0810.1:2.54mm
51 17
IN
IN
CPU_VIDSOUT
1
2
5%
1/20W
MF
0201
C
18
VCC1_05
VCC1_05
PP1V05_S0
29mA Max[1]
14 11
VCCUSB3PLL
B11
VCCSPI Y8
DCPSUS3
AH14
PP1V5_S0SW_AUDIO_HDA
AZALIA/HDA
VCCHDA
V8
W9
40mA Max[1]
11
J18
K19
PP1V05_S0_PCH_VCC_ICC
VCCCLK: 200mA Max
12 11
51 42 38 17 16 15 11 8 6
64 62 59 58 55
A20
PP1V05_S0_PCH_VCCACLKPLL
31mA Max
PP1V05_S0
VCCCLK: 200mA Max
WF: RSVD on Sawtooth Peak rev 1.0
62 59 58 57 46 18 14 11 8
64
PP3V3_SUS
3.3mA Max[1]
NC
NC
NC
J17
R21
T21
K18
M20
V21
AE20
AE21
VCCDSW3_3
VCC3_3
VCC3_3
8 11 14 18 46 57 58 59
62 64
PP1V05_S0
VCCASW AE9
VCCASW AF9
VCCASW AG8
DCPSUS1 AD10
DCPSUS1 AD8
THERMAL SENSOR
VCCTS1_5 J15
VCC3_3 K14
VCC3_3 K16
1
12 13 17 62 64
C0890
1UF
20%
10V
CERM
402
10%
6.3V
CERM
402
C0895
0.1UF
6 8 11 15 16 17 38 42 51
55 58 59 62 64
2
20%
10V
CERM
402
2
2
7
VCCST
VCCST
VCCST
VCC
VCC
VCC
VCC
VCC
VCC
BYPASS=U0500.AG10:6.35mm
BYPASS=U0500.AG10:6.35mm
BYPASS=U0500.AG10:6.35mm
D
C
B
185mA Max[1]
6 8 11 15 16 17 38 42 51 55 58
59 62 64
1499mA Max[1]
PLACE_NEAR=U0500.AG19:2.54mm
5.11
PPVOUT_S5_PCH_DCPSUSBYP_R
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
PP1V05_S0
1
Powered in DeepSx
2
1%
1/20W
MF-LF
201
PPVOUT_S5_PCH_DCPSUSBYP
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
1
C0899
1UF
6 8 11 15 16 17 38 42 51 55 58
59 62 64
473mA Max[1]
2
10%
6.3V
CERM
402
NC
NC
PP1V5_S0
3mA Max
PP3V3_S0
57 58 59 62 64
62 64 65 74
8 11 12 13 15 17 18 26 30 36 38
39 40 41 42 43 44 45 56 59 61
1mA Max[1]
VCCSDIO U8
VCCSDIO T9
SUS OSCILLATOR
DCPSUS4 AB8
RSVD AC20
PP3V3_S0
62 64 65 74
8 11 12 13 15 17 18 26 30 36 38
39 40 41 42 43 44 45 56 59 61
SYNC_MASTER=J43_MLB
17mA Max
SYNC_DATE=10/02/2012
PAGE TITLE
CPU/PCH POWER
DRAWING NUMBER
NC
Apple Inc.
R
NC
NOTICE OF PROPRIETARY PROPERTY:
VCC1_05 AG16
VCC1_05 AG17
6
& lt; SCH_NUM & gt;
REVISION
& lt; E4LABEL & gt;
WF: RSVD on Sawtooth Peak rev 1.0
PP1V05_S0
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6 8 11 15 16 17 38 42 51 55 58
59 62 64
213mA Max[1]
LPT LP POWER
8
VSS
PWR_DEBUG*
VSS
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
8 10 42 52 62 64
32A Max
SERIAL IO
VCCACLKPLL
VCCSUS3_3
VCCSUS3_3
1
0.1UF
D63
H59
P62
P60
P61
N59
N61
T59
AD60
AD59
AA59
AE60
AC59
AG58
U59
V59
C36
C40
C44
C48
C52
C56
E23
E25
E27
E29
E31
E33
E35
E37
E39
E41
E43
E45
E47
E49
E51
E53
E55
E57
F24
F28
F32
F36
F40
F44
F48
F52
F56
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
H23
J23
K23
K57
L22
M23
M57
P57
U57
W57
R0899
VCCCLK
VCCCLK
VCCCLK
VCCCLK
VCCCLK
RSVD
RSVD
RSVD
C0891
20%
10V
CERM
402
VIDALERT*
VIDSCLK
VIDSOUT
VCCST_PWRGD
VR_EN
VR_READY
PPVCC_S0_CPU
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
BYPASS=R0899:U0500:2.54mm
GPIO/LCC
AH10
PP3V3_S5
114mA Max
PP3V3_S0
VCCSUS3_3
VCCSUS3_3
J11
H11
H15
AE8
AF22
DCPSUSBYP AG19
DCPSUSBYP AG20
VRM/USB2/AZALIA
DCPSUS2
ICC
AC9
AA9
PP3V3_SUS
59mA Max[1]
74 65 64 62 61 59 56
30 26 18 17 15 13 12 11 8
45 44 43 42 41 40 39 38 36
AH13
USB2
NC
42 34 29 28 18 17 16 15 13 11
74 64 62 60 59 58 57
1
PP1V05_S0
VCC1P05
VCC1P05
VCC1P05
VCC1P05
VCC1P05
VCCAPLL
J13
OPI
W21
1
0.1UF
PP3V3_SUS
VCCASW AG14
VCCASW AG13
11mA Max
62 59 58 57 46 18 14 11 8
64
C0892
18mA Max
VCCSATA3PLL
Y20
NC AA21 VCCAPLL
VCCAPLL
NC
58 17 11
BYPASS=U0500.AE7:6.35mm
PPVOUT_S0_PCH_DCPRTC
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
2
57mA Max
A
DCPRTC AE7
USB3
11
PPVRTC_G3H
RSVD
VCCIO_OUT
VCCIOA_OUT
RSVD
RSVD
RSVD
PP1V05_S0
???mA Max
8 11 14 18 46 57 58 59 62 64
VCCRTC AG10
42mA Max
WF: RSVD on Sawtooth Peak rev 1.0
PP1V05_S0_PCH_VCCAPLL_OPI
55 51 42 38 17 16 15 11 8 6
64 62 59 58
PP3V3_SUS
0.3mA Max[1]
BGA
SYM 13 OF 19
CORE
B
12 11
B18
PP1V05_S0SW_PCH_VCCUSB3PLL
41mA Max
PP1V05_S0SW_PCH_VCCSATA3PLL
VCCSUS3_3 AH11
RTC
51 42 38 17 16 15 11 8 6
64 62 59 58 55
BROADWELL-ULT
2C+GT2
HSIO
SPI
1838mA Max
U0500
VCCHSIO
VCCHSIO
VCCHSIO
N8
P9
PP1V05_S0SW_PCH_HSIO
HSW ULT POWER
AB57
AD57
AG57
C24
C28
C32
NC
NC
NC
NC
NC
NC
NC
NC
NC
CRITICAL
OMIT_TABLE
62 58 11
BGA
SYM 12 OF 19
AC22
AE22
AE23
TP_CPU_RSVD_P60
TP_CPU_RSVDP61
TP_CPU_RSVD_N59
TP_CPU_RSVDN61
18
AB23
A59
E20
AD23
AA23
AE59
L62
N63
L63
B59
F60
C59
CPU_PWR_DEBUG
2
5%
1/20W
MF
0201
67 51
R0802.2:
R0800.2:
1
R0812
0
CPU_VIDSCLK
CPU_VIDALERT_R_L
CPU_VIDSCLK_R
CPU_VIDSOUT_R
CPU_VCCST_PWRGD
CPU_VR_EN
CPU_VR_READY
16
67 51
NC
NC
NC
NOTE: Aliases not used on CPU supply outputs
to avoid any extraneous connections.
2
5%
1/20W
MF
201
R0811
NC
AC58
NC
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
130
VCC_SENSE
BROADWELL-ULT
2C+GT2
1
100
5%
1/20W
MF
201
VCC
RSVD
RSVD
E63
D
R0860
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
F59
N58
1.4A Max (DDR3: 1.5-1.35V)
1.1A Max (LPDDR3: 1.2V)
PLACE_NEAR=U0500.C50:50.8mm
RSVD
RSVD
PPVMEMIO_S0_CPU
42 10
64 62 52 42 10 8
U0500
L59
J58
AH26
AJ31
AJ33
AJ37
AN33
AP43
AR48
AY35
AY40
AY44
AY50
NC
NC
K9
L10
M9
1
5
4
3
2
BRANCH
& lt; BRANCH & gt;
PAGE
8 OF 121
SHEET
8 OF 76
1
SIZE
D
A
8
7
6
5
4
CRITICAL
OMIT_TABLE
3
2
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE
U0500
U0500
U0500
BROADWELL-ULT
2C+GT2
BROADWELL-ULT
2C+GT2
BROADWELL-ULT
2C+GT2
BGA
SYM 14 OF 19
A11
A14
A18
A24
A28
A32
A36
A40
A44
A48
A52
A56
AA1
AA58
AB10
AB20
AB22
AB7
AC61
AD21
AD3
AD63
AE10
AE5
AE58
AF11
AF12
AF14
AF15
AF17
AF18
AG1
AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57
AJ13
AJ14
AJ23
AJ25
AJ27
AJ29
D
C
B
1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20
AP22
AP23
AP26
AP29
AP3
AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49
AR5
AR52
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63
AU1
AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55
BGA
SYM 15 OF 19
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AV59
AV8
AW16
AW24
AW33
AW35
AW37
AW4
AW40
AW42
AW44
AW47
AW50
AW51
AW59
AW60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33
AY4
AY51
AY53
AY57
AY59
AY6
B20
B24
B26
B28
B32
B36
B4
B40
B44
B48
B52
B56
B60
C11
C14
C18
C20
C25
C27
C38
C39
C57
D12
D14
D18
D2
D21
D23
D25
D26
D27
D29
D30
D31
D33
D34
D35
D37
D38
D39
D41
D42
D43
D45
D46
D47
D49
D5
D50
D51
D53
D54
D55
D57
D59
D62
D8
E11
E17
F20
F26
F30
F34
F38
F42
F46
F50
F54
F58
F61
G18
G22
G3
G5
G6
G8
H13
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BGA
SYM 16 OF 19
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_SENSE
VSS
H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63
D
C
V58
AH46
V23
E62
AH16
CPU_VCCSENSE_N
1
100
2
OUT
51 67
R0960
5%
1/20W
MF
201
PLACE_NEAR=U0500.E62:50.8mm
B
A
SYNC_MASTER=J43_MLB
SYNC_DATE=10/02/2012
PAGE TITLE
CPU/PCH GROUNDS
DRAWING NUMBER
Apple Inc.
& lt; SCH_NUM & gt;
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
9 OF 121
SHEET
9 OF 76
1
SIZE
D
A
8
7
6
5
4
3
2
1
All Intel recommendations from Intel doc #503160 Shark Bay Ultrabook Platform Power Delivery Design Guide Rev 1.0 unless stated otherwise
CPU VCC Decoupling
64 62 52 42 8
PPVCC_S0_CPU
Intel recommendation (Table 5-1): 23x 22uF 0805 stuff, 7x 22uF 0805 nostuff
Apple implementation
: 18x 10uF 0402 mirrored stuff, 1x 470uF stuff, 50x 10uF mirrored no stuff, 50x 10uF single sided no stuff
CRITICAL
1
CRITICAL
C1000
1
10UF
2
D
1
10UF
20%
4V
X6S
0402
2
NO STUFF
1
CRITICAL
C1001
1
1
10UF
20%
4V
X6S
0402
2
CRITICAL
C1015
NO STUFF
C1002
1
1
10UF
20%
4V
X6S
0402
2
CRITICAL
C1016
CRITICAL
C1003
1
1
10UF
20%
4V
X6S
0402
2
NO STUFF
C1018
1
C1005
NO STUFF
1
10UF
20%
4V
X6S
0402
2
CRITICAL
C1017
NO STUFF
C1004
20%
4V
X6S
0402
1
C1020
CRITICAL
1
10UF
2
NO STUFF
C1019
C1006
20%
4V
X6S
0402
C1021
NO STUFF
1
10UF
2
CRITICAL
1
C1007
20%
4V
X6S
0402
C1030
NO STUFF
1
10UF
2
NO STUFF
1
C1008
20%
4V
X6S
0402
C104A
CRITICAL
1
10UF
2
NO STUFF
1
C1009
20%
4V
X6S
0402
C104B
NO STUFF
1
10UF
2
NO STUFF
1
C1010
CRITICAL
1
10UF
20%
4V
X6S
0402
2
NO STUFF
1
C1011
C104C
20%
4V
X6S
0402
C104D
NO STUFF
1
10UF
2
NO STUFF
1
C1012
20%
4V
X6S
0402
C104E
1
10UF
2
NO STUFF
1
CRITICAL
C1013
NO STUFF
1
10UF
20%
4V
X6S
0402
2
NO STUFF
1
C1014
20%
4V
X6S
0402
1
C106A
NO STUFF
1
10UF
2
NO STUFF
C104F
C105A
20%
4V
X6S
0402
C106B
NO STUFF
1
10UF
2
NO STUFF
1
C105B
20%
4V
X6S
0402
C106C
2
1
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
4V
X6S
0402
2
1
20%
4V
X6S
0402
2
1
10UF
2
1
20%
4V
X6S
0402
2
1
20%
4V
X6S
0402
2
1
10UF
2
20%
4V
X6S
0402
2
20%
4V
X6S
0402
2
1
2
1
1
2
20%
4V
X6S
0402
2
1
1
2
1
2
2
NO STUFF
C1057
1
20%
4V
X6S
0402
1
20%
4V
X6S
0402
1
20%
4V
X6S
0402
2
1
1
20%
4V
X6S
0402
2
1
2
NO STUFF
C1059
1
2
20%
4V
X6S
0402
C1048
20%
4V
X6S
0402
1
C1063
20%
4V
X6S
0402
C1028
2
20%
4V
X6S
0402
20%
4V
X6S
0402
C1092
20%
4V
X6S
0402
2
C1029
20%
4V
X6S
0402
C1093
2
20%
4V
X6S
0402
2
C1032
20%
4V
X6S
0402
C1094
2
20%
4V
X6S
0402
2
C1033
2
20%
4V
X6S
0402
20%
4V
X6S
0402
2
C1095
20%
4V
X6S
0402
C1096
20%
4V
X6S
0402
2
C1034
20%
4V
X6S
0402
2
C1035
2
20%
4V
X6S
0402
CRITICAL
1
NO STUFF
1
C1036
2
20%
4V
X6S
0402
2
NO STUFF
1
C1064
NO STUFF
1
C1065
NO STUFF
1
C1066
NO STUFF
1
C1067
NO STUFF
1
C1068
NO STUFF
1
C1069
NO STUFF
1
C1098
2
NO STUFF
1
10UF
10UF
10UF
10UF
10UF
10UF
10UF
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
4V
X6S
0402
1
10UF
20%
4V
X6S
0402
20%
4V
X6S
0402
NO STUFF
1
NO STUFF
C109D
1
NO STUFF
C109E
1
2
NO STUFF
C109F
1
C108A
2
NO STUFF
1
C108B
2
NO STUFF
1
C108C
2
NO STUFF
1
C108D
2
NO STUFF
1
C108E
2
NO STUFF
1
C108F
2
NO STUFF
1
C107A
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
4V
X6S
0402
2
2
2
2
20%
4V
X6S
0402
2
2
2
2
2
2
2
C109A
10UF
2
20%
4V
X6S
0402
NO STUFF
1
10UF
2
C
C1038
NO STUFF
C1099
10UF
NO STUFF
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
4V
X6S
0402
C109C
C1084
C1049
10UF
1
20%
4V
X6S
0402
10UF
2
20%
4V
X6S
0402
C109B
10UF
2
10UF
20%
4V
X6S
0402
10UF
2
C106E
NO STUFF
1
10UF
2
1
10UF
20%
4V
X6S
0402
2
D
NO STUFF
C1037
10UF
2
20%
4V
X6S
0402
10UF
2
NO STUFF
1
10UF
20%
4V
X6S
0402
2
10UF
2
20%
4V
X6S
0402
10UF
2
2
20%
4V
X6S
0402
C1097
20%
4V
X6S
0402
NO STUFF
1
1
20%
4V
X6S
0402
10UF
2
2
2
C105F
CRITICAL
C1083
10UF
2
2
NO STUFF
1
10UF
10UF
2
10UF
20%
4V
X6S
0402
20%
4V
X6S
0402
2
20%
4V
X6S
0402
C105E
NO STUFF
1
NO STUFF
1
C1082
2
10UF
10UF
10UF
2
NO STUFF
1
NO STUFF
1
NO STUFF
1
10UF
C1081
10UF
10UF
2
2
NO STUFF
1
NO STUFF
1
NO STUFF
1
C1080
10UF
10UF
10UF
2
20%
4V
X6S
0402
2
NO STUFF
1
NO STUFF
1
NO STUFF
1
C1079
10UF
10UF
10UF
2
20%
4V
X6S
0402
2
NO STUFF
1
NO STUFF
1
NO STUFF
1
C1078
10UF
10UF
2
2
NO STUFF
1
NO STUFF
1
10UF
NO STUFF
C1062
2
NO STUFF
1
10UF
20%
4V
X6S
0402
2
C1027
C1091
C1077
10UF
10UF
NO STUFF
C1047
10UF
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
4V
X6S
0402
2
CRITICAL
1
NO STUFF
1
10UF
NO STUFF
C1046
2
NO STUFF
C1026
2
C1090
C1076
10UF
10UF
10UF
NO STUFF
C1058
1
NO STUFF
C1025
20%
4V
X6S
0402
2
CRITICAL
1
NO STUFF
C1089
2
10UF
20%
4V
X6S
0402
2
10UF
NO STUFF
C1045
10UF
20%
4V
X6S
0402
1
C1075
10UF
CRITICAL
C1088
10UF
20%
4V
X6S
0402
1
20%
4V
X6S
0402
2
NO STUFF
C1024
NO STUFF
C1044
20%
4V
X6S
0402
2
NO STUFF
C1074
10UF
10UF
10UF
20%
4V
X6S
0402
1
CRITICAL
C1087
NO STUFF
C1023
NO STUFF
C1056
20%
4V
X6S
0402
2
NO STUFF
C1073
10UF
10UF
10UF
NO STUFF
1
1
NO STUFF
C1039
1
NO STUFF
C1086
10UF
NO STUFF
1
2
NO STUFF
C1022
10UF
2
20%
4V
X6S
0402
2
NO STUFF
C1072
10UF
10UF
NO STUFF
C
1
NO STUFF
C1085
2
NO STUFF
C1071
10UF
NO STUFF
1
2
NO STUFF
C1070
10UF
2
1
10UF
20%
4V
X6S
0402
NO STUFF
1
NO STUFF
C106D
10UF
NO STUFF
1
2
NO STUFF
20%
4V
X6S
0402
C105D
10UF
20%
4V
X6S
0402
10UF
2
1
10UF
NO STUFF
1
NO STUFF
C105C
C107B
10UF
2
20%
4V
X6S
0402
B
B
CRITICAL
1
C1031
470UF-0.0045OHM
3
2
20%
2.5V
POLY-TANT
SM
CPU VDDQ DECOUPLING
42 8
PPVMEMIO_S0_CPU
Intel recommendation (Table 5-4): 4x 2.2uF 0402, 6x 10uF 0603
Apple implementation
: 4x 2.2uF 0402, 6x 10uF 0402, 2x 270uF B2 no stuff
1
C1040
1
C1041
1
C1042
2.2UF
2
1
2.2UF
20%
6.3V
CERM
402-LF
1
2.2UF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
2
C1050
1
C1051
2
1
C1052
C1043
2.2UF
2
1
20%
6.3V
CERM
402-LF
C1053
1
C1054
10UF
A
2
10UF
10UF
10UF
20%
6.3V
CERM-X5R
0402-1
20%
6.3V
CERM-X5R
0402-1
20%
6.3V
CERM-X5R
0402-1
20%
6.3V
CERM-X5R
0402-1
1
10UF
20%
6.3V
CERM-X5R
0402-1
2
2
2
2
C1055
10UF
2
20%
6.3V
CERM-X5R
0402-1
SYNC_MASTER=WILL_J43
SYNC_DATE=01/08/2013
PAGE TITLE
CPU Decoupling
DRAWING NUMBER
Apple Inc.
NO STUFF
1
1
C1060
270UF
2
8
C1061
270UF
20%
2V
TANT
CASE-B2-SM
2
7
& lt; SCH_NUM & gt;
REVISION
R
2x Bulk nostuff per Harris Beach v1.0 schematic
NOTICE OF PROPRIETARY PROPERTY:
20%
2V
TANT
CASE-B2-SM
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6
5
4
3
2
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
10 OF 121
SHEET
10 OF 76
1
SIZE
D
A
8
7
42 34 29 28 18 17 16 15 13 8
74 64 62 60 59 58 57
6
PCH VCCDSW3_3 BYPASS
(PCH 3.3V DSW PWR)
PP3V3_S5
5
4
PCH VCC3_3 BYPASS
(PCH 3.3V GPIO/LPC PWR)
61
PP3V3_S0
8
55 51 42 38 17 16 15 11 8 6
64 62 59 58
74 65 64 62
36 30 26 18 17 15 13 12 11
59 56 45 44 43 42 41 40 39 38
3
PCH VCCASW BYPASS
(PCH 1.05V ME CORE PWR)
PP1V05_S0
55 51 42 38 17 16 15 11 8 6
64 62 59 58
NO STUFF
C1200
2
1
PCH VCCIO BYPASS
(PCH 1.05V USB2 PWR)
PP1V05_S0
NO STUFF
1
C1212
1
C1250
1
1
C1251
C1264
1UF
22UF
22UF
1UF
20%
6.3V
X5R-CERM-1
603
20%
6.3V
X5R-CERM-1
603
10%
6.3V
CERM
402
10%
6.3V
CERM
402
1
1UF
10%
6.3V
CERM
402
2
BYPASS=U0500.AH10:6.35mm
2
2
2
BYPASS=U0500.V8:12.7mm
2
BYPASS=U0500.AG16:6.35mm
BYPASS=U0500.AE9:12.7mm
BYPASS=U0500.AE9:6.35mm
D
64 62 59 58 57 46 18 14 11 8
PCH VCCSPI BYPASS
(PCH 3.3V SPI PWR)
PP3V3_SUS
PCH VCC3_3 BYPASS
(PCH 3.3V THERMAL PWR)
61
PP3V3_S0
8
74 65 64 62
36 30 26 18 17 15 13 12 11
59 56 45 44 43 42 41 40 39 38
NO STUFF
C1202
55 51 42 38 17 16 15 11 8 6
64 62 59 58
1
C1214
0.1UF
20%
10V
CERM
402
2
BYPASS=U0500.Y8:6.35mm
64 62 59 58 57 46 18 14 11 8
55 51 42 38 17 16 15 11 8 6
64 62 59 58
1
C1255
2
1
1
C1256
1
C1257
C1266
1
22UF
62 58 11 8
1UF
1UF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
1
1UF
10%
6.3V
CERM
402
2
2
2
2
2
BYPASS=U0500.J17:6.35mm
BYPASS=U0500.R21:6.35mm
PCH VCCHSIO BYPASS
(PCH 1.05V PCIe/SATA/USB3 PWR)
PP1V05_S0SW_PCH_HSIO
2
BYPASS=U0500.AC9:12.7mm
C1260
C1261
1
1UF
10%
6.3V
CERM
402
1
1
2
C1262
2
1UF
10%
6.3V
CERM
402
PCH VCCSUS3_3 BYPASS
(PCH 3.3V SUSPEND RTC PWR)
PP3V3_SUS
C1206
C1267
1UF
20%
6.3V
X5R
603
BYPASS=U0500.J11:12.7mm
BYPASS=U0500.J11:6.35mm
BYPASS=U0500.AE8:6.35mm
20%
6.3V
X5R-CERM-1
603
1
10UF
BYPASS=U0500.K14:6.35mm
PCH VCCSUS3_3 BYPASS
(PCH 3.3V SUSPEND PWR)
PP3V3_SUS
C1204
64 62 59 58 57 46 18 14 11 8
D
PCH VCCCLK BYPASS
(PCH 1.05V CLK PWR)
PP1V05_S0
0.1UF
20%
10V
CERM
402
PCH VCC BYPASS
(PCH 1.05V CORE PWR)
PP1V05_S0
2
10UF
20%
6.3V
CERM-X5R
0402-1
BYPASS=U0500.K9:6.35mm
BYPASS=U0500.L10:6.35mm
BYPASS=U0500.M9:6.35mm
1
1UF
10%
6.3V
CERM
402
2
BYPASS=U0500.AH11:6.35mm
C
C
CRITICAL
L1270
PCH VCCSDIO BYPASS
(PCH 3.3V/1.8V SDIO PWR)
61
PP3V3_S0
8
55 51 42 38 17 16 15 11 8 6
64 62 59 58
R1270
PP1V05_S0
1
??mA Max
74 65 64 62
36 30 26 18 17 15 13 12 11
59 56 45 44 43 42 41 40 39 38
C1208
0
2
1
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
5%
1/16W
MF-LF
402
1
2.2UH-240MA-0.221OHM
PP1V05_S0_PCH_VCCACLKPLL_R
10%
6.3V
CERM
402
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.075 MM
VOLTAGE=1.05V
2
0603
C1270
1
C1271
47UF
2
20%
4V
CERM-X5R
0805-1
1
1
2
2
2
CRITICAL
PCH VCCSUSHDA BYPASS
(PCH 3.3V/1.5V HDA PWR)
PP1V5_S0SW_AUDIO_HDA
10%
10V
X5R
402
PCH VCCCLK FILTER/BYPASS
(PCH 1.05V VCCCLK PWR)
PP1V05_S0_PCH_VCC_ICC
L1275
R1275
1
0
2
1
2.2UH-240MA-0.221OHM
1
PP1V05_S0_PCH_VCC_ICC_R
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
5%
1/16W
MF-LF
402
1UF
10%
6.3V
CERM
402
C1272
BYPASS=U0500.A20:12.7mm
BYPASS=U0500.A20:12.7mm
BYPASS=U0500.A20:6.35mm
BYPASS=U0500.U8:6.35mm
C1210
8 12
31mA Max
1UF
47UF
20%
4V
CERM-X5R
0805-1
1UF
58 17 8
PCH VCCACLKPLL FILTER/BYPASS
(PCH 1.05V ACLK PLL PWR)
PP1V05_S0_PCH_VCCACLKPLL
C1275
0
1
1
2
2
2
C1277
1UF
47UF
20%
4V
CERM-X5R
0805-1
8
??mA Max
10%
10V
X5R
402
BYPASS=U0500.J18:12.7mm
BYPASS=U0500.J18:12.7mm
BYPASS=U0500.J18:6.35mm
2
5%
1/16W
MF-LF
402
B
C1276
20%
4V
CERM-X5R
0805-1
R1280
1
1
47UF
2
BYPASS=U0500.AH14:6.35mm
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.075 MM
VOLTAGE=1.05V
2
0603
CRITICAL
NO STUFF
1
B
PCH OPI VCCAPLL FILTER/BYPASS
(PCH 1.05V OPI PLL PWR)
PP1V05_S0_PCH_VCCAPLL_OPI
L1280
2.2UH-240MA-0.221OHM
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.075 MM
VOLTAGE=1.05V
2
0603
NO STUFF
NO STUFF
C1280
C1281
8
57mA Max
1
47UF
20%
4V
CERM-X5R
0805-1
1
1
2
2
2
C1282
1UF
47UF
20%
4V
CERM-X5R
0805-1
10%
10V
X5R
402
BYPASS=U0500.AA21:12.7mm
BYPASS=U0500.AA21:12.7mm
BYPASS=U0500.AA21:6.35mm
CRITICAL
PCH VCCSATA3PLL FILTER/BYPASS
(PCH 1.05V SATA3 PLL PWR)
PP1V05_S0SW_PCH_VCCSATA3PLL
L1290
62 58 11 8
2.2UH-240MA-0.221OHM
PP1V05_S0SW_PCH_HSIO
1
83mA Max
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.075 MM
VOLTAGE=1.05V
2
0603
8 12
42mA Max
NO STUFF
C1290
1
C1291
47UF
20%
4V
CERM-X5R
0805-1
1
1
2
2
2
C1292
1UF
47UF
20%
4V
CERM-X5R
0805-1
10%
10V
X5R
402
BYPASS=U0500.B11:12.7mm
BYPASS=U0500.B11:12.7mm
BYPASS=U0500.B11:6.35mm
A
CRITICAL
PCH VCCUSB3PLL FILTER/BYPASS
(PCH 1.05V USB3 PLL PWR)
PP1V05_S0SW_PCH_VCCUSB3PLL
L1295
2.2UH-240MA-0.221OHM
1
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.075 MM
VOLTAGE=1.05V
2
0603
NO STUFF
C1295
1
47UF
20%
4V
CERM-X5R
0805-1
C1296
1
1
20%
4V
CERM-X5R
0805-1
2
2
41mA Max
DRAWING NUMBER
Apple Inc.
C1297
10%
10V
X5R
402
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
LPT-LP current estimates from Lynx Point-LP PCH EDS, doc #503118, v1.0
as well as from clarification email, from Srini, dated 9/10/2012 2:11pm.
7
6
5
4
& lt; SCH_NUM & gt;
REVISION
R
BYPASS=U0500.B18:12.7mm
BYPASS=U0500.B18:12.7mm
BYPASS=U0500.B18:6.35mm
8
SYNC_DATE=02/07/2013
PCH Decoupling
1UF
47UF
2
SYNC_MASTER=J41_MLB
PAGE TITLE
8 14
3
2
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
12 OF 121
SHEET
11 OF 76
1
SIZE
D
A
8
7
6
5
4
3
2
1
PPVRTC_G3H
1
R1303
R1302 1
1
CRITICAL
OMIT_TABLE
R1301
U0500
AW5
AY5
RTCX1
RTCX2
PCH_INTRUDER_L
AU6
INTRUDER*
PCH_INTVRMEN
AV7
INTVRMEN
PCH_SRTCRST_L
20K
5%
1/20W
MF
201
AV6
SRTCRST*
20K
2
2
330K
1M
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
2
2
D
17
PCH_CLK32K_RTCX1
NC_RTC_CLK32K_RTCX2
IN
17
OUT
AU7
RTC_RESET_L
C1300
1
1
2
2
1UF
10%
10V
X5R
402
C1303
69 65 61
1UF
10%
10V
X5R
402
OUT
HDA_BIT_CLK
R1310
33
1
2
1
2
1
2
69
AW8
HDA_BIT_CLK_R
BROADWELL-ULT
2C+GT2
BGA
SYM 5 OF 19
SATA_RN0/PERN6_L3 J5
SATA_RP0/PERP6_L3 H5
69 65 61
OUT
HDA_SYNC
R1311
69 65 61
OUT
HDA_RST_L
R1312
33
69
AV11
HDA_SYNC_R
SATA_RN1/PERN6_L2 J8
SATA_RP1/PERP6_L2 H8
IN
64
AY10
AU12
HDA_SDIN0
NC_HDA_SDIN1
SATA_TN2/PETN6_L1 B14
SATA_TP2/PETP6_L1 C15
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
33
1
2
69 17
SATA
R1313
HDA_SDOUT
PCIE_SSD_R2D_C_N & lt; 1 & gt;
PCIE_SSD_R2D_C_P & lt; 1 & gt;
SATA_RN3/PERN6_L0 F5
SATA_RP3/PERP6_L0 E5
PCIE_SSD_D2R_N & lt; 0 & gt;
PCIE_SSD_D2R_P & lt; 0 & gt;
SATA_TN3/PETN6_L0 C17
SATA_TP3/PETP6_L0 D17
HDA_RST*/I2S_MCLK
AU11
HDA_SDO/I2S0_TXD
AW10
AV10
HDA_SDOUT_R
HDA_DOCK_EN*/I2S1_TXD
HDA_DOCK_RST*/I2S1_SFRM
5%
1/20W
MF
201
PLACE_NEAR=U0500.AU11:1.27mm
(IPD-PLTRST#)
TP_PCH_I2S1_TXD
TP_PCH_I2S1_SFRM
PCIE_SSD_R2D_C_N & lt; 0 & gt;
PCIE_SSD_R2D_C_P & lt; 0 & gt;
AY8
TP_PCH_I2S1_SCLK
Primary HDD/SSD
30 64 67
OUT
30 67
OUT
30 67
IN
D
30 64 67
IN
30 64 67
SSD Lane 2
Unused
SSD Lane 0
Secondary HDD/SSD
30 67
OUT
Reserved: ODD
SSD Lane 1
OUT
30 67
IN
30 64 67
IN
30 64 67
OUT
30 67
OUT
30 67
IN
30 64 67
IN
30 64 67
OUT
30 67
OUT
30 67
IN
15 16
I2S1_SCLK
IN
XDP_CPUPCH_TRST_L
AU62
69 64 16
IN
XDP_PCH_TCK
AE62
PCH_TCK
(IPD)
69 64 16
IN
XDP_PCH_TDI
AD61
PCH_TDI
(IPU)
69 64 16
OUT
XDP_PCH_TDO
AE61
XDP_PCH_TMS
PCH_TMS
AL11
RSVD
AC4
V1
U1
V6
AC1
XDP_FW_PME_L
XDP_PCH_GPIO35
XDP_PCH_UART_SSD_L_BT_H
XDP_SSD_PCIE0_SEL_L
RSVD
IN
12 16
IN
12 16
IN
16
PCH_TDO
AD62
SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37
PCH_TRST*
67 64 16 6
69 64 16
IN
(IPU)
C
NC
NC
16
AE63
PCH_JTAGX
BI
NC
AV2
SATA_IREF A12
JTAG
OUT
SSD Lane 3
PCIE_SSD_D2R_N & lt; 1 & gt;
PCIE_SSD_D2R_P & lt; 1 & gt;
(IPD-PLTRST#)
AU8
HDA_RST_R_L
(IPD)
69 65 61
SATA_RN2/PERN6_L1 J6
SATA_RP2/PERP6_L1 H6
HDA_SYNC/I2S0_SFRM
5%
1/20W
MF
201
PLACE_NEAR=U0500.AU8:1.27mm
69 65 61
PCIE_SSD_R2D_C_N & lt; 2 & gt;
PCIE_SSD_R2D_C_P & lt; 2 & gt;
SATA Port assignments:
30 64 67
IN
PCIE_SSD_D2R_N & lt; 2 & gt;
PCIE_SSD_D2R_P & lt; 2 & gt;
SATA_TN1/PETN6_L2 A17
SATA_TP1/PETP6_L2 B17
HDA_BCLK/I2S0_SCLK
5%
1/20W
MF
201
PLACE_NEAR=U0500.AV11:1.27mm
69
PCIE_SSD_R2D_C_N & lt; 3 & gt;
PCIE_SSD_R2D_C_P & lt; 3 & gt;
IN
RTCRST*
5%
1/20W
MF
201
PLACE_NEAR=U0500.AW8:1.27mm
33
PCIe Port assignments:
PCIE_SSD_D2R_N & lt; 3 & gt;
PCIE_SSD_D2R_P & lt; 3 & gt;
SATA_TN0/PETN6_L3 B15
SATA_TP0/PETP6_L3 A15
RTC
R1300 1
AUDIO
64 62 17 13 8
PP1V05_S0SW_PCH_VCCSATA3PLL
1
NC
RSVD K10
(IPU)
RSVD L11
NC
SATA_RCOMP C12
JTAGX
SATALED* U3
RSVD
8 11
R1370
3.01K
C
1%
1/20W
MF
2 201
PLACE_NEAR=U0500.C12:2.54mm
PCH_SATA_RCOMP
PCH_SATALED_L
12
CRITICAL
OMIT_TABLE
U0500
BROADWELL-ULT
2C+GT2
TP_PCIE_CLK100M_ENETSDN
TP_PCIE_CLK100M_ENETSDP
12
69 32
OUT
69 32
OUT
U2
ENETSD_CLKREQ_L
B41
A41
PCIE_CLK100M_CAMERA_N
PCIE_CLK100M_CAMERA_P
Y5
CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
PCIECLKRQ0*/GPIO18
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
IN
CAMERA_CLKREQ_L
69 64 29
OUT
69 64 29
OUT
PCIE_CLK100M_AP_N
PCIE_CLK100M_AP_P
C41
B42
CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
IN
AP_CLKREQ_L
AD1
PCIECLKRQ2*/GPIO20
NC_PCIE_CLK100M_FWN
NC_PCIE_CLK100M_FWP
B38
C37
CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
31 12
B
29 12
64
64
12
69 25
OUT
69 25
OUT
IN
OUT
67 64 30
OUT
PCIE_CLK100M_SSD_N
PCIE_CLK100M_SSD_P
IN
SSD_CLKREQ_L
30 12
B37
A37
T2
XTAL24_IN A25
XTAL24_OUT B25
PCH_CLK24M_XTALIN
PCH_CLK24M_XTALOUT
IN
17
OUT
17
PP1V05_S0_PCH_VCCACLKPLL
RSVD K21
RSVD M21
1
NC
NC
DIFFCLK_BIASREF C26
TESTLOW
TESTLOW
TESTLOW
TESTLOW
C35
C34
AK8
AL8
100K
100K
100K
1
2
1
2
1
2
1
2
1
2
MF
201
1/20W
MF
201
1/20W
MF
1
2
1
2
1
2
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
8
R1380
1%
1/20W
MF
2 201
PLACE_NEAR=U0500.C26:2.54mm
B
PCH_DIFFCLK_BIASREF
R1390
R1391
R1392
R1393
PCH_TESTLOW_C35
PCH_TESTLOW_C34
PCH_TESTLOW_AK8
PCH_TESTLOW_AL8
10K
10K
10K
10K
1
2
1
2
1
2
1
2
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
PCIECLKRQ3*/GPIO21
CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
PCIECLKRQ4*/GPIO22
CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
CLKOUT_LPC_0 AN15
LPC_CLK24M_SMC_R
CLKOUT_LPC_1 AP15
TP_LPC_CLK24M_LPCPLUS_R
OUT
17 69
(IPD-PWROK)
CLKOUT_ITPXDP_N B35
CLKOUT_ITPXDP_P A35
TP_ITPXDP_CLK100MN
TP_ITPXDP_CLK100MP
PCIECLKRQ5*/GPIO23
SYNC_MASTER=WILL_J43
1/20W
MF
SYNC_DATE=12/17/2012
PAGE TITLE
XDP_PCH_UART_SSD_L_BT_H
XDP_PCH_GPIO35
PCH_SATALED_L
PCH Audio/JTAG/SATA/CLK
12 16
DRAWING NUMBER
201
2
1
1/20W
5%
100K
100K
100K
100K
100K
100K
5%
5%
8 11
3.01K
PCIECLKRQ1*/GPIO19
64 65 74
8 11 13 15 17 18 26 30 36 38 39
40 41 42 43 44 45 56 59 61 62
PP3V3_S0
R1340
R1341
R1342
R1343
R1344
R1345
U5
TBT_CLKREQ_L
25 12
R1377
R1376
R1375
A39
B39
PCIE_CLK100M_TBT_N
PCIE_CLK100M_TBT_P
67 64 30
A
N1
FW_CLKREQ_L
CLOCK SIGNALS
BGA
SYM 6 OF 19
C43
C42
ENETSD_CLKREQ_L
CAMERA_CLKREQ_L
AP_CLKREQ_L
FW_CLKREQ_L
TBT_CLKREQ_L
SSD_CLKREQ_L
12 16
Apple Inc.
12
R
& lt; E4LABEL & gt;
12
NOTICE OF PROPRIETARY PROPERTY:
12 31
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
12 29
12
12 25
201
7
& lt; SCH_NUM & gt;
REVISION
12 30
6
5
4
3
2
BRANCH
& lt; BRANCH & gt;
PAGE
13 OF 121
SHEET
12 OF 76
1
SIZE
D
A
8
7
6
5
4
3
2
CRITICAL
OMIT_TABLE
PPVRTC_G3H
U0500
1
BROADWELL-ULT
2C+GT2
SYM 8 OF 19
R1400 kept for debug purposes.
39
AK2
IN
PM_SYSRST_L
AC3
SYS_RESET*
37 17 16
IN
PM_PCH_SYS_PWROK
AG2
SYS_PWROK
17 13
IN
PM_PCH_PWROK
AY7
PM_PCH_PWROK
AB5
IN
64 37 17
NO STUFF
SLP_S0# Isolation
74 65 64 62 61
36 30 26 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
R1400
1
0
PP3V3_S0
5%
1/20W
MF
0201
1
17 13
18 16 15
64 59
10%
10V
X5R-CERM
0201
39
PM_SLP_S0_L
4
DPWROK AV5
WAKE* AJ5
(IPD-DeepSx)
CLKRUN*/GPIO32 V5
PCH_PWROK
SUS_STAT*/GPIO61 AG4
APWROK
PM_DSW_PWRGD
5%
1/20W
MF
201
IN
PCIE_WAKE_L
IN
PM_CLKRUN_L
BI
LPC_PWRDWN_L
OUT
13 29 31 64
1
D
37
R1451
100K
13 37 64
37 64
2
OUT
PLT_RESET_L
AG7
PLTRST*
SUSCLK/GPIO62 AE6
PM_CLK32K_SUSCLK_R
OUT
PM_RSMRST_L
AW6
RSMRST*
SLP_S5*/GPIO63 AP5
PM_SLP_S5_L
OUT
13 37 59
AV4
SUSWARN*/SUSPWRDNACK/GPIO30
SLP_S4* AJ6
PM_SLP_S4_L
OUT
13 18 29 36 37 59
SLP_S3* AT4
PM_SLP_S3_L
OUT
13 17 18 37 59
OUT
5%
1/20W
MF
201
38 69
IN
13 42 59
OUT
IN
PM_PWRBTN_L
AL7
PWRBTN*
38 37
IN
SMC_ADAPTER_EN
AJ8
ACPRESENT/GPIO31
37 27 13
IN
PM_BATLOW_L
AN4
BATLOW*/GPIO72
SLP_SUS* AP4
PM_SLP_SUS_L
PCH_PM_SLP_S0_L
AF3
SLP_S0*
SLP_LAN* AJ7
TP_PCH_SLP_LAN_L
TP_PCH_SLP_WLAN_L
AM5
SLP_WLAN*/GPIO29
6
1
(IPU)
SLP_A* AL5
TP_PM_SLP_A_L
(IPD-DeepSx)
2
U1420
08
R1450
PCH_DSWVRMEN
37 16 13
74LVC1G08
SOT891
OUT
SUSACK*
2
PCH_SUSWARN_L
2
CRITICAL
37 18 13
IN
C1420
0.1UF
2
SYSTEM POWER MANAGEMENT
(IPU)
DSWVRMEN AW7
PCH_SUSACK_L
8 12 17 62 64
330K
BGA
D
1
NC
3
5
NC
SLP_S0# can be driven high outside of S0
U1420 ensures signal will only be high in S0.
CRITICAL
OMIT_TABLE
U0500
C
C
BROADWELL-ULT
2C+GT2
BGA
SYM 9 OF 19
OUT
EDP_BKLT_PWM
B8
EDP_BKLCTL
OUT
EDP_BKLT_EN
A9
EDP_BKLEN
60 13
OUT
26 13
IN
EDP_PANEL_PWR
C6
EDP_VDDEN
TBT_PWR_REQ_L
SMC_RUNTIME_SCI_L
HDMITBTMUX_FLAG
SSD_BOOT
U6
P4
N4
N2
DDPB_CTRLCLK B9
DDPB_CTRLDATA C9
eDP
SIDEBAND
56
56 13
PIRQA*/GPIO77
PIRQB*/GPIO78
PIRQC*/GPIO79
PIRQD*/GPIO80
DP_TBTSNK0_DDC_CLK
DP_TBTSNK0_DDC_DATA
OUT
DP_TBTSNK1_DDC_CLK
DP_TBTSNK1_DDC_DATA
OUT
(IPD-PLTRST#)
DDPC_CTRLCLK D9
DDPC_CTRLDATA D11
IN
64 13
IN
OUT
64
64 13
OUT
64 13
OUT
64 13
OUT
65 61 59 13
OUT
64 13
OUT
NC_PCI_PME_L
ODD_PWR_EN_L
HDMITBTMUX_LATCH
ENET_LOW_PWR
AUD_PWR_EN
AP_PCIE_DEV_WAKE
AD4
U7
L1
L3
R5
L4
PME*
(IPU)
GPIO55
GPIO52
GPIO54
GPIO51
GPIO53
PCI
37 13
30 13
DISPLAY
(IPD-PLTRST#)
BI
18 28
18 28
18
BI
18
DDPB_AUXN C5
DDPC_AUXN B6
DP_TBTSNK0_AUXCH_C_N
DP_TBTSNK1_AUXCH_C_N
BI
25 67
BI
18 25 67
DDPB_AUXP B5
DDPC_AUXP A6
DP_TBTSNK0_AUXCH_C_P
DP_TBTSNK1_AUXCH_C_P
BI
25 67
BI
18 25 67
DDPB_HPD C8
DP_TBTSNK0_HPD
IN
25
DDPC_HPD A8
DP_TBTSNK1_HPD
IN
18 25
DP_INT_HPD
IN
60
EDP_HPD D6
B
B
PP3V3_S5
PP3V3_S0
8 11 15 16 17 18 28 29 34 42 57
58 59 60 62 64 74
62 64 65 74
8 11 12 13 15 17 18 26 30 36 38
39 40 41 42 43 44 45 56 59 61
R1405
1K
1
2
R1410
10K
1
2
PM_PWRBTN_L
PCIE_WAKE_L
1/20W
MF
MF
201
2
R1460
R1461
R1462
R1463
R1464
100K
1
2
100K
1
2
100K
100K
1
2
1
2
100K
1
2
A
R1440
R1441
R1442
R1443
100K
100K
100K
100K
100K
1
1
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
1/20W
MF
5%
1/20W
MF
201
1/20W
MF
1
2
1
2
R1445
R1446
R1447
R1448
R1449
100K
100K
100K
100K
100K
2
1
2
1
2
1
2
1
2
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
1/20W
MF
1
2
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
8
EDP_BKLT_EN
EDP_PANEL_PWR
TBT_PWR_REQ_L
SMC_RUNTIME_SCI_L
HDMITBTMUX_FLAG
SSD_BOOT
13 18 29 36 37 59
13 17 18 37 59
13 18 37
13 42 59
13 56
13 60
SYNC_MASTER=J43_MLB
13 26
1/20W
MF
ODD_PWR_EN_L
HDMITBTMUX_LATCH
ENET_LOW_PWR
AUD_PWR_EN
AP_PCIE_DEV_WAKE
PCH PM/PCI/GFX
13 37
13 64
DRAWING NUMBER
13 30
Apple Inc.
13 64
& lt; SCH_NUM & gt;
REVISION
R
& lt; E4LABEL & gt;
13 64
NOTICE OF PROPRIETARY PROPERTY:
13 64
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
13 59 61 65
13 64
201
7
SYNC_DATE=02/20/2013
PAGE TITLE
201
2
1
5%
5%
1
13 37 59
201
2
2
PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L
PM_SLP_S0_L
PM_SLP_SUS_L
201
5%
100K
5%
5%
R1430
R1431
13 37 64
201
1/20W
13 29 31 64
PM_CLKRUN_L
201
2
1
MF
5%
1
10K
1/20W
13 27 37
201
5%
10K
R1455
MF
5%
R1452
1/20W
13 16 37
PM_BATLOW_L
5%
6
5
4
3
2
BRANCH
& lt; BRANCH & gt;
PAGE
14 OF 121
SHEET
13 OF 76
1
SIZE
D
A
8
7
6
5
4
CRITICAL
OMIT_TABLE
PCIe Port Assignments:
69 25
PCIE_TBT_D2R_N & lt; 0 & gt;
PCIE_TBT_D2R_P & lt; 0 & gt;
IN
Thunderbolt lane 0
69 25
OUT
69 25
OUT
IN
69 25
IN
69 25
OUT
69 25
69 25
OUT
69 25
OUT
69 64 29
IN
IN
AirPort
69 29
OUT
69 29
OUT
64
64
Reserved: FireWire
64
64
68 65 34
C
68 65 34
SD Card Reader
( & Ethernet if combo)
IN
IN
PERN3
PERP3
C29
B30
PETN3
PETP3
F13
G13
PERN4
PERP4
B29
A29
PETN4
PETP4
G17
F17
PERN1/USB3RN3
PERP1/USB3RP3
IN
IN
Camera
69 32
OUT
69 32
OUT
PP1V05_S0SW_PCH_VCCUSB3PLL
USB_BT_N
USB_BT_P
BI
29 68
BI
29 68
NC_USB_IRN
NC_USB_IRP
BI
64
BI
64
USB_TPAD_N
USB_TPAD_P
BI
36 64 68
BI
36 64 68
TP_USB_5N
TP_USB_5P
NC_USB_CAMERAN
NC_USB_CAMERAP
NC_USB_SDN
NC_USB_SDP
F15
G15
Ext B (LS/FS/HS)
BT
D
IR
Trackpad
Unused
64
Reserved: Camera
64
64
Reserved: SD (HS)
64
(IPD)
USB3 Port Assignments:
USB3_EXTA_D2R_N
USB3_EXTA_D2R_P
USB3_EXTA_R2D_C_N
USB3_EXTA_R2D_C_P
USB3_EXTB_D2R_N
USB3_EXTB_D2R_P
USB3TN2 B33
USB3TP2 A33
PERN2/USB3RN4
PERP2/USB3RP4
B31
A31
Ext A (LS/FS/HS)
USB3_EXTB_R2D_C_N
USB3_EXTB_R2D_C_P
IN
35 68
IN
35 68
OUT
35 68
OUT
35 68
Ext A (SS)
IN
61 65 68
IN
61 65 68
Ext B (SS)
OUT
61 65 68
OUT
61 65 68
C
PETN1/USB3TN3
PETP1/USB3TP3
PCH_PCIE_RCOMP
R1500
61 65 68
USB3RN2 E18
USB3RP2 F18
C30
C31
NC
NC
11 8
61 65 68
BI
USB3TN1 C33
USB3TP1 B34
PCIE_CAMERA_R2D_C_N
PCIE_CAMERA_R2D_C_P
OUT
BI
USB3RN1 G20
USB3RP1 H20
USB3_SD_R2D_C_N
USB3_SD_R2D_C_P
OUT
68 65 34
69 32
G11
F11
PCIE_CAMERA_D2R_N
PCIE_CAMERA_D2R_P
68 65 34
69 32
PETN5_L3
PETP5_L3
NC_PCIE_FW_R2D_CN
NC_PCIE_FW_R2D_CP
IN
69 25
Thunderbolt lane 3
USB_EXTB_N
USB_EXTB_P
USB2N6 AP11
USB2P6 AN11
B22
A21
PCIE_TBT_D2R_N & lt; 3 & gt;
PCIE_TBT_D2R_P & lt; 3 & gt;
1
35 68
USB2N5 AM13
USB2P5 AN13
NC_PCIE_FW_D2RN
NC_PCIE_FW_D2RP
IN
PERN5_L3
PERP5_L3
PCIE_AP_R2D_C_N
PCIE_AP_R2D_C_P
OUT
E6
F6
USB3_SD_D2R_N
USB3_SD_D2R_P
69 25
PETN5_L2
PETP5_L2
PCIE_TBT_R2D_C_N & lt; 3 & gt;
PCIE_TBT_R2D_C_P & lt; 3 & gt;
OUT
B21
C21
PCIE_AP_D2R_N
PCIE_AP_D2R_P
69 25
Thunderbolt lane 2
PERN5_L2
PERP5_L2
BI
USB2N4 AM15
USB2P4 AL15
H10
G10
PCIE_TBT_R2D_C_N & lt; 2 & gt;
PCIE_TBT_R2D_C_P & lt; 2 & gt;
IN
35 68
USB2N3 AR10
USB2P3 AT10
PCIE_TBT_D2R_N & lt; 2 & gt;
PCIE_TBT_D2R_P & lt; 2 & gt;
IN
69 25
BI
USB2N2 AR8
USB2P2 AP8
PETN5_L1
PETP5_L1
USB_EXTA_N
USB_EXTA_P
USB2N1 AR7
USB2P1 AT7
BGA
SYM 11 OF 19
PERN5_L1
PERP5_L1
B23
A23
USB2N0 AN8
USB2P0 AM8
BROADWELL-ULT
2C+GT2
PETN5_L0
PETP5_L0
2
USB Port Assignments:
U0500
USB2N7 AR13
USB2P7 AP13
PERN5_L0
PERP5_L0
F8
E8
PCIE_TBT_R2D_C_N & lt; 1 & gt;
PCIE_TBT_R2D_C_P & lt; 1 & gt;
OUT
69 25
69 64 29
C23
C22
PCIE_TBT_D2R_N & lt; 1 & gt;
PCIE_TBT_D2R_P & lt; 1 & gt;
69 25
Thunderbolt lane 1
69 25
F10
E10
PCIE_TBT_R2D_C_N & lt; 0 & gt;
PCIE_TBT_R2D_C_P & lt; 0 & gt;
IN
PCI-E
USB
69 25
D
3
E15
E13
A27
B27
USBRBIAS* AJ10
USBRBIAS AJ11
68
PCH_USB_RBIAS
PLACE_NEAR=U0500.AJ10:2.54mm
1
RSVD AN10
RSVD AM10
PETN2/USB3TN4
PETP2/USB3TP4
RSVD
RSVD
PCIE_RCOMP
PCIE_IREF
OC0*/GPIO40
OC1*/GPIO41
OC2*/GPIO42
OC3*/GPIO43
AL3
AT1
AH2
AV3
R1570
22.6
NC
NC
1%
1/20W
MF
2 201
XDP_USB_EXTA_OC_L
XDP_USB_EXTB_OC_L
XDP_USB_EXTC_OC_L
XDP_USB_EXTD_OC_L
IN
14 16 35
IN
14 16 61 65
IN
14 16
IN
14 16
1
3.01K
1%
1/20W
MF
CRITICAL
OMIT_TABLE
201
PLACE_NEAR=U0500.A27:2.54mm 2
U0500
BROADWELL-ULT
2C+GT2
BGA
SYM 7 OF 19
BI
OUT
LPC_FRAME_L
BI
69 64 37
R1540
R1541
R1542
R1543
33
33
33
33
1
1
2
R1544
33
2
1
2
1
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1
(IPU)
1/20W
MF
LPC_AD_R & lt; 0 & gt;
LPC_AD_R & lt; 1 & gt;
LPC_AD_R & lt; 2 & gt;
LPC_AD_R & lt; 3 & gt;
AU14
AW12
AY12
AW11
LPC_FRAME_R_L
2
AV12
LFRAME*
AA3
SPI_CLK
LAD0
LAD1
LAD2
LAD3
SMBALERT*/GPIO11 AN2
5%
1/20W
MF
69 46
201
OUT
SPI_CLK_R
14
OUT
SPI_CS0_R_L
Y7
SPI_CS0*
Y4
SPI_CS1*
AC2
SPI_CS2*
SML1CLK_GPIO75 AU3
SML1DATA/GPIO74 AH3
(IPU)
69 46 14
SPI_MOSI_R
BI
SPI_MISO
BI
SPI_IO & lt; 2 & gt;
BI
SPI_IO & lt; 3 & gt;
AA2
SPI_MOSI
WOL_EN
SML_PCH_0_CLK
SML_PCH_0_DATA
BI
PCH_SML1ALERT_L
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA
16 19 40 56 69
B
16 19 40 56 69
OUT
14 64
OUT
40 69
BI
40 69
SML1ALERT# pull-up not provided on this
page, may be wire-ORed into other signals.
Otherwise, 100k pull-up to 3.3V SUS required.
OUT
18 39
OUT
32 37 40 43 44 64 69 73
BI
32 37 40 43 44 64 69 73
(IPU/IPD)
AA4
SPI_MISO
(IPU)
Y6
SPI_IO2
(IPU)
AF1
SPI_IO3
(IPU/IPD)
C-LINK
69 46
BI
SPI
(IPU)
69 46 14
SML0CLK AN1
SML0DATA AK1
SML1ALERT*/PCHHOT*/GPIO73 AU4
(IPU)
TP_SPI_CS2_L
69 46
SML0ALERT*/GPIO60 AL2
OUT
(IPU)
TP_SPI_CS1_L
PP3V3_SUS
PP3V3_SUS
SMBUS_PCH_CLK
SMBUS_PCH_DATA
201
2
69 46
A
PCH_SMBALERT_L
SMBCLK AP2
SMBDATA AH1
LPC
BI
69 64 37
69 64 37
B
BI
SMBUS
69 64 37
LPC_AD & lt; 0 & gt;
LPC_AD & lt; 1 & gt;
LPC_AD & lt; 2 & gt;
LPC_AD & lt; 3 & gt;
69 64 37
(IPU/IPD)
CL_CLK AF2
NC_CLINK_CLK
64
CL_DATA AD2
NC_CLINK_DATA
64
CL_RST* AF4
NC_CLINK_RESET_L
64
(IPU)
8 11 14 18 46 57 58 59 62 64
8 11 14 18 46 57 58 59 62 64
SYNC_MASTER=WILL_J43
R1580
R1581
R1582
R1583
100K
100K
100K
100K
1
2
1
2
1
2
1
2
5%
1/20W
MF
201
1K
1K
1
1
2
R1590
R1591
100K
100K
1
1/20W
MF
201
5%
1/20W
MF
201
5%
R1548
R1549
5%
1/20W
MF
2
1/20W
MF
201
5%
2
5%
1/20W
MF
1/20W
MF
201
5%
8
PCH PCIe/USB/LPC/SPI/SMBus
14 16 61 65
DRAWING NUMBER
14 16
14 16
Apple Inc.
14 46 69
1/20W
MF
PCH_SMBALERT_L
WOL_EN
14 46 69
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
14
14 64
201
7
& lt; SCH_NUM & gt;
REVISION
R
201
5%
SPI_IO & lt; 2 & gt;
SPI_IO & lt; 3 & gt;
SYNC_DATE=09/13/2012
PAGE TITLE
14 16 35
201
2
1
XDP_USB_EXTA_OC_L
XDP_USB_EXTB_OC_L
XDP_USB_EXTC_OC_L
XDP_USB_EXTD_OC_L
6
5
4
3
2
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
15 OF 121
SHEET
14 OF 76
1
SIZE
D
A
8
7
6
5
4
3
2
1
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
RAMCFG_SLOT
RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H
58 55 51 42 38 17 16 11 8 6
64 62 59
TABLE_BOMGROUP_ITEM
PP1V05_S0
R1650 1
RAMCFG3:H
R1631 1
RAMCFG2:H
1
RAMCFG1:H
1
1K
PP3V3_S3
IN
R1696 1
R1611
100K
100K
100K
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
2
2
2
2
5%
1/20W
MF
201
16 15
XDP_MLB_RAMCFG0
XDP_MLB_RAMCFG1
XDP_MLB_RAMCFG2
XDP_MLB_RAMCFG3
D
U0500
100K
100K
15 16 18
THERMTRIP* D60
BROADWELL-ULT
2C+GT2
2
XDP_PCH_GPIO76
BI
5%
1/20W
MF
201
CRITICAL
OMIT_TABLE
SSD_LPSR:S3
RAMCFG0:H
R1635 1
R1636
64 62 58 41 40 36 33 19 18 15
P1
BGA
SYM 10 OF 19
BMBUSY*/GPIO76
PM_THRMTRIP_L
2
38 67
IN
18 25
LPC_SERIRQ
SERIRQ T4
PCH_OPI_COMP AW15
OUT
TBT_CIO_PLUG_EVENT_L
RCIN*/GPIO82 V4
CPU/MISC
62 64 65 74
8 11 12 13 15 17 18 26 30 36 38
39 40 41 42 43 44 45 56 59 61
PP3V3_S0
BI
15 37 64
D
PCH_OPI_COMP
BI
XDP_MLB_RAMCFG0
AU2
BI
HDMITBTMUX_SEL_TBT
AM7
LAN_PHY_PWR_CTRL/GPIO12
OUT
TP_MEM_VDD_SEL_1V5_L
AD6
GPIO15
BI
XDP_LPCPLUS_GPIO
16 15
IN
XDP_PCH_GPIO17
T3
GPIO17
GSPI0_CLK/GPIO84 L6
34 15
OUT
SD_RESET_L
AD5
GPIO24
GSPI0_MISO/GPIO85 N6
37 15
15 16 18
IN
SMC_WAKE_SCI_L
AN5
GPIO27
IN
TPAD_SPI_INT_GPIO28_L
AD7
GPIO28
GSPI1_CS*/GPIO87 R7
TPAD_SPI_CS_L
OUT
OUT
TPAD_USB_IF_EN
AN3
GPIO26
GSPI1_CLK/GPIO88 L5
TPAD_SPI_CLK
OUT
15 36 68
IN
15 36 68
OUT
15 36 68
18 16 15
15 16 18
25 18
15 16 18
18
GPIO12:
64 16 15
CR:
TBT_GO2SX_BIDIR,
requires 100k pull-up to SUS
RR/FR: DPHDMIMUX_SEL_TBT, requires 100k pull-up to TBTLC
PLT_RESET_L
IN
R1621 1
15
25 18
36 15
64 59 58 30 15
2
OUT
SSD_PWR_EN
OUT
IN
XDP_SDCONN_STATE_CHANGE_L
SD_PWR_EN
AK4
OUT
TBT_PWR_EN
AB6
OUT
XDP_JTAG_ISP_TCK
U4
XDP_JTAG_ISP_TDI
Y3
GPIO49
OUT
JTAG_TBT_TMS_PCH
P3
GPIO50
58 15
OUT
PCH_HSIO_PWR_EN
Y2
HSIOPC/GPIO71
TPAD_SPI_INT_L
R1682
36 15
OUT
TPAD_SPI_IF_EN
AT3
BI
XDP_MLB_RAMCFG3
AH4
0
5%
1/20W
MF
2 0201
18 16 15
64 46 15
TPAD_SPI_INT_GPIO46_L
18 15
15
AUD_SPI_CLK
15 64
TPAD_SPI_MISO
15 36
BI
SPIROM_USE_MLB
AM4
OUT
CAMERA_PWR_EN_PCH
AG5
GPIO44
PCH_BT_UART_D2R
15 64
UART0_TXD/GPIO92 K3
GPIO59
TPAD_SPI_MOSI
UART0_RXD/GPIO91 J1
PCH_BT_UART_R2D
15 64
UART0_RTS*/GPIO93 J2
PCH_BT_UART_RTS_L
15 64
UART0_CTS*/GPIO94 G1
GPIO47
PCH_BT_UART_CTS_L
15 64
UART1_RXD/GPIO0 K4
PCH_UART1_RXD
15
UART1_TXD/GPIO1 G2
PCH_UART1_TXD
15
UART1_RST*/GPIO2 J3
JTAG_ISP_TDO
PLT_RESET_L
IN
IN
GPIO13
UART1_CTS*/GPIO3 J4
GPIO14
I2C0_SDA/GPIO4 F2
AP_S0IX_WAKE_L
I2C0_SCL/GPIO5 F3
PCH_I2C1_SDA
PCH_I2C1_SCL
100K
15
30
74 65 64 62 61
36 30 26 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
GPIO46
AM3
GPIO9
18 16 15
BI
XDP_MLB_RAMCFG2
AM2
GPIO10
SDIO_CLK/GPIO64 E3
TBT_POC_RESET_L
OUT
26
64 30 15
2
OUT
SSD_SR_EN_L
P2
DEVSLP0/GPIO33
SDIO_CMD/GPIO65 F4
BT_PWRRST_L
OUT
OUT
AP_S0IX_WAKE_SEL
C4
SDIO_POWER_EN/GPIO70
L2
DEVSLP1/GPIO38
SDIO_D1/GPIO67 E4
1K
1
N5
DEVSLP2/GPIO39
SDIO_D2/GPIO68 C3
LCD_IRQ_L
PCH_TCO_TIMER_DISABLE
V2
SPKR/GPIO81
SDIO_D3/GPIO69 E2
LCD_PSR_EN
2
1/20W
MF
SDIO_D0/GPIO66 D3
PCH_STRP_TOPBLK_SWP_L
IN
39
ENET_MEDIA_SENSE
IN
(IPD-PLTRST#)
201
IN
15 64
OUT
Pull-up on TBT page
15 64
15 64
(IPD-PLTRST#)
Requires connection to SMC via 1K series R
8 11 13 16 17 18 28 29 34 42 57
58 59 60 62 64 74
15 18 19 33 36 40 41 58 62 64
34 37 39 65
15 18 19 33 36 40 41 58 62 64
31 41
45 56 59 61 62 64 65 74
8 11 12 13 15 17 18 26 30 36 38
39 40 41 42 43 44
62 64 65 74
8 11 12 13 15 17 18 26 30 36 38
39 40 41 42 43 44 45 56 59 61
74 65 64 62 61
36 30 26 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
64 15
TBTLC for CR, S0 for RR
R1610
100K
1
2
R1614
R1615
100K
100K
1
2
1
2
XDP_PCH_GPIO76
5%
1/20W
MF
5%
1/20W
MF
201
5%
1/20W
MF
1
1
2
1
2
1
2
1
2
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
5%
5%
R1622
R1623
R1624
R1625
R1626
R1627
R1628
R1629
R1630
100K SSD_LPSR:S0
1
2
5%
100K
1
2
5%
100K
1
2
5%
100K
1
2
5%
100K
1
2
5%
100K
1
2
5%
100K
1
2
5%
100K
1
2
5%
100K
1
2
R1632
R1633
R1634
100K
100K
100K
5%
A
1
2
1
2
1/20W
1/20W
MF
MF
MF
201
201
201
1/20W
MF
201
1/20W
MF
201
1/20W
MF
201
1/20W
MF
201
1/20W
MF
201
1/20W
MF
201
1/20W
MF
201
1/20W
MF
201
1/20W
MF
HDD_PWR_EN
XDP_SDCONN_STATE_CHANGE_L
SD_PWR_EN
TBT_PWR_EN
XDP_JTAG_ISP_TCK
XDP_JTAG_ISP_TDI
JTAG_TBT_TMS_PCH
PCH_HSIO_PWR_EN
TPAD_SPI_IF_EN
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
68 36 15
68 36 15
1
5%
1/20W
MF
201
5%
1/20W
MF
201
1/20W
MF
64 15
2
1
2
R1652
10K
1
R1668
R1669
47K
47K
1
15 36
64 15
2
15 30 58 59
64
SSD_LPSR:S0 BOM option is on R1620
PCH_UART1_RXD
PCH_UART1_TXD
JTAG_ISP_TDO
PCH_UART1_CTS_L
R1672
R1673
R1674
R1675
47K
47K
100K
47K
1
15
15 64
15
2
15 16 33
18 15
1
2
15 34
15
1
2
15 25
29 15
AP_S0IX_WAKE_L
R1676
100K
1
201
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
1/20W
MF
201
5%
1/20W
MF
201
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
1/20W
MF
201
1/20W
MF
201
1/20W
MF
1/20W
MF
5%
1/20W
MF
201
1/20W
MF
201
2
1
201
MF
1/20W
2
1
MF
1/20W
2
2
1
2
1
2
1
2
15 16 18 25
15 16 18 25
15 18
15
15 58
15
15 36
Stuffed R1632
15 46 64
64 15
R1678
R1679
PCH_I2C1_SDA
PCH_I2C1_SCL
PCH_BT_UART_RTS_L
PCH_BT_UART_CTS_L
R1670
R1677
2.2K
2.2K
47K
47K
1
2
1
2
1
2
2
No-Stuffed R1634
SYNC_MASTER=WILL_J43
1/20W
MF
SSD_SR_EN_L
AP_S0IX_WAKE_SEL
XDP_FW_PME_L
15 29
15 37 64
15 30 64
SYNC_DATE=01/14/2013
PAGE TITLE
PCH GPIO/MISC/LPIO
12 16
DRAWING NUMBER
Apple Inc.
201
& lt; SCH_NUM & gt;
REVISION
R
100K
1
2
R1693
R1694
R1695
100K
100K
100K
1
2
BT_PWRRST_L
5%
8
1
2
2
1/20W
MF
1/20W
MF
201
5%
1/20W
MF
201
1/20W
MF
NOTICE OF PROPRIETARY PROPERTY:
15 64
201
& lt; E4LABEL & gt;
BRANCH
201
5%
5%
1
201
15 18
15
LPC_SERIRQ
5%
R1691
201
2
1
201
2
1
PCH_BT_UART_D2R
PCH_BT_UART_R2D
1
15 37
15 36
1/20W
5%
201
5%
100K
100K
100K
R1664
R1665
R1666
R1667
5%
5%
TPAD_SPI_CS_L
TPAD_SPI_CLK
TPAD_SPI_MISO
TPAD_SPI_MOSI
47K
47K
47K
47K
201
5%
R1616 should also be stuffed if
platform does not use SD card
15 34
NOSTUFF
R1637
R1638
R1640
2
MF
5%
36 15
64 15
SPIROM_USE_MLB
CAMERA_PWR_EN_PCH
TPAD_SPI_INT_GPIO46_L
2
1
1/20W
5%
15 16
201
2
1
1/20W
1
5%
5%
64 15
68 36 15
SD_RESET_L
SMC_WAKE_SCI_L
TPAD_SPI_INT_L
TPAD_USB_IF_EN
SSD_PWR_EN
2
B
2
1
5%
64 15
201
2
1
15 16 64
SD_ON_MLB
100K
100K
100K
100K
100K
100K
100K
100K
100K
5%
15 16
201
XDP_LPCPLUS_GPIO
XDP_PCH_GPIO17
R1660
R1661
R1662
R1663
AUD_SPI_CS_L
AUD_SPI_CLK
AUD_SPI_MISO
AUD_SPI_MOSI
PP3V3_S0
5%
64 15
R1616
R1617
R1618
R1619
R1620
29
15 64
29 15
2
5%
B
AG3
XDP_MLB_RAMCFG1
OUT
R1641
PP3V3_S5
PP3V3_S3
PP3V3_S0SW_SD
PP3V3_S3
PP3V3_S3RS0_CAMERA
PP3V3_S0
PP3V3_S0
TPAD_SPI_INT_GPIO46_L
OUT
31 18
PP3V3_S0
5%
1/20W
MF
201
IN
BI
100K
5%
1/20W
MF
201
5%
1/20W
MF
201
OUT
CAM_PCIE_RESET_L
R1680
100K
2
GPIO45
SSD_RESET_L
R1639
C
13 15 16 18
15
GPIO25
PCH_UART1_CTS_L
15
1
IN
R1671
15
I2C1_SCL/GPIO7 F1
15 29
1
AP_RESET_L
I2C1_SDA/GPIO6 G4
15 18
18 16 15
1
1%
1/20W
MF
201
15 64
AUD_SPI_MOSI
2
15 64
AUD_SPI_MISO
GSPI_MOSI/GPIO90 K2
GPIO48
OUT
1
15 64
GPIO58
18 15
5%
1/20W
MF
2 0201
GSPI1_MISO/GPIO89 N7
GPIO57
AL4
25 18 16 15
0
R1655
49.9
AUD_SPI_CS_L
(IPD)
AP1
25 18 16 15
R1681
GSPI0_MOSI/GPIO86 L8
GPIO56
HDD_PWR_EN
1
36 15
AG6
BI
34 15
1
(IPD)
(IPD-DeepSx)
OUT
15
25 15
C
GSPI0_CS*/GPIO83 R6
AT5
33 16 15
TPAD_SPI_INT_GPIO28_L
PLACE_NEAR=U0500.AW15:2.54mm
NC
NC
(IPD-RSMRST#)
GPIO16
PCH_TBT_PCIE_RESET_L
OUT
64 15
RSVD AF20
RSVD AB21
(IPD-PLTRST#)
100K
5%
1/20W
MF
201
Y1
GPIO8
GPIO
LPIO
18 16 15 13
Pull-up/down on chipset support page (depends on TBT controller)
Cactus Ridge: Alias to TBT_CIO_PLUG_EVENT,
requires pull-down.
Redwood Ridge: Alias to TBT_CIO_PLUG_EVENT_L, requires pull-up (S0).
7
ENET_MEDIA_SENSE
LCD_IRQ_L
LCD_PSR_EN
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
15 64
15 64
15 64
6
5
4
3
2
& lt; BRANCH & gt;
PAGE
16 OF 121
SHEET
15 OF 76
1
SIZE
D
A
8
7
6
Extra BPM Testpoints
67 6
IN
XDP_BPM_L & lt; 3 & gt;
1
TP
TP-P6
67 6
IN
XDP_BPM_L & lt; 4 & gt;
1
67 6
IN
XDP_BPM_L & lt; 5 & gt;
1
67 6
IN
XDP_BPM_L & lt; 6 & gt;
1
IN
XDP_BPM_L & lt; 7 & gt;
1
TP
TP-P6
TP
TP-P6
TP
TP-P6
67 6
D
TP
CRITICAL
XDP_CONN
TP1802
J1800
TP1803
1
TP1804
TP1805
TP1806
2
67 64 6
TP1807
IN
IN
67 6
IN
67 6
IN
2
3
6
18
1K
1
IN
67 6
23
5%
PLACE_NEAR=U0500.C61:2.54mm
1/20W
MF
IN
37 13
R1802
PM_PWRBTN_L
OUT
0
1
64
2
5%
PLACE_NEAR=U5000.J3:2.54mm
1/20W
MF
PM_PCH_SYS_PWROK
OUT
R1804
0
1
MF-LF
69 56 40 19 14
69 64 16 12
67 64 16 6
BI
IN
OUT
SMBUS_PCH_DATA
SMBUS_PCH_CLK
XDP_PCH_TCK
R1835
0
1
39
41
44
43
46
XDP
5%
1/20W
MF
0201
PLACE_NEAR=J1800.58:28mm
C1804
XDP
1
1
0.1UF
10%
6.3V
CERM-X5R
0201
47
R1831
5%
1/16W
MF-LF
2 402
C1800
52
51
54
53
56
55
58
6 67
CPU_CFG & lt; 19 & gt;
CPU_CFG & lt; 18 & gt;
IN
6
IN
6
CPU_CFG & lt; 12 & gt;
CPU_CFG & lt; 13 & gt;
IN
6 67
IN
6 67
CPU_CFG & lt; 14 & gt;
CPU_CFG & lt; 15 & gt;
IN
6 67
IN
6 67
NC
NC
XDP
57
59
1
64
67
XDP_CPURST_L
XDP_DBRESET_L
R1805
1K
1
2
PLT_RESET_L
5%
1/20W
MF
201
PLACE_NEAR=U0500.AG7:2.54mm
17 67
OUT
IN
13 15 18
NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
1
XDP_PCH_TDO
63
XDP
C1801
2
518S0847
IN
12 16 64 69
XDP_PCH_TDI
XDP_PCH_TMS
OUT
12 16 64 69
OUT
12 16 64 69
XDP_CPU_TDO
IN
XDP_TRST_L
1
Q1840
0.1UF
10%
6.3V
CERM-X5R
0201
10%
6.3V
CERM-X5R
0201
2
C
CRITICAL
XDP
C1806
0.1UF
2
D
6 67
TDO
TRSTn
TDI
TMS
XDP_PRESENT#
XDP
0.1UF
10%
6.3V
CERM-X5R
0201
6 67
IN
49
XDP
1K
2
IN
IN
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
45
48
60
2
IN
6 67
DMN5L06VK-7
SOT563
D
PCH_JTAGX
OUT
6
37
42
XDP
16 12
35
40
SDA
SCL
TCK1
TCK0
XDP_CPU_TCK
OUT
33
36
PWRGD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
CPU_PWR_DEBUG
XDP_SYS_PWROK
201
31
34
402
69 56 40 19 14
C
OUT
64
1/16W
29
50
8
2
5%
XDP_CPU_VCCST_PWRGD
XDP_CPU_PWRBTN_L
0201
XDP
37 17 13
27
30
201
XDP
MF
25
38
2
1/20W
6
IN
OBSDATA_D2
OBSDATA_D3
21
28
OBSDATA_B2
OBSDATA_B3
IN
OBSDATA_D0
OBSDATA_D1
17
24
OBSDATA_B0
OBSDATA_B1
CPU_CFG & lt; 6 & gt;
CPU_CFG & lt; 7 & gt;
IN
67 6
XDP
R1800
CPU_VCCST_PWRGD
IN
CPU_CFG & lt; 4 & gt;
CPU_CFG & lt; 5 & gt;
IN
67 6
5%
19
22
OBSFN_B0
OBSFN_B1
CPU_CFG & lt; 10 & gt;
CPU_CFG & lt; 11 & gt;
OBSFN_D0
OBSFN_D1
15
32
67 6
201
13
16
CPU_CFG & lt; 8 & gt;
CPU_CFG & lt; 9 & gt;
OBSDATA_C2
OBSDATA_C3
11
CPU_CFG & lt; 17 & gt;
CPU_CFG & lt; 16 & gt;
OBSDATA_C0
OBSDATA_C1
9
26
IN
MF
7
12
OBSFN_C0
OBSFN_C1
5
10
OBSDATA_A2
OBSDATA_A3
XDP_BPM_L & lt; 0 & gt;
XDP_BPM_L & lt; 1 & gt;
IN
67 6
1/20W
1
1
4
20
67 6
5%
2
PLACE_NEAR=U0500.E60:28mm
OBSDATA_A0
OBSDATA_A1
CPU_CFG & lt; 2 & gt;
CPU_CFG & lt; 3 & gt;
IN
67 64 6
R1813
XDP_CPU_TCK
67 64 16 6
51
TDI and TMS are terminated in CPU.
OBSFN_A0
OBSFN_A1
CPU_CFG & lt; 0 & gt;
CPU_CFG & lt; 1 & gt;
2
61
14
67 64 6
1
XDP
M-ST-SM1
62
5%
1/16W
MF-LF
402
XDP_CPU_PREQ_L
XDP_CPU_PRDY_L
BI
51
PLACE_NEAR=U0500.F62:28mm
R1830
150
67 6
17 8
XDP
R1810
XDP_CPU_TDO
67 64 16 6
DF40RC-60DP-0.4V
8
TP-P6
NOTE: This is not the standard XDP pinout.
Use with 921-0133 Adapter Flex to
support chipset debug.
PP1V05_S0
G 5
TP
TP-P6
55 51 42 38 17 16 15 11 8 6
64 62 59 58
PLACE_NEAR=J1800.51:28MM
S
1
1
6 16 64 67
4
XDP_BPM_L & lt; 2 & gt;
2
Merged (CPU/PCH) Micro2-XDP
PP1V05_S0
55 51 42 38 17 16 15 11 8 6
64 62 59 58
3
VER 3
IN
4
3
67 6
5
DMN5L06VK-7
G 2
CRITICAL
XDP
Q1840
VER 3
XDP_CPU_PRESENT_L
S
XDP_CPUPCH_TRST_L
XDP_CPUPCH_TRST_L
XDP_CPUPCH_TRST_L
SOT563
OUT
XDP_USB_EXTC_OC_L
XDP_USB_EXTA_OC_L
MAKE_BASE=TRUE
XDP_USB_EXTB_OC_L
MAKE_BASE=TRUE
1
TP
TP-P6
IN
XDP_USB_EXTD_OC_L
OUT
BI
XDP_MLB_RAMCFG1
1
BI
XDP_MLB_RAMCFG2
1
TP
TP-P6
18 15
TP
TP-P6
18 15
BI
XDP_MLB_RAMCFG3
1
TP
TP-P6
IN
OUT
XDP_FW_PME_L
12
OUT
XDP_PCH_GPIO35
1
XDP_PCH_UART_SSD_L_BT_H
OUT
XDP_SSD_PCIE0_SEL_L
1
R1884
1K
1
TP
TP
TP-P6
2
BI
XDP_PCH_GPIO17
1
BI
XDP_PCH_GPIO76
1
NC
A
NC
Y
5
D
4
OUT
6 64 67
62 57
XDP_JTAG_CPU_ISOL_L
4
NC
XDP_CPU_TMS
PP1V05_SUS
NO STUFF
NC
16 12
R1899
PCH_JTAGX
1K
2
1
PLACE_NEAR=U0500.AE63:28mm
69 64 16 12
R1890
XDP_PCH_TDO
XDP_PCH_TDI
51
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
2
1/20W
MF
201
5%
1/20W
MF
201
1
PLACE_NEAR=U0500.AE61:28mm
TP1878
XDP
OUT
R1891
51
2
1
PLACE_NEAR=U0500.AD61:28mm
15 16 18 25
TP1879
69 64 16 12
51
2
1
PLACE_NEAR=U0500.AD62:28mm
NO STUFF
69 64 16 12
TP1881
R1896
XDP_PCH_TCK
51
2
1
PLACE_NEAR=U0500.AE62:28mm
NO STUFF
1/20W
MF
201
67 64 16 12 6
BI
XDP_JTAG_ISP_TDI
TP
R1892
XDP_PCH_TMS
NOTE: Must not short XDP pins together!
TP1880
XDP_LPCPLUS_GPIO
TP
TP-P6
IN
2
1
5%
1/20W
MF
201
69 64 16 12
OUT
MAKE_BASE=TRUE
TP-P6
25 18 16 15
ALL_SYS_PWRGD
15 16 33
2
XDP
XDP_LPCPLUS_GPIO
OUT
15
A
VCC
74LVC1G07GF
SOT891
B
TP1877
5%
15
64 16 15
330K
XDP
TP
TP-P6
12
SOT563
R1845
GND
XDP_JTAG_ISP_TCK
1
TP-P6
OUT
IN
1
U1845
2
TP1876
MAKE_BASE=TRUE
12
IN
1
0.1UF
59 37 17
XDP_JTAG_ISP_TCK
15 12
25 18 16 15
14 16 61 65
TP1874
XDP_SDCONN_STATE_CHANGE_L
TP
IN
10%
16V
X5R-CERM
0201
MAKE_BASE=TRUE
TP-P6
18 15
C1845
TP1873
XDP_SDCONN_STATE_CHANGE_L
1
DMN5L06VK-7
14 16 35
3
14
33 16 15
IN
D
14
TP-P6
CRITICAL
XDP
Q1842
TP1870
6
OUT
XDP_USB_EXTB_OC_L
35 16 14
6 64 67
G 2
XDP_USB_EXTA_OC_L
TP
6
OUT
65 61 16 14
B
BI
PP5V_S0
PP3V3_S5
6 12 16 64 67
OUT
XDP_CPU_TDI
S
42 34 29 28 18 17 15 13 11 8
74 64 62 60 59 58 57
1
6 12 16 64 67
OUT
1
62 61 59 58 56 52 51 45 32 17
64
Non-XDP Signals
XDP_MLB_RAMCFG0
18 15
3
PLACE_NEAR=J1800.55:28mm
VER 3
PCH/XDP Signals
CPU JTAG Isolation
OUT
G 5
DMN5L06VK-7
These signals do not connect to XDP connector in this architecture, only accessible
via Top-Side Probe. Nets are listed here to show XDP associations and to make clear
what restrictions exist on PCH GPIOs when Top-Side Probe is used for PCH debug.
S
Q1842
VER 3
CRITICAL
XDP
PCH XDP Signals
6 12 16 64 67
MAKE_BASE=TRUE
1
6
D
SOT563
R1897
XDP_CPUPCH_TRST_L
51
2
1
PLACE_NEAR=U0500.AU62:28mm
15 16 64
TP1886
TP1887
XDP_JTAG_ISP_TDI
MAKE_BASE=TRUE
15 16 18 25
SYNC_MASTER=WILL_J43
SYNC_DATE=12/17/2012
PAGE TITLE
Unused & MLB_RAMCFGx GPIOs have TPs.
CPU/PCH Merged XDP
USB Overcurrents are aliased, do not cause USB OC# events during PCH debug.
DRAWING NUMBER
Apple Inc.
SDCONN_STATE_CHANGE_L is aliased, do not plug/unplug SD Cards during PCH debug.
& lt; SCH_NUM & gt;
REVISION
R
& lt; E4LABEL & gt;
JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug.
NOTICE OF PROPRIETARY PROPERTY:
NOTE: Should force PCH GPIO47 high to ensure TBT router powered to avoid leakage/clamping of signals.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SSD_PCIEx_SEL_L straps are connected via 1K to common net.
LPCPLUS_GPIO is aliased, do not attempt use during PCH debug.
8
7
6
5
4
3
2
BRANCH
& lt; BRANCH & gt;
PAGE
18 OF 121
SHEET
16 OF 76
1
SIZE
D
A
8
7
6
5
4
3
2
1
System RTC Power Source & 32kHz / 25MHz Clock Generator
Chipset uses 24MHz crystal, GreenCLK kept to save 1x 25MHz crystal & 1x 32kHz crystal
69
4
NO STUFF
1
4
25.000MHZ-12PF-20PPM
R1906
1M
3
SM-3.2X2.5MM
12PF
3
SYSCLK_CLK25M_X2_R
2
2
5%
1/20W
MF
201
69
6
NC
NC
MEMVTT_PWR_EN
4
5
NC
MEMVTT_PWR_EN
NC
PCH_CLK24M_XTALOUT_R
1
1
CRITICAL
NC
NC
OUT
OUT
32 69
OUT
62 61 59 58 56 52 51 45 32 16
64
12
PP5V_S0
25 69
1
9
PCH ME Disable Strap
NC
8
SYSCLK_CLK25M_CAMERA
SYSCLK_CLK25M_TBT
PPVRTC_G3H
15
1
8 12 13 62 64
Q1920
For SB RTC Power
DMN5L06VK-7
THRM
PAD
SOT563
1
C1910
58 11 8
NC_RTC_CLK32K_RTCX2
20%
6.3V
X5R
0201
100K
5%
1/20W
MF
2 201
SPI_DESCRIPTOR_OVERRIDE_LS5V
SPI_DESCRIPTOR_OVERRIDE
1
NC_RTC_CLK32K_RTCX2
NO_TEST=TRUE
IN
D 6
1
5%
1/20W
MF
2 201
6.8PF
OUT
PCH_CLK24M_XTALIN
S 1
12 69
OUT
IPD = 9-50k
SPI_DESCRIPTOR_OVERRIDE_L
12
PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.
If high, ME is disabled. This allows for full re-flashing of SPI ROM.
SMC controls strap enable to allow in-field control of strap setting.
Q1920 & 5V pull-up allows circuit to work regardless of HDA voltage.
R1916
2
IN
G
12
5%
1/20W
MF
2 201
3.20X2.50MM-SM1
C
HDA_SDOUT_R
2
1M
24.000MHZ-20PPM-6PF
R1921
1K
12 17
37
5%
1/20W
MF
0201
Y1915
R1920
PP1V5_S0SW_AUDIO_HDA
1UF
MAKE_BASE=TRUE
IN
17 53
SILK_PART=SYS RESET
Q1920
PCH_CLK24M_XTALOUT
2
3
4
2
NC
NC
0
OUT
GND
R1915
2
D
17 53
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
VER 3
6.8PF
VCCST (1.05V S0) PWRGD
+/-0.1PF
25V
C0G
0201
PCH 24MHz Outputs
22
1
PLACE_NEAR=U0500.AN15:5.1mm
PP3V3_S5
1
MAKE_BASE=TRUE
C1930
LPC_CLK24M_SMC
2
PP1V05_S0
17 37 69
OUT
17 37 69
1
CRITICAL
0.1UF
10%
16V
X5R-CERM
0201
5%
1/20W
MF
201
59 37 17 16
59 37 18 13
IN
74AUP1G09
2
2
A
PM_SLP_S3_L
1
5
R1931
2
5%
1/20W
MF
201
B
NC
NC
Y
CPU_VCCST_PWRGD
4
OUT
8 16
B
GND
3
B
SOT891
VCC
ALL_SYS_PWRGD
6 8 11 15 16 38 42 51 55 58 59
62 64
10K
U1930
6
LPC_CLK24M_SMC_R
34 29 28 18 17 16 15 13 11 8
74 64 62 60 59 58 57 42
LPC_CLK24M_SMC
R1927
IN
Y
SOT563
C1915
69 12
1
2
A
DMN5L06VK-7
17 12
C1916
2
TPS51916 I(leak) = +/- 1uA,
Vih(min) = 1.8V
33uW when driven-low
5%
1/20W
MF
201
3
2
PCH_CLK32K_RTCX1
2
PCH 24MHz Crystal
1
12
SYSCLK_CLK25M_X1
C
+/-0.1PF
25V
C0G
0201
IN
74AUP1G07GF
SOT891
CPU_MEMVTT_PWR_EN_LSVDDQ
NOTE: 30 PPM or better required for RTC accuracy
5%
25V
CERM
0201
1
13
GND
R1997
6
330K
G 5
CRITICAL
Y1905
C1906
1
2
5%
1/20W
MF
0201
2
NC
NC
0
1
VG3HOT
TQFN
CRITICAL
VIOE_25M_A
32.768K
VIOE_25M_B
VIOE_25M_C
25M_A
25M_B
25M_C
X2
X1
VOUT
7
1
5%
25V
CERM
0201
5
SLG3NB148CV
6
NO STUFF
1
2
+V3.3A should be first
available ~3.3V power
to reduce VBAT draw.
U1900
20%
6.3V
X5R
0201
14
SYSCLK_CLK25M_X2
VDD
1UF
13 37 64
BI
R1970
VCC
U1970
S
2
PM_SYSRST_L
2
1
4
2
0.1UF
VBAT and +V3.3A are
internally ORed to
create VDD_RTC_OUT.
C1902
R1905
69
1
10%
16V
X5R-CERM
0201
VER 3
10%
16V
X5R-CERM
0201
1
CKPLUS_WAIVE=PwrTerm2Gnd
1
XDP_DBRESET_L
1
0.1UF
D
2
1
11
2
IN
C1970
3
C1922
0.1UF
10%
16V
X5R-CERM
0201
62 64 65 74
8 11 12 13 15 17 18 26 30 36 38
39 40 41 42 43 44 45 56 59 61
PP3V3_S0
5%
1/20W
MF
2 201
0
17
1
16
C1924
12PF
67 16
0
1/20W
0201
MF
5%
PP1V2_CAM_XTALPCIEVDD
PP3V3_TBTLC
C1905
XDP
R1996
10
64 62 26 25 18
PP1V2_S3
R1995
10K
Coin-Cell & G3Hot:
3.42V G3Hot
Coin-Cell & No G3Hot: 3.3V S5
No Coin-Cell:
3.3V S5
No bypass necessary
2
31
70 62 53 42 23 22 21 20 19
1
NC
CAM XTAL Power
TBT XTAL Power
PP3V3_S0
PP3V3_S5
34 29 28 18 17 16 15 13 11 8
74 64 62 60 59 58 57 42
PP3V3_S5RS3RS0_SYSCLKGEN
GreenCLK 25MHz Power
18
Must be powered if any VDDIO is powered.
Memory VTT Enable Level-Shifter
CPU output is on VDDQ rail (1.2V), TPS51916 has 1.8V Vih(min).
74 65 64 62 61
36 30 26 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
Coin-Cell:
VBAT (300-ohm & 10uF RC)
No Coin-Cell: 3.42V G3Hot (no RC)
This looks a little ugly to support
new and old parts. With GreenCLK Rev C
pin 5 must receive S5 power (Stuff R2042)
D
PCH Reset Button
PP3V42_G3H
50 49 46 40 38 37 36 35 30 17
65 64 62 61 59
PCH PWROK Generation
PM_PCH_PWROK
PM_PCH_PWROK
PP3V42_G3H
50 49 46 40 38 37 36 35 30 17
65 64 62 61 59
OUT
74 65 64 62 61
36 30 26 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
13 17
OUT
MAKE_BASE=TRUE
13 17
BYPASS=U1950:5MM
PP3V3_S0
1
C1950
0.1UF
51 8
IN
R1950
CPU_VR_EN
5%
1/20W
MF
201
1
10K
5%
1/20W
MF
201
A
51 17 8
OUT
IN
2
10K
R1955
51 17 8
1
CPU_VR_READY
R1951
IN
ALL_SYS_PWRGD
1
2
2
MAKE_BASE=TRUE
CPU_VR_READY
SOT833
A
U1950Y 7
0
5%
1/20W
MF
0201
2
0
5%
1/20W
MF
0201
2
CPUVR_PGOOD_R
59 37 17 16
1
NO STUFF
R1963 2
8 74LVC2G08GT/S505
NO STUFF
2
10%
16V
X5R-CERM
0201
B
0
1
1
5%
1/20W
MF
0201
R1961 1
100K
5%
1/20W
MF
201
SOT833
A
U1950Y 3
NO STUFF
4
CKPLUS_WAIVE=UNCONNECTED_PINS
8 74LVC2G08GT/S505
5
PM_S0_PGOOD
08
WF: Do we need this?
R1960
6
B
SYS_PWROK_R
SYNC_MASTER=J43_MLB1
R1962
1K
1
2
OUT
Chipset Support
13 16 37
5%
1/20W
MF
201
08
4
SYNC_DATE=01/09/2013
PAGE TITLE
PM_PCH_SYS_PWROK
DRAWING NUMBER
Apple Inc.
R
2
NOTICE OF PROPRIETARY PROPERTY:
38 37 27 26
8
7
IN
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SMC_DELAYED_PWRGD
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
19 OF 121
SHEET
17 OF 76
1
A
8
7
6
5
4
3
2
GreenCLK 25MHz Power
DDC Pull-Ups
Platform Reset Connections
2.2k pull-ups are required by PCH
to indicate active display interface.
NO STUFF
Unbuffered
R2040
64 62 58 41 40 36 33 19 15
16 15 13
0
PP3V3_S3
1
PLT_RESET_L
IN
PCA9557D_RESET_L
2
OUT
64
40
12
26
45
62
39
11
18
44
61
38
8
17
43
17 18
NO STUFF
74 65 64 62 61
36 30 26 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
1
R2041/2 should be stuffed for
GreekCLK A or B depending on S2 rail
2
5%
1/20W
MF
0201
R2042 should be stuffed for GreenCLK C
28 18 13
28 18 13
5
Buffered
R2072
CRITICAL
MC74VHC1G08
SC70-HF
4
U2071
0
PLT_RST_BUF_L
1
2
1
3
5%
1/20W
MF
201
10%
16V
X5R-CERM
0201
2
2
BKLT_PLT_RST_L
OUT
15 31
5%
1/20W
MF
0201
NOSTUFF
R2089
0
34 29 28 18 17 16 15 13 11 8
74 64 62 60 59 58 57 42
PCH_TBT_PCIE_RESET_L
MAKE_BASE=TRUE
64 62 26 25 17
OUT
5%
1/20W
MF
201 2
1
0.1UF
C2060
2
20%
10V
CERM
402
IN
PM_SLP_S4_L
IN
CAMERA_PWR_EN_PCH
1
25
IN
15
From PCH
JTAG_TBT_TDO
IN
JTAG_TBT_TMS_PCH
MAKE_BASE
5%
1/20W
MF
2 201
VCC
25 18 15
25 18 15
To PCH
1A
1Y
6
JTAG_ISP_TDO
OUT
15
3
2A
2Y
4
JTAG_TBT_TMS
OUT
25
25
OUT
25
08
OUT
OUT
NC
5
25
3
NC
R2030
0
5%
1/20W
MF
0201
59
28
11
16
42
64
58
18
8
15
34
62
R2019
1
R2014
10K
10K
5%
1/20W
MF
201 2
5%
1/20W
MF
2 201
5%
1/20W
MF
2 201
TBT Aliases
PP3V3_S5_DBGLED
28 18 13
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=3.3V
IN
28 18 13
BI
1
5%
1/16W
MF-LF
402
DP_TBTSNK0_DDC_CLK
DP_TBTSNK0_DDC_DATA
DP_TBTSNK0_DDC_CLK
DP_TBTSNK0_DDC_DATA
TRUE
TRUE
OUT
BI
DBGLED
DBGLED
DBGLED
R2092 1
R2093 1
R2095 1
25 18 13
DBGLED
R2091 1
20K
20K
20K
20K
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
2
DBGLED_S4
2
DBGLED_S3
2
DBGLED_S0I3
OUT
IN
67 25 18 13
BI
67 25 18 13
2
18 8
TP_CPU_RSVDN61
TP_CPU_RSVDP61
TP_CPU_RSVDP61
BI
18 13
IN
18 13
TP_CPU_RSVDN61
BI
8 18
MAKE_BASE=TRUE
DBGLED_S0
8 18
A
DBGLED
A
DBGLED
DBGLED
A
A
D2090
D2091
D2092
D2093
GREEN-56MCD-2MA-2.65V
LTQH9G-SM
GREEN-56MCD-2MA-2.65V
LTQH9G-SM
GREEN-56MCD-2MA-2.65V
LTQH9G-SM
GREEN-56MCD-2MA-2.65V
LTQH9G-SM
PLACE_SIDE=BOTTOM
SILK_PART=S5_ON
K
PLACE_SIDE=BOTTOM
SILK_PART=STBY_ON
K
DBGLED_S4_D
PLACE_SIDE=BOTTOM
SILK_PART=S3_ON
13 18 28
DBGLED_S3_D
DBGLED
Q2090
DMN5L06VK-7
Q2090
DMN5L06VK-7
25 18 16 15
DBGLED
DMN5L06VK-7
Q2091
DMN5L06VK-7
SOT563
SOT563
59 37 17 13
IN
37 13
IN
TRUE
TRUE
TRUE
VER 3
VER 3
5 25 67
5 25 67
BI
BI
13 18 25
67
13 18 25
67
13 18
B
13 18
XDP_JTAG_ISP_TCK
XDP_JTAG_ISP_TDI
OUT
OUT
15 16 18
25
15 16 18
25
No MAKE_BASE on TCK/TDI as these are provided on XDP page.
VER 3
G
S 1
5
G
S 4
2
G
S 1
5
G
RAM Configuration Straps
PP3V3_SUS
8 11 14 46 57 58 59 62 64
Pull-downs for chip-down RAM systems
S 4
OUT
16 15
OUT
16 15
OUT
16 15
S4_PWR_EN
PM_SLP_S4_L
PM_SLP_S3_L
PM_SLP_S0_L
OUT
XDP_MLB_RAMCFG0
XDP_MLB_RAMCFG1
XDP_MLB_RAMCFG2
XDP_MLB_RAMCFG3
1
R2010
100K
RAMCFG3:L
R2050 1
RAMCFG2:L
R2051 1
RAMCFG1:L
5%
1/20W
MF
2 201
RAMCFG0:L
R2052 1
R2053 1
10K
10K
10K
10K
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
2
2
2
39 14
OUT
PCH_SML1ALERT_L
2
A
SYNC_MASTER=J43_MLB
18 6
18 15
IN
TP_CPU_MEM_RESET_L
IN
TP_MEM_VDD_SEL_1V5_L
70 21 20 19 18
TP_CPU_MEM_RESET_L
TP_MEM_VDD_SEL_1V5_L
70 21 20 19 18
PP0V6_S3_MEM_VREFCA_A
70 23 22 19 18
PP0V6_S3_MEM_VREFDQ_B
PP0V6_S3_MEM_VREFCA_B
4
18 19 22 23 70
VOLTAGE=0.6V
PP0V6_S3_MEM_VREFCA_B
3
18 19 20 21 70
VOLTAGE=0.6V
PP0V6_S3_MEM_VREFDQ_B
MAKE_BASE=TRUE
18 19 20 21 70
VOLTAGE=0.6V
PP0V6_S3_MEM_VREFCA_A
MAKE_BASE=TRUE
5
Apple Inc.
15 18
VOLTAGE=0.6V
18 19 22 23 70
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
R
PP0V6_S3_MEM_VREFDQ_A
MAKE_BASE=TRUE
6
DRAWING NUMBER
6 18
MAKE_BASE=TRUE
MAKE_BASE=TRUE
70 23 22 19 18
Project Chipset Support
MAKE_BASE=TRUE
PP0V6_S3_MEM_VREFDQ_A
SYNC_DATE=01/17/2013
PAGE TITLE
LPDDR3 Alias Support
7
13 18 25
OUT
D 3
16 15
IN
TRUE
IN
OUT
SOT563
2
59 37 36 29 18 13
IN
DBGLED
D 6
VER 3
IN
TRUE
XDP_JTAG_ISP_TCK
XDP_JTAG_ISP_TDI
IN
25 18 16 15
PLACE_SIDE=BOTTOM
SILK_PART=S0_ON
SOT563
59 58 28
TRUE
DBGLED_S0_D
Q2091
D 3
DBGLED
GREEN-56MCD-2MA-2.65V
LTQH9G-SM
K
DBGLED_S0I3_D
DBGLED
D 6
TRUE
D2095
PLACE_SIDE=BOTTOM
SILK_PART=S0I3_ON
K
DP_TBTSNK1_HPD
DP_TBTSNK1_ML_C_P & lt; 3..0 & gt;
DP_TBTSNK1_ML_C_N & lt; 3..0 & gt;
DP_TBTSNK1_AUXCH_C_P
DP_TBTSNK1_AUXCH_C_N
DP_TBTSNK1_DDC_CLK
DP_TBTSNK1_DDC_DATA
Single-port TBT implementation does not require DDC Crossbar
MAKE_BASE=TRUE
DBGLED
DP_TBTSNK1_HPD
=DP_TBTSNK1_ML_C_P & lt; 3..0 & gt;
=DP_TBTSNK1_ML_C_N & lt; 3..0 & gt;
DP_TBTSNK1_AUXCH_C_P
DP_TBTSNK1_AUXCH_C_N
DP_TBTSNK1_DDC_CLK
DP_TBTSNK1_DDC_DATA
IN
Pin N61 needs a TP for Power to perform iFDIM test
Renaming the pins N61 and P61 to remove automatic diffpari property
18 8
2
DBGLED_S5
8
13 18 28
MAKE_BASE
20K
K
1
10K
5%
1/20W
MF
2 201
MAKE_BASE
DBGLED
A
R2018 1
R2017
10K
Power State Debug LEDs
R2090 1
B
1
5%
1/20W
MF
201 2
(For development only)
0
2
PLACE_SIDE=BOTTOM
15 18 25
C
10K
R2094
PP3V3_S5
IN
NOTE: This reference schematic assumes PCH JTAG GPIOs are only used for
Thunderbolt. If other ASIC JTAG signals are wired into these GPIOs
different isolation techniques will likely be necessary.
2
DBGLED
60
29
13
17
57
74
TBT_CIO_PLUG_EVENT_L
TRUE
R2016 1
NOTE: Solution shown is for LPT-LP. Other PCH’s may require isolation on TCK
and TDI as well for PCH glitch-prevention.
1
15 18 25
TBT_B_CIO_SEL
DP_TBTPB_HPD
TBT_B_CONFIG2_RC
TBT_B_CONFIG1_BUF
TBT_B_LSRX
IN
25
GND
31
BI
Required for unused second TBT port
To RR
25
OUT
HDMITBTMUX_SEL_TBT
TRUE
TBT_CIO_PLUG_EVENT_L
OUT
S0 pull-up on PCH page
1
S0 pull-up on PCH page
CAMERA_PWR_EN
4
HDMITBTMUX_SEL_TBT
BI
Falcon Ridge PLUG_EVENT is active-low, always driven (pull-up)
U2060
SOT891
From RR
R2062
100K
0.1UF
74LVC2G07
U2030
15
5%
1/20W
MF
201 2
2
59 37 36 29 18 13
1
2
74LVC1G08
SOT891
R2015 1
100K
100K
6
PP3V3_S0
PP3V3_TBTLC
R2061 1
NOSTUFF
CRITICAL
74 65 64 62 61
36 30 26 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
CR:
TBT_GO2SX_BIDIR,
requires 100k pull-up to SUS
RR/FR: DPHDMIMUX_SEL_TBT, requires 100k pull-up to TBTLC (on TBT page)
15 18 25
NOSTUFF
2
DP_TBTSNK1_DDC_CLK
DP_TBTSNK1_DDC_DATA
Thunderbolt Pull-up/downs
TBTLC can be on when S0 is off, and vice-versa
Isolation ensures no leakage to RR or PCH
BYPASS=U2030:3mm
C
D
TBTSNK1_DDC is pulled-up just to indicate that
DP port is used. No DDC on this port, AUX-only.
1
10%
10V
X5R-CERM
0201
5%
1/20W
MF
2 201
DP_TBTSNK0_DDC_CLK
DP_TBTSNK0_DDC_DATA
Redwood Ridge JTAG Isolation
2
PP3V3_S5
C2030
R2023
2.2K
5%
1/20W
MF
201 2
NOTE: Only DDC_DATA is sensed by PCH, so
DDC_CLK pull-ups are unstuffed.
2
PCH_TBT_PCIE_RESET_L
IN
18 13
5%
1/20W
MF
0201
5%
1/20W
MF
0201
25 18 15
2
1
2.2K
5%
1/20W
MF
2 201
56
OUT
1
37
CAM_PCIE_RESET_L
0
1
1
OUT
18 13
0
PP3V3_S5
R2088
100K
0.1UF
SMC_LRESET_L
2
5%
1/20W
MF
0201
R2070
C2071
1
34 29 28 18 17 16 15 13 11 8
74 64 62 60 59 58 57 42
R2022 1
R2021
2.2K
5%
1/20W
MF
201 2
R2042
1
1
2.2K
0
PP3V3_S0
NO STUFF
R2020 1
Scrub for Layout Optimization
PP3V3_S0
PP3V3_S0
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
5
65
41
13
30
56
74 65 64 62 61
36 30 26 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
R2041
19
5%
1/20W
MF
0201
D
17 18
PP3V3_S5RS3RS0_SYSCLKGEN
NO STUFF
0
1
DP++ spec violation, should remove!
PP3V3_S5RS3RS0_SYSCLKGEN
2
5%
1/20W
MF
0201
R2071
74
42
15
36
59
1
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
20 OF 121
SHEET
18 OF 76
1
A
6
CPU-Based Margining
1
Q2220
DDRVREF_DAC
DMN5L06VK-7
R2201
VREFMRGN_DQ_A_EN_RC
2
DDRVREF_DAC
5%
1/20W
MF
201
1
C2225
D
5%
1/20W
MF
201
10%
6.3V
CERM-X5R
0201
Always used, regardless
of margining option.
CRITICAL
DDRVREF_DAC
R2223
1%
1/20W
MF
201
Q2225 pin 6:
R2222
CPU_MEM_VREFDQ_B_ISOL
2
VER 3
5
CRITICAL
Q2220
10%
6.3V
CERM-X5R
0201
D
Q2265 pin 6:
8.2K
D
CPU_MEM_VREFCA_A_ISOL
10%
6.3V
X5R-CERM
0201
2
R2215
C2265
5%
1/20W
MF
201
D
SOT563
10%
6.3V
CERM-X5R
0201
G
24.9
2
2
R2262
3
1%
1/20W
MF
201
C2260
CPU_MEM_VREFCA_B_ISOL
C2200
1
20%
6.3V
CERM
402-LF
5%
1/20W
MF
201
C2201
2.2UF
0.1UF
2
10%
6.3V
CERM-X5R
0201
2
8
IN
SMBUS_PCH_CLK
6 SCL
BI
SMBUS_PCH_DATA
7 SDA
Addr=0x98(WR)/0x99(RD)
1
VREFMRGN_DQ_A
R2226
4.02K
1
2
2
VREFMRGN_DQ_B
R2246
4.02K
1
2
4
VREFMRGN_CA_AB
R2266
4.02K
1
2
VER 3
1%
1/20W
MF
201
PLACE_NEAR=Q2260.3:3mm
PP0V6_S3_MEM_VREFCA_B
2
1%
1/20W
MF
201
18 22 23 70
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
PLACE_NEAR=R2281.2:1mm
R2282 1
0.022UF
VREFMRGN_DQ_A_RDIV
1%
R2286
VREFMRGN_MEMVREG
4.02K
1
1/20W
MF
1/20W
2
PLACE_NEAR=Q2225.1:2.54mm
MF
201
PLACE_NEAR=Q2265.1:2.54mm
VREFMRGN_CA_A_RDIV
1/20W
MF
1%
1/20W
MF
2
R2280
MEM_VREFCA_B_RC
1
24.9
2
PLACE_NEAR=Q2225.4:2.54mm
1%
1/20W
MF
201
201
PLACE_NEAR=Q2265.4:2.54mm
VREFMRGN_CA_B_RDIV
2
10%
6.3V
X5R-CERM
0201
R22x6 pin 2:
201
VREFMRGN_DQ_B_RDIV
1%
5
1%
1/20W
MF
201
C2280
1
1%
VOUTD
2
8.2K
VOUTC
10 A1
R2281
8.2K
PLACE_NEAR=Q2260.3:2mm
MSOP
9 A0
2
10
1
2
(All 4 R’s)
DDRVREF_DAC
VOUTB
U2200 VOUTA
24.9
1
1%
1/20W
MF
201
R2283
2
CRITICAL
DDRVREF_DAC
DAC5574
56 40 19 16 14
69
1
DMN5L06VK-7
SOT563
0.1UF
10%
6.3V
CERM-X5R
0201
VDD
56 40 19 16 14
69
C2285
100K
DDRVREF_DAC
1
MEM_VREFCA_A_RC
D
R2207
DDRVREF_DAC
R2260
Q2265
1
C
2
3
NONE
NONE
NONE
402
1
DDRVREF_DAC
5%
1/20W
MF
201
CRITICAL
DDRVREF_DAC
S
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
DDRVREF_DAC
VREFMRGN_CA_B_EN_RC
4
PP3V3_S3_VREFMRGN_DAC
2
2
G
100K
5
R2285
1
10%
6.3V
X5R-CERM
0201
2
DDRVREF_DAC
R2218
1
18 20 21 70
1
8.2K
PLACE_NEAR=Q2220.3:2mm
1
DAC sets voltage level, PCA9557 & FETs enable outputs
and disables margining after platform reset.
OMIT
SHORT
PLACE_NEAR=Q2220.3:3mm
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
PLACE_NEAR=R2261.2:1mm
0.022UF
PP3V3_S3
1%
1/20W
MF
201
PP0V6_S3_MEM_VREFCA_A
2
1%
1/20W
MF
201
2
R2261
8.2K
10
1
DAC-Based Margining
36 33 19 18 15
64 62 58 41 40
1
2
1%
1/20W
MF
201
R2263
SOT563
1
0.1UF
100K
DMN5L06VK-7
S
1
1
DMN5L06VK-7
D
Q2260
DDRVREF_DAC
5%
1/20W
MF
201
MEM_VREFDQ_B_RC
Q2225
S
DDRVREF_DAC
CRITICAL
DDRVREF_DAC
4
VER 3
5
G
CRITICAL
VREFMRGN_CA_A_EN_RC
2
2
R2240
3
100K
5
R2265
4
1%
1/20W
MF
201
C2240
DDRVREF_DAC
1
18 22 23 70
R2242 1
0.022UF
VER 3
NOTE: CPU has single output for
VREFCA. Split into two
signals for independent DAC
margining support. When
DAC margining VREFCA ensure
VREFMRGN_CPU_EN is low
to remove short due to CPU.
PLACE_NEAR=Q2260.6:3mm
PP0V6_S3_MEM_VREFDQ_B
PLACE_NEAR=Q2260.6:2mm
1
3
S
CPU_DIMM_VREFCA
1%
1/20W
MF
201
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
PLACE_NEAR=R2241.2:1mm
PLACE_NEAR=Q2260.6:2.54mm
DMN5L06VK-7
4
IN
R2241
8.2K
2
2
1%
1/20W
MF
201
SOT563
7
1
2
10
1
2
2
24.9
1%
1/20W
MF
201
R2243
SOT563
0.1UF
1
DMN5L06VK-7
1
D
2
R2220
MEM_VREFDQ_A_RC
Q2265
1
5%
1/20W
MF
201
CRITICAL
DDRVREF_DAC
S
C2245
100K
VER 3
DDRVREF_DAC
5%
1/20W
MF
201
1
G
6
R2202
step sizes:
7.70mV per step
6.99mV per step
?.??mV per step
VREFMRGN_DQ_B_EN_RC
2
18 20 21 70
1
6
D
100K
1
DDRVREF_DAC
G
NOTE: CPU DAC output
DDR3
(1.5V)
DDR3L (1.35V)
LPDDR3 (1.2V)
10%
6.3V
X5R-CERM
0201
DDRVREF_DAC
2
VER 3
2
G
CPU_DIMMB_VREFDQ
1
IN
S
7
1%
1/20W
MF
201
0.022UF
R2245
PLACE_NEAR=Q2220.6:3mm
8.2K
C2220
CRITICAL
Q2260
1%
1/20W
MF
201
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
PLACE_NEAR=R2221.2:1mm
PLACE_NEAR=Q2220.6:2mm
1
DMN5L06VK-7
R2221
PP0V6_S3_MEM_VREFDQ_A
2
PLACE_NEAR=Q2220.6:2.54mm
SOT563
C
2
10
1
2
2
17 20 21 22 23 42 53 62 70
8.2K
DMN5L06VK-7
SOT563
BOM options provided by this page:
- DDRVREF_DAC - Stuffs DAC margining circuit.
1
Q2225
1
0.1UF
100K
6
S
CPU_DIMMA_VREFDQ
1
IN
EN RC’s to avoid drain glitches
May not be necessary due to C22x0
D
100K
PP1V2_S3
VRef Dividers
VER 3
R2225
1
6
VER 3
2
G
DDRVREF_DAC
CRITICAL
SOT563
7
2
CPU_MEM_VREFDQ_A_ISOL
FETs for CPU isolation during DAC margining
Signal aliases required by this page:
- =I2C_VREFDACS_SCL
- =I2C_VREFDACS_SDA
- =I2C_PCA9557D_SCL
- =I2C_PCA9557D_SDA
3
2
Power aliases required by this page:
- =PP3V3_S3_VREFMRGN
- =PPDDR_S3_MEMVREF
D
4
G
Page Notes
5
S
7
1
8
201
GND
3
NOTE: MEMVREG and SPARE share a
DAC output, cannot enable
both at the same time!
PP3V3_S3
B
C2202
16
DDRVREF_DAC
1
5%
1/20W
MF
201
PCA9557
QFN
(OD)
4
5
69 56 40 19 16 14
69 56 40 19 16 14
IN
BI
SMBUS_PCH_CLK
SMBUS_PCH_DATA
1
2
A0
A1
A2
SCL
SDA
THRM
17
PAD
RST* on ’platform reset’ so that system
watchdog will disable margining.
P0
P1
P2
P3
P4
P5
P6
P7
RESET*
7
9
10
11
12
13
14
IN
C2
V+
C3
R2214
MAX4253
UCSP
VREFMRGN_MEMVREG_BUF
38.3K
1
V-
R2213
NC
5%
1/20W
MF
201
OUT
53
1
100K
15
DDRREG_FB
PLACE_NEAR=R7415.2:1mm
CRITICAL
DDRVREF_DAC
DDRVREF_DAC
GND
2
1%
1/20W
MF
201
C4
B4
B1
A2
V+
U2204
MAX4253
UCSP
2
A1
A3
NOTE: Margining will be disabled across all
soft-resets and sleep/wake cycles.
18
B
DDRVREF_DAC
U2204
C1
VREFMRGN_CPU_EN
VREFMRGN_DQ_A_EN
VREFMRGN_DQ_B_EN
VREFMRGN_CA_A_EN
VREFMRGN_CA_B_EN
VREFMRGN_MEMVREG_EN
VREFMRGN_SPARE_EN
6
2
B1
2
8
3
Addr=0x30(WR)/0x31(RD)
10%
6.3V
CERM-X5R
0201
100K
U2201
2
1
0.1UF
R2200 1
VCC
0.1UF
10%
6.3V
CERM-X5R
0201
C2205
CRITICAL
DDRVREF_DAC
15 18 19 33 36 40 41 58 62 64
CRITICAL
DDRVREF_DAC
DDRVREF_DAC
VREFMRGN_SPARE_BUF
DDRVREF_DAC
A4
V-
1
B4
R2217
1M
Pins B1 & B4:
CKPLUS_WAIVE=unconnected_pins
PCA9557D_RESET_L
2
DDRVREF_DAC
5%
1/20W
MF
201
R2212 1
100K
A
MEM A VREF DQ
DAC Channel:
MEM B VREF DQ
A
PCA9557D Pin:
B
2
SYNC_MASTER=J41_MLB
4
DDR3 VREF MARGINING
5
LPDDR3 (1.2V)
0.675V (DAC: 0x34)
DDR3L (1.35V)
1.200V (DAC: 0x5D)
0.300V - 0.900V (+/- 300mV)
0.337V - 1.013V (+/- 337.5mV)
0.800V - 1.600V (+/- 400mV)
0.000V - 1.199V (0x00 - 0x5D)
0.000V - 1.354V (0x00 - 0x69)
0.000V - 2.397V (0x00 - 0xBA)
NOTICE OF PROPRIETARY PROPERTY:
0.000V - 2.694V (0x00 - 0xD1)
DAC step size:
(- = sourced)
+82uA - -82uA
6.36mV / step @ output
8
(- = sourced)
+21uA -
6.36mV / step @ output
7
-21uA (- = sourced)
+25uA -
4.28mV / step @ output
6
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
-25uA (- = sourced)
3.53mV / step @ output
5
& lt; SCH_NUM & gt;
REVISION
R
0.972V - 1.714V (+/- 371mV)
DAC range:
+73uA - -73uA
DRAWING NUMBER
NOTE: LPDDR3 assumes TPS51916 supply with 28.7k/57.6k divider
DDR3L assumes TPS51916 supply with 19.6k/57.6k divider
1.343V (DAC: 0x68)
Margined target:
VRef current:
SYNC_DATE=02/12/2013
PAGE TITLE
D
DDR3L (1.35V)
0.600V (DAC: 0x2E.5)
5%
1/20W
MF
201
MEM VREG
C
3
LPDDR3 (1.2V)
Nominal value
MEM B VREF CA
C
2
1
MEM A VREF CA
4
3
2
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
22 OF 121
SHEET
19 OF 76
1
SIZE
D
A
8
7
6
5
4
3
2
1
LPDDR3 CHANNEL A (0-31)
D
D
U2300
U2300
LPDDR3-16GB
LPDDR3-16GB
FBGA
70 63 24
IN
70 63 24
IN
70 63 24
IN
70 63 24
IN
70 63 24
IN
70 63 24 7
IN
70 63 24
IN
70 63 24
IN
70 63 24
IN
70 24 7
IN
70 24 7
IN
70 24 7
70 24 7
C
70 24 21 7
70 24 21 7
IN
IN
IN
IN
MEM_A_CAA & lt; 0 & gt;
MEM_A_CAA & lt; 1 & gt;
MEM_A_CAA & lt; 2 & gt;
MEM_A_CAA & lt; 3 & gt;
MEM_A_CAA & lt; 4 & gt;
MEM_A_CAA & lt; 5 & gt;
MEM_A_CAA & lt; 6 & gt;
MEM_A_CAA & lt; 7 & gt;
MEM_A_CAA & lt; 8 & gt;
MEM_A_CAA & lt; 9 & gt;
R2
MEM_A_CKE & lt; 0 & gt;
MEM_A_CKE & lt; 1 & gt;
K3
P2
N2
N3
M3
F3
E3
E2
D2
C2
K4
J3
MEM_A_CLK_P & lt; 0 & gt;
MEM_A_CLK_N & lt; 0 & gt;
J2
L3
MEM_A_CS_L & lt; 0 & gt;
MEM_A_CS_L & lt; 1 & gt;
L4
L8
G8
P8
D8
70 63 24 21 7
IN
J8
MEM_A_ODT & lt; 0 & gt;
B3
MEM_A_ZQ & lt; 0 & gt;
MEM_A_ZQ & lt; 1 & gt;
R2300
1
R2301
243
1%
1/20W
MF
201
70 21 19 18
243
1%
1/20W
MF
201
1
2
70 21 19 18
2
C2340
1
1
0.047UF
10%
6.3V
X5R
201
B4
H4
PP0V6_S3_MEM_VREFCA_A
PP0V6_S3_MEM_VREFDQ_A
J11
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
C2341
0.047UF
2
2
10%
6.3V
X5R
201
B
FBGA
(1 OF 2)
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
CKE0
CKE1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
OMIT_TABLE
CRITICAL
CK_T
CK_C
CS0*
CS1*
DM0
DM1
DM2
DM3
ODT
ZQ0
ZQ1
VREFCA
VREFDQ
A1
A2
P9
=MEM_A_DQ & lt; 0 & gt;
=MEM_A_DQ & lt; 1 & gt;
=MEM_A_DQ & lt; 2 & gt;
=MEM_A_DQ & lt; 3 & gt;
=MEM_A_DQ & lt; 4 & gt;
=MEM_A_DQ & lt; 5 & gt;
=MEM_A_DQ & lt; 6 & gt;
=MEM_A_DQ & lt; 7 & gt;
=MEM_A_DQ & lt; 8 & gt;
=MEM_A_DQ & lt; 9 & gt;
=MEM_A_DQ & lt; 10 & gt;
=MEM_A_DQ & lt; 11 & gt;
=MEM_A_DQ & lt; 12 & gt;
=MEM_A_DQ & lt; 13 & gt;
=MEM_A_DQ & lt; 14 & gt;
=MEM_A_DQ & lt; 15 & gt;
=MEM_A_DQ & lt; 16 & gt;
=MEM_A_DQ & lt; 17 & gt;
=MEM_A_DQ & lt; 18 & gt;
=MEM_A_DQ & lt; 19 & gt;
=MEM_A_DQ & lt; 20 & gt;
=MEM_A_DQ & lt; 21 & gt;
=MEM_A_DQ & lt; 22 & gt;
=MEM_A_DQ & lt; 23 & gt;
=MEM_A_DQ & lt; 24 & gt;
=MEM_A_DQ & lt; 25 & gt;
=MEM_A_DQ & lt; 26 & gt;
=MEM_A_DQ & lt; 27 & gt;
=MEM_A_DQ & lt; 28 & gt;
=MEM_A_DQ & lt; 29 & gt;
=MEM_A_DQ & lt; 30 & gt;
=MEM_A_DQ & lt; 31 & gt;
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8
BI
63
BI
63
BI
A5
A6
A10
63
BI
U3
63
BI
63
VDD1
U4
U5
BI
63
BI
63
BI
63
BI
63
BI
63
63
D4
BI
63
63
63
63
63
F5
J12
K2
H5
BI
E5
G5
BI
E4
D6
BI
C5
D5
BI
B5
A9
BI
B2
H6
U6
L6
U10
70 62 53 42 23 22 21 20 19 17
PP1V2_S3
M5
A8
OMIT_TABLE
VSS
N5
R4
CRITICAL
T2
T3
DQS0_C
DQS1_C
DQS2_C
DQS3_C
DQS0_T
DQS1_T
DQS2_T
DQS3_T
B1
B13
NU
T13
U1
U2
U12
L11
T5
H2
BI
63
H12
BI
63
J5
BI
63
J6
BI
63
K5
BI
63
K6
BI
63
K12
BI
63
L5
P3
BI
63
P4
M4
BI
63
P5
J4
BI
63
P6
BI
63
U8
BI
63
U9
BI
63
BI
L10
=MEM_A_DQS_N & lt; 0 & gt;
=MEM_A_DQS_N & lt; 1 & gt;
=MEM_A_DQS_N & lt; 2 & gt;
=MEM_A_DQS_N & lt; 3 & gt;
G11
P11
D11
63
C3
D3
VDD2
F4
G3
VSSCA
G10
P10
D10
G4
B6
B12
C6
70 62 53 42 23 22 21 20 19 17
PP1V2_S3
F2
BI
63
BI
63
BI
63
BI
D12
E6
63
BI
63
BI
63
E8
BI
63
E12
BI
63
G12
H3
F6
VDDCA
F12
L2
M2
G6
G9
70 62 53 42 23 22 21 20 19 17
=MEM_A_DQS_P & lt; 0 & gt;
=MEM_A_DQS_P & lt; 1 & gt;
=MEM_A_DQS_P & lt; 2 & gt;
=MEM_A_DQS_P & lt; 3 & gt;
C
T4
G2
A13
N4
R5
A12
T1
(2 OF 2)
A3
A4
63
BI
PP1V8_S3
63
BI
62 57 23 22 21 20
EDFA232A1MA-GD-F
IN
EDFA232A1MA-GD-F
70 63 24
PP1V2_S3
A11
H10
C12
VSSQ
K10
L9
M6
U13
M12
B
H8
N6
NC
NC
NC
H9
C4
P12
K9
H11
NC
R6
J9
R3
T6
J10
VDDQ
T12
K8
K11
70 62 53 42 23 22 21 20 19 17
PP1V2_S3
L12
N8
1
C2300
1
0.1UF
2
70 62 53 42 23 22 21 20 19 17
C2301
1
0.1UF
10%
16V
X5R-CERM
0201
C2302
1
1UF
2
10%
16V
X5R-CERM
0201
2
1
C2321
1
10%
10V
X5R
402
C2303
1UF
2
10%
10V
X5R
402
C2304
1
1UF
2
10%
10V
X5R
402
C2305
1
1UF
2
10%
10V
X5R
402
C2306
1
10UF
2
20%
25V
X5R-CERM
0603
C2307
N12
10UF
2
20%
25V
X5R-CERM
0603
R12
U11
PP1V2_S3
1
C2320
C2322
1
C2323
1UF
2
70 62 53 42 23 22 21 20 19 17
1
1UF
1UF
10%
10V
X5R
402
10%
10V
X5R
402
20%
25V
X5R-CERM
0603
1
10UF
10%
10V
X5R
402
2
2
2
C2324
10UF
2
20%
25V
X5R-CERM
0603
PP1V2_S3
1
C2310
1
C2311
1
A
2
PLACEMENT_NOTE:
C2312
1UF
1UF
10UF
10%
10V
X5R
402
10%
10V
X5R
402
20%
25V
X5R-CERM
0603
2
2
10uF caps are shared between DRAM.
Distribute evenly.
SYNC_MASTER=J41_MLB
SYNC_DATE=02/06/2013
PAGE TITLE
LPDDR3 DRAM Channel A (0-31)
DRAWING NUMBER
62 57 23 22 21 20
PP1V8_S3
Apple Inc.
1
C2330
1
1UF
2
8
7
C2331
1
1UF
10%
10V
X5R
402
2
6
10%
10V
X5R
402
C2332
1
10UF
2
20%
25V
X5R-CERM
0603
R
C2333
& lt; E4LABEL & gt;
10UF
2
& lt; SCH_NUM & gt;
REVISION
NOTICE OF PROPRIETARY PROPERTY:
20%
25V
X5R-CERM
0603
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
5
4
3
2
BRANCH
& lt; BRANCH & gt;
PAGE
23 OF 121
SHEET
20 OF 76
1
SIZE
D
A
8
7
6
5
4
3
2
1
LPDDR3 CHANNEL A (32-63)
D
D
U2400
U2400
LPDDR3-16GB
LPDDR3-16GB
FBGA
70 63 24
IN
70 63 24
IN
70 63 24
IN
70 63 24
IN
70 63 24
IN
70 63 24 7
IN
70 63 24
IN
70 63 24
IN
70 63 24
IN
70 24 7
IN
70 24 7
IN
70 24 7
70 24 7
C
70 24 20 7
70 24 20 7
IN
IN
IN
IN
MEM_A_CAB & lt; 0 & gt;
MEM_A_CAB & lt; 1 & gt;
MEM_A_CAB & lt; 2 & gt;
MEM_A_CAB & lt; 3 & gt;
MEM_A_CAB & lt; 4 & gt;
MEM_A_CAB & lt; 5 & gt;
MEM_A_CAB & lt; 6 & gt;
MEM_A_CAB & lt; 7 & gt;
MEM_A_CAB & lt; 8 & gt;
MEM_A_CAB & lt; 9 & gt;
R2
MEM_A_CKE & lt; 2 & gt;
MEM_A_CKE & lt; 3 & gt;
K3
P2
N2
N3
M3
F3
E3
E2
D2
C2
K4
J3
MEM_A_CLK_P & lt; 1 & gt;
MEM_A_CLK_N & lt; 1 & gt;
J2
L3
MEM_A_CS_L & lt; 0 & gt;
MEM_A_CS_L & lt; 1 & gt;
L4
L8
G8
P8
D8
70 63 24 20 7
IN
J8
MEM_A_ODT & lt; 0 & gt;
B3
MEM_A_ZQ & lt; 2 & gt;
MEM_A_ZQ & lt; 3 & gt;
R2400
1
R2401
243
1%
1/20W
MF
201
70 20 19 18
243
1%
1/20W
MF
201
1
2
70 20 19 18
2
C2440
1
1
0.047UF
10%
6.3V
X5R
201
B4
H4
PP0V6_S3_MEM_VREFCA_A
PP0V6_S3_MEM_VREFDQ_A
J11
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
C2441
0.047UF
2
2
10%
6.3V
X5R
201
B
FBGA
(1 OF 2)
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
CKE0
CKE1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
OMIT_TABLE
CRITICAL
CK_T
CK_C
CS0*
CS1*
DM0
DM1
DM2
DM3
ODT
ZQ0
ZQ1
VREFCA
VREFDQ
A1
A2
P9
=MEM_A_DQ & lt; 32 & gt;
=MEM_A_DQ & lt; 33 & gt;
=MEM_A_DQ & lt; 34 & gt;
=MEM_A_DQ & lt; 35 & gt;
=MEM_A_DQ & lt; 36 & gt;
=MEM_A_DQ & lt; 37 & gt;
=MEM_A_DQ & lt; 38 & gt;
=MEM_A_DQ & lt; 39 & gt;
=MEM_A_DQ & lt; 40 & gt;
=MEM_A_DQ & lt; 41 & gt;
=MEM_A_DQ & lt; 42 & gt;
=MEM_A_DQ & lt; 43 & gt;
=MEM_A_DQ & lt; 44 & gt;
MEM_A_DQ & lt; 33 & gt;
=MEM_A_DQ & lt; 46 & gt;
=MEM_A_DQ & lt; 47 & gt;
=MEM_A_DQ & lt; 48 & gt;
=MEM_A_DQ & lt; 49 & gt;
=MEM_A_DQ & lt; 50 & gt;
=MEM_A_DQ & lt; 51 & gt;
=MEM_A_DQ & lt; 52 & gt;
=MEM_A_DQ & lt; 53 & gt;
=MEM_A_DQ & lt; 54 & gt;
=MEM_A_DQ & lt; 55 & gt;
=MEM_A_DQ & lt; 56 & gt;
=MEM_A_DQ & lt; 57 & gt;
=MEM_A_DQ & lt; 58 & gt;
=MEM_A_DQ & lt; 59 & gt;
=MEM_A_DQ & lt; 60 & gt;
=MEM_A_DQ & lt; 61 & gt;
=MEM_A_DQ & lt; 62 & gt;
=MEM_A_DQ & lt; 63 & gt;
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8
BI
63
BI
63
BI
A5
A6
A10
63
BI
U3
63
BI
63
VDD1
U4
U5
BI
63
BI
63
BI
63
BI
63
BI
63
63
D4
BI
7 63 70
63
63
63
63
F5
J12
K2
H5
BI
E5
G5
BI
E4
D6
BI
C5
D5
BI
B5
A9
BI
B2
H6
U6
L6
U10
70 62 53 42 23 22 21 20 19 17
PP1V2_S3
M5
A8
OMIT_TABLE
VSS
N5
R4
CRITICAL
T2
T3
DQS0_C
DQS1_C
DQS2_C
DQS3_C
DQS0_T
DQS1_T
DQS2_T
DQS3_T
B1
B13
NU
T13
U1
U2
U12
L11
T5
H2
BI
63
H12
BI
63
J5
BI
63
J6
BI
63
K5
BI
63
K6
BI
63
K12
BI
63
L5
P3
BI
63
P4
M4
BI
63
P5
J4
BI
63
P6
BI
63
U8
BI
63
U9
BI
63
BI
L10
=MEM_A_DQS_N & lt; 4 & gt;
=MEM_A_DQS_N & lt; 5 & gt;
MEM_A_DQS_N & lt; 6 & gt;
=MEM_A_DQS_N & lt; 7 & gt;
G11
P11
D11
63
C3
D3
VDD2
F4
G3
VSSCA
G10
P10
D10
G4
B6
B12
C6
70 62 53 42 23 22 21 20 19 17
BI
PP1V2_S3
63
BI
63
BI
7 63 70
BI
F2
D12
E6
63
BI
63
H3
F6
VDDCA
F12
L2
M2
G6
G9
70 62 53 42 23 22 21 20 19 17
=MEM_A_DQS_P & lt; 4 & gt;
=MEM_A_DQS_P & lt; 5 & gt;
MEM_A_DQS_P & lt; 6 & gt;
=MEM_A_DQS_P & lt; 7 & gt;
C
T4
G2
A13
N4
R5
A12
T1
(2 OF 2)
A3
A4
63
BI
PP1V8_S3
63
BI
62 57 23 22 21 20
EDFA232A1MA-GD-F
IN
EDFA232A1MA-GD-F
70 63 24
PP1V2_S3
A11
H10
C12
BI
63
BI
7 63 70
BI
63
VSSQ
K10
E12
G12
E8
L9
M6
U13
M12
B
H8
N6
NC
NC
NC
H9
C4
P12
K9
H11
NC
R6
J9
R3
T6
J10
VDDQ
T12
K8
K11
70 62 53 42 23 22 21 20 19 17
PP1V2_S3
L12
N8
1
C2400
1
0.1UF
2
70 62 53 42 23 22 21 20 19 17
C2401
1
0.1UF
10%
16V
X5R-CERM
0201
C2402
1UF
2
10%
16V
X5R-CERM
0201
2
1
C2421
1
10%
10V
X5R
402
C2403
1
1UF
2
10%
10V
X5R
402
C2404
1
1UF
2
10%
10V
X5R
402
C2405
1
1UF
2
10%
10V
X5R
402
C2406
N12
10UF
2
R12
20%
25V
X5R-CERM
0603
U11
PP1V2_S3
1
C2420
C2422
1UF
2
70 62 53 42 23 22 21 20 19 17
1
1UF
10%
10V
X5R
402
10%
10V
X5R
402
1
1UF
10%
10V
X5R
402
2
2
C2423
10UF
2
20%
25V
X5R-CERM
0603
PP1V2_S3
1
C2410
1
C2411
1
A
2
PLACEMENT_NOTE:
C2412
1UF
1UF
10UF
10%
10V
X5R
402
10%
10V
X5R
402
20%
25V
X5R-CERM
0603
2
2
10uF caps are shared between DRAM.
Distribute evenly.
SYNC_MASTER=J41_MLB
SYNC_DATE=02/06/2013
PAGE TITLE
LPDDR3 DRAM Channel A (32-63)
DRAWING NUMBER
62 57 23 22 21 20
PP1V8_S3
Apple Inc.
1
C2430
1
1UF
2
8
7
C2431
1
1UF
10%
10V
X5R
402
2
6
10%
10V
X5R
402
R
C2432
& lt; E4LABEL & gt;
10UF
2
& lt; SCH_NUM & gt;
REVISION
NOTICE OF PROPRIETARY PROPERTY:
20%
25V
X5R-CERM
0603
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
5
4
3
2
BRANCH
& lt; BRANCH & gt;
PAGE
24 OF 121
SHEET
21 OF 76
1
SIZE
D
A
8
7
6
5
4
3
2
1
LPDDR3 CHANNEL B (0-31)
D
D
U2500
U2500
LPDDR3-16GB
LPDDR3-16GB
FBGA
70 63 24
IN
70 63 24
IN
70 63 24
IN
70 63 24
IN
70 63 24
IN
70 63 24 7
IN
70 63 24
IN
70 63 24
IN
70 63 24
IN
70 24 7
IN
70 24 7
IN
70 24 7
70 24 7
C
70 24 23 7
70 24 23 7
IN
IN
IN
IN
MEM_B_CAA & lt; 0 & gt;
MEM_B_CAA & lt; 1 & gt;
MEM_B_CAA & lt; 2 & gt;
MEM_B_CAA & lt; 3 & gt;
MEM_B_CAA & lt; 4 & gt;
MEM_B_CAA & lt; 5 & gt;
MEM_B_CAA & lt; 6 & gt;
MEM_B_CAA & lt; 7 & gt;
MEM_B_CAA & lt; 8 & gt;
MEM_B_CAA & lt; 9 & gt;
R2
MEM_B_CKE & lt; 0 & gt;
MEM_B_CKE & lt; 1 & gt;
K3
P2
N2
N3
M3
F3
E3
E2
D2
C2
K4
J3
MEM_B_CLK_P & lt; 0 & gt;
MEM_B_CLK_N & lt; 0 & gt;
J2
L3
MEM_B_CS_L & lt; 0 & gt;
MEM_B_CS_L & lt; 1 & gt;
L4
L8
G8
P8
D8
70 63 24 23 7
IN
J8
MEM_B_ODT & lt; 0 & gt;
B3
MEM_B_ZQ & lt; 0 & gt;
MEM_B_ZQ & lt; 1 & gt;
R2500
1
R2501
243
1%
1/20W
MF
201
70 23 19 18
243
1%
1/20W
MF
201
1
2
70 23 19 18
2
C2540
1
1
0.047UF
10%
6.3V
X5R
201
B4
H4
PP0V6_S3_MEM_VREFCA_B
PP0V6_S3_MEM_VREFDQ_B
J11
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
C2541
0.047UF
2
2
10%
6.3V
X5R
201
B
FBGA
(1 OF 2)
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
CKE0
CKE1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
OMIT_TABLE
CRITICAL
CK_T
CK_C
CS0*
CS1*
DM0
DM1
DM2
DM3
ODT
ZQ0
ZQ1
VREFCA
VREFDQ
A1
A2
P9
=MEM_B_DQ & lt; 0 & gt;
=MEM_B_DQ & lt; 1 & gt;
=MEM_B_DQ & lt; 2 & gt;
=MEM_B_DQ & lt; 3 & gt;
=MEM_B_DQ & lt; 4 & gt;
=MEM_B_DQ & lt; 5 & gt;
=MEM_B_DQ & lt; 6 & gt;
=MEM_B_DQ & lt; 7 & gt;
=MEM_B_DQ & lt; 8 & gt;
=MEM_B_DQ & lt; 9 & gt;
=MEM_B_DQ & lt; 10 & gt;
=MEM_B_DQ & lt; 11 & gt;
=MEM_B_DQ & lt; 12 & gt;
=MEM_B_DQ & lt; 13 & gt;
=MEM_B_DQ & lt; 14 & gt;
=MEM_B_DQ & lt; 15 & gt;
=MEM_B_DQ & lt; 16 & gt;
=MEM_B_DQ & lt; 17 & gt;
=MEM_B_DQ & lt; 18 & gt;
=MEM_B_DQ & lt; 19 & gt;
=MEM_B_DQ & lt; 20 & gt;
=MEM_B_DQ & lt; 21 & gt;
=MEM_B_DQ & lt; 22 & gt;
=MEM_B_DQ & lt; 23 & gt;
=MEM_B_DQ & lt; 24 & gt;
=MEM_B_DQ & lt; 25 & gt;
=MEM_B_DQ & lt; 26 & gt;
=MEM_B_DQ & lt; 27 & gt;
=MEM_B_DQ & lt; 28 & gt;
=MEM_B_DQ & lt; 29 & gt;
=MEM_B_DQ & lt; 30 & gt;
=MEM_B_DQ & lt; 31 & gt;
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8
BI
63
BI
63
BI
A5
A6
A10
63
BI
U3
63
BI
63
VDD1
U4
U5
BI
63
BI
63
BI
63
BI
63
BI
63
63
D4
BI
63
63
63
63
63
F5
J12
K2
H5
BI
E5
G5
BI
E4
D6
BI
C5
D5
BI
B5
A9
BI
B2
H6
U6
L6
U10
70 62 53 42 23 22 21 20 19 17
PP1V2_S3
M5
A8
OMIT_TABLE
VSS
N5
R4
CRITICAL
T2
T3
DQS0_C
DQS1_C
DQS2_C
DQS3_C
DQS0_T
DQS1_T
DQS2_T
DQS3_T
B1
B13
NU
T13
U1
U2
U12
L11
T5
H2
BI
63
H12
BI
63
J5
BI
63
J6
BI
63
K5
BI
63
K6
BI
63
K12
BI
63
L5
P3
BI
63
P4
M4
BI
63
P5
J4
BI
63
P6
BI
63
U8
BI
63
U9
BI
63
BI
L10
=MEM_B_DQS_N & lt; 0 & gt;
=MEM_B_DQS_N & lt; 1 & gt;
=MEM_B_DQS_N & lt; 2 & gt;
=MEM_B_DQS_N & lt; 3 & gt;
G11
P11
D11
63
C3
D3
VDD2
F4
G3
VSSCA
G10
P10
D10
G4
B6
B12
C6
70 62 53 42 23 22 21 20 19 17
PP1V2_S3
F2
BI
63
BI
63
BI
63
BI
D12
E6
63
BI
63
BI
63
E8
BI
63
E12
BI
63
G12
H3
F6
VDDCA
F12
L2
M2
G6
G9
70 62 53 42 23 22 21 20 19 17
=MEM_B_DQS_P & lt; 0 & gt;
=MEM_B_DQS_P & lt; 1 & gt;
=MEM_B_DQS_P & lt; 2 & gt;
=MEM_B_DQS_P & lt; 3 & gt;
C
T4
G2
A13
N4
R5
A12
T1
(2 OF 2)
A3
A4
63
BI
PP1V8_S3
63
BI
62 57 23 22 21 20
EDFA232A1MA-GD-F
IN
EDFA232A1MA-GD-F
70 63 24
PP1V2_S3
A11
H10
C12
VSSQ
K10
L9
M6
U13
M12
B
H8
N6
NC
NC
NC
H9
C4
P12
K9
H11
NC
R6
J9
R3
T6
J10
VDDQ
T12
K8
K11
70 62 53 42 23 22 21 20 19 17
PP1V2_S3
L12
N8
1
C2500
1
0.1UF
2
70 62 53 42 23 22 21 20 19 17
C2501
1
0.1UF
10%
16V
X5R-CERM
0201
C2502
1UF
2
10%
16V
X5R-CERM
0201
2
1
C2521
1
10%
10V
X5R
402
C2503
1
1UF
2
10%
10V
X5R
402
C2504
1
1UF
2
10%
10V
X5R
402
C2505
1
1UF
2
10%
10V
X5R
402
C2506
N12
10UF
2
R12
20%
25V
X5R-CERM
0603
U11
PP1V2_S3
1
C2520
C2522
1UF
2
70 62 53 42 23 22 21 20 19 17
1
1UF
10%
10V
X5R
402
10%
10V
X5R
402
1
1UF
10%
10V
X5R
402
2
2
C2523
10UF
2
20%
25V
X5R-CERM
0603
PP1V2_S3
1
C2510
1
C2511
1
A
2
PLACEMENT_NOTE:
C2512
1UF
1UF
10UF
10%
10V
X5R
402
10%
10V
X5R
402
20%
25V
X5R-CERM
0603
2
2
10uF caps are shared between DRAM.
Distribute evenly.
SYNC_MASTER=J41_MLB
SYNC_DATE=02/06/2013
PAGE TITLE
LPDDR3 DRAM Channel B (0-31)
DRAWING NUMBER
62 57 23 22 21 20
PP1V8_S3
Apple Inc.
1
C2530
1
1UF
2
8
7
C2531
1
1UF
10%
10V
X5R
402
2
6
10%
10V
X5R
402
R
C2532
& lt; E4LABEL & gt;
10UF
2
& lt; SCH_NUM & gt;
REVISION
NOTICE OF PROPRIETARY PROPERTY:
20%
25V
X5R-CERM
0603
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
5
4
3
2
BRANCH
& lt; BRANCH & gt;
PAGE
25 OF 121
SHEET
22 OF 76
1
SIZE
D
A
8
7
6
5
4
3
2
1
LPDDR3 CHANNEL B (32-63)
D
D
U2600
U2600
LPDDR3-16GB
LPDDR3-16GB
FBGA
70 63 24
IN
70 63 24
IN
70 63 24
IN
70 63 24
IN
70 63 24
IN
70 63 24 7
IN
70 63 24
IN
70 63 24
IN
70 63 24
IN
70 24 7
IN
70 24 7
IN
70 24 7
70 24 7
C
70 24 22 7
70 24 22 7
IN
IN
IN
IN
MEM_B_CAB & lt; 0 & gt;
MEM_B_CAB & lt; 1 & gt;
MEM_B_CAB & lt; 2 & gt;
MEM_B_CAB & lt; 3 & gt;
MEM_B_CAB & lt; 4 & gt;
MEM_B_CAB & lt; 5 & gt;
MEM_B_CAB & lt; 6 & gt;
MEM_B_CAB & lt; 7 & gt;
MEM_B_CAB & lt; 8 & gt;
MEM_B_CAB & lt; 9 & gt;
R2
MEM_B_CKE & lt; 2 & gt;
MEM_B_CKE & lt; 3 & gt;
K3
P2
N2
N3
M3
F3
E3
E2
D2
C2
K4
J3
MEM_B_CLK_P & lt; 1 & gt;
MEM_B_CLK_N & lt; 1 & gt;
J2
L3
MEM_B_CS_L & lt; 0 & gt;
MEM_B_CS_L & lt; 1 & gt;
L4
L8
G8
P8
D8
70 63 24 22 7
IN
J8
MEM_B_ODT & lt; 0 & gt;
B3
MEM_B_ZQ & lt; 2 & gt;
MEM_B_ZQ & lt; 3 & gt;
R2600
1
R2601
243
1%
1/20W
MF
201
70 22 19 18
243
1%
1/20W
MF
201
1
2
70 22 19 18
2
C2640
1
1
0.047UF
10%
6.3V
X5R
201
B4
H4
PP0V6_S3_MEM_VREFCA_B
PP0V6_S3_MEM_VREFDQ_B
J11
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
C2641
0.047UF
2
2
10%
6.3V
X5R
201
B
FBGA
(1 OF 2)
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
CKE0
CKE1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
OMIT_TABLE
CRITICAL
CK_T
CK_C
CS0*
CS1*
DM0
DM1
DM2
DM3
ODT
ZQ0
ZQ1
VREFCA
VREFDQ
A1
A2
P9
=MEM_B_DQ & lt; 32 & gt;
=MEM_B_DQ & lt; 33 & gt;
=MEM_B_DQ & lt; 34 & gt;
=MEM_B_DQ & lt; 35 & gt;
=MEM_B_DQ & lt; 36 & gt;
=MEM_B_DQ & lt; 37 & gt;
=MEM_B_DQ & lt; 38 & gt;
=MEM_B_DQ & lt; 39 & gt;
MEM_B_DQ & lt; 32 & gt;
=MEM_B_DQ & lt; 41 & gt;
=MEM_B_DQ & lt; 42 & gt;
=MEM_B_DQ & lt; 43 & gt;
=MEM_B_DQ & lt; 44 & gt;
=MEM_B_DQ & lt; 45 & gt;
=MEM_B_DQ & lt; 46 & gt;
=MEM_B_DQ & lt; 47 & gt;
=MEM_B_DQ & lt; 48 & gt;
=MEM_B_DQ & lt; 49 & gt;
=MEM_B_DQ & lt; 50 & gt;
=MEM_B_DQ & lt; 51 & gt;
=MEM_B_DQ & lt; 52 & gt;
=MEM_B_DQ & lt; 53 & gt;
=MEM_B_DQ & lt; 54 & gt;
=MEM_B_DQ & lt; 55 & gt;
=MEM_B_DQ & lt; 56 & gt;
=MEM_B_DQ & lt; 57 & gt;
=MEM_B_DQ & lt; 58 & gt;
=MEM_B_DQ & lt; 59 & gt;
=MEM_B_DQ & lt; 60 & gt;
=MEM_B_DQ & lt; 61 & gt;
=MEM_B_DQ & lt; 62 & gt;
=MEM_B_DQ & lt; 63 & gt;
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8
BI
63
BI
63
BI
A5
A6
A10
63
BI
U3
63
BI
63
VDD1
U4
U5
BI
63
BI
7 63 70
BI
63
BI
63
BI
63
63
D4
BI
63
63
63
63
63
F5
J12
K2
H5
BI
E5
G5
BI
E4
D6
BI
C5
D5
BI
B5
A9
BI
B2
H6
U6
L6
U10
70 62 53 42 23 22 21 20 19 17
PP1V2_S3
M5
A8
OMIT_TABLE
VSS
N5
R4
CRITICAL
T2
T3
DQS0_C
DQS1_C
DQS2_C
DQS3_C
DQS0_T
DQS1_T
DQS2_T
DQS3_T
B1
B13
NU
T13
U1
U2
U12
L11
T5
H2
BI
63
H12
BI
63
J5
BI
63
J6
BI
63
K5
BI
63
K6
BI
63
K12
BI
63
L5
P3
BI
63
P4
M4
BI
63
P5
J4
BI
63
P6
BI
63
U8
BI
63
U9
BI
63
BI
L10
=MEM_B_DQS_N & lt; 4 & gt;
=MEM_B_DQS_N & lt; 5 & gt;
=MEM_B_DQS_N & lt; 6 & gt;
MEM_B_DQS_N & lt; 6 & gt;
G11
P11
D11
63
C3
D3
VDD2
F4
G3
VSSCA
G10
P10
D10
G4
B6
B12
C6
70 62 53 42 23 22 21 20 19 17
PP1V2_S3
F2
BI
63
BI
63
BI
63
BI
D12
E6
7 63 70
BI
63
BI
63
E8
BI
63
E12
BI
7 63 70
G12
H3
F6
VDDCA
F12
L2
M2
G6
G9
70 62 53 42 23 22 21 20 19 17
=MEM_B_DQS_P & lt; 4 & gt;
=MEM_B_DQS_P & lt; 5 & gt;
=MEM_B_DQS_P & lt; 6 & gt;
MEM_B_DQS_P & lt; 6 & gt;
C
T4
G2
A13
N4
R5
A12
T1
(2 OF 2)
A3
A4
63
BI
PP1V8_S3
63
BI
62 57 23 22 21 20
EDFA232A1MA-GD-F
IN
EDFA232A1MA-GD-F
70 63 24
PP1V2_S3
A11
H10
C12
VSSQ
K10
L9
M6
U13
M12
B
H8
N6
NC
NC
NC
H9
C4
P12
K9
H11
NC
R6
J9
R3
T6
J10
VDDQ
T12
K8
K11
70 62 53 42 23 22 21 20 19 17
PP1V2_S3
L12
N8
1
C2600
1
0.1UF
2
70 62 53 42 23 22 21 20 19 17
C2601
1
0.1UF
10%
16V
X5R-CERM
0201
C2602
1UF
2
10%
16V
X5R-CERM
0201
2
1
C2621
1
10%
10V
X5R
402
C2603
1
1UF
2
10%
10V
X5R
402
C2604
1
1UF
2
10%
10V
X5R
402
C2605
1
1UF
2
10%
10V
X5R
402
C2606
N12
10UF
2
R12
20%
25V
X5R-CERM
0603
U11
PP1V2_S3
1
C2620
C2622
1UF
2
70 62 53 42 23 22 21 20 19 17
1
1UF
10%
10V
X5R
402
10%
10V
X5R
402
1
1UF
10%
10V
X5R
402
2
2
C2623
10UF
2
20%
25V
X5R-CERM
0603
PP1V2_S3
1
C2610
1
A
2
PLACEMENT_NOTE:
C2611
1UF
1UF
10%
10V
X5R
402
10%
10V
X5R
402
2
10uF caps are shared between DRAM.
Distribute evenly.
SYNC_MASTER=J41_MLB
SYNC_DATE=02/06/2013
PAGE TITLE
LPDDR3 DRAM Channel B (32-63)
DRAWING NUMBER
62 57 23 22 21 20
PP1V8_S3
Apple Inc.
1
C2630
1
1UF
2
8
7
C2631
1
1UF
10%
10V
X5R
402
2
6
10%
10V
X5R
402
R
C2632
& lt; E4LABEL & gt;
10UF
2
& lt; SCH_NUM & gt;
REVISION
NOTICE OF PROPRIETARY PROPERTY:
20%
25V
X5R-CERM
0603
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
5
4
3
2
BRANCH
& lt; BRANCH & gt;
PAGE
26 OF 121
SHEET
23 OF 76
1
SIZE
D
A
8
7
6
5
4
3
2
1
D
Intel reccomends 55 Ohm for CMD/ADDR, 80 Ohm for CTRL/CKE, 38 Ohm for CLK
D
62 53 24
70 63 20
IN
70 63 20
IN
70 63 20 7
70 63 20
IN
IN
70 63 20
IN
70 20 7
IN
70 20 7
70 20 7
70 20 7
IN
IN
IN
70 63 20
IN
70 63 20
IN
70 63 20
IN
70 63 20
IN
70 63 20
IN
70 63 21
IN
70 63 21
IN
70 63 21 7
IN
70 63 21
IN
70 63 21
70 21 7
70 21 7
IN
IN
IN
70 21 7
IN
70 21 7
IN
70 63 21
C
IN
70 63 21
IN
70 63 21
IN
70 63 21
IN
70 63 21
IN
70 21 20 7
IN
70 21 20 7
IN
70 63 21 20 7
IN
RP2701
RP2701
RP2701
RP2701
R2700
R2701
R2702
R2703
R2704
R2705
R2706
RP2703
RP2703
RP2703
R2725
RP2707
RP2707
RP2707
RP2707
R2707
R2708
R2709
R2720
R2721
RP2704
RP2704
RP2704
RP2704
R2722
R2723
R2724
MEM_A_CAA & lt; 9 & gt;
MEM_A_CAA & lt; 8 & gt;
MEM_A_CAA & lt; 6 & gt;
MEM_A_CAA & lt; 7 & gt;
MEM_A_CAA & lt; 5 & gt;
MEM_A_CLK_P & lt; 0 & gt;
MEM_A_CLK_N & lt; 0 & gt;
MEM_A_CKE & lt; 1 & gt;
MEM_A_CKE & lt; 0 & gt;
MEM_A_CAA & lt; 4 & gt;
MEM_A_CAA & lt; 3 & gt;
MEM_A_CAA & lt; 2 & gt;
MEM_A_CAA & lt; 1 & gt;
MEM_A_CAA & lt; 0 & gt;
MEM_A_CAB & lt; 9 & gt;
MEM_A_CAB & lt; 8 & gt;
MEM_A_CAB & lt; 6 & gt;
MEM_A_CAB & lt; 7 & gt;
MEM_A_CAB & lt; 5 & gt;
MEM_A_CLK_P & lt; 1 & gt;
MEM_A_CLK_N & lt; 1 & gt;
MEM_A_CKE & lt; 2 & gt;
MEM_A_CKE & lt; 3 & gt;
MEM_A_CAB & lt; 4 & gt;
MEM_A_CAB & lt; 2 & gt;
MEM_A_CAB & lt; 3 & gt;
MEM_A_CAB & lt; 1 & gt;
MEM_A_CAB & lt; 0 & gt;
MEM_A_CS_L & lt; 0 & gt;
MEM_A_CS_L & lt; 1 & gt;
MEM_A_ODT & lt; 0 & gt;
56
56
56
56
PP0V6_S0_DDRVTT
4
5
3
6
2
7
62 53 24
1
8
56
39
39
82
82
56
56
56
56
56
56
56
56
56
56
39
39
82
82
56
56
56
56
56
1
2
1
2
1
2
82
82
82
1
2
1
2
1
2
1
2
1
2
1
2
1
2
4
5
3
6
2
7
1
2
4
5
3
6
2
7
1
1
1
8
2
2
1
2
1
2
1
2
4
5
3
6
2
7
1
8
5%
1/32W
4X0201-HF
5%
1/32W
5%
1/32W
4X0201-HF
5%
1/32W
5%
1/20W
201
1/20W
201
MF
70 63 22
IN
70 63 22
IN
20%
4V
CERM-X5R-1
201
70 63 22
70 63 22 7
MF
5%
2
C2700
0.47UF
1
4X0201-HF
4X0201-HF
IN
IN
70 63 22
5%
1/20W
201
MF
5%
1/20W
201
MF
5%
1/20W
201
MF
C2701
1
C2702
0.47UF
2
20%
4V
CERM-X5R-1
201
2
IN
70 22 7
0.47UF
20%
4V
CERM-X5R-1
201
IN
70 22 7
1
70 22 7
70 22 7
IN
IN
IN
201
201
MF
1/32W
IN
MF
1/20W
5%
IN
70 63 22
1/20W
5%
IN
70 63 22
5%
70 63 22
4X0201-HF
5%
1/32W
1/32W
4X0201-HF
2
5%
1/20W
201
MF
C2704
70 63 22
IN
0.47UF
4X0201-HF
5%
1
C2703
0.47UF
20%
4V
CERM-X5R-1
201
20%
4V
CERM-X5R-1
201
70 63 22
IN
1
2
70 63 23
IN
70 63 23
1/32W
1/32W
1/32W
4X0201-HF
5%
1/32W
4X0201-HF
IN
4X0201-HF
5%
IN
4X0201-HF
5%
IN
70 63 23 7
5%
70 63 23
5%
1/20W
201
1/20W
201
MF
2
5%
1/20W
201
1/20W
201
1
C2706
20%
4V
CERM-X5R-1
201
70 63 23
0.47UF
20%
4V
CERM-X5R-1
201
2
70 23 7
70 23 7
IN
IN
IN
70 23 7
IN
MF
5%
C2705
0.47UF
MF
5%
1
MF
70 23 7
5%
1/20W
5%
1/32W
201
4X0201-HF
MF
5%
1/32W
4X0201-HF
5%
1/32W
4X0201-HF
5%
1/32W
IN
70 63 23
IN
70 63 23
IN
4X0201-HF
1
C2707
1
C2708
0.47UF
2
0.47UF
20%
4V
CERM-X5R-1
201
20%
4V
CERM-X5R-1
201
2
70 63 23
IN
70 63 23
IN
70 63 23
IN
70 23 22 7
1/20W
201
1/20W
201
MF
IN
70 63 23 22 7
IN
MF
5%
IN
70 23 22 7
5%
5%
1/20W
201
1
MF
6
2
7
1
8
56
39
39
82
82
56
56
56
56
56
56
56
56
56
56
39
39
82
82
56
56
56
56
56
1
2
1
2
1
2
82
82
82
1
2
1
2
1
2
1
2
1
2
1
2
1
2
4
5
3
6
2
7
1
2
5%
1/32W
4X0201-HF
5%
1/32W
1/32W
4X0201-HF
5%
1/32W
4X0201-HF
5%
1/20W
201
1/20W
201
MF
5%
1/20W
201
MF
5%
1/20W
201
MF
5%
1/20W
201
MF
5%
1/20W
201
MF
5%
1/20W
201
MF
5%
1/32W
4X0201-HF
5%
1/32W
4X0201-HF
5%
1/32W
4X0201-HF
4
5
3
6
2
7
1
8
1
2
1
2
1
2
1
2
1
2
4
5
3
6
2
7
1
8
C2710
MF
5%
1
4X0201-HF
5%
0.47UF
2
1
1
201
5%
1/32W
1/32W
1/32W
4X0201-HF
5%
1/32W
5%
1/20W
201
MF
5%
1/20W
201
MF
5%
1/20W
201
1/20W
201
MF
1/20W
201
MF
5%
1/32W
4X0201-HF
5%
1/32W
4X0201-HF
5%
1/32W
4X0201-HF
5%
1/32W
1/20W
201
1/20W
201
MF
1/20W
201
MF
C2714
0.47UF
2
20%
4V
CERM-X5R-1
201
MF
5%
1
4X0201-HF
5%
20%
4V
CERM-X5R-1
201
20%
4V
CERM-X5R-1
201
MF
5%
0.47UF
2
MF
5%
C2713
C2712
4X0201-HF
5%
1
4X0201-HF
5%
20%
4V
CERM-X5R-1
201
0.47UF
2
1/20W
C2711
0.47UF
2
5%
20%
4V
CERM-X5R-1
201
1
4X0201-HF
C2715
1
0.47UF
2
1
20%
4V
CERM-X5R-1
201
C2717
C2716
0.47UF
2
1
20%
4V
CERM-X5R-1
201
2
1
C
C2718
0.47UF
0.47UF
20%
4V
CERM-X5R-1
201
20%
4V
CERM-X5R-1
201
2
C2719
0.47UF
2
20%
4V
CERM-X5R-1
201
RP2713
56
8
5%
1/32W
4X0201-HF
5
3
Spare
56
1
4
5%
20%
4V
CERM-X5R-1
201
RP2703
NC
56
56
56
56
0.47UF
2
Spare
C2709
RP2712
RP2712
RP2712
RP2712
R2710
R2711
R2712
R2713
R2714
R2715
R2716
RP2713
RP2713
RP2713
R2735
RP2717
RP2717
RP2717
RP2717
R2717
R2718
R2719
R2730
R2731
RP2714
RP2714
RP2714
RP2714
R2732
R2733
R2734
MEM_B_CAA & lt; 9 & gt;
MEM_B_CAA & lt; 8 & gt;
MEM_B_CAA & lt; 7 & gt;
MEM_B_CAA & lt; 6 & gt;
MEM_B_CAA & lt; 5 & gt;
MEM_B_CLK_P & lt; 0 & gt;
MEM_B_CLK_N & lt; 0 & gt;
MEM_B_CKE & lt; 1 & gt;
MEM_B_CKE & lt; 0 & gt;
MEM_B_CAA & lt; 4 & gt;
MEM_B_CAA & lt; 2 & gt;
MEM_B_CAA & lt; 3 & gt;
MEM_B_CAA & lt; 1 & gt;
MEM_B_CAA & lt; 0 & gt;
MEM_B_CAB & lt; 9 & gt;
MEM_B_CAB & lt; 8 & gt;
MEM_B_CAB & lt; 7 & gt;
MEM_B_CAB & lt; 6 & gt;
MEM_B_CAB & lt; 5 & gt;
MEM_B_CLK_N & lt; 1 & gt;
MEM_B_CLK_P & lt; 1 & gt;
MEM_B_CKE & lt; 2 & gt;
MEM_B_CKE & lt; 3 & gt;
MEM_B_CAB & lt; 4 & gt;
MEM_B_CAB & lt; 2 & gt;
MEM_B_CAB & lt; 3 & gt;
MEM_B_CAB & lt; 1 & gt;
MEM_B_CAB & lt; 0 & gt;
MEM_B_CS_L & lt; 0 & gt;
MEM_B_CS_L & lt; 1 & gt;
MEM_B_ODT & lt; 0 & gt;
PP0V6_S0_DDRVTT
CRITICAL
NC
PLACE_NEAR=RP2701.5:4mm
1
NC
C2720
8
5%
1/32W
4X0201-HF
22UF
2
1
20%
6.3V
X5R-CERM-1
603
CRITICAL
NC
PLACE_NEAR=RP2714.8:4mm 1
C2740
22UF
2
20%
6.3V
X5R-CERM-1
603
B
B
A
SYNC_MASTER=J41_MLB
SYNC_DATE=02/06/2013
PAGE TITLE
LPDDR3 DRAM Termination
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
27 OF 121
SHEET
24 OF 76
1
A
8
7
6
5
4
3
2
1
CRITICAL
OMIT_TABLE
C2800
PCIE_TBT_R2D_C_P & lt; 0 & gt;
1
2
69 14
IN
1
2
IN
C2802
PCIE_TBT_R2D_C_P & lt; 1 & gt;
1
10%
IN
1
2
69 14
IN
D
C2804
PCIE_TBT_R2D_C_P & lt; 2 & gt;
1
IN
2
10%
IN
PCIE_TBT_R2D_C_P & lt; 3 & gt;
C2806
IN
PCIE_TBT_R2D_C_N & lt; 3 & gt;
C2807
1
10%
69
0201
69
69
1
2
16V
X5R-CERM
10%
0.1UF
IN
PCH_TBT_PCIE_RESET_L
P5
R2815
TBT_PWR_ON_POC_RST_L
R4
PWR_ON_POC_RSTN
3.3K
5%
1/20W
MF
201
5%
1/20W
MF
201
2
2
10%
6.3V
CERM
402
3.3K
2
5%
1/20W
MF
201
CRITICAL
OMIT_TABLE
NONE
NONE
NONE
0201 2
3.3K
5%
1/20W
MF
201
2
2
DI/IO0
2
DO/IO1
6
(TBT_SPI_MISO)
71
1
CS*
71
4MBIT
CLK
(TBT_SPI_CS_L)
TBTROM_HOLD_L
C
3
7
71
18 16 15
10K
HOLD*
5%
1/20W
MF
201 2
IN
18 16 15
18
IN
OUT
9
4
IN
18
R2829 1
WP*
GND THRM_PAD
1
R2825
67 25
100
5%
1/20W
MF
2 201
67 25
67 25
67 25
67 25
67 25
67 25
67 25
67 25
67 5
IN
DP_TBTSNK0_ML_C_P & lt; 0 & gt;
1
67 5
IN
DP_TBTSNK0_ML_C_N & lt; 0 & gt;
C2821
67 5
IN
DP_TBTSNK0_ML_C_P & lt; 1 & gt;
C2822
67 5
IN
DP_TBTSNK0_ML_C_N & lt; 1 & gt;
C2823
1
C2824
1
IN
DP_TBTSNK0_ML_C_N & lt; 2 & gt;
C2825
1
100K
5%
1/20W
MF
201
25 67
67 25
67 25
2
67 25
25 67
67 25
67 25
25 67
0201
67 25
25 67
0201
67 25
67 25
67 5
IN
DP_TBTSNK0_ML_C_P & lt; 3 & gt;
C2826
1
IN
DP_TBTSNK0_ML_C_N & lt; 3 & gt;
C2827
1
BI
DP_TBTSNK0_AUXCH_C_P
C2828
1
10%
16V
X5R-CERM
0.1UF
67 13
BI
DP_TBTSNK0_AUXCH_C_N
C2829
1
OUT
R2831 1
0201
5%
1/20W
MF
201
2
71 28
OUT
OUT
71 28
IN
71 28
25 67
IN
25 67
0201
IN
DP_TBTSNK1_ML_C_P & lt; 0 & gt;
SNK1 AC Coupling
C2830
1
67 18 5
IN
DP_TBTSNK1_ML_C_N & lt; 0 & gt;
C2831
1
67 18 5
IN
DP_TBTSNK1_ML_C_P & lt; 1 & gt;
IN
DP_TBTSNK1_ML_C_N & lt; 1 & gt;
C2832
1
10%
16V
X5R-CERM
0.1UF
67 18 5
C2833
1
10%
16V
X5R-CERM
0.1UF
A
67 18 5
IN
DP_TBTSNK1_ML_C_P & lt; 2 & gt;
C2834
1
10%
16V
X5R-CERM
0.1UF
67 18 5
IN
DP_TBTSNK1_ML_C_N & lt; 2 & gt;
IN
DP_TBTSNK1_ML_C_P & lt; 3 & gt;
C2835
1
10%
16V
X5R-CERM
0.1UF
67 18 5
C2836
1
67 18 5
IN
DP_TBTSNK1_ML_C_N & lt; 3 & gt;
C2837
1
10%
16V
X5R-CERM
0.1UF
IN
25 67
28
OUT
IN
OUT
71 28
OUT
25 67
BI
DP_TBTSNK1_AUXCH_C_P
C2838
1
BI
DP_TBTSNK1_AUXCH_C_N
C2839
0.1UF
8
1
10%
1
69
C2846
PCIE_TBT_D2R_C_P & lt; 3 & gt;
PCIE_TBT_D2R_C_N & lt; 3 & gt;
1
2
10%
1
2
10%
0.1UF
C2847
2
10%
0.1UF
C2845
2
1
2
10%
X5R-CERM
OUT
16V
X5R-CERM
16V
X5R-CERM
16V
X5R-CERM
16V
X5R-CERM
PCIE_TBT_D2R_N & lt; 2 & gt;
16V
X5R-CERM
0201
PCIE_TBT_D2R_P & lt; 3 & gt;
16V
X5R-CERM
0201
PCIE_TBT_D2R_N & lt; 3 & gt;
16V
X5R-CERM
0201
14 69
OUT
0201
14 69
OUT
PCIE_TBT_D2R_P & lt; 2 & gt;
14 69
OUT
0201
14 69
OUT
0201
PCIE_TBT_D2R_N & lt; 1 & gt;
14 69
OUT
PCIE_TBT_D2R_P & lt; 1 & gt;
14 69
OUT
0201
14 69
OUT
0201
14 69
D
TBT_RSENSE
TBT_RBIAS
1
AD1
L8
R2855
GPIO_16/DEVICE_PCIE_RST_N
GPIO_17
GPIO_18
GPIO_19
1%
1/20W
MF
201
64 62 26 25 18 17
Used for straps in host mode
TP_TBT_PCIE_RESET0_L
TBT_DFT_STRAP_1
TBT_ROM_SECURITY_XOR
TBT_DFT_STRAP_3
W6
AB3
AD3
V1
TBT_CLKREQ_L
PP3V3_TBTLC
NO STUFF
Security strap setting is XORed with
bit in the flash, so the active-level
depends on the code in the flash.
1
10K
If strap != bit then security is enabled?
OUT
2
1
12
1
10%
16V
X5R-CERM
7
W2
AB1
AA6
U6
R6
W8
TDI
TMS
TCK
TDO
TEST_EN
TEST_PWR_GOOD
DP_TBTSNK0_ML_P & lt; 3 & gt;
DP_TBTSNK0_ML_N & lt; 3 & gt;
E14
D13
DPSNK0_3_P
DPSNK0_3_N
DP_TBTSNK0_ML_P & lt; 2 & gt;
DP_TBTSNK0_ML_N & lt; 2 & gt;
E16
D15
DPSNK0_2_P
DPSNK0_2_N
DP_TBTSNK0_ML_P & lt; 1 & gt;
DP_TBTSNK0_ML_N & lt; 1 & gt;
E18
D17
DPSNK0_1_P
DPSNK0_1_N
DP_TBTSNK0_ML_P & lt; 0 & gt;
DP_TBTSNK0_ML_N & lt; 0 & gt;
E20
D19
DPSNK0_0_P
DPSNK0_0_N
DP_TBTSNK0_AUXCH_P
DP_TBTSNK0_AUXCH_N
G4
G2
AB5
2
REFCLK_100_IN_P AB21
REFCLK_100_IN_N AD21
XTAL_25_IN AA24
XTAL_25_OUT AB23
TMU_CLK_OUT AA4
DPSNK0_HPD
E6
D5
DPSNK1_3_P
DPSNK1_3_N
DP_TBTSNK1_ML_P & lt; 2 & gt;
DP_TBTSNK1_ML_N & lt; 2 & gt;
E8
D7
DPSNK1_2_P
DPSNK1_2_N
DP_TBTSNK1_ML_P & lt; 1 & gt;
DP_TBTSNK1_ML_N & lt; 1 & gt;
E10
D9
DPSNK1_1_P
DPSNK1_1_N
DP_TBTSNK1_ML_P & lt; 0 & gt;
DP_TBTSNK1_ML_N & lt; 0 & gt;
E12
D11
DPSNK1_0_P
DPSNK1_0_N
DP_TBTSNK1_AUXCH_P
DP_TBTSNK1_AUXCH_N
H3
H1
DPSNK1_AUX_P
DPSNK1_AUX_N
U4
DPSNK1_HPD
69
IN
12 69
IN
806
1
PA_CIO0_TX_P/DPSRC_0_P
PA_CIO0_TX_N/DPSRC_0_N
TBT_A_D2R_P & lt; 0 & gt;
TBT_A_D2R_N & lt; 0 & gt;
G22
E22
PA_CIO0_RX_P
PA_CIO0_RX_N
TBT_A_R2D_C_P & lt; 1 & gt;
TBT_A_R2D_C_N & lt; 1 & gt;
L24
J24
PA_CIO1_TX_P/DPSRC_2_P
PA_CIO1_TX_N/DPSRC_2_N
TBT_A_D2R_P & lt; 1 & gt;
TBT_A_D2R_N & lt; 1 & gt;
L22
J22
PA_CIO1_RX_P
PA_CIO1_RX_N
N8
J6
TBT_A_LSTX
TBT_A_LSRX
DP_TBTPA_ML_C_P & lt; 1 & gt;
DP_TBTPA_ML_C_N & lt; 1 & gt;
A16
B17
DP_TBTPA_ML_C_P & lt; 3 & gt;
DP_TBTPA_ML_C_N & lt; 3 & gt;
A18
B19
L4
L2
PA_DPSRC_1_P
PA_DPSRC_1_N
PA_DPSRC_3_P
PA_DPSRC_3_N
71 28
BI
71 28
BI
DP_TBTPA_AUXCH_C_P
DP_TBTPA_AUXCH_C_N
IN
DP_TBTPA_HPD
M3
PA_DPSRC_HPD
TBT_A_HV_EN
TBT_A_CIO_SEL
TBT_A_DP_PWRDN
R8
N2
P3
GPIO_0/PA_HV_EN/BYP0
GPIO_10/PA_CIO_SEL/BYP1
GPIO_12/PA_DP_PWRDN/BYP2
28
0201
OUT
28
OUT
28 25
OUT
25 67
0201
25 67
64
DPSRC_0_P A8
DPSRC_0_N B9
TP_DP_TBTSRC_ML_CP & lt; 0 & gt;
TP_DP_TBTSRC_ML_CN & lt; 0 & gt;
DPSRC_AUX_P J4
DPSRC_AUX_N J2
NC_DP_TBTSRC_AUXCH_CP
NC_DP_TBTSRC_AUXCH_CN
6
5%
1/20W
MF
2 201
5
5%
1/20W
MF
201
1
100K
5%
1/20W
MF
201
NC_DP_TBTSRC_ML_CP & lt; 1 & gt;
NC_DP_TBTSRC_ML_CN & lt; 1 & gt;
5%
1/20W
MF
201 2
64
R2880 1
100K
DPSRC_1_P A10
DPSRC_1_N B11
5%
1/20W
MF
201
100K
28 25
PP3V3_TBTLC
2
2
R2832 1
25 18 15
64
64
2
1
100K
R2878
64
DP_TBTSRC_HPD
1
100K
5%
1/20W
MF
201
25
TBT_GPIO2
TBT_PWR_EN
SMC_PME_S4_DARK_L
TBT_CIO_PLUG_EVENT_L
HDMITBTMUX_SEL_TBT
TBT_GPIO7
TBT_EN_CIO_PWR_L
TBT_BATLOW_L
TBTDP_AUXIO_EN
TBT_DDC_XBAR_EN_L
1
IN
OUT
OUT
IN
15
5%
1/20W
MF
201
R2879
100K
2
2
5%
1/20W
MF
201
62 58 39 38 36 33 29 27 26 25
64
R2884 1
5%
1/20W
MF
201
25 26
25 27
28 25
5%
1/20W
MF
201
25
64
IN
64
OUT
64
IN
64
IN
64
2
1
18
OUT
NC_TBT_B_LSTX
TBT_B_LSRX
OUT
64
IN
18
PB_DPSRC_1_P A20
PB_DPSRC_1_N B21
DP_TBTPB_ML_C_P & lt; 1 & gt;
DP_TBTPB_ML_C_N & lt; 1 & gt;
DP_TBTPB_ML_C_P & lt; 3 & gt;
DP_TBTPB_ML_C_N & lt; 3 & gt;
OUT
5%
1/20W
MF
201
10K
5%
1/20W
MF
201
R2887
10K
2
2
5%
1/20W
MF
201
NOTE: The following pins require testpoints:
0 - GPIO_13
8 - GPIO_15
1 - GPIO_1
9 - GPIO_11
2 - GPIO_2
10 - GPIO_14
3 - GPIO_3
11 - GPIO_0
4 - GPIO_5
12 - GPIO_12
5 - PCIE_RST_1_N
13 - GPIO_10
6 - PCIE_RST_2_N
14 - PB_LSTX
7 - PCIE_RST_3_N
15 - PB_LSRX
OUT
PB_DPSRC_3_P A22
PB_DPSRC_3_N B23
R2886
10K
2
18
IN
2
B
NO STUFF
1
10K
64
IN
NC_TBT_B_D2RP & lt; 1 & gt;
NC_TBT_B_D2RN & lt; 1 & gt;
28 27 25
64
IN
NC_TBT_B_R2D_CP & lt; 1 & gt;
NC_TBT_B_R2D_CN & lt; 1 & gt;
64
OUT
5%
1/20W
MF
201
TBT_BATLOW_L
TBT_A_DP_PWRDN
TBT_B_DP_PWRDN
TBT_A_HV_EN
TBT_B_HV_EN
27 25
25
OUT
TBT_B_CONFIG1_BUF
TBT_B_CONFIG2_RC
2
R2888 1
25 28
OUT
NC_TBT_B_D2RP & lt; 0 & gt;
NC_TBT_B_D2RN & lt; 0 & gt;
2
R2885 1
100K
OUT
NC_TBT_B_R2D_CP & lt; 0 & gt;
NC_TBT_B_R2D_CN & lt; 0 & gt;
100K
NO STUFF
15 18
15 18 25
IN
R2883
PP3V3_S4
33 37 38
OUT
5%
1/20W
MF
201
17 18 25 26 62 64
64
64
R2882
TBT_EN_CIO_PWR_L
TBT_DDC_XBAR_EN_L
HDMITBTMUX_SEL_TBT
TBTDP_AUXIO_EN
DP_TBTSRC_HPD
25
PB_AUX_P K3
PB_AUX_N K1
PA_AUX_P
PA_AUX_N
For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k).
0201
2
17 69
R2881 1
25
PB_LSTX/CIO_3_LSEO M5
PB_LSRX/CIO_3_LSOE P7
PA_LSTX/CIO_1_LSEO
PA_LSRX/CIO_1_LSOE
IN
1K
26 25
PB_CIO3_RX_P W22
PB_CIO3_RX_N U22
10K
PP3V3_TBTLC
PP3V3_S4
R2896
64
PB_CIO3_TX_P/DPSRC_2_P W24
PB_CIO3_TX_N/DPSRC_2_N U24
OUT
25 67
25 67
1
10K
64
PB_CONFIG1/CIO_2_LSEO D3
PB_CONFIG2/CIO_2_LSOE M1
PA_CONFIG1/CIO_0_LSEO
PA_CONFIG2/CIO_0_LSOE
2
R2863
64 62
TP_DP_TBTSRC_ML_CP & lt; 2 & gt;
TP_DP_TBTSRC_ML_CN & lt; 2 & gt;
PB_CIO2_RX_P R22
PB_CIO2_RX_N N22
5%
1/20W
MF
201
C
1%
1/20W
64 62 26 25 18 17
MF
201 39 38 36 33 29 27 26 25
58
TBT_TMU_CLK_OUT
DPSRC_2_P A12
DPSRC_2_N B13
PB_CIO2_TX_P/DPSRC_0_P R24
PB_CIO2_TX_N/DPSRC_0_N N24
10K
SYSCLK_CLK25M_TBT
2
64
U2
L6
H5
Y7
Y1
T7
V7
M7
T1
T3
1
R2862
R2895
SYSCLK_CLK25M_TBT_R
TP_TBT_XTAL25OUT
TP_DP_TBTSRC_ML_CP & lt; 3 & gt;
TP_DP_TBTSRC_ML_CN & lt; 3 & gt;
GPIO_2/TMU_CLK_IN/AC_PRESENT
GPIO_3/FORCE_PWR
GPIO_4/WAKE_OD_N
GPIO_5/CIO_PLUG_EVENT_N/HV_OK_OD
GPIO_6_OD/CIO_SDA_OD
GPIO_7_OD/CIO_SCL_OD
GPIO_8/EN_CIO_PWR_N_OD
GPIO_9/SX_CTRL_OD*
GPIO_14
GPIO_15
G24
E24
P1
K5
1
5%
1/20W
MF
201
Divides 3.3V to 1.8V
DPSRC_3_P A14
DPSRC_3_N B15
DPSRC_HPD_OD AC2
TBT_A_R2D_C_P & lt; 0 & gt;
TBT_A_R2D_C_N & lt; 0 & gt;
TBT_A_CONFIG1_BUF
TBT_A_CONFIG2_RC
R2861
5%
1/20W
MF
201
12 69
R2899 1
DPSNK0_AUX_P
DPSNK0_AUX_N
DP_TBTSNK1_ML_P & lt; 3 & gt;
DP_TBTSNK1_ML_N & lt; 3 & gt;
PCIE_CLK100M_TBT_P
PCIE_CLK100M_TBT_N
NO STUFF
71 28
25 67
0201
DP_TBTSNK1_AUXCH_N
2
XDP_JTAG_ISP_TDI
JTAG_TBT_TMS
XDP_JTAG_ISP_TCK
JTAG_TBT_TDO
TBT_TEST_EN
TBT_TEST_PWR_GOOD
R2867
10K
OUT
0201
DP_TBTSNK1_AUXCH_P
2
10%
16V
X5R-CERM
0.1UF
67 18 13
69
PCIE_CLKREQ_OD_N V3
71 28
28 27 25
67 18 13
C2844
PCIE_TBT_D2R_C_P & lt; 2 & gt;
PCIE_TBT_D2R_C_N & lt; 2 & gt;
25 67
0201
DP_TBTSNK1_ML_N & lt; 3 & gt;
2
IN
71 28
DP_TBTSNK1_ML_P & lt; 3 & gt;
2
10%
16V
X5R-CERM
0.1UF
71 28
25 67
0201
DP_TBTSNK1_ML_N & lt; 2 & gt;
2
OUT
28
DP_TBTSNK1_ML_P & lt; 2 & gt;
2
OUT
71 28
0201
DP_TBTSNK1_ML_N & lt; 1 & gt;
2
71 28
0201
DP_TBTSNK1_ML_P & lt; 1 & gt;
2
IN
25 67
0201
DP_TBTSNK1_ML_N & lt; 0 & gt;
2
10%
16V
X5R-CERM
0.1UF
IN
71 28
DP_TBTSNK1_ML_P & lt; 0 & gt;
2
10%
16V
X5R-CERM
0.1UF
28
28
67 18 5
69
2
10%
16V
PCIE_TBT_D2R_N & lt; 0 & gt;
25
71 28
100K
DP_TBTSNK0_AUXCH_N
2
10%
16V
X5R-CERM
0.1UF
18 13
25 67
0201
DP_TBTSNK0_AUXCH_P
2
25 67
0201
DP_TBTSNK0_ML_N & lt; 3 & gt;
2
10%
16V
X5R-CERM
0.1UF
67 13
DP_TBTSNK0_ML_P & lt; 3 & gt;
2
10%
16V
X5R-CERM
0.1UF
67 5
EE_DI
EE_DO
EE_CS_N
EE_CLK
DP_TBTSNK1_HPD
67 25
67 25
DP_TBTSNK0_ML_N & lt; 2 & gt;
2
10%
16V
X5R-CERM
0.1UF
25 67
R2830 1
0201
DP_TBTSNK0_ML_P & lt; 2 & gt;
2
10%
16V
X5R-CERM
0.1UF
67 5
TBT_SPI_MOSI
TBT_SPI_MISO
TBT_SPI_CS_L
TBT_SPI_CLK
DP_TBTSNK0_HPD
OUT
0201
DP_TBTSNK0_ML_N & lt; 1 & gt;
2
10%
16V
X5R-CERM
13
25 67
0201
DP_TBTSNK0_ML_P & lt; 1 & gt;
2
10%
16V
X5R-CERM
1
0.1UF
DP_TBTSNK0_ML_C_P & lt; 2 & gt;
THERMDA
AA2
Y3
T5
U8
0201
DP_TBTSNK0_ML_N & lt; 0 & gt;
2
10%
16V
X5R-CERM
1
0.1UF
IN
DP_TBTSNK0_ML_P & lt; 0 & gt;
2
10%
16V
X5R-CERM
0.1UF
67 5
67 25
SNK0 AC Coupling
C2820
0.1UF
B
69
MONOBSP
MONOBSN
AB7
1
PCIE_TBT_D2R_P & lt; 0 & gt;
W25X40CLXIG
USON
TBTROM_WP_L
W18
W16
Use AA8 GND ball for THERM_DN
U2890
(TBT_SPI_CLK)
C2843
2
10%
0.1UF
2
TP_TBT_THERM_DP
71
5
RSVD_GND
DEBUG: For monitoring clock
VCC
(TBT_SPI_MOSI)
C2842
PCIE_TBT_D2R_C_P & lt; 1 & gt;
PCIE_TBT_D2R_C_N & lt; 1 & gt;
DEBUG: For monitoring current/voltage
TBT_MONOBSP
TBT_MONOBSN
1
1K
AD23 MONDC0
AC24 MONDC1
TP_TBT_MONDC0
TP_TBT_MONDC1
NOSTUFF
R2893
69
RBIAS W20
PORT
3.3K
1UF
1
69
RSENSE U20
DISPLAY
R2891
1
C2841
2
10%
0.1UF
PETP_3 AD17
PETN_3 AD19
PORTS
1
R2892
8
R2890 1
1
PETP_2 AD13
PETN_2 AD15
PERST_OD_N
IN
1
0.1UF
0.1UF
OMIT
C2890
C2840
PCIE_TBT_D2R_C_P & lt; 0 & gt;
PCIE_TBT_D2R_C_N & lt; 0 & gt;
0201
PP3V3_TBTLC
1
69
0.1UF
AA18 PERP_3
AB19 PERN_3
PCIE_TBT_R2D_P & lt; 3 & gt;
PCIE_TBT_R2D_N & lt; 3 & gt;
26
BYPASS=U2890::2mm
69
0.1UF
PETP_1 AD9
PETN_1 AD11
AB15 PERP_2
AA16 PERN_2
PCIE_TBT_R2D_P & lt; 2 & gt;
PCIE_TBT_R2D_N & lt; 2 & gt;
18 15
64 62 26 25 18 17
PETP_0 AD5
PETN_0 AD7
AA12 PERP_1
AB13 PERN_1
PCIE_TBT_R2D_P & lt; 1 & gt;
PCIE_TBT_R2D_N & lt; 1 & gt;
0201
16V
X5R-CERM
2
0.1UF
69 14
16V
X5R-CERM
10%
0.1UF
69 14
0201
69
C2805
PCIE_TBT_R2D_C_N & lt; 2 & gt;
69
0201
16V
X5R-CERM
2
1
0.1UF
69 14
16V
X5R-CERM
10%
0.1UF
U2800
FALCON-RIDGE-FR2C
FCBGA
SYM 1 OF 2
69
C2803
PCIE_TBT_R2D_C_N & lt; 1 & gt;
0201
AB9 PERP_0
AA10 PERN_0
PCIE_TBT_R2D_P & lt; 0 & gt;
PCIE_TBT_R2D_N & lt; 0 & gt;
0201
16V
X5R-CERM
2
0.1UF
69 14
16V
X5R-CERM
10%
0.1UF
69 14
69
0201
69
C2801
PCIE_TBT_R2D_C_N & lt; 0 & gt;
16V
X5R-CERM
10%
0.1UF
PCIE GEN2
IN
MISC
69 14
PB_DPSRC_HPD N6
GPIO_1/PB_HV_EN/BYP0 F1
GPIO_11/PB_CIO_SEL/BYP1 R2
GPIO_13/PB_DP_PWRDN/BYP2 F3
OUT
SYNC_MASTER=T29_RR
Thunderbolt Host (1 of 2)
DRAWING NUMBER
NC_DP_TBTPB_AUXCH_CP
NC_DP_TBTPB_AUXCH_CN
BI
64 71
BI
64 71
Apple Inc.
& lt; SCH_NUM & gt;
REVISION
R
DP_TBTPB_HPD
IN
25
OUT
18
OUT
25
NOTICE OF PROPRIETARY PROPERTY:
3
& lt; E4LABEL & gt;
18
OUT
TBT_B_HV_EN
TBT_B_CIO_SEL
TBT_B_DP_PWRDN
All other port signals can be NC.
4
SYNC_DATE=01/19/2013
PAGE TITLE
OUT
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
BRANCH
& lt; BRANCH & gt;
PAGE
28 OF 121
SHEET
25 OF 76
1
SIZE
D
A
8
7
6
5
4
3
2
1
U2940
Part
TPS22920
Type
Load Switch
R(on)
8 mOhm Typ
@ 1.05V
11.5 mOhm Max
1.05V TBT " CIO " Switch
Internal switch not functional on RR.
CRITICAL
OMIT_TABLE
C2904
1
C2905
1
C2906
64 26
1.0UF
1.0UF
20%
6.3V
20%
6.3V
X5R
0201-1
20%
6.3V
X5R
0201-1
1
700 mA EDP
1.0UF
20%
6.3V
X5R
0201-1
2
2
2
2
X5R
2
0201-1
2
2
FALCON-RIDGE-FR2C
FCBGA
SYM 2 OF 2
VCC1P0_CIO
VCC1P0_RDV_DECAP
VCC3P3
PP1V05_TBT
MIN_LINE_WIDTH=0.50 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=1.05V
C2910
1
1.0UF
C
20%
6.3V
X5R
0201-1
C2911
J8
K9
L14
M15
M17
P17
V19
1
1.0UF
2
20%
6.3V
X5R
0201-1
2
A4
A6
B3
0.68UH-20%-4.2A-0.032OHM
1
2
P1V05TBT_SW
MIN_LINE_WIDTH=0.50 MM
MIN_NECK_WIDTH=0.20 MM
DIDT=TRUE
SWITCH_NODE=TRUE
PIMB041B-SM
C2923
1
10UF
20%
6.3V
CERM-X5R
0402-1
C2922
1
C2921
10UF
2
20%
6.3V
CERM-X5R
0402-1
1
10UF
20%
6.3V
CERM-X5R
0402-1
2
C2920
1
10UF
2
20%
6.3V
CERM-X5R
0402-1
CRITICAL
2
NC
C2931
1
20%
6.3V
X5R
0201-1
2
2
NSR1020MW2T1G
A
B
A
VOUT
VIN
5%
1/20W
C1
C2
MF
1200 mA EDP
201
2
CRITICAL
ON
2
D2
TBT_EN_CIO_PWR
GND
1
C2940
Q2945
DMN5L06VK-7
D
6
1.0UF
2
SOT563
20%
6.3V
X5R
0201-1
VER 3
S
1
74 65 64 62 61
36 30 26 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
G 2
PP3V3_S0
5
G
VER 5
S
D3
SVR input to RR - 1100 mA EDP
13
POC input to RR -
OUT
TBT_PWR_REQ_L
TBT_EN_CIO_PWR_L
4
IN
25
150 mA EDP
DMN5L06VK-7
Pull-up (S0) on PCH page
SOT563
Isolated to reduce noise from SVR
Q2945
PP3V3_S4
17 18 25 26 62 64
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
25 26 27 29 33 36 38 39 58 62
64
3.1 W (Dual-Port)
C
2.4 W (Single-Port)
SVR_VCC1P0
VCC3P3_RDV_DECAP
SVR_IND
H13
H15
H17
H7
L18
N18
R18
W10
C2970
1
100 mA EDP
C2950
VSS
VSS
G20
G6
G8
H21
H23
J14
J16
J20
K13
K21
K23
L12
L20
M13
M21
M23
M9
N12
N16
N20
P13
P21
P23
P9
R12
R16
R20
T13
T17
T21
T23
T9
U12
U16
V13
V21
V23
V9
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y9
1
C2951
1
C2952
1
C2953
1.0UF
10UF
10UF
10UF
20%
6.3V
X5R
0201-1
20%
6.3V
CERM-X5R
0402-1
20%
6.3V
CERM-X5R
0402-1
20%
6.3V
CERM-X5R
0402-1
20%
6.3V
CERM-X5R
0402-1
1
EDP: 1.25 A
10UF
2
2
2
2
PLACE_NEAR=C2953.1:1mm
2
2
XW2960
SM
1
PP3V3_TBTRDV
PP3V3_S4_TBT_F
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
B5 SVR_AMON
A2
A24
AA14
AA20
AA22
AA8
AB11
AB17
AC10
AC12
AC14
AC16
AC18
AC20
AC22
AC4
AC6
AC8
B1
B7
C10
C12
C14
C16
C18
C2
C20
C22
C24
C4
C6
C8
D21
D23
E4
F11
F13
F15
F17
F19
F21
F23
F5
F7
F9
SOD-323
1
1.0UF
20%
6.3V
X5R
0201-1
1
K
D2920
C2932
1.0UF
20%
6.3V
X5R
0201-1
PP3V3_TBTLC
GND
1900 mA EDP
1
1.0UF
VCC3P3_LC Y5
CRITICAL
L2920
D1
E2
H11
N4
V5
W4
C2930
100K
25 mA EDP
C2980
1
C2981
1.0UF
2
20%
6.3V
X5R
0201-1
C2960
1.0UF
2
20%
6.3V
X5R
0201-1
C2961
1.0UF
20%
6.3V
X5R
0201-1
1
1
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
1.0UF
20%
6.3V
X5R
0201-1
2
2
B
62 58 39 38 36 33 29 27 26 25
64
38 37 27 17
74 65 64 62 61
36 30 26 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
IN
PP3V3_S4
TBT " POC " Power-up Reset
SMC_DELAYED_PWRGD
PP3V3_S0
R2995
Q2995
1
1
DMN32D2LFB4
100K
R2990
100K
DFN1006H4-3
R2992
1
CRITICAL
1
6
1
1.0UF
D
R2945
B2
5%
5%
1/20W
MF
201
1/20W
SYM_VER_3
2
MF
2
201
5%
TPS3895ADRY
MF
IN
TBT_POC_RESET_L
201
USON
2
TBTPOCRST_MR_L
1
ENABLE
TBTPOCRST_SENSE
15
2
U2990
1/20W
3
SENSE
C2990
0.1UF
VCC
100K
10%
25V
X5R
402
Push-pull output
SENSE_OUT
4
TBT_PWR_ON_POC_RST_L
CT
5
TBTPOCRST_CT
OUT
1
10%
16V
X7R
0201
R2991
C2991
24.9K
330PF
10%
50V
1/20W
2
MF
2
X7R-CERM
201
Vth = 2.508V nominal
Delay = 4.04ms nominal
SYNC_MASTER=T29_RR
SYNC_DATE=12/17/2012
PAGE TITLE
Thunderbolt Host (2 of 2)
DRAWING NUMBER
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
EDP current / power consumption figures copied from R68 schematic (Rev 2, dated October 28, 2012, not available on IBL).
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
R
6
2
0402
NOTICE OF PROPRIETARY PROPERTY:
7
1
0.001UF
1%
Apple Inc.
8
25
GND
1
C2995
2
C2903
20%
6.3V
X5R
0201-1
A2
B1
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
D1
1
1.0UF
CSP
A1
64 62 PP1V05_TBTCIO
D
C2902
20%
6.3V
X5R
0201-1
17 18 25 26 62 64
3
1
1.0UF
1
1
C2901
20%
6.3V
X5R
0201-1
J10
J12
K11
L10
M11
N10
N14
P11
P15
R10
R14
T11
T15
U10
U14
V11
G
1
1.0UF
U2800
2
C2900
PP3V3_TBTLC
S
G10
G12
G14
G16
G18
H19
H9
J18
K15
K17
K19
K7
L16
M19
P19
T19
U18
V15
V17
W12
W14
PP1V05_TBTRDV
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=1.05V
26 64
TPS22920
VCC
D
PP1V05_TBT
U2940
Max Current = 4A (85C)
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
29 OF 121
SHEET
26 OF 76
1
A
6
5
Power aliases required by this page:
Q3080
SI8409DB
BGA
PPVIN_S4SW_TBTBST_FET
1
C3090
2
1%
1/20W
MF
201
VIN
25
TBTBST_EN_UVLO
150K
28
TBTBST_INTVCC
SNS1
6
SNS2
3
R3090
INTVCC
30
TBTBST_VC
C3081
DFN1006H4-3
2.2UF
20%
10V
X5R-CERM
402
20%
10V
X5R-CERM
402
C3087
47PF
2
2
33
TBTBST_RT
1%
1/16W
MF-LF
402
1%
1/20W
MF
201
10
NC
1
2
32
SS
34
TBTBST_SS
SYNC
C3088
22PF
36
2
5%
50V
CER-C0G
0402
TBTBST_VC_RC
20%
10V
X5R-CERM
402
10%
10V
X7R-CERM
0201
2
C3094
1
41.2K
1%
1/20W
MF
201
2
& lt; R2 & gt;
2
1
GND
C3089
100PF
2
GND_TBTBST_SGND
D
20%
25V
X5R-CERM
0603
1%
1/16W
MF-LF
402
20%
25V
X5R-CERM
0603
C3098
1
1
10UF
20%
25V
X5R-CERM
0603
2
2
2
5%
50V
CERM
402
R3096 1
1
1%
1/16W
MF-LF
402
C3084
1
10UF
15.8K
2
C309A
1
10UF
20%
25V
X5R-CERM
0603
2
C3099
0.001UF
20%
25V
X5R-CERM
0603
2
10%
50V
X7R-CERM
0402
2
& lt; Rb & gt;
C3085
C309B
1
10UF
20%
25V
X5R-CERM
0603
1
10UF
20%
25V
X5R-CERM
0603
2
2
C
Q3088
DMN5L06VK-7
1
SOT563
VER 3
1
2
10UF
133K
Vout = 1.6V * (1 + Ra / Rb)
6
C3097
10UF
20%
25V
X5R-CERM
0603
C3096
R3095 1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V
UVLO(falling) = 1.22 * (R1 + R2) / R2
UVLO(rising) = UVLO(falling) + (2uA * R1)
UVLO = 4.55V (falling), 4.95 (rising)
C
SGND
10%
6.3V
CERM-X5R
402
2
NO STUFF
no XW necessary.
0.33UF
1
10UF
TBTBST_FBX
31
GND inside package,
R3094 1
17
2
3300PF
16
C3093
C3095
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
15
1
2.2UF
14
2
1%
1/20W
MF
201
C3082
13
1
73.2K
12
R3092
FBX
SGND shorted to
37
1
PLACE_NEAR=C3095.1:2 mm
& lt; Ra & gt;
2
TBT_A_HV_EN
1
1
TBTBST_VSNS_RC
35
RT
10K
5%
25V
C0G
0201
1
2
NC
R3093 1
4
S
2
1
24
G
1
23
1
IN
C3092
1
2.2UF
SYM_VER_2
28 25
VC
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
3
2
2
49.9K
QFN
1
D
TBTBST_VSNS
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
TBTBST_PWREN_L
Q3005
SM
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
LT3957
2
D
XW3095
TBTBST_SNS2
SW
CRITICAL
EN/UVLO
Freq = 300KHz
5%
1/20W
MF
0201
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
U3090
DMN32D2LFB4
2
2
& lt; R1 & gt;
R3081 1
28 62 64
Max Current = 1.0A
0
1
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
2
DFLS230L
R3089
TBTBST_SNS1
200K
PP15V_TBT
K
Vout = 15.1V
R3091 1
TBTBST_PWREN_DIV_L
5%
1/20W
MF
201
20%
25V
X5R-CERM
0603
1
10UF
20%
25V
X5R-CERM
0603
A
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE
DIDT=TRUE
38
10%
25V
X5R
402
C3091
1
10UF
0.1UF
2
2
D3095
POWERDI-123
TBTBST_BOOST
2
PIMB062D-SM
1
5%
1/20W
MF
201
C3080
CRITICAL
L3095
G
1
470K
D
CRITICAL
Voltage not specified here,
add property on another page.
R3080 1
1
6.8UH-4.0A
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
(NONE)
2
TBT 15V Boost Regulator
9
BOM options provided by this page:
3
8-13V Input
Changes required
for 2S.
(NONE)
-30V
+/-12V
-1.4V
46mOhm @ 4.5V Vgs
3.7A @ 70C
21
PPBUS_G3H
D
62 56 50 49 42 41
64
2
Signal aliases required by this page:
3
8
(15V Boost Output)
S
- =PP15V_TBT_REG
CRITICAL
(8-13V Boost Input)
4
- =PPVIN_SW_TBTBST
4
SI8409DB:
Vds(max):
Vgs(max):
Vgs(th):
Rds(on):
Id(max):
20
7
27
8
Page Notes
S
G
2
R3088
330K
Max Vgs: 10V
2
5%
1/20W
MF
201
TBTBST_SHDN_DIV
1
R3087
3
D
330K
2
Q3088
DMN5L06VK-7
SOT563
5%
1/20W
MF
201
VER 3
4
S
G 5
SMC_DELAYED_PWRGD
B
IN
17 26 37 38
B
BATLOW# Isolation
PP3V3_S4
25 26 29 33 36 38 39 58 62 64
1
Q3000
DFN1006H4-3
SYM_VER_3
G
DMN32D2LFB4
S
TBT_BATLOW_L
2
PM_BATLOW_L
3
IN
D
Pull-up on RR page
37 13
TBT_BATLOW_L
OUT
25 27
25 27
MAKE_BASE=TRUE
A
SYNC_MASTER=WILL_J43
SYNC_DATE=12/17/2012
PAGE TITLE
TBT Power Support
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
30 OF 121
SHEET
27 OF 76
1
A
8
7
6
5
4
3
2
1
3.3V/HV Power MUX
V3P3 must be S4 to support
wake from Thunderbolt devices.
62 28
PP3V3_S4_TBTAPWR
PP3V3_S5
Min
Max
1100mA
1030mA
1200mA
IHVS0
890mA
830mA
930mA (assumes 15V, 12W minimum)
IHVS3
890mA
830mA
930mA (assumes 3S, 9-12.6V, 7.5-11.7W)
CRITICAL
1
C3280
100UF
D
20%
6.3V
X5R-CERM-1
603
1
1
22UF
20%
6.3V
POLY-TANT
CASE-B2-SM
2
C3281
0.1UF
2
2
V3P3OUT
12
OUT
6
15.75V Max
C3215
1
4.7UF
10%
25V
X5R-CERM
0603
0.1UF
2
2
14
C3285
10%
16V
X5R-CERM
0201
CD3211A1RGP
QFN
16
ENHVU
5
1
1
C3286
0.1UF
U3210
10%
25V
X5R
402
1
2
71 25
OUT
OUT
TBT_A_D2R_P & lt; 1 & gt;
C3276
71 25
BI
1
BI
10%
16V
X5R-CERM
0201
2
18 13
IN
S4_PWR_EN
8
TBTAPWRSW_ISET_V3P3
27 25
IN
TBT_A_HV_EN
11
HV_EN
ISET_S0
10
TBTAPWRSW_ISET_S0
59 57
IN
PM_SLP_S3_BUF_L
17
S0
ISET_S3
9
TBTAPWRSW_ISET_S3
ISET_V3P3
EN
1
71 DP_TBTPA_AUXCH_P
18 13
59 58 18
8
71 DP_TBTPA_AUXCH_N
10%
16V
X5R-CERM
0201
0.1UF
7
TBTB+
TB_ENA
AUXIO_EN
DP_PD
201
2
1
C3231
71 TBT_A_D2R_C_N & lt; 1 & gt;
71 TBT_A_D2R_C_P & lt; 1 & gt;
1
0.1UF
DP_TBTPA_AUXCH_C_P
201
2
20%
4V
CERM-X5R-1
DP_TBTPA_AUXCH_C_N
4
FAULTZ
HVQFN24-COMBO
C3230
71 25
2
BI
DP_TBTSNK0_DDC_DATA
4
IN
DP_TBTSNK0_DDC_CLK
5
OUT
TBT_A_CONFIG1_BUF
AUXAUX+
AUXIO(IPD) AUXIO+
(IPU)
R3210
12V: See
21
3
15
13
2
1
TBTHV:P15V
THRM
PAD
1%
1/20W
MF
201
1
1
R3211
22.6K
IN
DP_TBTPA_ML_C_N & lt; 1 & gt;
2
2
1%
1/20W
MF
201
2
1
0.22UF
6.3V
0201
1%
1/20W
MF
201
20%
X5R
C
IN
TBT_A_LSTX
14
OUT
TBT_A_LSRX
13
OUT
DP_TBTPA_HPD
12
6.3V
0201
25
1%
1/20W
MF
201
& lt; RV3P3 & gt;
LSTX
LSRX
TBTDP_AUXIO_EN
IN
25
IN
25
6
TBT_A_DP_PWRDN
23
TBT_A_D2R1_AUXDDC_N
28 71
22
TBT_A_D2R1_AUXDDC_P
28 71
CA_DET
18
TBT_A_CONFIG1_RC
28
DPMLO+
DPMLO-
19
DP_A_LSX_ML_P & lt; 1 & gt;
28 71
20
DP_A_LSX_ML_N & lt; 1 & gt;
28 71
TBT: LSX_A_R2P/P2R (P/N)
(IPD)
HPDOUT
HPD
17
TBT_A_HPD
28
GND THMPAD
TBTHV:P15V
1
24
(IPU)
Single-fault protection
R3214
9
1
10
DP+
DP-
2
TBTAPWRSW_ISET_S0_R
22.6K
IN
25
2
20%
X5R
0.22UF
C3233
R3212
36.5K
TBTAPWRSW_ISET_S3_R
R3213
CA_DETOUT
11
25
IN
71 25
TBTHV:P15V
1
22.6K
below
TBTHV:P15V
16
25
GND
1
TBT_A_CIO_SEL
TBT: RX_1
71 DP_TBTPA_ML_N & lt; 1 & gt;
C3232
DP_TBTPA_ML_C_P & lt; 1 & gt;
15
DDC_DAT
DDC_CLK
71 DP_TBTPA_ML_P & lt; 1 & gt;
25
71 25
D
U3220
CBTL05024
2
20%
4V
CERM-X5R-1
0.47UF
0.47UF
10%
25V
X5R
402
2
1
TBT_A_D2R_N & lt; 1 & gt;
0.1UF
20%
6.3V
CERM-X5R
0402
2
CRITICAL
(Both C’s)
C3277
71 25
C3211
10UF
SIGNAL_MODEL=TBT_MUX
VDD
2
GND_VOID=TRUE
PP3V3RHV_S4_TBTAPWR
CRITICAL
C3210
28 62
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V
VHV
7
1
10%
16V
X5R-CERM
0201
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
18
V3P3
20
PP15V_TBT
1
0.1UF
PP3V3_S4_TBTAPWR
19
64 62 27
C3220
10%
16V
X5R-CERM
0201
25
C3287
3
Nominal
IV3P3
21
34 29 18 17 16 15 13 11 8
74 64 62 60 59 58 57 42
requires two R’s per HV
22.6K
2
& lt; RHVS3 & gt;
2
ISET_Sx with CD3210.
1%
1/20W
MF
201
Single R on ISET_V3P3 OK.
& lt; RHVS0 & gt;
ILIM = 40000 / RISET
C
For 12V systems:
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
118S0145
2
RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF
R3210,R3213
TBTHV:P12V
118S0145
2
RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF
R3211,R3214
TBTHV:P12V
CRITICAL
Nominal
IHVS0/S3
Min
1120mA
1090mA
Thunderbolt Connector A
L3200
Max
FERR-120-OHM-3A
1170mA (12W minimum)
1
2
C3200
PP3V3RHV_S4_TBTAPWR_F
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V
0603
1
TBTACONN_1_C
10%
50V
X7R-CERM
0402
12
TBTACONN_20_RC
2
1
1
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18V
2
C3201
(Both C’s)
C3274
OUT
71 25
OUT
TBT_A_D2R_N & lt; 0 & gt;
1
TBT_A_D2R_P & lt; 0 & gt;
1
201
1
2
NO_XNET_CONNECTION=TRUE
C3278
71 25
IN
DP_TBTPA_ML_C_N & lt; 3 & gt;
1
DP_TBTPA_ML_C_P & lt; 3 & gt;
71 DP_TBTPA_ML_P & lt; 3 & gt;
6.3V
0201
71 DP_TBTPA_ML_N & lt; 3 & gt;
C3279
1
2
20%
X5R
0.22UF
6.3V
0201
TBT: Unused
R3279
1
1
470K
5%
1/20W
MF
201
R3278
470K
2
2
2
2
4
6
13
10
12
14
16
18
20
HOT_PLUG_DETECT
GND
CONFIG1
ML_LANE0P
CONFIG2
ML_LANE0N
GND
GND
ML_LANE3P
ML_LANE1P
ML_LANE3N
ML_LANE1N
GND
GND
AUX_CHP
ML_LANE2P
AUX_CHN
ML_LANE2N
DP_PWR
RETURN
GND_VOID=TRUE
GND_VOID=TRUE
C3206
(0-18.9V)
1
3
5
7
9
11
8
15
17
19
1
1
10%
25V
X5R-CERM
0201
2
2
2
28
27
26
25
24
23
22
21
1
1
6.3V
0201
2
20%
X5R
TBT_A_D2R1_AUXDDC_N
GND_VOID=TRUE
1
TBT_A_HPD
2
TBT_A_CONFIG1_RC
1
GND_VOID=TRUE
1
R3272
2
R3252
1M
5%
1/20W
MF
201
A
R3251
1M
2
2
5%
1/20W
MF
201
C3294
1
1
330PF
10%
16V
X7R
0201
C3295
2
10%
16V
X7R
0201
2
5%
1/20W
MF
201
down HPD input with
10%
16V
X5R-CERM
0201
greater than or equal
470k R’s for ESD protection
to 100K (DPv1.1a).
on AC-coupled signals.
R3241
100K
330PF
2
R3273
470K
5%
1/20W
MF
201
DP Source must pull
C3202
0.01UF
TBT_A_CONFIG2_RC
1
6.3V
0201
TBT: TX_1
TBT_A_D2R1_AUXDDC_P
470K
1
25 71
2
20%
X5R
0.22UF
TBT: RX_1
1
25 71
IN
(Both C’s)
0.22UF
28
IN
B
GND_VOID=TRUE
SHIELD PINS
71 TBT_A_R2D_N & lt; 1 & gt;
OUT
TBT_A_R2D_C_P & lt; 1 & gt;
5%
1/20W
MF
201
TBT: LSX_R2P/P2R (P/N)
C3273
25
28 71
R3271
470K
5%
1/20W
MF
201
71 TBT_A_R2D_P & lt; 1 & gt;
28
28 71
6.3V
0201
GND_VOID=TRUE
1
R3270
470K
0.01UF
C3272
71 28
25 71
2
20%
X5R
TBTACONN_7_C
5%
1/20W
MF
201
71 28
25 71
TBT_A_R2D_C_N & lt; 1 & gt;
6.3V
0201
IN
DP_A_LSX_ML_N & lt; 1 & gt;
1
IN
DP_A_LSX_ML_P & lt; 1 & gt;
C3271
TBT_A_R2D_C_P & lt; 0 & gt;
TBT_A_R2D_C_N & lt; 0 & gt;
20%
X5R
0.22UF
0.22UF
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18.9V
CRITICAL
NO_XNET_CONNECTION=TRUE
1
TBT Dir
TBT: TX_0
514-0818
5%
1/20W
MF
201
2
20%
X5R
0.22UF
2
GND_VOID=TRUE
71 TBT_A_R2D_N & lt; 0 & gt;
TBT: RX_0
R3295
1K
5%
1/20W
MF
201
2
71 TBT_A_R2D_P & lt; 0 & gt;
F-RT-TH
GND_VOID=TRUE
1
1K
IN
DP Dir
J3200
R3294
71 25
DP Dir
MDP-J11
GND_VOID=TRUE
1
C3270
TBT Dir
2
20%
4V
CERM-X5R-1
0.47UF
B
10%
25V
X5R-CERM
0201
71 TBT_A_D2R_C_N & lt; 0 & gt;
C3275
C3205
0.01UF
71 TBT_A_D2R_C_P & lt; 0 & gt;
201
GND_VOID=TRUE
(0-18.9V)
(Both C’s)
2
20%
4V
CERM-X5R-1
0.47UF
10%
50V
X7R-CERM
0402
2
5%
1/20W
MF
201
0.01UF
GND_VOID=TRUE
71 25
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18.9V
R3201
0.01UF
2
Sink HPD range:
5%
1/20W
MF
201
High: 2.0 - 5.0V
Low:
0 - 0.8V
SYNC_MASTER=T29_RR
SYNC_DATE=10/26/2012
PAGE TITLE
Thunderbolt Connector A
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
32 OF 121
SHEET
28 OF 76
1
A
8
7
6
5
4
3
2
1
3.3V WLAN Switch
Part
Load Switch
R(on)
@ 2.5V
D
TPS22924C
Type
18.5 mOhm Typ
25.8 mOhm Max
Sense resistor on
sensor page
PP3V3_WLAN
1
U3550
TPS22924
PP3V3_WLAN_R
41
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
C3521
0.1UF
B1
514S0335
CRITICAL
B2
CRITICAL
ON
SMC_WIFI_PWR_EN IN
C2
BYPASS=J3501:5mm
29 37 39
GND
C1
2
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
A2
VIN
VOUT
Max Current = 2A (85C)
10%
6.3V
CERM-X5R
0201
PP3V3_S5
CSP
A1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
37 38 39 41 64
D
1
C3550
1.0UF
J3501
SSD-K99
2
AIRPORT
F-RT-SM1
20%
6.3V
X5R
0201-1
1
2
WIFI_EVENT_L
OUT
37 38 64
3
4
69 64
PCIE_AP_R2D_N
C3531
69 64
PCIE_AP_R2D_P
C3530
8
14 69
IN
14 69
PCIE_CLK100M_AP_N
PCIE_CLK100M_AP_P
IN
12 64 69
IN
12 64 69
OUT
14 64 69
OUT
14 64 69
16V
0201
2
10%
X5R-CERM
IN
PCIE_AP_R2D_C_P
10%
X5R-CERM
1
0.1UF
7
PCIE_AP_R2D_C_N
2
0.1UF
5
6
1
16V
0201
9
10
C
PCIE_AP_D2R_P
PCIE_AP_D2R_N
11
C
12
Supervisor & CLKREQ# Isolation
13
Delay = 130 ms +/- 20%
14
15
PP3V3_S5
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
16
PP3V3_S4
25 26 27 29 33 36 38 39 58 62
64
APCLKRQ:ISOL
18
R3553 1
19
1
C3532
21
2
10%
6.3V
CERM-X5R
0201
R3554
0
10%
6.3V
CERM-X5R
0201
TDFN
CRITICAL
SENSE +
VREF -
AP_RESET_CONN_R_L
4
RESET*
R3558
1
2
SLG4AP041V
2
BYPASS=J3501:1.5mm
AP_RESET_CONN_L
C3540
0.1UF
U3540
1%
1/20W
MF
201
2
P3V3WLAN_VMON
64
1
VDD
232K
5%
1/20W
MF
201 2
0.1UF
20
1
100K
1
17
DLY
2
MR*
IN
THRM
PAD
R3555
6
SMC_WIFI_PWR_EN
AP_CLKREQ_R_L
8
IN
PCIe Wake Muxing
2
60
29
13
17
57
74
59
28
11
16
42
64
1
58
18
8
15
34
62
1
100K
2
5%
1/20W
MF
201
APCLKRQ:BIDIR
R3556
2
5%
1/20W
MF
0201
B
R3557
0
SEL
C3560
1
5
0.1UF
10%
6.3V
CERM-X5R
0201
OUTPUT
L
H
2
1
AP_CLKREQ_L
BI
12
5%
1/20W
MF
0201
PCIE_WAKE_L (B0)
AP_S0IX_WAKE_L (B1)
VCC
2
CRITICAL
U3560
S
6
B0
B1
3
NOSTUFF
AP_S0IX_WAKE_SEL
PCIE_WAKE_L
AP_S0IX_WAKE_L
IN
15
R3559
NC7SB3157P6XG
SC70
VER-3
AP_PCIE_WAKE_L
29 37 39
0
1%
1/20W
MF
201
PP3V3_S5
R3561
15
APCLKRQ:ISOL
GND
100K
B
IN
(OD)
9
1
7
AP_RESET_L
5
AP_CLKREQ_Q_L
64
3
EN
OUT
5%
1/20W
MF
0201
4
A
0
2
1
OUT
OUT
15
1
13 31 64
5%
1/20W
MF
0201
GND
2
NOSTUFF
BLUETOOTH
R3560
0
1
2
36 33 29 27 26 25
64 62 58 39 38
PP3V3_S4
5%
1/20W
MF
0201
C3510
5
1
U3510
10%
6.3V
CERM-X5R
0201
2
USB3740
DFN
SMC_PME_S4_WAKE_L
0.1UF
VDD
DP_2
DM_2
DP_1
DM_1
1
14 68
USB_BT_N
7
2
Q3510
BI
BI
68 64
68 64
USB_BT_CONN_P
USB_BT_CONN_N
10
9
DP
DM
S
1
NC
5
SYNC_MASTER=J41_MLB
SYNC_DATE=02/06/2013
PAGE TITLE
Wireless Connector
DRAWING NUMBER
1
PM_SLP_S4_L
SEL
IN
4
R3512
Apple Inc.
15K
13 18 36 37 59
GND
8
6
2
3
4
L
H
7
S
G
BT_WAKE
OUTPUT
2
8
3
DFN1006H4-3
SYM_VER_2
OE*
SIGNAL_MODEL=BT_MUX
D
14 68
CRITICAL
A
36 37 39
DMN32D2LFB4
USB_BT_P
6
OUT
NO_XNET_CONNECTION=TRUE
1%
1/20W
MF
201
BT_WAKE (1)
USB_BT (2)
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
35 OF 121
SHEET
29 OF 76
1
A
8
7
6
5
4
3
2
1
OOB Isolation
D
64 62 41 30
D
PP3V3_S0SW_SSD
BYPASS=U3710:5 mm
1
C3718
0.1UF
2
PLACE_NEAR=J3700.1:3mm
CRITICAL
CRITICAL
L3700
74LVC1G08
SOT891
FERR-26-OHM-6A
1
PP3V3_S0SW_SSD
64 62 41 30
2
64
C3701
1
0.1UF
4
C3702
2
PLACE_NEAR=L3700.1:1mm
74 65 64 62 61
36 30 26 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
R3710
514S0449
CRITICAL
1
52
64
3
51
64
1%
1/20W
MF
201
2
2
61 59 56 45 44 43 42
18 17 15 13 12 11 8
41 40 39 38 36 30 26
74 65 64 62
6
64 15
IN
64
R3701 0
IN
SSD_BOOT
PCIE_SSD_R2D_C_N & lt; 3 & gt;
67 12
IN
PCIE_SSD_R2D_C_P & lt; 3 & gt;
C3711
67 12
IN
PCIE_SSD_R2D_C_N & lt; 2 & gt;
C3712
13
IN
67 12
C3710
1
2 GND_VOID=TRUE
10%
16V
X5R-CERM
1
2
1
2
0.1UF
GND_VOID=TRUE
10%
16V
X5R-CERM
0.1UF
C3713
PCIE_SSD_R2D_C_P & lt; 2 & gt;
IN
C3714
PCIE_SSD_R2D_C_N & lt; 1 & gt;
IN
1
2
GND_VOID=TRUE
10%
16V
X5R-CERM
1
2 GND_VOID=TRUE
10%
16V
X5R-CERM
C3715
PCIE_SSD_R2D_C_P & lt; 1 & gt;
IN
GND_VOID=TRUE
10%
16V
X5R-CERM
C3719
C3716
PCIE_SSD_R2D_C_N & lt; 0 & gt;
IN
1
C3717
PCIE_SSD_R2D_C_P & lt; 0 & gt;
IN
TRUE
11
45 TRUE
TRUE
12
44 TRUE
PCIE_SSD_R2D_N & lt; 2 & gt;
PCIE_SSD_R2D_P & lt; 2 & gt;
10%
10V
X5R-CERM
0201
GND_VOID=TRUE
10%
16V
X5R-CERM
1
14
42 TRUE
TRUE
15
41 TRUE
18
38 TRUE
TRUE
19
37 TRUE
TRUE
21
35 TRUE
TRUE
22
34 TRUE
23
67 64
0201
0201
64
PCIE_SSD_R2D_N & lt; 0 & gt;
PCIE_SSD_R2D_P & lt; 0 & gt;
SSD_CLKREQ_CONN_L
5%
1/20W
MF
201
2
12 64 67
OUT
12 64 67
OUT
OUT
12 64 67
OUT
12 64 67
PCIE_SSD_D2R_N & lt; 0 & gt;
PCIE_SSD_D2R_P & lt; 0 & gt;
OUT
12 64 67
OUT
3
12 64 67
PCIE_SSD_D2R_N & lt; 1 & gt;
PCIE_SSD_D2R_P & lt; 1 & gt;
5
12 64 67
100K
1%
1/20W
MF
201
NC
2
R3702
64 30
60
61
62
SSD_PCIE_SEL_L
0
1
2
63
PCIE_CLK100M_SSD_N
PCIE_CLK100M_SSD_P
IN
12 64 67
IN
5%
1/20W
MF
0201
12 64 67
PCIe polarity inversion and lane reversal
are only permitted on the device side,
provided the device PHY supports it.
B
17 35 36 37 38 40 46 49 50 59
61 62 64 65
C3740
0.1UF
VDD
1%
1/20W
MF
201
2
1
1
CRITICAL
232K
OUT
R3703 1
12 64 67
PCIE_SSD_D2R_N & lt; 2 & gt;
PCIE_SSD_D2R_P & lt; 2 & gt;
C
59
58
30 41 62 64
R3741
OUT
4
08
29
57
Delay = ~55ms
30
56
Supervisor & CLKREQ# Isolation
31
55
1
PCIE_SSD_D2R_N & lt; 3 & gt;
PCIE_SSD_D2R_P & lt; 3 & gt;
32
54
100K
U3711
NC
24
28
R3740 1
15 30 58 59 64
SMC_PWRFAIL_WARN_L Signal no connect on X31
33
27
Per Intel PDG, use PCIe style decoupling, when muxing PCIe & SATA
PP3V42_G3H
37 64
IN
36
0201
26
PP3V3_S0SW_SSD
IN
74LVC1G08
SOT891
39
TRUE
20
67 64
PCIE_SSD_R2D_N & lt; 1 & gt;
PCIE_SSD_R2D_P & lt; 1 & gt;
25
B
CRITICAL
6
2
40
17
0201
67 64
GND_VOID=TRUE
10%
16V
X5R-CERM
2
30 64
0201
2
0.1UF
OUT
43
TRUE
16
0201
2
0.1UF
67 12
46
13
67 64
SSD_PCIE_SEL_L
TP_SSD_DEVSLP
SMC_PWRFAIL_WARN_L
SSD_PWR_EN
1
0.1UF
1
10
0201
67 64
0.1UF
67 12
NOSTUFF
PCIE_SSD_R2D_N & lt; 3 & gt;
PCIE_SSD_R2D_P & lt; 3 & gt;
47
37
BYPASS=U3711:5 mm
SMC_OOB1_R2D_CONN_L
SMC_OOB1_D2R_CONN_L
9
2
1
0.1UF
67 12
67 64
48
8
SSD_SR_EN_L
SSD_RESET_CONN_L
SSD_BOOT_R
49
7
MF 0201 5% 1/20W
0201
67 64
0.1UF
67 12
2
67 64
GND_VOID=TRUE
10%
16V
X5R-CERM
0.1UF
67 12
1
50
OUT
PP3V3_S0
4
5
SMC_OOB1_D2R_L
NC
100K
GND_VOID
53
2
5
R3700
5%
1/20W
MF
201
J3700
F-RT-SM
37
NOSTUFF1
100K
SSD-GS3
GND_VOID
IN
1
NC
3
NOSTUFF1
10%
10V
X5R-CERM
0201
SMC_OOB1_R2D_L
2
PP3V3_S0
PLACE_NEAR=L3700.1:1mm
C
6
U3710
08
0.1UF
10%
10V
X5R-CERM
0201
2
PP3V3_S0SW_SSD_FLT
MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.15mm
VOLTAGE=3.3V
0603
1
10%
10V
X5R-CERM
0201
U3740
2
SLG4AP016V
10%
6.3V
CERM-X5R
0201
Gumstick3 Connector
TDFN
P3V3SSD_VMON
2
SENSE +
0.7V
-
4
RESET*
DLY
SSD_PWR_EN
SSD_CLKREQ_L
8
(OD)
THRM
PAD
R3742
SSD_RESET_L
6
IN
15
IN
15 30 58 59 64
OUT
12
GND
5
1
IN
3
EN
OUT
9
7
MR*
100K
2
1%
1/20W
MF
201
A
SYNC_MASTER=J43_MLB
SYNC_DATE=02/20/2013
PAGE TITLE
SSD Connector
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
37 OF 121
SHEET
30 OF 76
1
A
8
7
6
5
4
3
2
PP1V8_CAM
L3902
NOSTUFF
1.0UH-1.6A-55MOHM
72 32 31
BYPASS=U3900.K13:2.54MM
PP1V35_CAM
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.35V
1
L3906
1
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.35V
1
2
SYM 3 OF 3
CRITICAL
MIPI_AGND
2
2
N6
PCIE_GND
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0.675V
DDR_VDDIO_CK
G5
1
PCIE_VDD1P2
C8
C3930
1
4.7UF
20%
6.3V
X5R
402
2
2
20%
6.3V
X5R
402
2
2
2
2
10%
6.3V
CERM-X5R
0201
DDR_AVDD1P8
20%
6.3V
X5R
0201-1
20%
6.3V
CERM-X5R
0402-1
2
D6
C3932
1
5%
1/20W
MF
201
2
OTP_VDD3P3
D7
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.8V
SR_VDD_3P3C
1
BYPASS=U3900.D7:2.54MM
C3938
G1
2
H14
G6
C3928
2
4.7UF
E5
10%
16V
X7R-1
0201
20%
6.3V
X5R
402
1
1000PF
10%
6.3V
CERM-X5R
0201
2
C3971
1
C3972
2
0201
C3973
1
1000PF
0.1UF
10%
16V
2 X7R-1
10%
6.3V
CERM-X5R
0201
2
0201
C3974
1
10%
6.3V
CERM-X5R
0201
C3975
1
0.1UF
2
C3914
SR_VLXC_O
1
1
C3919
C3918
1
1000PF
10%
6.3V
CERM-X5R
0201
1
C3916
C3917
1000PF
0.1UF
10%
16V
2 X7R-1
2
0201
1
10%
6.3V
CERM-X5R
0201
C3910
1
0.1UF
10%
16V
2 X7R-1
2
0201
C3951
72 32
2
N14
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
DIDT=TRUE
SR_VLXD_O
10%
6.3V
CERM-X5R
0201
2
10%
6.3V
CERM-X5R
0201
72 32
VDD_1P35A
PP1V35_CAM
F14
VDD_3P3A
2
2
31
PP1V8_CAM
32 31
20%
6.3V
X5R
402
1
PP1V2_CAM_XTALPCIEVDD
1
PP3V3_S3RS0_CAMERA
C3942
1
C3940
1
C3934
1
1
C3935
C3936
1
0.1UF
1000PF
K7
10%
6.3V
CERM-X5R
0201
10%
16V
X7R-1
0201
PP1V8_CAM
2
K8
1
F6
F7
1
1UF
2
2
2
2
20%
6.3V
CERM
402-LF
BYPASS=U3900:7mm
BYPASS=U3900:3mm
BYPASS=U3900:5mm
BYPASS=U3900:5mm
2
PP1V2_CAM
L9
64 32
1K
2
69 32
69 32
64 32
BI
64 29 13
OUT
2
5%
1/20W
MF
0201
PP1V8_CAM
32 31
1
31
R3990
100K
72 32
72 32
OUT
OUT
31
31 32 72
72 32
PP1V2_CAM_XTALPCIEVDD
B13
OUT
72 32
17 31
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V
MAKE_BASE=TRUE
OUT
72 32
OUT
72 32
OUT
72 32
17 31
72 32
OUT
72 32
OUT
C3960
72 32
OUT
0.1UF
72 32
OUT
72 32
OUT
72 32
OUT
72 32
OUT
PP1V2_CAM_XTALPCIEVDD
1
2
10%
6.3V
CERM-X5R
0201
OUT
72 32
CAM_UARTRXD
OUT
72 32
CAM_UARTCTS
OUT
72 32
R3975
OUT
72 32
R3976
51K
OUT
72 32
5%
1/20W
MF
201
OUT
72 32
51K
5%
1/20W
MF
201
2
OUT
72 32
1
MIPI_DP0
MIPI_DM0
OUT
72 32
R3912
1
240
1%
1/20W
MF
201
7
MIPI_DP1
MIPI_DM1
PCIE_RDP0
PCIE_RDN0
PCIE_REFCLKP
PCIE_REFCLKN
PCIE_TDP0
PCIE_TDN0
OUT
2
72 32
OUT
72 32
OUT
6
C14
B14
A15
E11
E10
F11
F10
G11
G10
H11
H10
J10
K11
K10
L11
L10
TP_CAM_TEST_MODE0
TP_CAM_TEST_MODE1
TP_CAM_TEST_MODE2
TP_CAM_LV_JTAG_TCK
TP_CAM_LV_JTAG_TDI
TP_CAM_LV_JTAG_TDO
TP_CAM_LV_JTAG_TMS
TP_CAM_LV_JTAG_TRSTN
NC
NC
NC
NC
NC
NC
NC
NC
NC
C
PP1V8_CAM
32 31
NOSTUFF
100K
PCIE_TESTP
PCIE_TESTN
A13
D15
A12
R10
C15
R9
R12
GPIO_00
GPIO_01
GPIO_02
GPIO_03
GPIO_04
GPIO_05
GPIO_06
GPIO_07
XTAL_P
XTAL_N
I2C_CLK_DBG
I2C_CLK_SENSOR
I2C_DATA_DBG
I2C_DATA_SENSOR
F13
P13
E12
P12
P11
P10
P9
N11
N10
N9
CAM_RAMCFG0
CAM_RAMCFG1
CAM_RAMCFG2
CAM_GPIO3
TP_CAM_PLL_BYPASS
5%
1/20W
MF
201
31
31
NOSTUFF
R3937
F12
D12
D11
2
MEM_CAM_A & lt; 0 & gt;
MEM_CAM_A & lt; 1 & gt;
MEM_CAM_A & lt; 2 & gt;
MEM_CAM_A & lt; 3 & gt;
MEM_CAM_A & lt; 4 & gt;
MEM_CAM_A & lt; 5 & gt;
MEM_CAM_A & lt; 6 & gt;
MEM_CAM_A & lt; 7 & gt;
MEM_CAM_A & lt; 8 & gt;
MEM_CAM_A & lt; 9 & gt;
MEM_CAM_A & lt; 10 & gt;
MEM_CAM_A & lt; 11 & gt;
MEM_CAM_A & lt; 12 & gt;
MEM_CAM_A & lt; 13 & gt;
MEM_CAM_A & lt; 14 & gt;
L3
MEM_CAM_BA & lt; 0 & gt;
MEM_CAM_BA & lt; 1 & gt;
MEM_CAM_BA & lt; 2 & gt;
K3
MEM_CAM_CLK_P
MEM_CAM_CLK_N
H2
MEM_CAM_DM & lt; 0 & gt;
MEM_CAM_DM & lt; 1 & gt;
C1
MEM_CAM_ZQ_S2
MEM_CAM_CKE
MEM_CAM_CS_L
G3
M4
N3
M3
M1
M2
P4
N2
P3
P2
J4
R2
L1
P1
R4
L2
K2
G2
C4
J3
L4
SYM 2 OF 3
DDR_DQ00
DDR_DQ01
DDR_DQ02
DDR_DQ03
DDR_DQ04
DDR_DQ05
DDR_DQ06
DDR_DQ07
DDR_DQ08
DDR_DQ09
DDR_DQ10
DDR_DQ11
DDR_DQ12
DDR_DQ13
DDR_DQ14
DDR_DQ15
C2
DDR_DQS_P0
DDR_DQS_N0
E2
DDR_CK_P0
DDR_CK_N0
DDR_DQS_P1
DDR_DQS_N1
A2
DDR_DM0
DDR_DM1
DDR_RAS*
DDR_WE*
DDR_CAS*
DDR_RESET*
H3
DDR_AD00
DDR_AD01
DDR_AD02
DDR_AD03
DDR_AD04
DDR_AD05
DDR_AD06
DDR_AD07
DDR_AD08
DDR_AD09
DDR_AD10
DDR_AD11
DDR_AD12
DDR_AD13
DDR_AD14
CRITICAL
OMIT_TABLE
DDR_BA0
DDR_BA1
DDR_BA2
E3
E4
D3
F3
F1
F4
F2
B5
C3
B1
B4
A5
C5
B2
B3
MEM_CAM_DQ & lt; 0 & gt;
MEM_CAM_DQ & lt; 1 & gt;
MEM_CAM_DQ & lt; 2 & gt;
MEM_CAM_DQ & lt; 3 & gt;
MEM_CAM_DQ & lt; 4 & gt;
MEM_CAM_DQ & lt; 5 & gt;
MEM_CAM_DQ & lt; 6 & gt;
MEM_CAM_DQ & lt; 7 & gt;
MEM_CAM_DQ & lt; 8 & gt;
MEM_CAM_DQ & lt; 9 & gt;
MEM_CAM_DQ & lt; 10 & gt;
MEM_CAM_DQ & lt; 11 & gt;
MEM_CAM_DQ & lt; 12 & gt;
MEM_CAM_DQ & lt; 13 & gt;
MEM_CAM_DQ & lt; 14 & gt;
MEM_CAM_DQ & lt; 15 & gt;
12
18 15
5%
1/20W
MF
201
OUT
IN
C11
32 72
BI
32 72
BI
32 72
BI
32 72
BI
32 72
BI
E13
TEST_OUT
TEST_MODE
J12
M10
CAM_TEST_OUT
CAM_TEST_MODE
STRAP_XTAL_FREQ
C13
CAM_XTAL_FREQ
C12
CAM_XTAL_SEL
32 72
BI
32 72
32
IN
BI
32 72
18
IN
BI
32 72
BI
32 72
BI
BI
32 72
BI
32 72
BI
32 72
DDR_ZQ
DDR_CKE
DDR_CS*
A3
1
C3990
J2
H4
R3
H12
R3901
10%
6.3V
CERM-X5R
0201
2
32 31
CAM_A1
31
R3915
31
100K
CAM_SENSOR_WAKE_L
CAMERA_PWR_EN
2
PP1V8_CAM
CAM_TEST_MODE
5%
1/20W
MF
201
NO STUFF
1
1
100K
2
5%
1/20W
MF
201
CAM_XTAL_FREQ
2
4
2
5%
1/20W
MF
201
100K
2
5%
1/20W
MF
201
PU = 25MHz
1
32 72
32 72
32
SYNC_MASTER=J43_MLB1
Camera 1 of 2
DRAWING NUMBER
R3907
Apple Inc.
100K
2
5%
1/20W
MF
201
SYNC_DATE=01/09/2013
PAGE TITLE
31
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
5
R3911
100K
5%
1/20W
MF
201
R3906
CAM_XTAL_SEL
CAM_XTAL:NO
32 72
OUT
A1 SILICON BUG
31 32
1
R3910
100K
31
CAM_XTAL:YES
R3904
32 72
OUT
31
31
CAM_TEST_OUT
CAM_JTAG_SRST_L
31
OUT
31
PP1V8_CAM
1
32 72
OUT
B
31
PD = 1.35V
5%
1/20W
MF
201
PU on PCH page
BI
31
100K
0.1UF
2
BI
MEM_CAM_RAS_L
MEM_CAM_WE_L
MEM_CAM_CAS_L
MEM_CAM_RESET_L
CAM_UARTRXD
TP_CAM_UARTTXD
32 72
R13
NOSTUFF
1
31
5%
1/20W
MF
201 2
PWR_MODE
RESET*
SENSOR_WAKE*
SHUTDOWN*
32 72
BI
E15
32 72
BI
G12
PCIE_CLKREQ*
PCIE_RST*
PCIE_WAKE*
32 72
BI
MEM_CAM_DQS_P & lt; 1 & gt;
MEM_CAM_DQS_N & lt; 1 & gt;
N12
32 72
BI
1
D2
R14
CAM_PWR_SEL
CAM_DEBUG_RESET_L
BI
MEM_CAM_DQS_P & lt; 0 & gt;
MEM_CAM_DQS_N & lt; 0 & gt;
CAM_UARTCTS
TP_CAM_UARTRTS
UARTRXD
UARTTXD
E14
1
100K
D13
D14
2
31
NC
NC
NC
UARTCTS
UARTRTS
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST*
JTAG_SRST*
BYPASS=U3900.G15:2.54MM
31
B11
DEBUG_00
DEBUG_01
DEBUG_02
DEBUG_03
DEBUG_04
DEBUG_05
DEBUG_06
DEBUG_07
DEBUG_08
DEBUG_09
DEBUG_10
DEBUG_11
DEBUG_12
DEBUG_13
DEBUG_14
DEBUG_15
DEBUG_16
STRAP_XTAL_SEL
1
FBGA
K12
C9
CAMERA_CLKREQ_L
CAM_PCIE_RESET_L
CAM_PCIE_WAKE_L
0
PCIE_WAKE_L
BCM15700
PP1V2_CAM
PP1V35_CAM
B9
TP_CAM_JTAG_TCK
TP_CAM_JTAG_TDI
TP_CAM_JTAG_TDO
TP_CAM_JTAG_TMS
TP_CAM_JTAG_TRST_L
CAM_JTAG_SRST_L
NOSTUFF
BYPASS=U3900:5mm
U3900
M11
B8
I2C_CAM_SMBDBG_CLK
I2C_CAM_SCK
I2C_CAM_SMBDBG_DAT
I2C_CAM_SDA
IN
OUT
BYPASS=U3900.F15:2.54MM
R11
XTAL_AVDD1P2
SYM 1 OF 3
CRITICAL
OMIT_TABLE
2
R3991
VDDO18
VSENSE_C
VSENSE_D
A8
CLK25M_CAM_CLKP
CLK25M_CAM_CLKN
OUT
31
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V
B15
L3901:1
L3902:1
MIPI_CP_CLK
MIPI_CM_CLK
R3914 1
5%
1/20W
MF
201
BYPASS=U3900:3mm
10%
10V
X5R
402
L8
XTAL_AVSS
2
C3939
L6
L5
R5
E9
20%
6.3V
X5R
402
C3941
2.2UF
2
F9
R1
OUT
31
10%
6.3V
CERM-X5R
0201
VDDC
OUT
1K
0.1UF
10%
16V
X7R-1
0201
P5
A10
PCIE_CAMERA_D2R_C_P
PCIE_CAMERA_D2R_C_N
C3937
1000PF
N1
2
R3936 1
R3913 1
15 41
10%
6.3V
CERM-X5R
0201
F8
B10
2
0.1UF
G15
PCIE_CLK100M_CAMERA_C_P
PCIE_CLK100M_CAMERA_C_N
NC
NC
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
31 32 72
R6
A7
SM
GND_CAM_PVSSD
P6
B7
XW3901
20%
6.3V
X5R
402
M9
IN
69 32
C3926
4.7UF
A14
IN
69 32
K6
K9
IN
5%
1/20W
MF
201
F15
VDD1P8_O
R8
PCIE_CAMERA_R2D_P
PCIE_CAMERA_R2D_N
IN
69 32
J11
VDD1P2_O
P8
NC
NC
K1
K5
IN
69 32
J8
J9
R7
MIPI_DATA_P
MIPI_DATA_N
IN
72 32
4.7UF
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
DIDT=TRUE
K14
J6
J7
IN
P7
0.1UF
PLACE_NEAR=U3900.M14:2.54MM
1
P1V35_CAM_SRVLXD_PHASE
K13
J5
4.7UF
20%
6.3V
X5R
402
GND_CAM_PVSSC
31
MIPI_CLK_P
MIPI_CLK_N
IN
69 32
P1V2_CAM_SRVLXC_PHASE 31
H8
H9
31
PLACE_NEAR=U3900.M13:4MM
20%
6.3V
CERM-X5R
0402-1
2
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
M13
H7
P1V2_CAM_SRVLXC_PHASE
2
C3915
PLACE_NEAR=U3900.M13:2.54MM
(=PP3V3_S3RS0_CAMERA)
VSSC
1
4.7UF
10%
6.3V
CERM-X5R
0201
BYPASS=U3900.F6:2.54MM
BYPASS=U3900.F9:2.54MM
BYPASS=U3900.F6:2.54MM
BYPASS=U3900.L9:2.54MM
BYPASS=U3900.F9:2.54MM
BYPASS=U3900.L9:2.54MM
69 32
J13
H5
8
L3901
2
J15
2
5%
1/20W
MF
201
2
31
0.1UF
10%
16V
2 X7R-1
SM
GND_CAM_PVSSC
G9
D
330K
5%
1/20W
MF
201
2
1008
1
XW3900
J14
1
31
BYPASS=U3900.J1:2.54MM
BYPASS=U3900.L7:2.54MM
BYPASS=U3900.J1:2.54MM
BYPASS=U3900.D6:2.54MM
BYPASS=U3900.L7:2.54MM
BYPASS=U3900.D6:2.54MM
H15
SR_VDD_3P3D
R3935
330K
5%
1/20W
MF
201
2
1000PF
N15
G8
31
1
C3970
1
10UF
20%
6.3V
X5R
0201-1
0.1UF
(=PP3V3_S3RS0_CAMERA)
M15
31
R3933
330K
I2C_CAM_SMBDBG_CLK
I2C_CAM_SMBDBG_DAT
72 32
1
2
D1
A
R3931
1
U3900
1
31
1
BCM15700
M14
D5
31
FBGA
B6
G7
1
PP1V2_CAM
C3933
1.0UF
A6
B12
100K
5%
1/20W
MF
201
PP1V8_CAM
A1
31
R3921
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V
L14
L15
5%
1/20W
MF
201
2
CAM_RAMCFG2
CAM_RAMCFG1
CAM_RAMCFG0
L7
PLL_VDD1P8
SR_PVSSD
2
100K
0603
1
PP1V2_CAM_PCIE_PVDD_FLT
L12
B
1
R3920
17 31
0.1UF
PP1V2_CAM_PCIE_VDD_FLT
J1
5%
1/20W
MF
201
1.0UH-1.6A-55MOHM
31
L3904
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V
D9
MIPI_AVDD1P8
PP1V2_CAM_XTALPCIEVDD
10UF
1
PCIE_PVDD1P2
5%
1/20W
MF
201
R3934
100K
PP1V8_CAM
32 31
100K
220-OHM-1.4A
SR_PVSSC
1
R3932
C3931
1.0UF
C3927
N5
K15
H6
PLACE_NEAR=U3900.K13:4MM
0603
1
2
C
2
C3913
GND_CAM_PVSSD
31
10%
6.3V
CERM-X5R
0201
N13
L13
4.7UF
10%
6.3V
CERM-X5R
0201
2
1
1
32 72
PMU_AVSS
R15
GND_CAM_PVSSD
20%
6.3V
X5R
0201-1
1
PP0V675_CAM_VREF
N4
P14
31
0.1UF
C3912
220-OHM-1.4A
G4
DDR_VREF
P15
2
1
L3903
K4
G14
GND_CAM_PVSSC
1.0UF
10%
6.3V
CERM-X5R
0201
2
C3924
1
C3900
0.1UF
31
20%
6.3V
X5R
0201-1
C3923
D4
OMIT_TABLE
DDR_VDDIO
M12
1
0.1UF
A4
C10
C7
C3922
0.1UF
FBGA
N8
1
NOSTUFF
NOSTUFF
1
R3930
100K
31
0402
BCM15700
N7
C3921
1.0UF
22NH
D
1
P1V35_CAM_SRVLXD_PHASE
2
1008
PP1V35_DDR_CLK
U3900
1
1
31 32
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
39 OF 121
SHEET
31 OF 76
1
A
8
72 31
7
6
5
4
3
2
PP1V35_CAM
69 14
BYPASS=U4000.A1:4mm
1
BYPASS=U4000.B2:4mm
C4002
C4003
1
10UF
2
10UF
20%
6.3V
CERM-X5R
0402-1
2
PP0V675_CAM_VREF
1
0201
2
5%
1/20W
72
72
2
1
2
20%
10V
X5R-CERM
402
2
10%
6.3V
CERM-X5R
0201
PCIE_CAMERA_R2D_C_P
C4033
1
2
10%
PCIE_CAMERA_R2D_P
1
2
10%
PCIE_CAMERA_R2D_N
1
2
10%
PCIE_CAMERA_D2R_P
1
2
10%
PCIE_CAMERA_D2R_N
2
PCIE_CLK100M_CAMERA_C_P
0.1UF
69 14
0.1UF
2.2UF
10%
6.3V
CERM-X5R
0201
IN
C4009
10%
6.3V
CERM-X5R
0201
IN
PCIE_CAMERA_R2D_C_N
C4032
0.1UF
69 31
BYPASS=U4000.R9:4mm
IN
PCIE_CAMERA_D2R_C_P
C4031
0.1UF
IN
PCIE_CAMERA_D2R_C_N
C4030
0.1UF
69 12
IN
PCIE_CLK100M_CAMERA_P
C4061
IN
PCIE_CLK100M_CAMERA_N
C4062
1
1
C4011
1
16V
16V
16V
69 17
H1
M8
R9
R1
N9
N1
K8
K2
G7
D9
B2
H9
H2
F1
E9
D2
16V
72 31
IN
72 31
IN
72 31
IN
72 31
IN
NOSTUFF
R4003
1
1K
5%
1/20W
MF
201
72 31
IN
72 31
IN
72 31
IN
72 31
IN
72 31
IN
72 31
IN
72 31
2
IN
72 31
IN
72 31
IN
72 31
IN
72 31
IN
72 31
C
MEM_CAM_BA & lt; 0 & gt;
MEM_CAM_BA & lt; 1 & gt;
MEM_CAM_BA & lt; 2 & gt;
IN
IN
M2
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
N8
M3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
U4000
72 31
84.5
1%
1/20W
MF
201
2
MEM_CAM_RAS_L
MEM_CAM_CAS_L
MEM_CAM_WE_L
IN
72 31
R4020
IN
72 31
IN
K3
L3
MEM_CAM_CLK_P
MEM_CAM_CLK_N
IN
4GB-DDR3-256MX16
FBGA
NC
H5TC4G63AFR
NO STUFF
72 31
J7
K7
IN
M7
1
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQSL
DQSL*
F3
DQSU
DQSU*
C7
K1
69
14 69
D
OUT
31 69
IN
0201
31 69
OUT
0201
F2
F8
H3
H8
G2
H7
G3
B7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
DML
DMU
ODT
CLK25M_CAM_CLKP
2
5%
1/20W
31 69
MF
MEM_CAM_DQ & lt; 0 & gt;
MEM_CAM_DQ & lt; 1 & gt;
MEM_CAM_DQ & lt; 2 & gt;
MEM_CAM_DQ & lt; 3 & gt;
MEM_CAM_DQ & lt; 4 & gt;
MEM_CAM_DQ & lt; 5 & gt;
MEM_CAM_DQ & lt; 6 & gt;
MEM_CAM_DQ & lt; 7 & gt;
BI
31 72
BI
31 72
BI
31 72
BI
31 72
BI
31 72
BI
CRITICAL
BI
BI
R4012
E7
C3
C8
C2
A7
A2
B8
A3
CAM_XTAL:YES
1M
SM-3.2X2.5MM
2
1%
1/20W
MF
201
R4010
31 72
BI
2
5%
1/20W
MF
0201
31 72
MEM_CAM_DQS_P & lt; 1 & gt;
MEM_CAM_DQS_N & lt; 1 & gt;
1
25.000MHZ-12PF-20PPM
CAM_XTAL:YES
12PF
1
NOSTUFF
5%
1/20W
MF
Y4000
NC
NC
0
CLK25M_CAM_XTALP_R
31 72
BI
69
31 72
MEM_CAM_DQS_P & lt; 0 & gt;
MEM_CAM_DQS_N & lt; 0 & gt;
2
31 72
BI
1
31 72
BI
R4009
0
CLK25M_CAM_XTALP
0201
5%
25V
CERM
0201
31 72
MEM_CAM_DQ & lt; 8 & gt;
MEM_CAM_DQ & lt; 9 & gt;
MEM_CAM_DQ & lt; 10 & gt;
MEM_CAM_DQ & lt; 11 & gt;
MEM_CAM_DQ & lt; 12 & gt;
MEM_CAM_DQ & lt; 13 & gt;
MEM_CAM_DQ & lt; 14 & gt;
MEM_CAM_DQ & lt; 15 & gt;
BI
1
2
5%
25V
CERM
0201
69
CAM_XTAL:YES
CLK25M_CAM_XTALN
0
1
BI
31 72
BI
31 72
BI
31 72
1
C4016
0201
C
PP1V8_CAM
31
R4005
100K
31 72
BI
31 69
5%
31 72
BI
OUT
CAM_XTAL:NO
100PF
31 72
BI
CLK25M_CAM_CLKN
CAM_XTAL:YES
25V
2 C0G
31 72
BI
2
5%
1/20W
MF
0201
NOTE: TBD PPM crystal required
31 72
CAM_WAKE:YES
2
R4030
64 32
CAM_SENSOR_WAKE_L_CONN
1
0201
CAM_WAKE:NO
0
2
31
5%
1/20W
MF
201
CAM_SENSOR_WAKE_L
5%
1/20W
MF
R4031 1
0
R4021
T2
31 72
IN
31 72
5%
1/20W
MF
0201
2
J2
G8
E1
B3
A9
G9
G1
VSS
F9
E8
D8
D1
B1
E2
VSSQ
5%
25V
C0G
0201
1
IN
RESET*
100PF
B
MEM_CAM_DM & lt; 0 & gt;
MEM_CAM_DM & lt; 1 & gt;
T9
MEM_CAM_RESET_L
T1
IN
R4006
P9
31
NO STUFF
D3
ZQ
P1
MEM_CAM_CKE_R
L8
M9
MEM_CAM_ZQ_DDR
M1
72
1%
1/20W
MF
201
J8
82
2
2
1
CKE
CS*
MEM_CAM_ODT
F7
R4007
12PF
1
C4014
E3
CK
CK*
L2
CAM_XTAL:YES
NC
NC
NC
NC
NC
CRITICAL
RAS*
CAS*
WE*
K9
L1
L9
BA0
BA1
BA2
MEM_CAM_CKE
MEM_CAM_CS_L
IN
1
J3
C4015
J1
J9
IN
1
X5R-CERM
0
CAM_XTAL:NO
SYSCLK_CLK25M_CAMERA
IN
1
2
N3
2
72 31
MEM_CAM_A & lt; 0 & gt;
MEM_CAM_A & lt; 1 & gt;
MEM_CAM_A & lt; 2 & gt;
MEM_CAM_A & lt; 3 & gt;
MEM_CAM_A & lt; 4 & gt;
MEM_CAM_A & lt; 5 & gt;
MEM_CAM_A & lt; 6 & gt;
MEM_CAM_A & lt; 7 & gt;
MEM_CAM_A & lt; 8 & gt;
MEM_CAM_A & lt; 9 & gt;
MEM_CAM_A & lt; 10 & gt;
MEM_CAM_A & lt; 11 & gt;
MEM_CAM_A & lt; 12 & gt;
MEM_CAM_A & lt; 13 & gt;
MEM_CAM_A & lt; 14 & gt;
IN
4
1K
72 31
X5R-CERM
OUT
0201
14 69
CAM_XTAL:YES
3
VDD
VREFDQ
VDDQ
VREFCA
R4002 1
5%
1/20W
MF
201
X5R-CERM
OUT
0201
31 69
R4008
C9
2
X5R-CERM
0201
31 69
OUT
16V
10%
0.1UF
10%
6.3V
CERM-X5R
0201
C1
2
X5R-CERM
OUT
0201
PCIE_CLK100M_CAMERA_C_N
0201
1%
1/20W
MF
201 2
X5R-CERM
2
1
0.1UF
A8
0.1UF
16V
10%
0.1UF
69 12
C4010
2
20%
10V
X5R-CERM
402
C4008
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.675V
2
1
2
1
0.1UF
2.2UF
10%
6.3V
CERM-X5R
0201
BYPASS=U4000.K2:4mm
C4007
69 31
1K
72 31
2
1
PP0V675_MEM_CAM_VREFCA
R4023 1
72 31
0.1UF
20%
4V
CERM-X5R-1
201
C4006
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.675V
1K
72 31
1
PP0V675_MEM_CAM_VREFDQ
MF
R4022 1
1%
1/20W
MF
201
C4005
BYPASS=U4000.H9:4mm
0
A1
72 31
1
0.47UF
20%
6.3V
CERM-X5R
0402-1
2
BYPASS=U4000.D2:4mm
C4004
R4000
B9
D
1
1
R4004
B
240
2
1%
1/20W
MF
201
L4009
CAMERA SENSOR
90-OHM-0.1A-0.7-2GHZ
TAM0605
SYM_VER-1
CRITICAL
1
4
MIPI_CLK_N
IN
31 72
2
3
MIPI_CLK_P
IN
31 72
J4002
CCR20-AK7100-1
F-RT-SM
14
PLACE_NEAR=J4002.2:2.54MM
CRITICAL
1
2
72 64
3
72 64
4
5
72 64
6
72 64
MIPI_CLK_CONN_N
MIPI_CLK_CONN_P
CAM_SENSOR_WAKE_L_CONN
MIPI_DATA_CONN_N
MIPI_DATA_CONN_P
L4007
90-OHM-0.1A-0.7-2GHZ
TAM0605
SYM_VER-1
32 64
1
4
MIPI_DATA_N
BI
31 72
3
MIPI_DATA_P
BI
31 72
7
2
A
ALS
8
9
10
11
12
13
64
SMBUS_SMC_1_S0_SDA
SMBUS_SMC_1_S0_SCL
I2C_CAM_SCK
I2C_CAM_SDA
PP5V_S3RS0_ALSCAM_F
BI
14 37 40 43 44 64 69 73
IN
IN
PLACE_NEAR=J4002.2:2.54MM
CRITICAL
14 37 40 43 44 64 69 73
31 64
BI
SYNC_MASTER=J43_MLB
L4010
2
1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
PP5V_S0
Camera 2 of 2
16 17 45 51 52 56 58 59 61 62
64
DRAWING NUMBER
0402-LF
C4013
20%
10V
CERM
402
518S0892
Apple Inc.
NOSTUFF
1
L4011
0.1uF
2
R
1
PP5V_S4RS3
NOTICE OF PROPRIETARY PROPERTY:
7
& lt; E4LABEL & gt;
6
BRANCH
& lt; BRANCH & gt;
35 47 49 54 55 58 62 64
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
77.2 mA nominal max
96.2 mA peak
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
FERR-120-OHM-1.5A
2
0402-LF
8
SYNC_DATE=09/14/2012
PAGE TITLE
FERR-120-OHM-1.5A
31 64
PAGE
40 OF 121
SHEET
32 OF 76
1
A
8
7
6
5
4
3
2
1
PP3V3_S4
62 58 39 38 36 33 29 27 26 25
64
1
R4410
470K
Q4410
D
S
D
SMC_PME_SDCONN
1
DMN5L06VK-7
SOT563
5%
1/20W
MF
201
2
6
SMC_PME_S4_DARK_L
33 25
38 37
G 5
VER 3
Q4410
To SMC
5%
1/20W
MF
201
2
G 2
470K
D
VER 3
R4411
DMN5L06VK-7
1
SMC_PME_S4_DARK_L
SDCONN_STATE_CHANGE Isolation
4
3
38 37 33 25
S
D
SOT563
PP3V3_S3
64 62 58 41 40 36 19 18 15
CRITICAL
U4410
6
74AUP1G09
SOT891
VCC
16 15
XDP_SDCONN_STATE_CHANGE_L
OUT
A
2
B
1
NC
4
5
Y
BYPASS=U4410.5:5mm
To PCH
C4410
1
0.1UF
NC
GND
2
3
10%
6.3V
CERM-X5R
0201
PP3V3_S4
62 58 39 38 36 33 29 27 26 25
64
BYPASS=U4430.1:5mm
C4430
C
CRITICAL
1
10%
16V
X5R-CERM
0201
C
1
0.1UF
2
VDD
U4430
SLG4AP014V
TDFN
2
LOW_PWR
RST
LOGIC
DLY
FROM SD CONN - & gt;
(OD)
8
7
XOR
DET_IN
(IPU)
NC
RST_IN*
6
4
DET_CHNGD*
(OD)
3
RST_OUT*
(IPU)
DLY block is 20ms nominal
SDCONN_STATE_CHANGE_SAK_L
SDCONN_DETECT_L
OUT
34 75
DET_OUT
THRM
PAD
9
5
GND
SD CARD CONNECTOR
CRITICAL
516-0253
J4400
SD-CARD-K16
CRITICAL
B
F-RT-TH-1
R4480
L4400
47NH-1.3OHM
75 34 IN SDCONN_CLK
75 34
OUT SDCONN_CMD
75 34
BI SDCONN_DATA & lt; 0 & gt;
75 34
BI SDCONN_DATA & lt; 1 & gt;
75 34
BI SDCONN_DATA & lt; 2 & gt;
75 34
BI SDCONN_DATA & lt; 3 & gt;
R4479
33
1
2
5%
1/20W
R4461
R4471
R4472
R4473
R4474
MF
201
0
0
0
0
0
1
SDCONN_CLK_L
1
2
5%
1/20W
MF
2
5%
1/20W
MF
2
5%
1/20W
MF
2
5%
1/20W
MF
2
5%
1/20W
MF
5%
SDCONN_CLK_R2
3
402
MF-LF
1
6
1/16W
2
0201
1
0
1/16W
2
0201
1
R4481
402
MF-LF
1
0201
1
5%
SDCONN_CLK_R1
0201
1
0
0402
2
0201
SD_CONN_CLK
SDCONN_CMD_R
SDCONN_R_DATA & lt; 0 & gt;
SDCONN_R_DATA & lt; 1 & gt;
SDCONN_R_DATA & lt; 2 & gt;
SDCONN_R_DATA & lt; 3 & gt;
5
2
7
8
9
1
NC
NC
NC
NC
SD_CD_L
10
11
12
13
14
15
NOSTUFF
NOSTUFF
1
2
1
5%
50V
CERM
402
C4470
1
2
NOSTUFF
C4473
15PF
C4471
22PF
NOSTUFF
1
10PF
5%
50V
CERM
402
5%
50V
CERM
402
2
C4475
10PF
2
75 34
5%
50V
CERM
402
34
NOSTUFF
1
10PF
2
2
5%
50V
CERM
402
5%
50V
CERM
402
4
17
R4482
18
0
C4474
10PF
C4472
16
NOSTUFF
1
NOSTUFF
1
SDCONN_WP
OUT
PP3V3_S0_SD_CONN
2
5%
1/16W
MF-LF
402
19
NOSTUFF
1
20
B
VSS
VSS
CLK
CMD
DAT0
DAT1
DAT2
CD/DAT3
DAT4
DAT5
DAT6
DAT7
CARD_DETECT_SW
CARD_DETECT_GND
WRITE_PROTECT_SW
VDD
(CARD INSERTED = GROUND)
SHLD_PIN
SHLD_PIN
SHLD_PIN
SHLD_PIN
C4476
10PF
2
5%
50V
CERM
402
SD CARD
A
SYNC_MASTER=MASTER
SYNC_DATE=07/01/2011
PAGE TITLE
SD READER CONNECTOR
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
44 OF 121
SHEET
33 OF 76
1
A
8
7
6
5
3.3V S3 SD Card Switch
R4595 1
1
VDD
10K
5%
1/20W
MF
201
U4550
PP3V3_S0SW_SD
SLG5AP1443V
2
7
SD_PWR_EN
TDFN
CAP
2
P3V3_SD_FET_RAMP
D
2
1
NOSTUFF
IN
3
PP3V3_S5
42 29 28 18 17 16 15 13 11 8
74 64 62 60 59 58 57
15
4
ON
65 39 37 34 15
PP3V3_S0SW_SD
C4561
1
8
1
U4550
4700PF
10%
10V
X7R
201
2
D
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
GND
1.0UF
20%
6.3V
X5R
0201-1
5
15 34 37 39 65
3
S
CRITICAL
BYPASS=U4550.A2:5mm
C4560
D
EDP: 1.05A
2
Part
SLG5AP1438V
Type
Load Switch
R(on)
15 mOhm Typ
17 mOhm Max
Current
2.5A
CRITICAL
CRITICAL
L4500
L4501
FERR-1000-OHM-450MA
1
FERR-1000-OHM-450MA
2
PP1V2_S0_SD_AVDD12
BYPASS=U4500.46:5mm
C4523
1
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
2
0402
BYPASS=U4500.43:5mm
BYPASS=U4500.3:5mm
C4524
0.1UF
10%
16V
X5R-CERM
0201
PP3V3_S0_SD_AVDD33
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.2V
0402
1
C4525
1
0.1UF
10%
16V
X5R-CERM
0201
2
C4526
1
1.0UF
C4527
1
0.1UF
BYPASS=U4500.3:5mm
10%
6.3V
X5R-CERM
0201-1
2
10%
16V
X5R-CERM
0201
BYPASS=U4500.9:5mm
2
1
0.1UF
10%
16V
X5R-CERM
0201
2
C4528
1
2.2UF
2
BYPASS=U4500.43:5mm
20%
6.3V
CERM
402-LF
2
C
C
PP1V2_S3_SD_DVDD12
0.1UF
10%
16V
X5R-CERM
0201
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.2V
C4520
1
34 33
2.2UF
20%
4V
X5R-CERM
0201
2
PP1V2_S0_SD_VUHS1
PP3V3_S0_SD_CONN
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.20MM
2
C4529
900mA max
PP3V3_S0_SD_CONN
C4530
1
47PF
BYPASS=U4500.30:5mm
45
44
2
7
8
LQFN
X1
X2
30
22
5%
25V
NP0-C0G-CERM
0201
C4531
1
100PF
5%
25V
NP0-CERM
0201
2
1.0UF
10%
6.3V
X5R-CERM
0201-1
2
24
25
29
28
SDCONN_DATA & lt; 1 & gt;
SDCONN_DATA & lt; 0 & gt;
SDCONN_DATA & lt; 2 & gt;
SDCONN_DATA & lt; 3 & gt;
BI
IN
C4510
USB3_SD_R2D_C_N
1
0.1UF
68 65 14
IN
C4511
USB3_SD_R2D_C_P
PLACE_NEAR=U4500.5:5mm
0.1UF
16V
GND_VOID=TRUE
X5R-CERM
0201
68
2
10%
16V
GND_VOID=TRUE
X5R-CERM
0201
USB3_SD_R2D_N
USB3_SD_R2D_P
4
5
SD_RTERM
10
RXN
RXP
CRITICAL
1
SD_RESET_R_L
2
41
5%
1/20W
MF
201
1
R4500
680
0.047UF
1%
1/20W
MF
201
2
2
12
13
14
15
16
17
18
19
32
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
26
35
33
75
1
BYPASS=U4500.31:5mm
2
2
33 75
C4512
23
27
20
34
36
37
SDCONN_CLK
SDCONN_WP
SDCONN_CMD
SDCONN_DETECT_L
1
0.1UF
OUT
33 75
IN
0.1UF
1
2
10%
16V
2
10%
GND_VOID=TRUE
16V
X5R-CERM
GND_VOID=TRUE
X5R-CERM
USB3_SD_D2R_N
OUT
14 65 68
USB3_SD_D2R_P
OUT
14 65 68
0201
0201
33 75
BI
IN
PLACE_NEAR=U4500.2:5mm
B
33 75
33 75
C4590
1
BYPASS=U4590.8:5mm
1.0UF
SD_SPI_CLK
SD_SPI_CS_L
SD_SPI_MOSI
SD_SPI_MISO
10%
6.3V
X5R-CERM
0201-1
VCC
R4590 1
5%
1/20W
MF
201
USON
W25X05CL
NOSTUFF
5
DIO(IO0)
2
DO(IO1)
2
3.3K
2
2
5%
1/20W
MF
201
6
3
R4591
1
7
SD_SPI_WP_L
SD_SPI_HOLD_L
GND
9
CLK
CS*
WP*
HOLD*
THRM
PAD
1
3.3K
U4590
NC
512KB
6
10%
6.3V
X5R
201
10%
16V
X5R-CERM
0201
33 75
BI
USB3_SD_D2R_C_N
USB3_SD_D2R_C_P
THRM
PAD
C4570
1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SD_CLK
SD_WP
SD_CMD
SD_CDZ
LED
RSTZ* (IPU)
(IPU)
11
2 68
SPI_CK
75
SPI_CS
75
SPI_SI
75
SPI_SO
(IPU)
3.3K
SD_RESET_L
1 68
47
IN
C4518
0.1UF
2
33 75
BI
C4513
RTERM
GND
15
TXN
TXP
OMIT_TABLE
R4570
B
10%
6.3V
X5R-CERM
0201-1
PLACE_NEAR=U4500.1:5mm
2
10%
68
1
1
1.0UF
2
33 75
BI
PLACE_NEAR=U4500.4:5mm
68 65 14
20%
6.3V
X5R
402
1
BYPASS=U4500.22:5mm
C4522
1
4.7UF
BYPASS=U4500.30:5mm
VUHSI
40
SD_D1
SD_D0
SD_D2
SD_D3
U4500
GL3219
USB_SD_DP
V33IN
38
DVDD33
DVDD33
DVDD33
31
42
21
9
43
3
DM
DP
DVDD12
DVDD12
0
5%
1/20W
MF
0201
AVDD33
AVDD33
R4580 1
AVDD12
AVDD12
2
PMOS33
4.7UF
39
NO USB 2.0 INTERFACE
USB_SD_DM
1
46
BYPASS=U4500.39:5mm
20%
6.3V
X5R
402
C4521
BYPASS=U4500.30:5mm
VOLTAGE=3.3V
MAKE_BASE=TRUE
34 33
C4550
BYPASS=U4500.38:5mm
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.8V
1
8
C4519
BYPASS=U4500.21:5mm
4
BYPASS=U4500.42:5mm
USING ON CHIP CLOCK SOURCE MODE (CRYSTAL AS BACK-UP)
C4580
R4581
12PF
2
1
69
A
1
25.000MHZ-12PF-20PPM
2
75 69
1
SDCLK_CLK25M_X2_R
R4582
1M
5%
1/20W
MF
2 201
3
12PF
0
5%
1/20W
MF
0201
Y4580
4
C4581
1
CRITICAL
2
NC
NC
1
5%
25V
NP0-C0G-CERM
0201
SDCLK_CLK25M_X2
SM-3.2X2.5MM
2
69
SDSCLK_CLK25M_X1
SYNC_MASTER=MASTER
SYNC_DATE=10/11/2010
PAGE TITLE
5%
25V
NP0-C0G-CERM
0201
SD CONTROLLER (GL3219)
DRAWING NUMBER
Apple Inc.
& lt; SCH_NUM & gt;
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
45 OF 121
SHEET
34 OF 76
1
SIZE
D
A
8
7
6
5
4
3
2
1
Right USB Port A
D
USB Port Power Switch
D
CRITICAL
CRITICAL
L4605
U4600
FERR-120-OHM-3A
TPS2557DRB
PP5V_S3_RTUSB_A_ILIM
SON
64 62 58 55 54 49 47 32
2
PP5V_S4RS3
3
IN_0
IN_1
OUT1
OUT2
ILIM
5
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.15 mm
VOLTAGE=5V
6
FAULT*
1
7
2
PP5V_S3_RTUSB_A_F
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V
0603
C4605
1
0.01UF
OUT
65 61 59
XDP_USB_EXTA_OC_L
8
USB_PWR_EN
4
EN
CRITICAL
1
1
10UF
20%
6.3V
CERM-X5R
0402-1
1
C4691
GND
C4696
0.1UF
2
2
R4600
1%
1/20W
MF
201
220UF-35MOHM
10%
16V
X5R-CERM
0201
2
10%
16V
X5R-CERM
0201
1
CRITICAL
2
J4600
USB3.0-J11-J13
22.1K
THRM
PAD
1
C4690
USB_ILIM
9
16 14
F-RT-TH
CRITICAL
C4695
1
20%
6.3V
CERM-X5R
0402-1
R4601
VBUS
SSTX+
SSTXGND
DD+
GND
SXRX+
SSRXGND
2
DLP0NS
SYM_VER-1
3
2
4
3
1
2
4
22.1K
2
1
90-OHM
10UF
2
USB_ILIM_R
20%
6.3V
POLY-TANT
CASE-B2-SM1
L4600
1
68
1%
1/20W
MF
201
68
USB2_EXTA_MUXED_N
USB2_EXTA_MUXED_P
68
68
5
USB2_EXTA_MUXED_F_N
USB2_EXTA_MUXED_F_P
6
7
8
CRITICAL
2
2
D4601
Current limit per port (R4600+R4601): 2.19A min / 2.76A max
9
D4600
ESD112-B1-02ELS
10
ESD112-B1-02ELS
0201-THICKSTNCL
0201-THICKSTNCL
1
C
CRITICAL
11
1
C
12
13
14
15
Mojo SMC Debug Mux
16
17
18
59 50 49 46 40 38 37 36 30 17
65 64 62 61
PP3V42_G3H
BYPASS=U4650.9:3:5mm
C4650
1
1
0.1UF
68 38 37
IN
68 38 37
OUT
R4650
100K
9
10%
10V
X5R-CERM
0201
2
VCC
SMC_DEBUGPRT_RX_L
SMC_DEBUGPRT_TX_L
5
USB_EXTA_P
USB_EXTA_N
7
4
M+
M-
U4650
2
Y+
Y-
68 14
OUT
68 14
OUT
APN: 514-0819
USB3_EXTA_D2R_N
USB3_EXTA_D2R_P
5%
1/20W
MF
201
1
2
PI3USB102EZLE
68 14
68 14
BI
BI
6
D+
D-
GND_VOID=TRUE
TQFN
GND_VOID=TRUE
CRITICAL
CRITICAL
2
2
D4621
ESD112-B1-02ELS
ESD112-B1-02ELS
0201-THICKSTNCL
8
OE*
SEL
SIGNAL_MODEL=MOJO_MUX_SMSC
10
SMC_DEBUGPRT_EN_L
SEL
IN
0201-THICKSTNCL
37
1
1
OUTPUT
3
GND
CRITICAL
D4620
L
H
SMC (M)
USB (D)
B
B
GND_VOID=TRUE
C4620
0.1UF
68 14
IN
USB3_EXTA_R2D_C_N
1
2
68 USB3_EXTA_R2D_N
C4621
10%
6.3V
CERM-X5R 0201
68 14
IN
USB3_EXTA_R2D_C_P
0.1UF
1
10%
2
68 USB3_EXTA_R2D_P
6.3V
CERM-X5R 0201
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
CRITICAL
2
2
D4611
ESD112-B1-02ELS
0201-THICKSTNCL
0201-THICKSTNCL
1
A
CRITICAL
D4610
ESD112-B1-02ELS
1
SYNC_MASTER=J43_MLB
SYNC_DATE=02/20/2013
PAGE TITLE
External A USB3 Connector
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
46 OF 121
SHEET
35 OF 76
1
A
8
7
6
5
4
3
2
1
PLACE_NEAR=J4800.10:1.5MM
R4830
62 58 39 38 36 33 29 27 26 25
64
PP3V3_S4
0
1
2
5%
1/20W
MF
0201
C4800
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.5 mm
1
IPD Flex Connector
0.1UF
10%
6.3V
CERM-X5R
0201
2
BYPASS=J4800.10:1.5MM
CRITICAL
PLACE_NEAR=J4800.14:1.5MM
D
518S0884
L4820
1
PP5V_S5
62 54 53
TF13BS-20S-0.4SH
F-RT-SM-1
22
2
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
0402-LF
C4810
1
R4850
65 64 61 38 37 36
33
0.1UF
10%
16V
X5R-CERM
0201
15
68
OUT TPAD_SPI_MISO
5%
2
1
1/20W
64
MF
50 49 46 40 38 37 35 30 17
65 64 62 61 59
PP3V42_G3H
C4820
2
3
10%
6.3V
CERM-X5R
0201
0
15
68
5%
1/20W
MF
0201
TPAD_INTWAKE:SHARED
R4843
0
SMC_PME_S4_WAKE_L
1
(TPAD_SPI_INT_S4_WAKE_L_CONN)
2
5%
1/20W
MF
0201
To SMC
PLACE_NEAR=R4841.1:1.5MM
IN
IN
2
(TPAD_WAKE_L)
2
5
6
15
68
R4841
1
BI
1
TPAD_INTWAKE:SPLIT
PLACE_NEAR=R4844.1:1.5MM
4
USB_TPAD_P
USB_TPAD_N
BI
68 64 14
0.1UF
OUT
1
SMC_LID
TPAD_SPI_MISO_R
201
68 64 14
BYPASS=J4800.19:1.5MM
39 37 29
IN
2
PLACE_NEAR=J4800.2:2.54mm
PLACE_NEAR=J4800.14:1.5MM
D
J4800
FERR-120-OHM-1.5A
TPAD_SPI_CLK
33
R4851
TPAD_SPI_CLK_R
64 TPAD_WAKE_L
PLACE_NEAR=J4800.7:2.54mm
33
1
2
TPAD_SPI_MOSI
R4852 64 TPAD_SPI_MOSI_R
5%
1/20W
MF
201
64 PP3V3_S4_IPD
PLACE_NEAR=J4800.9:2.54mm
33
1
2
R4853 64 TPAD_SPI_CS_R_L
5%
1/20W
MF
201
64 TPAD_SPI_IF_EN_CONN
PLACE_NEAR=J4800.12:2.54mm
64 TPAD_SPI_INT_S4_WAKE_L_CONN
64 PP5V_S4_IPD
64 TPAD_USB_IF_EN_CONN
SMBUS_SMC_3_SDA
73 64 44 40 37 36 BI
SMBUS_SMC_3_SCL
73 64 44 40 37 36 BI
SMC_LSOC_RST_L
64 38 36
OUT
(=PP3V42_G3H_IPD)
SMC_ONOFF_L
64 38 37 36
OUT
5%
1
1/20W
2
MF
7
64
201
8
9
10
11
12
13
14
15
16
17
18
19
20
21
C
C
TPAD_INTWAKE:SHARED
TPAD_INTWAKE:SHARED
1
0
Q4800
1
PP3V3_S3
5%
1/20W
MF
0201
DMN32D2LFB4
G
64 62 58 41 40 36 33 19 18 15
R4844
DFN1006H4-3
SYM_VER_3
2
D
3
TPAD_SPI_INT_L
2
OUT
S
PLACE_NEAR=J4800.8:1.5MM
15
To PCH
PLACE_NEAR=R4842.2:5MM
TPAD_INTWAKE:SPLIT
R4842
0
1
2
5%
1/20W
MF
0201
PLACE_NEAR=R4843.2:1.5MM
62 58 39 38 36 33 29 27 26 25
64
PP3V3_S4
C4841
1
0.1UF
BYPASS=U4810:3mm
10%
6.3V
CERM-X5R
0201
2
CRITICAL
8 74LVC2G08GT/S505
59 37 36 29 18 13
IN
PM_SLP_S4_L
1
15
IN
TPAD_USB_IF_EN
SOT833
2
A
U4810
B
From PCH
B
7
(TPAD_USB_IF_EN_CONN)
B
4
NOSTUFF
1
Y
08
R4810
100K
2
5%
1/20W
MF
201
CKPLUS_WAIVE=UNCONNECTED_PINS
8 74LVC2G08GT/S505
59 37 36 29 18 13
5
PM_SLP_S4_L
IN
SOT833
A
U4810
15
6
TPAD_SPI_IF_EN
IN
B
Y
3
(TPAD_SPI_IF_EN_CONN)
08
4
From PCH
64 62 58 41 40 36 33 19 18 15
PP3V3_S3
G
PP3V3_S0
1
1
74 65 64 62
38 30 26 18 17 15 13 12 11 8
61 59 56 45 44 43 42 41 40 39
Q4860
DFN1006H4-3
SYM_VER_3
NOSTUFF
1
C4832
100PF
5%
25V
2 C0G
0201
IN
TPAD_SPI_CS_L
D
15
36 37 40 44 64 73
5%
1/20W
MF
201
TPAD_SPI_CS_CONN_L
3
36 37 40 44 64 73
2
SMBUS_SMC_3_SDA
SMBUS_SMC_3_SCL
SMC_ONOFF_L
SMC_LID
SMC_LSOC_RST_L
S
2
A
R4860
100K
DMN32D2LFB4
SYNC_MASTER=J43_MLB
36 37 38 64
SYNC_DATE=01/17/2013
PAGE TITLE
36 37 38 61 64 65
IPD Connector
36 38 64
NOSTUFF
1
C4833
100PF
5%
25V
2 C0G
0201
DRAWING NUMBER
1
C4834
100PF
5%
25V
2 C0G
0201
1
C4835
100PF
5%
25V
2 C0G
0201
1
C4836
Apple Inc.
100PF
5%
25V
& lt; SCH_NUM & gt;
REVISION
R
& lt; E4LABEL & gt;
2 C0G
0201
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
BYPASS=J4800.4:1.5MM
BYPASS=J4800.6:1.5MM BYPASS=J4800.5:1.5mm
8
BYPASS=J4800.3:8.5MM
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
BYPASS=J4800.1:1.5MM
7
6
5
4
3
2
& lt; BRANCH & gt;
PAGE
48 OF 121
SHEET
36 OF 76
1
SIZE
D
A
8
7
6
5
4
3
2
1
D
D
U5000
LM4FSXAH5BB
69 64 14
BI
69 64 14
BI
69 64 14
69 64 14
BI
BI
69 17
IN
69 64 14
IN
18
IN
64 15
BI
64 13
OUT
64 13
IN
13
OUT
15
OUT
73 60 40
73 60 40
BI
BI
73 69 64 44 43 40 32 14
BI
73 69 64 44 43 40 32 14
BI
73 65 61 40
BI
73 65 61 40
BI
73 64 44 40 36
C
73 64 44 40 36
BI
BI
64
BI
64
BI
73 64 50 48 40
BI
73 64 50 48 40
BI
45
OUT
45
IN
64
OUT
64
IN
39
OUT
58 42 39
OUT
56
OUT
64
OUT
39
65 61
64
39
38
OUT
IN
OUT
OUT
BI
38
OUT
38
IN
64
39 36 29
B
IN
IN
38 33 25
IN
59 38
OUT
39 38
IN
LPC_AD & lt; 0 & gt;
LPC_AD & lt; 1 & gt;
LPC_AD & lt; 2 & gt;
LPC_AD & lt; 3 & gt;
LPC_CLK24M_SMC
LPC_FRAME_L
SMC_LRESET_L
LPC_SERIRQ
PM_CLKRUN_L
LPC_PWRDWN_L
SMC_RUNTIME_SCI_L
SMC_WAKE_SCI_L
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA
SMBUS_SMC_2_S3_SCL
SMBUS_SMC_2_S3_SDA
SMBUS_SMC_3_SCL
SMBUS_SMC_3_SDA
NC_SMBUS_SMC_4_ASF_SCL
NC_SMBUS_SMC_4_ASF_SDA
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA
B13
A13
C12
D11
H12
D12
C13
(OD)
H13
(OD)
G11
F13
F12
B12
(OD)
E10
(OD)
D13
(OD)
M4
(OD)
N2
(OD)
N8
(OD)
M8
(OD)
L8
(OD)
K8
(OD)
N7
(OD)
M7
(OD)
N4
(OD)
N3
SMC_FAN_0_CTL
SMC_FAN_0_TACH
NC_SMC_FAN_1_CTL
NC_SMC_FAN_1_TACH
SMC_TOPBLK_SWP_L
SMC_SENSOR_PWR_EN
SMC_SYS_KBDLED
NC_SMC_T25_EN_L
TP_SMC_5VSW_PWR_EN
SYS_ONEWIRE
NC_SMC_FAN_5_CTL
SMC_PCH_SUSACK_L
H11
L13
C11
A12
G3
D10
L11
N12
N11
M11
J4
J2
(OD)
CPU_PECI_R
SMC_PECI_L
C4
C6
SMC_BIL_BUTTON_L
NC_SMC_DP_HPD_L
SMC_PME_S4_WAKE_L
SMC_PME_S4_DARK_L
SMC_S4_WAKESRC_EN
SMC_SENSOR_ALERT_L
M13
L12
M5
J12
J13
L5
(OD)
NC
65 64 61 38 36
IN
D8
SMC_LID
K6
SMC_PCH_SUSWARN_L
SMS_INT_L
SMC_BC_ACOK
PM_SLP_S0_L
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
SMC_ONOFF_L
D4
BGA
AIN00
AIN01
AIN02
AIN03
AIN04
AIN05
AIN06
AIN07
AIN08
AIN09
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
AIN16
AIN17
AIN18
AIN19
AIN20
AIN21
AIN22
AIN23
C0C0+
C1PC5/C1+
T3CCP1/PJ5/C2T3CCP0/PJ4/C2+
K2
I2C0SCL
I2C0SDA
I2C1SCL
I2C1SDA
I2C2SCL
I2C2SDA
I2C3SCL
I2C3SDA
I2C4SCL
I2C4SDA
I2C5SCL
I2C5SDA
PM6/FAN0PWM0
PM7/FAN0TACH0
PK6/FAN0PWM1
PK7/FAN0TACH1
PN2/FAN0PWM2
PN3/FAN0TACH2
PN4/FAN0PWM3
PN5/FAN0TACH3
PN6/FAN0PWM4
PN7/FAN0TACH4
PH2/FAN0PWM5
PH3/FAN0TACH5
PECI0RX
PECI0TX
PP0/IRQ116
PP1/IRQ117
PP2/IRQ118
PP3/IRQ119
PP4/IRQ120
PP5/IRQ121
PP6/IRQ122
PP7/IRQ123
SMC_HS_COMPUTING_ISENSE
SMC_PBUS_VSENSE
SMC_BMON_ISENSE
SMC_DCIN_ISENSE
SMC_DCIN_VSENSE
SMC_BMON_DISCRETE_ISENSE
SMC_CPU_ISENSE
SMC_OTHER_HI_ISENSE
SMC_PANEL_ISENSE
SMC_1V2S3_ISENSE
SMC_LCDBKLT_ISENSE
SMC_P3V3S5_ISENSE
SMC_WLAN_ISENSE
SMC_SSD_ISENSE
SMC_P3V3S0_ISENSE
SMC_CAMERA_ISENSE
PP3V3_S0SW_SD
SMC_P1V05S0_VSENSE
SMC_CPUDDR_ISENSE
SMC_P1V05S0_ISENSE
SMC_CPU_VSENSE
SMC_CPUVR_ADJUST_ISENSE
SMC_CPU_IMON_ISENSE
PP3V3_WLAN
E2
LPC0AD0
(1 OF 2)
LPC0AD1
OMIT_TABLE
LPC0AD2
LPC0AD3
LPC0CLK
LPC0FRAME*
LPC0RESET*
LPC0SERIRQ
LPC0CLKRUN*
LPC0PD*
LPC0SCI*
PK5
E1
F2
F1
B3
A3
B4
A4
B5
A5
B6
A6
C1
C2
B1
B2
G2
G1
H1
H2
B7
A7
B8
A8
39 42
IN
39 41
IN
39 41
IN
39 42
IN
39 43
IN
39 42
IN
39 41
IN
39 43
IN
39 41
IN
39 41
IN
39 41
IN
39 41
IN
39 42
IN
L1
SPI_DESCRIPTOR_OVERRIDE_L
C5
CPU_CATERR_L
CPU_THRMTRIP_3V3
2
15 34 39 65
IN
L5001
30-OHM-1.7A
1
39 41
IN
17 30 35 36 38 40 46 49 50 59
61 62 64 65
39 42
IN
PP3V42_G3H
39 41
IN
39 42
IN
1
1
C5002
1
C5003
1
C5004
1
C5005
39 42
IN
0.1UF
0.1UF
10%
10V
X5R-CERM
0201
10%
10V
X5R-CERM
0201
10%
10V
X5R-CERM
0201
2
2
2
2
2
50 46 38
64
IN
64 38 29
1
C5007
1
C5008
1
BI
C5009
0.1UF
2
29 38 39 41 64
0.1UF
0.1UF
10%
10V
X5R-CERM
0201
10%
10V
X5R-CERM
0201
10%
10V
X5R-CERM
0201
2
38
2
IN
69 38
IN
38
38
WIFI_EVENT_L
SMC_WAKE_L
NC_SMC_HIB_L
B11
(OD)
N13
M12
M10
SMC_CLK32K
NC_SMC_XOSC1
N10
G12
G13
K12
6 67
IN
0.1UF
(2 OF 2)
SWCLK/TCK
SWDIO/TMS
PK4/RTCCLK
SWO/TDO
WAKE*
TDI
HIB*
NC
XOSC0
XOSC1
VDDA
OSC0
OSC1
VREFA+
VREFAVBAT
RST*
C10
A11
B10
A2
GNDA
38 46 64
38 46 64
38 64
IN
38
IN
65 61 50 38
IN
18 13
IN
59 18 17 13
IN
59 36 29 18 13
IN
59 13
IN
64 38 36
IN
64 38
IN
64 38
OUT
64 30
OUT
39 29
OUT
E4
F5
N5
N6
K5
M6
L6
L3
SMC_RX_L
SMC_TX_L
M1
SMC_PWRFAIL_WARN_L
SMC_WIFI_PWR_EN
E13
(OD)
E12
PQ0/IRQ124
PQ1/IRQ125
PQ2/IRQ126
PQ3/IRQ127
PQ4/IRQ128
PQ5/IRQ129
PQ6/IRQ130
PQ7/IRQ131
U0RX
U0TX
USB0DM (PL7)
USB0DP (PL6)
C
38 64
NC
D3
PP3V3_S5_AVREF_SMC
D2
38
D1
38
D7
SMC_TCK
SMC_TMS
SMC_TDO
SMC_TDI
A10
XW5000
SM
43 42
41
C3 38
GND_SMC_AVSS
2
1
E3
PLACE_NEAR=U5000.A1:4MM
SSI0CLK/PA2
SSI0FSS/PA3
SSI0RX/PA4
SSI0TX/PA5
SMC_PM_G2_EN
PM_DSW_PWRGD
SMC_DELAYED_PWRGD
SMC_PROCHOT
M2
M3
L4
N1
OUT
OUT
13
OUT
17 26 27 38
OUT
E6
38 54 59
38
OMIT_TABLE
E8
A1
E9
F10
C7
D9
VDD
J7
U1RX/B0
U1TX/PB1
T0CCP0/PB6
T0CCP1/PB7
SMC_DEBUGPRT_RX_L
SMC_DEBUGPRT_TX_L
NC_SMC_SYS_LED
NC_SMC_GFX_THROTTLE_L
F11
E11
F4
F3
SSI1RX/PF0
SSI1TX/PF1
SSI1CLK/PF2
SSI1FSS/PF3
PF4
PF5
K7
WT2CCP0/PH0
WT2CCP1/PH1
K3
WT3CCP0/PH4
WT3CCP1/PH5
WT4CCP0/PH6
WT4CCP1/PH7
J3
T1CCP0/PJ0
T1CCP1/PJ1
T2CCP0/PJ2
T2CCP1/PJ3
C9
N9
L10
K10
L9
K9
F9
H5
1
35 38 68
OUT
64
BI
WT5CCP1/PM3
PM_PWRBTN_L
PM_SYSRST_L
MEM_EVENT_L
SMC_ADAPTER_EN
H4
H3
GND
PP1V2_S5_SMC_VDDC
J1
J6
G4
C8
SMC_OOB1_D2R_L
SMC_OOB1_R2D_L
SMC_CPU_DBGPWR_RD_L
NC_BDV_BKL_PWM
H10
PM_BATLOW_L
B9
A9
10%
10V
X5R-CERM
0201
2
J5
MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.1MM
VOLTAGE=1.2V
64
C5021
1UF
2
20%
6.3V
X5R
0201
J8
46 69
K13
46 69
VDDC
J11
D6
OUT
46 69
OUT
13 16 17
BYPASS=U5000.D2:D1:1MM
54 59
IN
BYPASS=U5000.D2:D1:1MM
K11
46 69
IN
OUT
B
PLACE_NEAR=U5000.D6:5MM
PLACE_NEAR=U5000.K13:5MM
PLACE_NEAR=U5000.J6:5MM
PLACE_NEAR=U5000.J1:5MM
PLACE_NEAR=U5000.D6:5MM
PLACE_NEAR=U5000.K13:5MM
PLACE_NEAR=U5000.J6:5MM
PLACE_NEAR=U5000.J1:5MM
35
IN
64
IN
1
2
16 17 59
OUT
38
OUT
C5010
1
C5017
1
C5015
1
C5016
1
C5014
1
C5012
1
C5013
1.0UF
0.1UF
0.1UF
1.0UF
0.1UF
20%
6.3V
X5R
0201-1
10%
10V
X5R-CERM
0201
10%
10V
X5R-CERM
0201
20%
6.3V
X5R
0201-1
10%
10V
X5R-CERM
0201
10%
10V
X5R-CERM
0201
1
0.1UF
20%
6.3V
X5R
0201-1
2
2
2
2
2
2
C5011
0.1UF
2
10%
10V
X5R-CERM
0201
13 16
OUT
(OD)
1
0.01UF
IN
ALL_SYS_PWRGD
SMC_THRMTRIP
K4
C5020
H9
OUT
SMC_DEBUGPRT_EN_L
NC_SMC_GFX_OVERTEMP
L7
E5
J10
35 38 68
OUT
SPI_SMC_MISO
SPI_SMC_MOSI
SPI_SMC_CLK
SPI_SMC_CS_L
S5_PWRGD
PM_PCH_SYS_PWROK
M9
WT0CCP0/PG4
WT0CCP1/PG5
IN
J9
1.0UF
39
10%
10V
X5R-CERM
0201
BGA
G10
SMC_RESET_L
17
IN
C5001
2
LM4FSXAH5BB
SMC_EXTAL
SMC_XTAL
38
1
U5000
5%
1/20W
MF
201
6 38 51 67
OUT
MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.1MM
VOLTAGE=3.3V
R5002
1M
0.1UF
10%
10V
X5R-CERM
0201
39 43
IN
C5006
0.1UF
20%
6.3V
X5R
0201
39 43
IN
1
1UF
39 42
IN
PP3V3_S5_SMC_VDDA
0402
2
IN
L2
D5
39 41
IN
IN
CPU_PROCHOT_L
SMC_VCCIO_CPU_DIV2
SMC_S5_PWRGD_VIN
K1
IN
13 17 64
BI
OUT
IN
38
13 38
30
OUT
30
OUT
43
OUT
64
OUT
13 27
NOTE:
SMS Interrupt can be active high or low, rename net accordingly.
If SMS interrupt is not used, pull up to SMC rail.
A
NOTE:
Unused pins have " SMC_Pxx " names.
SYNC_MASTER=J41_MLB
Unused
SYNC_DATE=02/06/2013
PAGE TITLE
pins designed as outputs can be left floating,
SMC
those designated as inputs require pull-ups.
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
50 OF 121
SHEET
37 OF 76
1
A
8
7
6
5
4
3
2
1
SMC Reset " Button " , Supervisor & AVREF Supply
R5127
65
49
35
38
61
64
46
30
37
59
62
40
17
36
50
PP3V42_G3H
0
1
67 51 37 6
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=3.42V
NOSTUFF
5%
1/16W
MF-LF
402
1
C5127
6
C5131
Q5159
D
DMN5L06VK-7
1
SOT563
47PF
4.7UF
2
43 42 41 38 37
CPU_PROCHOT_L
BI
PP3V42_G3H_SMC_SPVSR
2
5%
25V
C0G
0201
20%
6.3V
X5R
402
GND_SMC_AVSS
PP3V42_G3H
17
2
S
G 2
Desktops: 5V
C5120
Mobiles: 3.42V
IN
MR1* (IPU) SN0903049
MR2* (IPU)
7
4
SMC_MANUAL_RST_L
DELAY
OMIT
OUT
5
SMC_RESET_L
OUT
3
37 46 50 64
PP3V3_S5_AVREF_SMC
C5101
0
1
C5125
0.01UF
5%
1/10W
MF-LF
603
1
1
SMC_PECI_L
IN
1
S
SMC_PECI_L_R
2
5%
1/20W
MF
0201
From SMC
NOSTUFF
1
2
SILK_PART=SMC_RST
SMC_THRMTRIP
IN
37 38
10%
10V
X5R-CERM
0201
2
2
2
GND_SMC_AVSS
PLACE_SIDE=BOTTOM
330
5%
1/20W
MF
201
2
5%
1/20W
MF
201
37 38 41 42 43
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=0V
MR1* and MR2* must both be low to cause manual reset.
R5151
1.6K
0.01UF
20%
10V
X5R-CERM
0402-1
1
R5153
G 5
C5126
10UF
10%
10V
X5R-CERM
0201
0
37
VER 3
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=3.3V
8
2
R5152
DMN5L06VK-7
37
G
1
Q5159
D
SOT563
REFOUT
THRM
S
PM_THRMTRIP_L
4
R5101
2
67 38 15
PAD
GND
2
1
CRITICAL
RESET*
3
SYM_VER_2
DFN
SMC_LSOC_RST_L
SMC_ONOFF_L
IN
2
D
D
DFN1006H4-3
9
64 36
Q5150
DMN32D2LFB4
5%
1/20W
MF
201
U5110
6
37
100K
VREF-3.3V-VDET-3.0V
2
CRITICAL
IN
R5100
VIN
V+
0.47UF
10%
6.3V
CERM-X5R
402
64 38 37 36
1
3
1
SMC_PROCHOT
1
38 37
CPU_THRMTRIP_3V3
OUT
Used on mobiles to support SMC reset via keyboard.
CRITICAL
3
NOTE: Internal pull-ups are to VIN, not V+.
R5134
Q5158
43
1
65 61 50 38 37
SMC_BC_ACOK
SMC_BC_ACOK
37
MMBT3904LP-7
37 38 50 61 65
DFN1006-3
MAKE_BASE=TRUE
Debug Power " Buttons "
R5158
2
PM_THRMTRIP_R_L
SMC_ONOFF_L
OMIT
R5116
1
1
C
2
1
CPU_PECI_R
1
PM_THRMTRIP_L
IN
2
NOSTUFF
15 38 67
CPU_PECI
5%
1/20W
MF
201
C5134
47PF
6
67
BI
From/To CPU/PCH
5%
5%
1/20W
MF
201
R5115
0
5%
1/10W
MF-LF
603 2
1
3.3K
OUT
To SMC
36 37 38 64
OMIT
0
PLACE_SIDE=BOTTOM
OUT
58 59 62 64
6 8 11 15 16
17 38 42 51 55
PP1V05_S0
1
PLACE_NEAR=Q5159.6:5MM
50 49 46 40 38 37 36 35 30
65 64 62 61 59
D
SMC12 PECI Support
VER 3
2 25V
C0G
0201
PLACE_NEAR=Q5150.2:5MM
PLACE_SIDE=TOP
5%
1/10W
MF-LF
2 603
SILK_PART=PWR_BTN
C
SILK_PART=PWR_BTN
50 49 46 40 38 37 36 35 30 17
65 64 62 61 59
SMC Crystal Circuit
74 65 64 62
36 30 26 18 17 15 13 12 11 8
61 59 56 45 44 43 42 41 40 39
SMC USB Clock require these crystal
PP3V42_G3H
PP3V3_S4
64 62 58 39 36 33 29 27 26 25
PP3V3_S0
values:5,6,8,10,12,16,18,20,24,25 MHz
38 37 33 25
SMC_PME_S4_DARK_L
R5167
100K
1
2
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
MF
201
R5110
37
SMC_XTAL
1
2.49K
SMC_XTAL_R
2
64 38 37 36
CRITICAL
1%
1/20W
MF
201
39 37
Y5110
65 64 61 37 36
3.2X2.5MM-SM
64 37
12.000MHZ-30PPM-10PF-85C
37
SMC_EXTAL
1
64 37
3
68 37 35
2
1
C5110
4
68 37 35
NCNC
1
12PF
2
38 37 33 25
C5111
SMC_PME_S4_DARK_L
IN
MAKE_BASE=TRUE
25 33 37 38
64 46 37
64 37
12PF
5%
25V
CERM
0201
SMC_PME_S4_DARK_L
5%
25V
CERM
0201
2
55 51 42 38 17 16 15 11 8 6
64 62 59 58
64 37
PP1V05_S0
64 46 37
1
B
R5112
22
69 13
IN
PM_CLK32K_SUSCLK_R
1
PLACE_NEAR=U0500.AE6:5.1mm
2
1/20W
MF
R5197
100K
SMC_CLK32K
5%
37
201
OUT
1%
1/20W
MF
2 201
37 69
37
65 61 50 38 37
37
37
SMC_VCCIO_CPU_DIV2
37
38 37
1
SMC_ONOFF_L
SMC_SENSOR_ALERT_L
SMC_LID
SMC_TX_L
SMC_RX_L
SMC_DEBUGPRT_TX_L
SMC_DEBUGPRT_RX_L
SMC_TMS
SMC_TDO
SMC_TDI
SMC_TCK
SMC_BIL_BUTTON_L
SMC_BC_ACOK
SMC_S5_PWRGD_VIN
SMS_INT_L
R5170
R5172
R5171
R5173
R5174
R5175
R5176
R5177
R5178
R5179
R5180
R5181
R5187
R5192
R5193
10K
10K
100K
10K
100K
20K
20K
10K
10K
10K
10K
10K
100K
100K
10K
MEM_EVENT_L
CPU_THRMTRIP_3V3
R5114
R5117
10K NO1 STUFF
100K 1
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
B
2
2
R5196
100K
2
1%
1/20W
MF
201
59 54 37
37 13
38 37
37 27 26 17
59 37
R5198
R5185
R5186
SMC_PM_G2_EN
SMC_ADAPTER_EN
SMC_THRMTRIP
SMC_DELAYED_PWRGD
SMC_S4_WAKESRC_EN
R5191
R5190
100K
100K
10K
100K
100K
1
2
1
2
1
2
1
1
2
2
PP3V3_WLAN
64 41 39 37 29
Module has 3.3K PU
64 37 29
NO STUFF
R5189
WIFI_EVENT_L
10K
1
2
5%
A
1/20W
SYNC_MASTER=WILL_J43
SYNC_DATE=12/17/2012
PAGE TITLE
SMC Shared Support
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
51 OF 121
SHEET
38 OF 76
1
A
8
7
6
5
41 39 37
SMC_HS_COMPUTING_ISENSE
42 39 37
SMC_PBUS_VSENSE
41 39 37
4
SMC_HS_COMPUTING_ISENSE
SMC_BMON_ISENSE
3
2
1
37 39 41
MAKE_BASE=TRUE
SMC_PBUS_VSENSE
37 39 42
MAKE_BASE=TRUE
SMC_BMON_ISENSE
37 39 41
MAKE_BASE=TRUE
41 39 37
SMC_DCIN_ISENSE
42 39 37
SMC_DCIN_ISENSE
SMC_DCIN_VSENSE
37 39 41
MAKE_BASE=TRUE
SMC_DCIN_VSENSE
37 39 42
MAKE_BASE=TRUE
43 39 37
SMC_BMON_DISCRETE_ISENSE
42 39 37
SMC_CPU_ISENSE
41 39 37
SMC_BMON_DISCRETE_ISENSE
SMC_OTHER_HI_ISENSE
37 39 43
MAKE_BASE=TRUE
SMC_CPU_ISENSE
37 39 42
MAKE_BASE=TRUE
D
SMC_OTHER_HI_ISENSE
D
37 39 41
MAKE_BASE=TRUE
43 39 37
SMC_PANEL_ISENSE
SMC_PANEL_ISENSE
37 39 43
MAKE_BASE=TRUE
41 39 37
SMC_1V2S3_ISENSE
41 39 37
SMC_LCDBKLT_ISENSE
42 39 37
SMC_P3V3S5_ISENSE
SMC_1V2S3_ISENSE
37 39 41
MAKE_BASE=TRUE
SMC_LCDBKLT_ISENSE
37 39 41
MAKE_BASE=TRUE
SMC_P3V3S5_ISENSE
37 39 42
MAKE_BASE=TRUE
41 39 37
SMC_WLAN_ISENSE
41 39 37
SMC_WLAN_ISENSE
SMC_SSD_ISENSE
37 39 41
MAKE_BASE=TRUE
SMC_SSD_ISENSE
37 39 41
MAKE_BASE=TRUE
41 39 37
SMC_P3V3S0_ISENSE
SMC_P3V3S0_ISENSE
37 39 41
MAKE_BASE=TRUE
41 39 37
SMC_CAMERA_ISENSE
SMC_CAMERA_ISENSE
37 39 41
MAKE_BASE=TRUE
PP3V3_S0SW_SD
42 39 37
SMC_P1V05S0_VSENSE
42 39 37
15 34 37
65
OUT
SMC_CPUDDR_ISENSE
SD alias on page 103
SMC_P1V05S0_VSENSE
37 39 42
MAKE_BASE=TRUE
SMC_CPUDDR_ISENSE
37 39 42
MAKE_BASE=TRUE
42 39 37
SMC_P1V05S0_ISENSE
42 39 37
SMC_CPU_VSENSE
SMC_P1V05S0_ISENSE
43 39 37
SMC_CPUVR_ADJUST_ISENSE
37 39 42
MAKE_BASE=TRUE
SMC_CPU_VSENSE
37 39 42
MAKE_BASE=TRUE
SMC_CPUVR_ADJUST_ISENSE
37 39 43
MAKE_BASE=TRUE
43 39 37
SMC_CPU_IMON_ISENSE
SMC_CPU_IMON_ISENSE
37 39 43
MAKE_BASE=TRUE
64 41 39 38 37 29
PP3V3_WLAN
PP3V3_WLAN
29 37 38 39 41 64
MAKE_BASE=TRUE
C
58 42 39 37
SMC_SENSOR_PWR_EN
SMC_SENSOR_PWR_EN
SMC_SENSOR_PWR_EN
C
37 39 42 58
37 39 42 58
MAKE_BASE=TRUE
39 37 29
SMC_WIFI_PWR_EN
SMC_WIFI_PWR_EN
29 37 39
TP_SMC_5VSW_PWR_EN
37 39
MAKE_BASE=TRUE
39 37
TP_SMC_5VSW_PWR_EN
MAKE_BASE=TRUE
R5230
37
IN
SMC_PCH_SUSWARN_L
0
1
PCH_SUSWARN_L
2
MAKE_BASE=TRUE
OUT
13
IN
13
5%
1/20W
MF
0201
Top-Block Swap
R5231
64 65 74
8 11 12 13 15 17 18 26 30 36 38
40 41 42 43 44 45 56 59 61 62
PP3V3_S0
R5296
37
OUT
0
SMC_PCH_SUSACK_L
1
PCH_SUSACK_L
2
MAKE_BASE=TRUE
5%
1/20W
MF
0201
1
1K
5%
1/20W
MF
201
37
IN
SMC_TOPBLK_SWP_L
R5283
2
1
1K
2
PCH_STRP_TOPBLK_SWP_L
OUT
15
5%
1/20W
MF
201
B
B
R5216
62 58 39 38 36 33 29 27 26 25
64
PP3V3_S4
43
IN
100
SMC_HS_COMP_ALERT_L
1
R5215
18 14
IN
PCH_SML1ALERT_L
100
1
2
5%
1/20W
MF
201
39 37 29
SMC_WIFI_PWR_EN
R5295
10K
1
2
NOSTUFF
5%
58 42 39 37
SMC_SENSOR_PWR_EN
R5294
10K
1
2
43
1/20W
MF
201
IN
1/20W
MF
R5213
SMC_BMON_COMP_ALERT_L
NOSTUFF
5%
1
65 61
IN
FINSTACKSNS_ALERT_L
100
1
A
IN
R5214
100
CPUTHMSNS_ALERT_L
1
R5211
25 26 27 29 33 36 38 39 58 62
64
44
1
IN
CPUBMONSNS_ALERT_L
37 36 29
39
IN
IN
SMC_PME_S4_WAKE_L
SMC_PME_S4_WAKE_L
44
SMC_PME_S4_WAKE_L
MAKE_BASE=TRUE
8
7
OUT
IN
TBTMLBSNS_ALERT_L
DRAWING NUMBER
R5212
1
100
2
Apple Inc.
SMC_SENSOR_ALERT_L
OUT
37 38
6
5
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
R
5%
1/20W
MF
201
29 36 37 39
SYNC_DATE=02/06/2013
SMC Project Support
2
5%
1/20W
MF
201
100K
37 36 29
39
SYNC_MASTER=J41_MLB
PAGE TITLE
100
1
R5282
5%
1/20W
MF
2 201
2
5%
1/20W
MF
201
NOSTUFF
PP3V3_S4
2
2
5%
1/20W
MF
201
44
100
5%
1/20W
MF
201
R5210
201
2
5%
1/20W
MF
201
NOSTUFF
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
52 OF 121
SHEET
39 OF 76
1
A
8
7
6
5
LYNX POINT LP S0 SMBus " 0 " Connections
4
3
1
1K
5%
1/20W
MF
201
(MASTER)
D
59 50 49 46 38 37 36 35 30 17 PP3V42_G3H
65 64 62 61
R5300 1
U0500
1
SMC " 5 " SMBus G3H Connections
SMC " 0 " SMBus S0 Connections
74 65 64 62 61
36 30 26 18 17 15 13 12 11 8 PP3V3_S0
59 56 45 44 43 42 41 40 39 38
LYNX POINT LP
2
R5301
LCD BACKLIGHT
1K
2
2
5%
1/20W
MF
201
SMBUS_PCH_CLK
40 19 16 14 SMBUS_PCH_DATA
69 56 MAKE_BASE=TRUE
SMBUS_PCH_DATA
Internal DP
R5380 1
SMC
U5000
5%
1/20W
MF
201
(MASTER)
2
2
ISL6259 - U7100
(Write: 0x12 Read: 0x13)
SMBUS_SMC_0_S0_SCL
73 60 40 37 SMBUS_SMC_0_S0_SDA
37 40 60
73
50 48 40 37 SMBUS_SMC_5_G3_SCL
73 64 MAKE_BASE=TRUE
SMBUS_SMC_5_G3_SCL
37 40 48
50 64 73
SMBUS_SMC_0_S0_SDA
73 60 40 37 SMBUS_SMC_0_S0_SCL
14 16 19
40 56 69
Battery Charger
2.0K
(See Table)
14 16 19
40 56 69
R5381
5%
1/20W
MF
201
U5000
(MASTER)
1
2.0K
J8300
U7701
(Write: 0x58 Read: 0X59)
40 19 16 14 SMBUS_PCH_CLK
69 56 MAKE_BASE=TRUE
Pullups are on eDP
connector page and
gated by EDP_PANEL_PWR
SMC
37 40 60
73
50 48 40 37 SMBUS_SMC_5_G3_SDA
73 64 MAKE_BASE=TRUE
SMBUS_SMC_5_G3_SDA
37 40 48
50 64 73
MAKE_BASE=TRUE
MAKE_BASE=TRUE
VRef DACs
D
Battery
U2200
J6950
Battery
(Write: 0x98 Read: 0x99)
(See Table)
TBT
Battery Manager - (Write: 0x16 Read: 0x17)
19 16 14 SMBUS_PCH_CLK
69 56 40
SMBUS_SMC_5_G3_SCL
37 40 48
50 64 73
SMBUS_SMC_5_G3_SDA
37 40 48
50 64 73
U2800
19 16 14 SMBUS_PCH_DATA
69 56 40
(Write: 0xFE Read: 0XFF)
SMBUS_PCH_CLK
14 16 19
40 56 69
SMBUS_PCH_DATA
14 16 19
40 56 69
Margin Control
SMC " 3 " SMBus S0
U2201
Connections
(Write: 0x30 Read: 0x31)
(* = Multiple options)
74 65 64 62 61
36 30 26 18 17 15 13 12 11 8 PP3V3_S0
59 56 45 44 43 42 41 40 39 38
19 16 14 SMBUS_PCH_CLK
69 56 40
Trackpad
19 16 14 SMBUS_PCH_DATA
69 56 40
J43
Internal DP
Samsung
Analogix T-con - (Write: 0x7B/0x87 Read: 0x7C/0x88)
N
Y
*
J41
LGD
Samsung
Y
LGD
AUO
SMC
*
Parade T-con
- (0x10-0x1F or 0x30-0x3F)
Y
N
*
N
- (Write: 0x4E Read: 0x4F)
Y
Y
Y
Y
1
2.0K
*
DVR
R5390 1
N
5%
1/20W
MF
201
U5000
J4800
R5391
(Write: 0x90 Read: 0x91)
2.0K
5%
1/20W
MF
201
2
2
SMBUS_SMC_3_SCL
36 37 40
44 64 73
SMBUS_SMC_3_SDA
(MASTER)
36 37 40
44 64 73
44 40 37 36 SMBUS_SMC_3_SCL
73 64 MAKE_BASE=TRUE
C
C
XDP Connectors
44 40 37 36 SMBUS_SMC_3_SDA
73 64 MAKE_BASE=TRUE
SMC " 2 " SMBus S3 Connections
J1800
TBT & MLBBOT, TBD Temp
(MASTER)
64 62 58 41 36 33 19 18 15 PP3V3_S3
40 19 16 14 SMBUS_PCH_CLK
69 56
EMC1414: U5810
(Write: 0x98 Read: 0x99)
40 19 16 14 SMBUS_PCH_DATA
69 56
R5370 1
SMC
1
1K
5%
1/20W
MF
201
U5000
(MASTER)
R5371
SMBUS_SMC_3_SCL
2
2
J9500
5%
1/20W
MF
201
36 37 40 44
64 73
(Write: 0x92 Read 0x93)
65 61 40 37 SMBUS_SMC_2_S3_SCL
73
MAKE_BASE=TRUE
SMBUS_SMC_2_S3_SCL
37 40 61
65 73
65 61 40 37 SMBUS_SMC_2_S3_SDA
73 MAKE_BASE=TRUE
B
36 37 40 44
64 73
SMBUS_SMC_3_SDA
LIO Finstack Temp
1K
SMBUS_SMC_2_S3_SDA
37 40 61
65 73
B
LYNX POINT LP S0 " SMLink 0 " Connections
74 65 64 62 61
36 30 26 18 17 15 13 12 11 8 PP3V3_S0
59 56 45 44 43 42 41 40 39 38
LYNX POINT LP
U0500
(MASTER)
SMC S0 " 1 " SMBus Connections
R5310 1
1
74 65 64 62 61
36 30 26 18 17 15 13 12 11 8 PP3V3_S0
59 56 45 44 43 42 41 40 39 38
R5311
8.2K
8.2K
5%
1/20W
MF
201
5%
1/20W
MF
201
2
2
R5360 1
SMC
69 14 SML_PCH_0_DATA
R5361
(MASTER)
MAKE_BASE=TRUE
CPU Temp, Inlet, DDR, BMON THR
2.0K
5%
1/20W
MF
201
U5000
MAKE_BASE=TRUE
1
2.0K
69 14 SML_PCH_0_CLK
5%
1/20W
MF
201
2
2
EMC1704-02: U5800
(Write: 0x98 Read: 0x99)
73
40 37 32 14 SMBUS_SMC_1_S0_SCL
69 64 44 43 MAKE_BASE=TRUE
SMBUS_SMC_1_S0_SCL
14 32 37 40 43 44 64
69 73
73
40 37 32 14 SMBUS_SMC_1_S0_SDA
69 64 44 43 MAKE_BASE=TRUE
SMBUS_SMC_1_S0_SDA
14 32 37 40 43 44 64
69 73
LYNX POINT LP S0 " SMLink 1 " Connections
Chipset current
PAC1921: U5620
(Write: 0x30 Read: 0x31)
SMBUS_SMC_1_S0_SCL
A
64 69 73
14 32 37
40 43 44
SMBUS_SMC_1_S0_SDA
LYNX POINT LP
64 69 73
14 32 37
40 43 44
U0500
SYNC_MASTER=J41_MLB
(Write: 0x88 Read: 0x89)
SYNC_DATE=02/06/2013
PAGE TITLE
73
40 37 32 14 SMBUS_SMC_1_S0_SCL
69 64 44 43
SMBus Connections
ALS
40 37 32 14 SMBUS_SMC_1_S0_SDA
69 64 44 43
73
DRAWING NUMBER
J4002
(Write: 0x72 Read 0x73)
Apple Inc.
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA
R
64 69 73
14 32 37
40 43 44
64 69 73
14 32 37
40 43 44
SMLink 1 is slave port to
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
access PCH
8
7
6
5
4
& lt; SCH_NUM & gt;
REVISION
3
2
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
53 OF 121
SHEET
40 OF 76
1
SIZE
D
A
8
7
6
5
4
3
2
1
IC0R : COMPUTING High Side Current Sense
IM3C :DDR 1V2 Current Sense (LPDDR + CPUDDR)
EDP Current :12A
GAIN :
74 65 64 62 61
36 30 26 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
24 mV
PP3V3_S0
EDP Current : 7.57A
100X
MAX Vdiff :
SENSE R :
INA214
74
43
ISNS_HS_COMPUTING_N
5
IN-
74 43
ISNS_HS_COMPUTING_P
4
IN+
1 3
R5450
0.002
OUT
SC70
43
5%
1/20W
MF
201
GND
2
PPBUS_G3H
1
4.53K
1%
1/20W
MF
201
C5455
37 39
74 53
Place close to SMC
5
IN-
74 53
ISNS_1V2_S3_P
IN
4
IN+
REF
1
R5465
R5461
(200V/V)
4.53K
1
SMC_1V2S3_ISENSE
2
5%
1/20W
MF
201
37 38 41 42 43
1
(For R and C)
C5465
D
DRAM_ISNS:YES
0.22UF
PLACEMENT_NOTEs:
2
37 39
OUT
PLACE_NEAR=U5000.A5:11mm
1%
1/20W
MF
201
1
20K
GND
GND_SMC_AVSS
PLACE_NEAR=U5000.A5:11mm
ISNS_1V2_IOUT
6
OUT
SC70
DRAM_ISNS:YES
10%
6.3V
CERM-X5R
0201
CRITICAL
20%
6.3V
X5R
0201
2
INA210
ISNS_1V2_S3_N
IN
CPU_HS_ISNS:YES
0.22UF
PLACEMENT_NOTEs:
2
OUT
PLACE_NEAR=U5000.E2:11mm
1
2
U5460
SMC_HS_COMPUTING_ISENSE
2
C5460
0.1UF
R5455
1
20K
2 4
DRAM_ISNS:YES
V+
R5451 1
1
REF
DRAM_ISNS:YES
PLACE_NEAR=R7450:5mm
PLACE_NEAR=U5000.E2:11mm
ISNS_HS_COMPUTING_IOUT
(100V/V)
APN: 107S0137
56 50
41 27
49 42
64 62
6
R7450 0.002R
CPU_HS_ISNS:YES
10%
6.3V
CERM-X5R
0201
CRITICAL
1%
1W
MF
0612
D
2
U5450
CRITICAL
C5450
0.1UF
V+
PPBUS_S5_HS_COMPUTING_ISNS
200X
2
3
CPU_HS_ISNS:YES
64 62
52 51
55 53
PP3V3_S4SW_SNS
15.14 mV 62 58 43 42 41
GAIN :
CPU_HS_ISNS:YES
1
3
MAX Vdiff :
2
Place close to SMC
20%
6.3V
X5R
0201
GND_SMC_AVSS
37 38 41 42 43
(For R and C)
IO0R : OTHER High Side Current Sense
EDP Current :10.75A
53.75 mV
GAIN :
50X
62 58 43 42 41
IAPC :AirPort Current Sense
PP3V3_S4SW_SNS
OTHER_HS_ISNS:YES
PLACE_NEAR=R5430:5mm
1
3
OTHER_HS_ISNS:YES
OUT PPBUS_S5_HS_OTHER_ISNS
62 54
64
2
U5430
OMIT
1 3
R5430
INA213
ISNS_HS_OTHER_N
74
5
IN-
0.003
C5430
MAX Vdiff :
0.1UF
V+
OUT
SC70
ISNS_HS_OTHER_P
74
62 58 43 42 41
4
IN+
REF
1
5%
1/20W
MF
201
PPBUS_G3H
37 39
OUT
AIRPORT_ISNS:YES
PLACE_NEAR=U5000.A4:11mm
64 39 38 37 29
1
20%
6.3V
X5R
0201
2
PLACEMENT_NOTEs:
R5470
OTHER_HS_ISNS:YES
2
74
ISNS_AIRPORT_N
5
IN-
74
1%
1W
MTL
0612
ISNS_AIRPORT_P
4
IN+
(For R and C)
REF
1
R5471
(100V/V)
1 3
2
PP3V3_WLAN_R
Place close to SMC
2
3V3S0_ISNS:YES
ISNS_P3V3_S0_N
74
5
IN-
OUT
SC70
4.53K
ISNS_P3V3_S0_IOUT
6
1
CRITICAL
0.003
ISNS_P3V3_S0_P
74
4
IN+
REF
1
R5441
(1000V/V)
1 3
OMIT
1
2
MAX Vdiff :
SMC_P3V3S0_ISENSE
2
15 mV
GAIN :
200X
37 39
OUT
3V3S0_ISNS:YES
1%
1/20W
MF
201
1
C5445
PLACE_NEAR=U5000.B1:11mm
62 58 43 42 41
0.22UF
20K
5%
1/20W
MF
201
GND
PP3V3_S0_FET_R
EDP Current : 3.00A
R5445
INA212
2 4
ISDC : SSD Current Sense
PLACE_NEAR=U5000.B1:11mm
10%
6.3V
CERM-X5R
0201
2
PLACEMENT_NOTEs:
PP3V3_S4SW_SNS
20%
6.3V
X5R
0201
SSD_ISNS:YES
PLACE_NEAR=R5480:5mm
SSD_ISNS:YES
2
GND_SMC_AVSS
Place close to SMC
64 62 30
37 38 41 42 43
PP3V3_S0SW_SSD
R5480
IS2C : 3.3V Camera Current Sense
1 3 74
INA210
ISNS_SSD_N
5
IN-
0.003
1%
1W
MF
0612
EDP Current : 0.82A
16.36 mV
74
ISNS_SSD_P
4
IN+
REF
58
1
R5481
(200V/V)
2
4.53K
1
5%
1/20W
MF
201
GND
2
PP3V3_S0SW_SSD_FET_R
SMC_SSD_ISENSE
2
1
2
2
Place close to SMC
1
GND_SMC_AVSS
0612-SHORT
MF
1w
0.5%
2
U5420
4
74
ISNS_CAMERA_N
IN-
4
IN+
74
1 3
ISNS_CAMERA_P
REF
6
1
(200V/V)
R5424
SMC_CAMERA_ISENSE
2
5%
1/20W
MF
201
1
2
37 39
2
Place close to SMC
500X
62 58 43 42 41
37 38 41 42 43
56 41
56 41
2
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=8.6V
MAKE_BASE=TRUE
0612-SHORT
MF
1w
0.5%
R5490
0
OMIT
2
56 41
56 41
C5490
0.1UF
2
INA211
4
74
ISNS_LCDBKLT_N
5
74
ISNS_LCDBKLT_P
4
IN-
OUT
SC70
6
IN+
REF
1
(500V/V)
1 3
45.3K
1
2
SMC_BMON_ISENSE
OUT
37 39
50
IN
CHGR_AMON
1%
MF
1
2
PART NUMBER
SMC_DCIN_ISENSE
OUT
1%
1/20W
MF
201
1
PLACEMENT_NOTEs:
2
1
117S0008
1/20W
PLACE_NEAR=U5000.A4:11MM
C5422
MF
201
PLACE_NEAR=U5000.B6:11mm
20%
6.3V
X5R
0201
GND_SMC_AVSS
37 38 41 42 43
(For R and C)
1
ISL6259 Gain: 20x
0201
REFERENCE DES
C5455
CRITICAL
BOM OPTION
CPU_HS_ISNS:NO
1
RES,MF,1/20W,100K OHM,5,0201,SMD
C5465
1
RES,MF,1/20W,100K OHM,5,0201,SMD
C5475
37 38 41 42 43
AIRPORT_ISNS:NO
DRAWING NUMBER
Apple Inc.
0201
GND_SMC_AVSS
1
RES,MF,1/20W,100K OHM,5,0201,SMD
C5485
SSD_ISNS:NO
1
RES,MF,1/20W,100K OHM,5,0201,SMD
C5495
LCDBKLT_ISNS:NO
1
RES,MF,1/20W,100K OHM,5,0201,SMD
C5433
OTHER_HS_ISNS:NO
117S0008
1
RES,MF,1/20W,100K OHM,5,0201,SMD
C5425
CAM_ISNS:NO
117S0008
37 38 41 42 43
Scale: 2.5A / V
117S0008
117S0008
Max VOut: 1.4V at 8.25A
SYNC_DATE=03/28/2013
High Side Current Sensing
DRAM_ISNS:NO
117S0008
10V
X5R-CERM
117S0008
GND_SMC_AVSS
SYNC_MASTER=J41_MLB
PAGE TITLE
10%
2
X7R-CERM
DESCRIPTION
RES,MF,1/20W,100K OHM,5,0201,SMD
117S0008
2.2NF
Sense R is R7120, 20mOhm
10V
1
C5431
201
10%
2
QTY
PLACE_NEAR=U5000.B3:11MM
3300PF
Scale: 2.78A / V
1
RES,MF,1/20W,100K OHM,5,0201,SMD
C5445
3V3S0_ISNS:NO
R
NOTICE OF PROPRIETARY PROPERTY:
107S0248
8
QTY
1
DESCRIPTION
RES,SENSE,0.003OHM,1W,4-TERM,1%,0612,TFT
7
REFERENCE DES
R5480
CRITICAL
BOM OPTION
CRITICAL
6
5
4
3
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
EDP Current: 3.5A
PART NUMBER
37 39
C5495
0.22UF
2
Place close to SMC
OUT
LCDBKLT_ISNS:YES
1
20K
37 39
1%
1/20W
EDP Current: 310A
R5491
5%
1/20W
MF
201
GND
PPVIN_S0SW_LCDBKLT_FET
PPVIN_S0SW_LCDBKLT_FET
SMC_LCDBKLT_ISENSE
2
CRITICAL
R5431
300K
Max VOut: 3.3V at 9.167A
4.53K
1
Replacing caps with 100K PD on ISENSE SMC inputs
PLACE_NEAR=U5000.B3:11MM
R5422
ISL6259 Gain: 36x
LCDBKLT_ISNS:YES
R5495
ISNS_LCDBKLT_IOUT
DC-IN (AMON) Current Sense
PLACE_NEAR=U5000.A4:11MM
CHGR_BMON
PLACE_NEAR=U5000.B6:11mm
10%
6.3V
CERM-X5R
0201
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=8.6V
MAKE_BASE=TRUE
CHARGER BMON High Side Current Sense
IN
2
0.020
5%
1/16W
MF-LF
402
1
V+
U5490
NOSTUFF
50
LCDBKLT_ISNS:YES
PPVIN_S0SW_LCDBKLT
PPVIN_S0SW_LCDBKLT
R5423
1
LCDBKLT_ISNS:YES
PLACE_NEAR=R5490:5mm
GND_SMC_AVSS
5%
1/16W
MF-LF
402
PP3V3_S3
PP3V3_S4SW_SNS
PLACE_NEAR=U5000.B2:11mm
20%
6.3V
X5R
0201
(For R and C)
0
0.06 mV
C5425
0.22UF
PLACEMENT_NOTEs:
2
MAX Vdiff :
GAIN :
OUT
CAM_ISNS:YES
1%
1/20W
MF
201
R5421
1
1
1
20K
VOLTAGE=3.3V
PP3V3_S0
EDP Current : 0.67A
4.53K
ISNS_CAMERA_IOUT
GND
PP3V3_S3RS0_CAMERA_R
IBLC : LCD Backlight Driver Input Current Sense
CAM_ISNS:YES
CRITICAL
0.020
OMIT
OUT
SC70
PLACE_NEAR=U5000.B2:11mm
R5425
INA210
5
10%
6.3V
CERM-X5R
0201
3
2
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
B
0.1UF
V+
PP3V3_S3RS0_CAMERA
A
37 38 41 42 43
C5420
2
CAM_ISNS:YES
3
PLACE_NEAR=R8061:5mm
R5420
64
40 36
18 15
33 19
62 58
PLACE_NEAR=U5000.C2:11mm
20%
6.3V
X5R
0201
CAM_ISNS:YES
PP3V3_S3RS0_CAMERA
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
37 39
C5485
0.22UF
PLACEMENT_NOTEs:
(For R and C)
PP3V3_S3RS0_CAMERA
OUT
SSD_ISNS:YES
1%
1/20W
MF
201
1
20K
4
PP3V3_S4SW_SNS
62 58 43 42 41
SSD_ISNS:YES
R5485
ISNS_P5VSSD_IOUT
6
CRITICAL
OMIT_TABLE
200X
OUT
SC70
PLACE_NEAR=U5000.C2:11mm
10%
6.3V
CERM-X5R
0201
2
U5480
CRITICAL
GAIN :
0.1UF
V+
(For R and C)
MAX Vdiff :
C5480
1
3
3
C5440
0.1UF
U5440
R5440
58
1
V+
PP3V3_S0
0612-SHORT
CYN
1w
1%
41
15
31
37 38 41 42 43
3V3S0_ISNS:YES
3V3S0_ISNS:YES
41
15
31
C
GND_SMC_AVSS
PP3V3_S4SW_SNS
62 58 43 42 41
PLACE_NEAR=R5440:5mm
B
PLACE_NEAR=U5000.C1:11mm
20%
6.3V
X5R
0201
2
(For R and C)
1000X
74
45 44 43 42 41 40
17 15 13 12 11 8
39 38 36 30 26 18
65 64 62 61 59 56
41
15
31
37 39
C5475
0.22UF
PLACEMENT_NOTEs:
2
OUT
AIRPORT_ISNS:YES
1
3.06 mV
GAIN :
SMC_WLAN_ISENSE
2
1%
1/20W
MF
201
1
20K
5%
1/20W
MF
201
GND
EDP Current :1.02A
MAX Vdiff :
4.53K
1
CRITICAL
APN: 104S0024
29
AIRPORT_ISNS:YES
R5475
ISNS_P5VWLAN_IOUT
6
OUT
SC70
PLACE_NEAR=U5000.C1:11mm
10%
6.3V
CERM-X5R
0201
2
INA214
4
0.025
GND_SMC_AVSS
IR0C : 3.3V S0 FET Current Sense
C5470
0.1UF
U5470
CRITICAL
Place close to SMC
C
1
V+
PP3V3_WLAN
C5433
0.22UF
2
AIRPORT_ISNS:YES
PLACE_NEAR=R5470:5mm
SMC_OTHER_HI_ISENSE
2
1%
1/20W
MF
201
20K
2
IN
4.53K
R5432 1
1
4
GND
56 50
41 27
49 42
64 62
PP3V3_S4SW_SNS
R5433
(50V/V)
2
100X
PLACE_NEAR=U5000.A4:11mm
CRITICAL
1%
1w
CYN
0612-SHORT
25 mV
GAIN :
OTHER_HS_ISNS:YES
10%
6.3V
CERM-X5R
0201
HS_OTHER_IOUT
6
EDP Current : 1.00A
3
MAX Vdiff :
PAGE
54 OF 121
SHEET
41 OF 76
1
A
8
7
6
5
4
3
2
1
VP0R: PBUS Voltage Sense Enable & Filter
ICS0 : CPU VCore Load Side Current Sense
Q5500
NTUD3169CZ
SOT-963
N-CHANNEL
PBUSVSENS_EN_L
6
74 65 64 62
36 30 26 18 17 15 13 12 11 8
61 59 56 45 44 43 41 40 39 38
D
R5502
58
37
39
SMC_SENSOR_PWR_EN
IN
G
2
1
1%
1/20W
MF
201
S
1
D
PLACE_NEAR=U5540.5:3MM
CPUVR_ISNS:YES
1
Max VOut: 3.3V at 19.77V Input
2
PBUS_S0_VSENSE
3
CPUVR_ISNS:YES
PLACE_NEAR=R7310.3:5MM
2
R5540
R5503
62 56 50 49 41 27
64
1
74 52
1%
1/20W
MF
201
S
PPBUS_G3H
4
2
OUT
5.49K
PBUSVSENS_EN_L_DIV
2
2
1%
1/16W
MF-LF
402
Sense R is R7310, R7320
Sense R is 0.75mOhm each, combined 0.375mOhm
CPUVR_ISNS:YES
R5541
C5504
74 52
IN
CPUVR_ISNS2_P
4.42K
1
U5540
74
CPUVR_ISUM_R_P
1
CPUVR_ISNS:YES
3
PLACE_NEAR=R7310.3:5MM
R5542
VD0R: DC-In Voltage Sense Enable & Filter
74 52
4.42K
CPUVR_ISNS1_N
IN
1
2
74 43
1.43K
CPUVR_ISNS1_N_R
1
2
1%
1/16W
MF-LF
402
Q5510
74
SOT-963
D
13
59
R5512
PM_SLP_SUS_L
IN
G
2
1%
1/20W
MF
201
S
C
1
74 52
IN
CPUVR_ISNS2_N
1
1
Max VOut: 3.3V at 19.77V Input
2
4.42K
37 39
OUT
CPUVR_ISNS:YES
PLACE_NEAR=U5000.B4:11MM
1
C5541
20%
6.3V
X5R
0201
GND_SMC_AVSS
37 38 41 42 43
R5547
1M
1
2
1
R5546
NO_XNET_CONNECTION=TRUE
1M
2
2
2
1%
1/16W
MF-LF
402
CPUVR_ISNS:YES
DCIN_S5_VSENSE
3
SMC_CPU_ISENSE
2
1%
1/20W
MF
201
CPUVR_ISNS:YES
1%
1/16W
MF-LF
402
100K
4.53K
0.22UF
R5543
Enables DC-In VSense
1
2
PLACE_NEAR=R7320.3:5MM
divider when SUS present.
CPUVR_ISUM_IOUT
CPUVR_ISUM_R_N
CPUVR_ISNS:YES
DCINVSENS_EN_L
6
4
1%
1/16W
MF-LF
402
NTUD3169CZ
N-CHANNEL
R5548
SC70-5
V-
-
R5545
CPUVR_ISNS:YES
PLACE_NEAR=U5000.B4:11MM
OPA333DCKG4
5
+
V+
CPUVR_ISNS:YES
37 38 41 42 43
TDP :28.05A
CRITICAL
2
1%
1/16W
MF-LF
402
20%
6.3V
X5R
0201
GND_SMC_AVSS
EDP: 32A
PLACE_NEAR=R7320.3:5MM
0.22UF
1%
1/20W
MF
201 2
2
Gain:274.72x
1.43K
1
37 39
PLACE_NEAR=U5000.E1:11MM
1
D
10%
6.3V
CERM-X5R
0201
CPUVR_ISNS:YES
SMC_PBUS_VSENSE
R5504 1
CPUVR_ISNS1_P_R
1%
1/16W
MF-LF
402
PLACE_NEAR=U5000.A3:11MM
100K
74 43
2
PLACE_NEAR=U5000.E1:11MM
RTHEVENIN = 4573 Ohms
P-CHANNEL
R5501 1
1%
1/20W
MF
201
IN
1
27.4K
G
R5544
4.42K
CPUVR_ISNS1_P
C5540
0.1UF
CPUVR_ISNS:YES
D
5
PP3V3_S0
100K
C
1%
1/16W
MF-LF
402
D
R5513
1%
1/20W
MF
201
S
4
PLACE_NEAR=U5000.B3:11MM
2
RTHEVENIN = 4573 Ohms
P-CHANNEL
PPDCIN_G3H_ISOL
SMC_DCIN_VSENSE
R5514
100K
1%
1/20W
MF
201
OUT
IM0C : CPU DDR Current Sense
37 39
PLACE_NEAR=U5000.F1:11MM
1
PLACE_NEAR=U5000.B3:11MM
1
1
5.49K
1%
1/20W
MF
201
2
PDCINVSENS_EN_L_DIV
EDP Current : 3.00A
C5514
MAX Vdiff :
2
20%
6.3V
X5R
0201
12.60 mV
GAIN :
0.22UF
2
200X
62 58 43 42 41
42 10 8
GND_SMC_AVSS
37 38 41 42 43
42 10 8
64
10 8
62 52
PPVCC_S0_CPU
1
CPUDDR_ISNS:YES
CPUVSENSE_IN
2
4.53K
1
PPVMEMIO_S0_CPU
2
PLACE_NEAR=R7310.2:5 MM
OUT
0612-SHORT
CYN
1w
1%
37 39
B
5
IN-
74
ISNS_CPUDDR_P
4
IN+
SC70
70 62 53 23 22 21 20 19 17
OUT
CPUDDR_ISNS:YES
R5575
REF
ISNS_CPUDDR_IOUT
6
R5571
1
(200V/V)
1 3
20%
6.3V
X5R
0201
2
ISNS_CPUDDR_N
OMIT
0.22UF
PLACE_NEAR=U5000.B7:11MM
74
R5570
C5520
PLACE_NEAR=U5000.H1:11mm
10%
6.3V
CERM-X5R
0201
INA210
4
0.003
PLACE_NEAR=U5000.B7:11MM
1
2
C5570
0.1UF
U5570
SMC_CPU_VSENSE
2
1%
1/20W
MF
201
1
V+
R5520
SM
CPUDDR_ISNS:YES
PLACE_NEAR=R5570:5mm
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.1 MM
VOLTAGE=1.2V
MAKE_BASE=TRUE
CPU Vcore Voltage Sense / Filter
XW5520
PP3V3_S4SW_SNS
PPVMEMIO_S0_CPU
3
R5511
PP1V2_S3
4.53K
1
SMC_CPUDDR_ISENSE
2
1
37 39
C5575
0.22UF
2
PLACE_NEAR=U5000.H1:11mm
20%
6.3V
X5R
0201
2
GND_SMC_AVSS
GND_SMC_AVSS
OUT
CPUDDR_ISNS:YES
1%
1/20W
MF
201
1
20K
5%
1/20W
MF
201
GND
2
62
49
50
64
1
27.4K
G
5
37 38 41 42 43
B
PLACEMENT_NOTEs:
37 38 41 42 43
Place close to SMC
1.05V Voltage Sense / Filter
R5530
1
P1V05VSENSE_IN
2
1
4.53K
EDP Current : 3.00A
SMC_P1V05S0_VSENSE
2
1%
1/20W
MF
201
PLACE_NEAR=R7640.2:5 MM
OUT
37 39
MAX Vdiff :
30.00 mV
GAIN :
100X
PLACE_NEAR=U5000.G1:11MM
1
C5530
62 58 43 42 41
0.22UF
2
PLACE_NEAR=U5000.G1:11MM
37 38 41 42 43
34 29 28 18 17 16 15 13 11 8
74 64 62 60 59 58 57
P3V3S5_ISNS:YES
PP3V3_S5
R5590
2
INA214
1 3 74
ISNS_P3V3S5_N
5
IN-
74
ISNS_P3V3S5_P
4
IN+
SC70
C5590
0.1UF
U5590
OMIT
EDP Current : 1A
OUT
6
PLACE_NEAR=U5000.A6:11mm
10%
6.3V
CERM-X5R
0201
P3V3S5_ISNS:YES
R5595
ISNS_P3V3S5_IOUT
0.003
1%
1w
CYN
0612-SHORT
5.65 mV
62 58 43 42 41
PP3V3_S4SW_SNS
P1V05_ISNS:YES
3
P1V05_ISNS:YES
1
C5560
2
U5560
10%
6.3V
CERM-X5R
0201
P1V05_ISNS:YES
IN
ISNS_1V05_S0_N
5
IN-
SC70
OUT
6
P1V05S0_IOUT
CRITICAL
74 55
IN
ISNS_1V05_S0_P
PLACE_NEAR=R7640.3:5MM
4
IN+
REF
(500V/V)
2
GND
1
R5562 1
4.53K
1
SMC_P1V05S0_ISENSE
2
1%
1/20W
MF
201
1
(100V/V)
2
5%
1/20W
MF
201
GND
OUT
37 39
P3V3S5_ISNS:YES
1
C5595
PLACE_NEAR=U5000.A6:11mm
0.22UF
2
20%
6.3V
X5R
0201
2
GND_SMC_AVSS
37 38 41 42 43
PLACEMENT_NOTEs:
Place close to SMC
37 39
(For R and C)
C5561
0.22UF
2
SMC_P3V3S5_ISENSE
2
1%
1/20W
MF
201
1
PP3V3_S5_REG_R
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
OUT
R5591
4.53K
1
20K
4
PP3V3_S5_REG_R
P1V05_ISNS:YES
1
20K
5%
1/20W
MF
201
54 42
R5561
INA211
74 55
REF
PLACE_NEAR=U5000.H2:11MM
0.1UF
V+
PLACE_NEAR=R7640.4:5MM
54 42
CRITICAL
2
500X
PLACE_NEAR=R7640:5mm
A
1
V+
IC1C: 1.05V S0 CURRENT SENSE / FILTER
GAIN :
P3V3S5_ISNS:YES
PLACE_NEAR=R5590:5mm
GND_SMC_AVSS
MAX Vdiff :
PP3V3_S4SW_SNS
20%
6.3V
X5R
0201
3
SM
PP1V05_S0
(For R and C)
IR5C :3.3 S5 REG Current Sense
XW5530
64
55 51 38
11 8 6
17 16 15
62 59 58
20%
6.3V
X5R
0201
SYNC_MASTER=J41_MLB
PLACE_NEAR=U5000.H2:11MM
Voltage & Load Side Current Sensing
2
GND_SMC_AVSS
SYNC_DATE=03/28/2013
PAGE TITLE
Replacing caps with 100K PD on ISENSE SMC inputs
37 38 41 42 43
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
RES,MF,1/20W,100K OHM,5,0201,SMD
C5541
DRAWING NUMBER
CRITICAL
Apple Inc.
BOM OPTION
R
117S0008
1
CPUVR_ISNS:NO
117S0008
7
6
5
RES,MF,1/20W,100K OHM,5,0201,SMD
C5561
P1V05_ISNS:NO
1
RES,MF,1/20W,100K OHM,5,0201,SMD
C5595
P3V3S5_ISNS:NO
117S0008
8
1
117S0008
1
RES,MF,1/20W,100K OHM,5,0201,SMD
C5575
CPUDDR_ISNS:NO
4
3
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
55 OF 121
SHEET
42 OF 76
1
A
8
7
6
5
4
3
2
1
Sense Pins gain stage for U5800 (EMC1704)
ICS3 : Adjustable Gain CPU VR Current
R5620
100
PP3V3_S4SW_SNS
58 43 42 41
62
1
1
74 65 64 62 61
36 30 26 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
VOLTAGE=3.3V
C5620
1.0UF
0
0
1
PP3V3_S0
2
BYPASS=U5620.1:5:3MM
10%
6.3V
CERM-X5R
0201
2
PU: SMBus mode
1
4.3K
5%
1/20W
MF
201
74
41
43
0
1
PAC1921-1-AIA
PLACE_NEAR=U5000.A7:5MM
74 42
74 42
IN
ADDR_SEL/GAIN_SEL
2
CPUVR_ISNS1_P_R
IN
SENSE+
SENSE-
3
CPUVR_ISNS1_N_R
OUT
READ*/INT
SM_CLK/INT_SEL
SM_DATA/OUT_SEL
COMM_SEL
PLACE_NEAR=U5540.1:5MM
PLACE_NEAR=R7150:5MM
R5625
DFN
4
8
0
1
SMC_CPUVR_ADJUST_ISENSE_R
SMC_CPU_DBGPWR_RD_L
IN
1
37
10
SMBUS_SMC_1_S0_SCL
BI
14 32 37
40 44 64 69 73
SMBUS_SMC_1_S0_SDA
BI
14 32 37 40 44 64 69 73
2
7
27K
37 39
OUT
U5660
C5625
CKPLUS_WAIVE=NdifPr_badTerm
0.22UF
9
20%
6.3V
X5R
0201
74 43 41
5
IN-
4
ISNS_HS_COMPUTING_P
IN
IN+
74 43 41
ISNS_HS_COMPUTING_N
IN
6
OUT
SC70
0
REF
1
R5663
(500V/V)
GND_SMC_AVSS
5
11
2
37 38 41 42 43
2
5%
1/20W
MF
0201
1
ISNS_HS_GAIN_OUT_R
NO STUFF
1
0
2
44 74
2
5%
1/20W
MF
0201
ISNS_HS_GAIN_N
D
NO STUFF
R5669
74
41
43
0
ISNS_HS_COMPUTING_N
IN
1
2
5%
1/20W
MF
0201
2
C5665
0.22UF
20K
5%
1/20W
MF
201
GND
EPAD
1
ISNS_HS_GAIN_OUT
CRITICAL
CKPLUS_WAIVE=NdifPr_badTerm
NO STUFF
1%
1/20W
MF
201
R5665
INA211
PLACE_NEAR=U5000.A7:5MM
GND
OUT
R5667
1
R5661 1
V+
2 SMC_CPUVR_ADJUST_ISENSE
5%
1/20W
MF
0201
44 74
5%
1/20W
MF
0201
U5620
6
OUT
NO STUFF
R5668
2
ISNS_HS_GAIN_N_R
2
ISNS_HS_GAIN_P
ISNS_HS_COMPUTING_P
IN
VDD
3
R5621
1%
1/20W
MF
201
0.1UF
2
5%
1/20W
MF
0201
1
1K
C5660
CPUVRSNS_ADDR_SEL
D
R5662
PLACE_NEAR=U5660.3:5MM
1
R5821: ADDR - 0x56/0x57 (r/w)
1
1
ISNS_HS_GAIN_P_R
5%
1/20W
MF
0201
20%
6.3V
X5R
0201-1
2
R5666
R5660
PP3V3_SNS_CPUVR_ADJUST_ISNS
2
1%
1/16W
MF-LF
402
2
20%
6.3V
X5R
0201
2
GAIN: 500X
ILDC :LCD Panel Current Sense / Filter
62 58 43 42 41
PP3V3_S0SW_LCD
PANEL_ISNS:YES
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
60 43
PLACE_NEAR=R5470:5mm
PANEL_ISNS:YES
1
3
60 43
PP3V3_S0SW_LCD
C
OMIT
R5670
1 3
74
2
INA210
ISNS_PANEL_N
5
IN-
0.020
0.5%
1w
MF
0612-SHORT
C5670
0.1UF
V+
U5670
OUT
SC70
60 43
PLACE_NEAR=U5000.C1:11mm
10%
6.3V
CERM-X5R
0201
PANEL_ISNS:YES
R5675
4.53K
ISNS_PANEL_IOUT
6
1
CRITICAL
74
ISNS_PANEL_P
4
IN+
REF
1
R5671
(200V/V)
2
5%
1/20W
MF
201
2
PP3V3_S0SW_LCD_R
PP3V3_S0SW_LCD_R
SMC_PANEL_ISENSE
2
1%
1/20W
MF
201
1
Gain: 200x
2
Scale:
0.25A / V
C
37 39
C5675
VR IMON Current Sense Filter
0.22UF
2
MAX VOUT: 3V AT 0.825A
OUT
PANEL_ISNS:YES
1
20K
4
GND
60 43
With 100mA battery current, Will have 10.2mV difference
going into sense pins of U5800.
This will set the minumum current threshold at 0.100mA
In battery discharge scenario negative voltage will be
present on IN+/- pins with INA output voltage decreasing
from 3.3V with increasing discharge current.
PP3V3_S4SW_SNS
20%
6.3V
X5R
0201
PLACE_NEAR=U5000.C1:11mm
PLACE_NEAR=U5000.B8:5MM
R5641
GND_SMC_AVSS
37 38 41 42 43
EDP Current: 0.750 A
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
51
Max Vdiff:
0
CPUVR_IMON
IN
PLACEMENT_NOTEs:
1
SMC_CPU_IMON_ISENSE
2
5%
1/20W
MF
0201
15 mV
Place close to SMC
37 39
OUT
NO STUFF
PLACE_NEAR=U5000.B8:5MM
1
C5641
2.2NF
(For R and C)
10%
10V
2
X5R-CERM
0201
GND_SMC_AVSS
Discrete High side Current threshold
NO STUFF
62
45
41
36
17
11
13
26
39
43
59
65
74
61
44
40
30
15
8
12
18
38
42
56
64
Vref = 0.406mV
Vth = 0.442 = 1A from Battery
C5611
Vtl = 0.290mv = 0.687A from battery
0.22UF
PP3V3_S0
1
2
BMON : Discrete BMON Current Sense / Filter
BYPASS=U5601:3MM
1
C5613
2
10%
6.3V
CERM-X5R
0201
R5614
R5616
294K
B
2
1%
1/16W
MF-LF
402
1
10.2K
1
3
2
5
MCP6541T
SC70-5
1
255K
10%
6.3V
CERM-X5R
0201
1
SMC_HS_COMP_ALERT_L
U5612
D
OUT
39
R5604
R5606
100K
3
DFN1006H4-3
2
1%
1/16W
MF-LF
402
1
10.2K
HS_IOUT_R
BMON_COMP_VREF
NOSTUFF
1
C5610
1
2
R5610
0
S
B
2
DMN32D2LFB4
2
DFN1006H4-3
SYM_VER_2
1
G
BMON_COMP_OUT
1
4
100K
2
1%
1/16W
MF-LF
402
BMON_IOUT_R
NOSTUFF
1
C5600
0.1UF
10%
25V
X5R
402
NOSTUFF
HS_IOUT_D
1
1
R5607
0
NOSTUFF
D5617
MCP6541T
SC70-5
39
R5605
5%
1/20W
MF
0201
2
U5602
OUT
3
2
Gain: 50x
Scale: 2A / V
Max VOut: 3.3V at 6.6A
10%
25V
X5R
402
200K
D
2
0
5%
1/20W
MF
0201
S
1
0.1UF
NOSTUFF
R5617
G
2
5
1
1%
1/16W
MF-LF
402
U5601
3
1%
1/16W
MF-LF
402
SYM_VER_2
SMC_BMON_COMP_ALERT_L
R5609
BMON_COMP_FB
4
1
2
20%
6.3V
X5R
0201
0.1UF
2
DMN32D2LFB4
1%
1/16W
MF-LF
402
2
C5603
HS_COMP_OUT
R5615
1
1
BYPASS=U5601:3MM
1
49.9K
2
PP3V3_S0
2
2
1
74 65 64 62 61
36 30 26 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
0.22UF
1%
1/16W
MF-LF
402
U5611
1%
1/16W
MF-LF
402
HS_COMP_VREF
NO STUFF
C5601
R5619
HS_COMP_FB
1
Hysteresis TBD based on RC value changes
20%
6.3V
X5R
0201
0.1UF
A
0201
2
BYPASS=U5600:3MM
RB521ES-30
C5606
K
1
10%
6.3V
CERM-X5R
0201
2
R5600
0
5%
1/20W
MF
0201
2
5%
1/20W
MF
0201
BMON_IOUT_D
0.1UF
NOSTUFF
2
D5607
A
0201
RB521ES-30
K
ISNS_HS_COMPUTING_IOUT
IN
SYNC_MASTER=J41_MLB
CHGR_CSO_R_P/N are swapped on purpose
to measure power into the system
3
41
Debug Sensors 1
U5600
CKPLUS_WAIVE=NdifPr_badTerm
73 50
IN
IN
PLACE_NEAR=U5000.A3:5MM
INA213
CHGR_CSO_R_P
CHGR_CSO_R_N
5
IN-
SC70
OUT
6
4
IN+
1
REF
(50V/V)
Replacing caps with 100K PD on ISENSE SMC inputs
117S0008
8
QTY
1
DESCRIPTION
REFERENCE DES
C5675
RES,MF,1/20W,100K OHM,5,0201,SMD
7
CRITICAL
5%
1/20W
MF
201
GND
BOM OPTION
2
4.53K
1%
1/20W
MF
201
Apple Inc.
SMC_BMON_DISCRETE_ISENSE
2
PLACE_NEAR=U5000.A3:5MM
1
C5602
0.22UF
2
20%
6.3V
X5R
0201
GND_SMC_AVSS
PANEL_ISNS:NO
6
R5601 1
20K
CKPLUS_WAIVE=NdifPr_badTerm
PART NUMBER
1
5
4
DRAWING NUMBER
R5608
BMON_IOUT
CRITICAL
73 50
SYNC_DATE=03/28/2013
PAGE TITLE
V+
2
A
37 38 41 42 43
3
43
41
37
38
42
OUT
37 39
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
56 OF 121
SHEET
43 OF 76
1
A
8
7
6
5
4
3
2
1
CPU Proximity, Inlet ,DDR and BMON THR Sensor
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mm
R5800
47
74 65 64 62 61
36 30 26 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
1
PP3V3_S0
2
PP3V3_S0_CPUTHMSNS_R
1
5%
1/20W
MF
201
C5800
0.1UF
2
10%
6.3V
CERM-X5R
0201
NOSTUFF
1
3
PLACE_NEAR=Q5830:3MM
1
Placement note:
Q5830
Place Q5810 next to DDR/5V/3.3V supply on TOP side
1
C5801
NO_XNET_CONNECTION=TRUE
PLACE_NEAR=U5800.2:5mm
C5830
DFN1006H4-3
2
2
10%
10V
5%
25V
NP0-C0G-CERM
0201
VDD
2200PF
47PF
BC846BLP
PLACE_NEAR=U5800.3:5mm
X7R-CERM
U5800
QFN
74 CPUTHMSNS_D2_P
1
Q5810
Placement note:
BC846BLP
Place Q5830 between near rear vent on bottom side
C5811
C5860
47PF
1
2
DFN1006H4-3
2
1
47PF
5%
25V
NP0-C0G-CERM
0201
5%
25V
NP0-C0G-CERM
0201
Q5860
C5802
OUT
39
ALERT*
10
CPUTHMSNS_ALERT_L
OUT
39
DP2/DN3
SMDATA
11
DN2/DP3
SMCLK
12
DN1
10%
10V
X7R-CERM
0201
3
PLACE_NEAR=Q5860:3MM
74 43
OUT
5
16
2
PLACE_NEAR=U5800.5:5mm
74 CPUTHMSNS_D2_N
15
ISNS_HS_GAIN_P
74 43
OUT
13
BI
14 32 37 40 43 64 69 73
SMBUS_SMC_1_S0_SCL
BI
14 32 37 40 43 64 69 73
7
1
GND
THRM_PAD
8
1
CPUTHMSNS_TH_SEL
10K
5%
1/20W
MF
201
GPIO
NOSTUFF
R5804
NC
5%
1/20W
MF
201
R5805
0
5%
1/20W
MF
0201
Placement note:
Place U5800 under CPU
1
Write Address: 0x98
Read Address: 0x99
10K
2
CPUTHMSNS_ADDR_SEL
2
CPUTHMSNS_DUR_SEL
R5803
6
DUR_SEL
TH_SEL
ISNS_HS_GAIN_N
NOSTUFF
ADDR_SEL
SENSE+
SENSE-
14
Detect DDR/5V/3.3V Proximity Temperature
SMBUS_SMC_1_S0_SDA
PLACE_NEAR=U5800.4:5mm
1
2200PF
BC846BLP
2
2
THERM*
DP1
4
NO_XNET_CONNECTION=TRUE
DFN1006H4-3
1
5%
1/20W
MF
201
CPUBMONSNS_ALERT_L
3
2
100K
9
2
PLACE_NEAR=Q5810:3MM
2
D
R5806
5%
1/20W
MF
201
EMC1704-2
2
0201
74 INLET_THMSNS_D1_N
3
1
R5802
100K
CRITICAL
1
17
D
1
74 INLET_THMSNS_D1_P
2
C
C
TBT,MLB Bottom Proximity Sensors
B
B
R5840
0
1
74 TBTTHMSNS_D2_R_P
3
1
Q5820
1
2
TBT_MLBBOT_THMSNS_P
TBT, MLBBOT and TBD Temp Sensor
44 74
5%
1/20W
MF
0201
PLACE_NEAR=Q5820:3MM
C5820
R5810
47PF
BC846BLP
DFN1006H4-3
2
2
5%
25V
NP0-C0G-CERM
0201
R5841
47
1
PP3V3_S0
2
TBT_MLBBOT_THMSNS_N
2
5%
1/20W
MF
201
0
1
TBTTHMSNS_D2_R_N
74
74 65 64 62 61
36 30 26 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
44 74
PP3V3_S0_TBTMLB_ISNS_R
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
VOLTAGE=3.3V
1
VDD
3
44 74
NO_XNET_CONNECTION=TRUE
DFN1006H4-3
2
2
2
C5813
Place Q5820 close to TBT on TOP side
10%
10V
X7R-CERM
0201
5%
25V
NP0-C0G-CERM
0201
74 44
TBT_MLBBOT_THMSNS_P
1
3
2200PF
C5840
47PF
BC846BLP
R5811
EMC1414-1-AIZL
BI
Placement note:
PLACE_NEAR=Q5840:3MM
1
1
10%
6.3V
CERM-X5R
0201
BI
2
4
TBDTHMSNS_D2_N
5
DP1
THERM*/ADDR
CRITICAL
1
22K
5%
1/20W
MF
201
MSOP
TBT_MLBBOT_THMSNS_N
Q5840
2
U5810
TBDTHMSNS_D2_P
74 44
C5810
0.1UF
1
5%
1/20W
MF
0201
2
7 TBT_INLET_THM_L
ALERT*
8
TBTMLBSNS_ALERT_L
DP2/DN3
SMDATA
9
SMBUS_SMC_3_SDA
BI
36 37 40 64 73
DN2/DP3
SMCLK
SMBUS_SMC_3_SCL
BI
36 37 40 64 73
DN1
10
OUT
39
GND
44 74
6
Placement note:
Place Q5840 on MLB bottom side opposite U5810
74 44
TBDTHMSNS_D2_P
TBT_MLBBOT_THMSNS_P
PLACE_NEAR=Q5850:3MM
1
BC846BLP
DFN1006H4-3
2
2
C5850
C5812
Placement note:
47PF
1
Q5850
BI
NO_XNET_CONNECTION=TRUE
3
A
44 74
TBD
PLACE_NEAR=U5810.4:5mm
TBDTHMSNS_D2_N
44 74
74 44
BI
10%
10V
X7R-CERM
0201
1
2200PF
PLACE_NEAR=U5810.5:5mm
5%
25V
NP0-C0G-CERM
0201
SYNC_MASTER=J41_MLB
2
SYNC_DATE=02/06/2013
PAGE TITLE
Thermal Sensors
Write Address: 0x39
Read Address: 0x38
TBT_MLBBOT_THMSNS_N
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
74 44
TBT_MLBBOT_THMSNS_P
74 44
TBT_MLBBOT_THMSNS_P
TBT_MLBBOT_THMSNS_P
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
44 74
TBT_MLBBOT_THMSNS_N
44 74
MAKE_BASE=TRUE
74 44
TBT_MLBBOT_THMSNS_N
74 44
TBT_MLBBOT_THMSNS_N
MAKE_BASE=TRUE
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
58 OF 121
SHEET
44 OF 76
1
A
8
7
6
5
4
3
2
1
FAN CONNECTOR
D
R6010
0
1
64 65 74
8 11 12 13 15 17 18 26 30 36 38
39 40 41 42 43 44 56 59 61 62
PP3V3_S0
2
NOSTUFF
5%
1/20W
MF
0201
1
C6010
0.1UF
NOSTUFF
CRITICAL
74LVC1G08
SOT891
PP3V3_S0_FAN
4
2
6
10%
6.3V
CERM-X5R
0201
BYPASS=U6010:3mm
2
U6010
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.1 MM
VOLTAGE=3.3V
C
D
08
1
PP5V_S0
16 17 32 51 52 56 58 59 61 62
64
NC
3
C
5
NC
518S0793
CRITICAL
R6060
J6000
1
FF14A-4C-R11DL-B-3H
47K
5%
1/20W
MF
201
R6065
37
OUT
47K
SMC_FAN_0_TACH
1
2
64
NC
2
1
2
FAN_RT_TACH
4
NC
B
IN
DMN32D2LFB4
DFN1006H4-3
SYM_VER_3
64
FAN_RT_PWM
3
D
1
G
2
2
SMC_FAN_0_CTL
6
Q6060
S
37
MOTOR CONTROL
GND
1
100K
5%
1/20W
MF
201
5V DC
TACH
3
5%
1/20W
MF
201
R6061
F-RT-SM
5
B
A
SYNC_MASTER=J41_MLB
SYNC_DATE=02/06/2013
PAGE TITLE
Fan
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
60 OF 121
SHEET
45 OF 76
1
A
8
7
6
5
4
3
2
1
SPI ROM
Quad-IO Mode (Mode 0 & 3) supported.
SPI Frequency: 50MHz for CPU, 20MHz for SMC.
64 62 59 58 57 18 14 11 8
SPI+SWD SAM Connector
PP3V3_SUS
SAMCONN
CRITICAL
D
D
C6101
BYPASS=U6100::3mm
0.1UF
C6100
10%
16V
X5R-CERM
0201
VCC
U6101
69 46
1
J6100
CRITICAL
DF40PC-12DP-0.4V-51
M-ST-SM
VCC
0.1UF
10%
16V
X5R-CERM
0201
8
2
8
BYPASS=U6101::3mm
1
14
U6100
2
SPI_MLB_CLK
W25Q64FVZPIG
64MBIT
6
2
IO0
WSON
CLK
46 69
69 46
64 46 15
SPI_MLB_CS_L
SPIROM_USE_MLB
3
5
6
Y
B CRITICAL
OE*
C
SPI_MLBROM_CS_L
7
1
A
SOT833
OMIT_TABLE
PLACE_NEAR=U6100.1:12MM
69 46
D
69 46
3
7
SPI_MLB_IO3_HOLD_L
CS*
WP*(IO2) IO2
HOLD*(IO3) IO3
GND
6
5
SPI_ALT_IO2_WP_L
SPI_ALT_IO3_HOLD_L
8
7
IO1
2
DO(IO1)
SPI_MLB_IO1_MISO
46 69
10
9
SMC_RESET_L
12
11
OUT
46 64
46 64
15 46 64
BI
37 38 64
BI
OUT
37 38 64
9
4
SPI_ALT_CLK
SPI_ALT_CS_L
SPIROM_USE_MLB
SMC_TMS
(SWDIO)
SMC_TCK
(SWCLK)
15
64 46
64 50 38 37
GND THRM_PAD
4
3
SPI_ALT_IO1_MISO
64 46
1
SPI_MLB_IO2_WP_L
1
4
SPI_ALT_IO0_MOSI
16
SPI_MLB_IO0_MOSI
64 46
64 46
5
DI(IO0)
74LVC1G99
2
13
PP3V42_G3H
59 50 49 40 38 37 36 35 30 17
65 64 62 61
NOTE: If HOLD* is asserted
ROM will ignore SPI cycles
in normal and Dual-IO modes.
Quad SPI and QPI instructions require the non-volatile Quad Enable bit (QE)
in Status Register-2 to be set. When QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3.
SPI Bus Series Termination
C
C
SPI_ALT_IO3_HOLD_L
SPI_ALT_IO2_WP_L
PLACE_NEAR=J6100.10:5mm
PLACE_NEAR=J6100.8:5mm
SPI_ALT_IO1_MISO
SPI_ALT_IO0_MOSI
PLACE_NEAR=J6100.2:5mm
PLACE_NEAR=J6100.15:5mm
SPI_ALT_CLK
SPI_ALT_CS_L
PLACE_NEAR=J6100.12:5mm
46 64
46 64
46 64
46 64
SAM Card ROM Slave
46 64
46 64
PLACE_NEAR=J6100.14:5mm
SAMCONN
1
R6133
SAMCONN
1
43
5%
1/20W
MF
2 201
SAMCONN
1
R6132
SAMCONN
1
R6128
43
24.9
5%
1/20W
MF
2 201
SAMCONN
1
R6127
43
1%
1/20W
MF
2 201
SAMCONN
1
R6126
43
5%
1/20W
MF
2 201
R6125
43
5%
1/20W
MF
2 201
5%
1/20W
MF
2 201
R6110
69 14
IN
1
2
IN
SPI_CLK_R
15
1
PLACE_NEAR=U0500.AA3:5mm
BI
69 14
BI
69
SPI_MISO
1
BI
BI
1
15
69
SPI_MOSI
2
69
SPI_MISO_R
1
46 69
OUT
46 69
PLACE_NEAR=R6126.2:5mm
MLB ROM Slave
SPI_MLB_IO0_MOSI
BI
46 69
BI
46 69
SPI_MLB_IO2_WP_L
BI
46 69
SPI_MLB_IO3_HOLD_L
BI
46 69
PLACE_NEAR=R6127.2:5mm
2
PLACE_NEAR=U6100.2:5mm
1
PLACE_NEAR=U0500.Y6:5mm
1
15
1%
1/20W
MF
201
R6118
SPI_IO & lt; 2 & gt;
PLACE_NEAR=U0500.AF1:5mm
2
2
5%
1/20W
MF
201
R6123
PLACE_NEAR=U0500.AA2:5mm
SPI_IO & lt; 3 & gt;
OUT
SPI_MLB_IO1_MISO
1
24.9
43
43
5%
1/20W
MF
201
R6122
2
5%
1/20W
MF
201
R6119
69 14
SPI_CLK
R6112
1
PLACE_NEAR=U0500.AA2:5mm
5%
1/20W
MF
201
69 14
2
5%
1/20W
MF
201
R6121
2
SPI_MOSI_R
15
SPI_MLB_CS_L
SPI_MLB_CLK
1
PLACE_NEAR=R6125.2:5mm
R6113
B
43
SPI_CS0_L
5%
1/20W
MF
201
5%
1/20W
MF
201
CPU Master
69 14
69
PLACE_NEAR=U0500.Y7:5mm
R6111
69 14
R6120
15
SPI_CS0_R_L
15
2
69
SPI_IO2_R
1
5%
1/20W
MF
201
2
SPI_IO3_R
1
5%
1/20W
MF
201
43
43
2
5%
1/20W
MF
201
R6131
69
PLACE_NEAR=R6132.2:5mm
2
5%
1/20W
MF
201
B
R6130
PLACE_NEAR=R6133.2:5mm
R6114
69 37
OUT
SPI_SMC_MISO
1
24.9
1%
1/20W
MF
201
69 37
IN
SPI_SMC_MOSI
2
PLACE_NEAR=U6100.2:1mm
R6115
1
15
5%
1/20W
MF
201
SMC12 Master
69 37
IN
SPI_SMC_CLK
2
PLACE_NEAR=U6100.5:1mm
R6116
1
15
5%
1/20W
MF
201
A
69 37
IN
2
PLACE_NEAR=U6100.6:1mm
R6117
15
SPI_SMC_CS_L
1
2
SYNC_MASTER=YHARTANTO_J44
PLACE_NEAR=U6100.1:1mm
SYNC_DATE=01/09/2013
PAGE TITLE
5%
1/20W
MF
201
SPI Debug Connector
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
BOM_COST_GROUP=CPU SUPPORT
8
7
6
5
4
3
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
61 OF 121
SHEET
46 OF 76
1
A
8
7
6
5
4
3
2
1
SPEAKER AMPLIFIERS
APN:353S2888
SPEAKER LOWPASS
80 HZ & lt; FC & lt; 132 HZ
GAIN
6DB
D
D
Right Speaker Connector
MIN_NECK_WIDTH=0.2 mm
ALIAS OF PP5VRT_S0, MIN_LINE_WIDTH=0.50MM, MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.5 mm
R6414
VOLTAGE=5V
0
1
PP5V_S3_U6210
2
5%
1/10W
MF-LF
603
1
C6407
OMIT_TABLE
10%
16V
X5R-CERM
0201
PVDD
C6410
MAX98300
0.1UF
IN
OMIT_TABLE
CRITICAL
C6411
IN
1
SPKRAMP_INR_N
74 MAX98300_R_P
2
A3
B3
10%
16V
X5R-CERM
0201
IN+
CRITICAL
IN-
IN
OUT+
OUT-
MIN_LINE_WIDTH=0.30 mm
74 64 SPKRAMP_ROUT_P
C1
2
MIN_LINE_WIDTH=0.30 mm
C2
SHDN*
NC
GAIN
C3
4
R_AMP_GAIN
2
1
2
R6411
R6412
100K
PGND
SPKRAMP_SHDN_L
1
1
74 64 SPKRAMP_ROUT_N
B1
A2
65 61
M-RT-SM
3
2
MIN_NECK_WIDTH=0.20 mm
10%
16V
X5R-CERM
0201
C
J6404
78171-0002
20%
6.3V
POLY-TANT
0805-LLP
MIN_NECK_WIDTH=0.20 mm
B2
0.1UF
74 65 61
C6401
47UF
2
WLP
74 MAX98300_R_N
1
SPKRAMP_INR_P
5%
1/20W
MF
201
1
1
100K
U6410
2
CRITICAL
74 65 61
R6413
518S0519
CRITICAL
CRITICAL
NOSTUFF
0.1UF
A1
64 62 58 55 54 49 35 32 PP5V_S4RS3
C
5%
1/20W
MF
201
100K
2
PART NUMBER
132S0460
QTY
2
5%
1/20W
MF
201
DESCRIPTION
REFERENCE DES
CAP,CER,X5R,0.1UF,10%,16V,0201,MURATA
C6410,C6411
CRITICAL
BOM OPTION
CRITICAL
B
B
A
SYNC_MASTER=J41_MLB
SYNC_DATE=04/26/2013
PAGE TITLE
Audio: Speaker Amp
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
64 OF 121
SHEET
47 OF 76
1
A
8
7
6
5
4
3
2
1
D
D
13 " SPECIFIC
Battery Connector
C
PPVBAT_G3H_CONN
CRITICAL
C6951
1
1
2
2
1UF
J6950
10%
16V
X5R
402
WTB-PWR-M82
M-RT-SM
C
50 64
C6950
0.1UF
10%
25V
X5R
402
1
2
3
4
5
6
64
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA
SYS_DETECT_L
IN
BI
37 40 50 64 73
37 40 50 64 73
7
1
518S0540
5%
1/20W
MF
201
2
10K
1
R6950
9
CRITICAL
NO STUFF
D6950
RCLAMP2402B
2
3
8
SC-75
B
B
A
SYNC_MASTER=MASTER
SYNC_DATE=MASTER
PAGE TITLE
Battery Connector
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
69 OF 121
SHEET
48 OF 76
1
A
8
7
6
5
4
3
2
1
MLB to LIO Power Cable Connector
CRITICAL
J7000
WTB-PWR-M82
M-RT-SM
64 62 50
PPDCIN_G3H
1
2
3
D
D
62 64
32 35 47
54 55 58
PP5V_S4RS3
4
5
6
1
518S0508
C7006
0.1UF
2
10%
16V
X5R-CERM
0201
NO STUFF
CRITICAL
NO STUFF
CRITICAL
C7007
1
1
1UF
10%
35V
X5R
603
2
2
C7008 NO STUFF
1UF
C7005 1
10%
35V
X5R
603
0.1UF
10%
50V
X7R
603-1
2
1
Input impedance of 68K meets
sparkitecture requirements
for detection of B121 (16.5V)
R7012
68K
CRITICAL
2
Q7010
1%
1/20W
MF
201
SI5419DU
POWERPAK
5A
S
D
1
C7012
4
1
2
C
R7011
2
DCIN_ISOL_GATE_R 1
10K
2
1%
1/20W
MF
201
DCIN_ISOL_GATE
64 62 50 42
5%
1/20W
MF
201
0.047UF
10%
25V
X7R
0402
C
R7010
100K
5
CRITICAL
G
1
PPDCIN_G3H_ISOL
CRITICAL
D7012
K
SDZT15R6.8
6.8V Zener
0201
A
CRITICAL
3.425V " G3Hot " Supply
R7006
1
5%
1/8W
MF-LF
805
R7005
10
1
2
5%
1/8W
MF-LF
805
B
2 PPBUS_G3H_R
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=8.6V
SOT-323
1
3
PP18V5_DCIN_ISOL_R
Supply needs to guarantee 3.31V delivered to SMC VRef generator
PPVIN_G3H_P3V42G3H
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=18.5V
2
P3V42G3H_BOOST
DIDT=TRUE
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=18.5V
3
PPBUS_G3H
BAT30CWFILM
6
64 62 56 50 42 41 27
D7005
4.7
VIN
C7094
BOOST
10%
10V
CERM
402
LT3470AED
B
1
0.22UF
U7090
CRITICAL
L7095
2
10UH-20%-0.85A-0.46OHM
PP3V42_G3H
DFN
8 SHDN*
R7080
0
CRITICAL
C7091
CRITICAL
1
1
1UF
10%
25V
X5R
402
C7090
2
2
CRITICAL
GND
1 CRITICAL
BIAS 2
1
P3V42G3H_SW
FB 1
THRM
PAD
2
20%
25V
POLY-TANT
CASE-B2-SM
300mA Max Output
C7095
22PF
2
NO STUFF
1
R7081
49.9K
2
1%
1/20W
MF
201
(Switcher limit)
348K
1%
1/20W
MF
201
5%
50V
C0G
0201
CRITICAL
2
1
C7099
1
10UF
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
& lt; Rb & gt;
R7096 1
1000PF
5%
25V
CERM
0402
& lt; Ra & gt;
R7095 1
P3V42G3H_FB
NO STUFF
C7080
Vout = 3.425V
2520
1
5.6UF
17 30 35 36 37 38 40 46 50
59 61 62 64 65
2
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE
C7092
1UF
10%
25V
X5R
402
7 NC
5
2
NC
5%
1/20W
MF
0201
SW 4
9
P3V42G3H_SHDN_L
1
1%
1/20W
MF
201
CRITICAL
1
2
C7098
10UF
20%
10V
2 X5R-CERM
0402-1
200K
2
20%
10V
X5R-CERM
0402-1
2
Vout = 1.25V * (1 + Ra / Rb)
A
SYNC_MASTER=J43_MLB
SYNC_DATE=09/13/2012
PAGE TITLE
DC-In & G3H Supply
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
70 OF 121
SHEET
49 OF 76
1
A
8
7
6
5
4
Reverse-Current Protection
3
2
1
Need to stuff R7192 if either PP5V5_DCIN:YES or PP5V5_VDDP are used!
PP5V5_DCIN:YES
5.5v " G3Hot " Supply
NO STUFF
R7190
For Erp Lot6 spec
MIN_NECK_WIDTH=0.2 mm
R7192
0
MIN_LINE_WIDTH=0.5 mm
1
0
1
PPCHGR_DCIN_D_R
50
2
CHGR_DCIN_D
MIN_NECK_WIDTH=0.2 mm
Inrush Limiter
MF-LF
DIDT=TRUE
MF-LF
MIN_LINE_WIDTH=0.5 mm
5%
25V
5
4
9
8
7
10
1
2
X5R-CERM
1/20W
PPDCIN_G3H
CRITICAL
201
2
SHDN*
SW
4
BIAS
8
MIN_LINE_WIDTH=0.6 mm
2
R7180
IRF9395TRPBF
10%
25V
1
10%
25V
G
PP5V1_CHGR_VDDP 50
402
X5R-CERM
MF
PP5V5_CHGR_VDDP
NO STUFF
GND
0603
2
NO STUFF
CRITICAL
CRITICAL
FB
THRM
PAD
D
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
VOLTAGE=5.5V
1
1
C7198
NO STUFF & lt; Ra & gt;
1
R7195
NO STUFF
1 C7195
681K
1
C7199
10UF
2
10UF
20%
10V
20%
10V
2
X5R
1%
22PF
603
Vout = 5.50V
200MA MAX OUTPUT
(Switcher limit)
X5R
603
1/20W
5%
6
3
2
SWITCH_NODE=TRUE
DIDT=TRUE
2
5
G
1/20W
201
CHGR_AGATE_DIV
5%
1/16W
2520
MIN_NECK_WIDTH=0.25 mm
CRITICAL
NC
7
4.7UF
5%
402
1
C7184
100K
DIRECTFET-MC
2
X5R
1
P5V1_SW
MIN_LINE_WIDTH=0.5 mm
VOLTAGE=18.5V
9
S
D
D
S
D
Q7180
MF-LF
10UH-20%-0.85A-0.46OHM
402
MIN_NECK_WIDTH=0.4 mm
0.1UF
L7195
10V
DFN
PPDCIN_G3H_INRUSH
MF
2
1
C7185
2
NO STUFF
CERM
LT3470A
0
1
10%
U7190
2
CRITICAL
0.22UF
NO STUFF
0603
64 62 49
3
6
10%
BOOST
R7191
1
C7194
VIN
4.7UF
R7185
1%470K
PP5V5_VDDP
NO STUFF
C7190
NCNCNCNC
CHGR_DCIN 50
402
1/16W
NO STUFF1
FROM ADAPTER
5%
402
1/16W
1
2
P5V1_BOOST
CHGR_SGATE_DIV
2
MIN_LINE_WIDTH=0.25 mm
MF
50V
201
C0G
2
0201
MIN_NECK_WIDTH=0.2 mm
R7186
1
1
332K
& lt; Rb & gt;
NO STUFF
R7196
5%
MF
1/20W
1
MF
201
2
PPDCIN_G3H_ISOL
64 62 49 42
R7181
62K
1%
1/20W
CRITICAL
P5V1_FB
2
D7105
200K
201
1%
(CHGR_AGATE)
MIN_LINE_WIDTH=0.25 mm
BAT30CWFILM
1/20W
MIN_NECK_WIDTH=0.2 mm
MF
Vout = 1.25V * (1 + Ra / Rb)
(CHGR_SGATE)
PP5V5_DCIN:NO
SOT-323
201
2
MIN_LINE_WIDTH=0.25 mm
1
R7105
1
50 PPCHGR_DCIN_D_R
3
20
MIN_NECK_WIDTH=0.2 mm
2
R7121
(CHGR_DCIN)
MIN_LINE_WIDTH=0.5 mm
10
MIN_LINE_WIDTH=0.5 mm
5%
1/10W
MF-LF
603
MIN_NECK_WIDTH=0.2 mm
2
VOLTAGE=18.5V
1
MIN_NECK_WIDTH=0.2 mm
2
MIN_LINE_WIDTH=0.2 mm
1
C7120
MF
0.047UF
MIN_LINE_WIDTH=0.2 mm
201
MIN_NECK_WIDTH=0.2 mm
10%
16V
DIVIDER SETS ACIN THRESHOLD AT 13.55V
2
30mA max load
0402
1
MIN_NECK_WIDTH=0.1 mm
0.5%
1W
MF-LF
0612
3
10
1
1
2
PPDCIN_G3H_CHGR
4.7
MIN_LINE_WIDTH=0.2 mm
0.020
73 CHGR_CSI_R_N
R7122
X7R-CERM
R7101
PP5V1_CHGR_VDD
R7120
4
73 CHGR_CSI_R_P
1/20W
ACIN pin threshold is 3.2V, +/- 50mV
CRITICAL
2
5%
MIN_NECK_WIDTH=0.2 mm
5%
50 PP5V1_CHGR_VDDP
2
1/16W
CRITICAL
MIN_NECK_WIDTH=0.15 mm
MF
MIN_NECK_WIDTH=0.2 mm
5%
MIN_LINE_WIDTH=0.6 mm
1/20W
MIN_LINE_WIDTH=0.2 mm
VOLTAGE=5.1V
201
C7130
VOLTAGE=5.1V
PP3V42_G3H
C7101
402
1
C7122
1UF
R7110
NO STUFF
X5R
20%
25V
POLY-TANT
0.1UF
10%
25V
2
2
1
25V
POLY-TANT
CASE-D3L
2
0.001UF
10%
25V
2
X5R
10%
50V
2
X5R
603-1
CASE-D3L
C7137
1UF
10%
25V
2
1
C7136
1UF
20%
2
1
C7135
X7R-CERM
603-1
C
0402
X5R
402
402
5%
VDD
MF
64 46 38 37
IN
SMC_RESET_L
1
CHGR_RST_L
13
IN
SMBUS_SMC_5_G3_SCL
11
BI
SMBUS_SMC_5_G3_SDA
IN
CHGR_VFRQ
2
5%
48 40 37
73 64
MF 48 40 37
73 64
0201
59
1/20W
Float CELL for 1S
10
4
CHGR_CELL
6
CHGR_ACIN
3
5
CHGR_ICOMP
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
CHGR_VNEG
5%
1/20W
1
8
MIN_LINE_WIDTH=0.2 mm
2
MIN_NECK_WIDTH=0.2 mm
R7111
2
R7115
73 CHGR_CSO_P
18
255K
MF
201
7
CHGR_VCOMP
100
73 CHGR_CSO_N
17
1%
1/20W
MF
201
1
C7150
0.47UF
46.4K
10%
10V
2
50 CHGR_DCIN
Max Current = 8A
CHGR_SGATE
1
CHGR_AGATE
28 73
CHGR_CSI_P
27 73
CHGR_CSI_N
PLACE_NEAR=U7100.25:2mm
1
2 3 4 9
C7125
0.22UF
Q7130
CERM
CHGR_BOOT
24
CHGR_UGATE
23
CHGR_PHASE
21
CHGR_LGATE
CRITICAL
NTMFD4902NF
402
25
TO SYSTEM
f = 400 kHz
CRITICAL
10%
10V
2
MIN_LINE_WIDTH=0.5 mm
DFN
1
DIDT=TRUE
CRITICAL
L7130
MIN_NECK_WIDTH=0.2 mm
F7140
4.7UH-17A
8AMP-24V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.5 mm
DIDT=TRUE
GATE_NODE=TRUE
1
2
1
2
PPBUS_G3H
10
MIN_LINE_WIDTH=0.5 mm
1206
MIN_LINE_WIDTH=0.6 mm
DIDT=TRUE
DIDT=TRUE
27 41 42 49 56 62 64
PIMC104T4R7MN-SM
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=8.6V
16
CHGR_BGATE
9
CHGR_AMON
OUT
41
15
CHGR_BMON
OUT
41
14
SMC_BC_ACOK
OUT
37 38 61 65
8
PPVBAT_G3H_CHGR_REG
MIN_LINE_WIDTH=0.6 mm
5 6 7
BYPASS=L7130:Q7130:1.5mm
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=8.6V
C7140
X5R
0402
C7115
20V/V
29
CHGR_VCOMP_R
1%
1/20W
MF
201
2
26
GATE_NODE=TRUE
BGATE
AMON
36V/V BMON
(OD) ACOK
CSOP
CSON
(AGND)
R7113
1
VDDP
VHST CRITICAL
DCIN
SMB_RST_N
SGATE
SCL
U7100 AGATE
TQFN
SDA
CSIP
VFRQ
CSIN
CELL
BOOT
ACIN
UGATE
ICOMP
PHASE
VCOMP
LGATE
VNEG
ISL6259
12
2
PGND
201
0
2
2
402
1/20W
R7100
1
C7121
10%
25V
X5R
1
100K
1
BYPASS=Q7130:1.5mm
1
20
R7102
C7131
33UF-0.06OHM
62UF-0.023OHM
20%
11V
TANT-POLY
CASE-B2S
22
2
1%
1/20W
MF
201
19
130K
1
0.1UF
10%
10V
THRM_PAD
C
1
1
33UF-0.06OHM
MF-LF
59 49 46 40 38 37 36 35 30 17
65 64 62 61
CRITICAL
VOLTAGE=18.5V
1
470PF
1
1
C7141
62UF-0.023OHM
20%
11V
TANT-POLY
CASE-B2S
2
2
1
1
2
C7143
62UF-0.023OHM
20%
11V
TANT-POLY
CASE-B2S
2
C7145
1000PF
10%
16V
X7R-1
0201
10%
16V
R7142 1
X5R-X7R-CERM
2
0201
1K
1
R7116 1
1%
1/20W
MF
201
XW7100
X5R
SM
402
1
Q7155
R7150
0.01
2
SI7137DP
0.5%
(GND)
SO-8
TO/FROM BATTERY
1W
MF
PLACE_NEAR=U7100.22:1mm
2
0612-4
2
3
4
PPVBAT_G3H_CHGR_R
PPVBAT_G3H_CONN
MIN_LINE_WIDTH=0.6 mm
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.15 mm
5
2
CHGR_VNEG_R
2.2
R7152
0
MIN_NECK_WIDTH=0.1 mm
1
2
73 43 CHGR_CSO_R_P
2
73 43 CHGR_CSO_R_N
5%
5%
MIN_LINE_WIDTH=0.2 mm
X5R-X7R-CERM
1
201
MIN_LINE_WIDTH=0.2 mm
(CHGR_CSO_N)
1/20W
1/20W
MF
MF
G
R7151
(CHGR_CSO_P)
10%
16V
0201
4
C7116
470PF
2
VOLTAGE=8.6V
1
VOLTAGE=8.6V
1
48 64
3
1
D
CHGR_ICOMP_R
CRITICAL
10%
10V
2
10K
B
C7102
1UF
2
S
B
5%
1/20W
MF
201
MIN_NECK_WIDTH=0.1 mm
0201
(PPVBAT_G3H_CHGR_R)
(PPVBAT_G3H_CHGR_R)
(CHGR_BGATE)
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.2 mm
1
C7142
C7111
0.1UF
1
2
2
0.01UF
10%
6.3V
2
1
X5R-CERM
0201
0201
C7105
1UF
10%
10V
CERM-X5R
C7100
C7126
1
X5R-CERM
10%
16V
X7R-1
0201
10%
50V
X5R
402-1
* R7151 HAS 2.2OHM TO COMPENSATE UNBALANCED VOLTAGE
1000PF
0.22UF
10%
10V
1
2
0603-1
DUE TO DIFFERENT CURRENT ON _P AND _N. (FROM INTERSIL)
2
C7117
1
1
10UF
GND_CHGR_AGND
MIN_NECK_WIDTH=0.2 mm
X5R
VOLTAGE=0V
805
A
C7114
1
C7113
1UF
2
2
1
0.1UF
10%
25V
10%
25V
MIN_LINE_WIDTH=0.2 mm
10%
25V
X5R
603-1
2
X5R
402
C7112
0.01UF
10%
25V
2
X7R
402
SYNC_MASTER=J43_MLB
SYNC_DATE=09/14/2012
PAGE TITLE
PBus Supply & Battery Charger
DRAWING NUMBER
Apple Inc.
R
& lt; E4LABEL & gt;
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
.
BRANCH
& lt; BRANCH & gt;
PAGE
71 OF 121
SHEET
50 OF 76
1
A
8
7
6
5
4
3
2
1
D
D
R7201
PP5V_S0
62 61 59 58 56 52 45 32 17 16
64
R7202
1
10
1
2
PP5V_S0_CPUVR_VDD
1
PLACE_NEAR=U7200.16:2mm
2
1
R7279 1
1
54.9
2
67 8
OUT
67 8
IN
IN
R7220
9.31K
21K
6.04K
1%
1/20W
MF
201
1%
1/20W
MF
201
1%
1/20W
MF
201
U7200
1%
1/20W
MF
201
2
2
2
ISL95826HRZ-_R6200
CPUVR_NTC
67 38 37 6
5
NTC
CPU_PROCHOT_L
OUT
4
VR_HOT*
BI
PLACE_NEAR=U7200.30:2mm
17 8
27
26
1
32
IN
845
1
1%
1/20W
2
1
CPUVR_ISUMN_RC
201
MF
1
10%
25V
R7210
CPUVR_ISUMN
1
255
0201
X7R-CERM
2
5%
0201
25V
IN
52
IN
8
(CPUVR_ISUMP)
C0G
15
14
CPUVR_ISUMN_R
2
1%
1/20W
MF
201
52
7
CPUVR_FB
CPUVR_FB2
47PF
2
43
3
CPUVR_IMON
OUT
12
CPUVR_ISEN1
CPUVR_ISEN2
11
10
C7210
0.01UF
10%
10V
X7R-CERM
0201
2
C7211
C7240
0.01UF
1
10%
10V
X7R-CERM
0201
+/-10%
10V
CERM
0201-1
CPUVR_PWM2
CPUVR_PWM1
DRSEL
25
CPUVR_DRSEL
52
1
R7225
22
NC
2
OUT
52
OUT
5%
1/20W
MF
0201
52
R7224
SDA
ALERT*
SCLK
CRITICAL
COMP
PGOOD
NC
NC
NC
NC
RTN
FB
FB2
2
9
19
21
24
CPU_VR_READY
0
1
OUT
8 17
C
2
5%
1/20W
MF
0201
NC
NC
NC
NC
ISUMP
ISUMN
IMON
ISEN1
ISEN2
ISEN3
1.2NF
2
20
OUT
1
33
1
23
CPUVR_FCCM
VR_ON
C7216
820PF
2
13
CPU_RTN
C7215
R7215
220PF
52
6
CPUVR_COMP
1
PWM3
PWM2
PWM1
PROG1
PROG2
PROG3
31
NO_XNET_CONNECTION=TRUE
18
SLOPE
28
CPU_VR_EN
IN
FCCM
0
29
30
10%
25V
X7R-CERM
201
NOSTUFF
CPUVR_PROG1
CPUVR_PROG2
CPUVR_PROG3
1%
1/20W
MF
2 201
C7214
LLP
CPUVR_SLOPE
R7280
CPUVR_ISUMP
67 8
PLACE_NEAR=U7200.17:2mm
2
17
16
1
R7221
CPU_VIDSOUT
CPU_VIDALERT_L
CPU_VIDSCLK
52
1
R7222
130
1%
1/20W
MF
201 2
PLACE_NEAR=U7200.32:2mm
C
1
R7223
16.9K
2
2
1
41 52 53 55 62 64
THRM
PAD
1
2
10%
6.3V
CERM-X5R
0201
PPBUS_S5_HS_COMPUTING_ISNS
FCCM = 1: Forced CCM
FCCM = 0: DCM
FCCM = FLOATING: PS4
VDD VIN
100KOHM
0201
PP1V05_S0
0.1UF
10%
25V
X7R
0402
10%
10V
X5R
402-1
2
5%
1/16W
MF-LF
402
(GND)
58 55 42 38 17 16 15 11 8 6
64 62 59
C7278
C7202
0.22UF
C7201
R7237
95.3K
PLACE_NEAR=R7279.32:2mm
1
1
1%
1/20W
MF
201
R7236 1
1%
1/20W
MF
201
2
9.31K
1
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.9V
1UF
R7235
CPUVR_NTC_R
PPVIN_S0_CPUVR_VIN
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
5%
1/16W
MF-LF
402
2
C7241
1
56PF
5%
25V
NP0-C0G
0201
CPUVR_COMP_RC
C7213
R7240 1
1
10%
6.3V
CERM-X5R
0201
B
1%
1/20W
MF
201
2
C7230
1
10%
10V
X5R-CERM
201
R7230
95.3K
1800PF
NO_XNET_CONNECTION=TRUE
75K
0.1UF
1
2
2
2
1%
1/20W
MF
201
B
2
NO_XNET_CONNECTION=TRUE
R7241
CPU_VCCSENSE_P_R
NO_XNET_CONNECTION=TRUE
1
67 8
IN
NO_XNET_CONNECTION=TRUE
0
CPU_VCCSENSE_P
1
2
C7242
2
1
5%
25V
C0G
0201
IN
2
CPU_VCCSENSE_N
NOSTUFF
NO_XNET_CONNECTION=TRUE
R7242
100PF
5%
1/20W
MF
0201
67 9
1.37K
1%
1/20W
MF
201
R7243
CPU_VCCSENSE_P_RC
XW7261
R7250
1K
2
2K
1
1%
1/20W
MF
201
1
2
CPUVR_FB_RC
1%
1/20W
MF
201
NOSTUFF
1
SM
1
2
NO_XNET_CONNECTION=TRUE
1
C7260
1
330PF
2
10%
16V
X7R
0201
C7250
330PF
2
10%
16V
X7R
0201
C7261
330PF
2
10%
16V
X7R
0201
A
SYNC_MASTER=J43_MLB
SYNC_DATE=10/09/2012
PAGE TITLE
CPU VR12.6 VCC Regulator IC
DRAWING NUMBER
Apple Inc.
& lt; SCH_NUM & gt;
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
72 OF 121
SHEET
51 OF 76
1
SIZE
D
A
8
7
64 62 55 53 51 41
6
5
4
3
2
1
Additonal Input Bulk Caps
PPBUS_S5_HS_COMPUTING_ISNS
NOSTUFF
CRITICAL
1
CRITICAL
1
C7313
62UF-0.023OHM
1
1
C7316
10UF
11V
TANT-POLY
2
CASE-B2S
1
1
C7317
1
C7318
C7319
C7370
CRITICAL
1
62UF-0.023OHM
10UF
20%
16V
X6S-CERM
0603
20%
11V
TANT-POLY
CRITICAL
CRITICAL
C7315
62UF-0.023OHM
20%
2
1
C7314
THESE TWO CAPS ARE FOR EMC
NOSTUFF
CRITICAL
2
CASE-B2S
1UF
20%
16V
X6S-CERM
0603
2
2
0.001UF
10%
16V
X6S-CERM
0402
2
0.001UF
10%
50V
X7R-CERM
0402
2
2
11V
TANT-POLY
CASE-B2S
CRITICAL
1
62UF-0.023OHM
20%
10%
50V
X7R-CERM
0402
C7371
11V
TANT-POLY
CASE-B2S
CRITICAL
1
62UF-0.023OHM
20%
2
C7372
62UF-0.023OHM
20%
2
CRITICAL
1
C7373
62UF-0.023OHM
20%
11V
TANT-POLY
2
CASE-B2S
C7375
CRITICAL
1
62UF-0.023OHM
20%
11V
TANT-POLY
2
CASE-B2S
CRITICAL
1
C7374
62UF-0.023OHM
20%
11V
TANT-POLY
2
CASE-B2S
11V
TANT-POLY
CRITICAL
1
C7376
62UF-0.023OHM
20%
2
CASE-B2S
C7377
20%
11V
TANT-POLY
2
CASE-B2S
11V
TANT-POLY
CASE-B2S
CRITICAL
64 62
51 45 32 17 16
61 59 58 56 52
PP5V_S0
R7310
CRITICAL
5
C7310 1
D
10%
16V
X6S-CERM
0402
D
G
4
PHASE 1
1
CPUVR_PHASE1
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
SISA18DN
SWITCH_NODE=TRUE
74 42
1
5%
1/10W
MF-LF
603
6
1
DFN
IN
IN
CPUVR_FCCM
7
2
3
R7314
1.00
2
1
8
THRM LGATE
PAD
5
2
5
CRITICAL
4
CPUVR_LGATE1
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
OUT
R7317
51 52
R7315 1
10%
50V
X7R-CERM
0402
1
1K
1%
1/20W
MF
201
NOSTUFF
1
R7316
200K
2
2
2
CPUVR_ISNS2_N
42 52 74
NO_XNET_CONNECTION=TRUE
NONE
NONE
NONE
0201
1%
1/20W
MF
201
Q7311
G
SISA12DN
CPUVR_ISEN1
OUT
51
CPUVR_ISUMP
PWRPAK-SM
OUT
51 52
DIDT=TRUE
9
4
OMIT_TABLE
CRITICAL
D
353S3942
S
R7311
1
2.2
CPUVR_BOOT1
2
2
3
1CPUVR_BOOT1_RC
MIN_LINE_WIDTH=0.25 MM
MIN_LINE_WIDTH=0.25 MM
5%
1/16W
MF-LF
402
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
C7311
MIN_NECK_WIDTH=0.2 MM
NOSTUFF
DIDT=TRUE
CRITICAL
1
CRITICAL
1
C7323
0.22UF
62UF-0.023OHM
1
2
C
PP5V_S0
2
CASE-B2S
CRITICAL
1
C7325
1
C7326
1
C7327
C7328
10UF
20%
11V
TANT-POLY
10%
16V
CERM
402
C7324
THESE TWO CAPS ARE FOR EMC
NOSTUFF
CRITICAL
1
62UF-0.023OHM
20%
2
61 59 58 56 52 51 45 32 17 16
64 62
OMIT
CPUVR_ISUMN
NO_XNET_CONNECTION=TRUE
C7312
0.001UF
GND
1%
1/20W
MF-LF
0201
DIDT=TRUE
NOSTUFF
1
2
UGATE
OUT
42 52 74
1
2
BOOT
FCCM
CPUVR_ISNS1_N
CPUVR_PH1_SNUB
PHASE
52 51
3
CPUVR_ISNS1_P
2.2
ISL6208D
PWM
OUT
D
1
4
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.8V
NOSTUFF
U7310
3
2
MPCG0730-SM
S
CPUVR_PWM1
MF
2
0612
R7312
DIDT=TRUE
VCC
51
1W
PPVCC_S0_CPU_PH1
152S1757
DIDT=TRUE
PWRPAK-SM
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
1%
0.40UH-20%-16A
Q7310
2
CPUVR_UGATE1
L7310
OMIT_TABLE
CRITICAL
1UF
0.00075
11V
TANT-POLY
2
CASE-B2S
10UF
1UF
20%
16V
X6S-CERM
0603
10%
16V
X6S-CERM
0402
10%
50V
X7R-CERM
0402
1
0.001UF
20%
16V
X6S-CERM
0603
2
2
2
C7329
0.001UF
2
10%
50V
X7R-CERM
0402
C
CRITICAL
R7320
CRITICAL
0.00075
L7320
C7320 1
1
CPUVR_PHASE2
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
2
5
MF
D
PHASE 2
6
VCC
1
NOSTUFF
74 42
1
5%
1/10W
MF-LF
603
PWRPAK-SM
DIDT=TRUE
3
1
IN
CPUVR_FCCM
7
2
1
3
UGATE
1
10%
50V
X7R-CERM
0402
8
THRM LGATE
PAD
5
5
OMIT_TABLE
CRITICAL
4
GND
9
CRITICAL
D
OMIT
CPUVR_ISUMN
OUT
R7325
1
1
1K
1%
1/20W
MF
201
NOSTUFF
1
R7326
200K
2
2
1%
1/20W
MF
201
CPUVR_ISNS1_N
2
NONE
NONE
NONE
0201
42 52 74
NO_XNET_CONNECTION=TRUE
Q7321
G
CPUVR_ISEN2
SISA12DN
OUT
51
CPUVR_ISUMP
4
CPUVR_LGATE2
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
R7327
51 52
NO_XNET_CONNECTION=TRUE
C7322
0.001UF
FCCM
1%
1/20W
MF-LF
0201
2
2
52 51
42 52 74
1.00
2
2
BOOT
OUT
R7324
DIDT=TRUE
NOSTUFF
DFN
PWM
CPUVR_ISNS2_N
1
PHASE
CPUVR_PWM2
CPUVR_ISNS2_P
S
U7320
IN
4
CPUVR_PH2_SNUB
ISL6208D
51
OUT
Vout = 1.85V max
32A max output
f = 700kHz
2
3
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.8V
2.2
SISA18DN
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
0612
R7322
Q7320
G
4
CPUVR_UGATE2
SWITCH_NODE=TRUE
PPVCC_S0_CPU_PH2
2
MPCG0730-SM
152S1757
DIDT=TRUE
OMIT_TABLE
CRITICAL
8 10 42 62 64
1W
1UF
10%
16V
X6S-CERM
0402
PPVCC_S0_CPU
1%
0.40UH-20%-16A
OUT
51 52
PWRPAK-SM
DIDT=TRUE
S
353S3942
B
R7321
1
2.2
2
CPUVR_BOOT2
2
B
3
1 CPUVR_BOOT2_RC
MIN_LINE_WIDTH=0.25 MM
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
C7321
5%
1/16W
MF-LF
402
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
0.22UF
1
2
10%
16V
CERM
402
A
SYNC_MASTER=J41_MLB
SYNC_DATE=05/21/2013
PAGE TITLE
CPU VR12.5 VCC Power Stage
DRAWING NUMBER
Apple Inc.
R
& lt; E4LABEL & gt;
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
.
BRANCH
& lt; BRANCH & gt;
PAGE
73 OF 121
SHEET
52 OF 76
1
A
8
7
6
5
4
3
2
1
D
D
64 62 55 52 51 41
PPBUS_S5_HS_COMPUTING_ISNS
1
1
C7430
62UF-0.023OHM
70 62 53 42 23 22 21 20 19 17
62 54 36
PP1V2_S3
1
C7431
20%
2 11V
TANT-POLY
CASE-B2S
1
C7432
0.001UF
10%
25V
X5R
603-1
2
1
C7433
1UF
62UF-0.023OHM
20%
2 11V
TANT-POLY
CASE-B2S
10%
50V
X7R-CERM
0402
2
C7434
62UF-0.023OHM
20%
2 11V
TANT-POLY
CASE-B2S
BYPASS=U7400.2:1mm
PP5V_S5
C7401
1
10UF
20%
10V
X5R
603
BYPASS=U7400.12:1mm
C7400
1
2
10UF
CRITICAL
2
Q7430
(DDRREG_DRVH)
C
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VLDOIN
59
IN
IN
MEMVTT_PWR_EN
DDRREG_EN
(VTT Enable)
(VDDQ/VTTREF Enable)
17
S3
S5
16
DDRREG_1V8_VREF
U7400
TPS51916
6
1
1
0.1UF
10%
16V
X7R-CERM
0402
BYPASS=U7400.6:1mm
19
VREF
8
R7415
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
28.7K
2
DDRREG_FB
DDRREG_MODE
DDRREG_TRIP
1%
1/20W
MF
2 201 PLACE_NEAR=U7400.8:5mm
REFIN
19
18
DDRREG_VBST
DDRREG_DRVH
15
14
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
10%
DIDT=TRUE
25V
X5R
402
DIDT=TRUE
GATE_NODE=TRUE
DIDT=TRUE
DDRREG_LL
13
SWITCH_NODE=TRUE
DIDT=TRUE
QFN
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
C7415
VBST
DRVH
SW
MODE
TRIP
DRVL
CRITICAL
PGOOD
VDDQSNS
VTT
VTTSNS
VTTREF
11
20
9
3
62
24
DDRREG_VTTSNS
1
2
3
TG
4
TGR
VSW
7
PDDR_S3_REG_L
8
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.1 MM
DIDT=TRUE
XW7460
BG
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
2
PLACE_NEAR=C2720.1:3mm
0.01UF
1%
1/20W
MF
2 201
2
10%
16V
X7R-CERM
0402
BYPASS=U7400.8:1mm
PLACE_NEAR=U7400.19:3mm
1
R7417
200K
1%
1/20W
MF
2 201
PLACE_NEAR=U7400.18:3mm
1
4
PPVTT_S3_DDR_BUF
R7418
49.9K
0.002
1
MF-LF1/4W
1206 1%
2
VOLTAGE=1.2V
3
MIN_LINE_WIDTH=0.8 MM
MIN_NECK_WIDTH=0.1 MM
74 41
OUT
OUT
DIDT=TRUE
CRITICAL
ISNS_1V2_S3_N
C7435
10%
50V
X7R-CERM
0402
C7446
20%
2.0V
POLY-TANT
CASE-B2-SM1
2
C7441
10%
50V
X7R-CERM
0402
14.1A max output
(Q7435 limit)
2
1
C7445
20%
10UF
20%
2.0V 2
POLY-TANT
CASE-B2-SM1
2
2
6.3V
X5R
603
PLACE_NEAR=C7440.1:1mm
2
XW7401
SM
1
BYPASS=U7400.3:3mm
1%
1/20W
MF
2 201
f = 400 kHz
1
330UF
1
Vout = 1.35V
1
0.001UF
CRITICAL
0.001UF
20%
6.3V
X5R
603
C7440
330UF
NOSTUFF
C7462
62 70
17 19 20 21
22 23 42 53
PP1V2_S3
4
ISNS_1V2_S3_P
74 41
5%
1/10W
MF-LF
603
10UF
2
PLACE_NEAR=U7400.21:1mm
2
XW7400
SM
1
B
1
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=0.6V
21
57.6K
C7416
7
1
10
R7416
VTT THRM
GND PAD
FDSD0630-SM
PPDDR_S3_REG_R
PDDR_S3_REG_SNUB
CRITICAL
PGND GND
PLACE_NEAR=U7400.8:5mm
2
1
R7435
2.2
10mA max load
1
1
NOSTUFF
1
5
R7450
L7430
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
(DDRREG_DRVL)
CRITICAL
1.0UH-20%-11A-0.011OHM
6
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
5
C
1
CRITICAL
(DDRREG_LL)
DDRREG_DRVL
DIDT=TRUE
GATE_NODE=TRUE
DDRREG_PGOOD
OUT 59
DDRREG_VDDQSNS
PP0V6_S0_DDRVTT
SM
1
VIN
0.1UF
1
DDRREG_VBST_RC 2
MF-LF
1/16W
2
0
9
17
V5IN
402
5%
1
Q3D
C7425
R7425
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
12
CSD58873Q3D
PGND
2
20%
10V
X5R
603
C7450
1
R7460
0.22UF
10%
10V
CERM
402
10
(DDRREG_VDDQSNS)
2
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.17 mm
1
2
5%
1/20W
MF
201
DDRREG_VDDQSNS_R
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.17 mm
B
GND_DDRREG_SGND
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.15 mm
VOLTAGE=0V
A
SYNC_MASTER=J41_MLB
SYNC_DATE=05/21/2013
PAGE TITLE
LPDDR3 Supply
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
74 OF 121
SHEET
53 OF 76
1
A
8
7
6
5
4
3
2
1
D
D
SKIPSEL Strap
VREF2
VREG3
PPBUS_S5_HS_OTHER_ISNS
64 62 41
Auto Skip
(Higher Efficiency)
OOA Auto Skip (Lower Efficiency)
BYPASS=Q7520.1:1.5mm
62 53 36 PP5V_S5
1
C7542
62UF-0.023OHM
1
1
C7540
20%
2
11V
TANT-POLY
CASE-B2S
2
2
11V
TANT-POLY
1
CASE-B2S
62 58 55 54 49 47 35 32 PP5V_S4RS3
64
C7541
1000PF
62UF-0.023OHM
20%
C7570
C7584
1UF
10%
16V
X7R-1
0201
10%
2
1
C7582
62UF-0.023OHM
54 P5VP3V3_VREG3
16V
1
C7500
X5R
11V
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
1
2
11V
TANT-POLY
1
C7581
C7583
1000PF
1UF
20%
2
2
TANT-POLY
CASE-B2S
1UF
402
1
62UF-0.023OHM
20%
CASE-B2S
10%
16V
X5R
10%
16V
X7R-1
0201
2
402
10%
16V
54
2
X5R
P5VP3V3_VREF2
BYPASS=Q7560.1:1.5mm
402
2
1
1/16W
VIN
25V
14
MF-LF
2
X5R
CRITICAL
DIDT=TRUE
1
2
SM
1
2
1
PLACE_NEAR=L7520.2:3mm
603
CASE-B2S
1
150UF-0.035OHM
CRITICAL
1
C7553
6.3V
PLACE_NEAR=L7520.1:3mm
C7571
NOSTUFF
1
2
2
POLY-TANT
2
CASE-B2-SM
1
54
2
2
P5VP3V3_VREG3
P5V_S4RS3_VFB1_XW
1/20W
11
P5V_S4RS3_FUNC
0201
9
P5V_S4RS3_VFB1
10
4
P5VS4RS3_EN_R
5
1
2
1
10%
50V
X7R-CERM
0402
13
22
VREF2
VREG3
25
402
MODE
VFB1
COMP1
18
DIDT=TRUE
P5V_S4RS3_COMP1_R
21
201
X7R-CERM
X7R
2
R7520
2
5%
1/10W
MF-LF
603
0402
R7546
R7539
7.5K
1
353S3905
2
1/20W
1
2
1/20W
201
1%
1
1%
1%
MF
1
MF
201
PLACE_NEAR=U7501.28:1mm
6.65K
1%
201
PLACE_NEAR=L7560.2:3mm
P3V3_S5_COMP2_R
1
4700PF
0201-1
6.3V
X7R
2
201
NP0-C0G
PLACE_NEAR=L7560.2:1.5mm
CRITICAL
150UF-0.018OHM-1.8A
1
C7594
20%
6.3V
XW7562
20%
2
6.3V
TANT
2
TANT
CASE-B2-SM
SM
CASE-B2-SM
1
C7562
2
P3V3_S5_VFB2_XW
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
10%
50V
X7R-CERM
0402
1
DIDT=TRUE
2
R7563
5%
1/20W
MF
201
P3V3_S5_VFB2_R
0201
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
1
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
B
R7560
54
MF
P5VP3V3_VREF2
54
P5VP3V3_VREF2
23.2K
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
201
2
10%
16V
X7R-1
0201
10
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
2
1000PF
TANT
C7593
P3V3_S5_CSP2_R
5%
10V
C7572
2
2
201
22PF
10%
2
2
1
2
1
MF
C7539
2
CRITICAL
2
0201
C7538
6.3V
150UF-0.018OHM-1.8A
1/20W
MF
201
X5R
CASE-B2-SM
0.001UF
R7516
2
MF
1
20%
PLACE_NEAR=L7560.1:3mm
DIDT=TRUE
MF
1/20W
1
C7592
10V
NOSTUFF
2
1/20W
20K
1%
R7506
201
DIDT=TRUE
1%
2
150UF-0.018OHM-1.8A
1
P3V3_S5_REG_SNUB
1.54K
1
1
P5V_S4RS3_CSP1_R
41.2K
SM
PLACE_NEAR=L7560.2:3mm
1
C7590
10UF
20%
XW7561
1
R7562
16V
20
10%
16V
10V
CRITICAL
1
2
603
NOSTUFF
X7R-CERM
P3V3S5_EN_R
2
10%
MF
F=400KHZ
2
2.2
270PF
4700PF
1/20W
2.2UH-20%-9A-0.012OHM
1
SM
10%
P3V3_S5_COMP2
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
1/20W
1/20W
L7560
DIDT=TRUE
XW7560
P3V3_S5_VFB2
15
5%
C7537 1
C7536 1
BG
C7588
1
1%
P3V3_S5_REG_L
8
2
5
2
201
7
152S1798
249K
2
VSW
PIME063T2R2MS-SM
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
1
16
C
6.5A MAX OUTPUT
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
SM
1
TGR
P3V3_S5_RF
1/20W
0
4
0.1UF
3
42
CRITICAL
P3V3_S5_DRVL
THRM_PAD
XW7500
TG
6
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
P3V3_S5_CSN2
EN2
PGOOD2
R7549
3
P3V3_S5_CSP2
17
PP3V3_S5_REG_R
1
Vout = 3.3V
CRITICAL
27
RF
VFB2
COMP2
EN1
PGOOD1
VIN
402
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
R7538
MF
Q3D
2
X5R
P3V3_S5_LL
CSP2
CSN2
GND
1%
CSD58873Q3D
1
0.1UF
P3V3_S5_DRVH
GATE_NODE=TRUE
2
4.22K
1
24
1
2
R7556
C7564
MF-LF
P3V3_S5_VBST
DRVL2
20K
1/20W
MF
201
P5V_S4RS3_VFB1_R
DRVH2
CSP1
CSN1
R7537
1%
MF
201
2
26
1
7.5K
1/20W
Q7560
R7564
25V
37 38 59
DIDT=TRUE
DRVL1
NO STUFF
R7536
1%
C7522
10
B
8
P5V_S4RS3_COMP1
NOSTUFF
0.001UF
1
VBST2
SW1
1.33K
1
IN
GATE_NODE=TRUE
7
R7547
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
30
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
0402
P5V_S4RS3_REG_SNUB
DIDT=TRUE
5%
1/20W
MF
201
2
MF
16V
X7R-CERM
PLACE_NEAR=L7520.1:1.5mm
R7523
0
1
5%
SM
SMC_PM_G2_EN
SWITCH_NODE=TRUE
P5V_S4RS3_CSN1
10%
5%
1/10W
MF-LF
603
X5R
603
R7548
R7522
XW7522
10%
16V
X7R-1
0201
12
GATE_NODE=TRUE
NO STUFF
0.1UF
1
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
10V
1/16W
EN
SWITCH_NODE=TRUE
DIDT=TRUE
C7518
2.2
1000PF
20%
32
P5V_S4RS3_CSP1
PLACE_NEAR=L7520.1:3mm
X5R
ELEC
XW7521
SM
P3V3_S5_VBST_R
20%
1
28
10V
2
PGND
CASE-B2-SM
20%
DIDT=TRUE
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
5
9
POLY-TANT
10UF
20%
6.3V
BG
10UF
402
10%
SW2
GATE_NODE=TRUE
P5V_S4RS3_LL
2
XW7520
20%
62UF
DIDT=TRUE
P5V_S4RS3_DRVL
2
X5R-CERM
402
0
U7501
DRVH1
1
P5V_S4RS3_DRVH
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
CRITICAL
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
1
C7550
2
CERM
5%
VBST1
31
P5V_S4RS3_VBST
4
10V
CRITICAL
DIDT=TRUE
152S1798
1
C7552
1
C7554
TGR
VSW
8
2
C7505
20%
QFN
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
PIME063T2R2MS-SM
150UF-0.035OHM
CRITICAL
7
2
SKIPSEL1
SKIPSEL2
OCSEL
2
3
6
2.2UH-20%-9A-0.012OHM
CRITICAL
TG
P5V_S4RS3_REG_L
L7520
7.2A MAX OUTPUT
6.3V
402
402
Vout = 5.0V
1
2.2UF
10V
2
6
19
10%
58 55 54 49 47 35 32 PP5V_S4RS3
64 62
VREG5
0201
P5VP3V3_SKIPSEL
5%
C
0201
0
0.1UF
1
2
C7503
10%
PGND
2
1
MF
1
0.22UF
9
R7545
1/20W
MF
VIN
1/20W
C7524
Q3D
5%
33
1
5%
TPS51980A
Q7520
CSD58873Q3D
F=400KHZ
0
C7501
R7501
0
V5SW
R7500
29
1
2
1
P5V_S4RS3_VBST_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
23
NOSTUFF
1%
1/20W
MF
201
59
OUT
OUT
2
P5VS4RS3_PGOOD
59 37
1
S5_PWRGD
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
R7521
10K
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
1
1%
R7561
1/20W
10K
MF
GND_P5VP3V3_SGND
201
2
1%
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
1/20W
MF
VOLTAGE=0V
201
2
PLACE_NEAR=U7501.4:2mm
1
PLACE_NEAR=U7501.21:2mm
1
R7551
0
2
59
IN
P5VS4RS3_EN
R7552
0
5%
1/20W
MF
0201
2
59
IN
5%
1/20W
MF
0201
S5_PWR_EN
Power
A
SYNC_MASTER=J41_MLB
SYNC_DATE=09/17/2012
PAGE TITLE
5V S4RS3 / 3.3V S5 Power Supply
DRAWING NUMBER
Apple Inc.
& lt; SCH_NUM & gt;
REVISION
R
& lt; E4LABEL & gt;
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
BRANCH
& lt; BRANCH & gt;
PAGE
75 OF 121
SHEET
54 OF 76
1
SIZE
D
A
8
7
6
5
4
3
2
1
D
D
1.05V S0 Regulator
PPBUS_S5_HS_COMPUTING_ISNS
64 62 53 52 51 41
C7620
55 51 42 38 17 16 15 11 8 6
64 62 59 58
1
C7621
62UF-0.023OHM
PP1V05_S0
1
C7622
5%
25V
CERM
0402
20%
2
11V
TANT-POLY
11V
TANT-POLY
CASE-B2S
2
CASE-B2S
P1V05S0_BOOT_RC
64 62 58 54 49 47 35 32
PP5V_S4RS3
C7601
1
10UF
C
C7600
10UF
20%
10V
X5R
603
2
1
C7619
C7624
1UF
62UF-0.023OHM
20%
2
11V
TANT-POLY
CASE-B2S
10%
16V
X5R
402
C7630
0.1UF
20%
10V
X5R
603
1
1
2
PLACE_NEAR=Q7630.8:1.5mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
1
1
1000PF
62UF-0.023OHM
20%
10%
16V
1
2
2
R7630
C
X7R-CERM
0402
2.2
BYPASS=U7600.2:1mm
CRITICAL
5%
1/10W
2
Q7630
MF-LF
603
2
FDPC1012S
2
BYPASS=U7600.12:1mm
LLP
VLDOIN
16
6
TPS51916
1
10%
16V
X7R-CERM
0402
BYPASS=U7600.6:1mm
R7611
35.7K
2
2
P1V05S0_FB
8
REFIN
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
P1V05S0_MODE
19
P1V05S0_TRIP
1%
1/20W
MF
201
18
MODE
TRIP
VTTREF
1%
1/20W
MF
201
2
PLACE_NEAR=U7600.8:5mm
C7616
0.01UF
2
1
10%
16V
X7R-CERM
0402
R7610
1
1K
BYPASS=U7600.8:1mm
2
1%
1/20W
MF
201
R7613
1
47.5K
2
1%
1/20W
MF
201
PLACE_NEAR=U7600.19:3mm
11
P1V05S0_DRVH_R
5%
1/16W
MF-LF
L7630
3
SW
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE
9
P1V05S0_VTT
0.003
1
1%
1w
CYN
0612-SHORT
1.0UH-20%-11A-0.011OHM
2
P1V05S0_LL
20
3
1
4
2 PP1V05_S0_REG_R
FDSD0630-SM
NOSTUFF
1
CRITICAL
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
7
LSG
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE
2
3
4
Vout = 1.05V
CRITICAL
R7632
C7649
5
2
5%
1/10W
MF-LF
603
P1V05S0_PGOOD
OUT
59
1
2.0V
2
PLACE_NEAR=U7600.18:3mm
C7650
f = 300 kHz
2
POLY-TANT
1000PF
74 42
OUT
5%
25V
CERM
0402
ISNS_1V05_S0_P
NOSTUFF
C7632
1
74 42
OUT
CASE-B2-SM1
2
CRITICAL
ISNS_1V05_S0_N
1
0.001UF
1%
1/20W
MF
201
21A Max Output
20%
C7623
P1V05S0_LL_SNUB
P1V05S0_VTTREF
1
330UF
PLACE_NEAR=L7630.2:1.5mm
DIDT=TRUE
R7614
64
42 51 55
6 8 11 15
16 17 38
58 59 62
PP1V05_S0
1
2.2
1
17.4K
2
HSG
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE
402
XW7600
B
2
VTT THRM
GND PAD
4
1
49.9K
10
R7612
7
PGND GND
1
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE
1
P1V05S0_DRVL
PLACE_NEAR=U7600.8:5mm
OMIT
R7640
0
P1V05S0_DRVH
13
21
1
0.1UF
DRVL
CRITICAL
PGOOD
VDDQSNS
VTT
VTTSNS
9
R7631
14
QFN
VREF
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
C7615
15
GND
GND
GND
59 P1V05S0_EN
P1V05_S0_VREF
VBST
DRVH
SW
U7600
V+
V+
10%
50V
X7R-CERM
0402
5
S3
S5
8
6
V5IN
17
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
10
12
Scrub S3 & S5 pins connections!
P1V05S3_EN
P1V05S0_VBST
C7648
330UF
20%
2
2
PLACE_NEAR=C7648.1:1mm
2
XW7610
SM
2.0V
POLY-TANT
CASE-B2-SM1
1
1
0.22UF
SM
1
10%
10V
CERM
402
B
2
P1V05S0_AGND
PLACE_NEAR=U7600.21:1mm
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
R7641
10
P1V05S0_VDDQSNS
1
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.17 mm
P1V05S0_VDDQSNS_R
2
5%
1/20W
MF
201
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.17 mm
A
SYNC_MASTER=J41_MLB
SYNC_DATE=05/21/2013
PAGE TITLE
1.05V S0 Power Supply
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
76 OF 121
SHEET
55 OF 76
1
A
8
7
6
5
4
3
2
1
PPBUS S0 LCDBkLT FET
MOSFET
CRITICAL
FDC638APZ
CHANNEL
P-TYPE
RDS(ON)
43 mOhm @4.5V
LOADING
0.65 A (EDP)
*C7797 AND C7799 SHOULD BE PLACED IN T-BONE FOR ACOUSTICS
Q7706
*PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.
FDC638APZ_SBMS001
SSOT6-HF
6
THERE IS A SENSE RESISTOR BETWEEN
PLACE_NEAR=L7701.2:3mm
1
PLACE_SIDE=BOTTOM
C7782
R7788
10%
16V
X7R-CERM
0402
1%
1/20W
MF
201
56 41
1
PPVIN_S0SW_LCDBKLT
C7712
1
1
10UF
10%
25V
X5R
805
0.1UF
2
2
PLACE_NEAR=L7701.1:3mm
A
LCDBKLT_BOOST
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.150 MM
VOLTAGE=50V
SWITCH_NODE=TRUE
DIDT=TRUE
C7713
K
CRITICAL
RB160M-60G
1
C7796
1
220PF
10%
25V
X5R
402
2
C7797
CRITICAL
1
10UF
10%
50V
X7R-CERM
0402
2
10%
50V
X5R
1210-1
C7799
10UF
2
10%
50V
X5R
1210-1
PLACE_NEAR=L7701.1:3mm
R7789
PLACE_NEAR=U7701.A5:3mm
PLACE_NEAR=D7701.2:5mm
PLACE_NEAR=D7701.2:3mm
147K
2
D
60 62 64
SOD-123
2
PIMB053T-SM
CRITICAL
2
PPHV_S0SW_LCDBKLT
D7701
15UH-2.8A
1
LCDBKLT_EN_DIV_L
1
CRITICAL
L7701
ON THE SENSOR PAGE
0.1UF
301K
2
CRITICAL
AND PPBUS_SW_BKL
1
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
603-HF
PPBUS_SW_LCDBKLT_PWR
2
PPVIN_S0SW_LCDBKLTFET
3
D
2
4
1
PPBUS_G3H
41
5
3AMP-32V-467
64 62 50 49 42 41 27
*LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT
PPVIN_S0SW_LCDBKLT_FET
F7700
1%
1/20W
MF
201
61 59 58 56 52 51 45 32 17 16
64 62
PP5V_S0
XW7720
LCDBKLT_EN_L
SM
Q7707
DMN5L06VK-7
PPVOUT_SW_LCDBKLT_FB
D 3
BYPASS=U7701.D1:5mm
BYPASS=U7701.D1:3mm
C7710
SOT563
VER 3
5
13
IN
G
EDP_BKLT_EN
1
1
2
2
1UF
10%
25V
X5R
603-1
S 4
74 65 64 62
36 30 26 18 17 15 13 12 11 8
61 59 45 44 43 42 41 40 39 38
VOLTAGE=50V
MIN_LINE_WIDTH=0.1 MM
MIN_NECK_WIDTH=0.1 MM
C7714
1
2
PLACE_NEAR=C7797.1:5mm
0.01UF
10%
10V
X5R-CERM
0201
10.2 ohm resistors for current
PP3V3_S0
LCDBKLT_DISABLE
measurement on LED strings.
BYPASS=U7701.C4:4mm
Q7707
C7711
D 6
DMN5L06VK-7
PART NUMBER
1
10%
6.3V
CERM-X5R
0201
G
R7731
1
1%
1/20W
MF
201
EDP_BKLT_PWM
1
33
TP7701
R7715
2
1
C1
D1
SDA
A4
PWM
EN
C3
A3
TP-P6
PLACE_SIDE=BOTTOM
100K
2
TP
D4
BKL_FAULT
2
SCLK
1%
1/20W
MF
201
1
I_LED=17.1mA
C7704
33PF
2
1
5%
25V
NP0-C0G
0201
10K
2
see spec for others
R7714 1
R7755
1
21.5K
5%
1/20W
MF
201
1%
1/20W
MF
201
D5
OUT3
OUT4
C5
OUT5
OUT6
FAULT
E5
OUT2
E2
E3
E1
BKL_ISEN1
BKL_ISEN2
BKL_ISEN3
BKL_ISEN4
BKL_ISEN5
BKL_ISEN6
2
I_LED=369/Riset
2
LED_RETURN_1
5%
1/16W
MF-LF
402
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
0
1
2
LED_RETURN_2
5%
1/16W
MF-LF 402
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
OUT
60 64
OUT
60 64
OUT
60 64
OUT
60 64
OUT
60 64
OUT
60 64
BKLT:PROD
R7719
0
1
2
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
PLACE_NEAR=U7701.C5:10mm
LED_RETURN_3
5%
1/16W
MF-LF
402
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
BKLT:PROD
R7720
0
1
2
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
PLACE_NEAR=U7701.E3:10mm
LED_RETURN_4
5%
1/16W
MF-LF 402
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
BKLT:PROD
R7721
0
1
2
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
PLACE_NEAR=U7701.E2:10mm
LED_RETURN_5
5%
1/16W
MF-LF
402
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
BKLT:PROD
R7722
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
PLACE_NEAR=U7701.E1:10mm
90.9K
2
1
BKLT:PROD
R7716
1%
1/20W
MF
201
0
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
PLACE_NEAR=U7701.E5:10mm
R7718
OUT1
0
1
2
LED_RETURN_6
5%
1/16W
MF-LF 402
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
XW7710
SM
GND_BKL_SGND
B
A5
R7717
B2
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
PLACE_NEAR=U7701.D5:10mm
CRITICAL
Fpwm=9.62kHz
5%
1/20W
MF
201
FB
BKLT:PROD
GND_SW
GND_SW
PPVIN_S0SW_LCDBKLT
R7704
IN
BKLT:ENG
A2
1
D3
BKL_PWM
BKL_EN
2
FSET
GND_L
0
5%
1/20W
MF
0201
ISET
B4
A1
1
200K
13
R7720,R7721,R7722
C
SW_0
SW_1
E4
56 41
RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM
B1
GND_S
SMBUS_PCH_DATA
Addr: 0x58(Wr)/0x59(Rd)
2
5%
1/20W
MF
0201
R7757
BI
0
1
B3
BKL_SCL
BKL_SDA
R7753
SMBUS_PCH_CLK
FILTER
BKL_FSET
5%
1/20W
MF
201
C2
BKL_ISET
2
VSYNC
BKL_FLTR
10K
D2
LP8550
BKL_VSYNC_R
R7741
69 40 19 16 14
BKLT:ENG
3
25-BUMP-MICRO
1
IN
R7717,R7718,R7719
U7701
BKLT_PLT_RST_L
69 40 19 16 14
BOM OPTION
RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM
VIN
VDDIO VLDO
S 1
B5
IN
CRITICAL
3
103S0198
(GND_BKL_SGND)
18
REFERENCE DES
103S0198
2
C4
VER 3
2
DESCRIPTION
0.1UF
SOT563
C
QTY
1
2
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V
B
(EEPROM should set EN_I_RES=1)
PLACEMENT_NOTE=Keep away from noise nodes(E4, A1, A2, B1, B2 pins)
Keyboard Backlight Driver & Detection
CRITICAL
L7750
PP5V_S0
61 59 58 56 52 51 45 32 17 16
64 62
Keyboard Backlight Connector
10UH-0.58A-0.35OHM
1
2
BYPASS=U7750.1:2:2 MM
1098AS-SM
C7750
1
10%
10V
X5R
402-1
2
1UF
KBDLED_SW
CRITICAL
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.225 MM
SWITCH_NODE=TRUE
DIDT=TRUE
J7715
FF14A-4C-R11DL-B-3H
VIN
2
NC
SPN035007G
1
MLF
3
SMC_SYS_KBDLED
BI
2
EN
SW
7
3
CRITICAL
64
1
A
6
KBDLED_FB
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=40V
NC
5
FB
OUT
KBDLED_ANODE
4
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=40V
NC
1
R7700
GND
4
5%
1/16W
MF-LF
402
8
4.7
2
1 64
THRM
C7755
1
NC
C7756
PAD
0.22UF
10%
50V
X5R-CERM
0603-1
10%
50V
X5R-CERM
0603-1
6
0.22UF
9
37
F-RT-SM
5
U7750
2
2
518S0793
SYNC_MASTER=J43_MLB
SYNC_DATE=09/13/2012
PAGE TITLE
LCD/KBD Backlight Driver
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
77 OF 121
SHEET
56 OF 76
1
A
8
7
6
5
4
3
2
1
1.05V SUS LDO
Cougar Point requires JTAG pull-ups to be powered at 1.05V when SUS suspend well is active.
Pull-ups (3) must be 51 ohms to support XDP (not required in production).
70mA is required to support pull-ups.
D
Alternative is strong voltage
D
dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.
CRITICAL
XDP
U7840
TPS720105
64 62 59 58 46 18 14 11 8
PP3V3_SUS
SON
4
PP1V05_SUS
6
IN
OUT
EN
NC
2
XDP
1.8V S3 REGULATOR
C7840
1
1UF
Vout = 1.05V
1
3
59 58 57 42
16 15 13 11 8 PP3V3_S5
34 29 28 18 17
74 64 62 60
GND
5
Max Current = 0.35A
NC
XDP
THRM
PAD
1
C7824
1
C7820
1000PF
10%
16V
X7R-1
0201
CERM
2
X5R
402
1
1
20%
6.3V
X5R-CERM-1
10%
6.3V
2
402
22UF
2
C7841
2.2UF
7
10%
6.3V
CRITICAL
16 62
BIAS
OMIT
152S1870
VIN
2
U7820
603
R7829
L7820
0.002
2.2UH-20%-2.0A-0.108OHM
ISL8009B
1%
1W
MF
0612-SHORT
2520-SM
DFN
59
P1V8S3_EN
2
EN
LX
8
IN
59
P1V8S3_PGOOD
3
POR
VFB
6
OUT
4
SKIP
RSI
5
CRITICAL
1
P1V8S3_SW
SWITCH_NODE=TRUE
DIDT=TRUE
2
1
CRITICAL
1
GND
7
C
C7823
1
THRM_PAD
R7820
9
1
113K
2
C7825
22UF
5%
25V
C0G
0201
20%
6.3V
2
4
NC
CRITICAL
C7821
47PF
2
3
PP1V8_S3_REG_R
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V
CRITICAL
P1V8S3_FB
20%
6.3V
603
X5R-CERM-1
20 21 22 23 57 62
NC
1
Vout = 1.794V
Max Current = 1.8A
Freq = 1 MHz
22UF
X5R-CERM-1
PP1V8_S3
2
C
603
1%
1/20W
MF
201
2
& lt; Ra & gt;
R7821
CRITICAL
1
C7822
90.9K
1%
1/20W
MF
201
1
22UF
20%
6.3V
X5R-CERM-1
2
2
603
& lt; Rb & gt;
Vout = 0.8V * (1 + Ra / Rb)
B
B
1.5V S0 LDO
CRITICAL
U7870
TPS72015
SON
PP1V5_S0
34 29 28 18 17 16 15 13 11 8 PP3V3_S5
74 64 62 60 59 58 57 42
4
6
IN
OUT
1
3
EN
NC
2
62 57 23 22 21 20
IN
PP1V8_S3
59 28
IN
PM_SLP_S3_BUF_L
C7870
1
C7871
1UF
A
10%
6.3V
1
CERM
402
2
CERM
GND
5
1UF
10%
6.3V
2
402
8 58 59 62 64
BIAS
THRM
PAD
Vout = 1.5V
Max Current = 0.02A
NC
1
7
C7872
2.2UF
2
10%
6.3V
X5R
402
SYNC_MASTER=J43_MLB
SYNC_DATE=10/04/2012
PAGE TITLE
BYPASS=U7870.4:1mm
Misc Power Supplies
BYPASS=U7870.6:1mm
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
78 OF 121
SHEET
57 OF 76
1
A
8
7
1.5V S0 Audio Switch
6
5
4
3
2
1
Loading specs per J41/43_PowerBudget_Riviera_rev0.99e
NOSTUFF
R8042
PP1V5_S0
0
1
59 57 8
64 62
R8040
0
1
5%
1/20W
MF
0201
NOSTUFF
PP1V5_S0SW_AUDIO_HDA
R8041
2
PP1V5_S0SW_AUDIO_HDA
2
5%
1/20W
MF
0201
OMIT
R8020
0.002
PP1V5_S0SW_AUDIO
U8040
5%
1/20W
MF
201 2
TPS22924
D
VIN
B1
C2
A1
VIN
B2
U8040
ON
59
P3V3SUS_EN
IN
C2
ON
19.6 mOhm Typ
21.8 mOhm Max
Current
1
8 11 14 18 46 57 59 62 64
D
NC
U8020
C1
R(on)
@ 1.8V
C1
TPS22924C
Load Switch
EDP: 112mA
NC
4
Part
2A Max
TPS22924C
Type
Load Switch
R(on)
@ 2.5V
18.5 mOhm Typ
25.8 mOhm Max
Current
2A Max
1.0UF
1.0UF
20%
6.3V
X5R
0201-1
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
GND
C8020
Part
Type
1
PP3V3_SUS_FET_R
B1
VOUT
PP3V3_SUS
3
CSP
A2
EDP: 35mA
GND
C8040
1%
1W
MF
0612-SHORT
1
2
TPS22924
PP3V3_S5
CRITICAL
CRITICAL
P1V5S0SW_AUDIO_EN
34 29 28 18 17 16 15 13 11 8
74 64 62 60 59 58 57 42
58 61 65
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE
A1
VOUT
U8020
58 61 65
PP1V5_S0SW_AUDIO
CSP
A2
B2
IN
3.3V SUS Switch
1
10K
59
8 11 17 58
8 11 17 58
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE
2
20%
6.3V
X5R
0201-1
2
1.05V PCH HSIO Switch
3.3V SSD Switch
3.3V S4 Switch
PP5V_S0
61 59 58 56 52 51 45 32 17 16
64 62
OMIT
0.002
U8000
A1
VIN
VOUT
B1
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
S4_PWR_EN
IN
C2
25 26 27 29 33 36 38 39 62 64
1
20%
6.3V
X5R
0201-1
Type
Load Switch
P3V3S0SW_SSD_FET_RAMP
2
R(on)
@ 2.5V
Current
C8071
18.5 mOhm Typ
25.8 mOhm Max
2A Max
1 30 15
64 59
IN
7
10%
6.3V
CERM-X5R
0201
2
58 15
IN
PCH_HSIO_PWR_EN
9
ON
ON
4700PF
10%
10V
X7R
201
3
S
5
SLG5AP1453V
Type
OMIT
Load Switch
R(on)
@ 4V Vgs
9.8 mOhm Typ
TBD mOhm Max
Current
C
SLG5AP1417V
6A Max
Load Switch
R(on)
@ 25C
2
5%
1/20W
MF
0201
R8011
U8005
HSIO has turn-on requirement of
& lt; 0.1V/uS ramp rate and
& lt; 65uS from EN to 95% (1.05V)
Part
7.8 mOhm Typ
8.5 mOhm Max
5.3A Max
0
1
8 11 58 62
Type
U8070
NOSTUFF
P3V3S0_EN
EDP: 1.84A
EDP: 5A
Sense R on sensor page
Current
IN
7
6 8 11 15 16 17 38 42 51 55
58 59 62 64
41
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
R8070
59 58
PP1V05_S0SW_PCH_HSIO
Part
PP3V3_S0SW_SSD_FET_R
GND
2
PP1V05_S0
5
GND
D
CRITICAL
3
S
CRITICAL
2
D
TDFN
0.1UF
TDFN
CAP
2
SSD_PWR_EN
D
S
C8070
U8070
TPS22924C
3.3V S3 Switch
U8005
SLG5AP1453V
Part
1.0UF
C
VDD
2
SLG5AP1471V
1
NC
U8000
GND
C8000
10%
10V
X5R
402
VDD
ON
C1
59 28 18
EDP: 119mA
4
NC
CRITICAL
1
1UF
8
B2
PP3V3_S4_FET_R
PP3V3_S4
3
CSP
A2
C8005
PP3V3_S5
1
PP3V3_S5
34 29 28 18 17 16 15 13 11 8
74 64 62 60 59 58 57 42
1%
1W
MF
0612-SHORT
1
2
TPS22924
8
74 64
57 42 34 29
15 13 11 8
28 18 17 16
62 60 59 58
1
R8000
0.002
74 64
57 42 34 29
15 13 11 8
28 18 17 16
62 60 59 58
1%
1W
MF
0612-SHORT
1
2
TPS22924
PP3V3_S5
PP3V3_S3_FET_R
CSP
A2
B2
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
A1
VIN
VOUT
B1
PP3V3_S3
3
U8010
EDP: 1.02A
4
NC
15 18 19 33 36 40 41 62 64
NOSTUFF
NC
P3V3S3_EN
PQFN3.3X3.3
ON
U8010
GND
3
IN
IRFHM830DPBF
Type
Load Switch
R(on)
@ 2.5V
18.5 mOhm Typ
25.8 mOhm Max
NOSTUFF
PP5V_S0
61 59 58 56 52 51 45 32 17 16
64 62
SOT-963
N-CHANNEL
5%
1/20W
MF
201
6
Sense R on sensor page
U8030
TPS22924
PP3V3_S5
PP3V3_S0_FET_R
CSP
5%
1/20W
MF
201
G
2
A2
B2
A1
VIN
VOUT
B1
EDP: 1A
CRITICAL
59 58
IN
P3V3S0_EN
C2
2
Part
NOSTUFF
D
18.5 mOhm Typ
25.8 mOhm Max
Current
C1
R8062 1
G
S 1
G
5
S
PCH_HSIO_PWR_EN
5%
1/20W
MF
201
C8060
5
1
G
S 4
0.01UF
10%
10V
X5R-CERM
0201
2
2
4
HSIOFET_DRV_H
Load Switch
R(on)
@ 2.5V
1
NOSTUFF
TPS22924C
Type
GND
C8030
IN
VER 3
3
P-CHANNEL
ON
DMN5L06VK-7
SOT563
2
330
58 15
D 3
HSIOFET_EN
VER 3
U8030
B
NOSTUFF
Q8062
1
D 6
41
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
5%
1/16W
MF-LF
402
330
DMN5L06VK-7
SOT563
58
18
8
15
34
62
R8060
HSIOFET_DISCHARGE
R8061 1
S
59
28
11
16
42
64
2
NOSTUFF
D
NOSTUFF
Q8062
HSIOFET_DRV_L
2
HSIOFET_EN_L
8 11 58 62
EDP: 1.84A
300
NTUD3169CZ
1
10K
2A Max
B
3.3V S0 Switch
1
Q8061
NOSTUFF
R8063
60
29
13
17
57
74
PP1V05_S0SW_PCH_HSIO
NOSTUFF
2
Current
PP1V05_S0
1
55 51 42 38 17 16 15 11 8 6
64 62 59 58
S
TPS22924C
G
20%
6.3V
X5R
0201-1
4
Part
1.0UF
D
1
5
C8010
C1
2
59
C2
CRITICAL
Q8060
CRITICAL
2A Max
(HSIOFET_EN_L)
1.0UF
20%
6.3V
X5R
0201-1
2
5V S0 Switch
64 62 55 54 49 47 35 32
PP5V_S4RS3
3.3V Sensor Switch
1
1
PP3V3_S4SW_SNS_FET_R
CSP
A2
B2
A1
VIN
VOUT
B1
1
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm
5%
1/16W
MF-LF
402
2
IN
SMC_SENSOR_PWR_EN
C2
PP3V3_S4SW_SNS
41 42 43 62
C8081
1
10%
10V
X7R
201
U8050
GND
C8050
P5VS0_FET_RAMP
7
CAP
2
ON
EDP: 50mA
1
59
IN
P5VS0_EN
4700PF
ON
OMIT
R8081
SLG5AP1443V
CRITICAL
42 39 37
10%
16V
X5R-CERM
0201
TDFN
CRITICAL
GND
0.002
D
S
5
1%
1W
MF
0612-SHORT
1
2
PP5V_S0_FET_R
VOLTAGE=5V
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
PP5V_S0
3
3
EDP: 300mA?
NC
4
SYNC_MASTER=J41_MLB
2
SYNC_DATE=02/06/2013
PAGE TITLE
Power FETs
16 17 32 45 51 52 56 58 59 61
62 64
DRAWING NUMBER
NC
U8080
8
TPS22924
PP3V3_S5
8
13
17
29
57
60
74
0
2
U8080
R8050
U8050
C1
A
64
59
42
28
16
11
15
18
34
58
62
C8080
0.1UF
VDD
Apple Inc.
Part
TPS22924C
Part
SLG5AP1438V
Type
Load Switch
Type
Load Switch
R(on)
@ 2.5V
18.5 mOhm Typ
25.8 mOhm Max
R(on)
15 mOhm Typ
17 mOhm Max
Current
2A Max
Current
R
& lt; E4LABEL & gt;
1.0UF
20%
6.3V
X5R
0201-1
8
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
2
7
6
5
4
2.5A
3
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; BRANCH & gt;
PAGE
80 OF 121
SHEET
58 OF 76
1
A
8
7
6
5
4
3
2
S5 Enables
S3 Enables
PLACE_NEAR=U7501.21:7mm
54 38 37
59
OUT
SMC_PM_G2_EN
54 38 37
59
IN
SMC_PM_G2_EN
59 37 36 29 18 13
R8140
100
1
MAKE_BASE=TRUE
S5_PWR_EN
S5_PWR_EN
OUT
MAKE_BASE=TRUE
5%
1/20W
MF
201
C8170
10%
6.3V
CERM-X5R
0201
0.47UF
10%
6.3V
CERM-X5R
402
0
5%
1/20W
MF
201
5%
1/20W
MF
0201
IN
S5 Power Good
IN
PM_SLP_S5_L
2
SMC_S4_WAKESRC_EN
59 53
S4_PWR_EN
OUT
MAKE_BASE=TRUE
OUT
18 28 58 59
C8111
1
3
R8115
1
2
USB_PWR:STBY
1
5%
1/20W
MF
0201
37 54 59
2
R8177
S4_PWR_EN
59 58 28 18
1
0
SSD_PWR_EN
65 61 59 35
IN
OUT
2
PM_SLP_S4_L
1
0
A NO STUFF
1
D8175
0201
2
K
PLACE_NEAR=U7820.2:6mm
10%
6.3V
CERM-X5R
402
PLACE_NEAR=U8010.D2:6mm
Mobile System Power State Table
SMC_PM_G2_ENABLE
SMC_S4_WAKESRC_EN
PM_SUS_EN
PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L
X
1
1
1
1
1
1
Sleep (S3AC)
1
1
1
1
1
1
0
C8114
Sleep (S3)
0
1
1
1
1
1
0
Deep Sleep (S4AC)
1
1
1
0
0
0
0
USB_PWR_EN
35 59 61 65
OUT
10%
6.3V
CERM-X5R
402
NO STUFF
2
R8176
Deep Sleep (S4)
0
1
1
0
0
0
0
Deep Sleep (S5AC)
1
1
0
0
0
0
0
Deep Sleep (S5)
0
1
0
0
0
0
0
Battery Off (G3HotAC)
toggle 3Hz
0
0
0
0
0
0
Battery Off (G3Hot)
2
R8175
0
RB521ES-30
5%
1/20W
MF
0201
0.47UF
2
Run (S0)
PLACE_NEAR=U7501.4:15mm
59 37 36 29 18 13
C8112
SMC_ADAPTER_EN
PLACE_NEAR=U4600.4:6mm
NO STUFF
R8179
D
State
USB_PWR:S3
MAKE_BASE=TRUE
2
5%
1/20W
MF
201
USB_PWR_EN
1
15 30 58 59 64
53 59
0.47UF
2
5%
1/20W
MF
0201
SSD_PWR_EN
OUT
100
5%
1/20W
MF
201
PLACE_NEAR=U4600.4:6mm
P5VS4RS3_EN_RC
64 59 58 30 15
10%
6.3V
CERM-X5R
402
PLACE_NEAR=U7400.16:6mm
MAKE_BASE=TRUE
SSD Enable
57 59
DDRREG_EN
58 59
R8117
100
USB_PWR:STBY
MAKE_BASE=TRUE
USB_PWR:S3
1
R8114
1
0.47UF
20%
10V
CERM
402
2
100K
OUT
OUT
NO STUFF
C8116
1
0.1UF
SMC-- & gt; PM_DSW_PWRGD
OUT
P1V8S3_EN
MAKE_BASE=TRUE
NO STUFF
S4_PWR_EN
NC
S5_PWRGD-- & gt; SMC
P3V3S3_EN
DDRREG_EN
18 28 58 59
0
S5_PWRGD
P1V8S3_EN
MAKE_BASE=TRUE
1
2
P3V3S3_EN
MAKE_BASE=TRUE
S4_PWR_EN
NC
S5_PWRGD
PLACE_NEAR=U8010.D2:6mm
SOT891
1
PLACE_NEAR=U7501.20:7mm
59 54 37
5%
1/20W
MF
0201
59 57
U8170
5
5%
1/20W
MF
201
PLACE_NEAR=U7820.2:6mm
74LVC1G32
PP3V42_G3H
R8141
2
59 58
4
38 37
R8112
0
NOSTUFF
6
37 13
2
PLACE_NEAR=U7400.16:6mm
2
1
R8116
20K
2
BYPASS=U8170.6:2.3mm
PLACE_NEAR=U7501.21:7mm
1
R8111
1
0.1UF
C8142
D
1
Standby Enables
NOSTUFF
54 59
NOSTUFF
1
PM_SLP_S4_L
IN
PP3V3_S5
34 29 28 18 17 16 15 13 11 8
74 64 62 60 59 58 57 42
2 59 54
2
61 59 50 49
36 35 30 17
46 40 38 37
65 64 62
1
1
0
0
0
0
0
0
PLACE_NEAR=U4600.4:6mm
5%
1/20W
MF
0201
PLACE_NEAR=U7501.4:15mm
240
P5VS4RS3_EN_D
1
5V needs to be held up
so 1.05V can fall after 1.5V
2
P5VS4RS3_EN
5%
1/20W
MF
201
54
OUT
NO STUFF
1
PLACE_NEAR=U7501.4:15mm
C
C8175
C
2.2UF
10%
6.3V
X5R
402
2
34 29 28 18 17 16 15 13 11 8
74 64 62 60 59 58 57 42
PP3V3_S5
PLACE_NEAR=U7501.4:15mm
BYPASS=U8180.6:3mm
1
C8180
0.1UF
2
R8178
S0 Rail PGOOD (BJT Version)
PP5V_S0
R8156
1K
1
2
C8159
5%
1/20W
MF
201
1
1UF
1%
1/20W
MF
201
10%
10V
X5R
402
2
ALL_SYS_PWRGD
NC
1K
1
65 61 13
1
0201
8
K
2
OUT
K
PLACE_NEAR=U7600.16:6mm
2
NO STUFF
1
820
2
PLACE_NEAR=U7600.16:6mm
R8138
D8184
0201
PLACE_NEAR=U8030.2:6mm
P3V3S0_EN_D
K
2
2
PLACE_NEAR=U8030.2:6mm
A
P5VS0_EN
OUT
58 59
P3V3S0_EN
OUT
58 59
P1V05S0_EN
OUT
55 59
PLACE_NEAR=U8080.2:6mm
59 58
2
P5VS0_EN
MAKE_BASE=TRUE
59 58
RB521ES-30
P3V3S0_EN
MAKE_BASE=TRUE
PLACE_NEAR=U8030.2:6mm
59 55
58
P1V05S0_EN
MAKE_BASE=TRUE
R8159
1
2
C8146
0.1UF
C8185
1
C8186
20%
10V
CERM
402
1
0.1UF
10%
10V
CERM
402
2
PLACE_NEAR=U7600.16:6mm
C8187
0.68UF
2
PLACE_NEAR=U8030.2:6mm
10%
6.3V
CERM
402
PLACE_NEAR=U8080.2:6mm
B
10%
25V
X5R
402
3.3V SUS Detect
34 29 28 18 17 16 15 13 11 8
74 64 62 60 59 58 57 42
3
NO STUFF
0.22UF
PLACE_NEAR=U8040.C2:7mm
PP3V3_S5
S0PGD_BJT_GND_R
VMON_Q4_BASE
5%
1/20W
MF
201
Vbe 0.7V max @ 2mA
Vce(sat) 0.1V max @ 1mA
Q1 Vth 0.7~1V @Id 250uA
59 57 28
CRITICAL
1
R8167
10K
64 62 59 58 57 46 18 14 11 8
54
PP1V05_S0
S0PGOOD_ISL
C8160
1
IN
P5VS4RS3_PGOOD
10%
6.3V
CERM-X5R
0201
R8160
R8170
R8172
6.04K
5V Divider:
3.19V @ 4.5Vmin
2
15K
1
1%
1/20W
MF
201
2
2
U8160
1
R8161
S0PGOOD_ISL
1
R8171
2
3
5
6
IN
1
V2MON
CRITICAL
V3MON
V4MON
GND
R8173
15K
15K
1%
1/20W
MF
201
1%
1/20W
MF
201
1
DDRREG_PGOOD
(IPU)
MR*
RST*
1
8
1
S0PGOOD_ISL
NC
R8162
3
2
QFN
CT
GND
C8131
6
OUT
MR*
4
5%
1/20W
MF
201
13 64
VFRQ Low: Fix Frequency
TP_SUS_PGOOD_MR_L
2
ALL_SYS_PWRGD_R
1
2
CHGR_VFRQ
Q8131
S
OUT
50
3
2
DFN1006H4-3
SYM_VER_2
100
100
G
PM_SLP_S3_R_L
SUS Enables
2
5%
1/20W
MF
201
59 42 13
IN
PM_SLP_SUS_L
PM_SLP_SUS_L
MAKE_BASE=TRUE
1
2
ALL_SYS_PWRGD
OUT
13 42 59
SYNC_MASTER=J43_MLB
Power Control
OUT
5%
1/20W
MF
0201
P3V3SUS_EN
59 58
16 17 37 59
DRAWING NUMBER
P3V3SUS_EN
MAKE_BASE=TRUE
NO STUFF
1
5
4
SYNC_DATE=09/16/2012
PAGE TITLE
R8190
0
5%
1/20W
MF
201
2
6
D
DMN32D2LFB4
10%
16V
X7R-1
0201
5%
1/20W
MF
201
THRM_PAD
2
VFRQ High: Variable Frequency
THRM
PAD
Apple Inc.
OUT
58 59
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
10%
25V
X5R
402
3
& lt; SCH_NUM & gt;
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
C8190
0.1UF
7
R8131 1
330K
PM_RSMRST_L
1000PF
2
1%
1/20W
MF
201
2
RESET*
2
330
S0PGOOD_ISL
15K
0.723V @ 1.02Vmin
53
U8130
PP3V42_G3H
R8164
P1V05S0_PGOOD
353S2310
TDFN
4
S0PGOOD_ISL
IN
SENSE
50 49 46 40 38 37 36 35 30 17
65 64 62 61 59
59
R8168
ISL88042IRTEZ
P5V_DIV_VMON
P1V5_DIV_VMON
P1V05_DIV_VMON
0.718V @ 1.45Vmin
55
5%
1/20W
MF
2 201
1
S0PGOOD_ISL
1%
1/20W
MF
201
1.5V Divider:
2
100K
2
2
5%
1/20W
MF
201
VDD
6.04K
1%
1/20W
MF
201
7
S0PGOOD_ISL
1
2
S0PGOOD_ISL
1
1
5%
1/20W
MF
201
100
1
9
S0PGOOD_ISL
1
8
P1V8S3_PGOOD
0.1UF
PP5V_S0
1.05V Divider:
IN
PP3V3_S0
PP1V5_S0
SUS_PGOOD_CT
100
R8165
55 51 42 38 17 16 15 11 8 6
64 62 58
64 62 59 58 57 8
2
CHGR VFRQ Generation
8 11 14 18 46 57 58 59 62 64
R8133
TPS3808G33
R8166
(ISL version used for development)
74 65 64 62 61
36 30 26 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
PP3V3_SUS
NO STUFF
S0 Rail PGOOD Circuitry
1
VDD
5%
1/20W
MF
2 201
Thresholds:
VDD:
2.734V-3.010V
V2MON: 2.815V-3.099V
V3MON: 0.572V-0.630V
V4MON: 0.572V-0.630V
10%
6.3V
CERM-X5R
0201
PM_SLP_S3_BUF_L
2
PP3V3_SUS
1
0.1UF
7
5%
1/20W
MF
201
C8130
U8130 Sense input
threhold is 3.07V
1
PP1V5_S0
64 62 59 58 57 8
2
100
5
1K
1
BYPASS=U8130.6:2.3mm
No stuff C8131, 12ms
Min delay time
R8157 1
R8155
A
28 57 59
5%
1/20W
MF
0201
5%
1/20W
MF
201
3.3V Divider: 1.07V
59
51
16
32
56
62
5%
1/20W
MF
201
1
2
Q4
1%
1/20W
MF
201
28 57 59
OUT
0
5%
1/20W
MF
201
2
5%
1/20W
MF
201
PLACE_NEAR=U8040.2:C7mm
1
7.15K
61
52
17
45
58
64
20K
5%
1/20W
MF
0201
1K
1
VMON_3V3_DIV
2
330
RB521ES-30
5%
1/20W
MF
201
OUT
R8187
0
R8146
A P1V5CODEC_EN_D
RB521ES-30
NC
1
R8186
NO STUFF
376S0854
Q3
1
R8184
0201
P1V05_EN_D
P1V5S0SW_AUDIO_EN
2
5%
1/20W
MF
201
D8146
1
R8185
PLACE_NEAR=U7600.16:6mm
100K
AUD_PWR_EN
IN
ASMCC0179
Q2
7
VMON_Q3_BASE
2
5%
1/20W
MF
201
1%
1/20W
MF
201
Q8150
1
D8185
R8180
R8145
DFN2015H4-8
R8154
R8158
A NO STUFF
PLACE_NEAR=U8040.2:C7mm
5
PM_SLP_S3_BUF_L
PM_SLP_S3_BUF_L
MAKE_BASE=TRUE
16 17 37 59
CRITICAL
Q1
64 65 74
38 39 40 41 42
8 11 12 13 15
17 18 26 30 36
43 44 45 56 59 61 62
PM_SLP_S3_BUF_L
NOSTUFF
1
1.5V Codec Enable
9ms RC delay
15K
1
4 59 57 28
2
6
R8152
PP3V3_S0
2
U8180
2
330K
S0PGD_C
VMON_Q2_BASE
B
SC70-HF
1
1%
1/20W
MF
201 2
R8153
S0 Enables
MC74VHC1G08
1
150K
1%
1/20W
MF
201
15K
1
PM_SLP_S3_R_L
5%
1/20W
MF
201
5.0V Divider: 1.07V
2
2 59
3
R8151
VMON_5V_DIV
1
100
1
PP3V3_S5
54.9K
2
PM_SLP_S3_L
IN
10%
6.3V
CERM-X5R
0201
4
1
16 17 32 45 51 52 56 58 59 61
62 64
28 18 17 16 15 13 11 8
74 64 62 60 59 58 57 42 34 29
37 18 17 13
5
2
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
81 OF 121
SHEET
59 OF 76
1
SIZE
D
A
8
7
6
5
4
3
2
1
D
D
LCD Connector
1
R8363
1
4.7K
2
R8364
Internal DP Connector: 518S0829
4.7K
5%
1/20W
MF
201
2
5%
1/20W
MF
201
CRITICAL
J8300
20525-130E-01
F-RT-SM
Pull-ups on panel side,
4.7 kOhm to 3.3V
R8361
73 40 37
BI
0
1
SMBUS_SMC_0_S0_SDA
2
64
64 62 56
PPHV_S0SW_LCDBKLT
31
1
I2C_TCON_SDA_R
5%
1/20W
MF
0201
NC
3
4
NC
R8362
IN
C
I2C_TCON_SCL_R
5%
1/20W
MF
0201
OUT
OUT
OUT
64 56
64
64 56
64 56
2
OUT
OUT
7
8
9
34 29 28 18 17 16 15 13 11 8
74 64 62 59 58 57 42
13
U8300
PP3V3_S5
OUT
DP_INT_HPD
1
FPF1009
13
IN
EDP_PANEL_PWR
1
ON
11
NC
FERR-120-OHM-1.5A
2
VIN_1
VOUT_1
3
VIN_2
VOUT_2
PP3V3_S0SW_LCD_R
4
Sense resistor on
43
sensor page
PP3V3_S0SW_LCD
1
6
1
C8309
THRM
PAD
0.1UF
7
C8311
0.1UF
2
10%
6.3V
CERM-X5R
0201
1
0.1UF
10%
6.3V
CERM-X5R
0201
1
C8312
67 5
BI
DP_INT_AUXCH_C_N
1
2
(DP_INT_AUX_CH_C_N)
10%
16V
X7R-1
0201
2
2
10%
16V
X5R-CERM
0201
67 5
BI
DP_INT_AUXCH_C_P
C8320
0.1UF
67 5
IN
DP_INT_ML_C_P & lt; 0 & gt;
IN
DP_INT_ML_C_N & lt; 0 & gt;
1
B
18
67 64
67 64
2
19
20
DP_INT_AUX_CH_C_N
DP_INT_AUX_CH_C_P
21
22
23
C8325
67 64
DP_INT_ML_P & lt; 0 & gt;
DP_INT_ML_N & lt; 0 & gt;
24
25
0.1UF
2
26
(DP_INT_AUX_CH_C_P)
NC
NC
10%
16V
X5R-CERM
0201
27
28
29
PLACE_NEAR=J8300.24:1mm
PLACE_NEAR=J8300.25:1mm
30
2
1
R8318
10%
16V
X5R-CERM
0201
67 5
PP3V3_S0SW_LCD_UF
MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
1
67 64
1
DisplayPort I/F
17
64
10UF
20%
6.3V
X5R
603
14
16
1000PF
C8324
DP_INT_HPD_CONN
15
0402-LF
C8315
GND
64
2
5
43
12
13
2
5%
1/20W
MF
0201
L8304
MFET-2X2-8IN
0
C
LED Backlight I/F
10
R8360
CRITICAL
5
6
LED_RETURN_6
LED_RETURN_5
LED_RETURN_4
LED_RETURN_3
LED_RETURN_2
LED_RETURN_1
OUT
64 56
0
1
SMBUS_SMC_0_S0_SCL
64 56
64 56
73 40 37
2
1M
0.1UF
2
5%
1/20W
MF
201
33
1M
5%
1/20W
MF
201
C8321
1
1
R8317
2
34
35
2
B
36
10%
16V
X5R-CERM
0201
37
38
39
40
41
PLACE_NEAR=J8300.14:2mm
R8350 1
32
1
100K
5%
1/20W
MF
201
A
R8380
1
R8370
1M
2
2
C8317
1M
5%
1/20W
MF
201
PLACE_NEAR=J8300.3:2mm
5%
1/20W
MF
201
2
1
1000PF
5%
50V
C0G-CERM
603
2
SYNC_MASTER=J43_MLB
SYNC_DATE=09/11/2012
PAGE TITLE
Internal DisplayPort Connector
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
83 OF 121
SHEET
60 OF 76
1
A
8
7
6
5
4
3
2
1
D
D
74 65 64 62
36 30 26 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
PP3V3_S0
50 49 46 40 38 37 36 35 30 17
65 64 62 59
PP3V42_G3H
CRITICAL
J9500
ON MLB SIDE AS LIO CAN’T FIT CAPS
DF40CG3.0-48DS-0.4V
F-ST-SM
49
50
C9521
GND_VOID=TRUE
(Right Speaker Enable)
65 50 38 37
IN
65 59 35
IN
65 39
65 58
C
OUT
1
3
5
7
9
11
13
15
SMC_BC_ACOK
USB_PWR_EN
FINSTACKSNS_ALERT_L
PP1V5_S0SW_AUDIO
73 65 40 37
73 65 40 37
BI
BI
SMBUS_SMC_2_S3_SDA
SMBUS_SMC_2_S3_SCL
2
4
6
8
10
12
14
16
1
68 65
BI
65 16 14
OUT
69 65 12
IN
65 64 38 37 36
IN
65 47
69 65 12
OUT
IN
69 65 12
69 65 12
C9520
IN
69 65 12
PLACE_NEAR=J9500.7:1.5mm
IN
IN
19
21
23
25
27
29
31
XDP_USB_EXTB_OC_L
HDA_RST_L
SMC_LID
SPKRAMP_SHDN_L
HDA_SYNC
HDA_SDIN0
HDA_BIT_CLK
HDA_SDOUT
20
22
24
26
28
30
32
35
37
39
41
43
45
47
SYS_ONEWIRE
36
38
40
42
44
46
48
OUT
IN
47 65 74
USB3_EXTB_R2D_P
C9550
10%
16V
X5R-CERM 2
0201
1
GND_VOID=TRUE
GND_VOID=TRUE
CRITICAL 2
2 CRITICAL
PP5V_S0_ALT_AUD_LDO_EN
AUD_PWR_EN
IN
2
13 59
65
MIN_LINE_WIDTH=0.1 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=5V
C9510
10%
16V
X5R-CERM
0201
1
51
1
0.1UF
5%
50V
CERM
0402
C
14 65 68
0.1UF
0201-THICKSTNCL
1
1
GND_VOID=TRUE
R9510
0
1
1
2
1/20W 5% MF 0201
5%
1/20W
MF
0201
NOSTUFF
GND_VOID=TRUE
USB_EXTB_P
USB_EXTB_N
BI
14 65 68
BI
14 65 68
PP5V_S0
C9531
16 17 32 45 51 52 56 58 59 62
64
15PF
68 65
USB3_EXTB_D2R_RC_N
GND_VOID=TRUE
25V
1
USB3_EXTB_D2R_N
2
0201
5%
IN
14 65 68
IN
14 65 68
NP0-CERM
GND_VOID=TRUE
68 65
USB3_EXTB_D2R_RC_P
NOSTUFF
GND_VOID=TRUE
15PF
52
GND_VOID=TRUE
0.1UF
2
2
10%
16V
X5R-CERM
0201
GND_VOID=TRUE
CRITICAL 2
C9500
2
D9510
516S1036
5%1
CRITICAL
2
NP0-CERM
25V
USB3_EXTB_D2R_P
0201
D9511
ESD112-B1-02ELS
ESD112-B1-02ELS
0201-THICKSTNCL
GND_VOID=TRUE
0201-THICKSTNCL
1
PLACE_NEAR=J9500.21:1.5mm
B
OUT
ESD112-B1-02ELS
R9501
0
USB3_EXTB_R2D_C_P
D9521
0201-THICKSTNCL
NOSTUFF
2
C9532
10PF
2
1
X5R-CERM
10%
0201
16V
47 65 74
ESD112-B1-02ELS
65
14 65 68
GND_VOID=TRUE
68 65
SPKRAMP_INR_N
SPKRAMP_INR_P
OUT
C9522
GND_VOID=TRUE
NOSTUFF
1
0.1UF
USB3_EXTB_R2D_C_N
0.1UF
GND_VOID=TRUE
D9520
65 37
USB3_EXTB_R2D_N
2
X5R-CERM
10%
0201
16V
R9520
1
1
PLACE_NEAR=J9500.9:1.5mm
0
B
2
1/20W 5% MF 0201
IO Ports
A
SYNC_MASTER=CLEAN_J43
SYNC_DATE=11/13/2012
PAGE TITLE
Left I/O (LIO) Connector
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
95 OF 121
SHEET
61 OF 76
1
A
8
7
6
" G3Hot " (Always-Present) Rails
64 62
42 41 27
56 50 49
PPBUS_G3H
PPBUS_G3H
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=8.6V
MAKE_BASE=TRUE
5
4
27 41 42 49 50 56 62 64
PP3V3_S5
34 29 28 18 17 16 15 13 11 8
74 64 62 60 59 58 57 42
PP3V3_S5
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
27 41 42 49 50 56 62 64
PPBUS_G3H
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
PP3V3_S5
27 41 42 49 50 56 62 64
PPBUS_G3H
27 41 42 49 50 56 62 64
PP3V3_S5
PPBUS_G3H
27 41 42 49 50 56 62 64
PP3V3_S5
PP3V3_S5
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
8 11 13 15 16 17 18 28
62 28
29 34 42 57 58 59 60 62 64 74
41 51 52 53 55 62 64
PP3V3_S5
PPBUS_S5_HS_COMPUTING_ISNS
41 51 52 53 55 62 64
PPBUS_S5_HS_COMPUTING_ISNS
41 51 52 53 55 62 64
PPBUS_S5_HS_COMPUTING_ISNS
41 51 52 53 55 62 64
PP3V3_S5
PP3V3_S5
PPDCIN_G3H_ISOL
PPDCIN_G3H_ISOL
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
PP3V3_S5
PP3V3_S5
42 49 50 62 64
62 58 39 38 36 33 29 27 26 25
64
42 49 50 62 64
MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
PPDCIN_G3H
PPDCIN_G3H
49 50 62 64
PP3V3_S4
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=18.5V
MAKE_BASE=TRUE
PP15V_TBT
PP1V8_S3
PP1V2_S3
PP1V2_S3
PP3V3_TBTLC
PP1V2_S3
PP1V2_S3
17 19 20 21 22 23 42 53 62 70
PP3V42_G3H
PP3V3_SUS
8 11 14 18 46 57 58 59 62 64
PP1V2_S3
17 19 20 21 22 23 42 53 62 70
8 11 14 18 46 57 58 59 62 64
PP1V2_S3
17 19 20 21 22 23 42 53 62 70
PP3V3_SUS
PP3V3_SUS
PP3V3_SUS
64 62 59 58 57 46 18 14 11 8
17 30 35 36 37 38 40 46 49 50
59 61 62 64 65
PP3V42_G3H
17
59
17
59
17
59
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
30
61
30
61
30
61
35
62
35
62
35
62
36
64
36
64
36
64
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
37 38 40 46 49 50
65
37 38 40 46 49 50
65
37 38 40 46 49 50
65
PP3V42_G3H
PP3V42_G3H
17 30 35 36 37 38 40 46
59 61 62
59 61 62 64 65
17 30 35 36 37 38 40 46
64 62 58 41 40 36 33 19 18 15
17 30 35 36 37 38 40 46
59 61 62 64 65
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
17
59
17
59
PP3V42_G3H
30
61
30
61
35
62
35
62
36
64
36
64
VOLTAGE=3.3V
MAKE_BASE=TRUE
8 11 14 18 46 57 58 59 62 64
PP1V2_S3
17 19 20 21 22 23 42 53 62 70
8 11 14 18 46 57 58 59 62 64
PP1V2_S3
17 19 20 21 22 23 42 53 62 70
PP3V3_SUS
8 11 14 18 46 57 58 59 62 64
PP3V3_SUS
8 11 14 18 46 57 58 59 62 64
PP3V3_SUS
8 11 14 18 46 57 58 59 62 64
PP3V3_SUS
17 30 35 36 37 38 40 46 49 50
59 61 62 64 65
PP3V42_G3H
8 11 14 18 46 57 58 59 62 64
PP1V05_SUS
16 57 62
PP3V3_S3
PP3V3_S3
49 50
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
37 38 40 46 49 50
65
37 38 40 46 49 50
65
15 18 19 33 36 40 41 58 62 64
VOLTAGE=3.3V
MAKE_BASE=TRUE
64
PP3V3_S3
15 18 19 33 36 40 41 58 62 64
PP3V3_S3
PP3V3_S3
15 18 19 33 36 40 41 58 62 64
PP3V3_S3
8 12 13 17 62 64 62 61
36 30 26 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
74 65 64
PP3V3_S0
PP3V3_S0
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP5V_S5
36 53 54 62
PP3V3_S0
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
MAKE_BASE=TRUE
PP3V3_S0
PP3V3_S0
PP5V_S5
36 53 54 62
PP3V3_S0
PP5V_S5
36 53 54 62
PP3V3_S0
PP3V3_S0
PP5V_S4RS3
PP5V_S4RS3
32 35 47 49 54 55 58 62 64
PP3V3_S0
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.175 MM
VOLTAGE=5V
MAKE_BASE=TRUE
PP3V3_S0
PP3V3_S0
PP5V_S4RS3
32 35 47 49 54 55 58 62 64
PP5V_S4RS3
32 35 47 49 54 55 58 62 64
PP5V_S4RS3
32 35 47 49 54 55 58 62 64
PP5V_S4RS3
32 35 47 49 54 55 58 62 64
PP5V_S4RS3
PP1V5_S0
32 35 47 49 54 55 58 62 64
PP3V3_S0
15 18 19 33 36 40 41 58 62 64
62 64 65 74
8 11 12 13 15 17 18 26 30 36 38
39 40 41 42 43 44 45 56 59 61
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP5V_S0
16 17 32 45 51 52 56 58 59 61
62 64
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
16 17 32 45 51 52 56 58 59 61
62 64
PP5V_S0
16
62
16
62
16
59
17 32 45 51 52 56 58 59 61
64
17 32 45 51 52 56 58 59 61
64
PP3V3_S4SW_SNS
17 32 45 51 52 56 58
61 62 64
16
62
16
62
16
62
17 32 45 51 52 56 58 59 61
64
17 32 45 51 52 56 58 59 61
64
17 32 45 51 52 56 58 59 61
64
PP5V_S0
PP5V_S0
PP5V_S0
A
PP5V_S0
PP5V_S0
PP5V_S0
16
62
16
62
16
62
PP5V_S0
PP5V_S0
24 53 62
PP3V3_S0
PP3V3_S0
PP0V6_S0_DDRVTT
24 53 62
PP0V6_S0_DDRVTT
24 53 62
PP1V05_S0
6 8 11 15 16 17 38 42 51 55 58
59 62 64
PP1V05_S0
6 8 11 15 16 17 38 42 51 55 58
59 62 64
6 8 11 15 16 17 38 42 51 55 58
59 62 64
6 8 11 15 16 17 38 42 51 55 58
59 62 64
PP1V05_S0
PP1V05_S0
PP1V05_S0
6 8 11 15 16 17 38 42 51 55 58
59 62 64
6 8 11 15 16 17 38 42 51 55 58
59 62 64
6 8 11 15 16 17 38 42 51 55 58
59 62 64
PP1V05_S0
PP1V05_S0
PP1V05_S0
6 8 11 15 16 17 38 42 51 55 58
59 62 64
PP1V05_S0
6 8 11 15 16 17 38 42 51 55 58
59 62 64
6 8 11 15 16 17 38 42 51 55 58
59 62 64
6 8 11 15 16 17 38 42 51 55 58
59 62 64
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP3V3_S4SW_SNS
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
PP1V05_S0
PP3V3_S4SW_SNS
41 42 43 58 62
PP3V3_S4SW_SNS
41 42 43 58 62
PP3V3_S4SW_SNS
41 42 43 58 62
PP3V3_S4SW_SNS
SYNC_MASTER=WILL_J43
Power Aliases
41 42 43 58 62
41 42 43 58 62
PP3V3_S4SW_SNS
41 42 43 58 62
PP3V3_S4SW_SNS
41 42 43 58 62
PP3V3_S4SW_SNS
41 42 43 58 62
PP3V3_S4SW_SNS
8 11 58 62
41 42 43 58 62
PP3V3_S4SW_SNS
PP1V05_S0SW_PCH_HSIO
41 42 43 58 62
PP3V3_S4SW_SNS
PP1V05_S0SW_PCH_HSIO
41 42 43 58 62
41 42 43 58 62
PP3V3_S4SW_SNS
41 42 43 58 62
DRAWING NUMBER
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
1.84A
Apple Inc.
PP1V05_S0SW_PCH_HSIO
5
8 11 58 62
PP1V05_S0SW_PCH_HSIO
6
SYNC_DATE=12/17/2012
PAGE TITLE
62 58 11 8
PP3V3_S4SW_SNS
PP3V3_S4SW_SNS
7
VOLTAGE=0V
MIN_NECK_WIDTH=0.075MM
MIN_LINE_WIDTH=0.6MM
41 42 43 58 62
PP3V3_S4SW_SNS
8
Digital Ground
GND
6 8 11 15 16 17 38 42 51 55 58
59 62 64
6 8 11 15 16 17 38 42 51 55 58
59 62 64
6 8 11 15 16 17 38 42 51 55 58
59 62 64
41 42 43 58 62
VOLTAGE=3.3V
MAKE_BASE=TRUE
PP1V05_S0
17 32 45 51 52 56 58 59 61
64
17 32 45 51 52 56 58 59 61
64
17 32 45 51 52 56 58 59 61
64
B
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=0.75V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.175 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
41 42 43 44 45 56 59 61 62 64
8 11 12 13 15 17 18 26 30 36 38
39 40 65
45 56 59 61 62 64 65 74
8 11 12 13 15 17 18 26 30 36 38
39 40 41 42 43 44
62 64 65 74
8 11 12 13 15 17 18 26 30 36 38
39 40 41 42 43 44 45 56 59 61
PP3V3_S0
PP5V_S0
8 57 58 59 62 64
PP0V6_S0_DDRVTT
8 10 42 52
62 64
8 57 58 59 62 64
PP1V5_S0
8 10 42 52
62 64
PPVCC_S0_CPU
59 61 62 64 65 74
38 39 40 41 42 43 44 45 56
8 11 12 13 15 17 18 26 30 36
74
41 42 43 44 45 56 59 61 62 64
8 11 12 13 15 17 18 26 30 36 38
39 40 65
45 56 59 61 62 64 65 74
8 11 12 13 15 17 18 26 30 36 38
39 40 41 42 43 44
62 64 65 74
8 11 12 13 15 17 18 26 30 36 38
39 40 41 42 43 44 45 56 59 61
45 56 59 61 62 64 65 74
15 17 18 26 30 36 38 39 40 41
12
42 43 44
8 59 61 62 64 65 74
11 38 39 40 41 42 43 44 45 56
13 11 12 13 15 17 18 26 30 36
8
41 42 43 44 45 56 59 61 62 64
12 13 15 17 18 26 30 36 38 39
8
65 74
11 59 61 62 64 65 74
40 38 39 40 41 42 43 44 45 56
8 11 12 13 15 17 18 26 30 36
74
32 35 47 49 54 55 58 62 64
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
MAKE_BASE=TRUE
8 10 42 52
62 64
8 57 58 59 62 64
PP1V5_S0
PP3V3_S0
PP5V_S0
PPVCC_S0_CPU
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.8V
MAKE_BASE=TRUE
PPVCC_S0_CPU
PP1V5_S0
41 42 43 44 45 56 59 61 62 64
12 13 15 17 18 26 30 36 38 39
8
65 74
11 59 61 62 64 65 74
40 38 39 40 41 42 43 44 45 56
8 11 12 13 15 17 18 26 30 36
74
41 42 43 44 45 56 59 61 62 64
8 11 12 13 15 17 18 26 30 36 38
39 40 65
45 56 59 61 62 64 65 74
8 11 12 13 15 17 18 26 30 36 38
39 40 41 42 43 44
62 64 65 74
8 11 12 13 15 17 18 26 30 36 38
39 40 41 42 43 44 45 56 59 61
45 56 59 61 62 64 65 74
15 17 18 26 30 36 38 39 40 41
42 43 44
12
8 59 61 62 64 65 74
11 38 39 40 41 42 43 44 45 56
13 11 12 13 15 17 18 26 30 36
8
40 41 42 43 44 45 56 59 61 62 PP0V6_S0_DDRVTT
12 13 15 17 18 26 30 36 38
8
64 65 74
11 59 61 62 64 65 74
39 38 39 40 41 42 43 44 45 56
8 11 12 13 15 17 18 26 30 36
74
41 42 43 44 45 56 59 61 62 64
8 11 12 13 15 17 18 26 30 36 38
39 40 65
45 56 59 61 62 64 65 74
8 11 12 13 15 17 18 26 30 36 38
39 40 41 42 43 44
62 64 65 74
62 64 65 74
8 11 12 13 15 17 18 26 30 36 38
39 40 41 42 43 44 45 56 59 61
PP1V05_S0
55 51 42 38 17 16 15 11 8 6
64 62 59 58
61 62 64 65 74
8 11 12 13 15 17 18 26 30 36 ? mA
38 39 40 41 42 43 44 45 56 59
PP3V3_S0
PP5V_S4RS3
PPVCC_S0_CPU
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE
8 11 12 13 15 17 18 26 30 36 38
39 40 41 42 43 44 45 56 59 61
62
8 11 12 13 15 17 18 26 30 36 38
39 40 41 42 43 44 45 56 59 61
64 65 74
PP3V3_S0
52 51 45 32 17 16
64 62 61 59 58 56
8 57 58 59 62 64
64 62 52 42 10 8
5V Rails
55 54 49 47 35 32
64 62 58
16 57 62
PP1V5_S0
15 18 19 33 36 40 41 58 62 64
PP3V3_S3
B
CPU " VCORE " RAILS
PP1V05_SUS
15 18 19 33 36 40 41 58 62 64
15 18 19 33 36 40 41 58 62 64
8 12 13 17 62 64
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3V
MAKE_BASE=TRUE
PP5V_S5
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
15 18 19 33 36 40 41 58 62 64
PP3V3_S3
62 54 53 36
PP1V05_SUS
15 18 19 33 36 40 41 58 62 64
PP3V3_S3
17 30 35 36 37 38 40 46 49 50
59 61 62 64 65
PPVRTC_G3H
PPVIN_SW_TBTBST
VOLTAGE=12.8V
PP3V3_S3
17 30 35 36 37 38 40 46 49 50
59 61 62 64 65
PPVRTC_G3H
C
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
49 50
PP3V42_G3H
PPVRTC_G3H
PP1V05_TBTCIO
64 26
49 50
64 65
PP3V42_G3H
13 12 8
64 62 17
17 19 20 21 22 23 42 53 62 70
PP3V3_SUS
17 30 35 36 37 38 40 46 49 50
59 61 62 64 65
17 30 35 36 37 38 40 46 49 50
59 61 62 64 65
17 18 25 26 62
64
17 19 20 21 22 23 42 53 62 70
8 11 14 18 46 57 58 59 62 64
49 50 62 64
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.42V
MAKE_BASE=TRUE
C
PP1V2_S3
25 26 27 29 33 36 38 39 58 62
64
PP3V3_SUS
PP3V42_G3H
25 26 27 29 33 36 38 39 58 62
64
17 18 25 26 62
64
PP3V3_TBTLC
PP3V3_S4
65 64 62
49 46 40
35 30 17
38 37 36
61 59 50
17 18 25 26 62
64
17 19 20 21 22 23 42 53 62 70
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.1 MM
VOLTAGE=1.2V
MAKE_BASE=TRUE
PP3V3_S4
PPDCIN_G3H
PP3V3_TBTLC
PP3V3_TBTLC
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
25 26 27 29 33 36 38 39 58 62
64
25 26 27 29 33 36 38 39 58 62
64
PP3V3_S4
20 21 22 23 57 62
64 62 26 25 18 17
27 28 62 64
20 21 22 23 57 62
25 26 27 29 33 36 38 39 58 62
64
70 62 53 42 23 22 21 20 19 17
25 26 27 29 33 36 38 39 58 62
64
PP3V3_S4
62 50 49
64
27 28 62 64
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=17.8V
MAKE_BASE=TRUE
PP1V8_S3
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
PP3V3_S4
PP3V3_S4
PP15V_TBT
PP15V_TBT
64 62 28 27
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
PP3V3_S5
42 49 50 62 64
20 21 22 23 57 62
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V
MAKE_BASE=TRUE
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
PP3V3_S5
PPDCIN_G3H_ISOL
TBT Rails (off when no cable)
PP1V8_S3
2A max supply
41 54 62 64
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=18.5V
MAKE_BASE=TRUE
28 62
VOLTAGE=3.3V
MAKE_BASE=TRUE
1.8V/1.5V/1.2V/1.05V Rails
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
PP1V8_S3
21 20
62 57 23 22
PP3V3_S5
PPDCIN_G3H_ISOL
56 60 62 64
D
PP3V3_S4_TBTAPWR
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
PP3V3_S5
PP3V3_S5
50 49 42
64 62
PP3V3_S4_TBTAPWR
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
41 54 62 64
PPBUS_S5_HS_OTHER_ISNS
PPHV_S0SW_LCDBKLT
30 41 62 64
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
PP3V3_S5
56 60 62 64
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
PP3V3_S5
PPBUS_S5_HS_OTHER_ISNS
PPHV_S0SW_LCDBKLT
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.375 MM
VOLTAGE=50V
MAKE_BASE=TRUE
30 41 62 64
VOLTAGE=3.3V
MAKE_BASE=TRUE
PP3V3_S0SW_SSD
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
PP3V3_S5
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=8.6V
MAKE_BASE=TRUE
PP3V3_S0SW_SSD
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.20MM
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
PP3V3_S5
PP3V3_S0SW_SSD
PPHV_S0SW_LCDBKLT
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
PP3V3_S5
PPBUS_S5_HS_COMPUTING_ISNS
64 62 60 56
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74 64 62 41 30
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
PP3V3_S5
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=8.6V
MAKE_BASE=TRUE
LCDBKLT Rail
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
27 41 42 49 50 56 62 64
PPBUS_G3H
62 54 41 PPBUS_S5_HS_OTHER_ISNS
64
1
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
PP3V3_S5
PPBUS_G3H
D
2
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
PP3V3_S5
64
52 51 41 PPBUS_S5_HS_COMPUTING_ISNS
62 55 53
3
3.3V Rails
8 11 58 62
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
100 OF 121
SHEET
62 OF 76
1
A
8
7
6
5
4
3
2
1
Memory Bit/Byte Swizzle
LPDDR3 Command/Address
MAKE_BASE
7
7
7
7
D
7
7
70 63 24 20 7
7
7
7
7
7
7
7
7
7
70 63 24 21 7
7
7
7
70 63 24 21 20 7
63 7
63 7
=MEM_A_A & lt; 5 & gt;
=MEM_A_A & lt; 9 & gt;
=MEM_A_A & lt; 6 & gt;
=MEM_A_A & lt; 8 & gt;
=MEM_A_A & lt; 7 & gt;
=MEM_A_BA & lt; 2 & gt;
MEM_A_CAA & lt; 6 & gt;
=MEM_A_A & lt; 11 & gt;
=MEM_A_A & lt; 15 & gt;
=MEM_A_A & lt; 14 & gt;
=MEM_A_A & lt; 13 & gt;
=MEM_A_CAS_L
=MEM_A_WE_L
=MEM_A_RAS_L
=MEM_A_BA & lt; 0 & gt;
=MEM_A_A & lt; 2 & gt;
MEM_A_CAB & lt; 6 & gt;
=MEM_A_A & lt; 10 & gt;
=MEM_A_A & lt; 1 & gt;
=MEM_A_A & lt; 0 & gt;
MEM_A_ODT & lt; 0 & gt;
TP_LPDDR3_RSVD1
TP_LPDDR3_RSVD2
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
MAKE_BASE
MEM_A_CAA & lt; 0 & gt;
MEM_A_CAA & lt; 1 & gt;
MEM_A_CAA & lt; 2 & gt;
MEM_A_CAA & lt; 3 & gt;
MEM_A_CAA & lt; 4 & gt;
MEM_A_CAA & lt; 5 & gt;
MEM_A_CAA & lt; 6 & gt;
MEM_A_CAA & lt; 7 & gt;
MEM_A_CAA & lt; 8 & gt;
MEM_A_CAA & lt; 9 & gt;
20 24 70
20
20 24 70
20
20 24 70
20
20 24 70
20
20 24 70
20
7 20 24 63 70
20
20 24 70
20
20 24 70
20
20 24 70
MEM_A_CAB & lt; 0 & gt;
MEM_A_CAB & lt; 1 & gt;
MEM_A_CAB & lt; 2 & gt;
MEM_A_CAB & lt; 3 & gt;
MEM_A_CAB & lt; 4 & gt;
MEM_A_CAB & lt; 5 & gt;
MEM_A_CAB & lt; 6 & gt;
MEM_A_CAB & lt; 7 & gt;
MEM_A_CAB & lt; 8 & gt;
MEM_A_CAB & lt; 9 & gt;
MEM_A_ODT & lt; 0 & gt;
TP_LPDDR3_RSVD1
TP_LPDDR3_RSVD2
20
20 24 70
20
20
21 24 70
20
21 24 70
20
21 24 70
20
21 24 70
20
21 24 70
20
21 24 70
20
7 21 24 63 70
20
21 24 70
20
21 24 70
20
21 24 70
20
7 20 21 24 63 70
20
7 63
20
7 63
20
7
7
7
7
7
7
C
70 63 24 22 7
7
7
7
7
7
7
7
7
7
70 63 24 23 7
7
7
7
70 63 24 23 22 7
63 7
63 7
=MEM_B_A & lt; 5 & gt;
=MEM_B_A & lt; 9 & gt;
=MEM_B_A & lt; 6 & gt;
=MEM_B_A & lt; 8 & gt;
=MEM_B_A & lt; 7 & gt;
=MEM_B_BA & lt; 2 & gt;
MEM_B_CAA & lt; 6 & gt;
=MEM_B_A & lt; 11 & gt;
=MEM_B_A & lt; 15 & gt;
=MEM_B_A & lt; 14 & gt;
TRUE
=MEM_B_A & lt; 13 & gt;
=MEM_B_CAS_L
=MEM_B_WE_L
=MEM_B_RAS_L
=MEM_B_BA & lt; 0 & gt;
=MEM_B_A & lt; 2 & gt;
MEM_B_CAB & lt; 6 & gt;
=MEM_B_A & lt; 10 & gt;
=MEM_B_A & lt; 1 & gt;
=MEM_B_A & lt; 0 & gt;
MEM_B_ODT & lt; 0 & gt;
TP_LPDDR3_RSVD3
TP_LPDDR3_RSVD4
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
MEM_B_CAA & lt; 0 & gt;
MEM_B_CAA & lt; 1 & gt;
MEM_B_CAA & lt; 2 & gt;
MEM_B_CAA & lt; 3 & gt;
MEM_B_CAA & lt; 4 & gt;
MEM_B_CAA & lt; 5 & gt;
MEM_B_CAA & lt; 6 & gt;
MEM_B_CAA & lt; 7 & gt;
MEM_B_CAA & lt; 8 & gt;
MEM_B_CAA & lt; 9 & gt;
22 24 70
20
22 24 70
20
22 24 70
20
22 24 70
20
22 24 70
20
22 24 70
20
7 22 24 63 70
20
22 24 70
21
22 24 70
MEM_B_CAB & lt; 0 & gt;
MEM_B_CAB & lt; 1 & gt;
MEM_B_CAB & lt; 2 & gt;
MEM_B_CAB & lt; 3 & gt;
MEM_B_CAB & lt; 4 & gt;
MEM_B_CAB & lt; 5 & gt;
MEM_B_CAB & lt; 6 & gt;
MEM_B_CAB & lt; 7 & gt;
MEM_B_CAB & lt; 8 & gt;
MEM_B_CAB & lt; 9 & gt;
MEM_B_ODT & lt; 0 & gt;
TP_LPDDR3_RSVD3
TP_LPDDR3_RSVD4
20
22 24 70
21
21
23 24 70
21
23 24 70
21
23 24 70
21
23 24 70
21
23 24 70
21
23 24 70
21
7 23 24 63 70
21
23 24 70
21
23 24 70
21
23 24 70
21
7 22 23 24 63 70
70 63 21 7
7 63
21
7 63
21
21
21
21
21
21
21
21
21
21
B
21
21
21
21
21
21
21
20
20
20
20
20
20
20
20
21
21
21
21
70 63 21 7
70 63 21 7
21
21
=MEM_A_DQ & lt; 0 & gt;
=MEM_A_DQ & lt; 1 & gt;
=MEM_A_DQ & lt; 2 & gt;
=MEM_A_DQ & lt; 3 & gt;
=MEM_A_DQ & lt; 4 & gt;
=MEM_A_DQ & lt; 5 & gt;
=MEM_A_DQ & lt; 6 & gt;
=MEM_A_DQ & lt; 7 & gt;
=MEM_A_DQ & lt; 8 & gt;
=MEM_A_DQ & lt; 9 & gt;
=MEM_A_DQ & lt; 10 & gt;
=MEM_A_DQ & lt; 11 & gt;
=MEM_A_DQ & lt; 12 & gt;
=MEM_A_DQ & lt; 13 & gt;
=MEM_A_DQ & lt; 14 & gt;
=MEM_A_DQ & lt; 15 & gt;
=MEM_A_DQ & lt; 16 & gt;
=MEM_A_DQ & lt; 17 & gt;
=MEM_A_DQ & lt; 18 & gt;
=MEM_A_DQ & lt; 19 & gt;
=MEM_A_DQ & lt; 20 & gt;
=MEM_A_DQ & lt; 21 & gt;
=MEM_A_DQ & lt; 22 & gt;
=MEM_A_DQ & lt; 23 & gt;
=MEM_A_DQ & lt; 24 & gt;
=MEM_A_DQ & lt; 25 & gt;
=MEM_A_DQ & lt; 26 & gt;
=MEM_A_DQ & lt; 27 & gt;
=MEM_A_DQ & lt; 28 & gt;
=MEM_A_DQ & lt; 29 & gt;
=MEM_A_DQ & lt; 30 & gt;
=MEM_A_DQ & lt; 31 & gt;
=MEM_A_DQ & lt; 32 & gt;
=MEM_A_DQ & lt; 33 & gt;
=MEM_A_DQ & lt; 34 & gt;
=MEM_A_DQ & lt; 35 & gt;
=MEM_A_DQ & lt; 36 & gt;
=MEM_A_DQ & lt; 37 & gt;
=MEM_A_DQ & lt; 38 & gt;
=MEM_A_DQ & lt; 39 & gt;
=MEM_A_DQ & lt; 40 & gt;
=MEM_A_DQ & lt; 41 & gt;
=MEM_A_DQ & lt; 42 & gt;
=MEM_A_DQ & lt; 43 & gt;
=MEM_A_DQ & lt; 44 & gt;
MEM_A_DQ & lt; 33 & gt;
=MEM_A_DQ & lt; 46 & gt;
=MEM_A_DQ & lt; 47 & gt;
=MEM_A_DQ & lt; 48 & gt;
=MEM_A_DQ & lt; 49 & gt;
=MEM_A_DQ & lt; 50 & gt;
=MEM_A_DQ & lt; 51 & gt;
=MEM_A_DQ & lt; 52 & gt;
=MEM_A_DQ & lt; 53 & gt;
=MEM_A_DQ & lt; 54 & gt;
=MEM_A_DQ & lt; 55 & gt;
=MEM_A_DQ & lt; 56 & gt;
=MEM_A_DQ & lt; 57 & gt;
=MEM_A_DQ & lt; 58 & gt;
=MEM_A_DQ & lt; 59 & gt;
=MEM_A_DQ & lt; 60 & gt;
=MEM_A_DQ & lt; 61 & gt;
=MEM_A_DQ & lt; 62 & gt;
=MEM_A_DQ & lt; 63 & gt;
TRUE
=MEM_A_DQS_P & lt; 0 & gt;
=MEM_A_DQS_N & lt; 0 & gt;
=MEM_A_DQS_P & lt; 1 & gt;
=MEM_A_DQS_N & lt; 1 & gt;
=MEM_A_DQS_P & lt; 2 & gt;
=MEM_A_DQS_N & lt; 2 & gt;
=MEM_A_DQS_P & lt; 3 & gt;
=MEM_A_DQS_N & lt; 3 & gt;
=MEM_A_DQS_P & lt; 4 & gt;
=MEM_A_DQS_N & lt; 4 & gt;
=MEM_A_DQS_P & lt; 5 & gt;
=MEM_A_DQS_N & lt; 5 & gt;
MEM_A_DQS_P & lt; 6 & gt;
MEM_A_DQS_N & lt; 6 & gt;
=MEM_A_DQS_P & lt; 7 & gt;
=MEM_A_DQS_N & lt; 7 & gt;
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
MAKE_BASE
MEM_A_DQ & lt; 9 & gt;
MEM_A_DQ & lt; 12 & gt;
MEM_A_DQ & lt; 10 & gt;
MEM_A_DQ & lt; 11 & gt;
MEM_A_DQ & lt; 8 & gt;
MEM_A_DQ & lt; 13 & gt;
MEM_A_DQ & lt; 14 & gt;
MEM_A_DQ & lt; 15 & gt;
MEM_A_DQ & lt; 0 & gt;
MEM_A_DQ & lt; 1 & gt;
MEM_A_DQ & lt; 2 & gt;
MEM_A_DQ & lt; 7 & gt;
MEM_A_DQ & lt; 4 & gt;
MEM_A_DQ & lt; 5 & gt;
MEM_A_DQ & lt; 3 & gt;
MEM_A_DQ & lt; 6 & gt;
MEM_A_DQ & lt; 29 & gt;
MEM_A_DQ & lt; 28 & gt;
MEM_A_DQ & lt; 27 & gt;
MEM_A_DQ & lt; 31 & gt;
MEM_A_DQ & lt; 24 & gt;
MEM_A_DQ & lt; 25 & gt;
MEM_A_DQ & lt; 26 & gt;
MEM_A_DQ & lt; 30 & gt;
MEM_A_DQ & lt; 18 & gt;
MEM_A_DQ & lt; 21 & gt;
MEM_A_DQ & lt; 16 & gt;
MEM_A_DQ & lt; 23 & gt;
MEM_A_DQ & lt; 20 & gt;
MEM_A_DQ & lt; 19 & gt;
MEM_A_DQ & lt; 22 & gt;
MEM_A_DQ & lt; 17 & gt;
MEM_A_DQ & lt; 41 & gt;
MEM_A_DQ & lt; 44 & gt;
MEM_A_DQ & lt; 46 & gt;
MEM_A_DQ & lt; 47 & gt;
MEM_A_DQ & lt; 40 & gt;
MEM_A_DQ & lt; 45 & gt;
MEM_A_DQ & lt; 42 & gt;
MEM_A_DQ & lt; 43 & gt;
MEM_A_DQ & lt; 36 & gt;
MEM_A_DQ & lt; 37 & gt;
MEM_A_DQ & lt; 34 & gt;
MEM_A_DQ & lt; 39 & gt;
MEM_A_DQ & lt; 32 & gt;
MEM_A_DQ & lt; 33 & gt;
MEM_A_DQ & lt; 35 & gt;
MEM_A_DQ & lt; 38 & gt;
MEM_A_DQ & lt; 52 & gt;
MEM_A_DQ & lt; 51 & gt;
MEM_A_DQ & lt; 48 & gt;
MEM_A_DQ & lt; 49 & gt;
MEM_A_DQ & lt; 53 & gt;
MEM_A_DQ & lt; 50 & gt;
MEM_A_DQ & lt; 54 & gt;
MEM_A_DQ & lt; 55 & gt;
MEM_A_DQ & lt; 58 & gt;
MEM_A_DQ & lt; 62 & gt;
MEM_A_DQ & lt; 60 & gt;
MEM_A_DQ & lt; 61 & gt;
MEM_A_DQ & lt; 59 & gt;
MEM_A_DQ & lt; 63 & gt;
MEM_A_DQ & lt; 57 & gt;
MEM_A_DQ & lt; 56 & gt;
MEM_A_DQS_P & lt; 1 & gt;
MEM_A_DQS_N & lt; 1 & gt;
MEM_A_DQS_P & lt; 0 & gt;
MEM_A_DQS_N & lt; 0 & gt;
MEM_A_DQS_P & lt; 3 & gt;
MEM_A_DQS_N & lt; 3 & gt;
MEM_A_DQS_P & lt; 2 & gt;
MEM_A_DQS_N & lt; 2 & gt;
MEM_A_DQS_P & lt; 5 & gt;
MEM_A_DQS_N & lt; 5 & gt;
MEM_A_DQS_P & lt; 4 & gt;
MEM_A_DQS_N & lt; 4 & gt;
MEM_A_DQS_P & lt; 6 & gt;
MEM_A_DQS_N & lt; 6 & gt;
MEM_A_DQS_P & lt; 7 & gt;
MEM_A_DQS_N & lt; 7 & gt;
22
7 70
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
70 63 23 7
7 70
23
7 70
23
7 70
23
7 70
23
7 21 63 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
23
7 70
23
7 70
23
7 70
23
7 21 63 70
23
7 21 63 70
23
7 70
70 63 23 7
7 70
70 63 23 7
=MEM_B_DQ & lt; 0 & gt;
=MEM_B_DQ & lt; 1 & gt;
=MEM_B_DQ & lt; 2 & gt;
=MEM_B_DQ & lt; 3 & gt;
=MEM_B_DQ & lt; 4 & gt;
=MEM_B_DQ & lt; 5 & gt;
=MEM_B_DQ & lt; 6 & gt;
=MEM_B_DQ & lt; 7 & gt;
=MEM_B_DQ & lt; 8 & gt;
=MEM_B_DQ & lt; 9 & gt;
=MEM_B_DQ & lt; 10 & gt;
=MEM_B_DQ & lt; 11 & gt;
=MEM_B_DQ & lt; 12 & gt;
=MEM_B_DQ & lt; 13 & gt;
=MEM_B_DQ & lt; 14 & gt;
=MEM_B_DQ & lt; 15 & gt;
=MEM_B_DQ & lt; 16 & gt;
=MEM_B_DQ & lt; 17 & gt;
=MEM_B_DQ & lt; 18 & gt;
=MEM_B_DQ & lt; 19 & gt;
=MEM_B_DQ & lt; 20 & gt;
=MEM_B_DQ & lt; 21 & gt;
=MEM_B_DQ & lt; 22 & gt;
=MEM_B_DQ & lt; 23 & gt;
=MEM_B_DQ & lt; 24 & gt;
=MEM_B_DQ & lt; 25 & gt;
=MEM_B_DQ & lt; 26 & gt;
=MEM_B_DQ & lt; 27 & gt;
=MEM_B_DQ & lt; 28 & gt;
=MEM_B_DQ & lt; 29 & gt;
=MEM_B_DQ & lt; 30 & gt;
=MEM_B_DQ & lt; 31 & gt;
=MEM_B_DQ & lt; 32 & gt;
=MEM_B_DQ & lt; 33 & gt;
=MEM_B_DQ & lt; 34 & gt;
=MEM_B_DQ & lt; 35 & gt;
=MEM_B_DQ & lt; 36 & gt;
=MEM_B_DQ & lt; 37 & gt;
=MEM_B_DQ & lt; 38 & gt;
=MEM_B_DQ & lt; 39 & gt;
MEM_B_DQ & lt; 32 & gt;
=MEM_B_DQ & lt; 41 & gt;
=MEM_B_DQ & lt; 42 & gt;
=MEM_B_DQ & lt; 43 & gt;
=MEM_B_DQ & lt; 44 & gt;
=MEM_B_DQ & lt; 45 & gt;
=MEM_B_DQ & lt; 46 & gt;
=MEM_B_DQ & lt; 47 & gt;
=MEM_B_DQ & lt; 48 & gt;
=MEM_B_DQ & lt; 49 & gt;
=MEM_B_DQ & lt; 50 & gt;
=MEM_B_DQ & lt; 51 & gt;
=MEM_B_DQ & lt; 52 & gt;
=MEM_B_DQ & lt; 53 & gt;
=MEM_B_DQ & lt; 54 & gt;
=MEM_B_DQ & lt; 55 & gt;
=MEM_B_DQ & lt; 56 & gt;
=MEM_B_DQ & lt; 57 & gt;
=MEM_B_DQ & lt; 58 & gt;
=MEM_B_DQ & lt; 59 & gt;
=MEM_B_DQ & lt; 60 & gt;
=MEM_B_DQ & lt; 61 & gt;
=MEM_B_DQ & lt; 62 & gt;
=MEM_B_DQ & lt; 63 & gt;
TRUE
=MEM_B_DQS_P & lt; 0 & gt;
=MEM_B_DQS_N & lt; 0 & gt;
=MEM_B_DQS_P & lt; 1 & gt;
=MEM_B_DQS_N & lt; 1 & gt;
=MEM_B_DQS_P & lt; 2 & gt;
=MEM_B_DQS_N & lt; 2 & gt;
=MEM_B_DQS_P & lt; 3 & gt;
=MEM_B_DQS_N & lt; 3 & gt;
=MEM_B_DQS_P & lt; 4 & gt;
=MEM_B_DQS_N & lt; 4 & gt;
=MEM_B_DQS_P & lt; 5 & gt;
=MEM_B_DQS_N & lt; 5 & gt;
=MEM_B_DQS_P & lt; 6 & gt;
=MEM_B_DQS_N & lt; 6 & gt;
MEM_B_DQS_P & lt; 6 & gt;
MEM_B_DQS_N & lt; 6 & gt;
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
MEM_B_DQ & lt; 12 & gt;
MEM_B_DQ & lt; 9 & gt;
MEM_B_DQ & lt; 10 & gt;
MEM_B_DQ & lt; 11 & gt;
MEM_B_DQ & lt; 13 & gt;
MEM_B_DQ & lt; 8 & gt;
MEM_B_DQ & lt; 14 & gt;
MEM_B_DQ & lt; 15 & gt;
MEM_B_DQ & lt; 0 & gt;
MEM_B_DQ & lt; 1 & gt;
MEM_B_DQ & lt; 2 & gt;
MEM_B_DQ & lt; 7 & gt;
MEM_B_DQ & lt; 4 & gt;
MEM_B_DQ & lt; 5 & gt;
MEM_B_DQ & lt; 6 & gt;
MEM_B_DQ & lt; 3 & gt;
MEM_B_DQ & lt; 28 & gt;
MEM_B_DQ & lt; 29 & gt;
MEM_B_DQ & lt; 30 & gt;
MEM_B_DQ & lt; 27 & gt;
MEM_B_DQ & lt; 24 & gt;
MEM_B_DQ & lt; 25 & gt;
MEM_B_DQ & lt; 31 & gt;
MEM_B_DQ & lt; 26 & gt;
MEM_B_DQ & lt; 20 & gt;
MEM_B_DQ & lt; 16 & gt;
MEM_B_DQ & lt; 23 & gt;
MEM_B_DQ & lt; 22 & gt;
MEM_B_DQ & lt; 21 & gt;
MEM_B_DQ & lt; 17 & gt;
MEM_B_DQ & lt; 18 & gt;
MEM_B_DQ & lt; 19 & gt;
MEM_B_DQ & lt; 44 & gt;
MEM_B_DQ & lt; 41 & gt;
MEM_B_DQ & lt; 42 & gt;
MEM_B_DQ & lt; 43 & gt;
MEM_B_DQ & lt; 45 & gt;
MEM_B_DQ & lt; 40 & gt;
MEM_B_DQ & lt; 46 & gt;
MEM_B_DQ & lt; 47 & gt;
MEM_B_DQ & lt; 32 & gt;
MEM_B_DQ & lt; 33 & gt;
MEM_B_DQ & lt; 34 & gt;
MEM_B_DQ & lt; 39 & gt;
MEM_B_DQ & lt; 36 & gt;
MEM_B_DQ & lt; 37 & gt;
MEM_B_DQ & lt; 38 & gt;
MEM_B_DQ & lt; 35 & gt;
MEM_B_DQ & lt; 57 & gt;
MEM_B_DQ & lt; 56 & gt;
MEM_B_DQ & lt; 60 & gt;
MEM_B_DQ & lt; 59 & gt;
MEM_B_DQ & lt; 63 & gt;
MEM_B_DQ & lt; 62 & gt;
MEM_B_DQ & lt; 58 & gt;
MEM_B_DQ & lt; 61 & gt;
MEM_B_DQ & lt; 49 & gt;
MEM_B_DQ & lt; 51 & gt;
MEM_B_DQ & lt; 48 & gt;
MEM_B_DQ & lt; 53 & gt;
MEM_B_DQ & lt; 52 & gt;
MEM_B_DQ & lt; 55 & gt;
MEM_B_DQ & lt; 50 & gt;
MEM_B_DQ & lt; 54 & gt;
MEM_B_DQS_P & lt; 1 & gt;
MEM_B_DQS_N & lt; 1 & gt;
MEM_B_DQS_P & lt; 0 & gt;
MEM_B_DQS_N & lt; 0 & gt;
MEM_B_DQS_P & lt; 3 & gt;
MEM_B_DQS_N & lt; 3 & gt;
MEM_B_DQS_P & lt; 2 & gt;
MEM_B_DQS_N & lt; 2 & gt;
MEM_B_DQS_P & lt; 5 & gt;
MEM_B_DQS_N & lt; 5 & gt;
MEM_B_DQS_P & lt; 4 & gt;
MEM_B_DQS_N & lt; 4 & gt;
MEM_B_DQS_P & lt; 7 & gt;
MEM_B_DQS_N & lt; 7 & gt;
MEM_B_DQS_P & lt; 6 & gt;
MEM_B_DQS_N & lt; 6 & gt;
7 70
7 70
7 70
7 70
D
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
C
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 23 63 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
B
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 23 63 70
7 23 63 70
A
SYNC_MASTER=J41_MLB
SYNC_DATE=08/30/2012
PAGE TITLE
Signal Aliases
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
102 OF 121
SHEET
63 OF 76
1
A
8
7
6
5
4
3
2
Functional Test Points
J3501: AirPort / BT Connector
PP3V3_WLAN
WIFI_EVENT_L
PCIE_AP_R2D_N
PCIE_AP_R2D_P
PCIE_CLK100M_AP_N
PCIE_CLK100M_AP_P
PCIE_AP_D2R_P
PCIE_AP_D2R_N
PCIE_WAKE_L
AP_RESET_CONN_L
AP_CLKREQ_Q_L
USB_BT_CONN_P
USB_BT_CONN_N
PP3V3_S4
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
(Need 6 TPs)
29 37 38
TRUE
29 69
TRUE
14 29 69
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PPVIN_SW_TBTBST
TRUE
PPBUS_S5_HS_COMPUTING_ISNS
PPDCIN_G3H
PP3V42_G3H
PPVRTC_G3H
PP3V3_S5
PP3V3_SUS
PP3V3_S3
PP3V3_S0
PP3V3_S0SW_SSD
PP1V5_S0
PP1V05_S0
PP15V_TBT
PP3V3_TBTLC
PP1V05_TBT
PPVCC_S0_CPU
PP1V05_TBTCIO
PPBUS_S5_HS_OTHER_ISNS
PPDCIN_G3H_ISOL
PP3V3_S4
TRUE
TRUE
TRUE
FUNC_TEST
14 29 69
13 29 31
TRUE
29
TRUE
29
TRUE
29 68
TRUE
29 68
TRUE
25 26 27 29 33 36 38
39 58 62 64
TRUE
TRUE
TRUE
(Need 5 TPs)
30
TRUE
30 67
TRUE
30 67
TRUE
42 43 44 45 56 59 61
8 11 12 13 15 17 18
26 30 36 38 39 40 41
62 64 65 74
30
TRUE
30
TRUE
30
TRUE
SMC_LID
TPAD_SPI_MISO_R
USB_TPAD_P
USB_TPAD_N
TPAD_SPI_CLK_R
TPAD_WAKE_L
TPAD_SPI_MOSI_R
PP3V3_S4_IPD
TPAD_SPI_CS_R_L
TPAD_SPI_IF_EN_CONN
TPAD_SPI_INT_S4_WAKE_L_CONN
PP5V_S4_IPD
TPAD_USB_IF_EN_CONN
SMBUS_SMC_3_SDA
SMBUS_SMC_3_SCL
SMC_LSOC_RST_L
PP3V42_G3H
SMC_ONOFF_L
TRUE
TRUE
TRUE
45
J4800: IPD Flex Connector
TRUE
TRUE
45
TRUE
J3700: SSD Connector
PP3V3_S0SW_SSD_FLT
PCIE_SSD_R2D_N & lt; 3..0 & gt;
PCIE_SSD_R2D_P & lt; 3..0 & gt;
PP3V3_S0
SSD_RESET_CONN_L
SSD_CLKREQ_CONN_L
SMC_OOB1_R2D_CONN_L
SMC_OOB1_D2R_CONN_L
SSD_PCIE_SEL_L
SSD_SR_EN_L
SMC_PWRFAIL_WARN_L
SSD_PWR_EN
PCIE_SSD_D2R_N & lt; 3..0 & gt;
PCIE_SSD_D2R_P & lt; 3..0 & gt;
PCIE_CLK100M_SSD_N
PCIE_CLK100M_SSD_P
TRUE
12 29 69
12 29 69
TRUE
TRUE
NO_TEST
MAKE_BASE
PPBUS_G3H
16 17 32 45 51 52 56
58 59 61 62
(Need to add 1 GND TP)
29 69
FUNC_TEST
TRUE
FUNC_TEST
PP5V_S0
FAN_RT_TACH
FAN_RT_PWM
TRUE
29 37 38 39 41
(Need to add 8 GND TPs)
C
Misc Voltages & Control Signals
FUNC_TEST
TRUE
D
NO_TEST Nets
J6000: Fan Connector
FUNC_TEST
36 37 38 61 65
TRUE
36
TRUE
14 36 68
TRUE
14 36 68
TRUE
36
TRUE
36
TRUE
36
TRUE
36
TRUE
36
TRUE
36
TRUE
36
TRUE
36
TRUE
36
TRUE
36 37 40 44 73
TRUE
27 41 42 49 50 56 62
(Need to add 27 GND TPs)
64
62
64
41 51 52 53 55 62
64 12
49 50 62 64
64 12
17 30 35 36 37 38 40 46 49 50
59 61 62 64 65
64 14
8 12 13 17 62
64 14
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 74
64 14
8 11 14 18 46 57 58 59 62
64 14
15 18 19 33 36 40 41 58 62
64 14
62 64 65 74
8 11 12 13 15 17 18 26 30 36 38
39 40 41 42 43 44 45 56 59 61
64 14
30 41 62
64 14
8 57 58 59 62
64 14
6 8 11 15 16 17 38 42 51 55 58
59 62 64
64 14
27 28 62
64 14
17 18 25 26 62
67
26
67
8 10 42 52 62
64 12
26 62
64 13
41 54 62
64 14
42 49 50 62
64 14
25 26 27 29 33 36 38 39 58 62
64
64 14
36 38
64 37
17 30 35 36 37 38 40 46 49 50
59 61 62 64 65
64
36 37 38
64
(Need to add 5 GND TPs)
64
30
64 37
J7000: DC-In Connector
15 30
64 37
FUNC_TEST
PPDCIN_G3H
PP5V_S4RS3
TRUE
15 30 58 59
TRUE
(Need 4 TPs)
64 37
49 50 62 64
(Need 3 TPs)
64 37
32 35 47 49 54 55 58 62
12 30 67
64 37
(Need to add 5 GND TPs)
12 30 67
64
12 30 67
64
J6404: Speaker Connector
12 30 67
64
(Need to add 6 GND TPs)
FUNC_TEST
J4002: Camera Connector
64 37
SPKRAMP_ROUT_P
SPKRAMP_ROUT_N
TRUE
TRUE
47 74
64 37
47 74
64 37
FUNC_TEST
MIPI_CLK_CONN_N
MIPI_CLK_CONN_P
CAM_SENSOR_WAKE_L_CONN
MIPI_DATA_CONN_N
MIPI_DATA_CONN_P
SMBUS_SMC_1_S0_SDA
SMBUS_SMC_1_S0_SCL
I2C_CAM_SCK
I2C_CAM_SDA
PP5V_S3RS0_ALSCAM_F
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
(Need to add 3 GND TPs)
64 37
32 72
64 37
J6950: Battery Connector
71
32
FUNC_TEST
32 72
PPVBAT_G3H_CONN
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA
SYS_DETECT_L
TRUE
32 72
TRUE
14 32 37 40 43 44 69
73
TRUE
14 32 37 40 43 44 69
73
31 32
TRUE
(Need 4 TPs)
71
48 50
71
37 40 48 50 73
71
37 40 48 50 73
64 25
48
71 64
(Need to add 4 GND TPs near
71 64
31 32
(Need TBD TPs)
J7050 and 1 for shield)
71 64 25
32
71 64 25
J8300: Internal DP Connector
25
FUNC_TEST
PPHV_S0SW_LCDBKLT
LED_RETURN_6
LED_RETURN_5
LED_RETURN_4
LED_RETURN_3
LED_RETURN_2
LED_RETURN_1
DP_INT_HPD_CONN
I2C_TCON_SDA_R
I2C_TCON_SCL_R
PP3V3_S0SW_LCD_UF
DP_INT_AUX_CH_C_N
DP_INT_AUX_CH_C_P
DP_INT_ML_P & lt; 0 & gt;
DP_INT_ML_N & lt; 0 & gt;
TRUE
TRUE
TRUE
TRUE
J6100: LPC+SPI Connector
TRUE
FUNC_TEST
TRUE
TRUE
TRUE
SPI_ALT_IO2_WP_L
46
TRUE
TRUE
SPI_ALT_IO3_HOLD_L
46
TRUE
TRUE
LPC_AD & lt; 3..0 & gt;
14 37 69
TRUE
TRUE
SPI_ALT_IO0_MOSI
TRUE
TRUE
XDP_LPCPLUS_GPIO
LPCPLUS_RESET_L
SMC_TDO
TP_SMC_TRST_L
TP_SMC_MD1
SMC_TX_L
TRUE
SPI_ALT_IO1_MISO
TRUE
LPC_FRAME_L
SPIROM_USE_MLB
PM_CLKRUN_L
SPI_ALT_CLK
SPI_ALT_CS_L
LPC_SERIRQ
LPC_PWRDWN_L
SMC_TDI
SMC_TCK
SMC_RESET_L
SMC_ROMBOOT
SMC_RX_L
SMC_TMS
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
46
TRUE
15 16
TRUE
69
TRUE
37 38
TRUE
TRUE
46
(Need 2 TPs)
25
56 60 62
25
56 60
25
56 60
64 25
56 60
64 25
56 60
25
56 60
25
56 60
64 25
60
64 25
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
14 64
14 64
D
14 64
14 64
14 64
CPU/PCH
14 64
14 64
14 64
14 64
5
5
12 64
13 64
14 64
14 64
NC_SMC_SYS_LED
NC_IR_RX_OUT_RC
NC_USB_SMCP
NC_USB_SMCN
NC_SMC_GFX_OVERTEMP
NC_SMC_GFX_THROTTLE_L
NC_SMC_FAN_1_CTL
NC_SMC_FAN_1_TACH
NC_SMC_FAN_5_CTL
NC_ENET_ASF_GPIO
NC_SMC_MPM5_LED_PWR
NC_SMC_MPM5_LED_CHG
NC_SMC_T25_EN_L
NC_SMC_DP_HPD_L
NC_SMBUS_SMC_4_ASF_SCL
NC_SMBUS_SMC_4_ASF_SDA
NC_BDV_BKL_PWM
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TBT_B_R2D_C_P & lt; 1..0 & gt;
TBT_B_R2D_C_N & lt; 1..0 & gt;
TBT_B_D2R_P & lt; 1..0 & gt;
TBT_B_D2R_N & lt; 1..0 & gt;
NC_TBT_B_LSTX
NC_DP_TBTPB_ML_CP & lt; 3..1:2 & gt;
NC_DP_TBTPB_ML_CN & lt; 3..1:2 & gt;
NC_DP_TBTPB_AUXCH_CP
NC_DP_TBTPB_AUXCH_CN
TP_DP_TBTSRC_ML_CP & lt; 3 & gt;
TP_DP_TBTSRC_ML_CN & lt; 3 & gt;
TP_DP_TBTSRC_ML_CP & lt; 2 & gt;
TP_DP_TBTSRC_ML_CN & lt; 2 & gt;
NC_DP_TBTSRC_ML_CP & lt; 1 & gt;
NC_DP_TBTSRC_ML_CN & lt; 1 & gt;
TP_DP_TBTSRC_ML_CP & lt; 0 & gt;
TP_DP_TBTSRC_ML_CN & lt; 0 & gt;
NC_DP_TBTSRC_AUXCH_CP
NC_DP_TBTSRC_AUXCH_CN
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
NC_SMC_SYS_LED
NC_IR_RX_OUT_RC
NC_USB_SMCP
NC_USB_SMCN
NC_SMC_GFX_OVERTEMP
NC_SMC_GFX_THROTTLE_L
NC_SMC_FAN_1_CTL
NC_SMC_FAN_1_TACH
NC_SMC_FAN_5_CTL
NC_ENET_ASF_GPIO
NC_SMC_MPM5_LED_PWR
NC_SMC_MPM5_LED_CHG
NC_SMC_T25_EN_L
NC_SMC_DP_HPD_L
NC_SMBUS_SMC_4_ASF_SCL
NC_SMBUS_SMC_4_ASF_SDA
NC_BDV_BKL_PWM
14 64
37 64
64
64
64
37 64
37 64
37 64
37 64
37 64
SMC
64
64
64
C
37 64
37 64
37 64
37 64
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
NC_TBT_B_R2D_CP & lt; 1..0 & gt;
NC_TBT_B_R2D_CN & lt; 1..0 & gt;
NC_TBT_B_D2RP & lt; 1..0 & gt;
NC_TBT_B_D2RN & lt; 1..0 & gt;
NC_TBT_B_LSTX
NC_DP_TBTPB_ML_CP & lt; 3..1:2 & gt;
NC_DP_TBTPB_ML_CN & lt; 3..1:2 & gt;
NC_DP_TBTPB_AUXCH_CP
NC_DP_TBTPB_AUXCH_CN
NC_DP_TBTSRC_ML_CP & lt; 3 & gt;
NC_DP_TBTSRC_ML_CN & lt; 3 & gt;
NC_DP_TBTSRC_ML_CP & lt; 2 & gt;
NC_DP_TBTSRC_ML_CN & lt; 2 & gt;
NC_DP_TBTSRC_ML_CP & lt; 1 & gt;
NC_DP_TBTSRC_ML_CN & lt; 1 & gt;
NC_DP_TBTSRC_ML_CP & lt; 0 & gt;
NC_DP_TBTSRC_ML_CN & lt; 0 & gt;
NC_DP_TBTSRC_AUXCH_CP
NC_DP_TBTSRC_AUXCH_CN
37 64
25
25
25
25
25 64
64 71
64 71
25 64 71
25 64 71
TBT
25 64
25 64
25 64
25 64
B
60
60 67
60 67
60 67
60 67
Unused nets with offpage
56
56
(Nets with offpages not used on this project)
46
15 37
J1800: XDP Connector
13 37
FUNC_TEST
37 38
I776
TRUE
I777
TRUE
I778
TRUE
37 38
I779
TRUE
37 38 46
I780
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
I789
TRUE
I790
TRUE
I791
TRUE
37 38 46
37 38 46 50
I792
TRUE
(Only a subset are needed
for FCT HVM test fixture)
XDP_CPU_TCK
XDP_PCH_TCK
XDP_CPU_TDI
XDP_CPU_TDO
XDP_CPUPCH_TRST_L
XDP_CPU_TMS
XDP_PCH_TMS
XDP_PCH_TDI
XDP_PCH_TDO
XDP_CPU_PREQ_L
XDP_CPU_PRDY_L
XDP_CPU_VCCST_PWRGD
PM_RSMRST_L
XDP_SYS_PWROK
PM_SYSRST_L
CPU_CFG & lt; 3 & gt;
PP1V05_S0
PCH_BT_UART_D2R
PCH_BT_UART_R2D
PCH_BT_UART_RTS_L
PCH_BT_UART_CTS_L
AUD_SPI_CS_L
AUD_SPI_CLK
AUD_SPI_MISO
AUD_SPI_MOSI
HDMITBTMUX_LATCH
HDD_PWR_EN
WOL_EN
BT_PWRRST_L
HDMITBTMUX_FLAG
FW_PWR_EN
FW_PME_L
ENET_MEDIA_SENSE
LCD_PSR_EN
LCD_IRQ_L
ODD_PWR_EN_L
ENET_LOW_PWR
AUD_IP_PERIPHERAL_DET
AUD_I2C_INT_L
AP_PCIE_DEV_WAKE
6 16 67
12 16 69
6 16 67
6 16 67
6 12 16 67
6 16 67
12 16 69
12 16 69
12 16 69
6 16 67
6 16 67
16
13 59
16
13 17 37
6 16 67
6 8 11 15 16 17 38 42 51 55 58
59 62 64
(Need to add 2 GND TPs)
GND
8
TRUE
TRUE
12 64
14 64
60
(Need to add 2 GND TPs)
I788
TRUE
TRUE
12 64
(Need 2 TPs)
46
I787
I793
TRUE
64
60
KBDLED_ANODE
KBDLED_FB
TRUE
13 37
I786
A
TRUE
64
J7715: KB BKLT Connector
I785
(Need to add 6 GND TPs)
TRUE
NC_PCIE_CLK100M_SDP
NC_PCIE_CLK100M_SDN
NC_PCIE_CLK100M_FWP
NC_PCIE_CLK100M_FWN
NC_PCIE_FW_D2RP
NC_PCIE_FW_D2RN
NC_PCIE_FW_R2D_CP
NC_PCIE_FW_R2D_CN
NC_USB_IRP
NC_USB_IRN
NC_USB_CAMERAP
NC_USB_CAMERAN
NC_USB_SDP
NC_USB_SDN
NC_INT_ML_CP & lt; 3..1 & gt;
NC_INT_ML_CN & lt; 3..1 & gt;
NC_HDA_SDIN1
NC_PCI_PME_L
NC_CLINK_CLK
NC_CLINK_DATA
NC_CLINK_RESET_L
FUNC_TEST
15 46
I784
TRUE
TRUE
14 37 69
I783
TRUE
TRUE
TRUE
37 38
I782
TRUE
TRUE
TRUE
(Need to add 5 GND TPs)
I781
TRUE
TRUE
32 72
(Need to add TBD GND TPs)
B
NC_PCIE_CLK100M_SDP
NC_PCIE_CLK100M_SDN
NC_PCIE_CLK100M_FWP
NC_PCIE_CLK100M_FWN
NC_PCIE_FW_D2RP
NC_PCIE_FW_D2RN
NC_PCIE_FW_R2D_CP
NC_PCIE_FW_R2D_CN
NC_USB_IRP
NC_USB_IRN
NC_USB_CAMERAP
NC_USB_CAMERAN
NC_USB_SDP
NC_USB_SDN
DP_INT_ML_C_P & lt; 3..1 & gt;
DP_INT_ML_C_N & lt; 3..1 & gt;
NC_HDA_SDIN1
NC_PCI_PME_L
NC_CLINK_CLK
NC_CLINK_DATA
NC_CLINK_RESET_L
36 37 40 44 73
30
30 37
1
7
6
5
4
3
15
15
15
15
15
15
15
15
13
15
14
15
13
SYNC_MASTER=WILL_J43
SYNC_DATE=12/17/2012
PAGE TITLE
Func Test / No Test
DRAWING NUMBER
15
Apple Inc.
15
R
& lt; E4LABEL & gt;
15
13
13
13
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
BRANCH
& lt; BRANCH & gt;
PAGE
104 OF 121
SHEET
64 OF 76
1
A
8
7
6
5
4
3
2
1
Functional Test Points
SD Card Aliases
J9500: LIO Connector
MAKE_BASE
FUNC_TEST
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
D
68 65 34 14
PP3V42_G3H
PP3V3_S0
PP1V5_S0SW_AUDIO
SYS_ONEWIRE
SMC_BC_ACOK
USB_PWR_EN
SMBUS_SMC_2_S3_SDA
SMBUS_SMC_2_S3_SCL
SPKRAMP_SHDN_L
TRUE
TRUE
TRUE
17 30 35 36 37 38 40 46 49 50
59 61 62 64
62 64 74
8 11 12 13 15 17 18 26 30 36 38
39 40 41 42 43 44 45 56 59 61
58 61
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
68 65 34 14
68 65 34 14
TRUE
TRUE
TRUE
TRUE
USB3_SD_D2R_P
USB3_SD_D2R_N
USB3_SD_R2D_C_P
USB3_SD_R2D_C_N
14 34 65 68
14 34 65 68
14 34 65 68
14 34 65 68
37 61
65 39 37 34 15
37 38 50 61
PP3V3_S0SW_SD
PP3V3_S0SW_SD
15 34 37 39 65
D
(MAKE_BASE=TRUE on page 45)
35 59 61
37 40 61 73
37 40 61 73
47 61
FINSTACKSNS_ALERT_L
SPKRAMP_INR_N
SPKRAMP_INR_P
USB_EXTB_N
USB_EXTB_P
PP5V_S0_ALT_AUD_LDO_EN
SMC_lID
HDA_SDOUT
HDA_BIT_CLK
HDA_SDIN0
XDP_USB_EXTB_OC_L
HDA_RST_L
HDA_SYNC
USB3_EXTB_D2R_RC_P
USB3_EXTB_D2R_RC_N
USB3_EXTB_R2D_P
USB3_EXTB_R2D_N
AUD_PWR_EN
TRUE
68 65 34 14
USB3_SD_D2R_P
USB3_SD_D2R_N
USB3_SD_R2D_C_P
USB3_SD_R2D_C_N
39 61
47 61 74
47 61 74
14 61 68
14 61 68
61
36 37 38 61 64
12 61 69
12 61 69
12 61 69
14 16 61
12 61 69
12 61 69
61 65 68
61 65 68
61 65 68
61 65 68
13 59 61
(Need to add 5 GND TPs)
C
C
Bead Probes
68 61 14
68 61 14
68 65 61
68 65 61
68 61 14
68 61 14
68 65 61
68 65 61
USB3_EXTB_D2R_N
USB3_EXTB_D2R_P
USB3_EXTB_D2R_RC_N
USB3_EXTB_D2R_RC_P
USB3_EXTB_R2D_C_N
USB3_EXTB_R2D_C_P
USB3_EXTB_R2D_N
USB3_EXTB_R2D_P
1
TP
1
TP
1
TP
1
TP
1
TP
1
TP
1
TP
1
TP
BEAD-PROBE
BEAD-PROBE
BEAD-PROBE
BEAD-PROBE
BEAD-PROBE
BEAD-PROBE
BEAD-PROBE
BEAD-PROBE
BPA511
BPA510
BPA520
BPA521
BPA513
BPA512
BPA523
BPA522
B
B
A
SYNC_MASTER=J41_MLB
SYNC_DATE=09/13/2012
PAGE TITLE
Project FCT/NC/Aliases
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
105 OF 121
SHEET
65 OF 76
1
A
8
7
6
5
4
3
2
1
J41/J43 Board-Specific Spacing & Physical Constraints
TABLE_BOARD_INFO
BOARD LAYERS
BOARD AREAS
BOARD UNITS
(MIL or MM)
ALLEGRO
VERSION
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM
NO_TYPE,BGA,MEM_TERM
MM
16.2
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
DEFAULT
TOP,BOTTOM
Y
=50_OHM_SE
=50_OHM_SE
DEFAULT
ISL2,ISL11
Y
=45_OHM_SE
=45_OHM_SE
DEFAULT
ISL3,ISL10
Y
=45_OHM_SE
=45_OHM_SE
DEFAULT
ISL4,ISL9
Y
=45_OHM_SE
=45_OHM_SE
DEFAULT
*
N
100 MM
100 MM
10 MM
0 MM
0 MM
STANDARD
*
=DEFAULT
=DEFAULT
=DEFAULT
=DEFAULT
=DEFAULT
=DEFAULT
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
D
D
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
Single-ended Physical Constraints
Spacing Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
0.100 MM
?
TABLE_PHYSICAL_RULE_ITEM
27P4_OHM_SE
TOP,BOTTOM
Y
0.310 MM
0.310 MM
TABLE_SPACING_RULE_ITEM
1:1_SPACING
*
TABLE_PHYSICAL_RULE_ITEM
27P4_OHM_SE
ISL2,ISL11
Y
0.182 MM
27P4_OHM_SE
ISL3,ISL10
Y
0.182 MM
0.182 MM
0.182 MM
27P4_OHM_SE
ISL4,ISL9
Y
0.182 MM
0.182 MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LINE-TO-LINE SPACING
WEIGHT
1x_DIELECTRIC
TOP,BOTTOM
LAYER
0.071 MM
?
1x_DIELECTRIC
ISL3,ISL10
0.053 MM
?
1x_DIELECTRIC
ISL4,ISL9
0.050 MM
?
1x_DIELECTRIC
*
0.090 MM
?
LINE-TO-LINE SPACING
WEIGHT
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
27P4_OHM_SE
*
N
100 MM
100 MM
=STANDARD
=STANDARD
=STANDARD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
35_OHM_SE
TOP,BOTTOM
Y
0.195 MM
0.195 MM
35_OHM_SE
ISL2,ISL11
Y
0.125 MM
0.125 MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
TABLE_PHYSICAL_RULE_ITEM
DEFAULT
Y
0.125 MM
0.125 MM
ISL4,ISL9
Y
0.125 MM
0.125 MM
35_OHM_SE
*
N
100 MM
100 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
0.1 MM
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
*
*
BGA
BGA_P075MM
=DEFAULT
?
*
0.075 MM
TABLE_SPACING_ASSIGNMENT_ITEM
?
*
BGA_P075MM
ISL3,ISL10
*
STANDARD
35_OHM_SE
35_OHM_SE
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
TABLE_SPACING_RULE_ITEM
?
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_ASSIGNMENT_HEAD
NET_PHYSICAL_TYPE
AREA_TYPE
PHYSICAL_RULE_SET
*
BGA
P070MM_BGA
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
C
C
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
P070MM_BGA
40_OHM_SE
TOP,BOTTOM
Y
0.170 MM
0.170 MM
40_OHM_SE
ISL2,ISL11
Y
0.096 MM
40_OHM_SE
ISL3,ISL10
Y
0.096 MM
ISL4,ISL9
Y
0.099 MM
*
N
100 MM
100 MM
=STANDARD
=STANDARD
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
45_OHM_SE
TOP,BOTTOM
Y
0.135 MM
0.135 MM
45_OHM_SE
ISL2,ISL11
Y
0.075 MM
0.075 MM
=STANDARD
PHYSICAL_RULE_SET
5 MM
0.099 MM
40_OHM_SE
0.070 MM
0.096 MM
40_OHM_SE
*
0.096 MM
0.075 MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
45_OHM_SE
ISL3,ISL10
Y
0.075 MM
0.075 MM
45_OHM_SE
ISL4,ISL9
Y
0.080 MM
0.080 MM
45_OHM_SE
*
N
100 MM
100 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
50_OHM_SE
TOP,BOTTOM
Y
0.110 MM
0.110 MM
50_OHM_SE
*
N
100 MM
100 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
55_OHM_SE
TOP,BOTTOM
Y
0.090 MM
0.090 MM
55_OHM_SE
*
N
100 MM
100 MM
=STANDARD
=STANDARD
=STANDARD
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
B
=STANDARD
=STANDARD
=STANDARD
B
TABLE_PHYSICAL_RULE_HEAD
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
Differential Pair Physical Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
73_OHM_DIFF
TOP,BOTTOM
Y
0.165 MM
73_OHM_DIFF
ISL2,ISL11
Y
73_OHM_DIFF
ISL3,ISL10
73_OHM_DIFF
73_OHM_DIFF
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
0.165 MM
0.150 MM
0.150 MM
0.106 MM
0.106 MM
0.150 MM
0.150 MM
Y
0.106 MM
0.106 MM
0.150 MM
0.150 MM
ISL4,ISL9
Y
0.110 MM
0.110 MM
0.150 MM
0.150 MM
*
N
100 MM
100 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
85_OHM_DIFF
TOP,BOTTOM
Y
0.120 MM
0.120 MM
0.150 MM
0.150 MM
85_OHM_DIFF
ISL2,ISL11
Y
0.078 MM
0.078 MM
0.160 MM
0.160 MM
85_OHM_DIFF
ISL3,ISL10
Y
0.078 MM
0.078 MM
0.160 MM
0.160 MM
85_OHM_DIFF
ISL4,ISL9
Y
0.082 MM
0.082 MM
0.140 MM
0.140 MM
85_OHM_DIFF
*
N
100 MM
100 MM
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
70_OHM_DIFF
TOP,BOTTOM
Y
0.165 MM
0.165 MM
0.110 MM
0.110 MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
70_OHM_DIFF
ISL2,ISL11
Y
0.105 MM
0.105 MM
0.100 MM
0.100 MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
70_OHM_DIFF
ISL3,ISL10
Y
0.105 MM
0.105 MM
0.100 MM
0.100 MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
70_OHM_DIFF
ISL4,ISL9
Y
0.110 MM
0.110MM
0.095 MM
0.095 MM
70_OHM_DIFF
*
N
100 MM
100 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
80_OHM_DIFF
TOP,BOTTOM
Y
0.132 MM
0.132 MM
0.130 MM
0.130 MM
80_OHM_DIFF
ISL2,ISL11
Y
0.081 MM
0.081 MM
0.115 MM
0.115 MM
80_OHM_DIFF
ISL3,ISL10
Y
0.081 MM
0.081 MM
0.115 MM
0.115 MM
80_OHM_DIFF
ISL4,ISL9
Y
0.088 MM
0.088 MM
0.110 MM
TABLE_PHYSICAL_RULE_ITEM
0.110 MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
A
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
SYNC_MASTER=CONSTRAINTS
SYNC_DATE=10/24/2012
TABLE_PHYSICAL_RULE_ITEM
80_OHM_DIFF
*
N
100 MM
100 MM
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
=STANDARD
=STANDARD
PAGE TITLE
PCB Rule Definitions
DRAWING NUMBER
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
Apple Inc.
TABLE_PHYSICAL_RULE_ITEM
90_OHM_DIFF
TOP,BOTTOM
Y
0.115 MM
0.115 MM
0.200 MM
0.200 MM
90_OHM_DIFF
ISL2,ISL11
Y
0.070 MM
0.070 MM
0.180 MM
0.180 MM
R
& lt; E4LABEL & gt;
TABLE_PHYSICAL_RULE_ITEM
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
TABLE_PHYSICAL_RULE_ITEM
90_OHM_DIFF
ISL3,ISL10
Y
0.070 MM
0.070 MM
0.180 MM
0.180 MM
90_OHM_DIFF
ISL4,ISL9
Y
0.076 MM
0.076 MM
0.180 MM
0.180 MM
90_OHM_DIFF
*
N
100 MM
100 MM
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
8
7
=STANDARD
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
BRANCH
& lt; BRANCH & gt;
PAGE
110 OF 121
SHEET
66 OF 76
1
A
8
7
6
5
CPU Signal Constraints
4
3
2
1
CPU Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
CPU_45S
*
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=STANDARD
NET_TYPE
DIFFPAIR NECK GAP
=STANDARD
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
CPU_27P4S
*
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
0.100 MM
CPU_PECI
0.100 MM
SPACING_RULE_SET
LINE-TO-LINE SPACING
WEIGHT
CPU_AGTL
TOP,BOTTOM
LAYER
=2x_DIELECTRIC
*
=STANDARD
CPU_AGTL
CPU_45S
CPU_AGTL
?
CPU_AGTL
CPU_COMP
CPU_45S
PM_MEM_PWRGD
TABLE_SPACING_RULE_HEAD
CPU_45S
PM_SYNC
=27P4_OHM_SE
?
back to TABLE_SPACING_RULE
CPU_45S
CPU_ITP
CPU_45S
CPU_ITP
CPU_45S
CPU_ITP
CPU_27P4S
CPU_COMP
CPU_27P4S
CPU_COMP
CPU_SM_RCOMP
CPU_27P4S
CPU_COMP
CPU_SM_RCOMP
CPU_27P4S
CPU_COMP
CPU_SM_RCOMP
CPU_27P4S
CPU_COMP
CPU_45S
CPU_ITP
CPU_45S
CPU_AGTL
once rdar://10308147 is resolved
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
*
*
CPU_8MIL_2ANY
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
CPU_8MIL_2ANY
*
8 MIL
?
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_ASSIGNMENT_ITEM
CPU_ITP
*
*
CPU_ITP_2ANY
TABLE_SPACING_RULE_ITEM
CPU_ITP_2ANY
*
=4x_DIELECTRIC
?
CPU_CATERR_L
CPU_45S
*
CPU_COMP_2SELF
LAYER
*
CPU_8MIL
CLK_PCIE_80D
CLK_PCIE
CLK_PCIE_80D
CLK_PCIE
DPLL_REF_CLK120M
CLK_PCIE_80D
CLK_PCIE
CLK_PCIE_80D
CLK_PCIE
ITPCPU_CLK100M
CLK_PCIE_80D
CLK_PCIE
ITPCPU_CLK100M
CLK_PCIE_80D
CLK_PCIE
CLK_PCIE_80D
CLK_PCIE
CLK_PCIE_80D
CLK_PCIE
ITPCPU_CLK100M
CLK_PCIE_80D
CLK_PCIE
ITPCPU_CLK100M
WEIGHT
=6x_DIELECTRIC
CLK_PCIE_80D
CLK_PCIE
CPU_45S
CPU_ITP
?
TABLE_SPACING_RULE_ITEM
CPU_COMP_2SELF
CPU_COMP_2OTHER
CPU_45S
DMI_CLK100M
LINE-TO-LINE SPACING
TOP,BOTTOM
TABLE_SPACING_ASSIGNMENT_ITEM
*
CPU_AGTL
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
CPU_COMP
CPU_45S
XDP_TDI
CPU_COMP
CPU_PWRGD
ITPCPU_CLK100M
CPU_COMP
CPU_AGTL
ITPCPU_CLK100M
SPACING_RULE_SET
CPU_AGTL
DPLL_REF_CLK120M
AREA_TYPE
CPU_45S
DMI_CLK100M
NET_SPACING_TYPE2
CPU_PROCHOT_L
PM_THRMTRIP_L
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
TABLE_SPACING_RULE_ITEM
CPU_COMP_2OTHER
TOP,BOTTOM
=10x_DIELECTRIC
?
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
CPU_COMP_2SELF
*
=4x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
CPU_COMP_2OTHER
*
=6x_DIELECTRIC
?
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_ASSIGNMENT_ITEM
CPU_VCCSENSE
CPU_VCCSENSE
*
CPU_VCCSENSE_2SELF
TABLE_SPACING_RULE_ITEM
TOP,BOTTOM
CPU_VCCSENSE_2SELF
=6x_DIELECTRIC
?
TABLE_SPACING_ASSIGNMENT_ITEM
CPU_VCCSENSE
*
*
TABLE_SPACING_RULE_ITEM
TOP,BOTTOM
=10x_DIELECTRIC
?
C
LAYER
CPU_45S
CPU_ITP
CPU_45S
CPU_ITP
CPU_45S
?
CPU_ITP
CPU_ITP
CPU_ITP
WEIGHT
=4x_DIELECTRIC
CPU_45S
XDP_BPM_L
LINE-TO-LINE SPACING
CPU_ITP
CPU_45S
SPACING_RULE_SET
CPU_ITP
CPU_45S
XDP_TCK
TABLE_SPACING_RULE_HEAD
CPU_45S
XDP_TRST_L
CPU_VCCSENSE_2OTHER
XDP_TDO
XDP_TMS
CPU_VCCSENSE_2OTHER
XDP_DBRESET_L
XDP_CPU_PRDY_L
XDP_CPU_PREQ_L
16 17
6 16 64
6 16 64
D
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
CPU_8MIL
6 38
Note: CPU_8MIL and CPU_ITP can be converted
TABLE_SPACING_RULE_ITEM
D
CPU_PECI
PM_SYNC
PM_MEM_PWRGD
TABLE_SPACING_RULE_ITEM
*
CPU_VCCSENSE_2SELF
TABLE_SPACING_RULE_ITEM
*
CPU_VCCSENSE_2OTHER
=6x_DIELECTRIC
?
CPU_45S
CPU_ITP
(FSB_CPURST_L)
CPU_45S
CPU_ITP
CPU_VCCSENSE
SENSE_1TO1_P2MM
CPU_VCCSENSE
PCI-Express Interface Constraints
EDP_COMP
CPU_PEG_COMP
CPU_SM_RCOMP & lt; 0 & gt;
CPU_SM_RCOMP & lt; 1 & gt;
CPU_SM_RCOMP & lt; 2 & gt;
CPU_CFG & lt; 11..0 & gt;
CPU_CATERR_L
CPU_VCCIO_SEL
CPU_PROCHOT_L
CPU_PWRGD
PM_THRMTRIP_L
DMI_CLK100M_CPU_P
DMI_CLK100M_CPU_N
DPLL_REF_CLKP
DPLL_REF_CLKN
ITPCPU_CLK100M_P
ITPCPU_CLK100M_N
ITPXDP_CLK100M_P
ITPXDP_CLK100M_N
XDP_CPU_CLK100M_P
XDP_CPU_CLK100M_N
XDP_CPU_TDI
XDP_CPU_TDO
XDP_CPU_TMS
XDP_CPU_TCK
XDP_CPUPCH_TRST_L
XDP_BPM_L & lt; 1..0 & gt;
XDP_BPM_L & lt; 7..2 & gt;
XDP_OBSDATA_B & lt; 3..0 & gt;
CPU_CFG & lt; 15..12 & gt;
XDP_CPURST_L
6
6
6
6 16 64
6 37
6 37 38 51
6
15 38
6 16 64
6 16 64
6 16 64
6 16 64
C
6 12 16 64
6 16
6 16
6 16
16
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
PCIE_80D
*
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
CLK_PCIE_80D
*
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
CPU_VCCSENSE
SENSE_1TO1_P2MM
CPU_VCCSENSE
CPU_VCCIOSENSE
SENSE_1TO1_P2MM
CPU_VCCSENSE
CPU_VCCIOSENSE
SENSE_1TO1_P2MM
CPU_VCCSENSE
CPU_AXG_SENSE
SENSE_1TO1_P2MM
CPU_VCCSENSE
CPU_AXG_SENSE
SENSE_1TO1_P2MM
CPU_VCCSENSE
CPU_VALSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_VALSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_VALSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_VALSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_VALSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_VALSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_SVIDALERT_L
CPU_45S
CPU_COMP
CPU_SVIDSCLK
CPU_45S
CPU_COMP
CPU_SVIDSOUT
CPU_45S
CPU_COMP
PCIE_CPU_SSD_R2D
PCIE_80D
PCIE_CPU_TX
PCIE_CPU_SSD_R2D
PCIE_80D
PCIE_CPU_TX
PCIE_80D
PCIE_CPU_TX
PCIE_80D
PCIE_CPU_TX
PCIE_80D
PCIE_CPU_RX
TABLE_PHYSICAL_RULE_ITEM
PCIE Clock Spacing
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_ASSIGNMENT_ITEM
CLK_PCIE
CLK_PCIE
*
CLK_PCIE_2SELF
TABLE_SPACING_RULE_ITEM
CLK_PCIE_2SELF
TOP,BOTTOM
=6x_DIELECTRIC
?
TABLE_SPACING_ASSIGNMENT_ITEM
CLK_PCIE
*
*
CLK_PCIE_2OTHER
TABLE_SPACING_RULE_ITEM
CLK_PCIE_2OTHER
TOP,BOTTOM
=10x_DIELECTRIC
?
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
CPU_VCCSENSE_P
CPU_VCCSENSE_N
CPU_VCCIOSENSE_P
CPU_VCCIOSENSE_N
CPU_AXG_SENSE_P
CPU_AXG_SENSE_N
CPU_VDDQ_SENSE_P
CPU_VDDQ_SENSE_N
CPU_AXG_VALSENSE_P
CPU_AXG_VALSENSE_N
CPU_VCC_VALSENSE_P
CPU_VCC_VALSENSE_N
8 51
9 51
TABLE_SPACING_RULE_ITEM
CLK_PCIE_2SELF
*
=4x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
CLK_PCIE_2OTHER
*
=6x_DIELECTRIC
?
CPU PCIE Spacing
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
PCIE_CPU_TX
PCIE_CPU_TX
*
PCIE_TX2TX
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=5x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
PCIE_TX2TX
TOP,BOTTOM
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_CPU_RX
PCIE_CPU_RX
*
PCIE_RX2RX
TABLE_SPACING_RULE_ITEM
PCIE_RX2RX
TOP,BOTTOM
=5x_DIELECTRIC
?
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_CPU_TX
*_CPU_TX
*
PCIE_TX2OTHERTX
TABLE_SPACING_RULE_ITEM
PCIE_TX2OTHERTX
TOP,BOTTOM
=5x_DIELECTRIC
?
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
*_CPU_RX
*
PCIE_RX2OTHERRX
PCIE_CPU_TX
*_CPU_RX
*
PCIE_TX2RX
PCIE_RX2OTHERRX
TOP,BOTTOM
=5x_DIELECTRIC
TOP,BOTTOM
=7x_DIELECTRIC
?
PCIE_CPU_RX
PCIE_80D
PCIE_CPU_RX
PCIE_CPU_SSD_D2R
PCIE_80D
PCIE_CPU_RX
?
PCIE_TX2RX
PCIE_80D
PCIE_CPU_SSD_D2R
PCIE_CPU_RX
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
*_CPU_TX
*
PCIE_RX2TX
PCIE_RX2TX
TOP,BOTTOM
=7x_DIELECTRIC
*_TX
*
PCIE_2OTHERHS
*_TX
*
PCIE_2OTHERHS
PCIE_CPU_TX
*_RX
*
TOP,BOTTOM
=6x_DIELECTRIC
CLK_PCIE
CLK_PCIE_80D
CLK_PCIE
I212
DP_TBT_ML
DP_80D
DP_TX
I211
DP_TBT_ML
?
TABLE_SPACING_RULE_ITEM
PCIE_2OTHER
TOP,BOTTOM
?
PCIE_2OTHERHS
=5x_DIELECTRIC
DP_80D
DP_TX
I210
DP_80D
DP_TX
I209
DP_80D
DP_TX
DP_80D
DP_AUX
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_CPU_RX
*_RX
*
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
PCIE_2OTHERHS
I208
PCIE_CPU_TX
*
*
PCIE_TX2TX
*
=2.5x_DIELECTRIC
?
DP_TBT_AUXCH
I206
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
DP_TBT_AUXCH
DP_80D
DP_AUX
I207
DP_80D
DP_AUX
I205
PCIE_2OTHER
DP_80D
DP_AUX
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
*
PCIE_CPU_RX
*
PCIE_RX2RX
*
=2.5x_DIELECTRIC
?
PCIE_2OTHER
TABLE_SPACING_RULE_ITEM
PCIE_TX2OTHERTX
*
=4x_DIELECTRIC
?
PCH PCIE Spacing
I204
PCIE_RX2OTHERRX
NET_SPACING_TYPE2
AREA_TYPE
*
=4x_DIELECTRIC
?
SPACING_RULE_SET
DP_TBT_ML
DP_80D
DP_TX
I203
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
DP_TBT_ML
DP_80D
DP_TX
DP_80D
DP_TX
DP_80D
DP_TX
TABLE_SPACING_RULE_ITEM
PCIE_TX2RX
*
=6x_DIELECTRIC
?
PCIE_RX2TX
*
=6x_DIELECTRIC
I202
?
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_PCH_TX
PCIE_PCH_TX
*
PCIE_PCH_RX
*
I201
TABLE_SPACING_RULE_ITEM
PCIE_TX2TX
PCIE_PCH_RX
PCIE_RX2RX
I200
DP_TBT_AUXCH
DP_80D
DP_AUX
I199
DP_TBT_AUXCH
DP_80D
DP_AUX
I198
DP_80D
DP_AUX
I197
DP_80D
DP_AUX
DP_INT_ML
DP_80D
DP_TX
DP_INT_ML
DP_80D
DP_TX
DP_80D
DP_TX
DP_80D
TABLE_SPACING_ASSIGNMENT_ITEM
DP_TX
DP_80D
DP_AUX
TABLE_SPACING_RULE_ITEM
PCIE_2OTHERHS
*
=4x_DIELECTRIC
?
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_PCH_TX
*_PCH_TX
*
*_PCH_RX
*
TABLE_SPACING_RULE_ITEM
PCIE_TX2OTHERTX
PCIE_PCH_RX
8 51
PCIE_SSD_R2D_C_P & lt; 3..0 & gt;
PCIE_SSD_R2D_C_N & lt; 3..0 & gt;
PCIE_SSD_R2D_P & lt; 3..0 & gt;
PCIE_SSD_R2D_N & lt; 3..0 & gt;
PCIE_SSD_D2R_C_P & lt; 3..0 & gt;
PCIE_SSD_D2R_C_N & lt; 3..0 & gt;
PCIE_SSD_D2R_P & lt; 3..0 & gt;
PCIE_SSD_D2R_N & lt; 3..0 & gt;
PCIE_CLK100M_SSD_P
PCIE_CLK100M_SSD_N
12 30
12 30
30 64
B
30 64
12 30 64
12 30 64
12 30 64
DP_TBTSNK0_ML_P & lt; 3..0 & gt;
DP_TBTSNK0_ML_N & lt; 3..0 & gt;
DP_TBTSNK0_ML_C_P & lt; 3..0 & gt;
DP_TBTSNK0_ML_C_N & lt; 3..0 & gt;
DP_TBTSNK0_AUXCH_P
DP_TBTSNK0_AUXCH_N
DP_TBTSNK0_AUXCH_C_P
DP_TBTSNK0_AUXCH_C_N
PCIe SSD
12 30 64
DP_TBTSNK1_ML_P & lt; 3..0 & gt;
DP_TBTSNK1_ML_N & lt; 3..0 & gt;
DP_TBTSNK1_ML_C_P & lt; 3..0 & gt;
DP_TBTSNK1_ML_C_N & lt; 3..0 & gt;
DP_TBTSNK1_AUXCH_P
DP_TBTSNK1_AUXCH_N
DP_TBTSNK1_AUXCH_C_P
DP_TBTSNK1_AUXCH_C_N
25
25
5 25
5 25
25
25
13 25
13 25
25
25
5 18 25
5 18 25
25
25
13 18 25
PCIE_RX2OTHERRX
PCIE_2OTHER
*
=3x_DIELECTRIC
?
TABLE_SPACING_ASSIGNMENT_ITEM
A
8 51
TABLE_SPACING_RULE_ITEM
PCIE_2OTHERHS
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_CPU_RX
CLK_PCIE_80D
?
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_CPU_TX
PCIE_CLK100M_SSD
PCIE_CLK100M_SSD
PCIE_CPU_RX
8 51
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
B
CPU_VIDALERT_L
CPU_VIDSCLK
CPU_VIDSOUT
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_PCH_TX
*_PCH_RX
*
PCIE_TX2RX
PCIE_PCH_RX
*_PCH_TX
*
PCIE_RX2TX
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_PCH_TX
*_TX
*
*_TX
*
PCIE_2OTHERHS
13 18 25
60 64
SYNC_MASTER=CONSTRAINTS
60 64
SYNC_DATE=09/25/2012
PAGE TITLE
5 60 64
CPU Constraints
5 60 64
PCIE_2OTHERHS
PCIE_PCH_RX
DP_INT_ML_P & lt; 3..0 & gt;
DP_INT_ML_N & lt; 3..0 & gt;
DP_INT_ML_C_P & lt; 3..0 & gt;
DP_INT_ML_C_N & lt; 3..0 & gt;
DRAWING NUMBER
TABLE_SPACING_ASSIGNMENT_ITEM
I215
*_RX
*
*_RX
*
DP_INT_AUXCH
DP_80D
DP_AUX
DP_80D
DP_AUX
DP_80D
DP_AUX
DP_80D
DP_AUX
DP_80D
Note: DisplayPort tables are on Page 113
PCIE_2OTHERHS
PCIE_PCH_RX
I214
DP_INT_AUXCH
PCIE_PCH_TX
DP_INT_AUXCH
DP_INT_AUXCH
TABLE_SPACING_ASSIGNMENT_ITEM
DP_AUX
PCIE_2OTHERHS
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_PCH_TX
*
*
PCIE_2OTHER
PCIE_PCH_RX
*
*
DP_INT_AUX_CH_C_P
DP_INT_AUX_CH_C_N
DP_INT_AUXCH_C_P
DP_INT_AUXCH_C_N
DP_INT_AUXCH_P
DP_INT_AUXCH_N
PCIE_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
SOURCE: 471984_Chief_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.
8
7
6
5
4
3
60 64
Apple Inc.
DP
60 64
5 60
R
NOTICE OF PROPRIETARY PROPERTY:
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
5 60
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
PAGE
111 OF 121
SHEET
67 OF 76
1
A
8
7
6
5
SATA Interface Constraints
4
3
2
1
PCH Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
SATA_80D
*
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
SPACING_RULE_SET
LAYER
NET_TYPE
DIFFPAIR NECK GAP
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
WEIGHT
=4x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
SATA_ICOMP
*
D
D
SATA_ICOMP
PCH_SATAICOMP
USB_HUB1_UP
USB_80D
USB
USB_HUB1_UP
USB_80D
USB
USB_BT
USB_80D
USB
USB_BT
USB_80D
USB
USB_80D
USB
USB_80D
USB
USB_80D
USB
USB_80D
USB
USB_TPAD
USB_80D
USB
USB_TPAD
USB_80D
USB
USB_80D
USB
USB_80D
USB
USB_HUB_UP_P
USB_HUB_UP_N
USB_BT_P
USB_BT_N
USB_BT_CONN_P
USB_BT_CONN_N
USB_BT_WAKE_P
USB_BT_WAKE_N
USB_TPAD_P
USB_TPAD_N
USB_TPAD_CONN_P
USB_TPAD_CONN_N
USB_80D
USB
USB_80D
USB
USB_TPAD_M
USB_80D
USB
USB_TPAD_M
USB_80D
USB
USB_SDCARD
USB_80D
USB
USB_SDCARD
USB_80D
USB
SPI_45S
SPI
SPI_45S
SPI
SPI_45S
SPI
PCH_SATA_ICOMP
C
SOURCE: 471984_Chief_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.
UART Interface Constraints
14 29
14 29
29 64
29 64
14 36 64
USB Hucopyb nets
14 36 64
TPAD_SPI_MOSI_USB_P
TPAD_SPI_MISO_USB_N
USB_TPAD_M_P
USB_TPAD_M_N
USB_SDCARD_P
USB_SDCARD_N
TPAD_SPI_MOSI
TPAD_SPI_MISO
TPAD_SPI_CLK
C
15 36
15 36
15 36
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
UART_45S
*
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
SPACING_RULE_SET
LAYER
TP SPI nets
TABLE_PHYSICAL_RULE_ITEM
USB_EXTA
USB_80D
USB
USB_EXTA
USB_80D
USB
UART_45S
UART
UART_45S
UART
USB2_EXTA
USB_80D
USB
USB2_EXTA
USB_80D
USB
USB2_EXTA
USB_80D
USB
USB2_EXTA
USB_80D
USB
USB3_EXTA_RX
USB_80D
USB3_PCH_RX
USB3_EXTA_RX
USB_80D
USB3_PCH_RX
USB3_EXTA_TX
USB_80D
USB3_PCH_TX
USB3_EXTA_TX
USB_80D
USB3_PCH_TX
USB_80D
USB3_PCH_RX
USB_80D
USB3_PCH_RX
USB_80D
USB3_PCH_TX
USB_80D
USB3_PCH_TX
USB_80D
USB3_PCH_TX
USB_80D
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
USB3_PCH_TX
WEIGHT
TABLE_SPACING_RULE_ITEM
UART
*
=2x_DIELECTRIC
?
USB 2.0 Interface Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
PCH_USB_RBIAS
*
=STANDARD
8 MIL
8 MIL
=STANDARD
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
USB_80D
*
SPACING_RULE_SET
LAYER
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
TABLE_SPACING_RULE_HEAD
WEIGHT
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
USB
*
=2x_DIELECTRIC
TABLE_SPACING_RULE_ITEM
?
USB
TOP,BOTTOM
=4x_DIELECTRIC
?
SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.8
USB 3.0 Interface Constraints
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
USB3_PCH_TX
USB3_PCH_TX
*
USB3_TX2TX
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=5x_DIELECTRIC
?
TOP,BOTTOM
*
USB3_RX2RX
*_PCH_TX
*
USB3_RX2RX
TOP,BOTTOM
=5x_DIELECTRIC
*_PCH_RX
*
USB3_PCH_RX
USB_80D
USB3_PCH_RX
USB_80D
USB3_PCH_RX
TABLE_SPACING_RULE_ITEM
TOP,BOTTOM
=5x_DIELECTRIC
?
USB3_RX2OTHERRX
USB3_RX2OTHERRX
USB
USB_80D
USB3_EXTB_RX
?
USB3_TX2OTHERTX
USB3_TX2OTHERTX
USB3_PCH_RX
USB
USB_80D
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
USB3_PCH_TX
USB_80D
USB_EXTB
TABLE_SPACING_RULE_ITEM
USB3_TX2TX
TABLE_SPACING_ASSIGNMENT_ITEM
USB3_PCH_RX
USB_EXTB
USB3_EXTB_RX
USB3_PCH_RX
TOP,BOTTOM
=5x_DIELECTRIC
?
USB_80D
*_PCH_TX
*
TOP,BOTTOM
=7x_DIELECTRIC
*_TX
*
*_TX
*
USB3_2OTHERHS
USB3_PCH_TX
USB3_SD_RX
USB_80D
USB3_PCH_RX
USB_80D
USB3_PCH_RX
USB_80D
USB3_PCH_TX
USB3_SD_TX
USB_80D
USB3_PCH_TX
USB_80D
USB3_PCH_RX
USB3_PCH_RX
USB_80D
USB3_PCH_TX
USB_80D
USB3_PCH_TX
TABLE_SPACING_RULE_ITEM
USB3_RX2TX
USB3_2OTHERHS
USB3_PCH_RX
USB3_PCH_TX
?
TOP,BOTTOM
=7x_DIELECTRIC
?
TABLE_SPACING_ASSIGNMENT_ITEM
USB3_PCH_TX
USB3_PCH_TX
USB_80D
USB3_TX2RX
USB3_RX2TX
USB_80D
USB_80D
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
USB3_PCH_RX
USB3_EXTB_TX
USB3_SD_TX
USB3_TX2RX
USB3_PCH_TX
USB3_SD_RX
*
USB_80D
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
*_PCH_RX
USB3_PCH_RX
USB3_EXTB_TX
USB_80D
TABLE_SPACING_ASSIGNMENT_ITEM
USB3_PCH_TX
USB3_2OTHERHS
TOP,BOTTOM
=6x_DIELECTRIC
*
TOP,BOTTOM
=5x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
USB3_2OTHERHS
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
USB3_PCH_RX
*_RX
*
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
USB3_2OTHERHS
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
USB3_PCH_TX
*
*
USB3_TX2TX
*
=2.5x_DIELECTRIC
?
USB3_2OTHER
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
USB3_PCH_RX
*
*
USB3_RX2RX
*
=2.5x_DIELECTRIC
?
USB3_2OTHER
TABLE_SPACING_RULE_ITEM
USB3_TX2OTHERTX
*
=4x_DIELECTRIC
35 37 38
35
35
35
35
14 35
USB EXTA nets (Right USB port)
14 35
35
35
14 35
USB_EXTB_P
USB_EXTB_N
USB3_EXTB_D2R_P
USB3_EXTB_D2R_N
USB3_EXTB_D2R_RC_P
USB3_EXTB_D2R_RC_N
USB3_EXTB_R2D_P
USB3_EXTB_R2D_N
USB3_EXTB_R2D_C_P
USB3_EXTB_R2D_C_N
14 35
14 61 65
14 61 65
B
14 61 65
14 61 65
61 65
61 65
61 65
61 65
USB EXTB nets (Left USB port)
14 61 65
14 61 65
USB3_RX2TX
*
=6x_DIELECTRIC
CLK_PCIE
CLK_PCIE_80D
CLK_PCIE
PCH_DIFFCLK_UNUSED_
CLK_PCIE_80D
CLK_PCIE
CLK_PCIE_80D
CLK_PCIE
PCH_DIFFCLK_UNUSED_
CLK_PCIE_80D
CLK_PCIE
PCH_DIFFCLK_UNUSED_
?
CLK_PCIE_80D
CLK_PCIE_80D
CLK_PCIE
CLK_PCIE
?
=6x_DIELECTRIC
PCH_DIFFCLK_UNUSED_
CPU_45S
=4x_DIELECTRIC
*
PCH_USB_RBIAS
PCH_DIFFCLK_UNUSED_
*
USB3_TX2RX
PCH_USB_RBIAS
PCH_DIFFCLK_UNUSED_
USB3_RX2OTHERRX
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
USB3_2OTHERHS
*
=4x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
USB3_2OTHER
*
=3x_DIELECTRIC
USB3_SD_D2R_P
USB3_SD_D2R_N
USB3_SD_R2D_C_P
USB3_SD_R2D_C_N
USB3_SD_D2R_C_P
USB3_SD_D2R_C_N
USB3_SD_R2D_P
USB3_SD_R2D_N
14 34 65
14 34 65
14 34 65
14 34 65
34
34
34
34
?
TABLE_SPACING_RULE_ITEM
A
35 37 38
?
USB3_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
*_RX
14 35
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
USB3_PCH_TX
14 35
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
B
USB_EXTA_P
USB_EXTA_N
SMC_DEBUGPRT_TX_L
SMC_DEBUGPRT_RX_L
USB2_EXTA_MUXED_P
USB2_EXTA_MUXED_N
USB2_EXTA_MUXED_F_P
USB2_EXTA_MUXED_F_N
USB3_EXTA_D2R_P
USB3_EXTA_D2R_N
USB3_EXTA_R2D_P
USB3_EXTA_R2D_N
USB3_EXTA_D2R_F_P
USB3_EXTA_D2R_F_N
USB3_EXTA_R2D_F_P
USB3_EXTA_R2D_F_N
USB3_EXTA_R2D_C_P
USB3_EXTA_R2D_C_N
?
PCH_USB_RBIAS
PCIE_CLK100M_PCH_P
PCIE_CLK100M_PCH_N
PCH_CLK96M_DOT_P
PCH_CLK96M_DOT_N
PCH_CLK100M_SATA_P
PCH_CLK100M_SATA_N
PCH_CLK14P3M_REFCLK
14
SYNC_MASTER=CLEAN_J43
SOURCE: 471984_Cheif_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.
SYNC_DATE=11/13/2012
PAGE TITLE
PCH Constraints 1
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
112 OF 121
SHEET
68 OF 76
1
A
8
7
6
5
LPC Bus Constraints
4
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
3
2
1
PCH Net Properties
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
NET_TYPE
Clock Net Properties
DIFFPAIR NECK GAP
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
LPC_45S
*
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=STANDARD
CLK_LPC_45S
*
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=STANDARD
NET_TYPE
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
LPC_AD
LPC_45S
LPC
LPC_FRAME_L
LPC_45S
LPC
LPC_45S
LPC
LPC_CLK33M
CLK_LPC_45S
CLK_LPC
CLK_LPC_45S
CLK_LPC
CLK_LPC_45S
CLK_LPC
CLK_LPC_45S
CLK_LPC
LPC_AD & lt; 3..0 & gt;
LPC_FRAME_L
LPCPLUS_RESET_L
LPC_CLK24M_SMC
LPC_CLK24M_SMC_R
LPC_CLK24M_LPCPLUS
LPC_CLK24M_LPCPLUS_R
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
14 37 64
LINE-TO-LINE SPACING
WEIGHT
=3x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
LPC
*
LPC_CLK33M
TABLE_SPACING_RULE_ITEM
CLK_LPC
D
*
=4x_DIELECTRIC
?
CLK_SLOW_45S
CLK_SLOW
SYSCLK_CLK32K_RTCX1
SYSCLK_CLK25M_SB
CLK_25M_45S
CLK_25M
CLK_25M_45S
CLK_25M
CLK_25M_45S
CLK_25M
CLK_25M_45S
CLK_25M
CLK_25M
CLK_25M_45S
LAYER
SYSCLK_CLK32K_RTC
CLK_25M_45S
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
14 37 64
CLK_25M
SYSCLK_CLK25M_CAMERA
CLK25M_CAM_CLKP
CLK25M_CAM_XTALP_R
CLK25M_CAM_XTALP
CLK25M_CAM_XTALN
CLK25M_CAM_CLKN
CLK_25M_45S
CLK_25M
CLK_25M_45S
CLK_25M
64
17 37
12 17
SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15
SMBus Interface Constraints
SMBUS_PCH_CLK
SMB_45S_R_50S
SMB
SMBUS_PCH_DATA
SMB_45S_R_50S
SMB
SMBUS_PCH_0_CLK
SMB_45S_R_50S
SMB
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
SMB_45S_R_50S
TOP,BOTTOM
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
SMB_45S_R_50S
*
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
SMBUS_PCH_CLK
SMBUS_PCH_DATA
SML_PCH_0_CLK
SML_PCH_0_DATA
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA
14 16 19 40 56
14 16 19 40 56
SMB_45S_R_50S
SMB
SMBUS_SMC_1_S0_SCL
SMB_45S_R_50S
SMB
SMBUS_SMC_1_S0_SDA
SMB_45S_R_50S
SMB
HDA_BIT_CLK
HDA_45S
HDA
HDA_45S
HDA
HDA_45S
HDA
HDA_45S
HDA
HDA_45S
HDA
HDA_45S
HDA
HDA_SDIN0
HDA_45S
HDA
HDA_SDOUT
HDA_45S
HDA
HDA_45S
HDA
PM_SUS_CLK
CLK_SLOW_45S
CLK_SLOW
CLK_SLOW_45S
CLK_SLOW
SPI_CLK
SPI_45S
SPI
SPI_45S
SPI
SPI_45S
SPI
SPI_45S
SPI
SPI_45S
SPI
SPI_45S
SPI
SPI_45S
SPI
SPI_45S
SPI
SPI_45S
SPI
SPI_45S
SPI
SPI_45S
SPI
SPI_45S
SPI
SPI_45S
SPI
PM_CLK32K_SUSCLK_R
SMC_CLK32K
SPI_CLK_R
SPI_CLK
SPI_MOSI_R
SPI_MOSI
SPI_MISO
SPI_MISO_R
SPI_CS0_R_L
SPI_CS0_L
SPI_SMC_CLK
SPI_SMC_MOSI
SPI_SMC_MISO
SPI_SMC_CS_L
SPI_MLB_CLK
SPI_45S
SPI
SPI_MLB_IO0_MOSI
SPI
SPI_MLB_IO1_MISO
SPI_45S
SPI
SPI_45S
SPI
SPI_45S
SPI
SPI_45S
SPI
SPI_45S
SPI
SPI_45S
SPI
SPI_45S
SPI
SPI_MLB_CS_L
SPI_IO & lt; 2 & gt;
SPI_IO2_R
SPI_MLB_IO2_WP_L
SPI_IO & lt; 3 & gt;
SPI_IO3_R
SPI_MLB_IO3_HOLD_L
PCIE_AP_R2D
PCIE_80D
PCIE_PCH_TX
PCIE_AP_R2D
PCIE_80D
PCIE_PCH_TX
PCIE_80D
PCIE_PCH_TX
PCIE_80D
PCIE_PCH_TX
PCIE_AP_D2R
LAYER
LINE-TO-LINE SPACING
PCIE_80D
PCIE_PCH_RX
14 32 37 40 43 44 64
73
14 32 37 40 43 44 64
73
*
=2x_DIELECTRIC
?
HDA_SYNC
HD Audio Interface Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
HDA_RST_L
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
HDA_45S
*
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=STANDARD
=STANDARD
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
SYSCLK_CLK25M_XTAL
CLK_25M_45S
32
D
31 32
SYSCLK_CLK25M_TBT
SYSCLK_CLK25M_TBT_R
17 25
25
CLK_25M
CLK_25M_45S
SYSCLK_CLK25M_X1
SYSCLK_CLK25M_X2
SYSCLK_CLK25M_X2_R
SDCLK_CLK25M_X2
SDCLK_CLK25M_X2_R
SDSCLK_CLK25M_X1
CLK_25M
CLK_25M_45S
CLK_25M
CLK_25M_45S
WEIGHT
TABLE_SPACING_RULE_ITEM
SMB
32
46
14 40
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
32
46
SPI_45S
=STANDARD
31 32
14 40
SMBUS_PCH_0_DATA
TABLE_PHYSICAL_RULE_ITEM
=STANDARD
SYSCLK_CLK25M_TBT
17 32
HDA_BIT_CLK
HDA_BIT_CLK_R
HDA_SYNC
HDA_SYNC_R
HDA_RST_R_L
HDA_RST_L
HDA_SDIN0
HDA_SDOUT
HDA_SDOUT_R
CLK_25M
12 61 65
CLK_25M_45S
CLK_25M
12
CLK_25M_45S
CLK_25M
17
17
17
34
34 75
34
12 61 65
12
12
12 61 65
12 61 65
12 61 65
12 17
WEIGHT
TABLE_SPACING_RULE_ITEM
HDA
*
=2x_DIELECTRIC
?
SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15
SIO Signal Constraints
SPI_MOSI
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
C
CLK_SLOW_45S
*
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=STANDARD
SPI_MISO
=STANDARD
SPI_CS0
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
CLK_SLOW
*
=4x_DIELECTRIC
?
SPI Interface Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
=45_OHM_SE
LAYER
=45_OHM_SE
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
13 38
37 38
14 46
46
14 46
46
14 46
C
46
14 46
46
37 46
37 46
37 46
37 46
46
TABLE_PHYSICAL_RULE_ITEM
SPI_45S
*
SPACING_RULE_SET
LAYER
=45_OHM_SE
=45_OHM_SE
=STANDARD
=STANDARD
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
SPI
*
=4x_DIELECTRIC
?
XDP Constraints
46
14 46
46
46
14 46
46
46
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
PCH_45S
*
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=STANDARD
=STANDARD
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=2:1_SPACING
?
TABLE_SPACING_RULE_ITEM
PCH_ITP
*
PCIE_AP_D2R
PCIE_80D
PCIE_PCH_RX
PCIE_CLK100M_AP
CLK_PCIE_80D
CLK_PCIE
PCIE_CLK100M_AP
DisplayPort
CLK_PCIE_80D
CLK_PCIE
TABLE_PHYSICAL_RULE_HEAD
B
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
DP_80D
*
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
PCIE_AP_R2D_P
PCIE_AP_R2D_N
PCIE_AP_R2D_C_P
PCIE_AP_R2D_C_N
PCIE_AP_D2R_P
PCIE_AP_D2R_N
PCIE_CLK100M_AP_P
PCIE_CLK100M_AP_N
29 64
29 64
14 29
14 29
14 29 64
14 29 64
12 29 64
B
12 29 64
TABLE_PHYSICAL_RULE_ITEM
PCIE_TBT_R2D
LINE-TO-LINE SPACING
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
=3x_DIELECTRIC
*
=4x_DIELECTRIC
?
DP_2DP
TOP,BOTTOM
=4x_DIELECTRIC
DP_2OTHERHS
TOP,BOTTOM
=6x_DIELECTRIC
=3x_DIELECTRIC
*
=3x_DIELECTRIC
PCIE_PCH_RX
PCIE_80D
PCIE_PCH_RX
PCIE_80D
PCIE_PCH_RX
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
?
DP_AUX
PCIE_80D
PCIE_TBT_D2R
?
TABLE_SPACING_RULE_ITEM
*
PCIE_PCH_TX
?
TABLE_SPACING_RULE_ITEM
DP_2OTHER
PCIE_80D
TABLE_SPACING_RULE_ITEM
?
DP_2OTHERHS
PCIE_PCH_TX
WEIGHT
TABLE_SPACING_RULE_ITEM
*
PCIE_PCH_TX
PCIE_80D
TABLE_SPACING_RULE_HEAD
WEIGHT
DP_2DP
PCIE_80D
PCIE_TBT_D2R
LAYER
PCIE_PCH_TX
PCIE_TBT_R2D
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
PCIE_80D
DP_2OTHER
?
TOP,BOTTOM
=4x_DIELECTRIC
?
DP_AUX
TOP,BOTTOM
=4x_DIELECTRIC
?
PCIE_80D
PCIE_PCH_RX
PCIE_CLK100M_TBT
CLK_PCIE_80D
CLK_PCIE
PCIE_CLK100M_TBT
TABLE_SPACING_RULE_ITEM
CLK_PCIE_80D
CLK_PCIE
TABLE_SPACING_RULE_ITEM
PCIE_TBT_R2D_P & lt; 3..0 & gt;
PCIE_TBT_R2D_N & lt; 3..0 & gt;
PCIE_TBT_R2D_C_P & lt; 3..0 & gt;
PCIE_TBT_R2D_C_N & lt; 3..0 & gt;
PCIE_TBT_D2R_P & lt; 3..0 & gt;
PCIE_TBT_D2R_N & lt; 3..0 & gt;
PCIE_TBT_D2R_C_P & lt; 3..0 & gt;
PCIE_TBT_D2R_C_N & lt; 3..0 & gt;
PCIE_CLK100M_TBT_P
PCIE_CLK100M_TBT_N
25
25
14 25
14 25
14 25
14 25
25
25
12 25
12 25
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
DP_TX
DP_TX
*
DP_2DP
CLK_PCIE_80D
CLK_PCIE
CLK_PCIE_80D
CLK_PCIE
PCH_45S
PCH_ITP
TABLE_SPACING_ASSIGNMENT_ITEM
PEG_CLK100M_P
PEG_CLK100M_N
TABLE_SPACING_ASSIGNMENT_ITEM
DP_TX
*_TX
*
DP_2OTHERHS
DP_TX
*_RX
*
DP_2OTHERHS
XDP_TDI
TABLE_SPACING_ASSIGNMENT_ITEM
XDP_TDO
PCH_ITP
PCIE_80D
PCIE_PCH_TX
PCIE_80D
PCIE_PCH_TX
PCIE_80D
PCIE_PCH_TX
PCIE_80D
A
PCH_45S
PCIE_CAM
PCIE_PCH_TX
PCIE_CAM
PCIE_80D
PCIE_PCH_RX
PCIE_CAM
PCIE_80D
PCIE_PCH_RX
PCIE_80D
PCIE_PCH_RX
PCIE_80D
PCIE_PCH_RX
PCIE_CLK100M_CAM
CLK_PCIE_80D
CLK_PCIE
PCIE_CLK100M_CAM
CLK_PCIE_80D
CLK_PCIE
CLK_PCIE_80D
CLK_PCIE
CLK_PCIE_80D
*
PCH_ITP
PCIE_CAM
*
PCH_ITP
PCH_45S
XDP_TCK
DP_TX
PCH_45S
XDP_TMS
TABLE_SPACING_ASSIGNMENT_ITEM
CLK_PCIE
DP_2OTHER
System Clock Signal Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
CLK_SLOW_45S
*
CLK_25M_45S
*
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=STANDARD
=STANDARD
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
XDP_PCH_TDI
XDP_PCH_TDO
XDP_PCH_TMS
XDP_PCH_TCK
PCIE_CAMERA_R2D_P
PCIE_CAMERA_R2D_N
PCIE_CAMERA_R2D_C_P
PCIE_CAMERA_R2D_C_N
PCIE_CAMERA_D2R_P
PCIE_CAMERA_D2R_N
PCIE_CAMERA_D2R_C_P
PCIE_CAMERA_D2R_C_N
PCIE_CLK100M_CAMERA_P
PCIE_CLK100M_CAMERA_N
PCIE_CLK100M_CAMERA_C_P
PCIE_CLK100M_CAMERA_C_N
12 16 64
12 16 64
12 16 64
12 16 64
31 32
31 32
14 32
14 32
14 32
14 32
31 32
LAYER
LINE-TO-LINE SPACING
*
R
NOTICE OF PROPRIETARY PROPERTY:
?
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
*
8
=5x_DIELECTRIC
?
NOTE: 25MHz system clocks very sensitive to noise.
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
31 32
TABLE_SPACING_RULE_ITEM
CLK_25M
Apple Inc.
31 32
BRANCH
WEIGHT
=2x_DIELECTRIC
DRAWING NUMBER
12 32
TABLE_SPACING_RULE_ITEM
CLK_SLOW
SYNC_DATE=12/14/2012
PCH Constraints 2
12 32
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
SYNC_MASTER=J41_MLB
PAGE TITLE
31 32
& lt; BRANCH & gt;
PAGE
113 OF 121
SHEET
69 OF 76
1
A
8
7
6
5
4
3
2
1
Memory Net Properties
Memory Bus Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
MEM_40S
*
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
MEM_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
NET_TYPE
SPACING
TABLE_PHYSICAL_RULE_ITEM
MEM_A_CLK0
MEM_A_CLK0
MEM_A_CLK1
MEM_A_CLK1
MEM_A_CTRL
MEM_A_CTRL
MEM_A_CKE0
MEM_A_CKE1
MEM_A_CMD0
MEM_A_CMD1
MEM_A_DQ_BYTE0
MEM_A_DQ_BYTE1
MEM_A_DQ_BYTE2
MEM_A_DQ_BYTE3
MEM_A_DQ_BYTE4
MEM_A_DQ_BYTE5
MEM_A_DQ_BYTE6
MEM_A_DQ_BYTE7
MEM_A_DQS0
MEM_A_DQS0
MEM_A_DQS1
MEM_A_DQS1
MEM_A_DQS2
MEM_A_DQS2
MEM_A_DQS3
MEM_A_DQS3
MEM_A_DQS4
MEM_A_DQS4
MEM_A_DQS5
MEM_A_DQS5
MEM_A_DQS6
MEM_A_DQS6
MEM_A_DQS7
MEM_A_DQS7
MEM_70D
*
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
MEM_73D
*
=73_OHM_DIFF
=73_OHM_DIFF
=73_OHM_DIFF
=73_OHM_DIFF
=73_OHM_DIFF
=73_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
D
Spacing Rule Sets
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
MEM_DATA2SELF
*
=2x_DIELECTRIC
?
MEM_DATA2OTHERMEM
*
=8x_DIELECTRIC
?
MEM_DQS2OWNDATA
*
=3x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MEM_CMD2CMD
*
=3x_DIELECTRIC
?
MEM_CMD2CTRL
*
=3x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
*
MEM_CTRL2CTRL
=3x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
MEM_CLK2CLK
*
=6x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
*
MEM_2OTHERMEM
=4x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
MEM_2PWR
*
=2x_DIELECTRIC
10000
TABLE_SPACING_RULE_ITEM
MEM_2GND
*
=2x_DIELECTRIC
10000
MEM_2OTHER
*
=6x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
Memory to Power Spacing
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_PHYSICAL_ASSIGNMENT_HEAD
NET_PHYSICAL_TYPE
AREA_TYPE
PHYSICAL_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_PWR
MEM_*
*
*
*
MEM_70D
DEFAULT
MEM_TERM
MEM_73D
MEM_40S
MEM_2PWR
MEM_PWR
TABLE_PHYSICAL_ASSIGNMENT_ITEM
MEM_TERM
MEM_50S
TABLE_SPACING_ASSIGNMENT_ITEM
C
TABLE_PHYSICAL_ASSIGNMENT_ITEM
Memory to GND Spacing
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
GND
MEM_*
*
MEM_2GND
TABLE_SPACING_ASSIGNMENT_ITEM
Memory Bus Spacing Group Assignments
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DQS_0
MEM_A_DATA_0
*
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DQS_0
MEM_DQS2OWNDATA
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DQS_1
MEM_A_DATA_1
*
MEM_A_DATA_2
*
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DQS_1
MEM_DQS2OWNDATA
*
*
MEM_2OTHER
MEM_A_DQS_2
MEM_DQS2OWNDATA
MEM_A_DQS_2
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DQS_3
MEM_A_DATA_3
*
MEM_DQS2OWNDATA
MEM_A_DQS_4
MEM_A_DATA_4
*
MEM_DQS2OWNDATA
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DQS_3
*
*
MEM_2OTHER
MEM_A_DQS_4
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DQS_5
MEM_A_DATA_5
*
MEM_DQS2OWNDATA
MEM_A_DQS_6
MEM_A_DATA_6
*
MEM_DQS2OWNDATA
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DQS_5
*
*
MEM_2OTHER
MEM_A_DQS_6
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DQS_7
MEM_A_DATA_7
*
MEM_DQS2OWNDATA
MEM_B_DQS_0
MEM_B_DATA_0
*
MEM_DQS2OWNDATA
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DQS_7
*
*
MEM_2OTHER
MEM_B_DQS_0
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_DQS_1
MEM_B_DATA_1
*
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_DQS_1
MEM_DQS2OWNDATA
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_DQS_2
MEM_B_DATA_2
*
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_DQS_2
MEM_DQS2OWNDATA
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
B
MEM_B_DQS_3
MEM_B_DATA_3
*
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_DQS_3
MEM_DQS2OWNDATA
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_DQS_4
MEM_B_DATA_4
*
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_DQS_4
MEM_DQS2OWNDATA
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_DQS_5
MEM_B_DATA_5
*
MEM_DQS2OWNDATA
MEM_B_DQS_6
MEM_B_DATA_6
*
MEM_DQS2OWNDATA
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_DQS_5
*
*
MEM_2OTHER
MEM_B_DQS_6
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_DQS_7
MEM_B_DATA_7
*
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_DQS_7
*
*
MEM_2OTHER
MEM_A_DATA_0
MEM_DQS2OWNDATA
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
MEM_CLK
MEM_CLK
MEM_CLK
MEM_CTRL
MEM_CTRL
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_A_DATA_0
MEM_A_DATA_1
MEM_A_DATA_2
MEM_A_DATA_3
MEM_A_DATA_4
MEM_A_DATA_5
MEM_A_DATA_6
MEM_A_DATA_7
MEM_A_DQS_0
MEM_A_DQS_0
MEM_A_DQS_1
MEM_A_DQS_1
MEM_A_DQS_2
MEM_A_DQS_2
MEM_A_DQS_3
MEM_A_DQS_3
MEM_A_DQS_4
MEM_A_DQS_4
MEM_A_DQS_5
MEM_A_DQS_5
MEM_A_DQS_6
MEM_A_DQS_6
MEM_A_DQS_7
MEM_A_DQS_7
MEM_A_CLK_P & lt; 0 & gt;
MEM_A_CLK_N & lt; 0 & gt;
MEM_A_CLK_P & lt; 1 & gt;
MEM_A_CLK_N & lt; 1 & gt;
MEM_A_CS_L & lt; 1..0 & gt;
MEM_A_ODT & lt; 0 & gt;
MEM_A_CKE & lt; 1..0 & gt;
MEM_A_CKE & lt; 3..2 & gt;
MEM_A_CAA & lt; 9..0 & gt;
MEM_A_CAB & lt; 9..0 & gt;
MEM_A_DQ & lt; 7..0 & gt;
MEM_A_DQ & lt; 15..8 & gt;
MEM_A_DQ & lt; 23..16 & gt;
MEM_A_DQ & lt; 31..24 & gt;
MEM_A_DQ & lt; 39..32 & gt;
MEM_A_DQ & lt; 47..40 & gt;
MEM_A_DQ & lt; 55..48 & gt;
MEM_A_DQ & lt; 63..56 & gt;
MEM_A_DQS_P & lt; 0 & gt;
MEM_A_DQS_N & lt; 0 & gt;
MEM_A_DQS_P & lt; 1 & gt;
MEM_A_DQS_N & lt; 1 & gt;
MEM_A_DQS_P & lt; 2 & gt;
MEM_A_DQS_N & lt; 2 & gt;
MEM_A_DQS_P & lt; 3 & gt;
MEM_A_DQS_N & lt; 3 & gt;
MEM_A_DQS_P & lt; 4 & gt;
MEM_A_DQS_N & lt; 4 & gt;
MEM_A_DQS_P & lt; 5 & gt;
MEM_A_DQS_N & lt; 5 & gt;
MEM_A_DQS_P & lt; 6 & gt;
MEM_A_DQS_N & lt; 6 & gt;
MEM_A_DQS_P & lt; 7 & gt;
MEM_A_DQS_N & lt; 7 & gt;
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_CLK
MEM_CLK
MEM_CLK
MEM_CLK
MEM_CTRL
MEM_CTRL
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_B_DATA_0
MEM_B_DATA_1
MEM_B_DATA_2
MEM_B_DATA_3
MEM_B_DATA_4
MEM_B_DATA_5
MEM_B_DATA_6
MEM_B_DATA_7
MEM_B_DQS_0
MEM_B_DQS_0
MEM_B_DQS_1
MEM_B_DQS_1
MEM_B_DQS_2
MEM_B_DQS_2
MEM_B_DQS_3
MEM_B_DQS_3
MEM_B_DQS_4
MEM_B_DQS_4
MEM_B_DQS_5
MEM_B_DQS_5
MEM_B_DQS_6
MEM_B_DQS_6
MEM_B_DQS_7
MEM_B_DQS_7
MEM_B_CLK_P & lt; 0 & gt;
MEM_B_CLK_N & lt; 0 & gt;
MEM_B_CLK_P & lt; 1 & gt;
MEM_B_CLK_N & lt; 1 & gt;
MEM_B_CS_L & lt; 1..0 & gt;
MEM_B_ODT & lt; 0 & gt;
MEM_B_CKE & lt; 1..0 & gt;
MEM_B_CKE & lt; 3..2 & gt;
MEM_B_CAA & lt; 9..0 & gt;
MEM_B_CAB & lt; 9..0 & gt;
MEM_B_DQ & lt; 7..0 & gt;
MEM_B_DQ & lt; 15..8 & gt;
MEM_B_DQ & lt; 23..16 & gt;
MEM_B_DQ & lt; 31..24 & gt;
MEM_B_DQ & lt; 39..32 & gt;
MEM_B_DQ & lt; 47..40 & gt;
MEM_B_DQ & lt; 55..48 & gt;
MEM_B_DQ & lt; 63..56 & gt;
MEM_B_DQS_P & lt; 0 & gt;
MEM_B_DQS_N & lt; 0 & gt;
MEM_B_DQS_P & lt; 1 & gt;
MEM_B_DQS_N & lt; 1 & gt;
MEM_B_DQS_P & lt; 2 & gt;
MEM_B_DQS_N & lt; 2 & gt;
MEM_B_DQS_P & lt; 3 & gt;
MEM_B_DQS_N & lt; 3 & gt;
MEM_B_DQS_P & lt; 4 & gt;
MEM_B_DQS_N & lt; 4 & gt;
MEM_B_DQS_P & lt; 5 & gt;
MEM_B_DQS_N & lt; 5 & gt;
MEM_B_DQS_P & lt; 6 & gt;
MEM_B_DQS_N & lt; 6 & gt;
MEM_B_DQS_P & lt; 7 & gt;
MEM_B_DQS_N & lt; 7 & gt;
MEM_PWR
MEM_PWR
MEM_PWR
MEM_PWR
MEM_PWR
TABLE_PHYSICAL_RULE_ITEM
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_B_CLK0
MEM_B_CLK0
MEM_B_CLK1
MEM_B_CLK1
MEM_B_CTRL
MEM_B_CTRL
MEM_B_CKE0
MEM_B_CKE1
MEM_B_CMD0
MEM_B_CMD1
MEM_B_DQ_BYTE0
MEM_B_DQ_BYTE1
MEM_B_DQ_BYTE2
MEM_B_DQ_BYTE3
MEM_B_DQ_BYTE4
MEM_B_DQ_BYTE5
MEM_B_DQ_BYTE6
MEM_B_DQ_BYTE7
MEM_B_DQS0
MEM_B_DQS0
MEM_B_DQS1
MEM_B_DQS1
MEM_B_DQS2
MEM_B_DQS2
MEM_B_DQS3
MEM_B_DQS3
MEM_B_DQS4
MEM_B_DQS4
MEM_B_DQS5
MEM_B_DQS5
MEM_B_DQS6
MEM_B_DQS6
MEM_B_DQS7
MEM_B_DQS7
TABLE_PHYSICAL_RULE_ITEM
PP1V2_S3
PP0V6_S3_MEM_VREFCA_A
PP0V6_S3_MEM_VREFDQ_A
PP0V6_S3_MEM_VREFCA_B
PP0V6_S3_MEM_VREFDQ_B
7 20 24
7 20 24
7 21 24
7 21 24
7 20 21 24
7 20 21 24 63
7 20 24
7 21 24
D
7 20 24 63
7 21 24 63
7 63
7 63
7 63
7 63
7 21 63
7 63
7 63
7 63
7 63
7 63
7 63
7 63
7 63
7 63
7 63
7 63
7 63
7 63
7 63
7 63
7 21 63
7 21 63
7 63
7 63
C
7 22 24
7 22 24
7 23 24
7 23 24
7 22 23 24
7 22 23 24 63
7 22 24
7 23 24
7 22 24 63
7 23 24 63
7 63
7 63
7 63
7 63
7 23 63
7 63
7 63
7 63
7 63
7 63
7 63
7 63
7 63
7 63
7 63
7 63
B
7 63
7 63
7 63
7 63
7 23 63
7 23 63
7 63
7 63
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DATA_1
*
*
MEM_2OTHER
MEM_A_DATA_2
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_*_DATA_*
=SAME
*
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DATA2SELF
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_A_DATA_0
MEM_*_DATA_*
*
MEM_2OTHERMEM
MEM_A_DATA_1
MEM_*_DATA_*
*
MEM_2OTHERMEM
MEM_A_DATA_2
MEM_*_DATA_*
*
MEM_2OTHERMEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DATA_3
*
*
MEM_2OTHER
MEM_A_DATA_4
*
*
MEM_2OTHER
MEM_A_DATA_5
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DATA_6
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_*_DATA_*
MEM_*
*
MEM_A_DATA_3
MEM_*_DATA_*
*
*
*
MEM_2OTHER
MEM_B_DATA_0
*
*
MEM_2OTHER
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
MEM_*_DATA_*
*
MEM_2OTHERMEM
MEM_A_DATA_5
MEM_*_DATA_*
*
MEM_2OTHERMEM
MEM_A_DATA_6
MEM_*_DATA_*
*
MEM_2OTHERMEM
MEM_A_DATA_7
MEM_*_DATA_*
*
MEM_2OTHERMEM
MEM_B_DATA_0
MEM_*_DATA_*
*
MEM_2OTHERMEM
MEM_B_DATA_1
MEM_*_DATA_*
*
MEM_2OTHERMEM
MEM_B_DATA_2
MEM_*_DATA_*
*
MEM_2OTHERMEM
MEM_B_DATA_3
MEM_*_DATA_*
*
MEM_2OTHERMEM
MEM_B_DATA_4
MEM_*_DATA_*
*
MEM_2OTHERMEM
MEM_B_DATA_5
MEM_*_DATA_*
*
MEM_2OTHERMEM
MEM_B_DATA_6
MEM_*_DATA_*
*
MEM_2OTHERMEM
TABLE_SPACING_ASSIGNMENT_ITEM
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CMD
*
MEM_B_DATA_1
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CMD2CMD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CMD
MEM_CTRL
*
MEM_B_DATA_2
*
*
MEM_2OTHER
MEM_B_DATA_3
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CMD2CTRL
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL
MEM_CTRL
*
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL2CTRL
TABLE_SPACING_ASSIGNMENT_ITEM
A
MEM_B_DATA_4
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CLK
MEM_CLK
*
MEM_CLK2CLK
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_DATA_5
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_DATA_6
*
*
MEM_2OTHER
MEM_B_DATA_7
*
*
MEM_2OTHER
MEM_CMD
*
*
MEM_2OTHER
MEM_CTRL
*
*
MEM_2OTHER
SYNC_MASTER=CONSTRAINTS
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
Memory Constraints
DRAWING NUMBER
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
Apple Inc.
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_*
*
MEM_CLK
8
7
*
*
MEM_2OTHER
6
& lt; E4LABEL & gt;
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_DATA_7
MEM_*_DATA_*
5
*
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
MEM_2OTHERMEM
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
R
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_2OTHERMEM
SYNC_DATE=09/25/2012
PAGE TITLE
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
MEM_*
18 19 22 23
MEM_2OTHERMEM
MEM_A_DATA_4
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CMD
18 19 22 23
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
18 19 20 21
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DATA_7
MEM_DATA2OTHERMEM
TABLE_SPACING_ASSIGNMENT_ITEM
17 19 20 21 22 23 42
53 62
18 19 20 21
& lt; BRANCH & gt;
PAGE
114 OF 121
SHEET
70 OF 76
1
A
8
7
6
5
DisplayPort Signal Constraints
4
3
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
Thunderbolt SPI Signal Constraints
TBT_A_R2D
TBTDP_80D
TBTDP_TX
TBT_A_R2D
TBTDP_80D
TBTDP_TX
TBTDP_80D
TBTDP_TX
TBTDP_80D
TBTDP_TX
DP_80D
DP_TX
DP_TBTPA_ML1
DP_80D
DP_TX
DP_TBTPA_ML3
DP_80D
DP_TX
DP_TBTPA_ML3
DP_80D
DP_TX
DP_80D
DP_TX
DP_80D
DP_TX
DP_80D
DP_TX
DP_80D
DP_TX
TBTDP_80D
TBTDP_RX
TABLE_PHYSICAL_RULE_HEAD
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
TBT_SPI_45S
*
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=STANDARD
=STANDARD
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=2x_DIELECTRIC
DP_TBTPA_ML1
?
TABLE_SPACING_RULE_ITEM
TBT_SPI
D
*
1
Thunderbolt/DP Net Properties
NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.
PHYSICAL_RULE_SET
2
Thunderbolt/DP Connector Signal Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TBTDP_80D
*
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
TBT_A_R2D_C_P & lt; 1..0 & gt;
TBT_A_R2D_C_N & lt; 1..0 & gt;
TBT_A_R2D_P & lt; 1..0 & gt;
TBT_A_R2D_N & lt; 1..0 & gt;
DP_TBTPA_ML_C_P & lt; 1 & gt;
DP_TBTPA_ML_C_N & lt; 1 & gt;
DP_TBTPA_ML_C_P & lt; 3 & gt;
DP_TBTPA_ML_C_N & lt; 3 & gt;
DP_TBTPA_ML_P & lt; 3..1:2 & gt;
DP_TBTPA_ML_N & lt; 3..1:2 & gt;
DP_A_LSX_ML_P & lt; 1 & gt;
DP_A_LSX_ML_N & lt; 1 & gt;
25 28
25 28
28
28
25 28
25 28
25 28
D
25 28
28
28
=80_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_HEAD
AREA_TYPE
SPACING_RULE_SET
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
TBTDP_TX
*
TBTDP_TX2TX
TBTDP_RX
TBTDP_RX
*
TBTDP_RX2RX
TBTDP_TX2TX
TOP,BOTTOM
=6x_DIELECTRIC
*
TBTDP_TX2RX
TBTDP_80D
TBTDP_RX
TBT_A_D2R0
?
TBTDP_RX2RX
TOP,BOTTOM
=6x_DIELECTRIC
TBTDP_80D
TBTDP_RX
TBTDP_80D
TBTDP_RX
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TBTDP_RX
TBT_A_D2R1
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TBTDP_TX
TBTDP_RX
WEIGHT
TABLE_SPACING_ASSIGNMENT_ITEM
TBTDP_TX
TBTDP_RX
TBTDP_80D
TBT_A_D2R0
NET_SPACING_TYPE2
TBTDP_80D
TBT_A_D2R1
NET_SPACING_TYPE1
TBTDP_TX2RX
TOP,BOTTOM
=10x_DIELECTRIC
TABLE_SPACING_RULE_ITEM
DP_AUX
DP_AUX
DP_80D
DP_AUX
TBTDP_80D
TBTDP_RX
TBTDP_RX
TBTDP_80D
TBTDP_TX
TBT_B_R2D
TBTDP_80D
TBTDP_TX
TBTDP_80D
TBTDP_TX
TBTDP_TX
DP_80D
DP_TX
DP_TBTPB_ML
DP_80D
DP_TX
DP_80D
DP_TX
DP_80D
DP_TX
DP_80D
DP_TX
?
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TBTDP_RX
*_TX
*
TBTDP_2OTHERHS
TBTDP_TX
*_RX
*
TBTDP_2OTHERHS
TBTDP_RX
*_RX
*
TBTDP_2OTHERHS
TBTDP_TX
*
*
TBTDP_2OTHER
DP_AUX
?
=6x_DIELECTRIC
DP_AUX
DP_TBTPB_ML
=10x_DIELECTRIC
TOP,BOTTOM
DP_AUX
TBTDP_80D
TOP,BOTTOM
TBTDP_2OTHER
DP_80D
DP_80D
TBTDP_2OTHERHS
DP_80D
TBT_B_R2D
TBTDP_2OTHERHS
DP_80D
TBTDP_80D
TBTDP_TX2RX
*
TBT_A_AUXCH
DP_80D
*
*_TX
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TBTDP_TX2TX
*
=4x_DIELECTRIC
?
TBTDP_RX2RX
*
=4x_DIELECTRIC
?
TABLE_SPACING_ASSIGNMENT_ITEM
*
*
TBTDP_2OTHER
25 28
25 28
DP_TBTPA_AUXCH_C_P
DP_TBTPA_AUXCH_C_N
DP_TBTPA_AUXCH_P
DP_TBTPA_AUXCH_N
DP_A_AUXCH_DDC_P
DP_A_AUXCH_DDC_N
TBT_A_D2R1_AUXDDC_P
TBT_A_D2R1_AUXDDC_N
25 28
25 28
25 28
28
28
28
28
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TBTDP_RX
28
25 28
?
TBT_A_AUXCH
TBTDP_TX
TBTDP_TX
28
28
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TBTDP_RX
TBT_A_D2R_C_P & lt; 1..0 & gt;
TBT_A_D2R_C_N & lt; 1..0 & gt;
TBT_A_D2R_P & lt; 1 & gt;
TBT_A_D2R_N & lt; 1 & gt;
TBT_A_D2R_P & lt; 0 & gt;
TBT_A_D2R_N & lt; 0 & gt;
28
TABLE_SPACING_RULE_ITEM
TBTDP_TX2RX
*
=6x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
TBTDP_2OTHERHS
*
=6x_DIELECTRIC
?
TBT_B_R2D_C_P & lt; 1..0 & gt;
TBT_B_R2D_C_N & lt; 1..0 & gt;
TBT_B_R2D_P & lt; 1..0 & gt;
TBT_B_R2D_N & lt; 1..0 & gt;
64
64
TABLE_SPACING_RULE_ITEM
TBTDP_2OTHER
*
=4x_DIELECTRIC
?
C
DP_80D
DP_TX
TBTDP_80D
TBTDP_RX
TBTDP_80D
TBTDP_RX
TBT_B_D2R
TBTDP_80D
TBTDP_RX
TBT_B_D2R
TBTDP_80D
TBTDP_RX
TBT_B_AUXCH
DP_80D
DP_AUX
TBT_B_AUXCH
DP_80D
DP_AUX
DP_80D
DP_AUX
DP_80D
DP_AUX
DP_80D
DP_AUX
DP_80D
DP_AUX
TBTDP_80D
TBTDP_RX
TBTDP_80D
TBTDP_RX
NC_DP_TBTPB_ML_CP & lt; 3..1:2 & gt;
NC_DP_TBTPB_ML_CN & lt; 3..1:2 & gt;
DP_TBTPB_ML_P & lt; 3..1:2 & gt;
DP_TBTPB_ML_N & lt; 3..1:2 & gt;
DP_B_LSX_ML_P & lt; 1 & gt;
DP_B_LSX_ML_N & lt; 1 & gt;
TBT_B_D2R_C_P & lt; 1..0 & gt;
TBT_B_D2R_C_N & lt; 1..0 & gt;
TBT_B_D2R_P & lt; 1..0 & gt;
TBT_B_D2R_N & lt; 1..0 & gt;
NC_DP_TBTPB_AUXCH_CP
NC_DP_TBTPB_AUXCH_CN
DP_TBTPB_AUXCH_P
DP_TBTPB_AUXCH_N
DP_B_AUXCH_DDC_P
DP_B_AUXCH_DDC_N
TBT_B_D2R1_AUXDDC_P
TBT_B_D2R1_AUXDDC_N
64
C
64
Only used on dual-port hosts.
64
64
25 64
25 64
Thunderbolt IC Net Properties
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
DP_80D
DP_TX
DP_80D
DP_TX
DP_80D
DP_AUX
DP_80D
DP_AUX
TBT_SPI_CLK
TBT_SPI_45S
TBT_SPI
TBT_SPI_MOSI
TBT_SPI_45S
TBT_SPI
TBT_SPI_MISO
TBT_SPI_45S
TBT_SPI
TBT_SPI_CS_L
TBT_SPI_45S
TBT_SPI
B
DP_TBTSRC_ML_C_P & lt; 3..0 & gt;
DP_TBTSRC_ML_C_N & lt; 3..0 & gt;
DP_TBTSRC_AUXCH_C_P
DP_TBTSRC_AUXCH_C_N
TBT_SPI_CLK
TBT_SPI_MOSI
TBT_SPI_MISO
TBT_SPI_CS_L
A
B
Only used on hosts supporting Thunderbolt video-in
25
25
25
25
SYNC_MASTER=CONSTRAINTS
SYNC_DATE=09/25/2012
PAGE TITLE
Thunderbolt Constraints
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
115 OF 121
SHEET
71 OF 76
1
A
8
7
6
5
4
3
2
1
Camera Net Properties
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
S2_MEM_CLK
S2_MEM_85D
S2_MEM_CLK
S2_MEM_CNTL
S2_MEM_45S
S2_MEM_CTRL
S2_MEM_CNTL
S2_MEM_45S
S2_MEM_CTRL
S2_MEM_45S
MEM_CAM_CLK_P
MEM_CAM_CLK_N
S2_MEM_CLK
S2_MEM_CLK
MIPI Interface Constraints
S2_MEM_85D
S2_MEM_CTRL
31 32
31 32
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
MIPI_85D
*
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
I101
D
I102
LAYER
LINE-TO-LINE SPACING
=4X_DIELECTRIC
SPACING_RULE_SET
?
LAYER
LINE-TO-LINE SPACING
*
=6X_DIELECTRIC
S2_MEM_45S
S2_MEM_CTRL
S2_MEM_CMD
S2_MEM_45S
S2_MEM_CTRL
S2_MEM_CMD
WEIGHT
S2_MEM_CMD
I104
TABLE_SPACING_RULE_HEAD
WEIGHT
S2_MEM_45S
S2_MEM_CMD
S2_MEM_45S
S2_MEM_CMD
?
TABLE_SPACING_RULE_ITEM
MIPI_2OTHER
I103
S2_MEM_CMD
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
TABLE_SPACING_RULE_ITEM
MIPI_2OTHER
TOP,BOTTOM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
?
?
*
S2_MEM_85D
S2_MEM_DQS0
S2_MEM_85D
S2_MEM_DQS0
S2_MEM_DQS1
S2_MEM_85D
S2_MEM_DQS1
S2_MEM_DQS1
S2_MEM_85D
S2_MEM_DQS1
S2_MEM_DATA_0
S2_MEM_45S
S2_MEM_DATA0
I110
S2_MEM_DATA_1
S2_MEM_45S
S2_MEM_DATA1
I147
S2_MEM_A
S2_MEM_45S
S2_MEM_CMD
S2_MEM_45S
S2_MEM_DATA0
S2_MEM_45S
S2_MEM_DATA1
I127
MIPI_DATA_S2
MIPI_85D
MIPI_DATA
I128
MIPI_DATA_S2
MIPI_85D
MIPI_DATA
I129
MIPI_85D
MIPI_DATA
I130
MIPI_85D
MIPI_DATA
TABLE_SPACING_RULE_ITEM
?
=7X_DIELECTRIC
S2_MEM_DQS0
S2_MEM_DATA_1
MIPICLK_2OTHER
S2_MEM_CMD
I109
=8X_DIELECTRIC
S2_MEM_CMD
I107
TOP,BOTTOM
S2_MEM_45S
I108
MIPI_2CLK
TABLE_SPACING_RULE_ITEM
S2_MEM_45S
S2_MEM_DATA_0
=6X_DIELECTRIC
S2_MEM_CMD
S2_MEM_DQS0
*
S2_MEM_CMD
I106
MIPI_2CLK
MEM_CAM_CKE
MEM_CAM_CS_L
MEM_CAM_ODT
MEM_CAM_CAS_L
MEM_CAM_RAS_L
MEM_CAM_WE_L
MEM_CAM_BA & lt; 0 & gt;
MEM_CAM_BA & lt; 1 & gt;
MEM_CAM_BA & lt; 2 & gt;
MEM_CAM_DQS_P & lt; 0 & gt;
MEM_CAM_DQS_N & lt; 0 & gt;
MEM_CAM_DQS_P & lt; 1 & gt;
MEM_CAM_DQS_N & lt; 1 & gt;
MEM_CAM_DM & lt; 0 & gt;
MEM_CAM_DM & lt; 1 & gt;
MEM_CAM_A & lt; 14..0 & gt;
MIPICLK_2OTHER
TOP,BOTTOM
?
=10X_DIELECTRIC
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
MIPI_DATA
*
*
MIPI_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
MIPI_DATA
CLK_MIPI
*
MIPI_2CLK
TABLE_SPACING_ASSIGNMENT_ITEM
CLK_MIPI
*
*
MIPICLK_2OTHER
Memory Bus Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
S2_MEM_45S
*
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
S2_MEM_85D
*
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
LINE-TO-LINE SPACING
WEIGHT
S2_DATA2SELF
*
=2x_DIELECTRIC
?
*
=2x_DIELECTRIC
?
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
S2_DATA2SELF
TOP,BOTTOM
=4x_DIELECTRIC
?
S2_DQS2OWNDATA
?
TOP,BOTTOM
=4x_DIELECTRIC
?
S2_CMD2CTRL
*
=2x_DIELECTRIC
=2x_DIELECTRIC
?
TOP,BOTTOM
=4x_DIELECTRIC
=4x_DIELECTRIC
S2_CMD2CTRL
TOP,BOTTOM
=4x_DIELECTRIC
TOP,BOTTOM
=4x_DIELECTRIC
*
=2x_DIELECTRIC
S2_2OTHERMEM
TOP,BOTTOM
=6x_DIELECTRIC
S2MEM_2GND
*
=2x_DIELECTRIC
TOP,BOTTOM
=4x_DIELECTRIC
=6x_DIELECTRIC
S2MEM_2GND
?
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
32 64
32 64
31 32
31 32
32 64
PP1V35_CAM
PP0V675_CAM_VREF
PP0V675_MEM_CAM_VREFCA
PP0V675_MEM_CAM_VREFDQ
S2_MEM_PWR
C
32 64
S2_MEM_PWR
I148
S2_MEM_PWR
I149
S2_MEM_PWR
31 32
31 32
32
32
?
TOP,BOTTOM
=4x_DIELECTRIC
?
S2MEM_2OTHER
?
*
31 32
TOP,BOTTOM
=10x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
S2MEM_2OTHER
31 32
?
S2MEM_2PWR
?
31 32
?
TABLE_SPACING_RULE_ITEM
S2MEM_2PWR
31 32
?
S2_CTRL2CTRL
?
31 32
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
*
31 32
?
TABLE_SPACING_RULE_ITEM
S2_2OTHERMEM
CLK_MIPI
I146
TABLE_SPACING_RULE_ITEM
S2_CMD2CMD
?
*
MIPI_85D
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
S2_CTRL2CTRL
CLK_MIPI
I145
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
=2x_DIELECTRIC
CLK_MIPI
MIPI_85D
WEIGHT
TABLE_SPACING_RULE_ITEM
*
D
32
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
S2_DQS2OWNDATA
MIPI_CLK_P
MIPI_CLK_N
MIPI_CLK_CONN_P
MIPI_CLK_CONN_N
CLK_MIPI
MIPI_85D
I131
TABLE_SPACING_RULE_HEAD
S2_CMD2CMD
MIPI_85D
MIPI_CLK_S2
I132
Spacing Rule Sets
LAYER
MIPI_CLK_S2
I133
SPACING_RULE_SET
MIPI_DATA_P
MIPI_DATA_N
MIPI_DATA_CONN_P
MIPI_DATA_CONN_N
31 32
=85_OHM_DIFF
I134
C
MEM_CAM_DQ & lt; 7..0 & gt;
MEM_CAM_DQ & lt; 15..8 & gt;
31 32
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
Memory Bus Spacing Group Assignments
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
S2_MEM_DQS1
S2_MEM_DATA1
*
S2_DQS2OWNDATA
S2_MEM_DQS0
S2_MEM_DATA0
*
S2_DQS2OWNDATA
TABLE_SPACING_ASSIGNMENT_ITEM
S2_MEM_DATA*
*
*
S2MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
S2_MEM_DQS*
*
*
S2MEM_2OTHER
S2_MEM_CMD
*
*
S2_MEM_CTRL
*
*
S2MEM_2OTHER
S2_MEM_CLK
*
*
S2MEM_2OTHER
S2_MEM_DATA*
=SAME
*
S2_DATA2SELF
S2_MEM_CMD
S2_MEM_CMD
*
S2_CMD2CMD
S2_MEM_CMD
S2_MEM_CTRL
*
S2_CMD2CTRL
S2_MEM_CTRL
S2_MEM_CTRL
*
TABLE_SPACING_ASSIGNMENT_ITEM
S2MEM_2OTHER
S2_CTRL2CTRL
TABLE_SPACING_ASSIGNMENT_ITEM
B
B
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
Memory to Power Spacing
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
S2_MEM_PWR
S2_MEM_*
*
S2MEM_2PWR
S2_MEM_PWR
*
*
DEFAULT
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
S2_MEM_*
S2_MEM_*
*
S2_2OTHERMEM
Memory to GND Spacing
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
GND
S2_MEM_*
*
S2MEM_2GND
TABLE_SPACING_ASSIGNMENT_ITEM
A
SYNC_MASTER=J41_MLB
SYNC_DATE=01/30/2013
PAGE TITLE
Camera Constraints
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
116 OF 121
SHEET
72 OF 76
1
A
8
7
6
5
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
3
2
1
SMC SMBus Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
4
DIFFPAIR NECK GAP
NET_TYPE
TABLE_PHYSICAL_RULE_ITEM
1TO1_DIFFPAIR
*
=STANDARD
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.1 MM
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
2TO1_DIFFPAIR
*
=STANDARD
0.2 MM
0.1 MM
=STANDARD
0.1 MM
0.1 MM
SMBUS_SMC_0_S0_SCL
SMB
SMBUS_SMC_0_S0_SDA
SMB_45S_R_50S
SMB
SMBUS_SMC_1_S0_SCL
SMB_45S_R_50S
SMB
SMBUS_SMC_1_S0_SDA
SMB_45S_R_50S
SMB
SMBUS_SMC_2_S3_SCL
SMB_45S_R_50S
SMB
SMBUS_SMC_2_S3_SDA
SMB_45S_R_50S
SMB
SMBUS_SMC_3_SCL
SMB_45S_R_50S
SMB
SMBUS_SMC_3_SDA
SMB_45S_R_50S
SMB
SMBUS_SMC_5_G3_SCL
SMB_45S_R_50S
SMB
SMBUS_SMC_5_G3_SDA
D
SMB_45S_R_50S
SMB_45S_R_50S
SMB
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA
SMBUS_SMC_2_S3_SCL
SMBUS_SMC_2_S3_SDA
SMBUS_SMC_3_SCL
SMBUS_SMC_3_SDA
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA
37 40 60
37 40 60
14 32 37 40 43 44 64 69
14 32 37 40 43 44 64 69
37 40 61 65
37 40 61 65
36 37 40 44 64
36 37 40 44 64
D
37 40 48 50 64
37 40 48 50 64
SMBus Charger Net Properties
NET_TYPE
PHYSICAL
ELECTRICAL_CONSTRAINT_SET
SENSE_DIFFPAIR
SENSE_DIFFPAIR
2TO1_DIFFPAIR
2TO1_DIFFPAIR
2TO1_DIFFPAIR
SENSE_DIFFPAIR
2TO1_DIFFPAIR
SENSE_DIFFPAIR
2TO1_DIFFPAIR
2TO1_DIFFPAIR
2TO1_DIFFPAIR
SPACING
CHGR_CSI_P
CHGR_CSI_N
CHGR_CSI_R_P
CHGR_CSI_R_N
CHGR_CSO_P
CHGR_CSO_N
CHGR_CSO_R_P
CHGR_CSO_R_N
50
50
50
50
50
50
43 50
43 50
C
C
B
B
A
SYNC_MASTER=CONSTRAINTS
SYNC_DATE=09/25/2012
PAGE TITLE
SMC Constraints
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
117 OF 121
SHEET
73 OF 76
1
A
8
7
6
5
4
3
2
1
J11/J13 Specific Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
SENSE_1TO1_45S
*
=1TO1_DIFFPAIR
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=1TO1_DIFFPAIR
NET_TYPE
DIFFPAIR NECK GAP
=1TO1_DIFFPAIR
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
*
=1TO1_DIFFPAIR
0.200 MM
0.100 MM
=1TO1_DIFFPAIR
=1TO1_DIFFPAIR
*
=1TO1_DIFFPAIR
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=1TO1_DIFFPAIR
THERM
THERM_1TO1_45S
THERM
=1TO1_DIFFPAIR
THERM_1TO1_45S
THERM_1TO1_45S
SENSE_DIFFPAIR
SENSE_1TO1_P2MM
SENSE_DIFFPAIR
INLET_THMSNS_D1_P
INLET_THMSNS_D1_N
44
=1TO1_DIFFPAIR
44
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
SPKR_DIFFPAIR
*
SPACING_RULE_SET
LAYER
=1TO1_DIFFPAIR
0.300 MM
0.100 MM
=1TO1_DIFFPAIR
=1TO1_DIFFPAIR
=1TO1_DIFFPAIR
SENSE_DIFFPAIR
D
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
TABLE_SPACING_RULE_ITEM
SENSE
*
=2:1_SPACING
*
=2:1_SPACING
THERM
THERM_1TO1_45S
THERM
THERM_1TO1_45S
THERM
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
?
THERM
THERM
THERM_1TO1_45S
SENSE_DIFFPAIR
TABLE_SPACING_ASSIGNMENT_HEAD
WEIGHT
THERM_1TO1_45S
SENSE_DIFFPAIR
SENSE_DIFFPAIR
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
CPU_COMP
?
GND
*
GND_P2MM
CPU_VCCSENSE
GND
*
GND_P2MM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
SENSE_DIFFPAIR
THERM_1TO1_45S
THERM
SENSE_DIFFPAIR
THERM_1TO1_45S
THERM
SENSE_DIFFPAIR
THERM_1TO1_45S
THERM
SENSE_DIFFPAIR
THERM_1TO1_45S
THERM
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_P2MM
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_P2MM
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_P2MM
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_P2MM
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE
SENSE_1TO1_P2MM
SENSE
SENSE_1TO1_P2MM
SENSE
SENSE_1TO1_45S
SENSE
SENSE_1TO1_45S
SENSE
TABLE_SPACING_RULE_ITEM
AUDIO
*
=2:1_SPACING
?
TBTTHMSNS_D2_R_P
TBTTHMSNS_D2_R_N
TBTTHMSNS_D2_P
TBTTHMSNS_D2_N
TBT_MLBBOT_THMSNS_P
TBT_MLBBOT_THMSNS_N
MLBBOT_THMSNS_D3_P
MLBBOT_THMSNS_D3_N
44
D
44
44
44
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
GND
CLK_PCIE
*
GND_P2MM
GND
PCIE*
*
GND_P2MM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
TABLE_SPACING_ASSIGNMENT_ITEM
WEIGHT
TABLE_SPACING_RULE_ITEM
GND
*
=STANDARD
TBDTHMSNS_D2_P
TBDTHMSNS_D2_N
44
44
TABLE_SPACING_ASSIGNMENT_ITEM
?
TABLE_SPACING_ASSIGNMENT_ITEM
GND
SATA*
*
GND_P2MM
CPUTHMSNS_D2_P
CPUTHMSNS_D2_N
44
44
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
GND
USB*
*
GND_P2MM
WEIGHT
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
GND_P2MM
*
0.20 MM
GND
LVDS*
*
GND_P2MM
SB_POWER
CLK_PCIE
*
CPUVCCIOS0_CS_N
CPUVCCIOS0_CS_P
PWR_P2MM
10000
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
PWR_P2MM
*
0.20 MM
10000
TABLE_SPACING_ASSIGNMENT_ITEM
SB_POWER
SATA*
*
PWR_P2MM
TABLE_SPACING_ASSIGNMENT_ITEM
SB_POWER
SATA*
PWR_P2MM
*
C
SENSE_DIFFPAIR
SENSE_1TO1_P2MM
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_P2MM
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_P2MM
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_P2MM
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE
I348
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE
I349
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE
AUD_DIFF
1TO1_DIFFPAIR
AUDIO
AUD_DIFF
1TO1_DIFFPAIR
AUDIO
1TO1_DIFFPAIR
AUDIO
1TO1_DIFFPAIR
AUDIO
SPKR_OUT
SPKR_DIFFPAIR
AUDIO
SPKR_OUT
SPKR_DIFFPAIR
AUDIO
B
SB_POWER
SB_POWER
A
GND
CPUVR_ISNS1_P
CPUVR_ISNS1_N
CPUVR_ISNS2_P
CPUVR_ISNS2_N
CPUVR_ISNS1_P_R
CPUVR_ISNS1_N_R
CPUVR_ISUM_R_P
CPUVR_ISUM_R_N
ISNS_CPUDDR_P
ISNS_CPUDDR_N
ISNS_P3V3S5_N
ISNS_P3V3S5_P
ISNS_3V3_S0_P
ISNS_3V3_S0_N
ISNS_CAMERA_P
ISNS_CAMERA_N
ISNS_P3V3_S0_N
ISNS_P3V3_S0_P
ISNS_1V05_S0_P
ISNS_1V05_S0_N
42 52
42 52
42 52
42 52
42 43
42 43
42
42
C
42
42
42
42
41
41
41
41
42 55
42 55
ISNS_BMON_GAIN_P
ISNS_BMON_GAIN_N
ISNS_HS_COMPUTING_N
ISNS_HS_COMPUTING_P
ISNS_HS_OTHER_N
ISNS_HS_OTHER_P
ISNS_1V2_S3_N
ISNS_1V2_S3_P
ISNS_AIRPORT_N
ISNS_AIRPORT_P
ISNS_SSD_N
ISNS_SSD_P
41 43
41 43
41
41
41 53
41 53
B
41
41
41
41
ISNS_LCDBKLT_N
ISNS_LCDBKLT_P
ISNS_PANEL_N
ISNS_PANEL_P
ISNS_HS_GAIN_N
ISNS_HS_GAIN_P
SPKRAMP_INR_P
SPKRAMP_INR_N
MAX98300_R_P
MAX98300_R_N
SPKRAMP_ROUT_P
SPKRAMP_ROUT_N
PP3V3_S5
PP3V3_S0
41
41
43
43
43 44
43 44
47 61 65
47 61 65
47
47
47 64
47 64
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64
62 64 65
8 11 12 13 15 17 18 26 30 36 38
39 40 41 42 43 44 45 56 59 61
GND
SYNC_MASTER=J41_MLB
SYNC_DATE=12/07/2012
PAGE TITLE
Project Specific Constraints
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
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& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
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SD Card Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
NET_TYPE
DIFFPAIR NECK GAP
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
SD_45SE
*
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
I347
SDDATA
I346
SDCLK
SD_45SE
I348
SD_45SE
I349
SD_45SE
I350
SD_45SE
I351
SD_45SE
I352
SD_45SE
I353
SD_45SE
I354
SD_45SE
I355
CLK_25M_45S
I356
D
SDCONN_DATA & lt; 0..3 & gt;
SDCONN_CLK
SD_45SE
CLK_25M_45S
SPI
SPI
SPI
SPI
SDCONN_WP
SDCONN_CMD
SDCONN_DETECT_L
SD_SPI_CLK
SD_SPI_CS_L
SD_SPI_MOSI
SD_SPI_MISO
SDSCLK_CLK_25M_X1
SDCLK_CLK25M_X2_R
33 34
33 34
33 34
33 34
D
33 34
34
34
34
34
34 69
C
C
B
B
A
SYNC_MASTER=CONSTRAINTS
SYNC_DATE=09/25/2012
PAGE TITLE
Project Specific Constraints
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
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& lt; E4LABEL & gt;
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Change List:
& lt; RDAR://COMPONENT/508934 & gt; J43 HW EE SCHEMATIC | PROTO 0
& lt; RDAR://COMPONENT/508937 & gt; J43 HW EE SCHEMATIC | PROTO 1
D
& lt; RDAR://COMPONENT/508941 & gt; J43 HW EE SCHEMATIC | EVT
D
& lt; RDAR://COMPONENT/508945 & gt; J43 HW EE SCHEMATIC | DVT
Kismet:
afp://kismet.apple.com/Kismet-Projects/J41-J43
Useful Wiki Links:
Schematic Conventions - https://hmts.ecs.apple.com/wiki/index.php/User:Wferry/SchConventions
Schematic Design Wiki - https://hmts.ecs.apple.com/wiki/index.php/Schematic_Design
MobileMac HW Radar:
C
& lt; rdar://component/497591 & gt;
& lt; rdar://component/497587 & gt;
& lt; rdar://component/497585 & gt;
& lt; rdar://component/497588 & gt;
& lt; rdar://component/497590 & gt;
& lt; rdar://component/497589 & gt;
MobileMac
MobileMac
MobileMac
MobileMac
MobileMac
MobileMac
HW
HW
HW
HW
HW
HW
|
|
|
|
|
|
Task
Schematic
New Bugs
Layout
Investigation
Architecture
C
Other Info:
Page Allocations - & lt; rdar://problem/11791318 & gt; 2012 Schematic Page Allocations
B
B
A
SYNC_MASTER=J41_MLB
SYNC_DATE=07/03/2012
PAGE TITLE
Reference
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
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& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
121 OF 121
SHEET
76 OF 76
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